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soc: interconnect: add logic to set a offset to bus slaves #2166

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add logic to set a offset to bus slaves.

Signed-off-by: Fin Maaß f.maass@vogl-electronic.com

add logic to set a offset to bus slaves.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
use offset logic for litespi uses (add_spi_flash. add_spi_ram).

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
maass-hamburg added a commit to VOGL-electronic/gw__litespi that referenced this pull request Jan 22, 2025
remove offset logic, this is now handled centrally here:
enjoy-digital/litex#2166

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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@enjoy-digital please take a look. It might be very useful for other bus slaves, that also expect a start at 0

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Thanks @maass-hamburg, would you mind describing the context/use-case to think about it and review it with this in mind?

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@enjoy-digital Most modules with a axi or wishbone bus don't have a offset logic(they don't know the offset in the SoCRegion), which means that they will send the axi or whishbone address directly to the device. If you want to access the address 0x0 an a mmaped flash(the first byte on that device), and the SoCRegion has the origin of that device at 0x400, you would start a read via the axi or wishbone bus at ```0x4000``, but that would lead to you reading at 0x4000 on that device, but you wanted 0x0. that why we have to substract the origin/start from the address.

The reason, why if wasn't noticed before, is that

  • a lot of devices have a rollover ( you want 0x405, but the device is only 0x100 big, it will return the value at 0x5)
  • some modules ignore the last bits, because they will only use the first 16 bit, so if our offset is 0x20000, than the 0x2 is ignored.

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