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Fix NaxRISCV Bare Metal Demo and small fix for demo.py make routine ci #3500: Pull request #2170 opened by BMorgan1296
January 29, 2025 04:15 26m 32s BMorgan1296:master
BMorgan1296:master
January 29, 2025 04:15 26m 32s
Merge pull request #2026 from VOGL-electronic/core_litei2c ci #3499: Commit c213c42 pushed by enjoy-digital
January 28, 2025 13:52 25m 54s master
master
January 28, 2025 13:52 25m 54s
Merge pull request #2168 from VOGL-electronic/build_tristate_io ci #3498: Commit 03823f4 pushed by enjoy-digital
January 27, 2025 07:54 28m 46s master
master
January 27, 2025 07:54 28m 46s
Merge pull request #2165 from VOGL-electronic/bring_back_lower_slice ci #3497: Commit d07c068 pushed by enjoy-digital
January 27, 2025 07:53 28m 7s master
master
January 27, 2025 07:53 28m 7s
build: common: TristateImpl: support longer oe ci #3496: Pull request #2168 synchronize by maass-hamburg
January 23, 2025 12:39 25m 43s VOGL-electronic:build_tristate_io
VOGL-electronic:build_tristate_io
January 23, 2025 12:39 25m 43s
build: common: TristateImpl: support longer oe ci #3495: Pull request #2168 opened by maass-hamburg
January 23, 2025 12:36 24m 55s VOGL-electronic:build_tristate_io
VOGL-electronic:build_tristate_io
January 23, 2025 12:36 24m 55s
litex: gen: fhdl: verilog.py: resolve slice in lower_complex_slices() ci #3494: Pull request #2165 synchronize by maass-hamburg
January 23, 2025 12:22 29m 40s VOGL-electronic:bring_back_lower_slice
VOGL-electronic:bring_back_lower_slice
January 23, 2025 12:22 29m 40s
litex: gen: fhdl: verilog.py: resolve slice in lower_complex_slices() ci #3493: Pull request #2165 synchronize by maass-hamburg
January 22, 2025 14:45 27m 8s VOGL-electronic:bring_back_lower_slice
VOGL-electronic:bring_back_lower_slice
January 22, 2025 14:45 27m 8s
Merge pull request #2167 from VOGL-electronic/fix_sinals_for_multibit_io ci #3492: Commit ad5d7d3 pushed by enjoy-digital
January 22, 2025 14:04 26m 20s master
master
January 22, 2025 14:04 26m 20s
build: common: make sure Signal lenght is right ci #3491: Pull request #2167 opened by maass-hamburg
January 22, 2025 10:14 27m 13s VOGL-electronic:fix_sinals_for_multibit_io
VOGL-electronic:fix_sinals_for_multibit_io
January 22, 2025 10:14 27m 13s
soc: interconnect: add logic to set a offset to bus slaves ci #3490: Pull request #2166 synchronize by maass-hamburg
January 22, 2025 08:45 25m 5s VOGL-electronic:soc_add_offset_logic
VOGL-electronic:soc_add_offset_logic
January 22, 2025 08:45 25m 5s
soc: interconnect: add logic to set a offset to bus slaves ci #3489: Pull request #2166 opened by maass-hamburg
January 21, 2025 21:58 26m 47s VOGL-electronic:soc_add_offset_logic
VOGL-electronic:soc_add_offset_logic
January 21, 2025 21:58 26m 47s
litex: gen: fhdl: verilog.py: resolve slice in lower_complex_slices() ci #3488: Pull request #2165 synchronize by maass-hamburg
January 20, 2025 10:59 28m 51s VOGL-electronic:bring_back_lower_slice
VOGL-electronic:bring_back_lower_slice
January 20, 2025 10:59 28m 51s
litex: gen: fhdl: verilog.py: resolve slice in lower_complex_slices() ci #3487: Pull request #2165 opened by maass-hamburg
January 20, 2025 10:06 27m 3s VOGL-electronic:bring_back_lower_slice
VOGL-electronic:bring_back_lower_slice
January 20, 2025 10:06 27m 3s
gen/fhdl: Revert PR #2161 since introducing regressions. ci #3486: Commit 666c9b4 pushed by enjoy-digital
January 20, 2025 09:54 27m 22s master
master
January 20, 2025 09:54 27m 22s
soc.py: ethernet: use phy_cd name from phy ci #3485: Pull request #2163 opened by maass-hamburg
January 16, 2025 14:24 25m 16s VOGL-electronic:soc_ethernet_phy
VOGL-electronic:soc_ethernet_phy
January 16, 2025 14:24 25m 16s
Merge pull request #2162 from trabucayre/altera_max10_fullmemorywe ci #3484: Commit e9e7cd9 pushed by enjoy-digital
January 16, 2025 13:22 24m 57s master
master
January 16, 2025 13:22 24m 57s
build/altera/quartus.py: don't call FullMemoryWE when target is based on max10 FPGA ci #3483: Pull request #2162 opened by trabucayre
January 16, 2025 13:13 25m 59s trabucayre:altera_max10_fullmemorywe
trabucayre:altera_max10_fullmemorywe
January 16, 2025 13:13 25m 59s
CHANGES.md: Update. ci #3482: Commit 08a6da2 pushed by enjoy-digital
January 15, 2025 08:16 26m 17s master
master
January 15, 2025 08:16 26m 17s
Merge pull request #2161 from VOGL-electronic/expression_slice ci #3481: Commit fefe317 pushed by enjoy-digital
January 15, 2025 07:41 27m 20s master
master
January 15, 2025 07:41 27m 20s
Merge pull request #2160 from FlyGoat/ibex ci #3480: Commit a9265ef pushed by enjoy-digital
January 15, 2025 07:28 24m 42s master
master
January 15, 2025 07:28 24m 42s
gen: fhdl: expression: resolve slice completly ci #3479: Pull request #2161 opened by maass-hamburg
January 14, 2025 18:41 25m 38s VOGL-electronic:expression_slice
VOGL-electronic:expression_slice
January 14, 2025 18:41 25m 38s
cores/cpu/ibex: Align with latest RTL ci #3478: Pull request #2160 opened by FlyGoat
January 14, 2025 18:07 25m 6s FlyGoat:ibex
FlyGoat:ibex
January 14, 2025 18:07 25m 6s
build: efinix: allow clk inverting and different in clk on reg tristates ci #3477: Pull request #2087 synchronize by maass-hamburg
January 14, 2025 17:16 28m 6s VOGL-electronic:io_kwargs
VOGL-electronic:io_kwargs
January 14, 2025 17:16 28m 6s
Merge pull request #2159 from FlyGoat/openc906-fixes ci #3476: Commit 5619d48 pushed by enjoy-digital
January 14, 2025 17:10 25m 48s master
master
January 14, 2025 17:10 25m 48s