Spiflash fixes for issues exposed by sys_clk = 200MHz and L2 cache #1881
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added 9 commits
February 1, 2024 14:37
Helps explain failures
require both phy and flash support to enable QUAD/QPI capability. Many flash devices support 4x read but may be on a 1x phy
Ensure default_divisor is set to desired default - 1 as required by LiteSPIClkGen Calculate actual PHY_CLK based on default_divisor
This is safer than defaulting to sys_clock / 2 if sys_clock > 100MHz clk_freq tuning will result in a faster clock if supported by hardware.
Correct CRC was always calculated, regardless of divisor, as the test flash block was in the L2 cache. This resulted in the minimum divisor being used and incorrect flash reads with 200MHz sys_clock.
Same CRC was always reported if the memory region was in the cache... Noticed when manually testing spiflash divisor.
many openfpgaloader args have a name with '-' as per normal convention. This kwarg now works: file_type="raw"
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Thanks @AndrewD! |
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This is a set of several changes to fix various issues identified when debugging why the mmap
spiflash data read with the bios did not match the data written with openfpgaloader.
Example boot with the fixes on a Efinix Ti60 based design: