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soc/cores/cpu/vexriscv_smp/core: allowing configure CSR/CLINT base address by overriding default value or using args #1876

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trabucayre
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As mentioned in issue #1875 with too many CSR this region overlap clint region.
This commit provides two way to move csr and clint region:

by overriding default value from the target with:

from litex.soc.cores.cpu.vexriscv_smp import VexRiscvSMP
VexRiscvSMP.clint_base = 0xf0100000

or by using arguments with

./Target.py [options] --clint-base=0xf0100000

@trabucayre trabucayre force-pushed the vexriscv_configurable_clint_csr_addr branch from 0800210 to 7db7de1 Compare January 22, 2024 17:35
…se address by overriding default value or using args
@trabucayre trabucayre force-pushed the vexriscv_configurable_clint_csr_addr branch from 7db7de1 to bb62f7a Compare January 22, 2024 17:36
@enjoy-digital enjoy-digital merged commit 1be3f02 into enjoy-digital:master Jan 23, 2024
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2 participants