dts: stm32: Streamline device tree binding descriptions

Ensure consistent (and concise) short descriptions of all the st,*.yaml bindings Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
zephyrproject-rtos · Mar 4, 2025 · e7cc834 · e7cc834
1 parent 14f382b
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diff --git a/dts/bindings/adc/st,stm32-adc.yaml b/dts/bindings/adc/st,stm32-adc.yaml
@@ -2,7 +2,7 @@
 # Copyright (c) 2018, Song Qiang <songqiang1304521@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
-description: ST STM32 family ADC
+description: STM32 ADC
 
 compatible: "st,stm32-adc"
 

diff --git a/dts/bindings/adc/st,stm32f1-adc.yaml b/dts/bindings/adc/st,stm32f1-adc.yaml
@@ -3,7 +3,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-        ST STM32F1 family ADC
+        STM32F1 ADC
+
         This compatible stands for all ADC blocks similar to the one on STM32F1,
         like STM32F37x.
         Remove the st,adc-clock-source and st,adc-prescaler property.

diff --git a/dts/bindings/adc/st,stm32f4-adc.yaml b/dts/bindings/adc/st,stm32f4-adc.yaml
@@ -3,7 +3,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-        ST STM32F4 family ADC
+        STM32F4 ADC
+
         This compatible stands for all ADC blocks similar to the one on STM32F4,
         like F2, F7 or L1.
 

diff --git a/dts/bindings/adc/st,stm32n6-adc.yaml b/dts/bindings/adc/st,stm32n6-adc.yaml
@@ -3,7 +3,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-        ST STM32N6 ADC
+        STM32N6 ADC
+
         This compatible stands for STM32N6 ADC.
 
 compatible: "st,stm32n6-adc"

diff --git a/dts/bindings/adc/st,stm32wb0-adc.yaml b/dts/bindings/adc/st,stm32wb0-adc.yaml
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
-description: STM32WB0 series Analog-to-Digital Converter
+description: STM32WB0 Analog-to-Digital Converter
 
 compatible: "st,stm32wb0-adc"
 

diff --git a/dts/bindings/can/st,stm32-fdcan.yaml b/dts/bindings/can/st,stm32-fdcan.yaml
@@ -1,4 +1,4 @@
-description: ST STM32 FDCAN CAN FD controller
+description: STM32 FDCAN CAN FD controller
 
 compatible: "st,stm32-fdcan"
 

diff --git a/dts/bindings/can/st,stm32h7-fdcan.yaml b/dts/bindings/can/st,stm32h7-fdcan.yaml
@@ -1,4 +1,4 @@
-description: ST STM32H7 series FDCAN CAN FD controller
+description: STM32H7 series FDCAN CAN FD controller
 
 compatible: "st,stm32h7-fdcan"
 

diff --git a/dts/bindings/clock/st,stm32-clock-mux.yaml b/dts/bindings/clock/st,stm32-clock-mux.yaml
@@ -3,6 +3,7 @@
 
 description: |
         STM32 Clock multiplexer
+
         Describes a clock multiplexer, such as per_ck on STM32H7 or
         CLK48 on STM32WB.
         The only property of this node is to select a clock input.

diff --git a/dts/bindings/clock/st,stm32-rcc.yaml b/dts/bindings/clock/st,stm32-rcc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32 Reset and Clock controller node.
+  STM32 RCC (Reset and Clock controller).
+
   This node is in charge of system clock ('SYSCLK') source selection and controlling
   clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
 

diff --git a/dts/bindings/clock/st,stm32c0-hsi-clock.yaml b/dts/bindings/clock/st,stm32c0-hsi-clock.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32 HSI Clock node description for STM32C0 devices
+  STM32C0 HSI Clock.
+
   On STM32C0, HSI is a 48MHz fixed clock.
 
   It also produces a HSISYS secondary clk which can be used as system clock

diff --git a/dts/bindings/clock/st,stm32f0-pll-clock.yaml b/dts/bindings/clock/st,stm32f0-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  Main PLL node binding for STM32F0 and STM32F3 devices.
+  STM32F0/F3 Main PLL.
 
   Takes one of clk_hse or clk_hsi as input clock.
 

diff --git a/dts/bindings/clock/st,stm32f0-rcc.yaml b/dts/bindings/clock/st,stm32f0-rcc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32F0 and G0 Reset and Clock controller node.
+  STM32F0/G0 RCC (Reset and Clock controller).
+
   For more description confere st,stm32-rcc.yaml
 
 compatible: "st,stm32f0-rcc"

diff --git a/dts/bindings/clock/st,stm32f1-clock-mco.yaml b/dts/bindings/clock/st,stm32f1-clock-mco.yaml
@@ -7,7 +7,7 @@
 compatible: "st,stm32f1-clock-mco"
 
 description: |
-        STM32 F1 series Microcontroller Clock Output (MCO)
+        STM32F1 Microcontroller Clock Output (MCO)
 
         The STM32F1 MCO is similar to other series but has no configurable
         prescaler before the output. However, note that certain inputs of

diff --git a/dts/bindings/clock/st,stm32f1-pll-clock.yaml b/dts/bindings/clock/st,stm32f1-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  Main PLL node binding for low-, medium-, high- and XL-density STM32F1 devices.
+  STM32F1 Main PLL for low-, medium-, high- and XL-density devices.
 
   Takes one of 'clk_hse', 'clk_hse / 2' (when 'xtpre' is set) or 'clk_hsi / 2'
   as input clock.

diff --git a/dts/bindings/clock/st,stm32f1-rcc.yaml b/dts/bindings/clock/st,stm32f1-rcc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32F1 and STM32F37x Reset and Clock controller node.
+  STM32F1/F3/7x RCC (Reset and Clock controller).
+
   Adds the ADC prescaler to the standard generic STM32 RCC.
   For more description confere st,stm32-rcc.yaml
 

diff --git a/dts/bindings/clock/st,stm32f100-pll-clock.yaml b/dts/bindings/clock/st,stm32f100-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  Main PLL node binding for STM32F100 devices
+  STM32F100 Main PLL.
 
   Takes one of clk_hse or clk_hsi as input clock.
   When clk_hsi is used a fixed prescaler is applied. When input clock is hse or

diff --git a/dts/bindings/clock/st,stm32f105-pll-clock.yaml b/dts/bindings/clock/st,stm32f105-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  Main PLL node binding for Connectivity line devices (STM32F105/STM32F107)
+  STM32F105/F107 Main PLL.
 
   Takes one of clk_hse, pll2 or clk_hsi as input clock.
   When clk_hsi is used a fixed prescaler is applied. When input clock is hse or

diff --git a/dts/bindings/clock/st,stm32f105-pll2-clock.yaml b/dts/bindings/clock/st,stm32f105-pll2-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  PLL2 node binding for Connectivity line devices (STM32F105/STM32F107)
+  STM32F105/F107 PLL2.
 
   Takes clk_hse as input clock, using prediv as prescaler.
 

diff --git a/dts/bindings/clock/st,stm32f2-pll-clock.yaml b/dts/bindings/clock/st,stm32f2-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32F2 Main PLL node binding:
+  STM32F2 Main PLL.
 
   Takes one of clk_hse or clk_hsi as input clock.
 

diff --git a/dts/bindings/clock/st,stm32f3-rcc.yaml b/dts/bindings/clock/st,stm32f3-rcc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32F3 Reset and Clock controller node.
+  STM32F3 RCC (Reset and Clock controller).
+
   Adds the STM32F3 ADC prescaler to the standard generic STM32 RCC.
   For more description confere st,stm32-rcc.yaml
 

diff --git a/dts/bindings/clock/st,stm32f4-pll-clock.yaml b/dts/bindings/clock/st,stm32f4-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32F4 Main PLL node binding:
+  STM32F4 Main PLL.
 
   Takes one of clk_hse or clk_hsi as input clock, with an
   input frequency from 1 to 2 MHz. PLLM factor is used to set the input clock

diff --git a/dts/bindings/clock/st,stm32f4-plli2s-clock.yaml b/dts/bindings/clock/st,stm32f4-plli2s-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32F4 PLL I2S node binding:
+  STM32F4 PLL I2S.
 
   Takes same input as Main PLL. PLLM factor and PLL source are common with Main PLL
 

diff --git a/dts/bindings/clock/st,stm32f411-plli2s-clock.yaml b/dts/bindings/clock/st,stm32f411-plli2s-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32F411 PLL I2S node binding:
+  STM32F411 PLL I2S.
 
   Fully configurable I2S dedicated PLL.
 

diff --git a/dts/bindings/clock/st,stm32f7-pll-clock.yaml b/dts/bindings/clock/st,stm32f7-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32F7 Main PLL node binding:
+  STM32F7 Main PLL.
 
   Takes one of clk_hse or clk_hsi as input clock.
 

diff --git a/dts/bindings/clock/st,stm32g0-hsi-clock.yaml b/dts/bindings/clock/st,stm32g0-hsi-clock.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32 HSI Clock node description for STM32G0 devices
+  STM32G0 HSI Clock.
+
   On STM32G0, HSI is a 16MHz fixed clock.
 
   It also produces a HSISYS secondary clk which can be used as system clock

diff --git a/dts/bindings/clock/st,stm32g0-pll-clock.yaml b/dts/bindings/clock/st,stm32g0-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  PLL node binding for STM32G0 devices
+  STM32G0 main PLL.
 
   It can take one of clk_hse or clk_hsi as input clock, with
   an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input

diff --git a/dts/bindings/clock/st,stm32g4-pll-clock.yaml b/dts/bindings/clock/st,stm32g4-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  PLL node binding for STM32G4 devices
+  STM32G4 main PLL.
 
   It can take one of clk_hse or clk_hsi as input clock, with
   an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input

diff --git a/dts/bindings/clock/st,stm32h7-pll-clock.yaml b/dts/bindings/clock/st,stm32h7-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  PLL node binding for STM32H7 devices
+  STM32H7 main PLL.
 
   It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
   Only PLL1 and PLL3 are supported for now.

diff --git a/dts/bindings/clock/st,stm32h7-rcc.yaml b/dts/bindings/clock/st,stm32h7-rcc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32 Reset and Clock controller node for STM32H7 devices
+  STM32H7 RCC (Reset and Clock controller).
+
   This node is in charge of system clock ('SYSCLK') source selection and
   System Clock Generation.
 

diff --git a/dts/bindings/clock/st,stm32h7rs-pll-clock.yaml b/dts/bindings/clock/st,stm32h7rs-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  PLL node binding for STM32H7RS devices
+  STM32H7RS main PLL.
 
   It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
 

diff --git a/dts/bindings/clock/st,stm32h7rs-rcc.yaml b/dts/bindings/clock/st,stm32h7rs-rcc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32 Reset and Clock controller node for STM32H7RS devices
+  STM32H7RS RCC (Reset and Clock controller).
+
   This node is in charge of system clock ('SYSCLK') source selection and
   System Clock Generation.
 

diff --git a/dts/bindings/clock/st,stm32l0-msi-clock.yaml b/dts/bindings/clock/st,stm32l0-msi-clock.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021, Linaro ltd
 # SPDX-License-Identifier: Apache-2.0
 
-description: STM32L0 and STM32L1 Multi Speed Internal Clock
+description: STM32L0/L1 Multi Speed Internal Clock
 
 compatible: "st,stm32l0-msi-clock"
 

diff --git a/dts/bindings/clock/st,stm32l0-pll-clock.yaml b/dts/bindings/clock/st,stm32l0-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32L0 and STM32L1 Main PLL node binding:
+  STM32L0/L1 Main PLL.
 
   Takes one of clk_hse, clk_hsi or clk_msi as input clock, with an
   input frequency from 2 to 24 MHz.

diff --git a/dts/bindings/clock/st,stm32l4-pll-clock.yaml b/dts/bindings/clock/st,stm32l4-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  PLL node binding for STM32L4 and STM32L5 devices
+  STM32L4/L5 main PLL.
 
   It can be used to describe 3 different PLLs: PLL, PLLSAI1 and PLLSAI2.
   Only main PLL is supported for now.

diff --git a/dts/bindings/clock/st,stm32mp1-rcc.yaml b/dts/bindings/clock/st,stm32mp1-rcc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32MP1 Reset and Clock controller node.
+  STM32MP1 RCC (Reset and Clock controller).
+
   On STM32MP1 platforms, clock control configuration is performed on A9 side.
   As a consequence, the only property to be set in devicetree node is the
   clock-frequency (mlhclk_ck).

diff --git a/dts/bindings/clock/st,stm32n6-cpu-clock-mux.yaml b/dts/bindings/clock/st,stm32n6-cpu-clock-mux.yaml
@@ -2,9 +2,11 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32N6 CPU Clock
+  STM32N6 CPU Clock.
+
   Describes the STM32N6 CPU clock multiplexer. On STM32N6, this is the CPU
   clock that feeds the SysTick.
+
   For instance:
   &cpusw {
     clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>;

diff --git a/dts/bindings/clock/st,stm32n6-ic-clock-mux.yaml b/dts/bindings/clock/st,stm32n6-ic-clock-mux.yaml
@@ -2,8 +2,10 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32N6 Divider IC multiplexer
-  This node select a clock input and a divider.
+  STM32N6 Divider IC multiplexer.
+
+  This node selects a clock input and a divider.
+
   For instance:
     &ic6 {
       pll-src = <2>;

diff --git a/dts/bindings/clock/st,stm32n6-pll-clock.yaml b/dts/bindings/clock/st,stm32n6-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  PLL node binding for STM32N6 devices
+  STM32N6 main PLL.
 
   It can be used to describe 4 different PLLs: PLL1, PLL2, PLL3 and PLL4.
 

diff --git a/dts/bindings/clock/st,stm32n6-rcc.yaml b/dts/bindings/clock/st,stm32n6-rcc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32 Reset and Clock controller node for STM32N6 devices
+  STM32N6 RCC (Reset and Clock controller).
+
   This node is in charge of system clock ('SYSCLK') source selection and
   System Clock Generation.
 

diff --git a/dts/bindings/clock/st,stm32u0-pll-clock.yaml b/dts/bindings/clock/st,stm32u0-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32U0 Main PLL node binding:
+  STM32U0 Main PLL.
 
   Takes one of clk_hse, clk_hsi or clk_msi as input clock, with
   an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input

diff --git a/dts/bindings/clock/st,stm32u5-pll-clock.yaml b/dts/bindings/clock/st,stm32u5-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  PLL node binding for STM32U5 devices
+  STM32U5 PLL.
 
   It can be used to describe 3 different PLLs: PLL1, PLL2 and PLL3.
 

diff --git a/dts/bindings/clock/st,stm32u5-rcc.yaml b/dts/bindings/clock/st,stm32u5-rcc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32U5 Reset and Clock controller node.
+  STM32U5 RCC (Reset and Clock controller).
+
   For more description confere st,stm32-rcc.yaml
 
 compatible: "st,stm32u5-rcc"

diff --git a/dts/bindings/clock/st,stm32wb-rcc.yaml b/dts/bindings/clock/st,stm32wb-rcc.yaml
@@ -3,6 +3,7 @@
 
 description: |
   STM32WB Reset and Clock controller node.
+
   For more description confere st,stm32-rcc.yaml
 
 compatible: "st,stm32wb-rcc"