Added PLL schematic

BGR/README.md

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+# BGR / Current source circuits
+
+- xschem: circuit design and simulation results
+- klayout: layout design

BGR/klayout/README.md

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+# BGR and Current Source: layout design
+
+## BGR
+
+- GDSII file: bgr_diode.gds
+- Netlist for LVS: bgr_diode.cdl
+- pin list: vdd (3.3 V supply), vss (ground), vout (voltage output)
+- size: 108 um x 200 um
+
+![image](https://github.com/atuchiya/DC23-LTC2/assets/49263791/6c8e2316-a329-44d8-8517-f05f2b79a016)
+
+
+## Current source
+
+- GDSII file: cs_vthref.gds
+- Netlist for LVS: cs_vthref.cdl
+- pin list: vdd (3.3 V supply), vss (ground), vb (bias voltage for pMOS current mirror)
+- size: 39 um x 49 um
+
+![image](https://github.com/atuchiya/DC23-LTC2/assets/49263791/741bb0b8-ffda-4fc8-b15a-b7af3cdb1eaa)
+

BGR/klayout/bgr_diode.cdl

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+** sch_path: /home/tsuchiya/chipathon/chipathon2023/BGR/xschem/bgr_diode.sch
+.subckt bgr_diode vss vdd vout
+*.PININFO vdd:B vss:B vout:O
+M5 net2 net1 net4 net4 nfet_03v3_dn L=1.12u W=11.2u nf=1 m=30
+M6 net2 net2 vdd vdd pfet_03v3 L=1.12u W=11.2u nf=1 m=30
+M7 net1 net1 net3 net3 nfet_03v3_dn L=1.12u W=11.2u nf=1 m=30
+M8 net1 net2 vdd vdd pfet_03v3 L=1.12u W=11.2u nf=1 m=30
+Q1 net5 net5 vss vss npn_10p00x10p00 m=1
+Q20 net6 net6 vss vss npn_10p00x10p00 m=1
+Q21 net6 net6 vss vss npn_10p00x10p00 m=1
+Q22 net6 net6 vss vss npn_10p00x10p00 m=1
+Q23 net6 net6 vss vss npn_10p00x10p00 m=1
+Q24 net6 net6 vss vss npn_10p00x10p00 m=1
+Q25 net6 net6 vss vss npn_10p00x10p00 m=1
+Q26 net6 net6 vss vss npn_10p00x10p00 m=1
+Q27 net6 net6 vss vss npn_10p00x10p00 m=1
+Q28 net6 net6 vss vss npn_10p00x10p00 m=1
+Q29 net6 net6 vss vss npn_10p00x10p00 m=1
+Q2a net6 net6 vss vss npn_10p00x10p00 m=1
+Q2b net6 net6 vss vss npn_10p00x10p00 m=1
+Q2c net6 net6 vss vss npn_10p00x10p00 m=1
+Q2d net6 net6 vss vss npn_10p00x10p00 m=1
+Q2e net6 net6 vss vss npn_10p00x10p00 m=1
+Q2f net6 net6 vss vss npn_10p00x10p00 m=1
+M1 vout net2 vdd vdd pfet_03v3 L=1.12u W=11.2u nf=1 m=30
+Q3 net7 net7 vss vss npn_10p00x10p00 m=1
+R1 net5 net3 vss ppolyf_u W=1.6u L=0.8u m=1
+R2 net6 net4 vss ppolyf_u W=1.6u L=0.8u m=1
+R3 net7 vout vss ppolyf_u W=1.6u L=5.4u m=1
+R4 net5 net3 vss ppolyf_u W=1.6u L=0.8u m=1
+R5 net5 net3 vss ppolyf_u W=1.6u L=0.8u m=1
+R6 net5 net3 vss ppolyf_u W=1.6u L=0.8u m=1
+R7 net5 net3 vss ppolyf_u W=1.6u L=0.8u m=1
+R8 net5 net3 vss ppolyf_u W=1.6u L=0.8u m=1
+R9 net5 net3 vss ppolyf_u W=1.6u L=0.8u m=1
+R10 net5 net3 vss ppolyf_u W=1.6u L=0.8u m=1
+R11 net5 net3 vss ppolyf_u W=1.6u L=0.8u m=1
+R12 net5 net3 vss ppolyf_u W=1.6u L=0.8u m=1
+.ends
+.end

BGR/klayout/cs_vthref.cdl

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+** sch_path: /home/tsuchiya/chipathon/chipathon2023/BGR/xschem/cs_vthref.sch
+.subckt cs_vthref vss vdd vb
+*.PININFO vdd:B vss:B vb:O
+M1 net1 net3 vss vss nfet_03v3_dn L=0.56u W=11.2u nf=1 m=1
+M2 vb net1 net3 net3 nfet_03v3_dn L=0.56u W=11.2u nf=1 m=1
+M3 net1 vb vdd vdd pfet_03v3 L=0.56u W=5.6u nf=1 m=8
+M4 vb vb vdd vdd pfet_03v3 L=0.56u W=5.6u nf=1 m=8
+R2 net2 net4 vss ppolyf_u W=0.8e-6 L=22e-6 m=1
+R1 net4 net3 vss ppolyf_u W=0.8e-6 L=22e-6 m=1
+R3 net5 net2 vss ppolyf_u W=0.8e-6 L=22e-6 m=1
+R4 vss net5 vss ppolyf_u W=0.8e-6 L=22e-6 m=1
+.ends
+.end

BGR/xschem/README.md

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+# BGR and Current Source : schematic design
+
+## BGR : diode + current mirror
+
+- core schematic file: bgr_diode.sch
+- symbol file: bgr_diode.sym
+- test bench file: tbdc_bgr_diode.sch
+- pin list: vdd (3.3 V supply), vss (ground), vout (voltage output)
+- output voltage (target) : 1.2 V
+
+![image](https://github.com/atuchiya/chipathon2023/assets/49263791/84613c58-23aa-4807-87c5-d8d372964450)
+
+Against Vdd variation (3.0 V - 3.3 V), output voltage fluctuation is 43 mV (3.6 %)
+
+![image](https://github.com/atuchiya/chipathon2023/assets/49263791/3cb59360-70e5-423d-8992-43fbc083fabc)
+
+Against temperature variation (-50 deg. - 125 deg.), output voltage fluctuation is 1.2 mV (0.1%)
+
+![image](https://github.com/atuchiya/chipathon2023/assets/49263791/d19f5c41-78d3-44e0-9319-8f65b84ad1bd)
+
+## Current source : Vth referenced current source + current mirror
+
+- core schematic file: cs_vthref.sch
+- symbol file: cs_vthref.sym
+- test bench file: tbdc_cs_vthref.sch
+- pin list: vdd (3.3 V supply), vss (ground), vb (bias voltage for pMOS current mirror)
+- current: 20 uA
+
+![image](https://github.com/atuchiya/chipathon2023/assets/49263791/3d4f6082-c33a-4986-9ab0-b2a28a172254)
+
+Against Vdd variation (3.0 V - 3.3 V), current fluctuation is 0.38 uA (1.9%)
+
+![image](https://github.com/atuchiya/chipathon2023/assets/49263791/9ba7c4bc-c648-453e-81b2-08a2b0e945e7)
+
+Against temperature variation (-50 deg. - 125 deg.), current fluctuation is 3.2 uA (16%).
+Against variation from 0 deg. to 40 deg., fluctuation is 0.69 uA (3.5%)
+
+![image](https://github.com/atuchiya/chipathon2023/assets/49263791/e4a7ebc7-c91a-4f9a-a9f6-7b5d7dd14e8f)
+
+