- lab1 - Some programs written in ToyRISC (used as benchmarks in the next few labs)
- lab2 - An assembler for the ToyRISC ISA
- lab3 - A single cycle processor simulator for ToyRISC
- lab4 - Updating to a 5 stage pipelined core model
- lab5 - Upgrading lab4 to a discrete event simulator
- lab6 - Added caches to the simulated memory system
This was part of the course CS2160 - Computer Organisation Lab offered by Indian Institute of Technology, Palakkad.