Merge pull request #8 from ziteh/develop

Rev 2.0

.gitignore

@@ -35,4 +35,7 @@ fp-info-cache
 *.drl
 
 # Backup
-*-backups/
+*-backups/
+
+# Exported JLCPCB tools plugin
+jlcpcb/

ErgoSNM_Keyboard/rev2/left/left.kicad_dru

@@ -11,13 +11,13 @@
 
 ### Trace Width and Spacing ###
 
-(rule "Track to Track Clearance"
-    (constraint clearance (min 0.127mm))
-    (condition "A.Type =='Track' && B.Type =='Track'"))
+# (rule "Track to Track Clearance"
+#     (constraint clearance (min 0.127mm))
+#     (condition "A.Type =='Track' && B.Type =='Track'"))
 
-(rule "Min Track width"
-    (constraint track_width (min 0.127mm))
-    (condition "A.Type =='Track'"))
+# (rule "Min Track width"
+#     (constraint track_width (min 0.15mm))
+#     (condition "A.Type =='Track'"))
 
 
 ### Min Clearance ###

ErgoSNM_Keyboard/rev2/left/left.kicad_prl

@@ -1,15 +1,15 @@
 {
   "board": {
-    "active_layer": 33,
+    "active_layer": 36,
     "active_layer_preset": "",
     "auto_track_width": true,
     "hidden_nets": [],
     "high_contrast_mode": 0,
     "net_color_mode": 1,
     "opacity": {
-      "pads": 1.0,
+      "pads": 0.8299999833106995,
       "tracks": 1.0,
-      "vias": 1.0,
+      "vias": 0.7699999809265137,
       "zones": 0.6
     },
     "ratsnest_display_mode": 0,
@@ -18,7 +18,7 @@
       "footprints": true,
       "graphics": true,
       "keepouts": true,
-      "lockedItems": true,
+      "lockedItems": false,
       "otherItems": true,
       "pads": true,
       "text": true,
@@ -62,7 +62,7 @@
       35,
       36
     ],
-    "visible_layers": "ffffeff_ffffffff",
+    "visible_layers": "ffdffff_ffffffff",
     "zone_display_mode": 1
   },
   "meta": {

ErgoSNM_Keyboard/rev2/left/left.kicad_pro

@@ -60,7 +60,9 @@
           "width": 0.92
         }
       ],
-      "drc_exclusions": [],
+      "drc_exclusions": [
+        "courtyards_overlap|163960001|59308501|abf585ec-e708-453f-b649-b5777ece85e6|eddaca4c-7506-4325-bd63-7dea02c1d967"
+      ],
       "meta": {
         "version": 2
       },
@@ -116,7 +118,7 @@
         "min_microvia_drill": 0.09999999999999999,
         "min_silk_clearance": 0.0,
         "min_through_hole_diameter": 0.3,
-        "min_track_width": 0.127,
+        "min_track_width": 0.15,
         "min_via_annular_width": 0.13,
         "min_via_diameter": 0.39999999999999997,
         "solder_mask_clearance": 0.0,
@@ -369,7 +371,7 @@
     "classes": [
       {
         "bus_width": 12.0,
-        "clearance": 0.2,
+        "clearance": 0.127,
         "diff_pair_gap": 0.25,
         "diff_pair_via_gap": 0.25,
         "diff_pair_width": 0.2,
@@ -400,17 +402,17 @@
         ],
         "pcb_color": "rgba(0, 0, 0, 0.000)",
         "schematic_color": "rgba(0, 0, 0, 0.000)",
-        "track_width": 0.4,
+        "track_width": 0.5,
         "via_diameter": 0.8,
         "via_drill": 0.4,
         "wire_width": 6.0
       },
       {
         "bus_width": 12.0,
-        "clearance": 0.127,
-        "diff_pair_gap": 0.127,
+        "clearance": 0.25,
+        "diff_pair_gap": 0.15,
         "diff_pair_via_gap": 0.25,
-        "diff_pair_width": 0.5,
+        "diff_pair_width": 0.6,
         "line_style": 0,
         "microvia_diameter": 0.3,
         "microvia_drill": 0.1,
@@ -421,7 +423,7 @@
         ],
         "pcb_color": "rgba(0, 0, 0, 0.000)",
         "schematic_color": "rgba(0, 0, 0, 0.000)",
-        "track_width": 0.5,
+        "track_width": 0.6,
         "via_diameter": 0.8,
         "via_drill": 0.4,
         "wire_width": 6.0
@@ -438,7 +440,7 @@
       "idf": "",
       "netlist": "",
       "specctra_dsn": "",
-      "step": "",
+      "step": "left.step",
       "vrml": ""
     },
     "page_layout_descr_file": ""