Minor formatting changes (found by PDF reading)

docs/RISC-V-Trace-Control-Interface.adoc

@@ -566,7 +566,7 @@ and Trace-off Debug module or External triggers respectively|WARL|0
 
 |15 |trTeInhibitSrc |
 *0:* Messages/packets generated by the trace encoder include a message source field if the
- source width held in `trTeSrcBits` is not 0.+
+ source width held in `trTeSrcBits` is not 0. +
 *1:* Disable inclusion of source field in trace messages/packets. 
 |WARL|SD
 
@@ -691,13 +691,13 @@ Timestamp Unit is an optional sub-component present in either Trace Encoder or T
 * *Shared* - shares timestamp with another Trace Encoder or Trace Funnel
 * *External* - accepts a binary timestamp value from an outside source such as ARM CoreSight(TM) trace (for both Trace Encoders and Trace Funnels)
 
-Implementations may have no timestamp, one timestamp mode, or more than one mode. The WARL field trTsMode is used to determine the system capability and to set the desired timestamp mode.
+Implementations may have no timestamp, one timestamp mode, or more than one mode. The WARL field `trTsMode`` is used to determine the system capability and to set the desired timestamp mode.
 
 The width of the timestamp is implementation-dependent, typically 40 or 48 bits (40 bit timestamp will overflow every 4.7 minutes assuming 1GHz timestamp clock).
 
 In a system with Funnels, typically all the Funnels are built with a Timestamp Unit. The top-level Funnel is the source of the timestamp (Internal System or External) and all the Encoders and other Funnels have a Shared timestamp. This assures that all timestamps in the system are the same and trace from different harts may be time-correlated. To perform the forwarding function, the mid-level Funnels must be programmed with `trFunnelActive` = 1 (which is natural as all trace messages must pass through that funnel).
 
-An Internal Timestamp Unit may include a timestamp clock prescaler divider, which can extend the range of a narrower timestamp and uses less power but has less resolution.
+An Internal Timestamp Unit may include a timestamp clock pre-scaler divider, which can extend the range of a narrower timestamp and uses less power but has less resolution.
 
 In a system with an Internal Core timestamp counter (implemented in Trace Encoder associated with a hart) an optional control bit is provided to stop the counter when the hart is halted by a debugger.
 
@@ -754,7 +754,7 @@ Prescale timestamp clock by 2^(2*trTsPrescale) (1, 4, 16, 64).
 
 ==== Debug Module Triggers
 
-Debug triggers are signals from the hart that a trigger (breakpoint or watchpoint) was hit, but the action associated with that trigger is a trace-related action. Action identifiers 2-5 are reserved for trace actions in the RISC-V Debug Specification, where triggers are defined. Actions 2-4 are defined by the Efficient Trace for RISC-V (E-Trace) Specification. The desired action is written to the action field of the Match Control mcontrol CSR (0x7a1). Not all harts support trace actions; the debugger should read back mcontrol CSR after setting one of these actions to verify that the option exists.
+Debug triggers are signals from the hart that a trigger (breakpoint or watchpoint) was hit, but the action associated with that trigger is a trace-related action. Action identifiers 2-5 are reserved for trace actions in the RISC-V Debug Specification, where triggers are defined. Actions 2-4 are defined by the Efficient Trace for RISC-V (E-Trace) Specification. The desired action is written to the `action` field of the Match Control `mcontrol` CSR (0x7a1). As not all harts may support all trace actions, the debugger should read back the `mcontrol` CSR after setting the desired trace action to verify that the option exists.
 
 .*Debug Trigger Actions*
 [cols="30%,70%",options="header",align=center]
@@ -793,7 +793,7 @@ External Trigger Outputs may also be present. A trigger out may be generated by
 |===
 |*Bit* |*Field* |*Description* |*RW* |*Reset*
 |3-0 |trTeTrigExtInAction0 a|
-Select action to perform when external trigger input 0 fires. If external trigger input 0 does not exist, then its action is fixed at 0. +
+Select action to perform when external trigger input #0 fires. If external trigger input #0 does not exist, then its action is fixed at 0. +
 *0:* No action +
 *1:* Reserved +
 *2:* *Trace-on action* +
@@ -806,23 +806,23 @@ When `trTeDataTrigEnable` = 1 it will stop data tracing (`trTeDataTracing` -> 0)
 If tracing is active (`trTeInstTracing` = 1), then the encoder generates a packet with the current PC and, if enabled, a timestamp. +
 *5-15:* Reserved +
 |WARL|0
-|31-4 |trTeTrigExtInAction *__n__* |Select actions (as defined for bits 3-0) for external trigger input *__n__* (1..7). If an external trigger input does not exist, then its action is fixed at 0. |WARL|0
+|31-4 |trTeTrigExtInAction**N** |Select actions (as defined for bits 3-0) for external trigger input #**N** (1..7). If an external trigger input does not exist, then its action is fixed at 0. |WARL|0
 |===
 
 .*Register: trTeTrigExtOutControl: External Trigger Output Control Register (trBaseEncoder+0x058)*
 [cols="5%,30%,~,8%,8%",options="header",]
 |===
 |*Bit* |*Field* |*Description* |*RW* |*Reset*
 |3-0 |trTeTrigExtOutEvent0 a|
-Bitmap to select which event(s) cause external trigger 0 output to fire. If external trigger output 0 does not exist, then all bits are fixed at 0. Bits 2 and 3 may be fixed at 0 if the corresponding feature is not implemented. +
+Bitmap to select which event(s) cause external trigger #0 output to fire. If external trigger output #0 does not exist, then all bits are fixed at 0. Bits 2 and 3 may be fixed at 0 if the corresponding feature is not implemented. +
 *Bit 0:* +
 Start trace transition (`trTeInstTracing` 0 -> 1) will fire the trigger. +
 *Bit 1:* + 
 Stop trace transition (`trTeInstTracing` 1 -> 0) will fire the trigger. +
 *Bit 2-3:* +
 Vendor-specific event (optional)
 |WARL|0
-|31-4 |trTeTrigExtOutEvent *__n__* |Select events for external trigger output *__n__* (1..7). If an external trigger output does not exist, then its event bits are fixed at 0 |WARL|0
+|31-4 |trTeTrigExtOutEvent**N** |Select events for external trigger output #**N** (1..7). If an external trigger output does not exist, then its event bits are fixed at 0 |WARL|0
 |===
 
 ==== Triggers Precedence
@@ -837,7 +837,7 @@ Trace encoder filters are an optional feature that can be used to control the ge
 
 The registers below divide the filter logic into filters and comparators to provide maximum flexibility at low cost. The number of filters and comparators depends on the system. Each filter unit can specify filtering against instruction and optionally against data trace inputs from the hart. When filter __i__ is implemented, the registers `trTeFilter__i__Control` and `trTeInstFilters` must be implemented to enable it. And to apply filter __i__ to the data trace, the `trTeDataFilters` register must also be present. And if a match bit in the `trTeFilter__i__Control` register can be set to 1 (= enabling a filter option), the corresponding register from the bit's description must have a correct value already set as otherwise the trigger may fire unintentionally. Each of the mentioned comparator units is actually a pair of comparators (primary and secondary, or P and S), so a limited range can be matched with a single comparator unit if needed.
 
-NOTE: Filter and comparator registers refer to values of some signals (as *priv*, *itype*, *ecause*, *dtype*, '*dsize*, ...) available on Trace Ingress Port. See E-Trace specification for details of encoding of these values.
+NOTE: Filter and comparator registers refer to values of some signals (as *priv*, *itype*, *ecause*, *dtype*, *dsize*, ...) available on Trace Ingress Port. See E-Trace specification for details of encoding of these values.
 
 .*Register: trTeFilter??: Trace Encoder Filter Registers (trBaseEncoder+0x400..0x5FF)*
 [cols="10%,35%,14%,~",options="header",]
@@ -915,7 +915,7 @@ When set, match *dsize* values as specified by `trTeFilterMatchChoiceDsize` fiel
 |===
 
 .*Register: trTeFilter__i__MatchInst : Filter _i_ Instruction Match Control Register (trBaseEncoder+0x404 + 0x20__i__)*
-[cols="5%,40%,~,8%,8%",options="header",]
+[cols="5%,38%,~,8%,8%",options="header",]
 |===
 |*Bit* |*Field* |*Description* |*RW* |*Reset*
 |7-0   |trTeFilterMatchChoicePrivilege | 
@@ -930,16 +930,16 @@ respectively.
 |===
 
 .*Register: trTeFilter__i__MatchEcauseLow : Filter _i_ Ecause Match Control (low) Register (trBaseEncoder+0x408 + 0x20__i__)*
-[cols="5%,40%,~,8%,8%",options="header",]
+[cols="5%,38%,~,8%,8%",options="header",]
 |===
 |*Bit* |*Field* |*Description* |*RW* |*Reset*
-|31-0   |trTeFilterMatchChoiceEcause | 
+|31-0   |trTeFilterMatchChoiceEcauseLow | 
 When `trTeFilterMatchEcause` field for filter #__i__ is set, match all excepion causes for which the corresponding bit is set. If bit N is 1, then match if the *ecause* is N.
 |WARL|SD 
 |===
 
 .*Register: trTeFilter__i__MatchEcauseHigh : Filter _i_ Ecause Match Control (high) Register (trBaseEncoder+0x40C + 0x20__i__)*
-[cols="5%,40%,~,8%,8%",options="header",]
+[cols="5%,38%,~,8%,8%",options="header",]
 |===
 |*Bit* |*Field* |*Description* |*RW* |*Reset*
 |31-0   |trTeFilterMatchChoiceEcauseHigh | This register stores bits 63:32 to allow matching of higher *ecause* codes. If bit N is 1, then match if the *ecause* is N+32.
@@ -1041,7 +1041,7 @@ known as a watchpoint.
 |31-16 |--|Reserved|--|0
 |===
 
-IMPORTANT: Comparisions are performed as unsigned numbers. Only bits from an input signal, as defined by `trTeCompPInput` or `trTeCompSInput`, should be compared. Additional bits from `trTeComp__j__PMatchLow/High` must be ignored.
+IMPORTANT: Comparisions are performed as unsigned numbers. Only bits from an input signal (as defined by `trTeCompPInput` and/or `trTeCompSInput` fields), should be compared. Additional most significant bits from the `trTeComp__j__PMatchLow/High` registers must be ignored.
 
 .*Register: trTeComp__j__PMatchLow : Comparator _j_ Primary match (low) Register (trBaseEncoder+0x610 + 0x20__j__)*
 [cols="5%,30%,~,8%,8%",options="header",]
@@ -1311,10 +1311,10 @@ down, and other register locations may be inaccessible. Hardware may take an arb
  See <<Enabling and Disabling,Enabling and Disabling>> chapter for more details.
 |RW |0
 |2 |--|Reserved|--|0
-|3 |trPibEmpty |Reads 1 when PIB internal buffers are empty |R|1
+|3 |trPibEmpty |Reads 1 when PIB internal buffers are empty.|R|1
 |7-4 |trPibMode |Select mode for output pins. Allowed values are described in the `Allowed PIB Configurations` table below.|WARL|0
-|8 |trPibClkCenter |In parallel modes, adjust TRC_CLK timing to the center of the bit period. This can be set only if `trPibMode` selects one of the parallel protocols. Optional. |WARL|SD
-|9 |trPibCalibrate |Set this to 1 to generate a repeating calibration pattern to help tune a probe's signal delays, bit rate, etc. In this mode input to the sink is not consumed. The calibration pattern is described below. Optional. |WARL|0
+|8 |trPibClkCenter |In parallel modes, adjust TRC_CLK timing to the center of the bit period. This can be set only if `trPibMode` selects one of the parallel protocols.|WARL|SD
+|9 |trPibCalibrate |Set this to 1 to generate a repeating calibration pattern to help tune a probe's signal delays, bit rate, etc. In this mode input to the sink is not consumed. The calibration pattern is described below.|WARL|0
 |11-10 |--|Reserved|--|0
 |14-12 |trPibAsyncFreq |
 *0:* Alignment synchronization packets disabled (may be the only choice for some protocols) +
@@ -1510,7 +1510,7 @@ SRAM mode only:
 * Register `trRamWPLow` must at least accept a write of 0.
 * Register `trRamRPLow` must accept any 32-bit aligned value in inclusive range < 0 .. `trRamLimitLow` >.
 ** If width of access to SRAM is wider than 32-bits any 32-bit aligned value of `trRamRP` must be allowed and reads must be buffered.
-* Register `trRamData` must be implemented for reading only.
+* Register `trRamData` may be implemented for reading only.
 * All other registers/fields/bits may be tied to 0.
 
 SMEM mode only:
@@ -1632,13 +1632,13 @@ Decoding trace
 
 === Legacy Interface Version
 
-Value of `trTeVerMajor` as 0 means this is the original version of this control interface.
+Value of `trTeVerMajor` as 0 means this is the original version of this trace control interface.
 
-Initially this specification was kept somewhat compatible, but after the split of components into 4K regions it was hard to list all changes.
+Initially this specification was kept somewhat compatible, but after the decision to split all components into 4K regions it was very hard to track and list all changes and appropriate chapter was removed.
 
-In general the migration path from 'ver 0' (for both IP providers and tool vendors) should not be hard as the main concepts remain unchanged.
+The migration path from 'ver 0' (for both IP providers and tool vendors) should not be hard as the main concepts remain unchanged.
 
-Original donation from SiFive is located here: 
+Original donation from SiFive (which describes implementation of legacy version 0) can be found here:
 https://lists.riscv.org/g/tech-nexus/files/RISC-V-Trace-Control-Interface-Proposed-20200612.pdf[RISC-V-Trace-Control-Interface-Proposed-20200612.pdf]
 
 IMPORTANT: Not all trace tools may support legacy version 0. But all such tools should reject the version 0 with a very clear message.