This repository includes the example codes for EIE330 FPGA-Based System Design. All codes are written in Verilog HDL.
In this course, the example experiments include
- Lab 1:
- 1-1. Simple LED Circuit
- 1-2. 2-to-1 Multiplexer
- 1-3. 3-8 Line Decoder
- 1-4. Half Adder
- Lab 2:
- 2-1. Top-Down Design
- 2-2. Avoid Latch
- 2-3. Flip-Flop
- Lab 3:
- 3-1. Simple Finite State Machine
- Lab 4:
- 4-1. PLL IP Core
- 4-2. VGA Display
- Lab 5:
- 5-1. RAM IP Core
- 5-2. Key Debounce
- 5-3. ROM IP Core
- 5-4. VGA with ROM
Note: Codes that students are required to implement by themselves are not included in this repository.