Merge pull request #13 from muhammadhamza15/main

Yaml files and Blackbox update

models_internal/verilog_blackbox/cell_sim_blackbox.v

@@ -289,6 +289,7 @@ module I_BUF #(
   ,   parameter IOSTANDARD = "DEFAULT" // IO Standard
 `endif // RAPIDSILICON_INTERNAL
   ) (
+  (* iopad_external_pin *)
   input logic I,
   input logic EN,
   output logic O
@@ -519,6 +520,7 @@ module O_BUFT #(
   ) (
   input logic I,
   input logic T,
+  (* iopad_external_pin *)
   output logic O
 );
 endmodule
@@ -541,6 +543,7 @@ module O_BUF
 `endif // RAPIDSILICON_INTERNAL
   (
   input logic I,
+  (* iopad_external_pin *)
   output logic O
 );
 endmodule

specs/I_BUF.yaml

@@ -51,6 +51,7 @@ ports:
    I:
      dir: input
      desc: Data input (connect to top-level port)
+     bb_attributes: iopad_external_pin
    EN:
      dir: input
      desc: Enable the input

specs/I_DDR.yaml

@@ -45,6 +45,7 @@
 # primitive name should match the filename root.
 name: I_DDR
 desc: DDR input register
+category: periphery
 
 ports:
    D:

specs/O_BUF.yaml

@@ -54,7 +54,7 @@ ports:
    O:
      dir: output
      desc: Data output (connect to top-level port)
-
+     bb_attributes: iopad_external_pin  
 
 # set in SDC or by synthesis attribute      
 properties:

specs/O_BUFT.yaml

@@ -57,6 +57,7 @@ ports:
    O:
      dir: output
      desc: Data output (connect to top-level port)
+     bb_attributes: iopad_external_pin
 
 parameters:
    WEAK_KEEPER:

specs/O_DDR.yaml

@@ -45,6 +45,7 @@
 # primitive name should match the filename root.
 name: O_DDR
 desc: DDR output register
+category: periphery
 
 ports:
    D[1:0]: