Updated Generators comments

os-fpga · Jul 23, 2024 · e5ba6ef · e5ba6ef
1 parent cc0e1c1
commit e5ba6ef
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Showing 4 changed files with 4 additions and 4 deletions.
diff --git a/rapidsilicon/ip/axi_sdram/v1_0/axi_sdram_gen.py b/rapidsilicon/ip/axi_sdram/v1_0/axi_sdram_gen.py
@@ -49,7 +49,7 @@ def sdram_interface():
         ("sdram_data_out_en_o", 0,  Pins(1)),
     ]
 
-# AXI RAM Wrapper ----------------------------------------------------------------------------------
+# SDRAM Wrapper ----------------------------------------------------------------------------------
 class SDRAMWRAPPER(Module):
     def __init__(self, platform):
         # Clocking ---------------------------------------------------------------------------------

diff --git a/rapidsilicon/ip/axi_sdram/v1_0/litex_wrapper/axi_sdram_litex_wrapper.py b/rapidsilicon/ip/axi_sdram/v1_0/litex_wrapper/axi_sdram_litex_wrapper.py
@@ -35,7 +35,7 @@ def colorer(s, color="bright"):
     trailer = "\x1b[0m"
     return header + str(s) + trailer
 
-# AXI RAM ------------------------------------------------------------------------------------------
+# AXI SDRAM ------------------------------------------------------------------------------------------
 
 class AXISDRAM(Module):
     def __init__(self, platform, s_axi ):

diff --git a/rapidsilicon/ip/boot_clock/v1_0/boot_clock_gen.py b/rapidsilicon/ip/boot_clock/v1_0/boot_clock_gen.py
@@ -30,7 +30,7 @@ def get_other_ios():
         ("O",  0, Pins(1)),
     ]
 
-# AXI RAM Wrapper ----------------------------------------------------------------------------------
+# Boot clock Wrapper ----------------------------------------------------------------------------------
 class BOOTCLOCKWrapper(Module):
     def __init__(self, platform, period):
         self.clock_domains.cd_sys  = ClockDomain()

diff --git a/rapidsilicon/ip/pll/v1_0/pll_gen.py b/rapidsilicon/ip/pll/v1_0/pll_gen.py
@@ -33,7 +33,7 @@ def get_clkin_ios():
         ("LOCK",            0, Pins(1)),
             ]
 
-# AXI RAM Wrapper ----------------------------------------------------------------------------------
+# PLL Wrapper ----------------------------------------------------------------------------------
 class PLLWrapper(Module):
     def __init__(self, platform, divide_clk_in_by_2, fast_clk_freq, ref_clk_freq, pll_post_div):