READMEs: Cosmetics, consistency fixes, typos.

lorcap · Apr 19, 2012 · 47cd3c8 · 47cd3c8
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diff --git a/dcf77/pollin_dcf1_module/README b/dcf77/pollin_dcf1_module/README
@@ -19,9 +19,7 @@ http://www.pollin.de/shop/downloads/D810054D.PDF
 Logic analyzer setup
 --------------------
 
-The logic analyzer used for capturing was a Saleae Logic.
-
-The logic analyzer probes were connected like this:
+The logic analyzer used was a Saleae Logic (at 1MHz):
 
   Probe       DCF77 module
   ------------------------

diff --git a/i2c/a2_dummy_write/README b/i2c/a2_dummy_write/README
@@ -3,15 +3,14 @@ Dummy I2C writes
 -------------------------------------------------------------------------------
 
 This an example capture of some dummy I2C traffic, where the master writes
-to a slave at address 0x51 (or 0x2a, if the read/write bit is included)
-in an infinite loop. The slave does not respond.
+to a slave (an RTC) at address 0x51 (or 0x2a, if the read/write bit is
+included) in an infinite loop. The slave does not respond.
 
 
 Logic analyzer setup
 --------------------
 
-The logic analyzer used for capturing was a ChronoVu LA8 at a sample rate
-of 1MHz. The logic analyzer probes were connected to the I2C pins like this:
+The logic analyzer used was a ChronoVu LA8 (at 1MHz):
 
   Probe       RTC chip pin
   ------------------------

diff --git a/i2c/edid/README b/i2c/edid/README
@@ -17,21 +17,21 @@ https://en.wikipedia.org/wiki/Display_Data_Channel
 samsung_le46b620r3p.sr / samsung_syncmaster245b.sr
 --------------------------------------------------
 
-The logic analyzer used was a Saleae Logic at 500kHz:
+The logic analyzer used was a Saleae Logic (at 500kHz):
 
-  Probe       I2C pins
-  --------------------
+  Probe       I2C pin
+  -------------------
   1 (black)   SDA
   2 (brown)   SCL
 
 
 samsung_syncmaster203b.sr
 -------------------------
 
-The logic analyzer used was a Saleae Logic at 1MHz:
+The logic analyzer used was a Saleae Logic (at 1MHz):
 
-  Probe       I2C pins
-  --------------------
+  Probe       I2C pin
+  -------------------
   1 (black)   SCL
   2 (brown)   SDA
 
diff --git a/i2c/gigabyte_6vle-vxl_i2c/README b/i2c/gigabyte_6vle-vxl_i2c/README
@@ -22,7 +22,7 @@ http://pdf1.alldatasheet.com/datasheet-pdf/view/90645/ICST/ICS950908.html
 Logic analyzer setup
 --------------------
 
-The logic analyzer used for capturing was a Saleae Logic:
+The logic analyzer used was a Saleae Logic (at 2MHz):
 
   Probe       I2C pin
   -------------------

diff --git a/i2c/melexis_mlx90614/README b/i2c/melexis_mlx90614/README
@@ -2,7 +2,7 @@
 Melexis MLX90614 Infrared Thermometer
 -------------------------------------------------------------------------------
 
-This an a collection of example captures of I2C traffic from/to a
+This is a collection of example captures of I2C traffic from/to a
 Melexis MLX90614 Infrared Thermometer chip.
 
 Details:
@@ -15,10 +15,10 @@ http://www.melexis.com/Assets/IR-sensor-thermometer-MLX90614-Datasheet-5152.aspx
 Logic analyzer setup
 --------------------
 
-The logic analyzer used for capturing was a Saleae Logic:
+The logic analyzer used was a Saleae Logic (at 1MHz):
 
-  Probe       I2C
-  ------------------------
+  Probe       I2C pin
+  -------------------
   6 (green)   SCL
   8 (purple)  SDA
 

diff --git a/i2c/rtc_epson_8564je/README b/i2c/rtc_epson_8564je/README
@@ -9,8 +9,7 @@ which has a slave address of 0x51 (or 0xa2, if the read/write bit is included).
 Logic analyzer setup
 --------------------
 
-The logic analyzer used for capturing was a ChronoVu LA8 at a sample rate
-of 1MHz. The logic analyzer probes were connected to the RTC chip like this:
+The logic analyzer used was a ChronoVu LA8 (at 1MHz):
 
   Probe       RTC chip pin
   ------------------------

diff --git a/i2c/trekstor_ebr30_a/README b/i2c/trekstor_ebr30_a/README
@@ -21,7 +21,7 @@ There are three chips which are connected to the main CPU's SCL/SDA pins:
 trekstor_ebr30_a_i2c_0x15.sr
 ----------------------------
 
-The logic analyzer used for capturing was a ChronoVu LA8:
+The logic analyzer used was a ChronoVu LA8 (at 4MHz):
 
   Probe       I2C pin
   -------------------
@@ -40,7 +40,7 @@ trekstor_ebr30_a_i2c_30s.sr and trekstor_ebr30_a_i2c_120s.sr
 This is a 30s/120s dump of the I2C traffic while the device was attached
 to USB.
 
-The logic analyzer used for capturing was a Saleae Logic:
+The logic analyzer used was a Saleae Logic (at 4MHz):
 
   Probe       I2C pin
   -------------------

diff --git a/i2s/2ch-16bit-16khz/README b/i2s/2ch-16bit-16khz/README
@@ -2,18 +2,16 @@
 I2S Master 2-channel 16-bit 16-kHz
 -------------------------------------------------------------------------------
 
-This is an example of an I2S master with a playing a recording of the BBC
+This is an example of an I2S master playing a recording of the BBC
 shipping forecast through one channel, and the other channel disconnected.
 
 Logic analyzer setup
 --------------------
 
-The logic analyzer used for capturing was a EE Electronics ESLA201A at a
-sample rate of 16MHz. The logic analyzer probes were connected to the I2S
-pins like this:
+The logic analyzer used was an EE Electronics ESLA201A (at 16MHz):
 
-  Probe       Signal
-  ------------------------
+  Probe       I2S pin
+  -------------------
   0           Clock
   1           Frame Select
   2           Data

diff --git a/jtag/olimex_stm32-h103/README b/jtag/olimex_stm32-h103/README
@@ -10,7 +10,8 @@ The JTAG adapter used was the FTDI FT2232H based Floss-JTAG (V0.2).
 The firmware flashed to the board is a simple LED-blinking libopencm3
 example named 'fancyblink'. The respective fancyblink.bin file is
 available as a reference in the same directory as this README.
-The file's MD5 sum is aa6980d55b9ced84fc0c64bfe9e5ff98.
+The file's MD5 sum is aa6980d55b9ced84fc0c64bfe9e5ff98. The binary is licensed
+under the GPL, version 3 or later (see URL below for the source code).
 
 Details:
 http://olimex.com/dev/stm32-h103.html
@@ -22,7 +23,7 @@ http://libopencm3.git.sourceforge.net/git/gitweb.cgi?p=libopencm3/libopencm3;a=t
 Logic analyzer setup
 --------------------
 
-The logic analyzer used for capturing was a Saleae Logic:
+The logic analyzer used was a Saleae Logic (at 4MHz):
 
   Probe       STM32-H103 JTAG connector
   -------------------------------------

diff --git a/mouse_sensors/avago_adns_2051/README b/mouse_sensors/avago_adns_2051/README
@@ -13,9 +13,7 @@ http://www.avagotech.com/pages/en/navigation_interface_devices/navigation_sensor
 Logic analyzer setup
 --------------------
 
-The logic analyzer used for capturing was a Saleae Logic.
-
-The logic analyzer probes were connected like this:
+The logic analyzer used was a Saleae Logic (at 4MHz):
 
   Probe       Avago ADNS-2051
   ---------------------------

diff --git a/spi/mx25l1605d/README b/spi/mx25l1605d/README
@@ -18,13 +18,10 @@ The software used for programming it is flashrom, see
 Logic analyzer setup
 --------------------
 
-The logic analyzer used for capturing is a ChronoVu LA8 at a sample rate
-of 25MHz.
+The logic analyzer used was a ChronoVu LA8 (at 25MHz):
 
-The ChronoVu LA8 probes were connected to the MX25L1605D chip like this:
-
-  Probe       SPI chip pin
-  ------------------------
+  Probe       MX25L1605D pin
+  --------------------------
   0 (green)   CS#
   1 (orange)  SO/SIO1 (a.k.a MISO)
   2 (white)   SCLK

diff --git a/uart/hello_world/README b/uart/hello_world/README
@@ -19,14 +19,11 @@ http://olimex.com/dev/stm32-h103.html
 Logic analyzer setup
 --------------------
 
-The logic analyzer used for capturing is a ChronoVu LA8 at a sample rate
-of 5MHz (for baud rates 921600 - 230400), 1MHz (for 115200 - 19200),
-and 625kHz (for baud rates 9600 - 1200).
-
-The ChronoVu LA8 probes were connected to the UART like this:
+The logic analyzer used was a ChronoVu LA8 at a sample rate of 5MHz (for baud
+rates 921600 - 230400), 1MHz (115200 - 19200), and 625kHz (9600 - 1200):
 
   Probe       UART
-  -------------------
+  ----------------
   0 (green)   TX
 
 

diff --git a/uart/panasonic_pan1321/README b/uart/panasonic_pan1321/README
@@ -16,10 +16,7 @@ http://www.datasheets.org.uk/indexdl/Datasheet-098/DSA00161388.pdf
 Logic analyzer setup
 --------------------
 
-The logic analyzer used for capturing is a ChronoVu LA8 at a sample rate
-of 500kHz.
-
-The logic analyzer probes were connected like this:
+The logic analyzer used was a ChronoVu LA8 (at 500kHz):
 
   Probe       PAN1321
   -------------------
@@ -63,7 +60,7 @@ The sigrok command line used was:
 
 The data sent/received is the same as in the above example. The difference
 is that we triggered on the first high RX state, which might lead to
-some garbage for the first few decoded characters. This is file intended as
+some garbage for the first few decoded characters. This file is intended as
 a test-case for this situation.
 
 

diff --git a/uart/trekstor_ebr30_a/README b/uart/trekstor_ebr30_a/README
@@ -15,10 +15,7 @@ The firmware sends the debug output at 115200 baud, with 8n1 settings.
 Logic analyzer setup
 --------------------
 
-The logic analyzer used for capturing is a ChronoVu LA8 at a sample rate
-of 1MHz.
-
-The ChronoVu LA8 probes were connected to the EBR30-a device like this:
+The logic analyzer used was a ChronoVu LA8 (at 1MHz):
 
   Probe       EBR30-a
   -------------------

diff --git a/usb/lisa_m_usbhid/README b/usb/lisa_m_usbhid/README
@@ -15,8 +15,7 @@ http://paparazzi.enac.fr/wiki/User/LisaM
 Logic analyser setup
 --------------------
 
-The capture was taken using the Openbench Logic Sniffer at a sample rate
-of 50MHz.
+The logic analyzer used was an Openbench Logic Sniffer (at 50MHz):
 
   Probe    Signal
   ---------------
@@ -27,11 +26,11 @@ of 50MHz.
   4        SPI_MOSI
   5        SPI_MISO
 
-The command line used was:
+The sigrok command line used was:
 
-sigrok-cli -d 0:samplerate=50mhz:rle=on \
-        -p 1=USB_DM,2=USB_DP,3=SPI_NCS,4=SPI_SCK,5=SPI_MOSI,6=SPI_MISO \
-        --time=50ms -o lisa_m_usb_spi.sr
+  sigrok-cli -d 0:samplerate=50mhz:rle=on \
+             -p 1=USB_DM,2=USB_DP,3=SPI_NCS,4=SPI_SCK,5=SPI_MOSI,6=SPI_MISO \
+             --time=50ms -o lisa_m_usb_spi.sr
 
 The OLS can't actually capture 50ms, so it just captures as much as it can
 buffer. No triggering was used.

diff --git a/usb/olimex_stm32-h103_usb_hid/README b/usb/olimex_stm32-h103_usb_hid/README
@@ -18,7 +18,7 @@ http://libopencm3.git.sourceforge.net/git/gitweb.cgi?p=libopencm3/libopencm3;a=t
 Logic analyzer setup
 --------------------
 
-The logic analyzer used for capturing was a ChronoVu LA8:
+The logic analyzer used was a ChronoVu LA8 (at 100MHz):
 
   Probe       STM32-H103
   ----------------------