Merge branch 'devel'

lnls-dig · Jun 4, 2018 · c00c28d · c00c28d
2 parents 91ebf0c + 99e041b
commit c00c28d
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Showing 8 changed files with 178 additions and 42 deletions.
diff --git a/hdl/ip_cores/dsp-cores b/hdl/ip_cores/dsp-cores
diff --git a/hdl/syn/.gitignore b/hdl/syn/.gitignore
@@ -68,3 +68,25 @@ planAhead_run_*/
 *.srcs/
 *.jou
 *.log
+
+# hdlmake stuff
+
+*tcl_bitstream
+*tcl_map
+*tcl_par
+*tcl_synthesize
+*tcl_translate
+
+*bitstream
+*map
+*par
+*synthesize
+*translate
+
+*bitstream.tcl
+*map.tcl
+*par.tcl
+*synthesize.tcl
+*translate.tcl
+*project.tcl
+*files.tcl
diff --git a/hdl/syn/afc_v3/vivado/dbe_bpm2_bo_sirius/Manifest.py b/hdl/syn/afc_v3/vivado/dbe_bpm2_bo_sirius/Manifest.py
@@ -1,6 +1,8 @@
 target = "xilinx"
 action = "synthesis"
 
+language = "vhdl"
+
 syn_device = "xc7a200t"
 syn_grade = "-2"
 syn_package = "ffg1156"

diff --git a/hdl/syn/afc_v3/vivado/dbe_bpm2_sr_sirius/Manifest.py b/hdl/syn/afc_v3/vivado/dbe_bpm2_sr_sirius/Manifest.py
@@ -1,6 +1,8 @@
 target = "xilinx"
 action = "synthesis"
 
+language = "vhdl"
+
 syn_device = "xc7a200t"
 syn_grade = "-2"
 syn_package = "ffg1156"

diff --git a/hdl/syn/afc_v3/vivado/dbe_bpm2_sr_uvx/Manifest.py b/hdl/syn/afc_v3/vivado/dbe_bpm2_sr_uvx/Manifest.py
@@ -1,6 +1,8 @@
 target = "xilinx"
 action = "synthesis"
 
+language = "vhdl"
+
 syn_device = "xc7a200t"
 syn_grade = "-2"
 syn_package = "ffg1156"

diff --git a/hdl/syn/afc_v3/vivado/dbe_bpm_sr_uvx/Manifest.py b/hdl/syn/afc_v3/vivado/dbe_bpm_sr_uvx/Manifest.py
@@ -1,6 +1,8 @@
 target = "xilinx"
 action = "synthesis"
 
+language = "vhdl"
+
 syn_device = "xc7a200t"
 syn_grade = "-2"
 syn_package = "ffg1156"

diff --git a/hdl/syn/afc_v3/vivado/dbe_pbpm/Manifest.py b/hdl/syn/afc_v3/vivado/dbe_pbpm/Manifest.py
@@ -1,6 +1,8 @@
 target = "xilinx"
 action = "synthesis"
 
+language = "vhdl"
+
 syn_device = "xc7a200t"
 syn_grade = "-2"
 syn_package = "ffg1156"

diff --git a/hdl/top/afc_v3/vivado/dbe_bpm_gen/dbe_bpm_gen.vhd b/hdl/top/afc_v3/vivado/dbe_bpm_gen/dbe_bpm_gen.vhd
+36 −0		hdl/modules/dsp_cores_pkg.vhd
+38 −9		hdl/modules/position_calc/position_calc.vhd
+319 −8		hdl/modules/wb_position_calc/wb_position_calc_core.vhd
+7,564 −1,198		hdl/modules/wb_position_calc/wbgen/doc/pos_calc_regs_wb.html
+237 −89		hdl/modules/wb_position_calc/wbgen/pos_calc_regs.h
+418 −94		hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs.vhd
+256 −14		hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs.wb
+90 −20		hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs_pkg.vhd
+24 −0		hdl/modules/wb_position_calc/xwb_position_calc_core.vhd
+85 −38		hdl/sim/regs/wb_pos_calc_regs.vh
+62 −45		hdl/testbench/cic/cic_bench.vhd
+40 −13		hdl/testbench/cic/wave.do
+2 −1		hdl/testbench/position/Manifest.py