Merge pull request #260 from icedland/viapadlock

Update VIA `PADLOCK` instructions, add missing `XSHA512`
icedland · Feb 3, 2022 · eae7e3a · eae7e3a
2 parents bfadd2a + 9857e63
commit eae7e3a
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diff --git a/build/build-dotnet b/build/build-dotnet
@@ -36,7 +36,7 @@ new_func() {
 generator_check() {
 	new_func "Run generator, verify no diff"
 
-	dotnet run -c $configuration -p "$root_dir/src/csharp/Intel/Generator/Generator.csproj"
+	dotnet run -c $configuration --project "$root_dir/src/csharp/Intel/Generator/Generator.csproj"
 	git diff --exit-code
 }
 

diff --git a/src/UnitTests/Intel/Decoder/Code.32Only.txt b/src/UnitTests/Intel/Decoder/Code.32Only.txt
@@ -235,3 +235,7 @@ Cyrix_DEDE
 Frinear
 Ccs_hash_16
 Ccs_encrypt_16
+Via_undoc_F30FA6F0_16
+Via_undoc_F30FA6F8_16
+Xsha512_16
+Xstore2_16
diff --git a/src/UnitTests/Intel/Decoder/Code.64Only.txt b/src/UnitTests/Intel/Decoder/Code.64Only.txt
@@ -716,3 +716,7 @@ MVEX_Vcvtfxpntps2dq_zmm_k1_zmmmt_imm8
 MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0
 MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1
 MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8
+Via_undoc_F30FA6F0_64
+Via_undoc_F30FA6F8_64
+Xsha512_64
+Xstore2_64
diff --git a/src/UnitTests/Intel/Decoder/DecoderTest16.txt b/src/UnitTests/Intel/Decoder/DecoderTest16.txt
diff --git a/src/UnitTests/Intel/Decoder/DecoderTest32.txt b/src/UnitTests/Intel/Decoder/DecoderTest32.txt
diff --git a/src/UnitTests/Intel/Decoder/DecoderTest64.txt b/src/UnitTests/Intel/Decoder/DecoderTest64.txt
diff --git a/src/UnitTests/Intel/Encoder/OpCodeInfos.txt b/src/UnitTests/Intel/Encoder/OpCodeInfos.txt
@@ -4821,3 +4821,15 @@ MVEX_Vcvtfxpntps2dq_zmm_k1_zmmmt_imm8, Vcvtfxpntps2dq, Unknown, Unknown, MVEX, 6
 MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D0, Undoc, Unknown, Unknown, MVEX, 66, 0F3A, D0, MVEX.512.66.0F3A.W0 D0 /r ib, UNDOC zmm1 {k1}| zmm2/mt| imm8, dec-opt=KNC 64 cpl0 cpl1 cpl2 cpl3 L512 W0 op=zmm_reg;zmm_or_mem;imm8 save-restore tt=N1 mvex=Float32;None;0xFF;0xFF er sae k intel64 amd64 lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam eh
 MVEX_Undoc_zmm_k1_zmmmt_imm8_512_66_0F3A_W0_D1, Undoc, Unknown, Unknown, MVEX, 66, 0F3A, D1, MVEX.512.66.0F3A.W0 D1 /r ib, UNDOC zmm1 {k1}| zmm2/mt| imm8, dec-opt=KNC 64 cpl0 cpl1 cpl2 cpl3 L512 W0 op=zmm_reg;zmm_or_mem;imm8 save-restore tt=N1 mvex=Float32;None;0xFF;0xFF er sae k intel64 amd64 lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam eh
 MVEX_Vcvtfxpntpd2dq_zmm_k1_zmmmt_imm8, Vcvtfxpntpd2dq, Unknown, Unknown, MVEX, F2, 0F3A, E6, MVEX.512.F2.0F3A.W1 E6 /r ib, VCVTFXPNTPD2DQ zmm1 {k1}| Sf64(zmm2/mt)| imm8, dec-opt=KNC 64 cpl0 cpl1 cpl2 cpl3 L512 W1 op=zmm_reg;zmm_or_mem;imm8 tt=N1 mvex=Float64;Sf64;0x7;0xFF er sae k intel64 amd64 lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam eh er-imm
+Via_undoc_F30FA6F0_16, Undoc, Unknown, Unknown, legacy, F3, 0F, A6F0, a16 F3 0F A6 F0, UNDOC, 16 32 cpl0 cpl1 cpl2 cpl3 a16 save-restore intel16 intel32 amd16 amd32 rm pm v86 cm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
+Via_undoc_F30FA6F0_32, Undoc, Unknown, Unknown, legacy, F3, 0F, A6F0, a32 F3 0F A6 F0, UNDOC, 16 32 64 cpl0 cpl1 cpl2 cpl3 a32 save-restore intel16 intel32 intel64 amd16 amd32 amd64 rm pm v86 cm lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
+Via_undoc_F30FA6F0_64, Undoc, Unknown, Unknown, legacy, F3, 0F, A6F0, a64 F3 0F A6 F0, UNDOC, 64 cpl0 cpl1 cpl2 cpl3 a64 save-restore intel64 amd64 lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
+Via_undoc_F30FA6F8_16, Undoc, Unknown, Unknown, legacy, F3, 0F, A6F8, a16 F3 0F A6 F8, UNDOC, 16 32 cpl0 cpl1 cpl2 cpl3 a16 save-restore intel16 intel32 amd16 amd32 rm pm v86 cm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
+Via_undoc_F30FA6F8_32, Undoc, Unknown, Unknown, legacy, F3, 0F, A6F8, a32 F3 0F A6 F8, UNDOC, 16 32 64 cpl0 cpl1 cpl2 cpl3 a32 save-restore intel16 intel32 intel64 amd16 amd32 amd64 rm pm v86 cm lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
+Via_undoc_F30FA6F8_64, Undoc, Unknown, Unknown, legacy, F3, 0F, A6F8, a64 F3 0F A6 F8, UNDOC, 64 cpl0 cpl1 cpl2 cpl3 a64 save-restore intel64 amd64 lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
+Xsha512_16, Xsha512, Unknown, Unknown, legacy, F3, 0F, A6E0, a16 F3 0F A6 E0, XSHA512, 16 32 cpl0 cpl1 cpl2 cpl3 a16 intel16 intel32 amd16 amd32 rm pm v86 cm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
+Xsha512_32, Xsha512, Unknown, Unknown, legacy, F3, 0F, A6E0, a32 F3 0F A6 E0, XSHA512, 16 32 64 cpl0 cpl1 cpl2 cpl3 a32 intel16 intel32 intel64 amd16 amd32 amd64 rm pm v86 cm lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
+Xsha512_64, Xsha512, Unknown, Unknown, legacy, F3, 0F, A6E0, a64 F3 0F A6 E0, XSHA512, 64 cpl0 cpl1 cpl2 cpl3 a64 intel64 amd64 lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
+Xstore2_16, Xstore2, Unknown, Unknown, legacy, F3, 0F, A7F8, a16 F3 0F A7 F8, XSTORE2, 16 32 cpl0 cpl1 cpl2 cpl3 a16 intel16 intel32 amd16 amd32 rm pm v86 cm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
+Xstore2_32, Xstore2, Unknown, Unknown, legacy, F3, 0F, A7F8, a32 F3 0F A7 F8, XSTORE2, 16 32 64 cpl0 cpl1 cpl2 cpl3 a32 intel16 intel32 intel64 amd16 amd32 amd64 rm pm v86 cm lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
+Xstore2_64, Xstore2, Unknown, Unknown, legacy, F3, 0F, A7F8, a64 F3 0F A7 F8, XSTORE2, 64 cpl0 cpl1 cpl2 cpl3 a64 intel64 amd64 lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
diff --git a/src/UnitTests/Intel/Formatter/Fast/Test16_Default.txt b/src/UnitTests/Intel/Formatter/Fast/Test16_Default.txt
@@ -518,3 +518,11 @@ pvalidate
 serialize
 xsusldtrk
 xresldtrk
+rep undoc
+rep undoc
+rep undoc
+rep undoc
+rep xsha512
+rep xsha512
+rep xstore2
+rep xstore2
diff --git a/src/UnitTests/Intel/Formatter/Fast/Test16_Inverted.txt b/src/UnitTests/Intel/Formatter/Fast/Test16_Inverted.txt
@@ -518,3 +518,11 @@ pvalidate
 serialize
 xsusldtrk
 xresldtrk
+rep undoc
+rep undoc
+rep undoc
+rep undoc
+rep xsha512
+rep xsha512
+rep xstore2
+rep xstore2
diff --git a/src/UnitTests/Intel/Formatter/Fast/Test32_Default.txt b/src/UnitTests/Intel/Formatter/Fast/Test32_Default.txt
@@ -729,3 +729,11 @@ rep ccs_hash
 rep ccs_hash
 rep ccs_encrypt
 rep ccs_encrypt
+rep undoc
+rep undoc
+rep undoc
+rep undoc
+rep xsha512
+rep xsha512
+rep xstore2
+rep xstore2
diff --git a/src/UnitTests/Intel/Formatter/Fast/Test32_Inverted.txt b/src/UnitTests/Intel/Formatter/Fast/Test32_Inverted.txt
@@ -729,3 +729,11 @@ rep ccs_hash
 rep ccs_hash
 rep ccs_encrypt
 rep ccs_encrypt
+rep undoc
+rep undoc
+rep undoc
+rep undoc
+rep xsha512
+rep xsha512
+rep xstore2
+rep xstore2
diff --git a/src/UnitTests/Intel/Formatter/Fast/Test64_Default.txt b/src/UnitTests/Intel/Formatter/Fast/Test64_Default.txt
@@ -13005,3 +13005,11 @@ vpsubrsetbd zmm2,k6,zmm19{bbbb}
 vpsubrsetbd zmm2,k6,zmm27{cccc}
 vpsubrsetbd zmm2,k6,zmm3{dddd}
 vpsubrsetbd zmm2,k6,zmm3
+rep undoc
+rep undoc
+rep undoc
+rep undoc
+rep xsha512
+rep xsha512
+rep xstore2
+rep xstore2
diff --git a/src/UnitTests/Intel/Formatter/Fast/Test64_Inverted.txt b/src/UnitTests/Intel/Formatter/Fast/Test64_Inverted.txt
@@ -13005,3 +13005,11 @@ vpsubrsetbd zmm2, k6, zmm19{bbbb}
 vpsubrsetbd zmm2, k6, zmm27{cccc}
 vpsubrsetbd zmm2, k6, zmm3{dddd}
 vpsubrsetbd zmm2, k6, zmm3
+rep undoc
+rep undoc
+rep undoc
+rep undoc
+rep xsha512
+rep xsha512
+rep xstore2
+rep xstore2
diff --git a/src/UnitTests/Intel/Formatter/Gas/OptionsResult.txt b/src/UnitTests/Intel/Formatter/Gas/OptionsResult.txt
@@ -2068,6 +2068,10 @@ rep xcryptcfb
 rep xcryptofb
 rep ccs_hash
 rep ccs_encrypt
+rep undoc
+rep undoc
+rep xsha512
+rep xstore2
 
 repne insb %dx,(%rdi)
 repne insw %dx,(%rdi)
@@ -2128,6 +2132,10 @@ rep xcryptcfb
 rep xcryptofb
 rep ccs_hash
 rep ccs_encrypt
+rep undoc
+rep undoc
+rep xsha512
+rep xstore2
 
 repne insb %dx,(%edi)
 repne insw %dx,(%edi)
@@ -2183,6 +2191,10 @@ rep xcryptcfb
 rep xcryptofb
 rep ccs_hash
 rep ccs_encrypt
+rep undoc
+rep undoc
+rep xsha512
+rep xstore2
 
 repne insb %dx,(%di)
 repne insw %dx,(%di)
@@ -2243,6 +2255,10 @@ rep xcryptcfb
 rep xcryptofb
 rep ccs_hash
 rep ccs_encrypt
+rep undoc
+rep undoc
+rep xsha512
+rep xstore2
 
 repne insb %dx,(%rdi)
 repne insw %dx,(%rdi)
@@ -2303,6 +2319,10 @@ rep xcryptcfb
 rep xcryptofb
 rep ccs_hash
 rep ccs_encrypt
+rep undoc
+rep undoc
+rep xsha512
+rep xstore2
 
 repne insb %dx,(%edi)
 repne insw %dx,(%edi)
@@ -2358,6 +2378,10 @@ rep xcryptcfb
 rep xcryptofb
 rep ccs_hash
 rep ccs_encrypt
+rep undoc
+rep undoc
+rep xsha512
+rep xstore2
 
 repne insb %dx,(%di)
 repne insw %dx,(%di)
@@ -2418,6 +2442,10 @@ rep xcryptcfb
 rep xcryptofb
 rep ccs_hash
 rep ccs_encrypt
+rep undoc
+rep undoc
+rep xsha512
+rep xstore2
 
 repne insb %dx,(%rdi)
 repne insw %dx,(%rdi)
@@ -2478,6 +2506,10 @@ rep xcryptcfb
 rep xcryptofb
 rep ccs_hash
 rep ccs_encrypt
+rep undoc
+rep undoc
+rep xsha512
+rep xstore2
 
 repne insb %dx,(%edi)
 repne insw %dx,(%edi)
@@ -2533,6 +2565,10 @@ rep xcryptcfb
 rep xcryptofb
 rep ccs_hash
 rep ccs_encrypt
+rep undoc
+rep undoc
+rep xsha512
+rep xstore2
 
 repne insb %dx,(%di)
 repne insw %dx,(%di)
@@ -2593,6 +2629,10 @@ rep xcryptcfb
 rep xcryptofb
 rep ccs_hash
 rep ccs_encrypt
+rep undoc
+rep undoc
+rep xsha512
+rep xstore2
 
 repnz insb %dx,(%rdi)
 repnz insw %dx,(%rdi)
@@ -2653,6 +2693,10 @@ rep xcryptcfb
 rep xcryptofb
 rep ccs_hash
 rep ccs_encrypt
+rep undoc
+rep undoc
+rep xsha512
+rep xstore2
 
 repnz insb %dx,(%edi)
 repnz insw %dx,(%edi)
@@ -2708,6 +2752,10 @@ rep xcryptcfb
 rep xcryptofb
 rep ccs_hash
 rep ccs_encrypt
+rep undoc
+rep undoc
+rep xsha512
+rep xstore2
 
 repnz insb %dx,(%di)
 repnz insw %dx,(%di)

diff --git a/src/UnitTests/Intel/Formatter/Gas/Test16_ForceSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test16_ForceSuffix.txt
@@ -518,3 +518,11 @@ addr32 pvalidate
 serialize
 xsusldtrk
 xresldtrk
+rep undoc
+addr32 rep undoc
+rep undoc
+addr32 rep undoc
+rep xsha512
+addr32 rep xsha512
+rep xstore2
+addr32 rep xstore2
diff --git a/src/UnitTests/Intel/Formatter/Gas/Test16_NoSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test16_NoSuffix.txt
@@ -518,3 +518,11 @@ addr32 pvalidate
 serialize
 xsusldtrk
 xresldtrk
+rep undoc
+addr32 rep undoc
+rep undoc
+addr32 rep undoc
+rep xsha512
+addr32 rep xsha512
+rep xstore2
+addr32 rep xstore2
diff --git a/src/UnitTests/Intel/Formatter/Gas/Test32_ForceSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test32_ForceSuffix.txt
@@ -729,3 +729,11 @@ rep ccs_hash
 addr16 rep ccs_hash
 rep ccs_encrypt
 addr16 rep ccs_encrypt
+addr16 rep undoc
+rep undoc
+addr16 rep undoc
+rep undoc
+addr16 rep xsha512
+rep xsha512
+addr16 rep xstore2
+rep xstore2
diff --git a/src/UnitTests/Intel/Formatter/Gas/Test32_NoSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test32_NoSuffix.txt
@@ -729,3 +729,11 @@ rep ccs_hash
 addr16 rep ccs_hash
 rep ccs_encrypt
 addr16 rep ccs_encrypt
+addr16 rep undoc
+rep undoc
+addr16 rep undoc
+rep undoc
+addr16 rep xsha512
+rep xsha512
+addr16 rep xstore2
+rep xstore2
diff --git a/src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt
@@ -13005,3 +13005,11 @@ vpsubrsetbd zmm19{bbbb}, k6, zmm2
 vpsubrsetbd zmm27{cccc}, k6, zmm2
 vpsubrsetbd zmm3{dddd}, k6, zmm2
 vpsubrsetbd zmm3, k6, zmm2
+addr32 rep undoc
+rep undoc
+addr32 rep undoc
+rep undoc
+addr32 rep xsha512
+rep xsha512
+addr32 rep xstore2
+rep xstore2
diff --git a/src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt b/src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt
@@ -13005,3 +13005,11 @@ vpsubrsetbd %zmm19{bbbb},%k6,%zmm2
 vpsubrsetbd %zmm27{cccc},%k6,%zmm2
 vpsubrsetbd %zmm3{dddd},%k6,%zmm2
 vpsubrsetbd %zmm3,%k6,%zmm2
+addr32 rep undoc
+rep undoc
+addr32 rep undoc
+rep undoc
+addr32 rep xsha512
+rep xsha512
+addr32 rep xstore2
+rep xstore2
diff --git a/src/UnitTests/Intel/Formatter/InstructionInfos16.txt b/src/UnitTests/Intel/Formatter/InstructionInfos16.txt
@@ -518,3 +518,11 @@ F2 0F 01 FF, Pvalidatew
 0F 01 E8, Serialize
 F2 0F 01 E8, Xsusldtrk
 F2 0F 01 E9, Xresldtrk
+F3 0FA6 F0, Via_undoc_F30FA6F0_16
+67 F3 0FA6 F0, Via_undoc_F30FA6F0_32
+F3 0FA6 F8, Via_undoc_F30FA6F8_16
+67 F3 0FA6 F8, Via_undoc_F30FA6F8_32
+F3 0FA6 E0, Xsha512_16
+67 F3 0FA6 E0, Xsha512_32
+F3 0FA7 F8, Xstore2_16
+67 F3 0FA7 F8, Xstore2_32
diff --git a/src/UnitTests/Intel/Formatter/InstructionInfos32.txt b/src/UnitTests/Intel/Formatter/InstructionInfos32.txt
@@ -644,7 +644,7 @@ F2 0F38F8 18, Enqcmd_r32_m512
 64 67 0F01 FC, Clzerow
 64 67 F3 0FAE F5, Umonitor_r16
 F3 0FA6 C0, Montmul_32
-67 F3 0FA6 C0, Montmul_16
+67 F3 0FA6 C0, Montmul_16, NoInvalidCheck
 F3 0FA6 C8, Xsha1_32
 67 F3 0FA6 C8, Xsha1_16
 F3 0FA6 D0, Xsha256_32
@@ -729,3 +729,11 @@ F3 0FA6 E8, Ccs_hash_32
 67 F3 0FA6 E8, Ccs_hash_16
 F3 0FA7 F0, Ccs_encrypt_32
 67 F3 0FA7 F0, Ccs_encrypt_16
+67 F3 0FA6 F0, Via_undoc_F30FA6F0_16
+F3 0FA6 F0, Via_undoc_F30FA6F0_32
+67 F3 0FA6 F8, Via_undoc_F30FA6F8_16
+F3 0FA6 F8, Via_undoc_F30FA6F8_32
+67 F3 0FA6 E0, Xsha512_16
+F3 0FA6 E0, Xsha512_32
+67 F3 0FA7 F8, Xstore2_16
+F3 0FA7 F8, Xstore2_32
diff --git a/src/UnitTests/Intel/Formatter/InstructionInfos64.txt b/src/UnitTests/Intel/Formatter/InstructionInfos64.txt
@@ -8260,7 +8260,7 @@ C4E3CD CF 10 A5, VEX_Vgf2p8affineinvqb_ymm_ymm_ymmm256_imm8
 64 0F01 FC, Clzeroq
 64 67 F3 0FAE F5, Umonitor_r32
 64 F3 0FAE F5, Umonitor_r64
-F3 0FA6 C0, Montmul_64
+F3 0FA6 C0, Montmul_64, NoInvalidCheck
 67 F3 0FA6 C0, Montmul_32
 F3 0FA6 C8, Xsha1_64
 67 F3 0FA6 C8, Xsha1_32
@@ -13005,3 +13005,11 @@ C4E379 3E D3 A5, VEX_KNC_Kextract_kr_r64_imm8, KNC
 62 924968 6F D3, MVEX_Vpsubrsetbd_zmm_k1_kr_zmmmt, KNC
 62 F24978 6F D3, MVEX_Vpsubrsetbd_zmm_k1_kr_zmmmt, KNC
 62 F24988 6F D3, MVEX_Vpsubrsetbd_zmm_k1_kr_zmmmt, KNC
+67 F3 0FA6 F0, Via_undoc_F30FA6F0_32
+F3 0FA6 F0, Via_undoc_F30FA6F0_64
+67 F3 0FA6 F8, Via_undoc_F30FA6F8_32
+F3 0FA6 F8, Via_undoc_F30FA6F8_64
+67 F3 0FA6 E0, Xsha512_32
+F3 0FA6 E0, Xsha512_64
+67 F3 0FA7 F8, Xstore2_32
+F3 0FA7 F8, Xstore2_64