1. Firmware synchronization 1.2.43

2. Due to the discontinuation of NXP SA612A, we started to produce compatible chip ZeeTK NE602A, but due to the different chip manufacturing process, there is a slight difference between the two in the use of harmonics, new compatible ZeeTK NE602A NanoVNA-H rev3.7 and NanoVNA-H4 rev4.4 version hardware schematic. Using the SJWCH5351 (formerly SMC5351 renamed) as a signal source, it can operate down to 600 Hz. New hardware improves port isolation below 300 MHz.
3. Upload a revised version of nanoVNAsharp to be compatible with the new firmware. nanoVNAsharp has no features to update.

FatFs/ff.c

@@ -623,6 +623,28 @@ static const BYTE DbcTbl[] = MKCVTBL(TBL_DC, FF_CODE_PAGE);
 #define  st_dword(ptr, val) *((uint32_t*)(ptr)) = ((uint32_t)(val))
 #define  st_qword(ptr, val) *((uint64_t*)(ptr)) = ((uint64_t)(val))
 
+#elif _WORD_ACCESS == 2
+// Compiler auto detect where need byte or word access optimisation
+struct __attribute__((packed)) T_UINT16 { uint16_t v; };
+struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+struct __attribute__((packed)) T_UINT64 { uint64_t v; };
+//	 Load a 2-byte little-endian word
+static WORD ld_word (const BYTE* ptr)   {return (((const struct T_UINT16 *)(const void *)(ptr))->v);}
+//   Load a 4-byte little-endian word
+static DWORD ld_dword (const BYTE* ptr) {return (((const struct T_UINT32 *)(const void *)(ptr))->v);}
+#if !FF_FS_READONLY
+//   Store a 2-byte word in little-endian
+static void st_word(BYTE* ptr, WORD val)   {(void)((((struct T_UINT16 *)(void *)(ptr))->v) = (val));}
+//   Store a 4-byte word in little-endian
+static void st_dword (BYTE* ptr, DWORD val){(void)((((struct T_UINT32 *)(void *)(ptr))->v) = (val));}
+#if FF_FS_EXFAT
+//   Load an 8-byte little-endian word
+static QWORD ld_qword (const BYTE* ptr) {return (((const struct T_UINT64 *)(const void *)(ptr))->v);}
+//   Store an 8-byte word in little-endian
+static void st_qword(BYTE* ptr, QWORD val) {(void)((((struct T_UINT64 *)(void *)(ptr))->v) = (val));}
+#endif
+#endif // FF_FS_READONLY
+
 #else
 
 static WORD ld_word (const BYTE* ptr)	/*	 Load a 2-byte little-endian word */

FatFs/ff.h

@@ -139,6 +139,7 @@ typedef struct {
 	BYTE	n_fats;			/* Number of FATs (1 or 2) */
 	BYTE	wflag;			/* win[] flag (b0:dirty) */
 	BYTE	fsi_flag;		/* FSINFO flags (b7:disabled, b0:dirty) */
+	BYTE    reserved;       /* align structure */
 	WORD	id;				/* Volume mount ID */
 	WORD	n_rootdir;		/* Number of root directory entries (FAT12/16) */
 	WORD	csize;			/* Cluster size [sectors] */
@@ -210,6 +211,7 @@ typedef struct {
 	FFOBJID	obj;			/* Object identifier (must be the 1st member to detect invalid object pointer) */
 	BYTE	flag;			/* File status flags */
 	BYTE	err;			/* Abort flag (error code) */
+	WORD    reserved;       /* align structure */
 	FSIZE_t	fptr;			/* File read/write pointer (Zeroed on file open) */
 	DWORD	clust;			/* Current cluster of fpter (invalid when fptr is 0) */
 	LBA_t	sect;			/* Sector number appearing in buf[] (0:invalid) */

FatFs/ffconf_072.h

@@ -297,12 +297,13 @@
 /  included somewhere in the scope of ff.h. */
 
 // STM32F0 processor (Cortex M0) not support read/write unaligned WORD or DWORD data
-#define _WORD_ACCESS	0	/* 0 or 1 */
+#define _WORD_ACCESS	0	/* 0 or 1 o 2 */
 /* The _WORD_ACCESS option is an only platform dependent option. It defines
 /  which access method is used to the word data on the FAT volume.
 /
 /   0: Byte-by-byte access. Always compatible with all platforms.
 /   1: Word access. Do not choose this unless under both the following conditions.
+/   2: Compiler auto detect where need byte or word access (use structures)
 /
 /  * Address misaligned memory access is always allowed for ALL instructions.
 /  * Byte order on the memory is little-endian.

FatFs/ffconf_303.h

@@ -297,12 +297,13 @@
 /  included somewhere in the scope of ff.h. */
 
 
-#define _WORD_ACCESS	1	/* 0 or 1 */
+#define _WORD_ACCESS	1	/* 0 or 1 o 2 */
 /* The _WORD_ACCESS option is an only platform dependent option. It defines
 /  which access method is used to the word data on the FAT volume.
 /
 /   0: Byte-by-byte access. Always compatible with all platforms.
 /   1: Word access. Do not choose this unless under both the following conditions.
+/   2: Compiler auto detect where need byte or word access (use structures)
 /
 /  * Address misaligned memory access is always allowed for ALL instructions.
 /  * Byte order on the memory is little-endian.

Makefile

@@ -45,7 +45,7 @@ endif
 
 # Enable this if you want link time optimizations (LTO)
 ifeq ($(USE_LTO),)
-  USE_LTO = no
+  USE_LTO = yes
 endif
 
 # If enabled, this option allows to compile the application in THUMB mode.
@@ -154,8 +154,13 @@ CSRC = $(STARTUPSRC) \
        $(STREAMSSRC) \
        FatFs/ff.c \
        FatFs/ffunicode.c \
+       fonts/numfont16x22.c \
+       fonts/Font5x7.c \
+       fonts/Font6x10.c \
+       fonts/Font7x11b.c \
+       fonts/Font11x14.c \
        usbcfg.c \
-       main.c si5351.c tlv320aic3204.c dsp.c plot.c ui.c ili9341.c numfont16x22.c Font5x7.c Font6x10.c Font7x11b.c Font11x14.c data_storage.c hardware.c vna_math.c
+       main.c common.c si5351.c tlv320aic3204.c dsp.c plot.c ui.c lcd.c data_storage.c hardware.c vna_math.c
 
 # C++ sources that can be compiled in ARM or THUMB mode depending on the global
 # setting.

NANOVNA_STM32_F072/exti_v1.c

@@ -72,6 +72,7 @@ OSAL_IRQ_HANDLER(Vector5C) {  // EXTI[4]...EXTI[15] interrupt handler
   uint32_t pr = EXTI->PR & ((1U << 4)  | (1U << 5)  | (1U << 6)  | (1U << 7)  | (1U << 8)  |
                             (1U << 9)  | (1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) |
                             (1U << 14) | (1U << 15));
+  EXTI->PR = pr;
 #ifdef EXT_CH4_HANDLER_FUNC
   if (pr & (1U << 4)) EXT_CH4_HANDLER_FUNC(4);
 #endif

NANOVNA_STM32_F072/i2c_v2.c

@@ -51,6 +51,7 @@ bool i2c_transfer(uint8_t addr, const uint8_t *w, size_t wn)
 // I2C TX and RX variant
 bool i2c_receive(uint8_t addr, const uint8_t *w, size_t wn, uint8_t *r, size_t rn)
 {
+  while(VNA_I2C->ISR & I2C_ISR_BUSY); // wait last transaction
   VNA_I2C->CR1|= I2C_CR1_PE;
   if (wn) {
     VNA_I2C->CR2 = (addr << I2C_CR2_SADD_7BIT_SHIFT) | (wn << I2C_CR2_NBYTES_SHIFT);

NANOVNA_STM32_F072/mcuconf.h

@@ -59,6 +59,8 @@
 
 // Define STM32_I2C1_CLOCK as 48MHz (STM32_I2C1SW is STM32_I2C1SW_SYSCLK)
 #define STM32_I2C1_CLOCK                    48
+// Core clock in MHz
+#define STM32_CORE_CLOCK                    48
 
 /*
  * RTC driver system settings for stm32f072

NANOVNA_STM32_F072/rtc_v2.c

@@ -149,7 +149,9 @@ void rtc_init(void){
   // If calendar has not been initialized yet then proceed with the initial setup.
   if ((RTC->ISR & RTC_ISR_INITS) == 0 || RTC->PRER != rtc_prer) {
     if (rtc_enter_init()){
-      RTC->CR   = 0;
+      RTC->CR   = 0
+//              | RTC_CR_COSEL    // RTC output 1Hz (or 512Hz if disabled)
+                 ;
       RTC->ISR  = RTC_ISR_INIT;     // Clearing all but RTC_ISR_INIT.
       RTC->PRER = rtc_prer;         // Prescaler value loaded in registers 2 times
       RTC->PRER = rtc_prer;
@@ -160,3 +162,17 @@ void rtc_init(void){
   else
     RTC->ISR &= ~RTC_ISR_RSF;
 }
+
+void rtc_set_cal(float ppm) {
+  int32_t cal = ppm * (1<<20) / 1000000.0f + 511.5f;
+  if ((RTC->ISR & RTC_ISR_RECALPF) || (uint32_t)cal > 1024)
+    return;
+  RTC->CALR = (511 - cal) & (RTC_CALR_CALP | RTC_CALR_CALM);
+}
+
+float rtc_get_cal(void) {
+  int32_t cal = -(RTC->CALR & RTC_CALR_CALM);
+  if (RTC->CALR & RTC_CALR_CALP)
+    cal += 512;
+  return cal * (1000000.0f / (1<<20));
+}

NANOVNA_STM32_F303/exti_v1.c

@@ -97,11 +97,11 @@ OSAL_IRQ_HANDLER(Vector68) {  // EXTI[4] interrupt handler.
 }
 #endif
 
-
 #if defined(EXT_CH5_HANDLER_FUNC) || defined(EXT_CH6_HANDLER_FUNC) || defined(EXT_CH7_HANDLER_FUNC) || \
     defined(EXT_CH8_HANDLER_FUNC) || defined(EXT_CH9_HANDLER_FUNC)
 OSAL_IRQ_HANDLER(Vector9C) {  // EXTI[5]...EXTI[9] interrupt handler
   uint32_t pr = EXTI->PR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9));
+  EXTI->PR = pr;
 #ifdef EXT_CH5_HANDLER_FUNC
   if (pr & (1U << 5)) EXT_CH5_HANDLER_FUNC(5);
 #endif
@@ -125,6 +125,7 @@ OSAL_IRQ_HANDLER(Vector9C) {  // EXTI[5]...EXTI[9] interrupt handler
 OSAL_IRQ_HANDLER(VectorE0) {  // EXTI[4]...EXTI[15] interrupt handler
   uint32_t pr = EXTI->PR & ((1U << 10) | (1U << 11) | (1U << 12) |
                             (1U << 13) | (1U << 14) | (1U << 15));
+  EXTI->PR = pr;
 #ifdef EXT_CH10_HANDLER_FUNC
   if (pr & (1U << 10)) EXT_CH10_HANDLER_FUNC(10);
 #endif

NANOVNA_STM32_F303/i2c_v2.c

@@ -51,6 +51,7 @@ bool i2c_transfer(uint8_t addr, const uint8_t *w, size_t wn)
 // I2C TX and RX variant
 bool i2c_receive(uint8_t addr, const uint8_t *w, size_t wn, uint8_t *r, size_t rn)
 {
+  while(VNA_I2C->ISR & I2C_ISR_BUSY); // wait last transaction
   VNA_I2C->CR1|= I2C_CR1_PE;
   if (wn) {
     VNA_I2C->CR2 = (addr << I2C_CR2_SADD_7BIT_SHIFT) | (wn << I2C_CR2_NBYTES_SHIFT);

NANOVNA_STM32_F303/mcuconf.h

@@ -64,6 +64,8 @@
 
 // Define STM32_I2C1_CLOCK as 72MHz (STM32_I2C1SW is STM32_I2C1SW_SYSCLK)
 #define STM32_I2C1_CLOCK                    72
+// Core clock in MHz
+#define STM32_CORE_CLOCK                    72
 
 /*
  * RTC driver system settings for stm32f303

NANOVNA_STM32_F303/rtc_v2.c

@@ -149,7 +149,9 @@ void rtc_init(void){
   // If calendar has not been initialized yet then proceed with the initial setup.
   if ((RTC->ISR & RTC_ISR_INITS) == 0 || RTC->PRER != rtc_prer) {
     if (rtc_enter_init()){
-      RTC->CR   = 0;
+      RTC->CR   = 0
+//              | RTC_CR_COSEL    // RTC output 1Hz (or 512Hz if disabled)
+                 ;
       RTC->ISR  = RTC_ISR_INIT;     // Clearing all but RTC_ISR_INIT.
       RTC->PRER = rtc_prer;         // Prescaler value loaded in registers 2 times
       RTC->PRER = rtc_prer;
@@ -160,3 +162,17 @@ void rtc_init(void){
   else
     RTC->ISR &= ~RTC_ISR_RSF;
 }
+
+void rtc_set_cal(float ppm) {
+  int32_t cal = ppm * (1<<20) / 1000000.0f + 511.5f;
+  if ((RTC->ISR & RTC_ISR_RECALPF) || (uint32_t)cal > 1024)
+    return;
+  RTC->CALR = ((511 - cal) & (RTC_CALR_CALP | RTC_CALR_CALM));
+}
+
+float rtc_get_cal(void) {
+  int32_t cal = -(RTC->CALR & RTC_CALR_CALM);
+  if (RTC->CALR & RTC_CALR_CALP)
+    cal += 512;
+  return cal * (1000000.0f / (1<<20));
+}