v0.13.1

Fixed

• Design elaboration for cell placement

v0.13.0

Added

• Initial work on cell placement
• spice parser support for subckt instances

v0.12.2

Added

• Examples

Fixed

• Composition analysis
• #42

v0.12.1

Fixed

• Functionality to determine whether two nodes are composed in parallel/choice/sequence in the net

v0.12.0

Added

• Cog programming language for a simpler user interface

Changed

• various internal fixes and improvements to generalizability in preparation for state variable insertion

v0.11.2

Fixed

• Cross platform support for macos and windows
• Installation flow

v0.11.1

Added

• Ghosts that annotate how transitions on a given conditional branch propagate into the rest of the state space
• Python is now loaded dynamically on demand with support for all versions of python3

Changed

• Cleaned up debug messages and hooked up the debug flag as needed

v0.11.0

Added

• extremely simple PN ratio computation
• parasitics data in the technology file

Changed

• rearch of technology file substrate and model specifications

Fixed

• #4

v0.10.3

Fixed

• route lowering bug
• group constraints bug
• stack linkage bug
• multiple transistor models in one stack
• gate separation bug
• well label bug
• polygons in GDS import

Changed

• min width rule now a full DRC rule

Added

• cell import (still some bugs)
• tech directory management

v0.10.2

2564 of 2680 cells (95.7%) from the skywater cell library are now DRC and LVS clean.
22 minutes and 55 seconds to complete the run (0.5s per cell).

Fixed

• cleaning up virtual pin placement
• adding gate alignment metric into placer
• make cell hashing algorithm sensitive to full cell structure
• diffusion base net
• route draw to pin
• pin positioning
• route lo/hi setting
• gate extraction
• lock pin constraints