forked from verilator/verilator
-
Notifications
You must be signed in to change notification settings - Fork 3
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Support basic dist constraints (verilator#5431)
- Loading branch information
Showing
8 changed files
with
188 additions
and
42 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,21 @@ | ||
| #!/usr/bin/env python3 | ||
| # DESCRIPTION: Verilator: Verilog Test driver/expect definition | ||
| # | ||
| # Copyright 2024 by Wilson Snyder. This program is free software; you | ||
| # can redistribute it and/or modify it under the terms of either the GNU | ||
| # Lesser General Public License Version 3 or the Perl Artistic License | ||
| # Version 2.0. | ||
| # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 | ||
|
|
||
| import vltest_bootstrap | ||
|
|
||
| test.scenarios('simulator') | ||
|
|
||
| if not test.have_solver: | ||
| test.skip("No constraint solver installed") | ||
|
|
||
| test.compile(verilator_flags2=['-Wno-CONSTRAINTIGN']) | ||
|
|
||
| test.execute() | ||
|
|
||
| test.passes() |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,39 @@ | ||
| // DESCRIPTION: Verilator: Verilog Test module | ||
| // | ||
| // This file ONLY is placed under the Creative Commons Public Domain, for | ||
| // any use, without warranty, 2024 by Antmicro Ltd. | ||
| // SPDX-License-Identifier: CC0-1.0 | ||
|
|
||
| `define check_rand(cl, field, cond) \ | ||
| begin \ | ||
| longint prev_result; \ | ||
| int ok = 0; \ | ||
| for (int i = 0; i < 10; i++) begin \ | ||
| longint result; \ | ||
| if (!bit'(cl.randomize())) $stop; \ | ||
| result = longint'(field); \ | ||
| if (!(cond)) $stop; \ | ||
| if (i > 0 && result != prev_result) ok = 1; \ | ||
| prev_result = result; \ | ||
| end \ | ||
| if (ok != 1) $stop; \ | ||
| end | ||
|
|
||
| class C; | ||
| rand int x, y; | ||
| constraint distrib { | ||
| x dist { [1:3] := 0, [5:6], [9:15] :/ 0 }; | ||
| y dist { [1:3] := 0, 5, 6 := 8, [9:15] :/ 0 }; | ||
| x < 20; | ||
| }; | ||
| endclass | ||
|
|
||
| module t; | ||
| initial begin | ||
| C c = new; | ||
| `check_rand(c, c.x, 5 <= c.x && c.x <= 6); | ||
| `check_rand(c, c.y, 5 <= c.y && c.y <= 6); | ||
| $write("*-* All Finished *-*\n"); | ||
| $finish; | ||
| end | ||
| endmodule |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,17 @@ | ||
| %Warning-CONSTRAINTIGN: t/t_constraint_dist_unsup.v:27:10: Constraint expression ignored (imperfect distribution) | ||
| : ... note: In instance 't' | ||
| 27 | x dist {que}; | ||
| | ^~~~ | ||
| ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest | ||
| ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. | ||
| %Warning-CONSTRAINTIGN: t/t_constraint_dist_unsup.v:28:10: Constraint expression ignored (imperfect distribution) | ||
| : ... note: In instance 't' | ||
| 28 | y dist {arr}; | ||
| | ^~~~ | ||
| %Warning-CONSTRAINTIGN: t/t_constraint_dist_unsup.v:27:10: Unsupported: randomizing this expression, treating as state | ||
| 27 | x dist {que}; | ||
| | ^~~~ | ||
| %Warning-CONSTRAINTIGN: t/t_constraint_dist_unsup.v:28:10: Unsupported: randomizing this expression, treating as state | ||
| 28 | y dist {arr}; | ||
| | ^~~~ | ||
| %Error: Exiting due to |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,16 @@ | ||
| #!/usr/bin/env python3 | ||
| # DESCRIPTION: Verilator: Verilog Test driver/expect definition | ||
| # | ||
| # Copyright 2024 by Wilson Snyder. This program is free software; you can | ||
| # redistribute it and/or modify it under the terms of either the GNU | ||
| # Lesser General Public License Version 3 or the Perl Artistic License | ||
| # Version 2.0. | ||
| # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 | ||
|
|
||
| import vltest_bootstrap | ||
|
|
||
| test.scenarios('linter') | ||
|
|
||
| test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) | ||
|
|
||
| test.passes() |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,40 @@ | ||
| // DESCRIPTION: Verilator: Verilog Test module | ||
| // | ||
| // This file ONLY is placed under the Creative Commons Public Domain, for | ||
| // any use, without warranty, 2024 by Antmicro Ltd. | ||
| // SPDX-License-Identifier: CC0-1.0 | ||
|
|
||
| `define check_rand(cl, field, cond) \ | ||
| begin \ | ||
| longint prev_result; \ | ||
| int ok = 0; \ | ||
| for (int i = 0; i < 10; i++) begin \ | ||
| longint result; \ | ||
| if (!bit'(cl.randomize())) $stop; \ | ||
| result = longint'(field); \ | ||
| if (!(cond)) $stop; \ | ||
| if (i > 0 && result != prev_result) ok = 1; \ | ||
| prev_result = result; \ | ||
| end \ | ||
| if (ok != 1) $stop; \ | ||
| end | ||
|
|
||
| class C; | ||
| int que[$] = '{3, 4, 5}; | ||
| int arr[3] = '{5, 6, 7}; | ||
| rand int x, y; | ||
| constraint distrib { | ||
| x dist {que}; | ||
| y dist {arr}; | ||
| }; | ||
| endclass | ||
|
|
||
| module t; | ||
| initial begin | ||
| C c = new; | ||
| `check_rand(c, c.x, 3 <= c.x && c.x <= 5); | ||
| `check_rand(c, c.y, 5 <= c.y && c.y <= 7); | ||
| $write("*-* All Finished *-*\n"); | ||
| $finish; | ||
| end | ||
| endmodule |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters