Releases · antmicro/topwrap

Changes:

Conversion of HDL sources into YAML IP core description files
- Verilog and VHDL support
- Interface recognition: AXI, AXI-Lite, AXI Stream, Wishbone
- YAML-based description format for command-line use
Design Assembly
- Ability to assemble top-level designs from IP cores
- Compliance checks for predefined interfaces
- Generation of FuseSoC .core files
- Use of Amaranth HDL for final top-level generation
GUI
- Graphical interface powered by Kenning Pipeline Manager
- Drag-and-drop functionality for creating and connecting cores
- Visualization of hierarchical designs
- Validation and building of designs to identify potential issues
- Conversion from YAML IP core/design to KPM specification/dataflow
User Repository
- Creation of custom libraries for reuse across projects
- Dedicated directories for each core with its HDL and parsed IP core
- Support for multiple HDL sources within a single repository entry
- Built-in interface definitions
- Automatic loading of IP core YAMLs from the user repositories
Documentation
- User documentation with examples and live previews
- Developer's guide covering advanced topics and contribution guidelines

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