OFS d5005 2023.2-1 snapshot

.gitattributes

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+*.png filter=lfs diff=lfs merge=lfs -text
+*.PNG filter=lfs diff=lfs merge=lfs -text
+*.ai filter=lfs diff=lfs merge=lfs -text
+*.pdf filter=lfs diff=lfs merge=lfs -text

.gitmodules

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+[submodule "ofs-common"]
+	url = https://github.com/OFS/ofs-fim-common.git
+	path = ofs-common

LICENSE.txt

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+Copyright (c) 2022 Intel Corporation 
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

README.md

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+# D5005 FPGA Development Directory
+
+This is the OFS D5005 Stratix 10 FPGA development top-level directory.
+
+## Cloning this repository
+
+*NOTE:* This repository uses [Git LFS](https://git-lfs.com/) to capture large files in the history without forcing the download of historic files during a plain `clone` operation. Please follow your preferred installation method [from the project's guide](https://github.com/git-lfs/git-lfs#installing) before proceeding. After installation, run `git lfs install` once to install hooks which will transparently fetch the large files into your workspace for use.
+
+To fetch both the `FIM` and `ofs-common` files in a single step, run the following command:
+
+   `git clone --recurse-submodules https://github.com/OFS/ofs-d5005.git`
+
+## Directories
+
+### Evaluation Scripts (***eval\_scripts***)
+   - Contains resources to report and setup D5005 development environment.
+### External Tools (***external***)
+   - Contains the software repositories needed for OFS/OPAE development and integration. 
+   - Lightweight virtual environment containing the required Python packages needed for this repo and its tools.
+### IP Subsystems (***ipss***)
+   - Contains the code and supporting files that define or set up the IP subsystems contained in the D5005 FPGA Interface Manager (FIM)
+### Licensing for Quartus (***license***)
+   - Contains the license setup software for the version of Quartus used for this distribution/release of the D5005 product.
+### OFS Common Content Directory (**Link to top-level directory _ofs-common_**)
+   - Contains the scripts, source code, and verification environment resources that are common to all of the repositories.
+   - This directory is referenced via a link within each of the FPGA-Specific repositories.
+### Simulation
+   - Contains the testbenches and supporting code for all of the unit test simulations.
+      - Bus Functional Model code is contained here.
+      - Scripts are included for automating a myriad of tasks.
+      - All of the individual unit tests and their supporting code is also located here.
+### FPGA Interface Module (FIM) Source code (***src***)
+   - This directory contains all of the structural and behavioral code for the FIM.
+   - Also included are scripts for generating the AXI buses for module interconnect.
+   - Top-level RTL for synthesis is located in this directory.
+   - Accelerated Functional Unit (AFU) infrastructure code is contained in this directory.
+### FPGA Synthesis
+   - This directory contains all of the scripts, settings, and setup files for running synthesis on the FIM.
+### Verification (UVM) (***verification***)
+   - This directory contains all of the scripts, testbenches, and test cases for the supported UVM tests for the D5005 FIM.
+   - **NOTE:** UVM resources are currently not available in this release due to difficulties in open-sourcing some components.  It is hoped that this will be included in future releases.

SECURITY.md

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+# Security Policy
+Intel is committed to rapidly addressing security vulnerabilities affecting our customers and providing clear guidance on the solution, impact, severity and mitigation.
+
+## Reporting a Vulnerability
+Please report any security vulnerabilities in this project [utilizing the guidelines here](https://www.intel.com/content/www/us/en/security-center/vulnerability-handling-guidelines.html).
+

ipss/.gitignore

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+*.bsf
+*.cmp
+*.csv
+*.html
+*.qgsimc
+*.qgsynthc
+*.sopcinfo
+*.xml
+*_bb.v
+*.rpt
+*_inst.v
+*_inst.vhd
+*.BAK.ip
+.qsys_edit
+aldec
+cadence
+ncsim_files.tcl
+riviera_files.tcl
+xcelium_files.tcl
+xcelium

ipss/README.md

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+# D5005 IP Subsystem Directory
+
+This directory contains the code and supporting files that define or set up the IP subsystems contained in the D5005 FPGA Interface Manager (FIM)
+
+## Directories
+
+### High Speed Serial Interface (HSSI) Ethernet (***hssi***)
+   - This directory contains the top-level description of the HSSI block and all of its supporting code.
+
+### DDR4 Memory (***mem***)
+   - This directory contains the top-level description of the DDR4 subsystem.
+   - This directory also contains a lot of the settings regarding the physical interface management and PHY settings.
+
+### Peripheral Component Interconnect Express (PCIe) Interface (***pcie***)
+   - This directory contains the top-level description of the system's Peripheral Component Interconnect Express (PCIe) interface.
+   - This is the main connection between the D5005 card and the host computer system.
+
+### Platform Management Interface Controller (PMCI) (***pmci***)
+   - This directory contains the top-level RTL block that connects one of the FPGA's AXI-Lite interfaces to its system controller via a SPI Bridge.
+
+### Serial Peripheral Interconnect (SPI) (***spi***)
+   - This directory contains the top-level RTL for the SPI bridge.
+   - A set of Control and Status Registers (CSRs) are also defined here.
+      - The RTL defining these registers and their function is included here.
+      - An Excel spreadsheet is also contained here that provides a better human-readable format describing the CSRs and their intended function.

ipss/hssi/inc/ofs_fim_eth_avst_if.sv

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+// Copyright 2020 Intel Corporation
+// SPDX-License-Identifier: MIT
+
+//-----------------------------------------------------------------------------
+// Description
+//-----------------------------------------------------------------------------
+//
+// Avalon stream wrappers around the same payloads as the Ethernet AXI
+// streams in ofs_fim_eth_if.sv. While AXI-S is used as the transport
+// from the MAC to the AFU across the PR boundary, AFUs may be written
+// using Avalon interfaces. The Platform Interface Manager provides a shim
+// for mapping between the two protocols.
+//
+//-----------------------------------------------------------------------------
+
+// Interface of Eth RX AVST channel (MAC -> AFU)
+interface ofs_fim_eth_rx_avst_if ();
+   logic clk;
+   logic rst_n; // Active-low reset
+
+   import ofs_fim_eth_avst_if_pkg::*;
+
+   t_avst_eth_rx rx;
+
+   // Ready signal
+   logic ready;
+
+   // AVST channel master (MAC side)
+   modport master (
+        input  ready,
+        output clk,
+        output rst_n,
+        output rx
+   );
+
+   // AVST channel slave
+   modport slave (
+        output ready,
+        input  clk,
+        input  rst_n,
+        input  rx
+   );
+
+endinterface : ofs_fim_eth_rx_avst_if
+
+
+// Interface of Eth TX AVST channel (MAC -> AFU)
+interface ofs_fim_eth_tx_avst_if ();
+   logic clk;
+   logic rst_n; // Active-low reset
+
+   import ofs_fim_eth_avst_if_pkg::*;
+
+   t_avst_eth_tx tx;
+
+   // Ready signal
+   logic ready;
+
+   // AVST channel master (MAC side)
+   modport master (
+        input  ready,
+        input  clk,
+        input  rst_n,
+        output tx
+   );
+
+   // AVST channel slave
+   modport slave (
+        output ready,
+        output clk,
+        output rst_n,
+        input  tx
+   );
+
+endinterface : ofs_fim_eth_tx_avst_if
+
+
+//
+// RX Interface of Eth sideband AVST channel (MAC -> AFU).
+//
+// There is no tready flow control on this interface. The payload may be
+// time-sensitive.
+//
+interface ofs_fim_eth_sideband_rx_avst_if ();
+   logic clk;
+   logic rst_n; // Active-low reset
+
+   import ofs_fim_eth_avst_if_pkg::*;
+
+   t_avst_eth_sideband_rx sb;
+
+   // AVST channel master (MAC side)
+   modport master (
+        output clk,
+        output rst_n,
+        output sb
+   );
+
+   // AVST channel slave
+   modport slave (
+        input  clk,
+        input  rst_n,
+        input  sb
+   );
+
+endinterface : ofs_fim_eth_sideband_rx_avst_if
+
+
+//
+// Tx Interface of Eth sideband AVST channel (AFU -> MAC)
+//
+// There is no tready flow control on this interface. The payload may be
+// time-sensitive.
+//
+interface ofs_fim_eth_sideband_tx_avst_if ();
+   logic clk;
+   logic rst_n; // Active-low reset
+
+   import ofs_fim_eth_avst_if_pkg::*;
+
+   t_avst_eth_sideband_tx sb;
+
+   // AVST channel master
+   modport master (
+        input  clk,
+        input  rst_n,
+        output sb
+   );
+
+   // AVST channel slave (MAC side)
+   modport slave (
+        output clk,
+        output rst_n,
+        input  sb
+   );
+
+endinterface : ofs_fim_eth_sideband_tx_avst_if

ipss/hssi/inc/ofs_fim_eth_avst_if_pkg.sv

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+// Copyright 2020 Intel Corporation
+// SPDX-License-Identifier: MIT
+
+// Description
+//-----------------------------------------------------------------------------
+//
+//  AVST equivalent of the AXI-S Ethernet interface data structures. Types
+//  are derived from the AXI-S configuration.
+//
+//----------------------------------------------------------------------------
+
+package ofs_fim_eth_avst_if_pkg;
+
+localparam MAX_NUM_AVST_ETH_CHANNELS = ofs_fim_eth_plat_if_pkg::MAX_NUM_ETH_CHANNELS;
+localparam NUM_AVST_ETH_CHANNELS     = ofs_fim_eth_plat_if_pkg::NUM_ETH_CHANNELS;
+
+localparam AVST_ETH_PACKET_WIDTH = ofs_fim_eth_plat_if_pkg::ETH_PACKET_WIDTH;
+// Unlike AXI-S "tkeep", which is a mask, "empty" is a count of the number
+// of unused bytes at the end of "data".
+localparam AVST_ETH_EMPTY_WIDTH = $clog2(AVST_ETH_PACKET_WIDTH/8);
+
+localparam AVST_ETH_RX_ERROR_WIDTH = ofs_fim_eth_plat_if_pkg::ETH_RX_ERROR_WIDTH;
+localparam AVST_ETH_TX_ERROR_WIDTH = ofs_fim_eth_plat_if_pkg::ETH_TX_ERROR_WIDTH;
+
+// Clocks exported by the MAC for use by the AFU. The primary "clk" is
+// guaranteed. Others are platform-specific.
+typedef ofs_fim_eth_plat_if_pkg::t_eth_clocks t_avst_eth_clocks;
+
+typedef ofs_fim_eth_plat_if_pkg::t_axis_eth_rx_tuser t_avst_eth_rx_user;
+typedef ofs_fim_eth_plat_if_pkg::t_axis_eth_tx_tuser t_avst_eth_tx_user;
+
+// AVST RX channel (MAC -> AFU)
+typedef struct packed {
+   logic                             valid;
+   logic                             sop;
+   logic                             eop;
+   logic [AVST_ETH_PACKET_WIDTH-1:0] data;
+   logic [AVST_ETH_EMPTY_WIDTH-1:0]  empty;
+   t_avst_eth_rx_user                user;
+} t_avst_eth_rx;
+localparam AVST_ETH_RX_WIDTH = $bits(t_avst_eth_rx);
+
+// AVST TX channel (AFU -> MAC)
+typedef struct packed {
+   logic                             valid;
+   logic                             sop;
+   logic                             eop;
+   logic [AVST_ETH_PACKET_WIDTH-1:0] data;
+   logic [AVST_ETH_EMPTY_WIDTH-1:0]  empty;
+   t_avst_eth_tx_user                user;
+} t_avst_eth_tx;
+localparam AVST_ETH_TX_WIDTH = $bits(t_avst_eth_tx);
+
+// AVST sideband RX channel (MAC -> AFU)
+typedef ofs_fim_eth_plat_if_pkg::t_eth_sideband_from_mac t_eth_sideband_from_mac;
+localparam AVST_ETH_SIDEBAND_RX_PACKET_WIDTH = $bits(t_eth_sideband_from_mac);
+
+typedef struct packed {
+   logic                   valid;
+   t_eth_sideband_from_mac data;
+} t_avst_eth_sideband_rx;
+
+// AVST sideband TX channel (AFU -> MAC)
+typedef ofs_fim_eth_plat_if_pkg::t_eth_sideband_to_mac t_eth_sideband_to_mac;
+localparam AVST_ETH_SIDEBAND_TX_PACKET_WIDTH = $bits(t_eth_sideband_to_mac);
+
+typedef struct packed {
+   logic                   valid;
+   t_eth_sideband_to_mac   data;
+} t_avst_eth_sideband_tx;
+
+
+// Convert an AXI-S data payload to an AVST payload. The two use opposite byte
+// order.
+function automatic logic [AVST_ETH_PACKET_WIDTH-1:0] eth_axi_to_avst_data(logic [AVST_ETH_PACKET_WIDTH-1:0] i_data);
+   logic [AVST_ETH_PACKET_WIDTH-1:0] o_data;
+
+   for (int b = 0; b < AVST_ETH_PACKET_WIDTH/8; b = b + 1) begin
+      o_data[8 * (AVST_ETH_PACKET_WIDTH/8 - 1 - b) +: 8] = i_data[8 * b +: 8];
+   end
+
+   return o_data;
+endfunction
+
+// Convert an AVST data payload to an AXI-S payload.
+function automatic logic [AVST_ETH_PACKET_WIDTH-1:0] eth_avst_to_axi_data(logic [AVST_ETH_PACKET_WIDTH-1:0] i_data);
+   // Reversing is the same operation in both directions
+   return eth_axi_to_avst_data(i_data);
+endfunction
+
+
+// Convert an AXI-S tkeep mask to an AVST empty. Empty is the count of unused
+// bytes at the end of data. Tkeep is a byte mask. The MAC uses the empty encoding,
+// so only the highest group of 0's in tkeep can act as a mask.
+function automatic logic [AVST_ETH_EMPTY_WIDTH-1:0] eth_tkeep_to_empty(logic [ofs_fim_eth_if_pkg::ETH_TKEEP_WIDTH-1:0] tkeep);
+   logic [AVST_ETH_EMPTY_WIDTH-1:0] num_empty = 0;
+
+   for (int b = ofs_fim_eth_if_pkg::ETH_TKEEP_WIDTH-1; b >= 0; b = b - 1) begin
+      if (tkeep[b]) break;
+      num_empty = num_empty + 1;
+   end
+
+   return num_empty;
+endfunction // eth_tkeep_to_empty
+
+// Reverse of eth_tkeep_to_empty above
+function automatic logic [ofs_fim_eth_if_pkg::ETH_TKEEP_WIDTH-1:0] eth_empty_to_tkeep(logic [AVST_ETH_EMPTY_WIDTH-1:0] empty);
+   return {ofs_fim_eth_if_pkg::ETH_TKEEP_WIDTH{1'b1}} >> empty;
+endfunction // eth_tkeep_to_empty
+
+endpackage