Date in version variable updated.

config-nstorm-bananapi-bpi-r4

@@ -767,7 +767,7 @@ CONFIG_USE_LTO=y
 CONFIG_USE_MOLD=y
 CONFIG_VERSIONOPT=y
 CONFIG_VERSION_BUG_URL=""
-CONFIG_VERSION_CODE="20241205-r43-nvme16"
+CONFIG_VERSION_CODE="20241215-r43-nvme16"
 CONFIG_VERSION_CODE_FILENAMES=y
 CONFIG_VERSION_DIST="OpenWrt"
 CONFIG_VERSION_FILENAMES=y

target/linux/mediatek/patches-6.6/999-3001-mtk-wed-add-dma-mask-limitation-and-GFP_DMA32-for-bo.patch

@@ -0,0 +1,40 @@
+From d8ad903337b79bc32ae138bf9ef04f31613e4bf2 Mon Sep 17 00:00:00 2001
+From: Rex Lu <rex.lu@mediatek.com>
+Date: Mon, 21 Oct 2024 12:37:18 +0800
+Subject: [PATCH] mtk: wed: add dma mask limitation and GFP_DMA32 for board >=
+ 4GB dram
+
+---
+ drivers/net/ethernet/mediatek/mtk_wed.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -670,7 +670,7 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_d
+ 		void *buf;
+ 		int s;
+
+-		page = __dev_alloc_page(GFP_KERNEL);
++		page = __dev_alloc_pages(GFP_KERNEL | GFP_DMA32, 0);
+ 		if (!page)
+ 			return -ENOMEM;
+
+@@ -793,7 +793,7 @@ mtk_wed_hwrro_buffer_alloc(struct mtk_we
+ 		struct page *page;
+ 		int s;
+
+-		page = __dev_alloc_page(GFP_KERNEL);
++		page = __dev_alloc_pages(GFP_KERNEL | GFP_DMA32, 0);
+ 		if (!page)
+ 			return -ENOMEM;
+
+@@ -2435,6 +2435,9 @@ mtk_wed_attach(struct mtk_wed_device *de
+ 	dev->wdma_idx = hw->index;
+ 	dev->version = hw->version;
+ 	dev->hw->pcie_base = mtk_wed_get_pcie_base(dev);
++	ret = dma_set_mask_and_coherent(hw->dev, DMA_BIT_MASK(32));
++	if (ret)
++		return ret;
+
+ 	if (hw->eth->dma_dev == hw->eth->dev &&
+ 	    of_dma_is_coherent(hw->eth->dev->of_node))

target/linux/mediatek/patches-6.6/999-3002-fix-SER-case-call-trace-due-to-double-free-hwrro-buf.patch

@@ -0,0 +1,19 @@
+From cd4c463856af91231164f8731e9726aa2f831242 Mon Sep 17 00:00:00 2001
+From: Rex Lu <rex.lu@mediatek.com>
+Date: Fri, 27 Sep 2024 13:46:33 +0800
+Subject: [PATCH 1/6] fix SER case call trace due to double free hwrro buffer
+
+---
+ drivers/net/ethernet/mediatek/mtk_wed.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -1735,7 +1735,6 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+ 				   false);
+ 	}
+ 	mtk_wed_free_rx_buffer(dev);
+-	mtk_wed_hwrro_free_buffer(dev);
+
+ 	return 0;
+ }

target/linux/mediatek/patches-6.6/999-3003-refactor-mtk_wed_assgin-not-base-on-pci-domain.patch

@@ -0,0 +1,64 @@
+From 73c2090956a1aac2314c6003c35f958dfd0f3a8f Mon Sep 17 00:00:00 2001
+From: Rex Lu <rex.lu@mediatek.com>
+Date: Fri, 27 Sep 2024 14:17:12 +0800
+Subject: [PATCH 2/6] refactor mtk_wed_assgin not base on pci domain
+
+---
+ drivers/net/ethernet/mediatek/mtk_wed.c | 31 +++++++------------------
+ 1 file changed, 8 insertions(+), 23 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -488,34 +488,21 @@ void mtk_wed_fe_reset_complete(void)
+ static struct mtk_wed_hw *
+ mtk_wed_assign(struct mtk_wed_device *dev)
+ {
+-	struct mtk_wed_hw *hw;
+ 	int i;
+
+-	if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) {
+-		hw = hw_list[pci_domain_nr(dev->wlan.pci_dev->bus)];
+-		if (!hw)
+-			return NULL;
++	for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
++		struct mtk_wed_hw *hw = hw_list[i];
+
+-		if (!hw->wed_dev)
+-			goto out;
++		if (!hw || hw->wed_dev)
++			continue;
+
+-		if (mtk_wed_is_v1(hw))
+-			return NULL;
++		hw->wed_dev = dev;
++		hw->pcie_base = MTK_WED_PCIE_BASE;
+
+-		/* MT7986 WED devices do not have any pcie slot restrictions */
+-	}
+-	/* MT7986 PCIE or AXI */
+-	for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
+-		hw = hw_list[i];
+-		if (hw && !hw->wed_dev)
+-			goto out;
++		return hw;
+ 	}
+
+ 	return NULL;
+-
+-out:
+-	hw->wed_dev = dev;
+-	return hw;
+ }
+
+ static int
+@@ -2403,9 +2390,7 @@ mtk_wed_attach(struct mtk_wed_device *de
+ 	RCU_LOCKDEP_WARN(!rcu_read_lock_held(),
+ 			 "mtk_wed_attach without holding the RCU read lock");
+
+-	if ((dev->wlan.bus_type == MTK_WED_BUS_PCIE &&
+-	     pci_domain_nr(dev->wlan.pci_dev->bus) > 1) ||
+-	    !try_module_get(THIS_MODULE))
++	if (!try_module_get(THIS_MODULE))
+ 		ret = -ENODEV;
+
+ 	rcu_read_unlock();

target/linux/mediatek/patches-6.6/999-3004-fix-wdma-rx-hang-on-wed1-after-SER.patch

@@ -0,0 +1,42 @@
+From c52a1e697f0bd2bd1ceb82140cb73a0887c6224b Mon Sep 17 00:00:00 2001
+From: Rex Lu <rex.lu@mediatek.com>
+Date: Fri, 27 Sep 2024 16:58:22 +0800
+Subject: [PATCH 3/6] fix wdma rx hang on wed1 after SER
+
+---
+ drivers/net/ethernet/mediatek/mtk_wed.c | 17 ++++++++++++++++-
+ 1 file changed, 16 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -250,7 +250,7 @@ mtk_wdma_rx_reset(struct mtk_wed_device
+ 	wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
+
+ 	for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++) {
+-		if (dev->rx_wdma[i].desc)
++		if (!dev->rx_wdma[i].desc)
+ 			continue;
+
+ 		wdma_w32(dev,
+@@ -1785,6 +1785,21 @@ mtk_wed_reset_dma(struct mtk_wed_device
+ 			wed_clr(dev, MTK_WED_WDMA_RX_PREF_CFG,
+ 				MTK_WED_WDMA_RX_PREF_DDONE2_EN);
+
++			/* Reset prefetch index */
++			wed_set(dev, MTK_WED_WDMA_RX_PREF_CFG,
++				MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR |
++				MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR);
++
++			wed_clr(dev, MTK_WED_WDMA_RX_PREF_CFG,
++				MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR |
++				MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR);
++
++			/* Reset prefetch FIFO */
++			wed_w32(dev, MTK_WED_WDMA_RX_PREF_FIFO_CFG,
++				MTK_WED_WDMA_RX_PREF_FIFO_RX0_CLR |
++				MTK_WED_WDMA_RX_PREF_FIFO_RX1_CLR);
++			wed_w32(dev, MTK_WED_WDMA_RX_PREF_FIFO_CFG, 0);
++
+ 			/* 2. Reset dma index */
+ 			wed_w32(dev, MTK_WED_WDMA_RESET_IDX,
+ 				MTK_WED_WDMA_RESET_IDX_RX_ALL);

target/linux/mediatek/patches-6.6/999-3005-Fix-reinsert-wifi-module-cause-memory-leak-issue.patch

@@ -0,0 +1,69 @@
+From d83af8f83169ec2ebef82af5d8cad95dc27ce455 Mon Sep 17 00:00:00 2001
+From: Rex Lu <rex.lu@mediatek.com>
+Date: Tue, 1 Oct 2024 14:07:22 +0800
+Subject: [PATCH 4/6] Fix reinsert wifi module cause memory leak issue
+
+---
+ drivers/net/ethernet/mediatek/mtk_wed.c | 22 ++++++++++++++++++++--
+ 1 file changed, 20 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -929,6 +929,16 @@ mtk_wed_free_ring(struct mtk_wed_device
+ static void
+ mtk_wed_free_rx_rings(struct mtk_wed_device *dev)
+ {
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(dev->rx_ring); i++)
++		if ((dev->tx_ring[i].flags & MTK_WED_RING_CONFIGURED))
++			mtk_wed_free_ring(dev, &dev->rx_ring[i]);
++
++	for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
++		if ((dev->tx_wdma[i].flags & MTK_WED_RING_CONFIGURED))
++			mtk_wed_free_ring(dev, &dev->tx_wdma[i]);
++
+ 	mtk_wed_free_rx_buffer(dev);
+ 	mtk_wed_free_ring(dev, &dev->rro.ring);
+ }
+@@ -939,9 +949,12 @@ mtk_wed_free_tx_rings(struct mtk_wed_dev
+ 	int i;
+
+ 	for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++)
+-		mtk_wed_free_ring(dev, &dev->tx_ring[i]);
++		if ((dev->tx_ring[i].flags & MTK_WED_RING_CONFIGURED))
++			mtk_wed_free_ring(dev, &dev->tx_ring[i]);
++
+ 	for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++)
+-		mtk_wed_free_ring(dev, &dev->rx_wdma[i]);
++		if ((dev->rx_wdma[i].flags & MTK_WED_RING_CONFIGURED))
++			mtk_wed_free_ring(dev, &dev->rx_wdma[i]);
+ }
+
+ static void
+@@ -1906,6 +1919,8 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_we
+ 					 dev->hw->soc->wdma_desc_size, true))
+ 		return -ENOMEM;
+
++	wdma->flags |= MTK_WED_RING_CONFIGURED;
++
+ 	wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
+ 		 wdma->desc_phys);
+ 	wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT,
+@@ -1952,6 +1967,8 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
+ 		}
+ 	}
+
++	wdma->flags |= MTK_WED_RING_CONFIGURED;
++
+ 	wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
+ 		 wdma->desc_phys);
+ 	wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT,
+@@ -2507,6 +2524,7 @@ mtk_wed_tx_ring_setup(struct mtk_wed_dev
+
+ 	ring->reg_base = MTK_WED_RING_TX(idx);
+ 	ring->wpdma = regs;
++	ring->flags |= MTK_WED_RING_CONFIGURED;
+
+ 	if (mtk_wed_is_v3_or_greater(dev->hw) && idx == 1) {
+ 		/* reset prefetch index */

target/linux/mediatek/patches-6.6/999-3006-Fix-Eagle-mlo-tx-T.P-too-low-issue.patch

@@ -0,0 +1,20 @@
+From 7385f88aec1d6b3717fd7a53709d6852e50c2816 Mon Sep 17 00:00:00 2001
+From: Rex Lu <rex.lu@mediatek.com>
+Date: Tue, 1 Oct 2024 14:20:09 +0800
+Subject: [PATCH 5/6] Fix Eagle mlo tx T.P too low issue
+
+---
+ drivers/net/ethernet/mediatek/mtk_wed.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -2134,7 +2134,7 @@ mtk_wed_dma_enable(struct mtk_wed_device
+ 			MTK_WED_WDMA_RX_PREF_DDONE2_EN);
+ 		wed_set(dev, MTK_WED_WDMA_RX_PREF_CFG, MTK_WED_WDMA_RX_PREF_EN);
+
+-		wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
++		wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
+ 			MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK_LAST);
+ 		wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
+ 			MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK |