Merge branch 'master' into pps_lock_hacking

.gitlab-ci.yml

@@ -8,7 +8,7 @@ stages:
 variables:
   XILINX_VIVADO: /non-free/Xilinx/Vivado/2020.2
   CI_REGISTRY: mohs.dhcp.lbl.gov
-  CONTAINER_IMAGE: $CI_REGISTRY/testing_base_bullseye
+  CONTAINER_IMAGE: $CI_REGISTRY/testing_base_bookworm
   # CONTAINER_IM_IMAGE: $CI_REGISTRY/riscv_bloat
   DOCKER_HOST: tcp://docker:2375/
   DOCKER_DRIVER: overlay2
@@ -31,6 +31,7 @@ include:
   - local: .gitlab/ci/dsp.gitlab-ci.yml
   - local: .gitlab/ci/marble_family.gitlab-ci.yml
   - local: .gitlab/ci/swap_gitid.gitlab-ci.yml
+  - local: .gitlab/ci/cdc_check.gitlab-ci.yml
 
 leep_test:
   script:
@@ -112,7 +113,6 @@ sphinx_docs:
     python3 -m pip install \
         sphinx==5.0.2 \
         sphinx_rtd_theme \
-        numpy \
         m2r2==0.3.2
     sed -i -e '/pattern="PS"/ s/rights=".*" pattern=/rights="read|write" pattern=/g' \
         -e '/pattern="PDF"/ s/rights=".*" pattern=/rights="read|write" pattern=/g' \

.gitlab/ci/cdc_check.gitlab-ci.yml

@@ -0,0 +1,11 @@
+badger_cdc:
+  stage: test
+  script:
+    - cd badger/tests && make hw_test_cdc.txt
+# not yet a regression test -- just checking the process for now
+
+marble_cdc:
+  stage: test
+  script:
+    - cd projects/test_marble_family && make marble_base_cdc.txt
+# not yet a regression test -- just checking the process for now

.gitlab/ci/oscope.gitlab-ci.yml

@@ -19,7 +19,7 @@ oscope_top_bmb7:
 
 oscope_top_marble:
   before_script:
-    - cd projects/oscope/marble_family && ls /non-free && apt-get update && apt-get install -y yosys
+    - cd projects/oscope/marble_family && ls /non-free
   stage: synthesis
   script:
     - verilator -V && XILINX_VIVADO=$XILINX_VIVADO PATH=$XILINX_VIVADO/bin:$PATH make oscope_top.bit
@@ -29,27 +29,22 @@ oscope_top_marble:
     paths:
       - projects/oscope/marble_family/oscope_top.bit
 
-# litex_trigger_capture:
-#   stage: synthesis
-#   before_script:
-#     - mkdir /litex_setup_dir && cd /litex_setup_dir
-#     - wget https://raw.githubusercontent.com/enjoy-digital/litex/70c5be6fb8/litex_setup.py && python3 litex_setup.py init
-#     - cd litex && git checkout 70c5be6fb8 && cd ..
-#     - cd liteeth && git checkout 8ba5cf06a6fb3979a6cde5ed46c10e91a053ba3f && cd ..
-#     - cd litedram && git checkout 2b0f806c96ff089bd8c51da8e223bfff23434ee1 && cd ..
-#     - cd liteiclink && git checkout bba716a9c06cc0870d90b31c6aa3bd0982377fcb && cd ..
-#     - cd litescope && git checkout 457f0875db0c1a0ff0e20659fe81b5bf696875d4 && cd ..
-#     - apt-get update && apt-get install -y ninja-build && pip3 install meson==0.64.1 && python3 litex_setup.py install
-#     - cd /builds/hdl-libraries/bedrock/projects/trigger_capture
-#   script:
-#     XILINXD_LICENSE_FILE=$XILINXD_LICENSE_FILE PATH=$XILINX_VIVADO/bin:$PATH && make marble.bit
-#   artifacts:
-#     name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
-#     expire_in: 1 week
-#     when: always
-#     paths:
-#       - projects/trigger_capture/build/marble/gateware/marble.bit
-#       - projects/trigger_capture/csr.csv
+litex_trigger_capture:
+  stage: synthesis
+  before_script:
+    - apt-get update && apt-get install -y ninja-build && pip3 install meson==0.64.1
+    - mkdir /litex_setup_dir
+    - (BD=$PWD && cd /litex_setup_dir && sh $BD/build-tools/litex_meta.sh)
+    - cd projects/trigger_capture
+  script:
+    XILINXD_LICENSE_FILE=$XILINXD_LICENSE_FILE PATH=$XILINX_VIVADO/bin:$PATH && make marble.bit
+  artifacts:
+    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
+    expire_in: 1 week
+    when: always
+    paths:
+      - projects/trigger_capture/build/marble/gateware/marble.bit
+      - projects/trigger_capture/csr.csv
 
 # oscope_program:
 #   before_script:

Dockerfile

@@ -1,4 +1,4 @@
-FROM debian:bullseye-slim as testing_base_bullseye
+FROM debian:bookworm-slim as testing_base_bookworm
 
 # Vivado needs libtinfo5, at least for Artix?
 RUN apt-get update && \
@@ -8,6 +8,8 @@ RUN apt-get update && \
     libbsd-dev \
     xc3sprog \
     build-essential \
+    yosys \
+    verilator \
     libtinfo5 \
     wget \
     iputils-ping \
@@ -19,6 +21,9 @@ RUN apt-get update && \
     python3-numpy \
     python3-scipy \
     python3-matplotlib \
+    python3-yaml \
+    python3-serial \
+    python3-setuptools-scm \
     gcc-riscv64-unknown-elf \
     picolibc-riscv64-unknown-elf \
     cmake \
@@ -35,71 +40,29 @@ RUN apt-get update && \
 # gcc-riscv64-unknown-elf above replace our previous
 #   approach, used in Buster, of building from source
 
+# Allow pip to install packages
+RUN mkdir -p $HOME/.config/pip && \
+    printf "[global]\nbreak-system-packages = true\n" > \
+        $HOME/.config/pip/pip.conf && \
+    cat $HOME/.config/pip/pip.conf
+
 # vhd2vl
 RUN git clone https://github.com/ldoolitt/vhd2vl && \
     cd vhd2vl && \
-    git checkout 37e3143395ce4e7d2f2e301e12a538caf52b983c && \
+    git checkout bbe3198c435a4a6325bdd08b7b43a47b6dacf5de && \
     make && \
     install src/vhd2vl /usr/local/bin && \
     cd .. && \
     rm -rf vhd2vl
 
-# Yosys
-# For now we need to build yosys from source, since Debian Bullseye
-# is stuck at yosys-0.9 that doesn't have the features we need.
-# Revisit this choice when Debian catches up, maybe in Bookworm,
-# and hope to get back to "apt-get install yosys" then.
-# Note that the standard yosys build process used here requires
-# network access to download abc from https://github.com/berkeley-abc/abc.
-RUN apt-get update && \
-    apt-get install -y \
-        clang \
-        libreadline-dev \
-        tcl-dev \
-        libffi-dev \
-        graphviz \
-        xdot \
-        libboost-system-dev \
-        libboost-python-dev \
-        libboost-filesystem-dev \
-        zlib1g-dev && \
-    rm -rf /var/lib/apt/lists/* && \
-    git clone https://github.com/cliffordwolf/yosys.git && \
-    cd yosys && \
-    git checkout 40e35993af6ecb6207f15cc176455ff8d66bcc69 && \
-    make config-clang && \
-    make -j4 && \
-    make install && \
-    cd .. && \
-    rm -rf yosys
+# Yosys and Verilator are no longer built from source, just included
+# in apt-get list above.  Tested good in Debian Bookworm.
 
+# Because we are running inside docker, installing
+# python packages system wide should be ok
 RUN pip3 install \
-    pyyaml==5.1.2 pyserial==3.4 setuptools-scm==7.1.0 \
     nmigen==0.2
 
-# we need a version of verilator with more than 20000, issue #1574,
-# any version > v4.110 should have this limit increased to 40000.
-# libz-dev required for Verilator FST support
-RUN apt-get update && \
-    apt-get install -y \
-        libfl2 \
-        libfl-dev \
-        libz-dev \
-        zlib1g \
-        zlib1g-dev \
-        autoconf && \
-    rm -rf /var/lib/apt/lists/* && \
-    git clone https://github.com/verilator/verilator && \
-    cd verilator && \
-    git checkout v4.228 && \
-    autoconf && \
-    ./configure && \
-    make -j4 && \
-    make install && \
-    cd ../ && \
-    rm -rf verilator && \
-    verilator -V
-
 # SymbiYosys formal verification tool + Yices 2 solver (`sby` command)
 RUN apt-get update && \
     apt-get install -y \
@@ -114,7 +77,6 @@ RUN apt-get update && \
         graphviz \
         xdot \
         pkg-config \
-        python \
         python3 \
         libftdi-dev \
         gperf \

badger/construct.v

@@ -41,9 +41,10 @@ module construct #(
 
 // Capture state across clock domains, convert back to binary
 reg [paw-1:0] gray_l=0, state=0;
+// verilator lint_save
 // verilator lint_off UNOPTFLAT
 wire [paw-1:0] new_state = gray_l ^ {1'b0, new_state[paw-1:1]};
-// verilator lint_on UNOPTFLAT
+// verilator lint_restore
 always @(posedge clk) begin
 	gray_l <= gray_state;
 	state <= new_state;

badger/mac_subset.v

@@ -49,6 +49,10 @@ test_tx_mac #(
 	.mac_data(mac_data)
 );
 
+// Move scanner_busy to tx_clk domain for use by precog
+reg scanner_busy_tx=0;
+always @(posedge tx_clk) scanner_busy_tx <= scanner_busy;
+
 // Instantiate precog
 wire clear_to_send;
 wire [10:0] precog_width = len_req + 2*ifg;
@@ -58,7 +62,7 @@ precog #(
 ) precog (
 	.clk (tx_clk),
 	.tx_packet_width  (precog_width),
-	.scanner_busy     (scanner_busy),
+	.scanner_busy     (scanner_busy_tx),
 	.request_to_send  (req),
 	.clear_to_send    (clear_to_send)
 );

badger/rtefi_center.v

@@ -146,9 +146,6 @@ assign ibadge_data = pbuf_din;
 // Also note the lack of a write-enable, just write every cycle.
 reg [8:0] pbuf[0:(1<<paw)-1];
 reg [8:0] pbuf_out=0;
-`ifndef YOSYS
-initial pbuf_out=0;
-`endif
 wire [paw-1:0] mem_a2;  // see below
 always @(posedge rx_clk) pbuf[pbuf_a_rx] <= pbuf_din;
 always @(posedge tx_clk) pbuf_out <= pbuf[mem_a2];

badger/scanner.v

@@ -78,12 +78,14 @@ reg [3:0] ifg_count=0;  // Inter-frame gap counter
 wire ifg_inc = ~(&ifg_count[3:2]);  // saturate at 12
 wire ifg_ok = ifg_count >= 10;  // slightly relaxed from spec of 12,
 // this configuration guarantees 11 non-data cycles between frames
+reg enable_rx_r=0;
 always @(posedge clk) begin
+	enable_rx_r <= enable_rx;  // cross clock domains
 	if (h_idle | h_preamble) ifg_count <= ifg_count + ifg_inc;
 	else ifg_count <= 0;
 	if (h_idle & eth_strobe) begin
 		h_idle <= 0;
-		if (eth_octet==8'h55 && enable_rx) h_preamble <= 1;
+		if (eth_octet==8'h55 && enable_rx_r) h_preamble <= 1;
 		else h_drop <= 1;
 	end
 	if (h_preamble) begin

badger/tests/Makefile

@@ -209,6 +209,16 @@ hw_test.vcd: tap-vpi.vpi
 hw_test_start: hw_test_tb tap-vpi.vpi
 	$(VVP) $<
 
+# =====
+# experimental check of CDC-correctness
+# not yet turned into a regression test
+hw_test_yosys.json: hw_test.v $(RTEFI_V) mac_compat_dpram.v activity.v base_rx_mac.v $(LB_DEMO_V) spi_gate.v ../../build-tools/cdc_snitch_proc.ys
+	$(YOSYS) --version
+	$(YOSYS) -q -p "read_verilog -DBUGGY_FORLOOP $(filter %.v, $^); script $(filter %_proc.ys, $^); write_json $@"
+# (I don't think yosys for-loop is actually buggy, just tediously slow, and in this case unnecessary)
+hw_test_cdc.txt: ../../build-tools/cdc_snitch.py hw_test_yosys.json
+	$(PYTHON) $^ -o $@
+
 # =====
 # experimental bitfiles, not for hardware
 bits: scanner.bit construct.bit xformer.bit ethernet_crc_add.bit udp_port_cam_wrap.bit rtefi_blob.bit
@@ -424,9 +434,9 @@ CLEAN += *_tb *.o *.vpi *.vcd *.d *.out *_synth.v *.svg crc_genguts.vh crc_deriv
 CLEAN += crc8e_guts.vh spellme* crc8e_guts_y.v rtefi_live Vrtefi_blob Vmem_gateway_wrap Vhw_test Vcluster
 CLEAN += stests.dat *3.dat pcap2v host_mem_gen host_mem test_tx.out mac_subset.out host_cmds_gen
 CLEAN += host_cmds.dat retrigger.dat selfmac_in.dat xfer1 lorem_ipsum.hex spi_flash.grab udprtx
-CLEAN += cluster_run.out
+CLEAN += cluster_run.out hw_test_cdc.txt hw_test_yosys.json
 CLEAN += $(RTEFI_CLEAN)
-CLEAN += *.html *.pdf
+CLEAN += *.html *.pdf *.log
 CLEAN_DIRS += obj_dir _xilinx
 # Actual "clean" rule in bottom_rules.mk
 include $(BUILD_DIR)/bottom_rules.mk

badger/tests/precog_tb.v

@@ -10,14 +10,12 @@ initial begin
 		$dumpfile("precog.vcd");
 		$dumpvars(5,precog_tb);
 	end
-	$display("Non-checking testbench.  Will always PASS");
 	while (1) begin
 		cc = cc + 1;
 		clk=0; #5;
 		clk=1; #5;
 	end
-	$display("PASS");
-	$finish(0);
+	// termination handled in another block
 end
 
 wire clear_to_send;
@@ -33,7 +31,7 @@ precog #(
 	.clk                (clk),
 	.tx_packet_width    (tx_packet_width),
 	.scanner_busy       (scanner_busy),
-	.request_to_send      (request_to_send),
+	.request_to_send    (request_to_send),
 	.clear_to_send      (clear_to_send)
 );
 

badger/tests/spi_flash_check.sh

@@ -11,5 +11,5 @@ esac
 # make udp-vpi.vpi spi_flash_tb lorem_ipsum.hex
 vvp -N spi_flash_tb +udp_port=3500 +firmware=lorem_ipsum.hex > /dev/null &
 sleep 3
-python3 "$1" --ip localhost --udp 3500 --wait 0.15 --power --dump spi_flash.grab --add 0 --pages 1
+python3 "$1" --ip localhost --udp 3500 --wait 0.15 --power --dump spi_flash.grab --pages 1
 kill %1

badger/tests/spi_test.py

@@ -402,7 +402,9 @@ def main():
         description="Utility for working with SPI Flash chips attached to Packet Badger")
     parser.add_argument('--ip', default='192.168.19.8', help='IP address')
     parser.add_argument('--udp', type=int, default=804, help='UDP Port number')
-    parser.add_argument('-a', '--add', type=lambda x: int(x, 0), help='Flash offset address')
+    if EXPERT:
+        parser.add_argument('-a', '--add', type=lambda x: int(x, 0), help='Flash offset address')
+    parser.add_argument('--upper', action='store_true', help="Use upper half of flash")
     parser.add_argument('--pages', type=int, help='Number of 256-byte pages')
     parser.add_argument('--mem_read', action='store_true', help='Read ROM info')
     parser.add_argument('--id', action='store_true',
@@ -447,7 +449,9 @@ def main():
     sock.connect((IPADDR, PORTNUM))
 
     # default starting address and length
-    ad = args.add if args.add is not None else 0x0
+    ad = 8388608 if args.upper else 0
+    if EXPERT and args.add is not None:
+        ad = args.add
     # 1814 for XC6SLX16, could also get this from JEDEC status?
     page_count = 1814
     page_count = 2
@@ -516,7 +520,7 @@ def main():
             print("Unexpected CONFIG, aborting")
             exit(1)
         write_status(sock, 0x98, config=0x24)
-        write_status(sock, 0x98, config=0x25)
+        # write_status(sock, 0x98, config=0x25)
     elif EXPERT and args.status_write is not None:
         write_status(sock, args.status_write, config=args.config_write)