Progress on timing control of AXI transactions across clock domains

BerkeleyLab · Aug 16, 2024 · 900bf91 · 900bf91
1 parent debf5f8
commit 900bf91
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Showing 11 changed files with 824 additions and 154 deletions.
diff --git a/axi/Makefile b/axi/Makefile
@@ -3,13 +3,16 @@ include ../dir_list.mk
 include $(BUILD_DIR)/top_rules.mk
 
 .PHONY: all
-all: axi_host_check axi_lb_check axi_lb_cdc_check axi_channel_xdomain_check axi_cdc_check
+all: axi_host_check axi_host_pipelined_check axi_lb_check axi_lb_cdc_check axi_channel_xdomain_check axi_cdc_check
 
 axi_host_tb: axi_host_tb.v axi_host.v axi_dummy.v axi_delay.v
 	$(VERILOG_TB)
 
+axi_host_pipelined_tb: axi_host_pipelined_tb.v axi_host_pipelined.v axi_dummy.v
+	$(VERILOG_TB)
+
 #axi_cdc_tb: axi_cdc_tb.v axi_cdc.v axi_host.v $(DSP_DIR)/data_xdomain.v $(DSP_DIR)/flag_xdomain.v $(DSP_DIR)/reg_tech_cdc.v axi_dummy.v
-axi_cdc_tb: axi_cdc_tb.v axi_cdc.v axi_channel_xdomain.v axi_host.v axi_dummy.v
+axi_cdc_tb: axi_cdc_tb.v axi_cdc.v axi_channel_xdomain.v axi_host_pipelined.v axi_dummy.v $(DSP_DIR)/fifo_2c.v $(DSP_DIR)/dpram.v
 	$(VERILOG_TB)
 
 axi_lb_tb: axi_lb_tb.v axi_lb.v axi_host.v axi_delay.v $(LOCALBUS_DIR)/lb_dummy.v $(LOCALBUS_DIR)/lb_delay.v
@@ -19,9 +22,9 @@ axi_lb_tb: axi_lb_tb.v axi_lb.v axi_host.v axi_delay.v $(LOCALBUS_DIR)/lb_dummy.
 axi_lb_cdc_tb: axi_lb_cdc_tb.v axi_lb_cdc.v axi_host.v axi_delay.v $(DSP_DIR)/fifo_2c.v $(DSP_DIR)/dpram.v $(LOCALBUS_DIR)/lb_dummy.v $(LOCALBUS_DIR)/lb_delay.v
 	$(VERILOG_TB)
 
-axi_channel_xdomain_tb: axi_channel_xdomain_tb.v axi_channel_xdomain.v channel_consumer.v channel_producer.v
+axi_channel_xdomain_tb: axi_channel_xdomain_tb.v axi_channel_xdomain.v channel_consumer.v channel_producer.v $(DSP_DIR)/fifo_2c.v $(DSP_DIR)/dpram.v
 
-CLEAN+=axi_lb_cdc_tb axi_lb_tb axi_host_tb axi_cdc_tb axi_channel_xdomain_tb
-CLEAN+=axi_lb_cdc.vcd axi_lb.vcd axi_host.vcd axi_cdc.vcd axi_channel_xdomain.vcd
+CLEAN+=axi_lb_cdc_tb axi_lb_tb axi_host_tb axi_host_pipelined_tb axi_cdc_tb axi_channel_xdomain_tb
+CLEAN+=axi_lb_cdc.vcd axi_lb.vcd axi_host.vcd axi_host_pipelined.vcd axi_cdc.vcd axi_channel_xdomain.vcd
 
 include $(BUILD_DIR)/bottom_rules.mk
diff --git a/axi/axi_cdc.v b/axi/axi_cdc.v
@@ -3,8 +3,14 @@
 
 module axi_cdc #(
   parameter C_AXI_DATA_WIDTH = 32,
-  parameter C_AXI_ADDR_WIDTH = 21
+  parameter C_AXI_ADDR_WIDTH = 21,
+  // If FIFO_AW == 0, stretches handshake signals across the clock boundary,
+  // guaranteeing the transaction at the cost of additional cycles delay
+  // Else, uses best effort (FIFO-based) transactions, which could
+  // overflow.
+  parameter FIFO_AW = 0
 ) (
+  input  s_read_enable,
   // AXI4LITE Ports from Host
   input  s_axi_aclk,
   input  s_axi_aresetn,
@@ -57,7 +63,8 @@ wire [C_AXI_ADDR_WIDTH+2: 0] s_aw_info, m_aw_info;
 assign s_aw_info = {s_axi_awprot, s_axi_awaddr};
 assign {m_axi_awprot, m_axi_awaddr} = m_aw_info;
 axi_channel_xdomain #(
-  .WIDTH(C_AXI_ADDR_WIDTH+3)
+  .WIDTH(C_AXI_ADDR_WIDTH+3),
+  .FIFO_AW(FIFO_AW)
 ) xdomain_awaddr (
   .clka(s_axi_aclk), // input
   .dataa(s_aw_info), // input [WIDTH-1:0]
@@ -66,7 +73,8 @@ axi_channel_xdomain #(
   .clkb(m_axi_aclk), // input
   .datab(m_aw_info), // output [WIDTH-1:0]
   .validb(m_axi_awvalid), // output
-  .readyb(m_axi_awready) // input
+  .readyb(m_axi_awready), // input
+  .enb(1'b1) // input
 );
 // ==================== Read Address Channel: ARVALID ARREADY ARADDR ARPROT ===================
 // htop
@@ -75,7 +83,8 @@ assign s_ar_info = {s_axi_arprot, s_axi_araddr};
 assign {m_axi_arprot, m_axi_araddr} = m_ar_info;
 wire s_axi_arready;
 axi_channel_xdomain #(
-  .WIDTH(C_AXI_ADDR_WIDTH+3)
+  .WIDTH(C_AXI_ADDR_WIDTH+3),
+  .FIFO_AW(FIFO_AW)
 ) xdomain_araddr (
   .clka(s_axi_aclk), // input
   .dataa(s_ar_info), // input [WIDTH-1:0]
@@ -84,15 +93,17 @@ axi_channel_xdomain #(
   .clkb(m_axi_aclk), // input
   .datab(m_ar_info), // output [WIDTH-1:0]
   .validb(m_axi_arvalid), // output
-  .readyb(m_axi_arready) // input
+  .readyb(m_axi_arready), // input
+  .enb(1'b1) // input
 );
 // ====================== Write Data Channel: WVALID WREADY WDATA WSTRB =======================
 // htop
 wire [C_AXI_DATA_WIDTH+(C_AXI_DATA_WIDTH/8)-1: 0] s_w_info, m_w_info;
 assign s_w_info = {s_axi_wstrb, s_axi_wdata};
 assign {m_axi_wstrb, m_axi_wdata} = m_w_info;
 axi_channel_xdomain #(
-  .WIDTH(C_AXI_DATA_WIDTH+(C_AXI_DATA_WIDTH/8))
+  .WIDTH(C_AXI_DATA_WIDTH+(C_AXI_DATA_WIDTH/8)),
+  .FIFO_AW(FIFO_AW)
 ) xdomain_wdata (
   .clka(s_axi_aclk), // input
   .dataa(s_w_info), // input [WIDTH-1:0]
@@ -101,12 +112,14 @@ axi_channel_xdomain #(
   .clkb(m_axi_aclk), // input
   .datab(m_w_info), // output [WIDTH-1:0]
   .validb(m_axi_wvalid), // output
-  .readyb(m_axi_wready) // input
+  .readyb(m_axi_wready), // input
+  .enb(1'b1) // input
 );
 // ======================= Write Response Channel: BVALID BREADY BRESP ========================
 // ptoh
 axi_channel_xdomain #(
-  .WIDTH(2)
+  .WIDTH(2),
+  .FIFO_AW(FIFO_AW)
 ) xdomain_bresp (
   .clka(m_axi_aclk), // input
   .dataa(m_axi_bresp), // input [WIDTH-1:0]
@@ -115,7 +128,8 @@ axi_channel_xdomain #(
   .clkb(s_axi_aclk), // input
   .datab(s_axi_bresp), // output [WIDTH-1:0]
   .validb(s_axi_bvalid), // output
-  .readyb(s_axi_bready) // input
+  .readyb(s_axi_bready), // input
+  .enb(1'b1) // input
 );
 
 // ======================= Read Data Channel: RVALID RREADY RDATA RRESP =======================
@@ -124,7 +138,8 @@ wire [C_AXI_DATA_WIDTH+1: 0] s_r_info, m_r_info;
 assign m_r_info = {m_axi_rresp, m_axi_rdata};
 assign {s_axi_rresp, s_axi_rdata} = s_r_info;
 axi_channel_xdomain #(
-  .WIDTH(C_AXI_DATA_WIDTH+2)
+  .WIDTH(C_AXI_DATA_WIDTH+2),
+  .FIFO_AW(FIFO_AW)
 ) xdomain_rdata (
   .clka(m_axi_aclk), // input
   .dataa(m_r_info), // input [WIDTH-1:0]
@@ -133,7 +148,8 @@ axi_channel_xdomain #(
   .clkb(s_axi_aclk), // input
   .datab(s_r_info), // output [WIDTH-1:0]
   .validb(s_axi_rvalid), // output
-  .readyb(s_axi_rready) // input
+  .readyb(s_axi_rready), // input
+  .enb(s_read_enable) // input
 );
 
 endmodule