test_marble_family: add option to use GTP clock as system clock

projects/test_marble_family/marble_features.yaml

@@ -13,6 +13,8 @@ marble_mini:
         default_enable_rx: 1
         misc_config_default: 4
         use_rgmii_idelay: 1
+        # Options are "gtp_ref_clk, ddr_ref_clk or sysclk"
+        sysclk_src: "gtp_ref_clk"
 
 marble_v2:
     defs:
@@ -26,3 +28,5 @@ marble_v2:
         default_enable_rx: 1
         misc_config_default: 4
         use_rgmii_idelay: 1
+        # Options are "gtp_ref_clk, ddr_ref_clk or sysclk"
+        sysclk_src: "ddr_ref_clk"

projects/test_marble_family/marble_top.v

@@ -106,28 +106,24 @@ wire [23:0] FMC2_HA_P;
 wire [23:0] FMC2_HA_N;
 `endif
 
-wire clk125;
-// Use DDR_REF_CLK_P as the reference for Marble V2, as this does not depend
-// on the ADN4600 clock switch configuration
+// Only Marble V2 has DDR ref clk
 `ifdef MARBLE_V2
 wire ddrrefclk_unbuf, ddrrefclk;
-IBUFDS passi_125(.I(DDR_REF_CLK_P), .IB(DDR_REF_CLK_N), .O(ddrrefclk_unbuf));
+IBUFDS ddri_125(.I(DDR_REF_CLK_P), .IB(DDR_REF_CLK_N), .O(ddrrefclk_unbuf));
 // Vivado fails, with egregiously useless error messages,
 // if you don't put this BUFG in the chain to the MMCM.
-BUFG passg_125(.I(ddrrefclk_unbuf), .O(ddrrefclk));
-assign clk125 = ddrrefclk;
+BUFG ddrg_125(.I(ddrrefclk_unbuf), .O(ddrrefclk));
+`endif
+
 // For Marblemini, GTPREFCLKs are routed directly to MGTCLK pins,
 // so using them does not depend on the clock switch configuration
 // either
-`else
 wire gtpclk0, gtpclk;
 // Gateway GTP refclk to fabric
 IBUFDS_GTE2 passi_125(.I(GTPREFCLK_P), .IB(GTPREFCLK_N), .CEB(1'b0), .O(gtpclk0));
 // Vivado fails, with egregiously useless error messages,
 // if you don't put this BUFG in the chain to the MMCM.
 BUFG passg_125(.I(gtpclk0), .O(gtpclk));
-assign clk125 = gtpclk;
-`endif
 
 wire si570;
 `ifdef USE_SI570
@@ -159,8 +155,26 @@ wire clk200;  // clk200 should be 200MHz +/- 10MHz or 300MHz +/- 10MHz,
 // have problems with the Xilinx DNA readout.
 `define USE_IDELAYCTRL
 
-`ifdef USE_SYSCLK
+// Sanity check for C_SYSCLK_SRC
+generate
+if (C_SYSCLK_SRC != "gtp_ref_clk" &&
+    C_SYSCLK_SRC != "ddr_ref_clk" &&
+    C_SYSCLK_SRC != "sys_clk") begin
+    $error("C_SYSCLK_SRC parameter has an invalid_value");
+end
+endgenerate
+
+// If using ddr_ref_clk it must be a v2
+generate
+if (C_SYSCLK_SRC == "ddr_ref_clk" &&
+    C_CARRIER_REV != "v2") begin
+    $error("C_SYSCLK_SRC == ddr_ref_clk can only be used with a Marble v2");
+end
+endgenerate
+
+generate
 // this configuration is probably bit-rotted
+if(C_SYSCLK_SRC == "sys_clk") begin
 wire SYSCLK_N = 0;
 gmii_clock_handle clocks(
 	.sysclk_p(SYSCLK_P),
@@ -171,7 +185,21 @@ gmii_clock_handle clocks(
 	.clk_locked(clk_locked)
 );
 assign test_clk=0;
-`else
+end
+else begin
+
+wire clk125;
+// Use GTPREFCLK_P
+if (C_SYSCLK_SRC == "gtp_ref_clk") begin
+assign clk125 = gtpclk;
+end
+// Use DDR_REF_CLK_P, preferred because it does not depend
+// on the ADN4600 clock switch configuration. Only available
+// on Marble v2
+else if (C_SYSCLK_SRC == "ddr_ref_clk") begin
+assign clk125 = ddrrefclk;
+end
+
 xilinx7_clocks #(
 	.DIFF_CLKIN("BYPASS"),
 	.CLKIN_PERIOD(8),  // REFCLK = 125 MHz
@@ -192,7 +220,9 @@ xilinx7_clocks #(
 	.clk_out3f(test_clk),  // not buffered, straight from MMCM
 	.locked   (clk_locked)
 );
-`endif
+end
+endgenerate
+
 `ifdef USE_IDELAYCTRL
 assign clk200 = clk_out1;
 reg bad_slow_clock=0;