diff --git a/boards/renesas/rza3ul_smarc/Kconfig.rza3ul_smarc b/boards/renesas/rza3ul_smarc/Kconfig.rza3ul_smarc new file mode 100644 index 000000000000..56e7567e7777 --- /dev/null +++ b/boards/renesas/rza3ul_smarc/Kconfig.rza3ul_smarc @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RZA3UL_SMARC + select SOC_R9A07G063U02GBG diff --git a/boards/renesas/rza3ul_smarc/board.cmake b/boards/renesas/rza3ul_smarc/board.cmake new file mode 100644 index 000000000000..f67ff5510ecc --- /dev/null +++ b/boards/renesas/rza3ul_smarc/board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R9A07G063U02GBG") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/rza3ul_smarc/board.yml b/boards/renesas/rza3ul_smarc/board.yml new file mode 100644 index 000000000000..d00b2df7af96 --- /dev/null +++ b/boards/renesas/rza3ul_smarc/board.yml @@ -0,0 +1,6 @@ +board: + name: rza3ul_smarc + full_name: RZ/A3UL SMARC Evaluation Board Kit + vendor: renesas + socs: + - name: r9a07g063u02gbg diff --git a/boards/renesas/rza3ul_smarc/doc/index.rst b/boards/renesas/rza3ul_smarc/doc/index.rst new file mode 100644 index 000000000000..8b8ffec73a36 --- /dev/null +++ b/boards/renesas/rza3ul_smarc/doc/index.rst @@ -0,0 +1,140 @@ +.. zephyr:board:: rza3ul_smarc + +Overview +******** + +The Renesas RZ/A3UL SMARC Evaluation Board Kit (RZ/A3UL-EVKIT) consists of a SMARC v2.1 module board and a carrier board. +Two types of evaluation boards are available: QSPI version and Octal-SPI version. The QSPI version is supported. + +* Device: RZ/A3UL R9A07G063U02GBG + + * Cortex-A55 Single + * BGA361pin, 13mmSq body, 0.5mm pitch + * Certified device in `Azure Certified Device Catalog `_ + +* SMARC v2.1 Module Board Functions + + * Two types of evaluation boards are available: + + * QSPI version: QSPI Serial Flash (Boot) + DDR4 + * Octal-SPI version: Octa Flash (Boot) + OctaRAM + DDR4 + + * DDR4 SDRAM: 1GB x 1pc + * QSPI flash memory: 128Mb x 1pc `AT25QL128A `_ (QSPI version) + * Octa RAM memory: 512Mb x 1pc / Octa flash memory: 1Gb x 1pc (Octal-SPI version) + * eMMC memory: 64GB x 1pc + * The microSD card slot is implemented and used as an eSD for boot. + * 5-output clock oscillator `5P35023 `_ implemented + * PMIC power supply `DA9062 `_ implemented + +* Carrier Board Functions + + * The FFC/FPC connector is mounted as standard for connection to high-speed serial interface for camera module. + * The Micro-HDMI connector via DSI/HDMI conversion module is mounted as standard for connection to high-speed serial interface for digital video module. + * The Micro-AB receptacle (ch0: USB2.0 OTG) and A receptacle (ch1: USB2.0 Host) are respectively mounted as standard for connection to USB interface. + * The RJ45 connector is mounted as standard for software development and evaluation using Ethernet. + * The audio codec is mounted as standard for advance development of audio system. The audio jack is implemented for connection to audio interface. + * The Micro-AB receptacles are implemented for connection to asynchronous serial port interface. + * The microSD card slot and two sockets for PMOD are implemented as an interface for RZ/A3UL peripheral functions. + * For power supply, a mounted USB Type-C receptacle supports the USB PD standard. + +Hardware +******** +The Renesas RZ/A3UL MPU documentation can be found at `RZ/A3UL Group Website`_ + +.. figure:: rza3ul_block_diagram.webp + :width: 600px + :align: center + :alt: RZ/A3UL group feature + + RZ/A3UL block diagram (Credit: Renesas Electronics Corporation) + +Supported Features +================== + +The ``rza3ul_smarc`` board supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| GIC | on-chip | generic interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | arch/arm | ++-----------+------------+-------------------------------------+ +| PINCTRL | on-chip | pinctrl | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +RZ/A3UL-EVKIT uses Initial Program Loader (IPL) to perform initial settings and copy the Zephyr image from flash to DDR SRAM for execution. It only needs to be written to flash once. + +There are two options to write IPL: + + 1. (Recommended) Follow ''4. Tutorial: Your First RZ MPU Project - Blinky'' of `Getting Started with RZ/A Flexible Software Package`_ to start writing a blinky sample with FSP. The IPL will be written to flash by default in debugging time. + + 2. Follow the `Initial Program Loader Application Note`_ to write the IPL separately. The minimal steps are described below. + + a. Follow ''6. IPL development environment construction procedure'' to prepare the build environment. + + b. Follow ''7. IPL build environment construction procedure'' to build Initial Program Loader. + If the build is successful, Initial Program Loader file will be generated in /build/a3ul/release/rza3ul_smarc_qspi_ipl.srec + + c. Follow ''8.1 Create Debug Configuration'' to create a Debug configuration to run Initial Program Loader on the target board. + + d. Follow ''8.2 Connection to SMARC EVK Board'' to setup target board with SW1 Debugger Enable (SW1-1 OFF) and Boot (1.8V) Mode (SW11[1:4]=OFF OFF OFF ON). + + e. Follow ''8.4 Execution procedure of IPL'' to write Initial Program Loader to the target board. + +Applications for the ``rza3ul_smarc`` board can be built in the usual way as +documented in :ref:`build_an_application`. + +Console +======= +The UART port is accessed by USB Type-mircoB port (CN14). + +Debugging +========= + +It is possible to load and execute a Zephyr application binary on this board on the Cortex-A55 System Core +from the DDR SDRAM, using ``JLink`` debugger (:ref:`jlink-debug-host-tools`). + +Here is an example for building and debugging with the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rza3ul_smarc + :goals: build debug + +Flashing +======== + +Zephyr application can be flashed to QSPI/Octal-SPI storage and then loaded by Initial Program Loader. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rza3ul_smarc + :goals: build flash + +References +********** + +.. target-notes:: + +.. _RZ/A3UL Group Website: + https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rza3ul-powerful-1ghz-64-bit-mpus-rtos-support-enables-high-definition-hmi-and-quick-startup? + +.. _RZA3UL-EVKIT Website: + https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rza3ul-evkit-rza3ul-evaluation-board-kit + +.. _Initial Program Loader Application Note: + https://github.com/renesas/rza-initial-program-loader/tree/main/application_note + +.. _Getting Started with RZ/A Flexible Software Package: + https://www.renesas.com/en/document/apn/rza-getting-started-flexible-software-package diff --git a/boards/renesas/rza3ul_smarc/doc/rza3ul_block_diagram.webp b/boards/renesas/rza3ul_smarc/doc/rza3ul_block_diagram.webp new file mode 100644 index 000000000000..1eee3f8b4bc0 Binary files /dev/null and b/boards/renesas/rza3ul_smarc/doc/rza3ul_block_diagram.webp differ diff --git a/boards/renesas/rza3ul_smarc/doc/rza3ul_smarc.webp b/boards/renesas/rza3ul_smarc/doc/rza3ul_smarc.webp new file mode 100644 index 000000000000..91335d3057f1 Binary files /dev/null and b/boards/renesas/rza3ul_smarc/doc/rza3ul_smarc.webp differ diff --git a/boards/renesas/rza3ul_smarc/rza3ul_smarc-pinctrl.dtsi b/boards/renesas/rza3ul_smarc/rza3ul_smarc-pinctrl.dtsi new file mode 100644 index 000000000000..25e26032f610 --- /dev/null +++ b/boards/renesas/rza3ul_smarc/rza3ul_smarc-pinctrl.dtsi @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +&pinctrl { + /omit-if-no-ref/ scif0_pins: scif0 { + scif0-pinmux { + pinmux = , /* RXD */ + ; /* TXD */ + drive-strength = <1>; + slew-rate = "fast"; + }; + }; +}; diff --git a/boards/renesas/rza3ul_smarc/rza3ul_smarc.dts b/boards/renesas/rza3ul_smarc/rza3ul_smarc.dts new file mode 100644 index 000000000000..c3c0be4c817e --- /dev/null +++ b/boards/renesas/rza3ul_smarc/rza3ul_smarc.dts @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rza3ul_smarc-pinctrl.dtsi" + +/ { + model = "Renesas RZ/A3UL SMARC"; + compatible = "renesas,rza3ul-smarc"; + + chosen { + zephyr,sram = &ddr; + zephyr,flash = &spi_flash; + zephyr,console = &scif0; + zephyr,shell-uart = &scif0; + zephyr,code-partition= &slot0_partition; + }; + + ddr: memory@40200000 { + compatible ="zephyr,memory-region", "mmio-sram"; + reg = <0x40200000 (DT_SIZE_M(1024) - 0x200000)>; + zephyr,memory-region = "DDR"; + }; + + sram: memory@1e000 { + compatible ="zephyr,memory-region", "mmio-sram"; + reg = <0x1e000 DT_SIZE_K(72)>; + zephyr,memory-region = "SRAM"; + }; + + spi_flash: memory@20020000 { + compatible = "mmio-sram"; + reg = <0x20020000 (DT_SIZE_M(16) - 0x20000)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + header: partition@0 { + label = "header"; + reg = <0x00000000 0x200>; + read-only; + }; + + slot0_partition: partition@200 { + label = "image-0"; + reg = <0x00000200 (DT_SIZE_M(16)- 0x20200)>; + read-only; + }; + }; + }; + +}; + +&scif0 { + current-speed = <115200>; + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/renesas/rza3ul_smarc/rza3ul_smarc.yaml b/boards/renesas/rza3ul_smarc/rza3ul_smarc.yaml new file mode 100644 index 000000000000..1c29ec9fa27c --- /dev/null +++ b/boards/renesas/rza3ul_smarc/rza3ul_smarc.yaml @@ -0,0 +1,10 @@ +identifier: rza3ul_smarc +name: Cortex-A55 for Renesas RZ/A3UL SMARC +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +supported: + - uart + - gpio diff --git a/boards/renesas/rza3ul_smarc/rza3ul_smarc_defconfig b/boards/renesas/rza3ul_smarc/rza3ul_smarc_defconfig new file mode 100644 index 000000000000..dd2f33248dd5 --- /dev/null +++ b/boards/renesas/rza3ul_smarc/rza3ul_smarc_defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n + +# MMU Options +CONFIG_MAX_XLAT_TABLES=24 + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/drivers/gpio/gpio_renesas_rz.c b/drivers/gpio/gpio_renesas_rz.c index 386bae12bfb1..95f851815294 100644 --- a/drivers/gpio/gpio_renesas_rz.c +++ b/drivers/gpio/gpio_renesas_rz.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,6 +15,10 @@ #include #include "gpio_renesas_rz.h" #include +#if defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L) +#include "r_icu.h" +#include +#endif LOG_MODULE_REGISTER(rz_gpio, CONFIG_GPIO_LOG_LEVEL); #define LOG_DEV_ERR(dev, format, ...) LOG_ERR("%s:" #format, (dev)->name, ##__VA_ARGS__) @@ -28,7 +32,12 @@ struct gpio_rz_config { const ioport_cfg_t *fsp_cfg; const ioport_api_t *fsp_api; const struct device *int_dev; - uint8_t tint_num[GPIO_RZ_MAX_TINT_NUM]; + uint8_t int_num[GPIO_RZ_MAX_INT_NUM]; +#if defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L) + const struct device *eirq_dev[GPIO_RZ_MAX_INT_NUM]; + + void (*cb_list[GPIO_RZ_MAX_INT_NUM])(void *arg); +#endif }; struct gpio_rz_data { @@ -36,64 +45,74 @@ struct gpio_rz_data { sys_slist_t cb; ioport_instance_ctrl_t *fsp_ctrl; struct k_spinlock lock; +#if defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L) + uint8_t pin[GPIO_RZ_MAX_INT_NUM]; +#endif }; -struct gpio_rz_tint_isr_data { +struct gpio_rz_isr_data { const struct device *gpio_dev; gpio_pin_t pin; }; -struct gpio_rz_tint_data { - struct gpio_rz_tint_isr_data tint_data[GPIO_RZ_MAX_TINT_NUM]; +struct gpio_rz_int_data { + struct gpio_rz_isr_data gpio_mapping[GPIO_RZ_MAX_INT_NUM]; uint32_t irq_set_edge; }; +struct gpio_rz_hw_config { + gpio_flags_t p_pm; + uint8_t pfc; +}; + struct gpio_rz_tint_config { void (*gpio_int_init)(void); }; -static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, uint32_t *flags); - -#ifdef CONFIG_GPIO_GET_CONFIG -static int gpio_rz_pin_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *flags) -{ - const struct gpio_rz_config *config = dev->config; - bsp_io_port_pin_t port_pin = config->fsp_port | pin; - - gpio_rz_pin_config_get_raw(port_pin, flags); - return 0; -} -#endif - /* Get previous pin's configuration, used by pin_configure/pin_interrupt_configure api */ -static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, uint32_t *flags) +static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, struct gpio_rz_hw_config *flags) { bsp_io_port_t port = (port_pin >> 8U) & 0xFF; gpio_pin_t pin = port_pin & 0xFF; - volatile uint8_t *p_p = GPIO_RZ_IOPORT_P_REG_BASE_GET; - volatile uint16_t *p_pm = GPIO_RZ_IOPORT_PM_REG_BASE_GET; + volatile uint8_t *p_p = GPIO_RZ_IOPORT_P_REG_GET(port, pin); + volatile uint16_t *p_pm = GPIO_RZ_IOPORT_PM_REG_GET(port, pin); + volatile uint32_t *p_pfc = GPIO_RZ_IOPORT_PFC_REG_GET(port, pin); - uint8_t adr_offset; uint8_t p_value; uint16_t pm_value; - - adr_offset = (uint8_t)GPIO_RZ_REG_OFFSET(port, pin); - - p_p = &p_p[adr_offset]; - p_pm = &p_pm[adr_offset]; + uint32_t pfc_value; p_value = GPIO_RZ_P_VALUE_GET(*p_p, pin); pm_value = GPIO_RZ_PM_VALUE_GET(*p_pm, pin); + pfc_value = GPIO_RZ_PFC_VALUE_GET(*p_pfc, pin); + + flags->p_pm = 0; + flags->pfc = 0; if (p_value) { - *flags |= GPIO_OUTPUT_INIT_HIGH; + flags->p_pm |= GPIO_OUTPUT_INIT_HIGH; } else { - *flags |= GPIO_OUTPUT_INIT_LOW; + flags->p_pm |= GPIO_OUTPUT_INIT_LOW; } - *flags |= ((pm_value << 16)); + flags->p_pm |= (pm_value << 16); + flags->pfc |= pfc_value; + return 0; +} + +#ifdef CONFIG_GPIO_GET_CONFIG +static int gpio_rz_pin_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *flags) +{ + const struct gpio_rz_config *config = dev->config; + bsp_io_port_pin_t port_pin = config->fsp_port | pin; + struct gpio_rz_hw_config hw_flags; + + gpio_rz_pin_config_get_raw(port_pin, &hw_flags); + *flags = hw_flags.p_pm; + return 0; } +#endif static int gpio_rz_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) { @@ -101,14 +120,14 @@ static int gpio_rz_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_ struct gpio_rz_data *data = dev->data; bsp_io_port_pin_t port_pin = config->fsp_port | pin; uint32_t ioport_config_data = 0; - gpio_flags_t pre_flags; + struct gpio_rz_hw_config pre_flags; fsp_err_t err; gpio_rz_pin_config_get_raw(port_pin, &pre_flags); if (!flags) { /* Disconnect mode */ - ioport_config_data = 0; + GPIO_RZ_PIN_DISCONNECT(config->fsp_port, pin); } else if (!(flags & GPIO_OPEN_DRAIN)) { /* PM register */ ioport_config_data &= GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET; @@ -124,7 +143,7 @@ static int gpio_rz_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_ } /* P register */ if (!(flags & (GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOW))) { - flags |= pre_flags & (GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOW); + flags |= pre_flags.p_pm & (GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOW); } if (flags & GPIO_OUTPUT_INIT_HIGH) { @@ -136,21 +155,36 @@ static int gpio_rz_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_ if (flags & GPIO_PULL_UP) { ioport_config_data |= IOPORT_CFG_PULLUP_ENABLE; } else if (flags & GPIO_PULL_DOWN) { - ioport_config_data |= IOPORT_CFG_PULLUP_ENABLE; + ioport_config_data |= IOPORT_CFG_PULLDOWN_ENABLE; } - /* ISEL register */ + /* + * Interrupt register + * RZG: ISEL + * RZTN: PMC + */ if (flags & GPIO_INT_ENABLE) { ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_INT_ENABLE; } else if (flags & GPIO_INT_DISABLE) { ioport_config_data &= GPIO_RZ_PIN_CONFIGURE_INT_DISABLE; } - /* Drive Ability register */ - ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_GET_DRIVE_ABILITY(flags); - - /* Filter register, see in renesas-rz-gpio-ioport.h */ - ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_GET_FILTER(flags); + /* + * Drive ability register + * RZG: IOLH + * RZTN: DRCTL + */ + ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_GET(flags); + + /* PFC register */ + ioport_config_data |= GPIO_RZ_IOPORT_PFC_SET(pre_flags.pfc); + + /* + * Specific register + * RZG: FILONOFF, FILNUM, FILCLKSEL + * RZTN: RSELP + */ + ioport_config_data |= GPIO_RZ_PIN_SPECIAL_FLAG_GET(flags); } else { return -ENOTSUP; } @@ -228,7 +262,7 @@ static int gpio_rz_port_toggle_bits(const struct device *dev, gpio_port_pins_t p const struct gpio_rz_config *config = dev->config; struct gpio_rz_data *data = dev->data; bsp_io_port_pin_t port_pin; - gpio_flags_t pre_flags; + struct gpio_rz_hw_config pre_flags; ioport_size_t value = 0; fsp_err_t err; @@ -236,9 +270,9 @@ static int gpio_rz_port_toggle_bits(const struct device *dev, gpio_port_pins_t p if (pins & (1U << idx)) { port_pin = config->fsp_port | idx; gpio_rz_pin_config_get_raw(port_pin, &pre_flags); - if (pre_flags & GPIO_OUTPUT_INIT_HIGH) { + if (pre_flags.p_pm & GPIO_OUTPUT_INIT_HIGH) { value &= (1U << idx); - } else if (pre_flags & GPIO_OUTPUT_INIT_LOW) { + } else if (pre_flags.p_pm & GPIO_OUTPUT_INIT_LOW) { value |= (1U << idx); } } @@ -251,60 +285,99 @@ static int gpio_rz_port_toggle_bits(const struct device *dev, gpio_port_pins_t p return 0; } -#define GPIO_RZ_HAS_INTERRUPT DT_HAS_COMPAT_STATUS_OKAY(renesas_rz_gpio_int) +#define GPIO_RZ_HAS_INTERRUPT \ + DT_HAS_COMPAT_STATUS_OKAY(renesas_rz_gpio_int) | \ + DT_HAS_COMPAT_STATUS_OKAY(renesas_rz_ext_irq) #if GPIO_RZ_HAS_INTERRUPT -static int gpio_rz_int_disable(const struct device *dev, uint8_t tint_num) +static int gpio_rz_int_disable(const struct device *dev, const struct device *gpio_dev, + uint8_t int_num, gpio_pin_t pin) { - struct gpio_rz_tint_data *data = dev->data; - volatile uint32_t *tssr = &R_INTC_IM33->TSSR0; - volatile uint32_t *titsr = &R_INTC_IM33->TITSR0; - volatile uint32_t *tscr = &R_INTC_IM33->TSCR; + +#if (defined(CONFIG_SOC_SERIES_RZG3S) || defined(CONFIG_SOC_SERIES_RZA3UL)) + volatile uint32_t *tssr = &R_INTC->TSSR0; + volatile uint32_t *titsr = &R_INTC->TITSR0; + volatile uint32_t *tscr = &R_INTC->TSCR; + struct gpio_rz_int_data *data = dev->data; /* Get register offset base on interrupt number. */ - tssr = &tssr[tint_num / 4]; - titsr = &titsr[tint_num / 16]; + tssr = &tssr[int_num / 4]; + titsr = &titsr[int_num / 16]; - irq_disable(GPIO_RZ_TINT_IRQ_GET(tint_num)); + irq_disable(GPIO_RZ_TINT_IRQ_GET(int_num)); /* Disable interrupt and clear interrupt source. */ - *tssr &= ~(0xFF << GPIO_RZ_TSSR_OFFSET(tint_num)); + *tssr &= ~(0xFF << GPIO_RZ_TSSR_OFFSET(int_num)); /* Reset interrupt dectect type to default. */ - *titsr &= ~(0x3 << GPIO_RZ_TITSR_OFFSET(tint_num)); + *titsr &= ~(0x3 << GPIO_RZ_TITSR_OFFSET(int_num)); /* Clear interrupt detection status. */ - if (data->irq_set_edge & BIT(tint_num)) { - *tscr &= ~BIT(tint_num); - data->irq_set_edge &= ~BIT(tint_num); + if (data->irq_set_edge & BIT(int_num)) { + *tscr &= ~BIT(int_num); + data->irq_set_edge &= ~BIT(int_num); + } + + data->gpio_mapping[int_num].gpio_dev = NULL; + data->gpio_mapping[int_num].pin = UINT8_MAX; + +#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L) + + const struct gpio_rz_config *gpio_config = gpio_dev->config; + const struct device *eirq_dev = gpio_config->eirq_dev[pin]; + + if (device_is_ready(eirq_dev)) { + intc_rz_ext_irq_disable(eirq_dev); } - data->tint_data[tint_num].gpio_dev = NULL; - data->tint_data[tint_num].pin = UINT8_MAX; + +#endif /* CONFIG_SOC_SERIES_* */ return 0; } static int gpio_rz_int_enable(const struct device *int_dev, const struct device *gpio_dev, - uint8_t tint_num, uint8_t irq_type, gpio_pin_t pin) + uint8_t int_num, uint8_t irq_type, gpio_pin_t pin) { - struct gpio_rz_tint_data *int_data = int_dev->data; + if (irq_type == GPIO_RZ_INT_UNSUPPORTED) { + return -ENOTSUP; + } + const struct gpio_rz_config *gpio_config = gpio_dev->config; - volatile uint32_t *tssr = &R_INTC_IM33->TSSR0; - volatile uint32_t *titsr = &R_INTC_IM33->TITSR0; - tssr = &tssr[tint_num / 4]; - titsr = &titsr[tint_num / 16]; +#if (defined(CONFIG_SOC_SERIES_RZG3S) || defined(CONFIG_SOC_SERIES_RZA3UL)) + volatile uint32_t *tssr = &R_INTC->TSSR0; + volatile uint32_t *titsr = &R_INTC->TITSR0; + struct gpio_rz_int_data *int_data = int_dev->data; + + tssr = &tssr[int_num / 4]; + titsr = &titsr[int_num / 16]; /* Select interrupt detect type. */ - *titsr |= (irq_type << GPIO_RZ_TITSR_OFFSET(tint_num)); + *titsr &= ~(3U << GPIO_RZ_TITSR_OFFSET(int_num)); + *titsr |= (irq_type << GPIO_RZ_TITSR_OFFSET(int_num)); /* Select interrupt source base on port and pin number.*/ - *tssr |= (GPIO_RZ_TSSR_VAL(gpio_config->port_num, pin)) << GPIO_RZ_TSSR_OFFSET(tint_num); + *tssr |= (GPIO_RZ_TSSR_VAL(gpio_config->port_num, pin)) << GPIO_RZ_TSSR_OFFSET(int_num); - if (irq_type == GPIO_RZ_TINT_EDGE_RISING || irq_type == GPIO_RZ_TINT_EDGE_FALLING) { - int_data->irq_set_edge |= BIT(tint_num); + if (irq_type == GPIO_RZ_INT_EDGE_RISING || irq_type == GPIO_RZ_INT_EDGE_FALLING) { + int_data->irq_set_edge |= BIT(int_num); /* Clear interrupt status. */ - R_INTC_IM33->TSCR &= ~BIT(tint_num); + R_INTC->TSCR &= ~BIT(int_num); } - int_data->tint_data[tint_num].gpio_dev = gpio_dev; - int_data->tint_data[tint_num].pin = pin; - irq_enable(GPIO_RZ_TINT_IRQ_GET(tint_num)); + irq_enable(GPIO_RZ_TINT_IRQ_GET(int_num)); + int_data->gpio_mapping[int_num].gpio_dev = gpio_dev; + int_data->gpio_mapping[int_num].pin = pin; + +#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L) + + const struct device *eirq_dev = gpio_config->eirq_dev[pin]; + struct gpio_rz_data *gpio_data = gpio_dev->data; + + gpio_data->pin[int_num] = pin; + if (device_is_ready(eirq_dev)) { + intc_rz_ext_irq_set_type(eirq_dev, irq_type); + intc_rz_ext_irq_enable(eirq_dev); + intc_rz_ext_irq_set_callback(eirq_dev, gpio_config->cb_list[int_num], + (void *)gpio_dev); + } + +#endif /* CONFIG_SOC_SERIES_* */ return 0; } @@ -315,54 +388,56 @@ static int gpio_rz_pin_interrupt_configure(const struct device *dev, gpio_pin_t const struct gpio_rz_config *config = dev->config; struct gpio_rz_data *data = dev->data; bsp_io_port_pin_t port_pin = config->fsp_port | pin; - uint8_t tint_num = config->tint_num[pin]; + uint8_t int_num = config->int_num[pin]; uint8_t irq_type = 0; - gpio_flags_t pre_flags = 0; + struct gpio_rz_hw_config pre_flags; k_spinlock_key_t key; + int ret = 0; - if (tint_num >= GPIO_RZ_MAX_TINT_NUM) { - LOG_DEV_ERR(dev, "Invalid TINT interrupt:%d >= %d", tint_num, GPIO_RZ_MAX_TINT_NUM); + if (int_num >= GPIO_RZ_MAX_INT_NUM) { + LOG_DEV_ERR(dev, "Invalid interrupt:%d >= %d", int_num, GPIO_RZ_MAX_INT_NUM); } if (pin > config->ngpios) { return -EINVAL; } - if (trig == GPIO_INT_TRIG_BOTH) { - return -ENOTSUP; - } - key = k_spin_lock(&data->lock); if (mode == GPIO_INT_MODE_DISABLED) { gpio_rz_pin_config_get_raw(port_pin, &pre_flags); - pre_flags |= GPIO_INT_DISABLE; - gpio_rz_pin_configure(dev, pin, pre_flags); - gpio_rz_int_disable(config->int_dev, tint_num); + pre_flags.p_pm |= GPIO_INT_DISABLE; + gpio_rz_pin_configure(dev, pin, pre_flags.p_pm); + gpio_rz_int_disable(config->int_dev, dev, int_num, pin); goto exit_unlock; } if (mode == GPIO_INT_MODE_EDGE) { - irq_type = GPIO_RZ_TINT_EDGE_RISING; if (trig == GPIO_INT_TRIG_LOW) { - irq_type = GPIO_RZ_TINT_EDGE_FALLING; + irq_type = GPIO_RZ_INT_EDGE_FALLING; + } else if (trig == GPIO_INT_TRIG_HIGH) { + irq_type = GPIO_RZ_INT_EDGE_RISING; + } else { + irq_type = GPIO_RZ_INT_BOTH_EDGE; } } else { - irq_type = GPIO_RZ_TINT_LEVEL_HIGH; if (trig == GPIO_INT_TRIG_LOW) { - irq_type = GPIO_RZ_TINT_LEVEL_LOW; + irq_type = GPIO_RZ_INT_LEVEL_LOW; + } else if (trig == GPIO_INT_TRIG_HIGH) { + irq_type = GPIO_RZ_INT_LEVEL_HIGH; } } - /* Set register ISEL */ - gpio_rz_pin_config_get_raw(port_pin, &pre_flags); - pre_flags |= GPIO_INT_ENABLE; - gpio_rz_pin_configure(dev, pin, pre_flags); - gpio_rz_int_enable(config->int_dev, dev, tint_num, irq_type, pin); + ret = gpio_rz_int_enable(config->int_dev, dev, int_num, irq_type, pin); + if (ret == 0) { + gpio_rz_pin_config_get_raw(port_pin, &pre_flags); + pre_flags.p_pm |= GPIO_INT_ENABLE; + gpio_rz_pin_configure(dev, pin, pre_flags.p_pm); + } exit_unlock: k_spin_unlock(&data->lock, key); - return 0; + return ret; } static int gpio_rz_manage_callback(const struct device *dev, struct gpio_callback *callback, @@ -373,41 +448,42 @@ static int gpio_rz_manage_callback(const struct device *dev, struct gpio_callbac return gpio_manage_callback(&data->cb, callback, set); } -static void gpio_rz_isr(const struct device *dev, uint8_t pin) +static void gpio_rz_isr(uint16_t irq, void *param) { - struct gpio_rz_data *data = dev->data; - - gpio_fire_callbacks(&data->cb, dev, BIT(pin)); -} -static void gpio_rz_tint_isr(uint16_t irq, const struct device *dev) -{ - struct gpio_rz_tint_data *data = dev->data; - volatile uint32_t *tscr = &R_INTC_IM33->TSCR; - uint8_t tint_num; +#if (defined(CONFIG_SOC_SERIES_RZG3S) || defined(CONFIG_SOC_SERIES_RZA3UL)) - tint_num = irq - GPIO_RZ_TINT_IRQ_OFFSET; + const struct device *dev = param; + struct gpio_rz_int_data *int_data = dev->data; + volatile uint32_t *tscr = &R_INTC->TSCR; - if (!(*tscr & BIT(tint_num))) { - LOG_DEV_DBG(dev, "tint:%u spurious irq, status 0", tint_num); + if (!(*tscr & BIT(irq))) { + LOG_DEV_DBG(dev, "tint:%u spurious irq, status 0", irq); return; } - if (data->irq_set_edge & BIT(tint_num)) { - *tscr &= ~BIT(tint_num); + if (int_data->irq_set_edge & BIT(irq)) { + *tscr &= ~BIT(irq); } - gpio_rz_isr(data->tint_data[tint_num].gpio_dev, data->tint_data[tint_num].pin); -} + uint8_t pin = int_data->gpio_mapping[irq].pin; + const struct device *gpio_dev = int_data->gpio_mapping[irq].gpio_dev; + struct gpio_rz_data *gpio_data = gpio_dev->data; -static int gpio_rz_int_init(const struct device *dev) -{ - const struct gpio_rz_tint_config *config = dev->config; + gpio_fire_callbacks(&gpio_data->cb, gpio_dev, BIT(pin)); - config->gpio_int_init(); - return 0; +#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L) + + const struct device *gpio_dev = (const struct device *)param; + struct gpio_rz_data *gpio_data = gpio_dev->data; + uint8_t pin = gpio_data->pin[irq]; + + gpio_fire_callbacks(&gpio_data->cb, gpio_dev, BIT(pin)); + +#endif /* CONFIG_SOC_SERIES_* */ } -#endif + +#endif /* GPIO_RZ_HAS_INTERRUPT */ static DEVICE_API(gpio, gpio_rz_driver_api) = { .pin_configure = gpio_rz_pin_configure, @@ -426,18 +502,29 @@ static DEVICE_API(gpio, gpio_rz_driver_api) = { }; /*Initialize GPIO interrupt device*/ -#define GPIO_RZ_TINT_ISR_DECLARE(irq_num, node_id) \ - static void rz_gpio_isr_##irq_num(void *param) \ +#define GPIO_RZ_ISR_DEFINE(irq_num, _) \ + static void rz_gpio_isr##irq_num(void *param) \ { \ - gpio_rz_tint_isr(DT_IRQ_BY_IDX(node_id, irq_num, irq), param); \ + gpio_rz_isr(irq_num, param); \ } -#define GPIO_RZ_TINT_ISR_INIT(node_id, irq_num) LISTIFY(irq_num, \ - GPIO_RZ_TINT_ISR_DECLARE, (), node_id) +#define GPIO_RZ_ALL_ISR_DEFINE(irq_num) LISTIFY(irq_num, GPIO_RZ_ISR_DEFINE, ()) + +#if (defined(CONFIG_SOC_SERIES_RZG3S) || defined(CONFIG_SOC_SERIES_RZA3UL)) && GPIO_RZ_HAS_INTERRUPT + +#define GPIO_RZ_INT_DEFINE(inst) .int_dev = DEVICE_DT_GET_OR_NULL(DT_INST(0, renesas_rz_gpio_int)) + +static int gpio_rz_int_init(const struct device *dev) +{ + const struct gpio_rz_tint_config *config = dev->config; + + config->gpio_int_init(); + return 0; +} #define GPIO_RZ_TINT_CONNECT(irq_num, node_id) \ IRQ_CONNECT(DT_IRQ_BY_IDX(node_id, irq_num, irq), \ - DT_IRQ_BY_IDX(node_id, irq_num, priority), rz_gpio_isr_##irq_num, \ + DT_IRQ_BY_IDX(node_id, irq_num, priority), rz_gpio_isr##irq_num, \ DEVICE_DT_GET(node_id), 0); #define GPIO_RZ_TINT_CONNECT_FUNC(node_id) \ @@ -449,18 +536,43 @@ static DEVICE_API(gpio, gpio_rz_driver_api) = { } /* Initialize GPIO device*/ #define GPIO_RZ_INT_INIT(node_id) \ - GPIO_RZ_TINT_ISR_INIT(node_id, DT_NUM_IRQS(node_id)) \ + GPIO_RZ_ALL_ISR_DEFINE(DT_NUM_IRQS(node_id)) \ GPIO_RZ_TINT_CONNECT_FUNC(node_id) \ static const struct gpio_rz_tint_config rz_gpio_tint_cfg_##node_id = { \ .gpio_int_init = rz_gpio_tint_connect_func##node_id, \ }; \ - static struct gpio_rz_tint_data rz_gpio_tint_data_##node_id = {}; \ + static struct gpio_rz_int_data rz_gpio_tint_data_##node_id = {}; \ DEVICE_DT_DEFINE(node_id, gpio_rz_int_init, NULL, &rz_gpio_tint_data_##node_id, \ &rz_gpio_tint_cfg_##node_id, POST_KERNEL, \ UTIL_DEC(CONFIG_GPIO_INIT_PRIORITY), NULL); - DT_FOREACH_STATUS_OKAY(renesas_rz_gpio_int, GPIO_RZ_INT_INIT) +#elif (defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)) && \ + GPIO_RZ_HAS_INTERRUPT + +GPIO_RZ_ALL_ISR_DEFINE(GPIO_RZ_MAX_INT_NUM) + +#define EIRQ_CB_GET(eirq_line, _) [eirq_line] = rz_gpio_isr##eirq_line + +#define EIRQ_DEV_LABEL_GET(inst, idx) CONCAT(irq, DT_INST_PROP_BY_IDX(inst, irqs, UTIL_INC(idx))) + +#define EIRQ_DEV_GET(idx, inst) \ + COND_CODE_1(DT_INST_PROP_HAS_IDX(inst, irqs, idx), \ + ([DT_INST_PROP_BY_IDX(inst, irqs, idx)] = \ + DEVICE_DT_GET_OR_NULL(DT_NODELABEL(EIRQ_DEV_LABEL_GET(inst, idx))),), \ + ()) + +#define ALL_EIRQ_DEV_GET(inst) \ + FOR_EACH_FIXED_ARG(EIRQ_DEV_GET, (), inst, \ + LISTIFY(DT_INST_PROP_LEN_OR(inst, irqs, 0), VALUE_2X, (,))) + +#define GPIO_RZ_INT_DEFINE(inst) \ + .eirq_dev = {ALL_EIRQ_DEV_GET(inst)}, \ + .cb_list = {LISTIFY(GPIO_RZ_MAX_INT_NUM, EIRQ_CB_GET, (,))} +#else +#define GPIO_RZ_INT_DEFINE(inst) +#endif /* CONFIG_SOC_SERIES_* */ + #define VALUE_2X(i, _) UTIL_X2(i) #define PIN_IRQ_GET(idx, inst) \ COND_CODE_1(DT_INST_PROP_HAS_IDX(inst, irqs, idx), \ @@ -489,9 +601,8 @@ DT_FOREACH_STATUS_OKAY(renesas_rz_gpio_int, GPIO_RZ_INT_INIT) .ngpios = (uint8_t)DT_INST_PROP(inst, ngpios), \ .fsp_cfg = &g_ioport_##inst##_cfg, \ .fsp_api = &g_ioport_on_ioport, \ - .int_dev = DEVICE_DT_GET_OR_NULL(DT_INST(0, renesas_rz_gpio_int)), \ - .tint_num = {PIN_IRQS_GET(inst)}, \ - }; \ + .int_num = {PIN_IRQS_GET(inst)}, \ + GPIO_RZ_INT_DEFINE(inst)}; \ static ioport_instance_ctrl_t g_ioport_##inst##_ctrl; \ static struct gpio_rz_data gpio_rz_##inst##_data = { \ .fsp_ctrl = &g_ioport_##inst##_ctrl, \ diff --git a/drivers/gpio/gpio_renesas_rz.h b/drivers/gpio/gpio_renesas_rz.h index 6980450f40c9..b0879cc065ee 100644 --- a/drivers/gpio/gpio_renesas_rz.h +++ b/drivers/gpio/gpio_renesas_rz.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,40 +7,108 @@ #ifndef ZEPHYR_DRIVERS_GPIO_RENESAS_RZ_H_ #define ZEPHYR_DRIVERS_GPIO_RENESAS_RZ_H_ -#include #include "r_ioport.h" -#define GPIO_RZ_IOPORT_P_REG_BASE_GET (&R_GPIO->P_20) -#define GPIO_RZ_IOPORT_PM_REG_BASE_GET (&R_GPIO->PM_20) +#define GPIO_RZ_INT_UNSUPPORTED 0xF + +#if defined(CONFIG_SOC_SERIES_RZG3S) || defined(CONFIG_SOC_SERIES_RZA3UL) +#include + +#if defined(CONFIG_SOC_SERIES_RZG3S) +#define GPIO_RZ_IOPORT_P_REG_BASE_GET (&R_GPIO->P_20) +#define GPIO_RZ_IOPORT_PM_REG_BASE_GET (&R_GPIO->PM_20) +#define GPIO_RZ_IOPORT_PFC_REG_BASE_GET (&R_GPIO->PFC_20) +#define GPIO_RZ_TINT_IRQ_OFFSET 429 +#define R_INTC R_INTC_IM33 + +#elif defined(CONFIG_SOC_SERIES_RZA3UL) +#define GPIO_RZ_IOPORT_P_REG_BASE_GET (&R_GPIO->P10) +#define GPIO_RZ_IOPORT_PM_REG_BASE_GET (&R_GPIO->PM10) +#define GPIO_RZ_IOPORT_PFC_REG_BASE_GET (&R_GPIO->PFC10) +#define GPIO_RZ_TINT_IRQ_OFFSET 476 +#define R_INTC R_INTC_IA55 +#endif + +#define GPIO_RZ_IOPORT_P_REG_GET(port, pin) (&GPIO_RZ_IOPORT_P_REG_BASE_GET[port + (pin / 4)]) +#define GPIO_RZ_IOPORT_PM_REG_GET(port, pin) (&GPIO_RZ_IOPORT_PM_REG_BASE_GET[port + (pin / 4)]) +#define GPIO_RZ_IOPORT_PFC_REG_GET(port, pin) (&GPIO_RZ_IOPORT_PFC_REG_BASE_GET[port + (pin / 4)]) -#define GPIO_RZ_REG_OFFSET(port, pin) (port + (pin / 4)) +#define GPIO_RZ_P_VALUE_GET(value, pin) ((value >> pin) & 1U) +#define GPIO_RZ_PM_VALUE_GET(value, pin) ((value >> (pin * 2)) & 3U) +#define GPIO_RZ_PFC_VALUE_GET(value, pin) ((value >> (pin * 4)) & 0xF) -#define GPIO_RZ_P_VALUE_GET(value, pin) ((value >> pin) & 1U) -#define GPIO_RZ_PM_VALUE_GET(value, pin) ((value >> (pin * 2)) & 3U) +#define GPIO_RZ_IOPORT_PFC_SET(value) (value << 24) + +#define GPIO_RZ_PIN_DISCONNECT(port, pin) /* do nothing */ #define GPIO_RZ_MAX_PORT_NUM 19 -#define GPIO_RZ_MAX_TINT_NUM 32 +#define GPIO_RZ_MAX_INT_NUM 32 -#define GPIO_RZ_TINT_IRQ_OFFSET 429 #define GPIO_RZ_TINT_IRQ_GET(tint_num) (tint_num + GPIO_RZ_TINT_IRQ_OFFSET) -#define GPIO_RZ_TINT_EDGE_RISING 0x0 -#define GPIO_RZ_TINT_EDGE_FALLING 0x1 -#define GPIO_RZ_TINT_LEVEL_HIGH 0x2 -#define GPIO_RZ_TINT_LEVEL_LOW 0x3 +#define GPIO_RZ_INT_EDGE_RISING 0x0 +#define GPIO_RZ_INT_EDGE_FALLING 0x1 +#define GPIO_RZ_INT_LEVEL_HIGH 0x2 +#define GPIO_RZ_INT_LEVEL_LOW 0x3 +#define GPIO_RZ_INT_BOTH_EDGE GPIO_RZ_INT_UNSUPPORTED #define GPIO_RZ_TSSR_VAL(port, pin) (0x80 | (gpio_rz_int[port] + pin)) #define GPIO_RZ_TSSR_OFFSET(irq) ((irq % 4) * 8) #define GPIO_RZ_TITSR_OFFSET(irq) ((irq % 16) * 2) -#define GPIO_RZ_PIN_CONFIGURE_GET_FILTER(flag) (((flags >> RZG3S_GPIO_FILTER_SHIFT) & 0x1F) << 19U) -#define GPIO_RZ_PIN_CONFIGURE_GET_DRIVE_ABILITY(flag) \ - (((flag >> RZG3S_GPIO_IOLH_SHIFT) & 0x3) << 10U) +#define GPIO_RZ_PIN_CONFIGURE_GET_FILTER(flag) (((flags >> RZ_GPIO_FILTER_SHIFT) & 0x1F) << 19U) +#define GPIO_RZ_PIN_CONFIGURE_GET(flag) (((flag >> RZ_GPIO_IOLH_SHIFT) & 0x3) << 10U) #define GPIO_RZ_PIN_CONFIGURE_INT_ENABLE IOPORT_CFG_TINT_ENABLE #define GPIO_RZ_PIN_CONFIGURE_INT_DISABLE (~(IOPORT_CFG_TINT_ENABLE)) #define GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET (~(0x3 << 2)) - +#define GPIO_RZ_PIN_SPECIAL_FLAG_GET(flag) GPIO_RZ_PIN_CONFIGURE_GET_FILTER(flag) static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 43, 47, 52, 56, 58, 63, 66, 70, 72, 76}; +#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L) +#include +#define GPIO_RZ_IOPORT_REG_REGION_GET(p) (R_BSP_IoRegionGet(p) == BSP_IO_REGION_NOT_SAFE ? 1 : 0) + +#define GPIO_RZ_IOPORT_P_REG_BASE_GET(port, pin) \ + (GPIO_RZ_IOPORT_REG_REGION_GET((port << 8U) | pin) == 1 ? &R_PORT_NSR->P[port] \ + : &R_PORT_SR->P[port]) + +#define GPIO_RZ_IOPORT_PM_REG_BASE_GET(port, pin) \ + (GPIO_RZ_IOPORT_REG_REGION_GET((port << 8U) | pin) == 1 ? &R_PORT_NSR->PM[port] \ + : &R_PORT_SR->PM[port]) + +#define GPIO_RZ_IOPORT_PFC_REG_BASE_GET(port, pin) \ + (GPIO_RZ_IOPORT_REG_REGION_GET((port << 8U) | pin) == 1 ? &R_PORT_NSR->PFC[port] \ + : &R_PORT_SR->PFC[port]) + +#define GPIO_RZ_IOPORT_P_REG_GET(port, pin) (GPIO_RZ_IOPORT_P_REG_BASE_GET(port, pin)) +#define GPIO_RZ_IOPORT_PM_REG_GET(port, pin) (GPIO_RZ_IOPORT_PM_REG_BASE_GET(port, pin)) +#define GPIO_RZ_IOPORT_PFC_REG_GET(port, pin) (GPIO_RZ_IOPORT_PFC_REG_BASE_GET(port, pin)) + +#define GPIO_RZ_P_VALUE_GET(value, pin) ((value >> pin) & 1U) +#define GPIO_RZ_PM_VALUE_GET(value, pin) ((value >> (pin * 2)) & 3U) +#define GPIO_RZ_PFC_VALUE_GET(value, pin) ((value >> (pin * 4)) & 0xF) + +#define GPIO_RZ_IOPORT_PFC_SET(value) (value << 4) + +#define GPIO_RZ_PIN_DISCONNECT(port, pin) \ + *GPIO_RZ_IOPORT_PM_REG_GET((port >> 8U), pin) &= ~(3U << (pin * 2)) + +#define GPIO_RZ_MAX_INT_NUM 16 + +#define GPIO_RZ_INT_EDGE_FALLING 0x0 +#define GPIO_RZ_INT_EDGE_RISING 0x1 +#define GPIO_RZ_INT_BOTH_EDGE 0x2 +#define GPIO_RZ_INT_LEVEL_LOW 0x3 +#define GPIO_RZ_INT_LEVEL_HIGH GPIO_RZ_INT_UNSUPPORTED + +#define GPIO_RZ_PIN_CONFIGURE_GET(flag) (((flag >> RZTN_GPIO_DRCTL_SHIFT) & 0x33) << 8U) + +#define GPIO_RZ_PIN_CONFIGURE_INT_ENABLE (1U << 3) +#define GPIO_RZ_PIN_CONFIGURE_INT_DISABLE (~(1U << 3)) +#define GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET (~(0x3 << 2)) +#define GPIO_RZ_PIN_SPECIAL_FLAG_GET(flag) IOPORT_CFG_REGION_NSAFETY + +#endif /* CONFIG_SOC_* */ + #endif /* ZEPHYR_DRIVERS_GPIO_RENESAS_RZ_H_ */ diff --git a/drivers/pinctrl/renesas/rz/Kconfig b/drivers/pinctrl/renesas/rz/Kconfig index 745496b8f170..debfef38ada0 100644 --- a/drivers/pinctrl/renesas/rz/Kconfig +++ b/drivers/pinctrl/renesas/rz/Kconfig @@ -12,7 +12,7 @@ config PINCTRL_RZT2M config PINCTRL_RENESAS_RZ bool "Renesas RZ pin controller driver" default y - depends on DT_HAS_RENESAS_RZG_PINCTRL_ENABLED + depends on DT_HAS_RENESAS_RZG_PINCTRL_ENABLED || DT_HAS_RENESAS_RZA_PINCTRL_ENABLED select USE_RZ_FSP_IOPORT help Enable Renesas RZ pinctrl driver. diff --git a/drivers/serial/uart_renesas_rz_scif.c b/drivers/serial/uart_renesas_rz_scif.c index 92fe28cdc8ff..d6348e90c162 100644 --- a/drivers/serial/uart_renesas_rz_scif.c +++ b/drivers/serial/uart_renesas_rz_scif.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * SPDX-License-Identifier: Apache-2.0 */ @@ -41,11 +41,11 @@ struct uart_rz_scif_data { }; #ifdef CONFIG_UART_INTERRUPT_DRIVEN -void scif_uart_rxi_isr(void); -void scif_uart_txi_isr(void); -void scif_uart_tei_isr(void); -void scif_uart_eri_isr(void); -void scif_uart_bri_isr(void); +void scif_uart_rxi_isr(void *irq); +void scif_uart_txi_isr(void *irq); +void scif_uart_tei_isr(void *irq); +void scif_uart_eri_isr(void *irq); +void scif_uart_bri_isr(void *irq); #endif static int uart_rz_scif_poll_in(const struct device *dev, unsigned char *c) @@ -106,10 +106,10 @@ static int uart_rz_scif_apply_config(const struct device *dev) struct uart_config *uart_config = &data->uart_config; uart_cfg_t *fsp_cfg = data->fsp_cfg; + data->fsp_ctrl->p_cfg = data->fsp_cfg; scif_baud_setting_t baud_setting; - scif_uart_extended_cfg_t config_extend; - const scif_uart_extended_cfg_t *fsp_config_extend = fsp_cfg->p_extend; + scif_uart_extended_cfg_t *fsp_extend = (scif_uart_extended_cfg_t *)fsp_cfg->p_extend; fsp_err_t fsp_err; @@ -119,7 +119,7 @@ static int uart_rz_scif_apply_config(const struct device *dev) return -EIO; } - memcpy(fsp_config_extend->p_baud_setting, &baud_setting, sizeof(scif_baud_setting_t)); + memcpy(fsp_extend->p_baud_setting, &baud_setting, sizeof(scif_baud_setting_t)); switch (uart_config->data_bits) { case UART_CFG_DATA_BITS_7: @@ -157,25 +157,21 @@ static int uart_rz_scif_apply_config(const struct device *dev) return -ENOTSUP; } - memcpy(&config_extend, fsp_config_extend->p_baud_setting, sizeof(scif_baud_setting_t)); - switch (uart_config->flow_ctrl) { case UART_CFG_FLOW_CTRL_NONE: - config_extend.flow_control = SCIF_UART_FLOW_CONTROL_NONE; - config_extend.uart_mode = SCIF_UART_MODE_RS232; - config_extend.rs485_setting.enable = SCI_UART_RS485_DISABLE; + fsp_extend->flow_control = SCIF_UART_FLOW_CONTROL_NONE; + fsp_extend->uart_mode = SCIF_UART_MODE_RS232; + fsp_extend->rs485_setting.enable = 0; break; case UART_CFG_FLOW_CTRL_RTS_CTS: - config_extend.flow_control = SCIF_UART_FLOW_CONTROL_AUTO; - config_extend.uart_mode = SCIF_UART_MODE_RS232; - config_extend.rs485_setting.enable = SCI_UART_RS485_DISABLE; + fsp_extend->flow_control = SCIF_UART_FLOW_CONTROL_AUTO; + fsp_extend->uart_mode = SCIF_UART_MODE_RS232; + fsp_extend->rs485_setting.enable = 0; break; default: return -ENOTSUP; } - memcpy(fsp_config_extend->p_baud_setting, &config_extend, sizeof(scif_baud_setting_t)); - return 0; } @@ -229,7 +225,7 @@ static int uart_rz_scif_fifo_fill(const struct device *dev, const uint8_t *tx_da fsp_ctrl->tx_src_bytes = size; fsp_ctrl->p_tx_src = tx_data; - scif_uart_txi_isr(); + scif_uart_txi_isr((void *)fsp_ctrl->p_cfg->txi_irq); return (size - fsp_ctrl->tx_src_bytes); } @@ -246,9 +242,9 @@ static int uart_rz_scif_fifo_read(const struct device *dev, uint8_t *rx_data, co /* Read all available data in the FIFO */ /* If there are more available data than required, they will be lost */ if (data->int_data.rxi_flag) { - scif_uart_rxi_isr(); + scif_uart_rxi_isr((void *)fsp_ctrl->p_cfg->rxi_irq); } else { - scif_uart_tei_isr(); + scif_uart_tei_isr((void *)fsp_ctrl->p_cfg->tei_irq); } data->int_data.rx_fifo_busy = false; @@ -353,9 +349,10 @@ static void uart_rz_scif_txi_isr(const struct device *dev) static void uart_rz_scif_tei_isr(const struct device *dev) { struct uart_rz_scif_data *data = dev->data; + scif_uart_instance_ctrl_t *fsp_ctrl = data->fsp_ctrl; if (data->int_data.tei_flag) { - scif_uart_tei_isr(); + scif_uart_tei_isr((void *)fsp_ctrl->p_cfg->tei_irq); } else { data->int_data.rxi_flag = false; data->int_data.rx_fifo_busy = true; @@ -367,12 +364,19 @@ static void uart_rz_scif_tei_isr(const struct device *dev) static void uart_rz_scif_eri_isr(const struct device *dev) { - scif_uart_eri_isr(); + struct uart_rz_scif_data *data = dev->data; + scif_uart_instance_ctrl_t *fsp_ctrl = data->fsp_ctrl; + + scif_uart_eri_isr((void *)fsp_ctrl->p_cfg->eri_irq); } static void uart_rz_scif_bri_isr(const struct device *dev) { - scif_uart_bri_isr(); + struct uart_rz_scif_data *data = dev->data; + uart_cfg_t *fsp_cfg = data->fsp_cfg; + scif_uart_extended_cfg_t *fsp_extend = (scif_uart_extended_cfg_t *)fsp_cfg->p_extend; + + scif_uart_bri_isr((void *)fsp_extend->bri_irq); } static void uart_rz_scif_event_handler(uart_callback_args_t *p_args) @@ -446,22 +450,28 @@ static int uart_rz_scif_init(const struct device *dev) return 0; } -#define UART_RZG_IRQ_CONNECT(n, irq_name, isr) \ +#ifdef CONFIG_CPU_CORTEX_M +#define GET_IRQ_FLAGS(index) 0 +#else /* Cortex-A/R */ +#define GET_IRQ_FLAGS(index) DT_INST_IRQ_BY_IDX(index, 0, flags) +#endif + +#define UART_RZ_IRQ_CONNECT(n, irq_name, isr) \ do { \ IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, irq_name, irq), \ DT_INST_IRQ_BY_NAME(n, irq_name, priority), isr, \ - DEVICE_DT_INST_GET(n), 0); \ + DEVICE_DT_INST_GET(n), GET_IRQ_FLAGS(n)); \ irq_enable(DT_INST_IRQ_BY_NAME(n, irq_name, irq)); \ } while (0) -#define UART_RZG_CONFIG_FUNC(n) \ - UART_RZG_IRQ_CONNECT(n, eri, uart_rz_scif_eri_isr); \ - UART_RZG_IRQ_CONNECT(n, rxi, uart_rz_scif_rxi_isr); \ - UART_RZG_IRQ_CONNECT(n, txi, uart_rz_scif_txi_isr); \ - UART_RZG_IRQ_CONNECT(n, tei, uart_rz_scif_tei_isr); \ - UART_RZG_IRQ_CONNECT(n, bri, uart_rz_scif_bri_isr); +#define UART_RZ_CONFIG_FUNC(n) \ + UART_RZ_IRQ_CONNECT(n, eri, uart_rz_scif_eri_isr); \ + UART_RZ_IRQ_CONNECT(n, rxi, uart_rz_scif_rxi_isr); \ + UART_RZ_IRQ_CONNECT(n, txi, uart_rz_scif_txi_isr); \ + UART_RZ_IRQ_CONNECT(n, tei, uart_rz_scif_tei_isr); \ + UART_RZ_IRQ_CONNECT(n, bri, uart_rz_scif_bri_isr); -#define UART_RZG_INIT(n) \ +#define UART_RZ_INIT(n) \ static scif_uart_instance_ctrl_t g_uart##n##_ctrl; \ static scif_baud_setting_t g_uart##n##_baud_setting; \ static scif_uart_extended_cfg_t g_uart##n##_cfg_extend = { \ @@ -470,14 +480,14 @@ static int uart_rz_scif_init(const struct device *dev) .clock = SCIF_UART_CLOCK_INT, \ .noise_cancel = SCIF_UART_NOISE_CANCELLATION_ENABLE, \ .p_baud_setting = &g_uart##n##_baud_setting, \ - .rx_fifo_trigger = SCIF_UART_RECEIVE_TRIGGER_MAX, \ + .rx_fifo_trigger = 3, \ .rts_fifo_trigger = SCIF_UART_RTS_TRIGGER_14, \ .uart_mode = SCIF_UART_MODE_RS232, \ .flow_control = SCIF_UART_FLOW_CONTROL_NONE, \ .rs485_setting = \ { \ - .enable = (sci_uart_rs485_enable_t)NULL, \ - .polarity = SCI_UART_RS485_DE_POLARITY_HIGH, \ + .enable = 0, \ + .polarity = 0, \ .de_control_pin = \ (bsp_io_port_pin_t)SCIF_UART_INVALID_16BIT_PARAM, \ }, \ @@ -519,11 +529,11 @@ static int uart_rz_scif_init(const struct device *dev) static int uart_rz_scif_init_##n(const struct device *dev) \ { \ IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, \ - (UART_RZG_CONFIG_FUNC(n);)) \ + (UART_RZ_CONFIG_FUNC(n);)) \ return uart_rz_scif_init(dev); \ } \ DEVICE_DT_INST_DEFINE(n, &uart_rz_scif_init_##n, NULL, &uart_rz_scif_data_##n, \ &uart_rz_scif_config_##n, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \ &uart_rz_scif_driver_api); -DT_INST_FOREACH_STATUS_OKAY(UART_RZG_INIT) +DT_INST_FOREACH_STATUS_OKAY(UART_RZ_INIT) diff --git a/dts/arm64/renesas/rz/rza/r9a07g063.dtsi b/dts/arm64/renesas/rz/rza/r9a07g063.dtsi new file mode 100644 index 000000000000..fd75543def8e --- /dev/null +++ b/dts/arm64/renesas/rz/rza/r9a07g063.dtsi @@ -0,0 +1,333 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +/ { + compatible = "renesas,r9a07g063"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + clock-frequency = ; + reg = <0>; + }; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&gic>; + }; + + soc { + interrupt-parent = <&gic>; + + gic: interrupt-controller@11900000 { + compatible = "arm,gic-v3", "arm,gic"; + reg = <0x11900000 0x10000>, /* GICD */ + <0x11940000 0x20000>; /* GICR */ + interrupt-controller; + #interrupt-cells = <4>; + status = "okay"; + }; + + pinctrl: pin-controller@11030000 { + compatible = "renesas,rza-pinctrl"; + reg = <0x11030000 DT_SIZE_K(64)>; + reg-names = "pinctrl"; + + gpio: gpio-common { + compatible = "renesas,rz-gpio-int"; + interrupts = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + gpio0: gpio@0 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <4>; + reg = <0x0>; + status = "disabled"; + }; + + gpio1: gpio@100 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <5>; + reg = <0x100>; + status = "disabled"; + }; + + gpio2: gpio@200 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <4>; + reg = <0x200>; + status = "disabled"; + }; + + gpio3: gpio@300 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <4>; + reg = <0x300>; + status = "disabled"; + }; + + gpio4: gpio@400 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <6>; + reg = <0x400>; + status = "disabled"; + }; + + gpio5: gpio@500 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <5>; + reg = <0x500>; + status = "disabled"; + }; + + gpio6: gpio@600 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <5>; + reg = <0x600>; + status = "disabled"; + }; + + gpio7: gpio@700 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <5>; + reg = <0x700>; + status = "disabled"; + }; + + gpio8: gpio@800 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <5>; + reg = <0x800>; + status = "disabled"; + }; + + gpio9: gpio@900 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <4>; + reg = <0x900>; + status = "disabled"; + }; + + gpio10: gpio@a00 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <5>; + reg = <0xa00>; + status = "disabled"; + }; + + gpio11: gpio@b00 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <4>; + reg = <0xb00>; + status = "disabled"; + }; + + gpio12: gpio@c00 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <2>; + reg = <0xc00>; + status = "disabled"; + }; + + gpio13: gpio@d00 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <5>; + reg = <0xd00>; + status = "disabled"; + }; + + gpio14: gpio@e00 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <3>; + reg = <0xe00>; + status = "disabled"; + }; + + gpio15: gpio@f00 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <4>; + reg = <0xf00>; + status = "disabled"; + }; + + gpio16: gpio@1000 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <2>; + reg = <0x1000>; + status = "disabled"; + }; + + gpio17: gpio@1100 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <4>; + reg = <0x1100>; + status = "disabled"; + }; + + gpio18: gpio@1200 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells=<2>; + ngpios = <6>; + reg = <0x1200>; + status = "disabled"; + }; + }; + }; + + scif0: serial@1004b800 { + compatible = "renesas,rz-scif-uart"; + channel = <0>; + reg = <0x1004b800 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "eri", "bri", "rxi", "txi", "tei"; + status = "disabled"; + }; + + scif1: serial@1004bc00 { + compatible = "renesas,rz-scif-uart"; + channel = <1>; + reg = <0x1004bc00 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "eri", "bri", "rxi", "txi", "tei"; + status = "disabled"; + }; + + scif2: serial@1004c000 { + compatible = "renesas,rz-scif-uart"; + channel = <2>; + reg = <0x1004c000 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "eri", "bri", "rxi", "txi", "tei"; + status = "disabled"; + }; + + scif3: serial@1004c400 { + compatible = "renesas,rz-scif-uart"; + channel = <3>; + reg = <0x1004c400 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "eri", "bri", "rxi", "txi", "tei"; + status = "disabled"; + }; + + scif4: serial@1004c800 { + compatible = "renesas,rz-scif-uart"; + channel = <4>; + reg = <0x1004c800 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "eri", "bri", "rxi", "txi", "tei"; + status = "disabled"; + }; + }; +}; diff --git a/dts/bindings/pinctrl/renesas,rza-pinctrl.yaml b/dts/bindings/pinctrl/renesas,rza-pinctrl.yaml new file mode 100644 index 000000000000..7b2da83da1f0 --- /dev/null +++ b/dts/bindings/pinctrl/renesas,rza-pinctrl.yaml @@ -0,0 +1,105 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: | + Below generic example shows of supported pinctrl definitions: + + #include + example_pins: device_pin { + device-pinmux { + pinmux = , + ; + bias_pull_up; + renesas,filter = RZA_FILTER_SET(RZA_FILNUM_8_STAGE,RZA_FILCLKSEL_DIV_18000); + drive-strength = <1>; + slew-rate = "fast"; + }; + + device-spins { + pins = , ; + input-enable; + renesas,filter = RZA_FILTER_SET(RZA_FILNUM_8_STAGE,RZA_FILCLKSEL_DIV_18000); + drive-strength = <2>; + slew-rate = "fast"; + }; + }; + + +compatible: renesas,rza-pinctrl + +include: base.yaml +properties: + reg: + required: true + + reg-names: + required: true + +child-binding: + description: | + This RZA pins mux/cfg nodes description. + + child-binding: + description: | + The RZA pinmux/pincfg configuration nodes description. + + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-disable + - bias-high-impedance + - bias-pull-down + - bias-pull-up + - bias-pull-pin-default + - drive-strength + - input-enable + - input-disable + - output-enable + - power-source + - low-power-enable + - low-power-disable + + properties: + pinmux: + type: array + description: | + Pinmux configuration node. + Values are constructed from GPIO port number, pin number, and + alternate function configuration number using the RZA_PINMUX() + helper macro in pinctrl_rza.h + + pins: + type: array + description: | + Special Purpose pins configuration node. + Values are define in pinctrl_rza.h. + Ex: BSP_IO_XSPI_IO0,BSP_IO_I3C_SCL,... + + drive-strength: + type: int + default: 0 + description: | + Maximum sink or source current in mA for pin which shall be selected + depending on device and pin group. + + renesas,filter: + type: int + default: 0 + description: | + Digital Noise Filter configuration for a pin which shall be defined + using RZA_FILTER_SET() helper macro in pinctrl_rza.h to specify + FILNUM and FILCLKSEL. With 24Mhz external clock: + - min debounce time will be 166.666ns for FILNUM=0 and FILCLKSEL=0 + - max debounce time will be 24ms for FILNUM=3 and FILCLKSEL=3. + This property intentionally redefined to avoid unnecessary conversation from usec to + FILNUM and FILCLKSEL values depending on external clock value as this configuration + is static. + + slew-rate: + type: string + default: "fast" + enum: + - "slow" + - "fast" + description: | + Select slew rate for pin. diff --git a/include/zephyr/dt-bindings/gpio/renesas-rz-gpio.h b/include/zephyr/dt-bindings/gpio/renesas-rz-gpio.h index 30729af98bd3..207295a1840f 100644 --- a/include/zephyr/dt-bindings/gpio/renesas-rz-gpio.h +++ b/include/zephyr/dt-bindings/gpio/renesas-rz-gpio.h @@ -6,37 +6,37 @@ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZ_GPIO_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZ_GPIO_H_ -/*********************************RZG3S*****************************************/ +/*********************************RZ/A,G,V**************************************/ /** - * @brief RZ G3S specific GPIO Flags + * @brief RZAGV specific GPIO Flags * The pin driving ability flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as * follows: - * - Bit 9..8: Pin driving ability value - * - Bit 11..10: Digital Noise Filter Clock Selection value - * - Bit 13..12: Digital Noise Filter Number value - * - Bit 14: Digital Noise Filter ON/OFF + * - Bit 8..9: Pin driving ability value + * - Bit 10: Digital Noise Filter ON/OFF + * - Bit 11..12: Digital Noise Filter Number value + * - Bit 13..14: Digital Noise Filter Clock Selection value * example: * gpio-consumer { - * out-gpios = <&port8 2 (GPIO_PULL_UP | RZG3S_GPIO_FILTER_SET(1, 3, 3))>; + * out-gpios = <&port8 2 (GPIO_PULL_UP | RZ_GPIO_FILTER_SET(1, 3, 3))>; * }; * gpio-consumer { - * out-gpios = <&port8 2 (GPIO_PULL_UP | RZG3S_GPIO_IOLH_SET(2))>; + * out-gpios = <&port8 2 (GPIO_PULL_UP | RZ_GPIO_IOLH_SET(2))>; * }; */ /* GPIO drive IOLH */ -#define RZG3S_GPIO_IOLH_SHIFT 7U -#define RZG3S_GPIO_IOLH_SET(iolh_val) (iolh_val << RZG3S_GPIO_IOLH_SHIFT) +#define RZ_GPIO_IOLH_SHIFT 8U +#define RZ_GPIO_IOLH_SET(iolh_val) (iolh_val << RZ_GPIO_IOLH_SHIFT) /* GPIO filter */ -#define RZG3S_GPIO_FILTER_SHIFT 9U -#define RZG3S_GPIO_FILNUM_SHIFT 1U -#define RZG3S_GPIO_FILCLKSEL_SHIFT 3U -#define RZG3S_GPIO_FILTER_SET(fillonoff, filnum, filclksel) \ - (((fillonoff) | ((filnum) << RZG3S_GPIO_FILNUM_SHIFT) | \ - ((filclksel) << RZG3S_GPIO_FILCLKSEL_SHIFT)) \ - << RZG3S_GPIO_FILTER_SHIFT) +#define RZ_GPIO_FILTER_SHIFT 10U +#define RZ_GPIO_FILNUM_SHIFT 1U +#define RZ_GPIO_FILCLKSEL_SHIFT 3U +#define RZ_GPIO_FILTER_SET(fillonoff, filnum, filclksel) \ + (((fillonoff) | ((filnum) << RZ_GPIO_FILNUM_SHIFT) | \ + ((filclksel) << RZ_GPIO_FILCLKSEL_SHIFT)) \ + << RZ_GPIO_FILTER_SHIFT) /*******************************************************************************/ diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza-common.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza-common.h new file mode 100644 index 000000000000..38bf44752f9c --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza-common.h @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZA_COMMON_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZA_COMMON_H_ + +/* Superset list of all possible IO ports. */ +#define PORT_00 0x0000 /* IO port 0 */ +#define PORT_01 0x0100 /* IO port 1 */ +#define PORT_02 0x0200 /* IO port 2 */ +#define PORT_03 0x0300 /* IO port 3 */ +#define PORT_04 0x0400 /* IO port 4 */ +#define PORT_05 0x0500 /* IO port 5 */ +#define PORT_06 0x0600 /* IO port 6 */ +#define PORT_07 0x0700 /* IO port 7 */ +#define PORT_08 0x0800 /* IO port 8 */ +#define PORT_09 0x0900 /* IO port 9 */ +#define PORT_10 0x0A00 /* IO port 10 */ +#define PORT_11 0x0B00 /* IO port 11 */ +#define PORT_12 0x0C00 /* IO port 12 */ +#define PORT_13 0x0D00 /* IO port 13 */ +#define PORT_14 0x0E00 /* IO port 14 */ +#define PORT_15 0x0F00 /* IO port 15 */ +#define PORT_16 0x1000 /* IO port 16 */ +#define PORT_17 0x1100 /* IO port 17 */ +#define PORT_18 0x1200 /* IO port 18 */ + +/* + * Create the value contain port/pin/function information + * + * port: port number BSP_IO_PORT_00..BSP_IO_PORT_18 + * pin: pin number + * func: pin function + */ +#define RZA_PINMUX(port, pin, func) (port | pin | (func << 4)) + +/* Special purpose port */ +#define BSP_IO_NMI 0xFFFF0100 /* NMI */ + +#define BSP_IO_TMS_SWDIO 0xFFFF0200 /* TMS_SWDIO */ + +#define BSP_IO_TDO 0xFFFF0300 /* TDO */ + +#define BSP_IO_AUDIO_CLK1 0xFFFF0400 /* AUDIO_CLK1 */ +#define BSP_IO_AUDIO_CLK2 0xFFFF0401 /* AUDIO_CLK2 */ + +#define BSP_IO_SD0_CLK 0xFFFF0600 /* CD0_CLK */ +#define BSP_IO_SD0_CMD 0xFFFF0601 /* CD0_CMD */ +#define BSP_IO_SD0_RST_N 0xFFFF0602 /* CD0_RST_N */ + +#define BSP_IO_SD0_DATA0 0xFFFF0700 /* SD0_DATA0 */ +#define BSP_IO_SD0_DATA1 0xFFFF0701 /* SD0_DATA1 */ +#define BSP_IO_SD0_DATA2 0xFFFF0702 /* SD0_DATA2 */ +#define BSP_IO_SD0_DATA3 0xFFFF0703 /* SD0_DATA3 */ +#define BSP_IO_SD0_DATA4 0xFFFF0704 /* SD0_DATA4 */ +#define BSP_IO_SD0_DATA5 0xFFFF0705 /* SD0_DATA5 */ +#define BSP_IO_SD0_DATA6 0xFFFF0706 /* SD0_DATA6 */ +#define BSP_IO_SD0_DATA7 0xFFFF0707 /* SD0_DATA7 */ + +#define BSP_IO_SD1_CLK 0xFFFF0800 /* SD1_CLK */ +#define BSP_IO_SD1_CMD 0xFFFF0801 /* SD1_CMD */ + +#define BSP_IO_SD1_DATA0 0xFFFF0900 /* SD1_DATA0 */ +#define BSP_IO_SD1_DATA1 0xFFFF0901 /* SD1_DATA1 */ +#define BSP_IO_SD1_DATA2 0xFFFF0902 /* SD1_DATA2 */ +#define BSP_IO_SD1_DATA3 0xFFFF0903 /* SD1_DATA3 */ + +#define BSP_IO_QSPI0_SPCLK 0xFFFF0A00 /* QSPI0_SPCLK */ +#define BSP_IO_QSPI0_IO0 0xFFFF0A01 /* QSPI0_IO0 */ +#define BSP_IO_QSPI0_IO1 0xFFFF0A02 /* QSPI0_IO1 */ +#define BSP_IO_QSPI0_IO2 0xFFFF0A03 /* QSPI0_IO2 */ +#define BSP_IO_QSPI0_IO3 0xFFFF0A04 /* QSPI0_IO3 */ +#define BSP_IO_QSPI0_SSL 0xFFFF0A05 /* QSPI0_SSL */ + +#define BSP_IO_OM_CS1_N 0xFFFF0B00 /* OM_CS1_N */ +#define BSP_IO_OM_DQS 0xFFFF0B01 /* OM_DQS */ +#define BSP_IO_OM_SIO4 0xFFFF0B02 /* OM_SIO4 */ +#define BSP_IO_OM_SIO5 0xFFFF0B03 /* OM_SIO5 */ +#define BSP_IO_OM_SIO6 0xFFFF0B04 /* OM_SIO6 */ +#define BSP_IO_OM_SIO7 0xFFFF0B05 /* OM_SIO7 */ + +#define BSP_IO_QSPI_RESET_N 0xFFFF0C00 /* QSPI_RESET_N */ +#define BSP_IO_QSPI_WP_N 0xFFFF0C01 /* QSPI_WP_N */ + +#define BSP_IO_WDTOVF_PERROUT_N 0xFFFF0D00 /* WDTOVF_PERROUT_N */ + +#define BSP_IO_RIIC0_SDA 0xFFFF0E00 /* RIIC0_SDA */ +#define BSP_IO_RIIC0_SCL 0xFFFF0E01 /* RIIC0_SCL */ +#define BSP_IO_RIIC1_SDA 0xFFFF0E02 /* RIIC1_SDA */ +#define BSP_IO_RIIC1_SCL 0xFFFF0E03 /* RIIC1_SCL */ + +/* FILNUM */ +#define RZA_FILNUM_4_STAGE 0 +#define RZA_FILNUM_8_STAGE 1 +#define RZA_FILNUM_12_STAGE 2 +#define RZA_FILNUM_16_STAGE 3 + +/* FILCLKSEL */ +#define RZA_FILCLKSEL_NOT_DIV 0 +#define RZA_FILCLKSEL_DIV_9000 1 +#define RZA_FILCLKSEL_DIV_18000 2 +#define RZA_FILCLKSEL_DIV_36000 3 + +#define RZA_FILTER_SET(filnum, filclksel) (((filnum) & 0x3) << 0x2) | (filclksel & 0x3) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZA_COMMON_H_ */ diff --git a/soc/renesas/rz/common/pinctrl_rza.h b/soc/renesas/rz/common/pinctrl_rza.h new file mode 100644 index 000000000000..5471a358699f --- /dev/null +++ b/soc/renesas/rz/common/pinctrl_rza.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZA_H_ +#define ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZA_H_ + +#include +#include +#include +#include "r_ioport.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Porting */ +typedef struct pinctrl_cfg_data_t { + uint32_t reserved: 4; + uint32_t pupd_reg: 6; + uint32_t iolh_reg: 6; + uint32_t pmc_reg: 1; + uint32_t sr_reg: 1; + uint32_t ien_reg: 1; + uint32_t filonoff_reg: 1; + uint32_t filnum_reg: 2; + uint32_t filclksel_reg: 2; + uint32_t pfc_reg: 3; +} pinctrl_cfg_data_t; + +typedef struct pinctrl_soc_pin_t { + bsp_io_port_pin_t port_pin; + pinctrl_cfg_data_t config; +} pinctrl_soc_pin_t; + +/* Iterate over each pinctrl-n phandle child */ +#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \ + DT_FOREACH_CHILD(DT_PHANDLE_BY_IDX(node_id, state_prop, idx), \ + Z_PINCTRL_STATE_PIN_CHILD_INIT) + +/* Iterate over each pinctrl-n phandle child */ +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_PROP_ELEM_SEP(node_id, prop, Z_PINCTRL_STATE_PIN_INIT, ())}; + +#define Z_PINCTRL_STATE_PIN_CHILD_INIT(node_id) \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, pinmux), \ + (DT_FOREACH_PROP_ELEM(node_id, pinmux, Z_PINCTRL_PINMUX_INIT)), \ + ()) \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, pins), \ + (DT_FOREACH_PROP_ELEM(node_id, pins, Z_PINCTRL_SPECIAL_PINS_INIT)), \ + ()) + +#define RZA_GET_PORT_PIN(pinmux) (pinmux & ~(0xF << 4)) +#define RZA_GET_FUNC(pinmux) ((pinmux & 0xF0) >> 4) + +#define RZA_GET_PU_PD(node_id) \ + DT_PROP(node_id, bias_pull_up) == 1 ? 1U : (DT_PROP(node_id, bias_pull_down) == 1 ? 2U : 0U) + +#define RZA_GET_FILNUM(node_id) ((DT_PROP(node_id, renesas_filter) >> 2) & 0x3) + +#define RZA_GET_FILCLKSEL(node_id) (DT_PROP(node_id, renesas_filter) & 0x3) + +#define RZA_FILTER_ON_OFF(node_id) COND_CODE_0(DT_PROP(node_id, renesas_filter), (0), (1)) + +/* Process pinmux cfg */ +#define Z_PINCTRL_PINMUX_INIT(node_id, state_prop, idx) \ + { \ + .port_pin = RZA_GET_PORT_PIN(DT_PROP_BY_IDX(node_id, state_prop, idx)), \ + .config = \ + { \ + .reserved = 0, \ + .pupd_reg = RZA_GET_PU_PD(node_id), \ + .iolh_reg = DT_PROP(node_id, drive_strength), \ + .pmc_reg = 1, \ + .sr_reg = DT_ENUM_IDX(node_id, slew_rate), \ + .ien_reg = DT_PROP(node_id, input_enable), \ + .filonoff_reg = RZA_FILTER_ON_OFF(node_id), \ + .filnum_reg = RZA_GET_FILNUM(node_id), \ + .filclksel_reg = RZA_GET_FILCLKSEL(node_id), \ + .pfc_reg = RZA_GET_FUNC(DT_PROP_BY_IDX(node_id, state_prop, idx)), \ + }, \ + }, + +#define Z_PINCTRL_SPECIAL_PINS_INIT(node_id, state_prop, idx) \ + { \ + .port_pin = DT_PROP_BY_IDX(node_id, state_prop, idx), \ + .config = \ + { \ + .reserved = 0, \ + .pupd_reg = RZA_GET_PU_PD(node_id), \ + .iolh_reg = DT_PROP(node_id, drive_strength), \ + .pmc_reg = 0, \ + .sr_reg = DT_ENUM_IDX(node_id, slew_rate), \ + .ien_reg = DT_PROP(node_id, input_enable), \ + .filonoff_reg = RZA_FILTER_ON_OFF(node_id), \ + .filnum_reg = RZA_GET_FILNUM(node_id), \ + .filclksel_reg = RZA_GET_FILCLKSEL(node_id), \ + .pfc_reg = 0, \ + }, \ + }, + +#ifdef __cplusplus +} +#endif +#endif /* ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZA_H_ */ diff --git a/soc/renesas/rz/rza3ul/CMakeLists.txt b/soc/renesas/rz/rza3ul/CMakeLists.txt new file mode 100644 index 000000000000..b7bb7ee2f2a6 --- /dev/null +++ b/soc/renesas/rz/rza3ul/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) +zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + +zephyr_include_directories(.) + +zephyr_linker_sources(SECTIONS sections.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/rz/rza3ul/Kconfig b/soc/renesas/rz/rza3ul/Kconfig new file mode 100644 index 000000000000..f5b3226633ca --- /dev/null +++ b/soc/renesas/rz/rza3ul/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RZA3UL + select ARM64 + select CPU_CORTEX_A55 + select ARM_ARCH_TIMER + select HAS_RENESAS_RZ_FSP + select SOC_EARLY_INIT_HOOK diff --git a/soc/renesas/rz/rza3ul/Kconfig.defconfig b/soc/renesas/rz/rza3ul/Kconfig.defconfig new file mode 100644 index 000000000000..6af7d5b7c9a2 --- /dev/null +++ b/soc/renesas/rz/rza3ul/Kconfig.defconfig @@ -0,0 +1,31 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RZA3UL + +config SYS_CLOCK_EXISTS + default y + +config NUM_IRQS + default 512 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 24000000 + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +DT_CHOSEN_IMAGE_ZEPHYR = zephyr,code-partition +DT_CHOSEN_SRAM_ZEPHYR = zephyr,sram + +config BUILD_OUTPUT_ADJUST_LMA + default "$(dt_chosen_partition_addr_hex,$(DT_CHOSEN_IMAGE_ZEPHYR)) - \ + $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_SRAM_ZEPHYR))" + +config BUILD_OUTPUT_ADJUST_LMA_SECTIONS + default "*;!.header" + +endif # SOC_SERIES_RZA3UL diff --git a/soc/renesas/rz/rza3ul/Kconfig.soc b/soc/renesas/rz/rza3ul/Kconfig.soc new file mode 100644 index 000000000000..f77dd2aa1d57 --- /dev/null +++ b/soc/renesas/rz/rza3ul/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RZA3UL + bool + select SOC_FAMILY_RENESAS_RZ + help + Renesas RZ/A3UL series + +config SOC_SERIES + default "rza3ul" if SOC_SERIES_RZA3UL + +config SOC_R9A07G063U02GBG + bool + select SOC_SERIES_RZA3UL + help + R9A07G063U02GBG + +config SOC + default "r9a07g063u02gbg" if SOC_R9A07G063U02GBG diff --git a/soc/renesas/rz/rza3ul/mmu_regions.c b/soc/renesas/rz/rza3ul/mmu_regions.c new file mode 100644 index 000000000000..3f07572e5804 --- /dev/null +++ b/soc/renesas/rz/rza3ul/mmu_regions.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +static const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("IO_REG", 0x10000000, 0x10000000, + MT_DEVICE_nGnRnE | MT_RW | MT_DEFAULT_SECURE_STATE), +}; + +const struct arm_mmu_config mmu_config = { + .num_regions = ARRAY_SIZE(mmu_regions), + .mmu_regions = mmu_regions, +}; diff --git a/soc/renesas/rz/rza3ul/pinctrl_soc.h b/soc/renesas/rz/rza3ul/pinctrl_soc.h new file mode 100644 index 000000000000..44733d79afdc --- /dev/null +++ b/soc/renesas/rz/rza3ul/pinctrl_soc.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_RENESAS_RZ_RZA3UL_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RZ_RZA3UL_PINCTRL_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RZ_RZA3UL_PINCTRL_SOC_H_ */ diff --git a/soc/renesas/rz/rza3ul/sections.ld b/soc/renesas/rz/rza3ul/sections.ld new file mode 100644 index 000000000000..25c35faa737c --- /dev/null +++ b/soc/renesas/rz/rza3ul/sections.ld @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +SECTION_PROLOGUE(.header, CONFIG_FLASH_BASE_ADDRESS,) +{ + QUAD(__start) + QUAD(0xFFFFFFFFFFFFFFFF-__start) + QUAD(CONFIG_SRAM_BASE_ADDRESS) + QUAD(0xFFFFFFFFFFFFFFFF-CONFIG_SRAM_BASE_ADDRESS) + QUAD(z_mapped_size) + QUAD(0xFFFFFFFFFFFFFFFF-z_mapped_size) + FILL(0x00) + . += 0x1B0; + QUAD(0x4120505346205a52) + QUAD(0x69746163696c7070) + QUAD(0x0000000000006e6f) + QUAD(0x0000000000000000) +} GROUP_LINK_IN(FLASH) + +z_mapped_size = z_mapped_end - z_mapped_start; diff --git a/soc/renesas/rz/rza3ul/soc.c b/soc/renesas/rz/rza3ul/soc.c new file mode 100644 index 000000000000..b300b61a10b9 --- /dev/null +++ b/soc/renesas/rz/rza3ul/soc.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RZ/A3UL Group + */ + +#include +#include "soc.h" + +/** System Clock Frequency (Core Clock) */ +/** TODO: bsp_clock_cfg.h should get its values from device tree? */ + +uint32_t SystemCoreClock; + +void soc_early_init_hook(void) +{ + /* Configure system clocks. */ + bsp_clock_init(); + + /* InitFialize SystemCoreClock variable. */ + SystemCoreClockUpdate(); +} diff --git a/soc/renesas/rz/rza3ul/soc.h b/soc/renesas/rz/rza3ul/soc.h new file mode 100644 index 000000000000..5df3ba6851e6 --- /dev/null +++ b/soc/renesas/rz/rza3ul/soc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_RENESAS_RZA3UL_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RZA3UL_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RZG3S_SOC_H_ */ diff --git a/soc/renesas/rz/soc.yml b/soc/renesas/rz/soc.yml index 3cc8edd8baf7..f4726185def3 100644 --- a/soc/renesas/rz/soc.yml +++ b/soc/renesas/rz/soc.yml @@ -6,3 +6,6 @@ family: - name: r9a08g045s33gbg cpuclusters: - name: cm33 + - name: rza3ul + socs: + - name: r9a07g063u02gbg diff --git a/tests/drivers/gpio/gpio_api_1pin/boards/rza3ul_smarc.overlay b/tests/drivers/gpio/gpio_api_1pin/boards/rza3ul_smarc.overlay new file mode 100644 index 000000000000..240a562fa01b --- /dev/null +++ b/tests/drivers/gpio/gpio_api_1pin/boards/rza3ul_smarc.overlay @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + led0 = &led_0; + }; + + gpio-led { + compatible = "gpio-leds"; + led_0: led_0 { + gpios = <&gpio1 3 0>; + }; + }; +}; + +&gpio{ + status = "okay"; +}; + +&gpio1 { + irqs = <3 15>; + status = "okay"; +}; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rza3ul_smarc.conf b/tests/drivers/gpio/gpio_basic_api/boards/rza3ul_smarc.conf new file mode 100644 index 000000000000..b9d02cf11d5d --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/rza3ul_smarc.conf @@ -0,0 +1 @@ +CONFIG_SKIP_PULL_TEST=y diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rza3ul_smarc.overlay b/tests/drivers/gpio/gpio_basic_api/boards/rza3ul_smarc.overlay new file mode 100644 index 000000000000..2af1444ddc94 --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/rza3ul_smarc.overlay @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + resources { + compatible = "test-gpio-basic-api"; + out-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + in-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio{ + status = "okay"; +}; + +&gpio1{ + irqs = <4 20>; + status = "okay"; +}; diff --git a/west.yml b/west.yml index c90f5fa1f73e..fcbaeea22104 100644 --- a/west.yml +++ b/west.yml @@ -219,7 +219,7 @@ manifest: - hal - name: hal_renesas path: modules/hal/renesas - revision: 3204903bdc5eda6869a40363560a69369c8d0e22 + revision: pull/82/head groups: - hal - name: hal_rpi_pico