Add TI J721e R5 and BeagleBone AI64 R5 initial support. And fix up current PINCTRL selection for other TI boards.

boards/beagle/beaglebone_ai64/Kconfig.beaglebone_ai64

@@ -0,0 +1,7 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_BEAGLEBONE_AI64
+	select SOC_J721E_MAIN_R5F0_0 if BOARD_BEAGLEBONE_AI64_J721E_MAIN_R5F0_0

boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0-pinctrl.dtsi

@@ -0,0 +1,21 @@
+/* Copyright (C) 2023 BeagleBoard.org Foundation
+ * Copyright (C) 2023 S Prashanth
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ *	Andrew Davis <afd@ti.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h>
+
+&pinctrl {
+	uart2_tx_default: uart2_tx_default {
+		/* 0x1c is address of padconfig register of p8.34 and 14 is mux mode */
+		pinmux = <K3_PINMUX(0x1c, PIN_OUTPUT, MUX_MODE_14)>;
+	};
+
+	uart2_rx_default: uart2_rx_default {
+		/* 0x14 is address of padconfig register of p8.22 and 14 is mux mode */
+		pinmux = <K3_PINMUX(0x14, PIN_INPUT, MUX_MODE_14)>;
+	};
+};

boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts

@@ -0,0 +1,57 @@
+/* Copyright (C) 2023 BeagleBoard.org Foundation
+ * Copyright (C) 2023 S Prashanth
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ *	Andrew Davis <afd@ti.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <ti/j721e_main_r5.dtsi>
+#include "beaglebone_ai64_j721e_main_r5f0_0-pinctrl.dtsi"
+#include <freq.h>
+
+/ {
+	model = "BeagleBoard.org BeagleBone AI-64";
+	compatible = "beagle,beaglebone-ai64";
+
+	chosen {
+		zephyr,sram = &atcm;
+		zephyr,console = &uart2;
+	};
+
+	cpus {
+		cpu@0 {
+			status = "okay";
+		};
+	};
+
+	ddr0: memory@a2000000 {
+		compatible = "mmio-sram";
+		reg = <0xa2000000 DT_SIZE_M(1)>;
+	};
+
+	rsc_table: memory@a2100000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0xa2100000 DT_SIZE_M(1)>;
+		zephyr,memory-region = "RSC_TABLE";
+	};
+
+	ddr1: memory@a2200000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0xa2200000 DT_SIZE_M(14)>;
+		zephyr,memory-region = "DRAM";
+	};
+};
+
+&uart2 {
+	status = "okay";
+	pinctrl-0 = <&uart2_tx_default &uart2_rx_default>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+};
+
+&systick_timer {
+	status = "okay";
+};

boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.yaml

@@ -0,0 +1,17 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: beaglebone_ai64/j721e/main_r5f0_0
+name: BeagleBone-AI64 R5
+type: mcu
+arch: arm
+ram: 32
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+supported:
+  - uart
+vendor: beagle

boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0_defconfig

@@ -0,0 +1,15 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Zephyr Kernel Configuration
+CONFIG_XIP=n
+
+# Serial Driver
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y

boards/beagle/beaglebone_ai64/board.yml

@@ -0,0 +1,5 @@
+board:
+  name: beaglebone_ai64
+  vendor: beagle
+  socs:
+  - name: j721e

boards/beagle/beaglebone_ai64/doc/index.rst

@@ -0,0 +1,129 @@
+.. _beaglebone_ai64:
+
+BeagleBone AI-64
+################
+
+Overview
+********
+
+BeagleBone AI-64 is a computational platform powered by TI J721E SoC, which is
+targeted for automotive applications.
+
+.. figure:: assets/bbai_64.webp
+   :align: center
+   :width: 600px
+   :alt: BeagleBoard.org BeagleBone AI-64
+
+Hardware
+********
+
+BeagleBone AI-64 is powered by TI J721E SoC, which has three domains (MAIN,
+MCU, WKUP). This document gives overview of Zephyr running on Cortex R5's
+in the MAIN domain.
+
+L1 Memory System
+----------------
+
+* 16 KB instruction cache.
+* 16 KB data cache.
+* 64 KB TCM.
+
+Region Address Translation
+--------------------------
+
+The RAT module performs a region based address translation. It translates a
+32-bit input address into a 48-bit output address. Any input transaction that
+starts inside of a programmed region will have its address translated, if the
+region is enabled.
+
+VIM Interrupt Controller
+------------------------
+
+The VIM aggregates device interrupts and sends them to the R5F CPU(s). The VIM
+module supports 512 interrupt inputs per R5F core. Each interrupt can be either
+a level or a pulse (both active-high). The VIM has two interrupt outputs per core
+IRQ and FIQ.
+
+Supported Features
+******************
+
+The board configuration supports,
+
++-----------+------------+-----------------------+
+| Interface | Controller | Driver/Component      |
++===========+============+=======================+
+| UART      | on-chip    | serial port-polling   |
+|           |            | serial port-interrupt |
++-----------+------------+-----------------------+
+
+Other hardwares features are currently not supported.
+
+Running Zephyr
+**************
+
+The J721E does not have a separate flash for the R5 cores. Because of this
+the A72 core has to load the program for the R5 cores to the right memory
+address, set the PC and start the processor.
+This can be done from Linux on the A72 core via remoteproc.
+
+By default the R5's Memory Protection Unit (MPU) only allows for execution of
+instructions in the ATCM/BTCM. There is also a couple regions of DRAM memory
+carved out for each R5 by Linux. These can be used for IPC (DDR0) and for
+data (DDR1). DDR1 can also be used for executable regions after programming
+the MPU.
+
+This is the memory mapping from A72 to the memory usable by the R5. Note that
+the R5 cores always see their local ATCM at address 0x00000000 and their BTCM
+at address 0x41010000. The ATCM/BTCM locations are fixed in hardware, but the
+DDR regions are by convention. If you would like to use different DRAM
+locations or sizes, you must also update for the same on the A72 software.
+(For Linux as the A72 host, this would be changed in Device Tree).
+
++------------+--------------+--------------+--------------+--------------+--------+
+| Region     | R5FSS0 Core0 | R5FSS0 Core1 | R5FSS1 Core0 | R5FSS1 Core1 | Size   |
++============+==============+==============+==============+==============+========+
+| ATCM       | 0x05c00000   | 0x05d00000   | 0x05e00000   | 0x05f00000   | 32KB   |
++------------+--------------+--------------+--------------+--------------+--------+
+| BTCM       | 0x05c10000   | 0x05d10000   | 0x05e10000   | 0x05f00000   | 32KB   |
++------------+--------------+--------------+--------------+--------------+--------+
+| DDR0       | 0xA2000000   | 0xA3000000   | 0xA4000000   | 0xA5000000   | 1MB    |
++------------+--------------+--------------+--------------+--------------+--------+
+| DDR1       | 0xA2100000   | 0xA3000000   | 0xA4100000   | 0xA5000000   | 15MB   |
++------------+--------------+--------------+--------------+--------------+--------+
+
+Steps to build and run an image
+-------------------------------
+
+Here is an example for the :zephyr:code-sample:`hello_world` application
+targeting one of the Cortex R5F on BeagleBone AI-64:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: beaglebone_ai64/j721e/main_r5f0_0
+   :goals: build
+
+To load the image:
+
+| Copy Zephyr image to the /lib/firmware/ directory.
+| ``cp build/zephyr/zephyr.elf /lib/firmware/``
+|
+| Ensure the core is not running.
+| ``echo stop > /dev/remoteproc/j7-main-r5f0_0/state``
+|
+| Configuring the image name to the remoteproc module.
+| ``echo zephyr.elf > /dev/remoteproc/j7-main-r5f0_0/firmware``
+|
+| Once the image name is configured, send the start command.
+| ``echo start > /dev/remoteproc/j7-main-r5f0_0/state``
+
+Console
+-------
+
+Zephyr on BeagleBone AI-64 J721E Cortex R5 uses UART 2 (Rx p8.22, Tx p8.34)
+as console.
+
+References
+**********
+
+* `BeagleBone AI-64 Homepage <https://www.beagleboard.org/boards/beaglebone-ai-64>`_
+* `J721E TRM <https://www.ti.com/lit/zip/spruil1>`_

boards/ti/sk_am62/sk_am62_am6234_m4_defconfig

@@ -11,9 +11,6 @@ CONFIG_CORTEX_M_SYSTICK=y
 # Zephyr Kernel Configuration
 CONFIG_XIP=n
 
-# Enable Pinctrl
-CONFIG_PINCTRL=y
-
 # Serial Driver
 CONFIG_SERIAL=y
 

drivers/serial/Kconfig.ns16550

@@ -69,6 +69,7 @@ config UART_NS16550_ACCESS_WORD_ONLY
 
 config UART_NS16550_TI_K3
 	bool "Add support for NS16550 variant specific to TI K3 SoCs"
+	select PINCTRL
 	help
 	  Enabling this configuration allows the users to use the UART port in
 	  Texas Instruments K3 SoCs by enabling a vendor specific extended register

dts/arm/ti/j721e_main_r5.dtsi

@@ -0,0 +1,85 @@
+/* Copyright (C) 2023 BeagleBoard.org Foundation
+ * Copyright (C) 2023 S Prashanth
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ *	Andrew Davis <afd@ti.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <freq.h>
+#include <arm/armv7-r.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/ti-vim.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r5";
+			reg = <0>;
+		};
+	};
+
+	atcm: memory@0 {
+		device_type = "memory";
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x00000000 DT_SIZE_K(32)>;
+		zephyr,memory-region = "ATCM";
+	};
+
+	btcm: memory@41010000 {
+		device_type = "memory";
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x41010000 DT_SIZE_K(32)>;
+		zephyr,memory-region = "BTCM";
+	};
+
+	vim: interrupt-controller@ff80000 {
+		#address-cells = <1>;
+		compatible = "ti,vim";
+		reg = <0x0ff80000 0x2800>;
+		interrupt-controller;
+		#interrupt-cells = <4>; /* {IRQ/FIQ, IRQ_NUM, IRQ_TYPE, IRQ_PRIO} */
+		status = "okay";
+	};
+
+	pinctrl: pinctrl@11c000 {
+		compatible = "ti,k3-pinctrl";
+		reg = <0x0011c000 0x2b4>;
+		status = "okay";
+	};
+
+	uart1: uart@2810000 {
+		compatible = "ns16550";
+		reg = <0x02810000 0x100>;
+		clock-frequency = <48000000>;
+		interrupts = <0 159 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart2: uart@2820000 {
+		compatible = "ns16550";
+		reg = <0x02820000 0x100>;
+		clock-frequency = <48000000>;
+		interrupts = <0 160 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	systick_timer: timer@24c0000 {
+		compatible = "ti,am654-timer";
+		reg = <0x24c0000 0x70>;
+		interrupts = <0 168 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		status = "disabled";
+	};
+};

include/zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h

@@ -39,7 +39,12 @@
 #define MUX_MODE_7		7
 #define MUX_MODE_8		8
 #define MUX_MODE_9		9
+#define MUX_MODE_10		10
+#define MUX_MODE_11		11
+#define MUX_MODE_12		12
+#define MUX_MODE_13		13
+#define MUX_MODE_14		14
 
 #define K3_PINMUX(offset, value, mux_mode)	(((offset) & 0x1fff)) ((value) | (mux_mode))
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_TI_K3_PINCTRL_H_ */

soc/ti/k3/am6x/CMakeLists.txt

@@ -18,4 +18,15 @@ elseif(CONFIG_SOC_SERIES_AM6X_M4)
   endif()
 
   set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/m4/linker.ld CACHE INTERNAL "")
+elseif(CONFIG_SOC_SERIES_AM6X_R5)
+  zephyr_sources(r5/soc.c)
+
+  zephyr_include_directories(r5)
+
+  if(CONFIG_OPENAMP_RSC_TABLE)
+    zephyr_linker_section(NAME .resource_table GROUP ROM_REGION NOINPUT)
+    zephyr_linker_section_configure(SECTION .resource_table KEEP INPUT ".resource_table*")
+  endif()
+
+  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/r5/linker.ld CACHE INTERNAL "")
 endif()