[RFC] System devicetree demo for mps2 an521 board

boards/arm/sysdt_mps2_an521/Kconfig.board

@@ -0,0 +1,21 @@
+# Copyright (c) 2018-2019 Linaro Limited
+# Copyright (c) 2022 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_SYSDT_MPS2_AN521_CPU0
+	bool "ARM Cortex-M33 SMM on V2M-MPS2 (AN521) (CPU0)"
+	depends on SOC_MPS2_AN521_CPU0
+	select QEMU_TARGET
+	select HAS_COVERAGE_SUPPORT
+
+config BOARD_SYSDT_MPS2_AN521_CPU0_NS
+	bool "ARM Cortex-M33 SMM on V2M-MPS2 (AN521) (CPU0 Non-Secure)"
+	depends on SOC_MPS2_AN521_CPU0
+	select QEMU_TARGET
+	select HAS_COVERAGE_SUPPORT
+
+config BOARD_SYSDT_MPS2_AN521_CPU1
+	bool "ARM Cortex-M33 SMM on V2M-MPS2 (AN521) CPU1"
+	depends on SOC_MPS2_AN521_CPU1
+	select QEMU_TARGET
+	select HAS_COVERAGE_SUPPORT

boards/arm/sysdt_mps2_an521/Kconfig.defconfig

@@ -0,0 +1,32 @@
+# Copyright (c) 2018-2019 Linaro Limited
+# Copyright (c) 2022 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_SYSDT_MPS2_AN521_CPU0 || BOARD_SYSDT_MPS2_AN521_CPU0_NS || BOARD_SYSDT_MPS2_AN521_CPU1
+
+# MPU-based null-pointer dereferencing detection cannot
+# be applied as the (0x0 - 0x400) is unmapped but QEMU
+# will still permit bus access.
+choice NULL_POINTER_EXCEPTION_DETECTION
+	bool
+	default NULL_POINTER_EXCEPTION_DETECTION_NONE if QEMU_TARGET
+endchoice
+
+config BOARD
+	default "mps2_an521_ns" if TRUSTED_EXECUTION_NONSECURE
+	default "mps2_an521_remote" if BOARD_SYSDT_MPS2_AN521_CPU1
+	default "mps2_an521"
+
+# By default, if we build for a Non-Secure version of the board,
+# force building with TF-M as the Secure Execution Environment.
+config BUILD_WITH_TFM
+	default y if TRUSTED_EXECUTION_NONSECURE
+
+if SERIAL
+
+config UART_INTERRUPT_DRIVEN
+	default y
+
+endif # SERIAL
+
+endif

boards/arm/sysdt_mps2_an521/board.cmake

@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: Apache-2.0
+
+set(SUPPORTED_EMU_PLATFORMS qemu)
+
+set(QEMU_CPU_TYPE_${ARCH} cortex-m33)
+set(QEMU_FLAGS_${ARCH}
+  -cpu ${QEMU_CPU_TYPE_${ARCH}}
+  -machine mps2-an521
+  -nographic
+  -m 16
+  -vga none
+  )
+board_set_debugger_ifnset(qemu)
+
+ # To enable a host tty switch between serial and pty
+ #  -chardev serial,path=/dev/ttyS0,id=hostS0
+list(APPEND QEMU_EXTRA_FLAGS -chardev pty,id=hostS0 -serial chardev:hostS0)
+
+if (CONFIG_BUILD_WITH_TFM)
+  # Override the binary used by qemu, to use the combined
+  # TF-M (Secure) & Zephyr (Non Secure) image (when running
+  # in-tree tests).
+  set(QEMU_KERNEL_OPTION "-device;loader,file=${CMAKE_BINARY_DIR}/tfm_merged.hex")
+
+elseif (CONFIG_SOC_MPS2_AN521_CPU1)
+  set(CPU0_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR}/zephyr/boards/arm/sysdt_mps2_an521/empty_cpu0-prefix/src/empty_cpu0-build/zephyr)
+  set(QEMU_KERNEL_OPTION "-device;loader,file=${CPU0_BINARY_DIR}/zephyr.elf")
+  list(APPEND QEMU_EXTRA_FLAGS "-device;loader,file=${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME}")
+endif()

boards/arm/sysdt_mps2_an521/domains/domain_cpu0.overlay

@@ -0,0 +1,16 @@
+/* HACK
+ *
+ * This hack is just in place until we have better system devicetree
+ * support for the interrupts-extended property, so that we can
+ * filter out interrupt parents which aren't relevant after converting
+ * to a regular devicetree.
+ *
+ * We add an overlay to fix up the interrupt-parent as needed for
+ * interrupt generating nodes.
+ */
+
+/ {
+	peripherals {
+		interrupt-parent = <&cpu0_nvic>;
+	};
+};

boards/arm/sysdt_mps2_an521/domains/domain_cpu0_defconfig

@@ -0,0 +1,24 @@
+#
+# Copyright (c) 2018-2019 Linaro Limited
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_SOC_SERIES_MPS2=y
+CONFIG_SOC_MPS2_AN521_CPU0=y
+CONFIG_BOARD_SYSDT_MPS2_AN521_CPU0=y
+CONFIG_RUNTIME_NMI=y
+CONFIG_ARM_TRUSTZONE_M=y
+CONFIG_ARM_MPU=y
+CONFIG_QEMU_ICOUNT_SHIFT=7
+
+# GPIOs
+CONFIG_GPIO=y
+
+# Serial
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+
+# Build a Secure firmware image
+CONFIG_TRUSTED_EXECUTION_SECURE=y

boards/arm/sysdt_mps2_an521/domains/domain_cpu0_ns_defconfig

@@ -0,0 +1,22 @@
+#
+# Copyright (c) 2018-2019 Linaro Limited
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_SOC_SERIES_MPS2=y
+CONFIG_SOC_MPS2_AN521_CPU0=y
+CONFIG_BOARD_SYSDT_MPS2_AN521_CPU0_NS=y
+CONFIG_ARM_TRUSTZONE_M=y
+CONFIG_RUNTIME_NMI=y
+CONFIG_TRUSTED_EXECUTION_NONSECURE=y
+CONFIG_ARM_MPU=y
+CONFIG_QEMU_ICOUNT_SHIFT=6
+
+# GPIOs
+CONFIG_GPIO=y
+
+# Serial
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y

boards/arm/sysdt_mps2_an521/domains/domain_cpu1_defconfig

@@ -0,0 +1,21 @@
+#
+# Copyright (c) 2018-2019 Linaro Limited
+# Copyright (c) 2021 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_SOC_SERIES_MPS2=y
+CONFIG_SOC_MPS2_AN521_CPU1=y
+CONFIG_BOARD_SYSDT_MPS2_AN521_CPU1=y
+CONFIG_RUNTIME_NMI=y
+CONFIG_ARM_MPU=y
+CONFIG_QEMU_ICOUNT_SHIFT=7
+
+# GPIOs
+CONFIG_GPIO=y
+
+# Serial
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y

boards/arm/sysdt_mps2_an521/sysdt_mps2_an521.sysdts

@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2018-2019 Linaro Limited
+ * Copyright (c) 2022 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * This file is a system devicetree for the Arm MPS2 AN521 board.
+ * It pulls in the system devicetree include file (.sysdtsi) for
+ * the SoC, and provides board-level details that are common to
+ * all CPU clusters.
+ */
+
+/dts-v1/;
+
+#include <zephyr/dt-bindings/sys/armv8-m.h>
+#include <sys/arm/mps2_an521.sysdtsi>
+
+/ {
+	aliases {
+		led0 = &led_0;
+		led1 = &led_1;
+		sw0 = &button_0;
+		sw1 = &button_1;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led_0: led-0 {
+			gpios = <&gpio_led0 0>;
+			label = "USERLED0";
+		};
+		led_1: led-1 {
+			gpios = <&gpio_led0 1>;
+			label = "USERLED1";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+		button_0: button-0 {
+			label = "USERPB0";
+			gpios = <&gpio_button 0>;
+		};
+		button_1: button-1 {
+			label = "USERPB1";
+			gpios = <&gpio_button 1>;
+		};
+	};
+
+	domains {
+		/* TODO:
+		 *
+		 * - MCUboot
+		 * - TF-M
+		 */
+
+		/* Notes:
+		 *
+		 * - 'id' properties are currently required by
+		 *   the system DT spec, but zephyr isn't using them,
+		 *   so just ignore them. It's not clear what they're
+		 *   for, anyway.
+		 *
+		 * - 'memory', 'sram', etc properties are optional
+		 *   and not how zephyr is set up to configure application
+		 *   memory regions, so we don't use them.
+		 *
+		 * - For now, the defconfig for each domain is hard-coded
+	         *   to domains_{domain_name}_defconfig in the board
+		 *   directory.
+		 *
+		 *   For example, domain 'cpu0_ns' has defconfig
+		 *   'domain_cpu0_ns_defconfig'. Applying this to domains
+		 *   like MCUboot and TF-M will take some more build system
+		 *   engineering, but it's enough for a demo.
+		 */
+
+		domain_cpu0 {
+			compatible = "openamp,domain-v1";
+			cpus = <&cpu0 0x1 EXECUTION_LEVEL_SECURE>;
+			id = <1>;
+			chosen {
+				zephyr,console = &uart0;
+				zephyr,shell-uart = &uart0;
+				zephyr,flash = &cpu0_flash;
+				zephyr,sram = &cpu0_sram;
+			};
+		};
+		domain_cpu0_ns {
+			compatible = "openamp,domain-v1";
+			cpus = <&cpu0 0x1 EXECUTION_LEVEL_NONSECURE>;
+			id = <2>;
+			chosen {
+				zephyr,console = &uart0;
+				zephyr,shell-uart = &uart0;
+				zephyr,flash = &cpu0_ns_flash;
+				zephyr,sram = &cpu0_ns_sram;
+			};
+		};
+		domain_cpu1 {
+			compatible = "openamp,domain-v1";
+			cpus = <&cpu1 0x1 EXECUTION_LEVEL_NONSECURE>;
+			id = <3>;
+			chosen {
+				zephyr,console = &uart0;
+				zephyr,shell-uart = &uart0;
+				zephyr,flash = &cpu1_flash;
+				zephyr,sram = &cpu1_sram;
+			};
+		};
+	};
+
+	memory-partitions {
+		/*
+		 * The default memory partitions for different firmware
+		 * configurations for this board are all defined in child nodes.
+		 * Individual domains can refer to them as needed.
+		 *
+		 * Note: we're not bothering to define a compatible for
+		 *       this node, because our devicetree python tooling
+		 *       will generate the appropriate C macros for
+		 *       properties like 'reg' that are defined in the
+		 *       DT specification, and it seems likely that we'll
+		 *       need to revisit this approach at some point.
+		 */
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/*
+		 * cpu0 secure firmware
+		 *
+		 * If building firmware for the secure world,
+		 * dedicate all of the RAM to it. Be careful
+		 * if you're also going to use cpu1 ("remote");
+		 * conflicts are possible.
+		 */
+		cpu0_flash: memory-partition@10000000 {
+			reg = <0x10000000 DT_SIZE_M(4)>;
+		};
+
+		cpu0_sram: memory-partition@38000000 {
+			reg = <0x38000000 DT_SIZE_M(4)>;
+		};
+
+		/*
+		 * cpu0 non-secure firmware when running under TF-M.
+		 *
+		 * The memory regions defined below must match what the TF-M
+		 * project has defined for that board - a single image boot is
+		 * assumed. Please see the memory layout in:
+		 *
+		 * https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps2/an521/partition/flash_layout.h
+		 */
+
+		cpu0_ns_flash: memory-partition@100000 {
+			reg = <0x00100000 DT_SIZE_K(512)>;
+		};
+
+		cpu0_ns_sram: memory-partition@28100000 {
+			reg = <0x28100000 DT_SIZE_K(512)>;
+		};
+
+		/*
+		 * cpu1 firmware
+		 *
+		 * The memory regions defined below are selected to remain
+		 * compatible with what TF-M has defined for a single boot image,
+		 * where 468 KB memory at the bottom of the 4 MB code region is
+		 * marked as 'Unused'.
+		 */
+		cpu1_flash: memory-partition@38b000 {
+			reg = <0x0038b000 DT_SIZE_K(468)>;
+		};
+
+		cpu1_sram: memory-partition@28180000 {
+			reg = <0x28180000 DT_SIZE_K(512)>;
+		};
+	};
+};

boards/arm/sysdt_mps2_an521/sysdt_mps2_an521.yaml

@@ -0,0 +1,5 @@
+identifier: sysdt_mps2_an521
+name: ARM V2M MPS2-AN521
+simulation: qemu
+toolchain:
+  - zephyr