diff --git a/dts/bindings/adc/st,stm32-adc.yaml b/dts/bindings/adc/st,stm32-adc.yaml index 7df14029cc59..ab4af9663d22 100644 --- a/dts/bindings/adc/st,stm32-adc.yaml +++ b/dts/bindings/adc/st,stm32-adc.yaml @@ -2,7 +2,7 @@ # Copyright (c) 2018, Song Qiang # SPDX-License-Identifier: Apache-2.0 -description: ST STM32 family ADC +description: STM32 ADC compatible: "st,stm32-adc" diff --git a/dts/bindings/adc/st,stm32f1-adc.yaml b/dts/bindings/adc/st,stm32f1-adc.yaml index a8c99d677abf..7541591bff92 100644 --- a/dts/bindings/adc/st,stm32f1-adc.yaml +++ b/dts/bindings/adc/st,stm32f1-adc.yaml @@ -3,7 +3,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - ST STM32F1 family ADC + STM32F1 ADC + This compatible stands for all ADC blocks similar to the one on STM32F1, like STM32F37x. Remove the st,adc-clock-source and st,adc-prescaler property. diff --git a/dts/bindings/adc/st,stm32f4-adc.yaml b/dts/bindings/adc/st,stm32f4-adc.yaml index a24769e12006..607c8d4fa51f 100644 --- a/dts/bindings/adc/st,stm32f4-adc.yaml +++ b/dts/bindings/adc/st,stm32f4-adc.yaml @@ -3,7 +3,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - ST STM32F4 family ADC + STM32F4 ADC + This compatible stands for all ADC blocks similar to the one on STM32F4, like F2, F7 or L1. diff --git a/dts/bindings/adc/st,stm32n6-adc.yaml b/dts/bindings/adc/st,stm32n6-adc.yaml index dd791bdcc672..da83fd1b9ba2 100644 --- a/dts/bindings/adc/st,stm32n6-adc.yaml +++ b/dts/bindings/adc/st,stm32n6-adc.yaml @@ -3,7 +3,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - ST STM32N6 ADC + STM32N6 ADC + This compatible stands for STM32N6 ADC. compatible: "st,stm32n6-adc" diff --git a/dts/bindings/adc/st,stm32wb0-adc.yaml b/dts/bindings/adc/st,stm32wb0-adc.yaml index b2b6599c8344..b8b166a49f06 100644 --- a/dts/bindings/adc/st,stm32wb0-adc.yaml +++ b/dts/bindings/adc/st,stm32wb0-adc.yaml @@ -1,6 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 -description: STM32WB0 series Analog-to-Digital Converter +description: STM32WB0 Analog-to-Digital Converter compatible: "st,stm32wb0-adc" diff --git a/dts/bindings/can/st,stm32-fdcan.yaml b/dts/bindings/can/st,stm32-fdcan.yaml index f4cfb310dac6..7df1123ace95 100644 --- a/dts/bindings/can/st,stm32-fdcan.yaml +++ b/dts/bindings/can/st,stm32-fdcan.yaml @@ -1,4 +1,4 @@ -description: ST STM32 FDCAN CAN FD controller +description: STM32 FDCAN CAN FD controller compatible: "st,stm32-fdcan" diff --git a/dts/bindings/can/st,stm32h7-fdcan.yaml b/dts/bindings/can/st,stm32h7-fdcan.yaml index 14f6fad61c56..ca42621d6498 100644 --- a/dts/bindings/can/st,stm32h7-fdcan.yaml +++ b/dts/bindings/can/st,stm32h7-fdcan.yaml @@ -1,4 +1,4 @@ -description: ST STM32H7 series FDCAN CAN FD controller +description: STM32H7 series FDCAN CAN FD controller compatible: "st,stm32h7-fdcan" diff --git a/dts/bindings/clock/st,stm32-clock-mux.yaml b/dts/bindings/clock/st,stm32-clock-mux.yaml index a6a1409c69fe..afa7c9e643eb 100644 --- a/dts/bindings/clock/st,stm32-clock-mux.yaml +++ b/dts/bindings/clock/st,stm32-clock-mux.yaml @@ -3,6 +3,7 @@ description: | STM32 Clock multiplexer + Describes a clock multiplexer, such as per_ck on STM32H7 or CLK48 on STM32WB. The only property of this node is to select a clock input. diff --git a/dts/bindings/clock/st,stm32-rcc.yaml b/dts/bindings/clock/st,stm32-rcc.yaml index 4d7aa666cc34..6199eae4a9ca 100644 --- a/dts/bindings/clock/st,stm32-rcc.yaml +++ b/dts/bindings/clock/st,stm32-rcc.yaml @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32 Reset and Clock controller node. + STM32 RCC (Reset and Clock controller). + This node is in charge of system clock ('SYSCLK') source selection and controlling clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains. diff --git a/dts/bindings/clock/st,stm32c0-hsi-clock.yaml b/dts/bindings/clock/st,stm32c0-hsi-clock.yaml index a19fd6f605d0..55c918088182 100644 --- a/dts/bindings/clock/st,stm32c0-hsi-clock.yaml +++ b/dts/bindings/clock/st,stm32c0-hsi-clock.yaml @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32 HSI Clock node description for STM32C0 devices + STM32C0 HSI Clock. + On STM32C0, HSI is a 48MHz fixed clock. It also produces a HSISYS secondary clk which can be used as system clock diff --git a/dts/bindings/clock/st,stm32f0-pll-clock.yaml b/dts/bindings/clock/st,stm32f0-pll-clock.yaml index f35804b9a54b..92e6c54242bb 100644 --- a/dts/bindings/clock/st,stm32f0-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32f0-pll-clock.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - Main PLL node binding for STM32F0 and STM32F3 devices. + STM32F0/F3 Main PLL. Takes one of clk_hse or clk_hsi as input clock. diff --git a/dts/bindings/clock/st,stm32f0-rcc.yaml b/dts/bindings/clock/st,stm32f0-rcc.yaml index c85205ab8fd1..3e278b774f03 100644 --- a/dts/bindings/clock/st,stm32f0-rcc.yaml +++ b/dts/bindings/clock/st,stm32f0-rcc.yaml @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32F0 and G0 Reset and Clock controller node. + STM32F0/G0 RCC (Reset and Clock controller). + For more description confere st,stm32-rcc.yaml compatible: "st,stm32f0-rcc" diff --git a/dts/bindings/clock/st,stm32f1-clock-mco.yaml b/dts/bindings/clock/st,stm32f1-clock-mco.yaml index 5024a8166023..dc3670c76b75 100644 --- a/dts/bindings/clock/st,stm32f1-clock-mco.yaml +++ b/dts/bindings/clock/st,stm32f1-clock-mco.yaml @@ -7,7 +7,7 @@ compatible: "st,stm32f1-clock-mco" description: | - STM32 F1 series Microcontroller Clock Output (MCO) + STM32F1 Microcontroller Clock Output (MCO) The STM32F1 MCO is similar to other series but has no configurable prescaler before the output. However, note that certain inputs of diff --git a/dts/bindings/clock/st,stm32f1-pll-clock.yaml b/dts/bindings/clock/st,stm32f1-pll-clock.yaml index 04c9a8e29543..5102a362e7c8 100644 --- a/dts/bindings/clock/st,stm32f1-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32f1-pll-clock.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - Main PLL node binding for low-, medium-, high- and XL-density STM32F1 devices. + STM32F1 Main PLL for low-, medium-, high- and XL-density devices. Takes one of 'clk_hse', 'clk_hse / 2' (when 'xtpre' is set) or 'clk_hsi / 2' as input clock. diff --git a/dts/bindings/clock/st,stm32f1-rcc.yaml b/dts/bindings/clock/st,stm32f1-rcc.yaml index 00f54374335c..f013d8daa093 100644 --- a/dts/bindings/clock/st,stm32f1-rcc.yaml +++ b/dts/bindings/clock/st,stm32f1-rcc.yaml @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32F1 and STM32F37x Reset and Clock controller node. + STM32F1/F3/7x RCC (Reset and Clock controller). + Adds the ADC prescaler to the standard generic STM32 RCC. For more description confere st,stm32-rcc.yaml diff --git a/dts/bindings/clock/st,stm32f100-pll-clock.yaml b/dts/bindings/clock/st,stm32f100-pll-clock.yaml index a861a445fefa..e1898b57ef7f 100644 --- a/dts/bindings/clock/st,stm32f100-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32f100-pll-clock.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - Main PLL node binding for STM32F100 devices + STM32F100 Main PLL. Takes one of clk_hse or clk_hsi as input clock. When clk_hsi is used a fixed prescaler is applied. When input clock is hse or diff --git a/dts/bindings/clock/st,stm32f105-pll-clock.yaml b/dts/bindings/clock/st,stm32f105-pll-clock.yaml index d2f01e8989b5..d294a438a76c 100644 --- a/dts/bindings/clock/st,stm32f105-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32f105-pll-clock.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - Main PLL node binding for Connectivity line devices (STM32F105/STM32F107) + STM32F105/F107 Main PLL. Takes one of clk_hse, pll2 or clk_hsi as input clock. When clk_hsi is used a fixed prescaler is applied. When input clock is hse or diff --git a/dts/bindings/clock/st,stm32f105-pll2-clock.yaml b/dts/bindings/clock/st,stm32f105-pll2-clock.yaml index b9b881d4f107..3292ab5babcd 100644 --- a/dts/bindings/clock/st,stm32f105-pll2-clock.yaml +++ b/dts/bindings/clock/st,stm32f105-pll2-clock.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - PLL2 node binding for Connectivity line devices (STM32F105/STM32F107) + STM32F105/F107 PLL2. Takes clk_hse as input clock, using prediv as prescaler. diff --git a/dts/bindings/clock/st,stm32f2-pll-clock.yaml b/dts/bindings/clock/st,stm32f2-pll-clock.yaml index eda981c3e070..917b64768b80 100644 --- a/dts/bindings/clock/st,stm32f2-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32f2-pll-clock.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32F2 Main PLL node binding: + STM32F2 Main PLL. Takes one of clk_hse or clk_hsi as input clock. diff --git a/dts/bindings/clock/st,stm32f3-rcc.yaml b/dts/bindings/clock/st,stm32f3-rcc.yaml index 64851cdaf59d..6db97343e988 100644 --- a/dts/bindings/clock/st,stm32f3-rcc.yaml +++ b/dts/bindings/clock/st,stm32f3-rcc.yaml @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32F3 Reset and Clock controller node. + STM32F3 RCC (Reset and Clock controller). + Adds the STM32F3 ADC prescaler to the standard generic STM32 RCC. For more description confere st,stm32-rcc.yaml diff --git a/dts/bindings/clock/st,stm32f4-pll-clock.yaml b/dts/bindings/clock/st,stm32f4-pll-clock.yaml index 1346ec8a55fd..81ccb5182da4 100644 --- a/dts/bindings/clock/st,stm32f4-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32f4-pll-clock.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32F4 Main PLL node binding: + STM32F4 Main PLL. Takes one of clk_hse or clk_hsi as input clock, with an input frequency from 1 to 2 MHz. PLLM factor is used to set the input clock diff --git a/dts/bindings/clock/st,stm32f4-plli2s-clock.yaml b/dts/bindings/clock/st,stm32f4-plli2s-clock.yaml index b5e6e9cc4a32..aff08c757884 100644 --- a/dts/bindings/clock/st,stm32f4-plli2s-clock.yaml +++ b/dts/bindings/clock/st,stm32f4-plli2s-clock.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32F4 PLL I2S node binding: + STM32F4 PLL I2S. Takes same input as Main PLL. PLLM factor and PLL source are common with Main PLL diff --git a/dts/bindings/clock/st,stm32f411-plli2s-clock.yaml b/dts/bindings/clock/st,stm32f411-plli2s-clock.yaml index 459e990422dd..ed9b235d3275 100644 --- a/dts/bindings/clock/st,stm32f411-plli2s-clock.yaml +++ b/dts/bindings/clock/st,stm32f411-plli2s-clock.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32F411 PLL I2S node binding: + STM32F411 PLL I2S. Fully configurable I2S dedicated PLL. diff --git a/dts/bindings/clock/st,stm32f7-pll-clock.yaml b/dts/bindings/clock/st,stm32f7-pll-clock.yaml index 163426ef7bd3..fc1a29fca297 100644 --- a/dts/bindings/clock/st,stm32f7-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32f7-pll-clock.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32F7 Main PLL node binding: + STM32F7 Main PLL. Takes one of clk_hse or clk_hsi as input clock. diff --git a/dts/bindings/clock/st,stm32g0-hsi-clock.yaml b/dts/bindings/clock/st,stm32g0-hsi-clock.yaml index a2d523fb0eb8..bf2df7d5f02b 100644 --- a/dts/bindings/clock/st,stm32g0-hsi-clock.yaml +++ b/dts/bindings/clock/st,stm32g0-hsi-clock.yaml @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32 HSI Clock node description for STM32G0 devices + STM32G0 HSI Clock. + On STM32G0, HSI is a 16MHz fixed clock. It also produces a HSISYS secondary clk which can be used as system clock diff --git a/dts/bindings/clock/st,stm32g0-pll-clock.yaml b/dts/bindings/clock/st,stm32g0-pll-clock.yaml index c397b3c708b4..7468425de9bd 100644 --- a/dts/bindings/clock/st,stm32g0-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32g0-pll-clock.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - PLL node binding for STM32G0 devices + STM32G0 main PLL. It can take one of clk_hse or clk_hsi as input clock, with an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input diff --git a/dts/bindings/clock/st,stm32g4-pll-clock.yaml b/dts/bindings/clock/st,stm32g4-pll-clock.yaml index 735895258ab2..fb23b6217019 100644 --- a/dts/bindings/clock/st,stm32g4-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32g4-pll-clock.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - PLL node binding for STM32G4 devices + STM32G4 main PLL. It can take one of clk_hse or clk_hsi as input clock, with an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input diff --git a/dts/bindings/clock/st,stm32h7-pll-clock.yaml b/dts/bindings/clock/st,stm32h7-pll-clock.yaml index 2e441876116e..a62cd19aadb2 100644 --- a/dts/bindings/clock/st,stm32h7-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32h7-pll-clock.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - PLL node binding for STM32H7 devices + STM32H7 main PLL. It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3. Only PLL1 and PLL3 are supported for now. diff --git a/dts/bindings/clock/st,stm32h7-rcc.yaml b/dts/bindings/clock/st,stm32h7-rcc.yaml index b0e6622e6d30..f2246e757084 100644 --- a/dts/bindings/clock/st,stm32h7-rcc.yaml +++ b/dts/bindings/clock/st,stm32h7-rcc.yaml @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32 Reset and Clock controller node for STM32H7 devices + STM32H7 RCC (Reset and Clock controller). + This node is in charge of system clock ('SYSCLK') source selection and System Clock Generation. diff --git a/dts/bindings/clock/st,stm32h7rs-pll-clock.yaml b/dts/bindings/clock/st,stm32h7rs-pll-clock.yaml index cb2980dd39c5..6ff7100f3470 100644 --- a/dts/bindings/clock/st,stm32h7rs-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32h7rs-pll-clock.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - PLL node binding for STM32H7RS devices + STM32H7RS main PLL. It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3. diff --git a/dts/bindings/clock/st,stm32h7rs-rcc.yaml b/dts/bindings/clock/st,stm32h7rs-rcc.yaml index 780c84564f44..5eb4ad2f6bfb 100644 --- a/dts/bindings/clock/st,stm32h7rs-rcc.yaml +++ b/dts/bindings/clock/st,stm32h7rs-rcc.yaml @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32 Reset and Clock controller node for STM32H7RS devices + STM32H7RS RCC (Reset and Clock controller). + This node is in charge of system clock ('SYSCLK') source selection and System Clock Generation. diff --git a/dts/bindings/clock/st,stm32l0-msi-clock.yaml b/dts/bindings/clock/st,stm32l0-msi-clock.yaml index 29d8d1cdcb9c..07bf13cd1a35 100644 --- a/dts/bindings/clock/st,stm32l0-msi-clock.yaml +++ b/dts/bindings/clock/st,stm32l0-msi-clock.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2021, Linaro ltd # SPDX-License-Identifier: Apache-2.0 -description: STM32L0 and STM32L1 Multi Speed Internal Clock +description: STM32L0/L1 Multi Speed Internal Clock compatible: "st,stm32l0-msi-clock" diff --git a/dts/bindings/clock/st,stm32l0-pll-clock.yaml b/dts/bindings/clock/st,stm32l0-pll-clock.yaml index a62df8ffeae5..23a79b50d85b 100644 --- a/dts/bindings/clock/st,stm32l0-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32l0-pll-clock.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32L0 and STM32L1 Main PLL node binding: + STM32L0/L1 Main PLL. Takes one of clk_hse, clk_hsi or clk_msi as input clock, with an input frequency from 2 to 24 MHz. diff --git a/dts/bindings/clock/st,stm32l4-pll-clock.yaml b/dts/bindings/clock/st,stm32l4-pll-clock.yaml index 32ed2c4ae13a..b4fc59949c35 100644 --- a/dts/bindings/clock/st,stm32l4-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32l4-pll-clock.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - PLL node binding for STM32L4 and STM32L5 devices + STM32L4/L5 main PLL. It can be used to describe 3 different PLLs: PLL, PLLSAI1 and PLLSAI2. Only main PLL is supported for now. diff --git a/dts/bindings/clock/st,stm32mp1-rcc.yaml b/dts/bindings/clock/st,stm32mp1-rcc.yaml index 8282b46d1124..14af40db531d 100644 --- a/dts/bindings/clock/st,stm32mp1-rcc.yaml +++ b/dts/bindings/clock/st,stm32mp1-rcc.yaml @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32MP1 Reset and Clock controller node. + STM32MP1 RCC (Reset and Clock controller). + On STM32MP1 platforms, clock control configuration is performed on A9 side. As a consequence, the only property to be set in devicetree node is the clock-frequency (mlhclk_ck). diff --git a/dts/bindings/clock/st,stm32n6-cpu-clock-mux.yaml b/dts/bindings/clock/st,stm32n6-cpu-clock-mux.yaml index 653a0b0a15a5..c37cfa4c082a 100644 --- a/dts/bindings/clock/st,stm32n6-cpu-clock-mux.yaml +++ b/dts/bindings/clock/st,stm32n6-cpu-clock-mux.yaml @@ -2,9 +2,11 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32N6 CPU Clock + STM32N6 CPU Clock. + Describes the STM32N6 CPU clock multiplexer. On STM32N6, this is the CPU clock that feeds the SysTick. + For instance: &cpusw { clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>; diff --git a/dts/bindings/clock/st,stm32n6-ic-clock-mux.yaml b/dts/bindings/clock/st,stm32n6-ic-clock-mux.yaml index 2462d3166b75..fcfdc8b7a25f 100644 --- a/dts/bindings/clock/st,stm32n6-ic-clock-mux.yaml +++ b/dts/bindings/clock/st,stm32n6-ic-clock-mux.yaml @@ -2,8 +2,10 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32N6 Divider IC multiplexer - This node select a clock input and a divider. + STM32N6 Divider IC multiplexer. + + This node selects a clock input and a divider. + For instance: &ic6 { pll-src = <2>; diff --git a/dts/bindings/clock/st,stm32n6-pll-clock.yaml b/dts/bindings/clock/st,stm32n6-pll-clock.yaml index b445304aa7d7..ec14ab02b7f2 100644 --- a/dts/bindings/clock/st,stm32n6-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32n6-pll-clock.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - PLL node binding for STM32N6 devices + STM32N6 main PLL. It can be used to describe 4 different PLLs: PLL1, PLL2, PLL3 and PLL4. diff --git a/dts/bindings/clock/st,stm32n6-rcc.yaml b/dts/bindings/clock/st,stm32n6-rcc.yaml index b3e1750e42a8..2cb11669288f 100644 --- a/dts/bindings/clock/st,stm32n6-rcc.yaml +++ b/dts/bindings/clock/st,stm32n6-rcc.yaml @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32 Reset and Clock controller node for STM32N6 devices + STM32N6 RCC (Reset and Clock controller). + This node is in charge of system clock ('SYSCLK') source selection and System Clock Generation. diff --git a/dts/bindings/clock/st,stm32u0-pll-clock.yaml b/dts/bindings/clock/st,stm32u0-pll-clock.yaml index 73d9d6f7324d..5e56fc8ffe44 100644 --- a/dts/bindings/clock/st,stm32u0-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32u0-pll-clock.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32U0 Main PLL node binding: + STM32U0 Main PLL. Takes one of clk_hse, clk_hsi or clk_msi as input clock, with an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input diff --git a/dts/bindings/clock/st,stm32u5-pll-clock.yaml b/dts/bindings/clock/st,stm32u5-pll-clock.yaml index 241c8acb8419..a83d6c22dfa2 100644 --- a/dts/bindings/clock/st,stm32u5-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32u5-pll-clock.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - PLL node binding for STM32U5 devices + STM32U5 PLL. It can be used to describe 3 different PLLs: PLL1, PLL2 and PLL3. diff --git a/dts/bindings/clock/st,stm32u5-rcc.yaml b/dts/bindings/clock/st,stm32u5-rcc.yaml index 3cf2aa064a3f..505acf4bf4a3 100644 --- a/dts/bindings/clock/st,stm32u5-rcc.yaml +++ b/dts/bindings/clock/st,stm32u5-rcc.yaml @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32U5 Reset and Clock controller node. + STM32U5 RCC (Reset and Clock controller). + For more description confere st,stm32-rcc.yaml compatible: "st,stm32u5-rcc" diff --git a/dts/bindings/clock/st,stm32wb-rcc.yaml b/dts/bindings/clock/st,stm32wb-rcc.yaml index 6867f97fd00c..fa0aea63bbc2 100644 --- a/dts/bindings/clock/st,stm32wb-rcc.yaml +++ b/dts/bindings/clock/st,stm32wb-rcc.yaml @@ -3,6 +3,7 @@ description: | STM32WB Reset and Clock controller node. + For more description confere st,stm32-rcc.yaml compatible: "st,stm32wb-rcc" diff --git a/dts/bindings/clock/st,stm32wb0-rcc.yaml b/dts/bindings/clock/st,stm32wb0-rcc.yaml index bfebe71de2bd..272889ada718 100644 --- a/dts/bindings/clock/st,stm32wb0-rcc.yaml +++ b/dts/bindings/clock/st,stm32wb0-rcc.yaml @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32WB0 Reset and Clock controller node for STM32WB0 devices + STM32WB0 RCC (Reset and Clock controller). + This node is in charge of the system clock ('SYSCLK') source selection and generation. diff --git a/dts/bindings/clock/st,stm32wba-pll-clock.yaml b/dts/bindings/clock/st,stm32wba-pll-clock.yaml index 03a755f0ee3f..a47b61183f5a 100644 --- a/dts/bindings/clock/st,stm32wba-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32wba-pll-clock.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - PLL node binding for STM32WBA devices + STM32WBA PLL. It can be used to describe PLL1 diff --git a/dts/bindings/clock/st,stm32wba-rcc.yaml b/dts/bindings/clock/st,stm32wba-rcc.yaml index 797c366da11e..ea6bd32e7417 100644 --- a/dts/bindings/clock/st,stm32wba-rcc.yaml +++ b/dts/bindings/clock/st,stm32wba-rcc.yaml @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32 Reset and Clock controller node. + STM32WBA RCC (Reset and Clock controller). + This node is in charge of system clock ('SYSCLK') source selection and controlling clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains. diff --git a/dts/bindings/clock/st,stm32wl-rcc.yaml b/dts/bindings/clock/st,stm32wl-rcc.yaml index 882493ea8ea7..5d0ac82bbf45 100644 --- a/dts/bindings/clock/st,stm32wl-rcc.yaml +++ b/dts/bindings/clock/st,stm32wl-rcc.yaml @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32WL Reset and Clock controller node. + STM32WL RCC (Reset and Clock controller). + For more description confere st,stm32-rcc.yaml compatible: "st,stm32wl-rcc" diff --git a/dts/bindings/dac/st,stm32-dac.yaml b/dts/bindings/dac/st,stm32-dac.yaml index 5b142d528bc1..325ac2495a18 100644 --- a/dts/bindings/dac/st,stm32-dac.yaml +++ b/dts/bindings/dac/st,stm32-dac.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2020 Libre Solar Technologies GmbH # SPDX-License-Identifier: Apache-2.0 -description: ST STM32 family DAC +description: STM32 family DAC compatible: "st,stm32-dac" diff --git a/dts/bindings/dma/st,stm32u5-dma.yaml b/dts/bindings/dma/st,stm32u5-dma.yaml index 57b0ce0138ea..b9d6f8a041db 100644 --- a/dts/bindings/dma/st,stm32u5-dma.yaml +++ b/dts/bindings/dma/st,stm32u5-dma.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32 DMA controller for the stm32U5 soc family + STM32U5 DMA controller. It is present on stm32U5 devices as a GP DMA This controller includes several channels with different requests. diff --git a/dts/bindings/ethernet/st,stm32h7-ethernet.yaml b/dts/bindings/ethernet/st,stm32h7-ethernet.yaml index 00f2addd21c2..7878817c4fd6 100644 --- a/dts/bindings/ethernet/st,stm32h7-ethernet.yaml +++ b/dts/bindings/ethernet/st,stm32h7-ethernet.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - ST STM32H7 Ethernet + STM32H7 Ethernet This binding file describes the device tree properties required to configure and use the Ethernet controller on STM32H7 and STM32H5 series microcontrollers. diff --git a/dts/bindings/flash_controller/st,stm32f1-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32f1-flash-controller.yaml index 1ba1208d90a7..27bf78323caf 100644 --- a/dts/bindings/flash_controller/st,stm32f1-flash-controller.yaml +++ b/dts/bindings/flash_controller/st,stm32f1-flash-controller.yaml @@ -1,4 +1,4 @@ -description: STM32 F1 flash controller +description: STM32F1 flash controller compatible: "st,stm32f1-flash-controller" diff --git a/dts/bindings/flash_controller/st,stm32f2-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32f2-flash-controller.yaml index 65ab19a07144..5e3f9cef4e9e 100644 --- a/dts/bindings/flash_controller/st,stm32f2-flash-controller.yaml +++ b/dts/bindings/flash_controller/st,stm32f2-flash-controller.yaml @@ -1,4 +1,4 @@ -description: STM32 F2 flash controller +description: STM32F2 flash controller compatible: "st,stm32f2-flash-controller" diff --git a/dts/bindings/flash_controller/st,stm32f4-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32f4-flash-controller.yaml index cea824302ab9..c7ee38f5a665 100644 --- a/dts/bindings/flash_controller/st,stm32f4-flash-controller.yaml +++ b/dts/bindings/flash_controller/st,stm32f4-flash-controller.yaml @@ -1,4 +1,4 @@ -description: STM32 F4 flash controller +description: STM32F4 flash controller compatible: "st,stm32f4-flash-controller" diff --git a/dts/bindings/flash_controller/st,stm32f7-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32f7-flash-controller.yaml index cdeaa308df81..e03bca31c984 100644 --- a/dts/bindings/flash_controller/st,stm32f7-flash-controller.yaml +++ b/dts/bindings/flash_controller/st,stm32f7-flash-controller.yaml @@ -1,4 +1,4 @@ -description: STM32 F7 flash controller +description: STM32F7 flash controller compatible: "st,stm32f7-flash-controller" diff --git a/dts/bindings/flash_controller/st,stm32g0-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32g0-flash-controller.yaml index 226858e3e5b3..40a32902f0c7 100644 --- a/dts/bindings/flash_controller/st,stm32g0-flash-controller.yaml +++ b/dts/bindings/flash_controller/st,stm32g0-flash-controller.yaml @@ -1,4 +1,4 @@ -description: STM32 G0 flash controller +description: STM32G0 flash controller compatible: "st,stm32g0-flash-controller" diff --git a/dts/bindings/flash_controller/st,stm32g4-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32g4-flash-controller.yaml index 71df716072e5..e3debe1f7208 100644 --- a/dts/bindings/flash_controller/st,stm32g4-flash-controller.yaml +++ b/dts/bindings/flash_controller/st,stm32g4-flash-controller.yaml @@ -1,4 +1,4 @@ -description: STM32 G4 flash controller +description: STM32G4 flash controller compatible: "st,stm32g4-flash-controller" diff --git a/dts/bindings/flash_controller/st,stm32h7-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32h7-flash-controller.yaml index 305107cc1ca5..fff76143d1bc 100644 --- a/dts/bindings/flash_controller/st,stm32h7-flash-controller.yaml +++ b/dts/bindings/flash_controller/st,stm32h7-flash-controller.yaml @@ -1,4 +1,4 @@ -description: STM32 H7 flash controller +description: STM32H7 flash controller compatible: "st,stm32h7-flash-controller" diff --git a/dts/bindings/flash_controller/st,stm32l4-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32l4-flash-controller.yaml index 17e3e76fbafd..cb5f50b1ad88 100644 --- a/dts/bindings/flash_controller/st,stm32l4-flash-controller.yaml +++ b/dts/bindings/flash_controller/st,stm32l4-flash-controller.yaml @@ -1,4 +1,4 @@ -description: STM32 L4 flash controller +description: STM32L4 flash controller compatible: "st,stm32l4-flash-controller" diff --git a/dts/bindings/flash_controller/st,stm32l5-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32l5-flash-controller.yaml index 0f6edba9d920..bfb7938ab78f 100644 --- a/dts/bindings/flash_controller/st,stm32l5-flash-controller.yaml +++ b/dts/bindings/flash_controller/st,stm32l5-flash-controller.yaml @@ -1,4 +1,4 @@ -description: STM32 L5 flash controller +description: STM32L5 flash controller compatible: "st,stm32l5-flash-controller" diff --git a/dts/bindings/flash_controller/st,stm32wb-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32wb-flash-controller.yaml index 3234a34d8614..d72cd171e92c 100644 --- a/dts/bindings/flash_controller/st,stm32wb-flash-controller.yaml +++ b/dts/bindings/flash_controller/st,stm32wb-flash-controller.yaml @@ -1,4 +1,4 @@ -description: STM32 WB flash controller +description: STM32WB flash controller compatible: "st,stm32wb-flash-controller" diff --git a/dts/bindings/flash_controller/st,stm32wba-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32wba-flash-controller.yaml index 5ef97c10ece9..9b34765d65d4 100644 --- a/dts/bindings/flash_controller/st,stm32wba-flash-controller.yaml +++ b/dts/bindings/flash_controller/st,stm32wba-flash-controller.yaml @@ -1,4 +1,4 @@ -description: STM32 WBA flash controller +description: STM32WBA flash controller compatible: "st,stm32wba-flash-controller" diff --git a/dts/bindings/gpio/st,stm32-gpio.yaml b/dts/bindings/gpio/st,stm32-gpio.yaml index be1061ac085e..1b9ac07b4ced 100644 --- a/dts/bindings/gpio/st,stm32-gpio.yaml +++ b/dts/bindings/gpio/st,stm32-gpio.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2018, Linaro Limited # SPDX-License-Identifier: Apache-2.0 -description: STM32 GPIO node +description: STM32 GPIO controller compatible: "st,stm32-gpio" diff --git a/dts/bindings/interrupt-controller/st,stm32-exti.yaml b/dts/bindings/interrupt-controller/st,stm32-exti.yaml index c25e1bf6001f..3cb8b7586823 100644 --- a/dts/bindings/interrupt-controller/st,stm32-exti.yaml +++ b/dts/bindings/interrupt-controller/st,stm32-exti.yaml @@ -1,4 +1,4 @@ -description: STMicroelectronics STM32 family External Interrupt Controller +description: STM32 External Interrupt Controller compatible: "st,stm32-exti" diff --git a/dts/bindings/interrupt-controller/st,stm32g0-exti.yaml b/dts/bindings/interrupt-controller/st,stm32g0-exti.yaml index 6f8704416ddb..06b778a7371f 100644 --- a/dts/bindings/interrupt-controller/st,stm32g0-exti.yaml +++ b/dts/bindings/interrupt-controller/st,stm32g0-exti.yaml @@ -3,7 +3,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32 controller + STM32G0 External Interrupt Controller + This compatible stands for all interrupt-controller blocks with two dedicated Rising and Falling interrupt pending registers. diff --git a/dts/bindings/interrupt-controller/st,stm32h7rs-exti.yaml b/dts/bindings/interrupt-controller/st,stm32h7rs-exti.yaml index 1e441fb47b80..ad981acae46c 100644 --- a/dts/bindings/interrupt-controller/st,stm32h7rs-exti.yaml +++ b/dts/bindings/interrupt-controller/st,stm32h7rs-exti.yaml @@ -3,7 +3,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32 controller + STM32H7RS External Interrupt Controller + This compatible stands for the stm32H7RS interrupt-controller block with two dedicated Rising and Falling interrupt pending registers diff --git a/dts/bindings/lora/st,stm32wl-subghz-radio.yaml b/dts/bindings/lora/st,stm32wl-subghz-radio.yaml index 4066c1bcb2cf..1eaa264cf288 100644 --- a/dts/bindings/lora/st,stm32wl-subghz-radio.yaml +++ b/dts/bindings/lora/st,stm32wl-subghz-radio.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2021 Fabio Baltieri # SPDX-License-Identifier: Apache-2.0 -description: STM32WL SUBGHZ Radio +description: STM32WL Sub-GHz Radio compatible: "st,stm32wl-subghz-radio" diff --git a/dts/bindings/mdio/st,stm32-mdio.yaml b/dts/bindings/mdio/st,stm32-mdio.yaml index e536ed1c23a7..5a302d6b65e6 100644 --- a/dts/bindings/mdio/st,stm32-mdio.yaml +++ b/dts/bindings/mdio/st,stm32-mdio.yaml @@ -2,7 +2,7 @@ # Copyright (c) 2024 Analog Devices Inc. # SPDX-License-Identifier: Apache-2.0 -description: ST MDIO Features +description: STM32 MDIO Controller compatible: "st,stm32-mdio" diff --git a/dts/bindings/memory-controllers/st,stm32h7-fmc.yaml b/dts/bindings/memory-controllers/st,stm32h7-fmc.yaml index 89fa3bf2a470..a0d27b01bca0 100644 --- a/dts/bindings/memory-controllers/st,stm32h7-fmc.yaml +++ b/dts/bindings/memory-controllers/st,stm32h7-fmc.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32 Flexible Memory Controller (FMC). + STM32H7 Flexible Memory Controller (FMC). The FMC allows to interface with static-memory mapped external devices such as SRAM, NOR Flash, NAND Flash, SDRAM... diff --git a/dts/bindings/mmc/st,stm32-sdmmc.yaml b/dts/bindings/mmc/st,stm32-sdmmc.yaml index 7daf115520d4..f8c77f992ad8 100644 --- a/dts/bindings/mmc/st,stm32-sdmmc.yaml +++ b/dts/bindings/mmc/st,stm32-sdmmc.yaml @@ -1,4 +1,4 @@ -description: stm32 sdmmc disk access +description: STM32 SDMMC Disk Access compatible: "st,stm32-sdmmc" diff --git a/dts/bindings/mtd/st,stm32-nv-flash.yaml b/dts/bindings/mtd/st,stm32-nv-flash.yaml index 518c12ab4503..81a5a9447935 100644 --- a/dts/bindings/mtd/st,stm32-nv-flash.yaml +++ b/dts/bindings/mtd/st,stm32-nv-flash.yaml @@ -1,7 +1,8 @@ description: | - STM32 flash memory. This binding is for the flash memory itself, not - the flash controller peripheral. For that, see the - "st,stm32-flash-controller" binding. + STM32 flash memory. + + This binding is for the flash memory itself, not the flash controller peripheral. + For that, see the "st,stm32-flash-controller" binding. include: soc-nv-flash.yaml diff --git a/dts/bindings/mtd/st,stm32f4-nv-flash.yaml b/dts/bindings/mtd/st,stm32f4-nv-flash.yaml index 258e2c209a7c..c56dbb9b065c 100644 --- a/dts/bindings/mtd/st,stm32f4-nv-flash.yaml +++ b/dts/bindings/mtd/st,stm32f4-nv-flash.yaml @@ -1,5 +1,5 @@ description: | - ST STM32F4 family flash memory. + STM32F4 flash memory. include: st,stm32-nv-flash.yaml diff --git a/dts/bindings/mtd/st,stm32l0-nv-flash.yaml b/dts/bindings/mtd/st,stm32l0-nv-flash.yaml index 682ee48a6017..1c5ea5ecebbb 100644 --- a/dts/bindings/mtd/st,stm32l0-nv-flash.yaml +++ b/dts/bindings/mtd/st,stm32l0-nv-flash.yaml @@ -1,5 +1,5 @@ description: | - ST STM32L0 family flash memory. + STM32L0 flash memory. include: st,stm32-nv-flash.yaml diff --git a/dts/bindings/ospi/st,stm32-ospi.yaml b/dts/bindings/ospi/st,stm32-ospi.yaml index b1666d67d91e..f28abdbb1e14 100644 --- a/dts/bindings/ospi/st,stm32-ospi.yaml +++ b/dts/bindings/ospi/st,stm32-ospi.yaml @@ -2,8 +2,9 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32 OSPI device representation. Enabling a stm32 octospi node in a board - description would typically requires this: + STM32 OSPI Controller. + + Enabling a stm32 octospi node in a board description would typically requires this: &octospi { pinctrl-0 = <&octospi_clk_pe9 &octospi_ncs_pe10 &octospi_dqs_pe11 diff --git a/dts/bindings/phy/st,stm32u5-otghs-phy.yaml b/dts/bindings/phy/st,stm32u5-otghs-phy.yaml index f844d813a992..38e9a36f3e71 100644 --- a/dts/bindings/phy/st,stm32u5-otghs-phy.yaml +++ b/dts/bindings/phy/st,stm32u5-otghs-phy.yaml @@ -3,6 +3,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | + STM32U5 OTG HS PHY. + This binding is to be used by the STM32U5xx transceivers which are built-in with USB HS PHY IP and a configurable HSE clock source. diff --git a/dts/bindings/pinctrl/st,stm32-pinctrl.yaml b/dts/bindings/pinctrl/st,stm32-pinctrl.yaml index 26278a7370e0..0be9533919ef 100644 --- a/dts/bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/dts/bindings/pinctrl/st,stm32-pinctrl.yaml @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32 Pin controller Node + STM32 Pin controller. + Based on pincfg-node.yaml binding. Note: `bias-disable` and `drive-push-pull` are default pin configurations. diff --git a/dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml b/dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml index 9d6cda27307c..6de98d270587 100644 --- a/dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml +++ b/dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32F1 Pin controller Node + STM32F1 Pin controller. + Based on pincfg-node.yaml binding. Note: `bias-disable` and `drive-push-pull` are default pin configurations. diff --git a/dts/bindings/qspi/st,stm32-qspi.yaml b/dts/bindings/qspi/st,stm32-qspi.yaml index f656bd90586e..5cbdd93d9c28 100644 --- a/dts/bindings/qspi/st,stm32-qspi.yaml +++ b/dts/bindings/qspi/st,stm32-qspi.yaml @@ -2,8 +2,9 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32 QSPI device representation. A stm32 quadspi node would typically - looks to this: + STM32 QSPI Controller. + + An stm32 quadspi node would typically look like this: &quadspi { pinctrl-0 = <&quadspi_clk_pe10 &quadspi_ncs_pe11 diff --git a/dts/bindings/reset/st,stm32-rcc-rctl.yaml b/dts/bindings/reset/st,stm32-rcc-rctl.yaml index 3629db3813a9..69b0746add10 100644 --- a/dts/bindings/reset/st,stm32-rcc-rctl.yaml +++ b/dts/bindings/reset/st,stm32-rcc-rctl.yaml @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32 Reset and Clock Control (RCC) node. + STM32 Reset and Clock Control (RCC) Controller. + This node is in charge of reset control for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains. diff --git a/dts/bindings/sensor/st,stm32-digi-temp.yaml b/dts/bindings/sensor/st,stm32-digi-temp.yaml index 4faba85246dd..5c6f5c08cdbf 100644 --- a/dts/bindings/sensor/st,stm32-digi-temp.yaml +++ b/dts/bindings/sensor/st,stm32-digi-temp.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2024, Aurelien Jarno # SPDX-License-Identifier: Apache-2.0 -description: STM32 family Digital Temperature Sensor node +description: STM32 Digital Temperature Sensor. compatible: "st,stm32-digi-temp" diff --git a/dts/bindings/sensor/st,stm32-temp.yaml b/dts/bindings/sensor/st,stm32-temp.yaml index 1a53f33b43ab..118c19d74125 100644 --- a/dts/bindings/sensor/st,stm32-temp.yaml +++ b/dts/bindings/sensor/st,stm32-temp.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2021, Eug Krashtan # SPDX-License-Identifier: Apache-2.0 -description: STM32 family TEMP node +description: STM32 Internal Temperature Sensor. compatible: "st,stm32-temp" diff --git a/dts/bindings/sensor/st,stm32-vbat.yaml b/dts/bindings/sensor/st,stm32-vbat.yaml index c23b8f84a354..04616485ecb5 100644 --- a/dts/bindings/sensor/st,stm32-vbat.yaml +++ b/dts/bindings/sensor/st,stm32-vbat.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2022 STMicroelectronics # SPDX-License-Identifier: Apache-2.0 -description: STM32 family VBAT node +description: STM32 VBAT include: sensor-device.yaml diff --git a/dts/bindings/sensor/st,stm32-vref.yaml b/dts/bindings/sensor/st,stm32-vref.yaml index 7a2987871a5b..1e9a8b0de2a7 100644 --- a/dts/bindings/sensor/st,stm32-vref.yaml +++ b/dts/bindings/sensor/st,stm32-vref.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2023 Kenneth J. Miller # SPDX-License-Identifier: Apache-2.0 -description: STM32 family VREF+ node +description: STM32 VREF+. compatible: "st,stm32-vref" diff --git a/dts/bindings/sensor/st,stm32c0-temp-cal.yaml b/dts/bindings/sensor/st,stm32c0-temp-cal.yaml index d217782cadee..82dcd09821c6 100644 --- a/dts/bindings/sensor/st,stm32c0-temp-cal.yaml +++ b/dts/bindings/sensor/st,stm32c0-temp-cal.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32 family TEMP node for production calibrated sensors with a single calibration temperature. + STM32 TEMP for production calibrated sensors with a single calibration temperature. compatible: "st,stm32c0-temp-cal" diff --git a/dts/bindings/spi/st,stm32-spi-host-cmd.yaml b/dts/bindings/spi/st,stm32-spi-host-cmd.yaml index db5cb55d5f2d..944048315f65 100644 --- a/dts/bindings/spi/st,stm32-spi-host-cmd.yaml +++ b/dts/bindings/spi/st,stm32-spi-host-cmd.yaml @@ -3,6 +3,7 @@ description: | Host Command version of STM32 SPI controller. + All properties are the same, but a different driver is used. compatible: "st,stm32-spi-host-cmd" diff --git a/dts/bindings/spi/st,stm32h7-spi.yaml b/dts/bindings/spi/st,stm32h7-spi.yaml index 69f1a8c52ae7..252d6b09d4a2 100644 --- a/dts/bindings/spi/st,stm32h7-spi.yaml +++ b/dts/bindings/spi/st,stm32h7-spi.yaml @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32H7 SPI controller + STM32H7 SPI controller. + This compatible stands for all SPI hardware blocks matching the version available in STM32H7 SoCs. This version of STM32 SPI hardware block could be identified by the diff --git a/dts/bindings/tcpc/st,stm32-ucpd.yaml b/dts/bindings/tcpc/st,stm32-ucpd.yaml index 8d49b78a31a4..93b72faf0a9e 100644 --- a/dts/bindings/tcpc/st,stm32-ucpd.yaml +++ b/dts/bindings/tcpc/st,stm32-ucpd.yaml @@ -2,8 +2,9 @@ # SPDX-License-Identifier: Apache-2.0 description: | - ST STM32 family USB Type-C / Power Delivery. The default values were - taken from the LL_UCPD_StructInit function defined in the HAL. + STM32 USB Type-C / Power Delivery. + + The default values were taken from the LL_UCPD_StructInit function defined in the HAL. compatible: "st,stm32-ucpd" diff --git a/dts/bindings/timer/st,stm32-lptim.yaml b/dts/bindings/timer/st,stm32-lptim.yaml index 159d8bdff003..31e4ea0e8efd 100644 --- a/dts/bindings/timer/st,stm32-lptim.yaml +++ b/dts/bindings/timer/st,stm32-lptim.yaml @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32 lptim : low power timer + STM32 low-power timer (LPTIM). + The lptim node to be used for counting ticks during lowpower modes must be named stm32_lp_tick_source in the DTS, as follows: stm32_lp_tick_source: &lptim1 { diff --git a/dts/bindings/usb/st,stm32f4-fsotg.yaml b/dts/bindings/usb/st,stm32f4-fsotg.yaml index 7b681a362c81..2d657f700998 100644 --- a/dts/bindings/usb/st,stm32f4-fsotg.yaml +++ b/dts/bindings/usb/st,stm32f4-fsotg.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2023 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 # -description: STM32F4 SoC series OTG_FS DWC2 compatible controller +description: STM32F4 OTG_FS DWC2 compatible controller. compatible: "st,stm32f4-fsotg" diff --git a/dts/bindings/video/st,stm32-dcmi.yaml b/dts/bindings/video/st,stm32-dcmi.yaml index 8381ae0acaf2..567b8d0efa8c 100644 --- a/dts/bindings/video/st,stm32-dcmi.yaml +++ b/dts/bindings/video/st,stm32-dcmi.yaml @@ -5,7 +5,8 @@ # description: | - STMicroelectronics STM32 Digital Camera Memory Interface (DCMI). + STM32 Digital Camera Memory Interface (DCMI). + Example of node configuration at board level: &dcmi { diff --git a/dts/bindings/xspi/st,stm32-xspi.yaml b/dts/bindings/xspi/st,stm32-xspi.yaml index 388c3d20bca1..873c5c8776f6 100644 --- a/dts/bindings/xspi/st,stm32-xspi.yaml +++ b/dts/bindings/xspi/st,stm32-xspi.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 description: | - STM32 XSPI device representation. Enabling a stm32 xspi node in a board + STM32 XSPI Controller. compatible: "st,stm32-xspi"