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pfb_fir_core.mdl
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ConRadixGroup "Use specified scaling"
OutScaling "[]"
OutDataTypeStr "Inherit: Inherit from 'Constant value'"
LockScale off
SampleTime "inf"
FramePeriod "inf"
PreserveConstantTs off
}
Block {
BlockType Inport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
VarSizeSig "Inherit"
SampleTime "-1"
OutMin "[]"
OutMax "[]"
DataType "auto"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
OutDataTypeStr "Inherit: auto"
LockScale off
SignalType "auto"
SamplingMode "auto"
LatchByDelayingOutsideSignal off
LatchInputForFeedbackSignals off
Interpolate on
}
Block {
BlockType Outport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
VarSizeSig "Inherit"
SampleTime "-1"
OutMin "[]"
OutMax "[]"
DataType "auto"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
OutDataTypeStr "Inherit: auto"
LockScale off
SignalType "auto"
SamplingMode "auto"
SourceOfInitialOutputValue "Dialog"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType SubSystem
ShowPortLabels "FromPortIcon"
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
TreatAsAtomicUnit off
CheckFcnCallInpInsideContextMsg off
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Terminator
}
Block {
BlockType ToWorkspace
VariableName "simulink_output"
MaxDataPoints "1000"
Decimation "1"
SampleTime "0"
FixptAsFi off
}
}
System {
Name "pfb_fir_core"
Location [150, 135, 899, 436]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
ReportName "simulink-default.rpt"
SIDHighWatermark 16
Block {
BlockType Reference
Name " System Generator"
SID 1
Tag "genX"
Ports []
Position [112, 30, 163, 80]
ShowName off
AttributesFormatString "System\\nGenerator"
LibraryVersion "1.2"
UserDataPersistent on
UserData "DataTag0"
SourceBlock "xbsIndex_r4/ System Generator"
SourceType "Xilinx System Generator Block"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
infoedit " System Generator"
xilinxfamily "virtex5"
part "xc5vsx95t"
speed "-1"
package "ff1136"
synthesis_tool "XST"
clock_wrapper "Clock Enables"
directory "./pfb_fir_core"
proj_type "Project Navigator"
Synth_file "XST Defaults"
Impl_file "ISE Defaults"
testbench off
simulink_period "1"
sysclk_period "5"
dcm_input_clock_period "100"
incr_netlist off
trim_vbits "Everywhere in SubSystem"
dbl_ovrd "According to Block Masks"
core_generation "According to Block Masks"
run_coregen off
deprecated_control off
eval_field "0"
has_advanced_control "0"
sggui_pos "326,212,464,470"
block_type "sysgen"
block_version "10.1.3"
sg_icon_stat "51,50,0,0,token,white,0,58c5b5770fe5f7c311f53dbc6e73f0f6,right,,[ ],[ ]"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 51 51 0 0 ],[0 0 50 50 0 ],[1 1 1 ]"
");\npatch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.1"
"55 36.655 ],[0.933333 0.203922 0.141176 ]);\npatch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 3"
"6.655 26.155 ],[0.698039 0.0313725 0.219608 ]);\npatch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.15"
"5 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);\npatch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.15"
"5 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);\nfprintf('','COMMENT: end icon graph"
"ics');\nfprintf('','COMMENT: begin icon text');\n\nfprintf('','COMMENT: end icon text');"
}
Block {
BlockType Reference
Name "Band-Limited\nWhite Noise"
SID 2
Ports [0, 1]
Position [15, 165, 45, 195]
ShowName off
LibraryVersion "1.216"
SourceBlock "simulink/Sources/Band-Limited\nWhite Noise"
SourceType "Band-Limited White Noise."
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Cov "(16/128)^2"
Ts "1"
seed "[23341]"
VectorParams1D on
}
Block {
BlockType Constant
Name "Constant1"
SID 3
Position [50, 203, 65, 217]
ShowName off
Value "0"
}
Block {
BlockType Reference
Name "Repeating\nSequence\nStair1"
SID 4
Ports [0, 1]
Position [15, 105, 45, 135]
ShowName off
LibraryVersion "1.216"
SourceBlock "simulink/Sources/Repeating\nSequence\nStair"
SourceType "Repeating Sequence Stair"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
OutValues "[1, zeros(1,2^12-1)]"
tsamp "1"
OutMin "[]"
OutMax "[]"
OutDataTypeStr "float('double')"
OutputDataTypeScalingMode "Specify via dialog"
OutDataType "float('double')"
ConRadixGroup "Best Precision: Vector-wise"
OutScaling "2^-12"
LockScale off
}
Block {
BlockType Terminator
Name "Terminator1"
SID 5
Position [710, 205, 720, 215]
ShowName off
}
Block {
BlockType ToWorkspace
Name "To Workspace"
SID 6
Ports [1]
Position [690, 170, 735, 190]
ShowName off
VariableName "pfbout"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Array"
}
Block {
BlockType ToWorkspace
Name "To Workspace1"
SID 7
Ports [1]
Position [690, 140, 735, 160]
ShowName off
VariableName "pfbsync"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Array"
}
Block {
BlockType SubSystem
Name "c_to_ri"
SID 8
Ports [1, 2]
Position [485, 166, 525, 224]
AttributesFormatString "18_17 r/i"
AncestorBlock "casper_library/Misc/c_to_ri"
UserDataPersistent on
UserData "DataTag1"
MinAlgLoopOccurrences off
PropExecContextOutsideSubsystem off
RTWSystemCode "Auto"
FunctionWithSeparateData off
Opaque off
RequestExecContextInheritance off
MaskHideContents off
MaskType "c_to_ri"
MaskDescription "Outputs real and imaginary components of a complex input.\nUseful for simplifying interco"
"nnects.\nSee also: Real-Imag to Complex (ri_to_c)"
MaskHelp "eval('xlWeb(''http://casper.berkeley.edu/wiki/C_to_ri'')')"
MaskPromptString "Bit Width|Binary Point"
MaskStyleString "edit,edit"
MaskTunableValueString "on,on"
MaskCallbackString "|"
MaskEnableString "on,on"
MaskVisibilityString "on,on"
MaskToolTipString "on,on"
MaskVariables "n_bits=@1;bin_pt=@2;"
MaskInitialization "annotation=sprintf('%d_%d r/i',n_bits,bin_pt);\nset_param(gcb,'AttributesFormatString',"
"annotation);"
MaskSelfModifiable on
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskPortRotate "default"
MaskIconUnits "autoscale"
MaskValueString "18|17"
System {
Name "c_to_ri"
Location [698, 94, 968, 282]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
SIDHighWatermark 7
Block {
BlockType Inport
Name "c"
SID 1
Position [20, 63, 50, 77]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType Reference
Name "force_im"
SID 2
Ports [1, 1]
Position [150, 79, 190, 111]
LibraryVersion "1.2"
SourceBlock "xbsIndex_r4/Reinterpret"
SourceType "Xilinx Type Reinterpreter Block"
infoedit "Changes signal type without altering the binary representation. You can changed the signal between s"
"igned and unsigned, and relocate the binary point.<P><P>Hardware notes: In hardware this block costs nothing.<P><P>"
"Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned wi"
"th 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in "
"binary)."
force_arith_type on
arith_type "Signed (2's comp)"
force_bin_pt on
bin_pt "bin_pt"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "reinterpret"
block_version "9.1.01"
sg_icon_stat "40,32,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 32 32 0 ],[0.77 0.82 0.91"
" ]);\nplot([0 40 40 0 0 ],[0 0 32 32 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[20.44 20.44 24.4"
"4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[16.44 16.44 20.44 20.44 16.44 ],"
"[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([15."
"1 28.88 24.88 20.88 16.88 11.1 15.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','"
"COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret');\nfp"
"rintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "force_re"
SID 3
Ports [1, 1]
Position [150, 29, 190, 61]
LibraryVersion "1.2"
SourceBlock "xbsIndex_r4/Reinterpret"
SourceType "Xilinx Type Reinterpreter Block"
infoedit "Changes signal type without altering the binary representation. You can changed the signal between s"
"igned and unsigned, and relocate the binary point.<P><P>Hardware notes: In hardware this block costs nothing.<P><P>"
"Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned wi"
"th 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in "
"binary)."
force_arith_type on
arith_type "Signed (2's comp)"
force_bin_pt on
bin_pt "bin_pt"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "reinterpret"
block_version "9.1.01"
sg_icon_stat "40,32,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 32 32 0 ],[0.77 0.82 0.91"
" ]);\nplot([0 40 40 0 0 ],[0 0 32 32 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[20.44 20.44 24.4"
"4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[16.44 16.44 20.44 20.44 16.44 ],"
"[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([15."
"1 28.88 24.88 20.88 16.88 11.1 15.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','"
"COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret');\nfp"
"rintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "slice_im"
SID 4
Ports [1, 1]
Position [80, 81, 125, 109]
LibraryVersion "1.2"
SourceBlock "xbsIndex_r4/Slice"
SourceType "Xilinx Bit Slice Extractor Block"
infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type "
"is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware "
"notes: In hardware this block costs nothing."
nbits "n_bits"
boolean_output off
mode "Lower Bit Location + Width"
bit1 "0"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
dbl_ovrd off
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "slice"
block_version "9.1.01"
sg_icon_stat "45,28,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91"
" ]);\nplot([0 45 45 0 0 ],[0 0 28 28 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[18.44 18.44 22.4"
"4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[14.44 14.44 18.44 18.44 14.44 ],"
"[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([17."
"1 30.88 26.88 22.88 18.88 13.1 17.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','"
"COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:"
"b]');\nfprintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "slice_re"
SID 5
Ports [1, 1]
Position [80, 31, 125, 59]
LibraryVersion "1.2"
SourceBlock "xbsIndex_r4/Slice"