We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
埋め込んだ perl 記述を eval() して結果を出力するディレクティブを検討する.
必要性も含めて.
Verilog だと 256この信号とかの生成に便利だったが,SystemC だと for ループでなんとかなるのか???
The text was updated successfully, but these errors were encountered:
No branches or pull requests
埋め込んだ perl 記述を eval() して結果を出力するディレクティブを検討する.
必要性も含めて.
Verilog だと 256この信号とかの生成に便利だったが,SystemC だと for ループでなんとかなるのか???
The text was updated successfully, but these errors were encountered: