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Add FUGen models for load ops #1

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Add FUGen models for load ops #1

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Binary file modified aivotta/hdb/fugen.hdb
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1 change: 1 addition & 0 deletions aivotta/hdb/fugen/vhdl/ld1024-post-op.vhd
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op2 <= rdata_out_1;
2 changes: 2 additions & 0 deletions aivotta/hdb/fugen/vhdl/ld32-post-op.vhd
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op2 <= (others => '0');
op2(31 downto 0) <= rdata_out_1(to_integer(unsigned(addr_low_out_1(6 downto 2)))*32+31 downto to_integer(unsigned(addr_low_out_1(6 downto 2)))*32);
6 changes: 6 additions & 0 deletions aivotta/hdb/fugen/vhdl/ld512-post-op.vhd
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op2 <= (others => '0');
if addr_low_out_1(6) = '0' then
op2(512 downto 0) <= rdata_out_1(511 downto 0);
else
op2(512 downto 0) <= rdata_out_1(1023 downto 512);
end if;
2 changes: 2 additions & 0 deletions aivotta/hdb/fugen/vhdl/ldu16-post-op.vhd
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op2 <= (others => '0');
op2(15 downto 0) <= rdata_out_1(to_integer(unsigned(addr_low_out_1(7 downto 1)))*16+15 downto to_integer(unsigned(addr_low_out_1(7 downto 1)))*16);
2 changes: 2 additions & 0 deletions aivotta/hdb/fugen/vhdl/ldu8-post-op.vhd
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op2 <= (others => '0');
op2(7 downto 0) <= rdata_out_1(to_integer(unsigned(addr_low_out_1))*8+7 downto to_integer(unsigned(addr_low_out_1))*8);
3 changes: 3 additions & 0 deletions aivotta/hdb/fugen/vhdl/ldxx.vhd
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avalid_in_1 <= '1';
aaddr_in_1 <= op1(addrw_c-1 downto 0);
awren_in_1 <= '0';
15 changes: 15 additions & 0 deletions aivotta/hdb/fugen/vhdl/lsu_defaults.vhd
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avalid_in_1 <= '0';
awren_in_1 <= '0';
aaddr_in_1 <= (others => '0');
astrb_in_1 <= (others => '0');
adata_in_1 <= (others => '0');
avalid_out(0) <= avalid_out_1;
aready_in_1 <= aready_in(0);
aaddr_out <= aaddr_out_1;
awren_out(0) <= awren_out_1;
astrb_out <= astrb_out_1;
adata_out <= adata_out_1;
rvalid_in_1 <= rvalid_in(0);
rready_out(0) <= rready_out_1;
rdata_in_1 <= rdata_in;
glockreq <= glockreq_out_1;
181 changes: 181 additions & 0 deletions aivotta/hdb/fugen/vhdl/lsu_registers.vhdl
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-- Copyright (c) 2017 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : LSU interface registers
-------------------------------------------------------------------------------
-- File : lsu_registers.vhdl
-- Author : Kati Tervo
-- Company :
-- Created : 2019-08-27
-- Last update: 2019-08-27
-- Platform :
-------------------------------------------------------------------------------
-- Description: LSU interface, handling registers and locking
--
-- Revisions :
-- Date Version Author Description
-- 2019-08-27 1.0 katte Created
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;

entity lsu_registers is
generic (
dataw_g : integer := 32;
low_bits_g : integer := 2;
addrw_g : integer := 11
);
port(
clk : in std_logic;
rstx : in std_logic;
glock_in : in std_logic;
glockreq_out : out std_logic;

avalid_in : in std_logic;
awren_in : in std_logic;
aaddr_in : in std_logic_vector(addrw_g-1 downto 0);
astrb_in : in std_logic_vector(dataw_g/8-1 downto 0);
adata_in : in std_logic_vector(dataw_g-1 downto 0);

avalid_out : out std_logic;
aready_in : in std_logic;
aaddr_out : out std_logic_vector(addrw_g-low_bits_g-1 downto 0);
awren_out : out std_logic;
astrb_out : out std_logic_vector(dataw_g/8-1 downto 0);
adata_out : out std_logic_vector(dataw_g-1 downto 0);

rvalid_in : in std_logic;
rready_out : out std_logic;

rdata_in : in std_logic_vector(dataw_g-1 downto 0);
rdata_out : out std_logic_vector(dataw_g-1 downto 0);

addr_low_out : out std_logic_vector(low_bits_g-1 downto 0)
);
end lsu_registers;

architecture rtl of lsu_registers is

-- Access channel registers
signal avalid_r : std_logic;
signal aaddr_r : std_logic_vector(aaddr_out'range);
signal awren_r : std_logic;
signal astrb_r : std_logic_vector(astrb_out'range);
signal adata_r : std_logic_vector(adata_out'range);
signal rready_r : std_logic;
signal rready_rr : std_logic;
signal rdata_r : std_logic_vector(rdata_in'range);

signal addr_low_r, addr_low_rr : std_logic_vector(addr_low_out'range);

signal fu_glock, glockreq : std_logic;
begin
-- Design-wide assertions
-- coverage off
-- synthesis translate_off
assert low_bits_g = integer(ceil(log2(real(dataw_g/8))))
report "Incorrect low_bits_g value"
severity failure;
-- coverage on
-- synthesis translate_on

avalid_out <= avalid_r;
awren_out <= awren_r;
aaddr_out <= aaddr_r;
astrb_out <= astrb_r;
adata_out <= adata_r;
rready_out <= rready_rr;
addr_low_out <= addr_low_rr;

gen_lockreq : process(rready_rr, rvalid_in, avalid_r, aready_in,
glock_in, glockreq)
begin
if (rready_rr = '1' and rvalid_in = '0')
or (avalid_r = '1' and aready_in = '0') then
glockreq <= '1';
else
glockreq <= '0';
end if;

fu_glock <= glockreq or glock_in;
glockreq_out <= glockreq;
end process gen_lockreq;

access_channel_sync : process(clk, rstx)
begin
if rstx = '0' then
avalid_r <= '0';
awren_r <= '0';
aaddr_r <= (others => '0');
astrb_r <= (others => '0');
adata_r <= (others => '0');
rready_r <= '0';
rready_rr <= '0';
addr_low_r <= (others => '0');
addr_low_rr <= (others => '0');
elsif rising_edge(clk) then

if avalid_r = '1' and aready_in = '1' then
avalid_r <= '0';
end if;

if rready_rr = '1' and rvalid_in = '1' then
rready_rr <= '0';
rdata_r <= rdata_in;
end if;

if fu_glock = '0' then
avalid_r <= avalid_in;
aaddr_r <= aaddr_in(aaddr_in'high downto low_bits_g);
addr_low_r <= aaddr_in(low_bits_g-1 downto 0);
addr_low_rr <= addr_low_r(low_bits_g-1 downto 0);
awren_r <= awren_in;
astrb_r <= astrb_in;
adata_r <= adata_in;

if avalid_in = '1' and awren_in = '0' then
rready_r <= '1';
else
rready_r <= '0';
end if;

if rready_r = '1' then
rready_rr <= '1';
end if;

end if;
end if;
end process access_channel_sync;

access_channel_comb : process(rready_rr, rvalid_in, rdata_r, rdata_in)
begin
if (rready_rr = '1' and rvalid_in = '1') then
rdata_out <= rdata_in;
else
rdata_out <= rdata_r;
end if;
end process access_channel_comb;

end rtl;
5 changes: 5 additions & 0 deletions aivotta/hdb/fugen/vhdl/st1024.vhd
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avalid_in_1 <= '1';
aaddr_in_1 <= op1(addrw_c-1 downto 0);
awren_in_1 <= '1';
astrb_in_1 <= (others => '1');
adata_in_1 <= op2;
7 changes: 7 additions & 0 deletions aivotta/hdb/fugen/vhdl/st16.vhd
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avalid_in_1 <= '1';
aaddr_in_1 <= op1(addrw_c-1 downto 0);
awren_in_1 <= '1';
astrb_in_1 <= (others => '0');
astrb_in_1(to_integer(unsigned(op1(6 downto 1))*2+1 downto unsigned(op1(6 downto 1))*2)) <= "11";
adata_in_1 <= (others => '0');
adata_in_1(to_integer(unsigned(op1(6 downto 1)))*16+15 downto to_integer(unsigned(op1(6 downto 1)))*16) <= op2;
7 changes: 7 additions & 0 deletions aivotta/hdb/fugen/vhdl/st32.vhd
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avalid_in_1 <= '1';
aaddr_in_1 <= op1(addrw_c-1 downto 0);
awren_in_1 <= '1';
astrb_in_1 <= (others => '0');
astrb_in_1(to_integer(unsigned(op1(6 downto 2))*4+3 downto unsigned(op1(6 downto 2))*4)) <= "1111";
adata_in_1 <= (others => '0');
adata_in_1(to_integer(unsigned(op1(6 downto 2)))*32+31 downto to_integer(unsigned(op1(6 downto 2)))*32) <= op2;
10 changes: 10 additions & 0 deletions aivotta/hdb/fugen/vhdl/st512.vhd
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avalid_in_1 <= '1';
aaddr_in_1 <= op1(addrw_c-1 downto 0);
awren_in_1 <= '1';
if op1(6) = '0' then
astrb_in_1 <= (1023 downto 521 => '0', 511 downto 0 => '1');
adata_in_1 <= (511 downto 0 => '0') & op2;
else
astrb_in_1 <= (1023 downto 521 => '1', 511 downto 0 => '0');
adata_in_1 <= op2 & (511 downto 0 => '0');
end if;
7 changes: 7 additions & 0 deletions aivotta/hdb/fugen/vhdl/st8.vhd
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avalid_in_1 <= '1';
aaddr_in_1 <= op1(addrw_c-1 downto 0);
awren_in_1 <= '1';
astrb_in_1 <= (others => '0');
astrb_in_1(to_integer(unsigned(op1(6 downto 0)))) <= '1';
adata_in_1 <= (others => '0');
adata_in_1(to_integer(unsigned(op1(6 downto 0)))*8+7 downto to_integer(unsigned(op1(6 downto 0)))*8) <= op2;
118 changes: 118 additions & 0 deletions aivotta/hdb/fugen/xml/lsu_1024bit.absDef.1.0.xml
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<?xml version="1.0" encoding="UTF-8"?>
<ipxact:abstractionDefinition xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014" xmlns:kactus2="http://kactus2.cs.tut.fi" xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014/ http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
<ipxact:vendor>CPC</ipxact:vendor>
<ipxact:library>interface</ipxact:library>
<ipxact:name>lsu_1024bit.absDef</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busType vendor="CPC" library="interface" name="lsu_32bit" version="1.0"/>
<ipxact:ports>
<ipxact:port>
<ipxact:logicalName>avalid_out</ipxact:logicalName>
<ipxact:wire>
<ipxact:onMaster>
<ipxact:presence>required</ipxact:presence>
<ipxact:width>1</ipxact:width>
<ipxact:direction>out</ipxact:direction>
</ipxact:onMaster>
<ipxact:defaultValue>0</ipxact:defaultValue>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:logicalName>aready_in</ipxact:logicalName>
<ipxact:wire>
<ipxact:onMaster>
<ipxact:presence>required</ipxact:presence>
<ipxact:width>1</ipxact:width>
<ipxact:direction>in</ipxact:direction>
</ipxact:onMaster>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:logicalName>aaddr_out</ipxact:logicalName>
<ipxact:wire>
<ipxact:qualifier>
<ipxact:isAddress>true</ipxact:isAddress>
</ipxact:qualifier>
<ipxact:onMaster>
<ipxact:presence>required</ipxact:presence>
<ipxact:width>addrw_c-7</ipxact:width>
<ipxact:direction>out</ipxact:direction>
</ipxact:onMaster>
<ipxact:defaultValue>0</ipxact:defaultValue>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:logicalName>awren_out</ipxact:logicalName>
<ipxact:wire>
<ipxact:onMaster>
<ipxact:presence>required</ipxact:presence>
<ipxact:width>1</ipxact:width>
<ipxact:direction>out</ipxact:direction>
</ipxact:onMaster>
<ipxact:defaultValue>0</ipxact:defaultValue>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:logicalName>astrb_out</ipxact:logicalName>
<ipxact:wire>
<ipxact:onMaster>
<ipxact:presence>required</ipxact:presence>
<ipxact:width>128</ipxact:width>
<ipxact:direction>out</ipxact:direction>
</ipxact:onMaster>
<ipxact:defaultValue>0</ipxact:defaultValue>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:logicalName>rvalid_in</ipxact:logicalName>
<ipxact:wire>
<ipxact:onMaster>
<ipxact:presence>required</ipxact:presence>
<ipxact:width>1</ipxact:width>
<ipxact:direction>in</ipxact:direction>
</ipxact:onMaster>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:logicalName>rready_out</ipxact:logicalName>
<ipxact:wire>
<ipxact:onMaster>
<ipxact:presence>required</ipxact:presence>
<ipxact:width>1</ipxact:width>
<ipxact:direction>out</ipxact:direction>
</ipxact:onMaster>
<ipxact:defaultValue>0</ipxact:defaultValue>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:logicalName>rdata_in</ipxact:logicalName>
<ipxact:wire>
<ipxact:qualifier>
<ipxact:isData>true</ipxact:isData>
</ipxact:qualifier>
<ipxact:onMaster>
<ipxact:presence>required</ipxact:presence>
<ipxact:width>1024</ipxact:width>
<ipxact:direction>in</ipxact:direction>
</ipxact:onMaster>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:logicalName>adata_out</ipxact:logicalName>
<ipxact:wire>
<ipxact:qualifier>
<ipxact:isData>true</ipxact:isData>
</ipxact:qualifier>
<ipxact:onMaster>
<ipxact:presence>required</ipxact:presence>
<ipxact:width>1024</ipxact:width>
<ipxact:direction>out</ipxact:direction>
</ipxact:onMaster>
<ipxact:defaultValue>0</ipxact:defaultValue>
</ipxact:wire>
</ipxact:port>
</ipxact:ports>
<ipxact:vendorExtensions>
<kactus2:version>3,4,0,0</kactus2:version>
</ipxact:vendorExtensions>
</ipxact:abstractionDefinition>
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