diff --git a/.gitignore b/.gitignore index b1126cc3..24265f69 100644 --- a/.gitignore +++ b/.gitignore @@ -52,20 +52,25 @@ *.map *.list *.size +sofware_version_id.h *.bin udp_send do-tftp.sh -gd32f10x*.* +lib-*/src/esp8266/* +lib-*/include/esp8266/* + +lib-*/src/h3/* + +gd32f1*.* lib-gd32/gd32f10x/* -gd32f30x*.* +gd32f3*.* lib-gd32/gd32f30x/* -gd32f4xx*.* +gd32f4*.* lib-gd32/gd32f4xx/* +gd32fh*.* +lib-gd32/gd32h7xx/* -lib-*/src/esp8266/* -lib-*/include/esp8266/* -lib-*/src/h3/* -lib-*/include/h3/* +software_version_id.h diff --git a/CMSIS/.cproject b/CMSIS/.cproject new file mode 100644 index 00000000..5f16a37f --- /dev/null +++ b/CMSIS/.cproject @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/lib-uuid/.project b/CMSIS/.project similarity index 93% rename from lib-uuid/.project rename to CMSIS/.project index dd0edd7a..e2e0ca79 100644 --- a/lib-uuid/.project +++ b/CMSIS/.project @@ -1,26 +1,26 @@ - - - lib-uuid - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - + + + CMSIS + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/lib-c/.settings/language.settings.xml b/CMSIS/.settings/language.settings.xml similarity index 88% rename from lib-c/.settings/language.settings.xml rename to CMSIS/.settings/language.settings.xml index 4367d277..ed16b203 100644 --- a/lib-c/.settings/language.settings.xml +++ b/CMSIS/.settings/language.settings.xml @@ -1,6 +1,6 @@ - + diff --git a/gd32_rdm_responder/.settings/org.eclipse.core.resources.prefs b/CMSIS/.settings/org.eclipse.core.resources.prefs similarity index 100% rename from gd32_rdm_responder/.settings/org.eclipse.core.resources.prefs rename to CMSIS/.settings/org.eclipse.core.resources.prefs diff --git a/CMSIS/Core/Include/cachel1_armv7.h b/CMSIS/Core/Include/cachel1_armv7.h new file mode 100644 index 00000000..abebc95f --- /dev/null +++ b/CMSIS/Core/Include/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.1 + * @date 19. April 2021 + ******************************************************************************/ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/lib-gd32/gd32f20x/CMSIS/cmsis_armcc.h b/CMSIS/Core/Include/cmsis_armcc.h similarity index 71% rename from lib-gd32/gd32f20x/CMSIS/cmsis_armcc.h rename to CMSIS/Core/Include/cmsis_armcc.h index f2bb66a0..a955d471 100644 --- a/lib-gd32/gd32f20x/CMSIS/cmsis_armcc.h +++ b/CMSIS/Core/Include/cmsis_armcc.h @@ -1,734 +1,888 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return(result); -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/CMSIS/Core/Include/cmsis_armclang.h b/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 00000000..69114177 --- /dev/null +++ b/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/CMSIS/Core/Include/cmsis_armclang_ltm.h b/CMSIS/Core/Include/cmsis_armclang_ltm.h new file mode 100644 index 00000000..1e255d59 --- /dev/null +++ b/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/CMSIS/Core/Include/cmsis_compiler.h b/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 00000000..adbf296f --- /dev/null +++ b/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/CMSIS/Core/Include/cmsis_gcc.h b/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 00000000..67bda4ef --- /dev/null +++ b/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/CMSIS/Core/Include/cmsis_iccarm.h b/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 00000000..65b824b0 --- /dev/null +++ b/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/CMSIS/Core/Include/cmsis_version.h b/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 00000000..8b4765f1 --- /dev/null +++ b/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/CMSIS/Core/Include/core_cm3.h b/CMSIS/Core/Include/core_cm3.h new file mode 100644 index 00000000..74fb87e5 --- /dev/null +++ b/CMSIS/Core/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS/Core/Include/core_cm4.h b/CMSIS/Core/Include/core_cm4.h new file mode 100644 index 00000000..e21cd149 --- /dev/null +++ b/CMSIS/Core/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS/Core/Include/core_cm7.h b/CMSIS/Core/Include/core_cm7.h new file mode 100644 index 00000000..010506e9 --- /dev/null +++ b/CMSIS/Core/Include/core_cm7.h @@ -0,0 +1,2366 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.6 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/CMSIS/Core/Include/mpu_armv7.h b/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 00000000..d9eedf81 --- /dev/null +++ b/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/CMSIS/Core/Include/tz_context.h b/CMSIS/Core/Include/tz_context.h new file mode 100644 index 00000000..0d09749f --- /dev/null +++ b/CMSIS/Core/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/CMSIS/LICENSE.txt b/CMSIS/LICENSE.txt new file mode 100644 index 00000000..8dada3ed --- /dev/null +++ b/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright {yyyy} {name of copyright owner} + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/README.md b/README.md index d40e2f92..c2e54183 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ ![GitHub](https://img.shields.io/github/license/vanvught/GD32F207RG-DMX512-RDM) -[![C++ Standard](https://img.shields.io/badge/C%2B%2B-11-blue.svg)](https://img.shields.io/badge/C%2B%2B-11%-blue.svg) +[![C++ Standard](https://img.shields.io/badge/C%2B%2B-20-blue.svg)](https://img.shields.io/badge/C%2B%2B-11%-blue.svg) ![GitHub issues](https://img.shields.io/github/issues-raw/vanvught/GD32F207RG-DMX512-RDM) ![GitHub contributors](https://img.shields.io/github/contributors/vanvught/GD32F207RG-DMX512-RDM) ![GitHub Sponsors](https://img.shields.io/github/sponsors/vanvught) diff --git a/firmware-template-gd32/Artnet.mk b/firmware-template-gd32/Artnet.mk new file mode 100644 index 00000000..7c46203a --- /dev/null +++ b/firmware-template-gd32/Artnet.mk @@ -0,0 +1,5 @@ +ifeq ($(findstring ARTNET_VERSION=4,$(DEFINES)),ARTNET_VERSION=4) + ifeq ($(findstring ARTNET_HAVE_DMXIN,$(DEFINES)),ARTNET_HAVE_DMXIN) + DEFINES+=-DE131_HAVE_DMXIN + endif +endif \ No newline at end of file diff --git a/firmware-template-gd32/Board.mk b/firmware-template-gd32/Board.mk new file mode 100644 index 00000000..bc44a934 --- /dev/null +++ b/firmware-template-gd32/Board.mk @@ -0,0 +1,108 @@ +$(info "Board.mk") + +ifndef BOARD + $(error BOARD is not set) +endif + +ifndef DEFINES + DEFINES= +endif + +ifeq ($(strip $(BOARD)),BOARD_GD32F103RC) + MCU=GD32F103RC + DEFINES+=-DCONFIG_STORE_USE_ROM + DEFINES+=-DNO_EMAC +endif + +ifeq ($(strip $(BOARD)),BOARD_GD32F107RC) + MCU=GD32F107RC + DEFINES+=-DCONFIG_STORE_USE_ROM +endif + +ifeq ($(strip $(BOARD)),BOARD_GD32F207RG) + MCU=GD32F207RG + DEFINES+=-DCONFIG_STORE_USE_SPI +endif + +ifeq ($(strip $(BOARD)),BOARD_GD32F207VC_2) + MCU=GD32F207VC + DEFINES+=-DCONFIG_STORE_USE_ROM + BITBANGING595=1 +endif + +ifeq ($(strip $(BOARD)),BOARD_GD32F207VC_4) + MCU=GD32F207VC + DEFINES+=-DCONFIG_STORE_USE_ROM + BITBANGING595=1 +endif + +ifeq ($(strip $(BOARD)),BOARD_GD32F303RC) + MCU=GD32F303RC + DEFINES+=-DCONFIG_STORE_USE_ROM + DEFINES+=-DNO_EMAC +endif + +ifeq ($(strip $(BOARD)),BOARD_GD32F407RE) + MCU=GD32F407RE + DEFINES+=-DCONFIG_STORE_USE_SPI +endif + +ifeq ($(strip $(BOARD)),BOARD_GD32F450VE) + MCU=GD32F450VE + DEFINES+=-DCONFIG_STORE_USE_RAM + BITBANGING595=1 +endif + +ifeq ($(strip $(BOARD)),BOARD_GD32F450VI) + MCU=GD32F450VI +endif + +ifeq ($(strip $(BOARD)),BOARD_16X4U_PIXEL) + MCU=GD32F450VI +endif + +ifeq ($(strip $(BOARD)),BOARD_GD32F470VG) + MCU=GD32F470VG +endif + +ifeq ($(strip $(BOARD)),BOARD_GD32F207C_EVAL) + MCU=GD32F207VC + DEFINES+=-DCONFIG_STORE_USE_ROM +endif + +ifeq ($(strip $(BOARD)),BOARD_GD32F470Z_EVAL) + MCU=GD32F470ZK + DEFINES+=-DCONFIG_STORE_USE_RAM +endif + +ifeq ($(strip $(BOARD)),BOARD_GD32H759I_EVAL) + MCU=GD32H759IM + DEFINES+=-DCONFIG_STORE_USE_ROM +endif + +ifeq ($(strip $(BOARD)),BOARD_BW_OPIDMX4) + BOARD_DMX=4 + DEFINES+=-DCONFIG_STORE_USE_SPI +endif + +ifeq ($(strip $(BOARD)),BOARD_DMX3) + BOARD_DMX=3 + DEFINES+=-DCONFIG_STORE_USE_SPI +endif + +ifeq ($(strip $(BOARD)),BOARD_DMX4) + DEFINES+=-DCONFIG_STORE_USE_SPI + BOARD_DMX=4 +endif + +ifdef BOARD_DMX + ifeq ($(MCU),GD32F207RG) + else ifeq ($(MCU),GD32F407RE) + else + $(error MCU is not support for BOARD_DMX) + endif +endif + +ifndef MCU + $(error BOARD is not configured) +endif \ No newline at end of file diff --git a/firmware-template-gd32/FreeRTOS.mk b/firmware-template-gd32/FreeRTOS.mk new file mode 100644 index 00000000..92ace9f2 --- /dev/null +++ b/firmware-template-gd32/FreeRTOS.mk @@ -0,0 +1,35 @@ +$(info "FreeRTOS.mk") + +ifndef ARMOPS + $(error ARMOPS is not set) +endif + +ifeq ($(findstring USE_FREE_RTOS,$(DEFINES)), USE_FREE_RTOS) + USEFREERTOS=1 +endif +ifeq ($(findstring USE_FREE_RTOS,$(MAKE_FLAGS)), USE_FREE_RTOS) + USEFREERTOS=1 +endif + +ifdef USEFREERTOS + INCLUDES+=-I../lib-gd32/FreeRTOS/FreeRTOS-Kernel/include + + ifeq ($(findstring cortex-m3,$(ARMOPS)), cortex-m3) + FREE_RTOS_PORTABLE=ARM_CM3 + endif + + ifeq ($(findstring cortex-m4,$(ARMOPS)), cortex-m4) + FREE_RTOS_PORTABLE=ARM_CM4F + endif + + ifeq ($(findstring cortex-m7,$(ARMOPS)), cortex-m7) + FREE_RTOS_PORTABLE=ARM_CM7 + endif + + ifndef FREE_RTOS_PORTABLE + $(error FREE_RTOS_PORTABLE is not set) + endif + + INCLUDES+=-I../lib-gd32/FreeRTOS/FreeRTOS-Kernel/portable/GCC/$(FREE_RTOS_PORTABLE) + DEFINES+=-D$(FREE_RTOS_PORTABLE) +endif \ No newline at end of file diff --git a/firmware-template-gd32/Includes.mk b/firmware-template-gd32/Includes.mk index ce9b5765..71aadc06 100644 --- a/firmware-template-gd32/Includes.mk +++ b/firmware-template-gd32/Includes.mk @@ -1,13 +1,14 @@ -INCLUDES:=-I./include -I../include -I../lib-hal/include -I../lib-debug/include -INCLUDES+=$(addprefix -I,$(EXTRA_INCLUDES)) +$(info "Includes.mk") + +INCLUDES:=-I./include -I../include INCLUDES+=-I../firmware-template-gd32/include INCLUDES+=-I../firmware-template-gd32/template +INCLUDES+=-I../CMSIS/Core/Include INCLUDES+=-I../lib-gd32/${FAMILY}/${FAMILY_UC}_standard_peripheral/Include -INCLUDES+=-I../lib-gd32/${FAMILY}/CMSIS INCLUDES+=-I../lib-gd32/${FAMILY}/CMSIS/GD/${FAMILY_UC}/Include INCLUDES+=-I../lib-gd32/include +INCLUDES+=$(addprefix -I,$(EXTRA_INCLUDES)) -USB_HOST= ifeq ($(findstring ENABLE_USB_HOST,$(DEFINES)), ENABLE_USB_HOST) USB_HOST=1 endif @@ -15,7 +16,6 @@ ifeq ($(findstring ENABLE_USB_HOST,$(MAKE_FLAGS)), ENABLE_USB_HOST) USB_HOST=1 endif -USB_HOST_MSC= ifeq ($(findstring ENABLE_USB_HOST,$(DEFINES)), ENABLE_USB_HOST) USB_HOST_MSC=1 endif @@ -52,6 +52,18 @@ ifeq ($(findstring gd32f4xx,$(FAMILY)), gd32f4xx) endif endif +ifeq ($(findstring gd32h7xx,$(FAMILY)), gd32h7xx) + ifdef USB_HOST + INCLUDES+=-I../lib-gd32/${FAMILY}/GD32H7xx_usbhs_library/driver/Include + INCLUDES+=-I../lib-gd32/${FAMILY}/GD32H7xx_usbhs_library/host/core/Include + INCLUDES+=-I../lib-gd32/${FAMILY}/GD32H7xx_usbhs_library/ustd/common + ifdef USB_HOST_MSC + INCLUDES+=-I../lib-gd32/${FAMILY}/GD32H7xx_usbhs_library/host/class/msc/Include + INCLUDES+=-I../lib-gd32/${FAMILY}/GD32H7xx_usbhs_library/ustd/class/msc + endif + endif +endif + ifdef USB_HOST_MSC - EXTRA_INCLUDES+=../lib-hal/ff12c + INCLUDES+=-I../lib-hal/ff14b/source endif \ No newline at end of file diff --git a/firmware-template-gd32/Mcu.mk b/firmware-template-gd32/Mcu.mk index 63127eec..46058e8f 100644 --- a/firmware-template-gd32/Mcu.mk +++ b/firmware-template-gd32/Mcu.mk @@ -1,7 +1,12 @@ +$(info "Mcu.mk") + ifndef MCU $(error MCU is not set) endif +$(info $$MCU [${MCU}]) + +# Extract upper and lower case versions of MCU name MCU_UC=$(shell echo $(MCU) | rev | cut -c3- | rev ) MCU_LC=$(shell echo $(MCU_UC) | tr A-Z a-z ) @@ -9,6 +14,8 @@ $(info $$MCU [${MCU}]) $(info $$MCU_LC [${MCU_LC}]) $(info $$MCU_UC [${MCU_UC}]) +# Set LINKER, FAMILY, and LINE based on MCU + ifeq ($(strip $(MCU)),GD32F103RC) LINKER=$(FIRMWARE_DIR)gd32f103rc_flash.ld FAMILY=gd32f10x @@ -57,16 +64,76 @@ ifeq ($(strip $(MCU)),GD32F450VI) LINE=gd32f450 endif +ifeq ($(strip $(MCU)),GD32F470VG) + LINKER=$(FIRMWARE_DIR)gd32f470vg_flash.ld + FAMILY=gd32f4xx + LINE=gd32f470 +endif + +ifeq ($(strip $(MCU)),GD32F470ZK) + LINKER=$(FIRMWARE_DIR)gd32f470zk_flash.ld + FAMILY=gd32f4xx + LINE=gd32f470 +endif + +ifeq ($(strip $(MCU)),GD32H759IM) + LINKER=$(FIRMWARE_DIR)gd32h7xx_xM_flash.ld + FAMILY=gd32h7xx + LINE=gd32h759 +endif + ifndef LINKER $(error MCU is not configured) endif +# Common ARM options for Cortex-M3 +ARMOPS_CM3=-mcpu=cortex-m3 -mthumb -mfloat-abi=soft + +# Common ARM options for Cortex-M4 +ARMOPS_CM4=-mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fsingle-precision-constant + +# Common ARM options for Cortex-M7 +ARMOPS_CM7=-mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 -fsingle-precision-constant + +# CMSIS options for FPU present +CMSISOPS_FPU_PRESENT = -D__FPU_PRESENT=1 -DARM_MATH_CM4 + +# Common CMSIS options +CMSISOPS=-D__Vendor_SysTickConfig=0 + +# Set ARM options and CMSIS options based on FAMILY + +ifeq ($(FAMILY),gd32f10x) + ARMOPS=$(ARMOPS_CM3) +endif + +ifeq ($(FAMILY),gd32f20x) + ARMOPS=$(ARMOPS_CM3) +endif + +ifeq ($(FAMILY),gd32f30x) + ARMOPS=$(ARMOPS_CM4) + CMSISOPS+=$(CMSISOPS_FPU_PRESENT) +endif + +ifeq ($(FAMILY),gd32f4xx) + ARMOPS=$(ARMOPS_CM4) + CMSISOPS+=$(CMSISOPS_FPU_PRESENT) +endif + +ifeq ($(FAMILY),gd32h7xx) + ARMOPS=$(ARMOPS_CM7) + CMSISOPS+=-D__FPU_PRESENT=1 -DARM_MATH_CM7 +endif + FAMILY_UC=$(shell echo $(FAMILY) | tr a-w A-W) +FAMILY_UCA=$(shell echo $(FAMILY) | tr a-z A-Z) +LINE_UC=$(shell echo $(LINE) | tr a-z A-Z) + $(info $$FAMILY [${FAMILY}]) $(info $$FAMILY_UC [${FAMILY_UC}]) - -LINE_UC=$(shell echo $(LINE) | tr a-z A-Z) +$(info $$FAMILY_UCA [${FAMILY_UCA}]) $(info $$LINE [${LINE}]) $(info $$LINE_UC [${LINE_UC}]) \ No newline at end of file diff --git a/firmware-template-gd32/Rules.mk b/firmware-template-gd32/Rules.mk index 1ea28ce2..e0e4b61a 100644 --- a/firmware-template-gd32/Rules.mk +++ b/firmware-template-gd32/Rules.mk @@ -9,35 +9,28 @@ LD = $(PREFIX)ld AR = $(PREFIX)ar BOARD?=BOARD_GD32F207RG -ENET_PHY?=DP83848 +ENET_PHY?=RTL8201F -# Output TARGET=gd32f207.bin LIST=$(FAMILY).list MAP=$(FAMILY).map SIZE=$(FAMILY).size BUILD=build_gd32/ -# Input -SOURCE=./ FIRMWARE_DIR=./../firmware-template-gd32/ DEFINES:=$(addprefix -D,$(DEFINES)) -ifeq ($(findstring ARTNET_VERSION=4,$(DEFINES)),ARTNET_VERSION=4) - ifeq ($(findstring ARTNET_HAVE_DMXIN,$(DEFINES)),ARTNET_HAVE_DMXIN) - DEFINES+=-DE131_HAVE_DMXIN - endif -endif - MCU=GD32F207RG +include ../firmware-template-gd32/Board.mk include ../firmware-template-gd32/Mcu.mk include ../firmware-template/libs.mk - -LIBS+=c++ c gd32 - include ../firmware-template-gd32/Includes.mk +include ../firmware-template-gd32/Artnet.mk +include ../firmware-template-gd32/Validate.mk + +LIBS+=gd32 clib # The variable for the libraries include directory LIBINCDIRS:=$(addprefix -I../lib-,$(LIBS)) @@ -53,31 +46,26 @@ LDLIBS:=$(addprefix -l,$(LIBS)) # The variables for the dependency check LIBDEP=$(addprefix ../lib-,$(LIBS)) -$(info $$BOARD [${BOARD}]) -$(info $$ENET_PHY [${ENET_PHY}]) -$(info $$DEFINES [${DEFINES}]) -$(info $$LIBS [${LIBS}]) -$(info $$LIBDEP [${LIBDEP}]) - -COPS=-DBARE_METAL -DGD32 -D$(LINE_UC) -D$(MCU) -D$(BOARD) -DPHY_TYPE=$(ENET_PHY) -COPS+=$(DEFINES) $(MAKE_FLAGS) $(INCLUDES) $(LIBINCDIRS) -COPS+=-Os -mcpu=cortex-m3 -mthumb -COPS+=-nostartfiles -ffreestanding -nostdlib +COPS=-DGD32 -D$(FAMILY_UCA) -D$(LINE_UC) -D$(MCU) -D$(BOARD) -DPHY_TYPE=$(ENET_PHY) +COPS+=$(strip $(DEFINES) $(MAKE_FLAGS) $(INCLUDES) $(LIBINCDIRS)) +COPS+=$(strip $(ARMOPS) $(CMSISOPS)) +COPS+=-Os -nostartfiles -ffreestanding -nostdlib COPS+=-fstack-usage COPS+=-ffunction-sections -fdata-sections -COPS+=-Wall -Werror -Wpedantic -Wextra -Wunused -Wsign-conversion -Wconversion -COPS+=-Wduplicated-cond -Wlogical-op +COPS+=-Wall -Werror -Wpedantic -Wextra -Wunused -Wsign-conversion -Wconversion -Wduplicated-cond -Wlogical-op -CPPOPS=-std=c++11 +CPPOPS=-std=c++20 CPPOPS+=-Wnon-virtual-dtor -Woverloaded-virtual -Wnull-dereference -fno-rtti -fno-exceptions -fno-unwind-tables CPPOPS+=-Wuseless-cast -Wold-style-cast CPPOPS+=-fno-threadsafe-statics -LDOPS=--gc-sections --print-gc-sections +LDOPS=--gc-sections --print-gc-sections --print-memory-usage PLATFORM_LIBGCC+= -L $(shell dirname `$(CC) $(COPS) -print-libgcc-file-name`) +PLATFORM_LIBC+= -L $(shell dirname `$(CC) $(COPS) --print-file-name=libc.a`) $(info $$PLATFORM_LIBGCC [${PLATFORM_LIBGCC}]) +$(info $$PLATFORM_LIBC [${PLATFORM_LIBC}]) C_OBJECTS=$(foreach sdir,$(SRCDIR),$(patsubst $(sdir)/%.c,$(BUILD)$(sdir)/%.o,$(wildcard $(sdir)/*.c))) C_OBJECTS+=$(foreach sdir,$(SRCDIR),$(patsubst $(sdir)/%.cpp,$(BUILD)$(sdir)/%.o,$(wildcard $(sdir)/*.cpp))) @@ -88,13 +76,13 @@ BUILD_DIRS:=$(addprefix $(BUILD),$(SRCDIR)) OBJECTS:=$(ASM_OBJECTS) $(C_OBJECTS) define compile-objects -$(BUILD)$1/%.o: $(SOURCE)$1/%.cpp +$(BUILD)$1/%.o: $1/%.cpp $(CPP) $(COPS) $(CPPOPS) -c $$< -o $$@ -$(BUILD)$1/%.o: $(SOURCE)$1/%.c +$(BUILD)$1/%.o: $1/%.c $(CC) $(COPS) -c $$< -o $$@ -$(BUILD)$1/%.o: $(SOURCE)$1/%.S +$(BUILD)$1/%.o: $1/%.S $(CC) $(COPS) -D__ASSEMBLY__ -c $$< -o $$@ endef @@ -122,7 +110,7 @@ clean: $(LIBDEP) lisdep: $(LIBDEP) $(LIBDEP): - $(MAKE) -f Makefile.GD32 $(MAKECMDGOALS) 'FAMILY=${FAMILY}' 'MCU=${MCU}' 'BOARD=${BOARD}' 'ENET_PHY=${ENET_PHY}' 'MAKE_FLAGS=$(DEFINES)' -C $@ + $(MAKE) -f Makefile.GD32 $(MAKECMDGOALS) 'FAMILY=${FAMILY}' 'BOARD=${BOARD}' 'ENET_PHY=${ENET_PHY}' 'MAKE_FLAGS=$(DEFINES)' -C $@ # # Build bin @@ -131,23 +119,18 @@ $(LIBDEP): $(BUILD_DIRS) : mkdir -p $(BUILD_DIRS) -$(BUILD)startup_$(FAMILY)_cl.o : $(FIRMWARE_DIR)/startup_$(FAMILY)_cl.S - $(AS) $(COPS) -D__ASSEMBLY__ -c $(FIRMWARE_DIR)/startup_$(FAMILY)_cl.S -o $(BUILD)startup_$(FAMILY)_cl.o +$(BUILD)startup_$(LINE).o : $(FIRMWARE_DIR)/startup_$(LINE).S + $(AS) $(COPS) -D__ASSEMBLY__ -c $(FIRMWARE_DIR)/startup_$(LINE).S -o $(BUILD)startup_$(LINE).o $(BUILD)hardfault_handler.o : $(FIRMWARE_DIR)/hardfault_handler.c $(CC) $(COPS) -c $(FIRMWARE_DIR)/hardfault_handler.c -o $(BUILD)hardfault_handler.o -$(BUILD)main.elf: Makefile.GD32 $(LINKER) $(BUILD)startup_$(FAMILY)_cl.o $(BUILD)hardfault_handler.o $(OBJECTS) $(LIBDEP) - $(LD) $(BUILD)startup_$(FAMILY)_cl.o $(BUILD)hardfault_handler.o $(OBJECTS) -Map $(MAP) -T $(LINKER) $(LDOPS) -o $(BUILD)main.elf $(LIBGD32) $(LDLIBS) $(PLATFORM_LIBGCC) -lgcc +$(BUILD)main.elf: Makefile.GD32 $(LINKER) $(BUILD)startup_$(LINE).o $(BUILD)hardfault_handler.o $(OBJECTS) $(LIBDEP) + $(LD) $(BUILD)startup_$(LINE).o $(BUILD)hardfault_handler.o $(OBJECTS) -Map $(MAP) -T $(LINKER) $(LDOPS) -o $(BUILD)main.elf $(LIBGD32) $(LDLIBS) $(PLATFORM_LIBGCC) -lgcc $(PREFIX)objdump -D $(BUILD)main.elf | $(PREFIX)c++filt > $(LIST) - $(PREFIX)size -A -x $(BUILD)main.elf > $(FAMILY).size - $(MAKE) -f Makefile.GD32 calculate_unused_ram SIZE_FILE=$(FAMILY).size LINKER_SCRIPT=$(LINKER) + $(PREFIX)size -A -x $(BUILD)main.elf $(TARGET) : $(BUILD)main.elf - $(PREFIX)objcopy $(BUILD)main.elf -O binary $(TARGET) --remove-section=.sram1* --remove-section=.sram2* + $(PREFIX)objcopy $(BUILD)main.elf -O binary $(TARGET) --remove-section=.tcmsram* --remove-section=.ram* --remove-section=.sram1* --remove-section=.sram2* --remove-section=.ramadd* --remove-section=.bkpsram* $(foreach bdir,$(SRCDIR),$(eval $(call compile-objects,$(bdir)))) - -.PHONY: calculate_unused_ram -calculate_unused_ram: $(FAMILY).size $(LINKER) - @$(FIRMWARE_DIR)/calculate_unused_ram.sh $(FAMILY).size $(LINKER) diff --git a/firmware-template-gd32/Validate.mk b/firmware-template-gd32/Validate.mk new file mode 100644 index 00000000..9531da32 --- /dev/null +++ b/firmware-template-gd32/Validate.mk @@ -0,0 +1,33 @@ +$(info "Validate.mk") +$(info $$MAKE_FLAGS [${MAKE_FLAGS}]) +$(info $$DEFINES [${DEFINES}]) + +FLAGS:=$(MAKE_FLAGS) +ifeq ($(FLAGS),) + FLAGS:=$(DEFINES) +endif + +ifneq (,$(findstring OUTPUT_DMX_SEND,$(FLAGS))$(findstring CONFIG_RDM,$(FLAGS))$(findstring RDM_CONTROLLER,$(FLAGS))$(findstring LTC,$(FLAGS))) + TIMER6_HAVE_IRQ_HANDLER=1 + ifneq (,$(findstring CONFIG_TIMER6_HAVE_NO_IRQ_HANDLER,$(MAKE_FLAGS))) + $(error CONFIG_TIMER6_HAVE_NO_IRQ_HANDLER is set) + endif +endif + +ifndef TIMER6_HAVE_IRQ_HANDLER + DEFINES+=-DCONFIG_TIMER6_HAVE_NO_IRQ_HANDLER +endif + +ifneq ($(findstring USE_FREE_RTOS,$(FLAGS)),USE_FREE_RTOS) + DEFINES+=-DCONFIG_HAL_USE_SYSTICK +else + DEFINES+=-DCONFIG_HAL_USE_SYSTICK # Temporarily need to fix TIMER10 +endif + +ifeq ($(findstring ENABLE_TFTP_SERVER,$(FLAGS)),ENABLE_TFTP_SERVER) + ifneq ($(findstring CONFIG_HAL_USE_SYSTICK,$(FLAGS)),CONFIG_HAL_USE_SYSTICK) + DEFINES+=-DCONFIG_HAL_USE_SYSTICK + endif +endif + +$(info $$DEFINES [${DEFINES}]) diff --git a/firmware-template-gd32/calculate_unused_ram.sh b/firmware-template-gd32/calculate_unused_ram.sh deleted file mode 100755 index 6a96603f..00000000 --- a/firmware-template-gd32/calculate_unused_ram.sh +++ /dev/null @@ -1,32 +0,0 @@ -#!/bin/bash - -if [ $# -lt 2 ]; then - echo "Usage: $0 " - exit 1 -fi - -size_file="$1" -linker_script="$2" - -used_data=$(grep '.data' "$size_file" | tail -n 1 | awk '{print $2}') -used_bss=$(grep ".bss" "$size_file" | awk '{print $2}') - -total_ram=$(grep "RAM (xrw)" "$linker_script" | awk '{print $NF}' | sed 's/K$//' | awk '{printf "%d", $0 * 1024}') -unused_ram=$(( $(echo $total_ram) - $(echo $used_data) - $(echo $used_bss) )) - -used_stack=$(grep ".stack" "$size_file" | awk '{print $2}') -used_heap=$(grep ".heap" "$size_file" | awk '{print $2}') - -total_ram1=$(grep "RAM1 (xrw)" "$linker_script" | awk '{print $NF}' | sed 's/K$//' | awk '{printf "%d", $0 * 1024}') -unused_ram1=$(( $(echo $total_ram1) - $(echo $used_stack)- $(echo $used_heap) )) - -used_ram2=$(grep ".sram2" "$size_file" | awk '{print $2}') - -total_ram2=$(grep "RAM2 (xrw)" "$linker_script" | awk '{print $NF}' | sed 's/K$//' | awk '{printf "%d", $0 * 1024}') -unused_ram2=$(( $(echo $total_ram2) - $(echo $used_ram2) )) - -cat $1 -echo "SRAM0 $total_ram bytes, Unused: $unused_ram bytes" -echo "SRAM1 $total_ram1 bytes, Unused: $unused_ram1 bytes" -echo "SRAM2 $total_ram2 bytes, Unused: $unused_ram2 bytes" -echo \ No newline at end of file diff --git a/firmware-template-gd32/gd32f207rg_flash.ld b/firmware-template-gd32/gd32f207rg_flash.ld index ac7caeb9..b5e44b19 100644 --- a/firmware-template-gd32/gd32f207rg_flash.ld +++ b/firmware-template-gd32/gd32f207rg_flash.ld @@ -36,31 +36,37 @@ SECTIONS KEEP (*(.fini)) . = ALIGN(4); _etext = .; + } >FLASH - . = ALIGN(8); - + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .preinit_array : + { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); - + } >FLASH + + .init_array : + { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); - + } >FLASH + + .fini_array : + { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(.fini_array*)) KEEP (*(SORT(.fini_array.*))) PROVIDE_HIDDEN (__fini_array_end = .); - - } >FLASH - - .rodata : - { - . = ALIGN(4); - *(.rodata) - *(.rodata*) - . = ALIGN(4); } >FLASH _sidata = LOADADDR(.data); @@ -108,8 +114,7 @@ SECTIONS heap_top = .; . = ALIGN(4); } >RAM1 - - + .sram2 : { . = ALIGN(4); @@ -141,5 +146,4 @@ SECTIONS } } - /* input sections */ -GROUP(libgcc.a libc.a) \ No newline at end of file +GROUP(libgcc.a) diff --git a/firmware-template-gd32/hardfault_handler.c b/firmware-template-gd32/hardfault_handler.c index 22abbdf2..039d1f9d 100644 --- a/firmware-template-gd32/hardfault_handler.c +++ b/firmware-template-gd32/hardfault_handler.c @@ -1,5 +1,5 @@ /* - * hardfault_handler.cpp + * hardfault_handler.c */ /** * Using Cortex-M3/M4/M7 Fault Exceptions @@ -50,24 +50,24 @@ void hardfault_handler(unsigned long *hardfault_args, unsigned int lr_value) { printf("[HardFault]\n"); printf("- Stack frame:\n"); - printf(" R0 = %x\n", stacked_r0); - printf(" R1 = %x\n", stacked_r1); - printf(" R2 = %x\n", stacked_r2); - printf(" R3 = %x\n", stacked_r3); - printf(" R12 = %x\n", stacked_r12); - printf(" LR = %x\n", stacked_lr); - printf(" PC = %x\n", stacked_pc); - printf(" PSR = %x\n", stacked_psr); + printf(" R0 = %x\n", (unsigned int) stacked_r0); + printf(" R1 = %x\n", (unsigned int) stacked_r1); + printf(" R2 = %x\n", (unsigned int) stacked_r2); + printf(" R3 = %x\n", (unsigned int) stacked_r3); + printf(" R12 = %x\n", (unsigned int) stacked_r12); + printf(" LR = %x\n", (unsigned int) stacked_lr); + printf(" PC = %x\n", (unsigned int) stacked_pc); + printf(" PSR = %x\n", (unsigned int) stacked_psr); printf("- FSR/FAR:\n"); - printf(" CFSR = %x\n", cfsr); - printf(" HFSR = %x\n", SCB->HFSR); - printf(" DFSR = %x\n", SCB->DFSR); - printf(" AFSR = %x\n", SCB->AFSR); + printf(" CFSR = %x\n", (unsigned int) cfsr); + printf(" HFSR = %x\n", (unsigned int) SCB->HFSR); + printf(" DFSR = %x\n", (unsigned int) SCB->DFSR); + printf(" AFSR = %x\n", (unsigned int) SCB->AFSR); if (cfsr & 0x0080) { - printf(" MMFAR = %x\n", memmanage_fault_address); + printf(" MMFAR = %x\n", (unsigned int) memmanage_fault_address); } if (cfsr & 0x8000) { - printf(" BFAR = %x\n", bus_fault_address); + printf(" BFAR = %x\n", (unsigned int) bus_fault_address); } printf("- Misc\n"); printf(" LR/EXC_RETURN= %x\n", lr_value); diff --git a/firmware-template-gd32/include/software_version.h b/firmware-template-gd32/include/software_version.h index 8c65b31d..c5152360 100644 --- a/firmware-template-gd32/include/software_version.h +++ b/firmware-template-gd32/include/software_version.h @@ -2,7 +2,7 @@ * @file software_version.h * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,6 +26,6 @@ #ifndef SOFTWARE_VERSION_H_ #define SOFTWARE_VERSION_H_ -constexpr char SOFTWARE_VERSION[] = "2.0"; +constexpr char SOFTWARE_VERSION[] = "2.1"; #endif /* SOFTWARE_VERSION_H_ */ diff --git a/firmware-template-gd32/lib/Rules.mk b/firmware-template-gd32/lib/Rules.mk index f64fa048..177b8efd 100644 --- a/firmware-template-gd32/lib/Rules.mk +++ b/firmware-template-gd32/lib/Rules.mk @@ -9,49 +9,40 @@ AS = $(CC) LD = $(PREFIX)ld AR = $(PREFIX)ar -FAMILY?=gd32f20x -MCU?=GD32F207RG BOARD?=BOARD_GD32F207RG -ENET_PHY?=DP83848 +ENET_PHY?=RTL8201F -FAMILY:=$(shell echo $(FAMILY) | tr A-Z a-z) -FAMILY_UC=$(shell echo $(FAMILY) | tr a-w A-W) - -$(info $$FAMILY [${FAMILY}]) -$(info $$FAMILY_UC [${FAMILY_UC}]) $(info $$BOARD [${BOARD}]) $(info $$ENET_PHY [${ENET_PHY}]) SRCDIR=src src/gd32 $(EXTRA_SRCDIR) -include ../firmware-template-gd32/Includes.mk - DEFINES:=$(addprefix -D,$(DEFINES)) DEFINES+=-D_TIME_STAMP_YEAR_=$(shell date +"%Y") -D_TIME_STAMP_MONTH_=$(shell date +"%-m") -D_TIME_STAMP_DAY_=$(shell date +"%-d") -ifeq ($(findstring ARTNET_VERSION=4,$(DEFINES)),ARTNET_VERSION=4) - ifeq ($(findstring ARTNET_HAVE_DMXIN,$(DEFINES)),ARTNET_HAVE_DMXIN) - DEFINES+=-DE131_HAVE_DMXIN - endif -endif +MCU=GD32F207RG + +include ../firmware-template-gd32/Board.mk +include ../firmware-template-gd32/Mcu.mk +include ../firmware-template-gd32/Includes.mk +include ../firmware-template-gd32/Artnet.mk +include ../firmware-template-gd32/Validate.mk -COPS=-DBARE_METAL -DGD32 -DGD32F20X_CL -D$(MCU) -D$(BOARD) -DPHY_TYPE=$(ENET_PHY) -COPS+=$(DEFINES) $(MAKE_FLAGS) $(INCLUDES) -COPS+=-Os -mcpu=cortex-m3 -mthumb -COPS+=-nostartfiles -ffreestanding -nostdlib +INCLUDES+=-I../lib-configstore/include -I../lib-device/include -I../lib-display/include -I../lib-flash/include -I../lib-flashcode/include -I../lib-hal/include -I../lib-lightset/include -I../lib-network/include + +COPS=-DGD32 -D$(FAMILY_UCA) -D$(LINE_UC) -D$(MCU) -D$(BOARD) -DPHY_TYPE=$(ENET_PHY) +COPS+=$(strip $(DEFINES)) $(MAKE_FLAGS) $(INCLUDES) +COPS+=$(strip $(ARMOPS) $(CMSISOPS)) +COPS+=-Os -nostartfiles -ffreestanding -nostdlib COPS+=-fstack-usage COPS+=-ffunction-sections -fdata-sections -COPS+=-Wall -Werror -Wpedantic -Wextra -Wunused -Wsign-conversion -Wconversion -COPS+=-Wduplicated-cond -Wlogical-op +COPS+=-Wall -Werror -Wpedantic -Wextra -Wunused -Wsign-conversion -Wconversion -Wduplicated-cond -Wlogical-op -CPPOPS=-std=c++11 +CPPOPS=-std=c++20 CPPOPS+=-Wnon-virtual-dtor -Woverloaded-virtual -Wnull-dereference -fno-rtti -fno-exceptions -fno-unwind-tables CPPOPS+=-Wuseless-cast -Wold-style-cast CPPOPS+=-fno-threadsafe-statics -CURR_DIR:=$(notdir $(patsubst %/,%,$(CURDIR))) -LIB_NAME:=$(patsubst lib-%,%,$(CURR_DIR)) - BUILD=build_gd32/ BUILD_DIRS:=$(addprefix build_gd32/,$(SRCDIR)) $(info $$BUILD_DIRS [${BUILD_DIRS}]) @@ -66,19 +57,22 @@ EXTRA_BUILD_DIRS:=$(addsuffix $(EXTRA_C_DIRECTORIES), $(BUILD)) OBJECTS:=$(strip $(ASM_OBJECTS) $(C_OBJECTS) $(CPP_OBJECTS) $(EXTRA_C_OBJECTS)) -$(info $$OBJECTS [${OBJECTS}]) +CURR_DIR:=$(notdir $(patsubst %/,%,$(CURDIR))) +LIB_NAME:=$(patsubst lib-%,%,$(CURR_DIR)) +TARGET=lib_gd32/lib$(LIB_NAME).a -TARGET=lib_gd32/lib$(LIB_NAME).a +$(info $$DEFINES [${DEFINES}]) +$(info $$MAKE_FLAGS [${MAKE_FLAGS}]) +$(info $$OBJECTS [${OBJECTS}]) $(info $$TARGET [${TARGET}]) -LIST = lib.list - define compile-objects +$(info $1) $(BUILD)$1/%.o: $1/%.c $(CC) $(COPS) -c $$< -o $$@ $(BUILD)$1/%.o: $1/%.cpp - $(CPP) $(COPS) $(CPPOPS) -c $$< -o $$@ + $(CPP) $(COPS) $(CPPOPS) -c $$< -o $$@ $(BUILD)$1/%.o: $1/%.S $(CC) $(COPS) -D__ASSEMBLY__ -c $$< -o $$@ @@ -99,13 +93,13 @@ clean: $(BUILD)%.o: %.c $(CC) $(COPS) -c $< -o $@ - + $(BUILD_DIRS) : mkdir -p $(BUILD_DIRS) mkdir -p lib_gd32 $(TARGET): Makefile.GD32 $(OBJECTS) $(AR) -r $(TARGET) $(OBJECTS) - $(PREFIX)objdump -d $(TARGET) | $(PREFIX)c++filt > lib_gd32/$(LIST) + $(PREFIX)objdump -d $(TARGET) | $(PREFIX)c++filt > lib_gd32/lib.list $(foreach bdir,$(SRCDIR),$(eval $(call compile-objects,$(bdir)))) \ No newline at end of file diff --git a/firmware-template-gd32/startup_gd32f20x_cl.S b/firmware-template-gd32/startup_gd32f20x_cl.S index 851bf0bd..bf95a052 100644 --- a/firmware-template-gd32/startup_gd32f20x_cl.S +++ b/firmware-template-gd32/startup_gd32f20x_cl.S @@ -1,59 +1,93 @@ +/** + * @file startup_gd32f20x_cl.S + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + .syntax unified .cpu cortex-m3 .fpu softvfp .thumb - + .global Default_Handler -.word _sidata +/* Necessary symbols defined in linker script to initialize data */ .word _sdata +.word _sidata .word _edata .word _sbss .word _ebss -.section .text.Reset_Handler +.section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: - movs r1, #0 - b DataInit - +/* Copy .data section from FLASH to RAM */ CopyData: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -DataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyData - ldr r2, =_sbss - b Zerobss -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -Zerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss + ldr r1, =_sdata /* Load the start address of .data section (RAM) into r1 */ + ldr r2, =_sidata /* Load the start address of .data section (FLASH) into r2 */ + ldr r3, =_edata /* Load the end address of .data section (RAM) into r3 */ + subs r3, r3, r1 /* Calculate the size of .data section by subtracting start from end */ + beq ZeroBSS /* If size is zero, jump to ZeroBSS */ +CopyDataLoop: + ldrb r4, [r2], #1 /* Load a byte from Flash (source), post-increment r2 by 1 */ + strb r4, [r1], #1 /* Store the byte to RAM (destination), post-increment r1 by 1 */ + subs r3, r3, #1 /* Decrement the remaining byte count by 1 */ + bgt CopyDataLoop /* If there are still bytes left, continue looping */ +/* Initialize .bss section to zero */ +ZeroBSS: + ldr r2, =_sbss /* Load the start address of the .bss section */ + ldr r3, =_ebss /* Load the end address of the .bss section */ + sub r3, r3, r2 /* Calculate bytes count (r3 = (end - start) */ + mov r4, #0 /* Load zero into r4 */ +ZeroBSSLoop: + str r4, [r2], #4 /* Store zero to memory location, increment address */ + subs r3, r3, #4 /* Subtract 4 bytes from the remaining byte count */ + bgt ZeroBSSLoop /* If there are still bytes left, continue looping */ +/* Call stack_debug_init function if in debug mode */ #if defined (DEBUG_STACK) - bl stack_debug_init + bl stack_debug_init /* Branch to stack_debug_init if DEBUG_STACK is defined */ #endif +/* Call SystemInit function to perform system-specific initialization */ bl SystemInit +/* Call static constructors to initialize global objects */ + bl __libc_init_array +/* Call the main function to start the application */ bl main +/* Return from main (in case main returns) */ bx lr +/* NOP to align the code (optional) */ + nop /* No operation; used for code alignment and readability */ + .size Reset_Handler, .-Reset_Handler .section .text.Default_Handler,"ax",%progbits + Default_Handler: Infinite_Loop: b Infinite_Loop - .size Default_Handler, .-Default_Handler + +.size Default_Handler, .-Default_Handler .section .vectors,"a",%progbits .global __gVectors @@ -75,7 +109,6 @@ __gVectors: .word 0 /* Reserved */ .word PendSV_Handler /* 14:PendSV Handler */ .word SysTick_Handler /* 15:SysTick Handler */ - /* External Interrupts */ .word WWDGT_IRQHandler /*16,Window Watchdog Timer*/ .word LVD_IRQHandler /*17,LVD through EXTI Line detect */ @@ -170,6 +203,12 @@ __gVectors: .size __gVectors, . - __gVectors +/******************************************************************************* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +*******************************************************************************/ + .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler diff --git a/firmware-template/libs.mk b/firmware-template/libs.mk index 6e68aeb2..1f0b26c5 100755 --- a/firmware-template/libs.mk +++ b/firmware-template/libs.mk @@ -27,34 +27,29 @@ ifeq ($(findstring NODE_PP,$(DEFINES)),NODE_PP) LIBS+=pp endif -RDM= +ifeq ($(findstring NODE_SHOWFILE,$(DEFINES)),NODE_SHOWFILE) + LIBS+=showfile osc +endif ifeq ($(findstring RDM_CONTROLLER,$(DEFINES)),RDM_CONTROLLER) RDM=1 - ifeq ($(findstring NO_EMAC,$(DEFINES)),NO_EMAC) - else - LIBS+=rdmdiscovery - endif + DMX=1 endif ifeq ($(findstring RDM_RESPONDER,$(DEFINES)),RDM_RESPONDER) - ifneq ($(findstring rdmresponder,$(LIBS)),rdmresponder) - LIBS+=rdmresponder - endif ifneq ($(findstring rdmsensor,$(LIBS)),rdmsensor) - LIBS+=rdmsensor device - endif - ifneq ($(findstring rdmsubdevice,$(LIBS)),rdmsubdevice) - LIBS+=rdmsubdevice + LIBS+=rdmsensor endif - LIBS+=dmxreceiver dmx RDM=1 + ifneq ($(findstring NODE_ARTNET,$(DEFINES)),NODE_ARTNET) + ifeq ($(findstring OUTPUT_DMX_,$(DEFINES)),OUTPUT_DMX_) + DMX=1 + endif + endif endif ifeq ($(findstring NODE_RDMNET_LLRP_ONLY,$(DEFINES)),NODE_RDMNET_LLRP_ONLY) - ifneq ($(findstring rdmnet,$(LIBS)),rdmnet) - LIBS+=rdmnet - endif + RDM=1 ifneq ($(findstring e131,$(LIBS)),e131) LIBS+=e131 endif @@ -64,23 +59,23 @@ ifeq ($(findstring NODE_RDMNET_LLRP_ONLY,$(DEFINES)),NODE_RDMNET_LLRP_ONLY) ifneq ($(findstring rdmsubdevice,$(LIBS)),rdmsubdevice) LIBS+=rdmsubdevice endif - RDM=1 endif -ifdef RDM - LIBS+=rdm +ifeq ($(findstring OUTPUT_DMX_MONITOR,$(DEFINES)),OUTPUT_DMX_MONITOR) + LIBS+=dmxmonitor endif -ifeq ($(findstring e131,$(LIBS)),e131) - LIBS+=uuid +ifeq ($(findstring OUTPUT_DMX_SEND,$(DEFINES)),OUTPUT_DMX_SEND) + LIBS+= + DMX=1 endif -ifeq ($(findstring OUTPUT_DMX_MONITOR,$(DEFINES)),OUTPUT_DMX_MONITOR) - LIBS+=dmxmonitor +ifdef RDM + LIBS+=rdm endif -ifeq ($(findstring OUTPUT_DMX_SEND,$(DEFINES)),OUTPUT_DMX_SEND) - LIBS+=dmxsend dmx +ifdef DMX + LIBS+=dmx endif ifeq ($(findstring OUTPUT_DDP_PIXEL_MULTI,$(DEFINES)),OUTPUT_DDP_PIXEL_MULTI) @@ -99,12 +94,12 @@ ifeq ($(findstring OUTPUT_DDP_PIXEL,$(DEFINES)),OUTPUT_DDP_PIXEL) LIBS+=ws28xx endif -LIBS+=configstore flashcode network lightset +LIBS+=configstore flashcode network ifeq ($(findstring DISPLAY_UDF,$(DEFINES)),DISPLAY_UDF) LIBS+=displayudf endif -LIBS+=flash properties display hal +LIBS+=lightset flash properties display device hal -$(info $$LIBS [${LIBS}]) \ No newline at end of file +$(info $$LIBS [${LIBS}]) diff --git a/gd32_emac_artnet_dmx_multi/.cproject b/gd32_emac_artnet_dmx_multi/.cproject index 68eb245d..d74891b4 100644 --- a/gd32_emac_artnet_dmx_multi/.cproject +++ b/gd32_emac_artnet_dmx_multi/.cproject @@ -14,7 +14,7 @@ - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + diff --git a/gd32_emac_artnet_dmx_multi/Common.mk b/gd32_emac_artnet_dmx_multi/Common.mk new file mode 100644 index 00000000..13051062 --- /dev/null +++ b/gd32_emac_artnet_dmx_multi/Common.mk @@ -0,0 +1,19 @@ +DEFINES+=NODE_ARTNET_MULTI ARTNET_VERSION=4 +DEFINES+=ARTNET_HAVE_DMXIN +DEFINES+=ARTNET_HAVE_FAILSAFE_RECORD + +DEFINES+=OUTPUT_DMX_SEND_MULTI +DEFINES+=OUTPUT_HAVE_STYLESWITCH + +DEFINES+=RDM_CONTROLLER + +DEFINES+=CONFIG_STORE_USE_SPI + +DEFINES+=RTL8201F_LED1_LINK_ALL + +DEFINES+=DISPLAY_UDF + +DEFINES+=ENABLE_HTTPD ENABLE_CONTENT + +DEFINES+=DISABLE_RTC +DEFINES+=DISABLE_FS \ No newline at end of file diff --git a/gd32_emac_artnet_dmx_multi/Makefile-bw-softuart0.GD32 b/gd32_emac_artnet_dmx_multi/Makefile-bw-softuart0.GD32 index a11187cf..1598b18e 100644 --- a/gd32_emac_artnet_dmx_multi/Makefile-bw-softuart0.GD32 +++ b/gd32_emac_artnet_dmx_multi/Makefile-bw-softuart0.GD32 @@ -1,34 +1,21 @@ BOARD=BOARD_BW_OPIDMX4 -DEFINES =NODE_ARTNET_MULTI ARTNET_VERSION=4 LIGHTSET_PORTS=4 -DEFINES+=ARTNET_PAGE_SIZE=1 -DEFINES+=ARTNET_HAVE_DMXIN -DEFINES+=ARTNET_HAVE_FAILSAFE_RECORD - -DEFINES+=RDM_CONTROLLER - -DEFINES+=OUTPUT_DMX_SEND_MULTI -DEFINES+=OUTPUT_HAVE_STYLESWITCH +DEFINES=LIGHTSET_PORTS=4 DEFINES+=ENET_RXBUF_NUM=16 ENET_TXBUF_NUM=4 -DEFINES+=DISPLAY_UDF - -DEFINES+=ENABLE_HTTPD ENABLE_CONTENT - -DEFINES+=CONFIG_STORE_USE_SPI +# DEFINES+=CONFIG_USE_SOFTUART0 -DEFINES+=DISABLE_RTC -DEFINES+=DISABLE_FS - +DEFINES+=DEBUG_STACK DEFINES+=NDEBUG LIBS= SRCDIR=firmware lib +include Common.mk include ../firmware-template-gd32/Rules.mk prerequisites: diff --git a/gd32_emac_artnet_dmx_multi/Makefile-bw.GD32 b/gd32_emac_artnet_dmx_multi/Makefile-bw.GD32 index cd358a06..c0eec0f1 100644 --- a/gd32_emac_artnet_dmx_multi/Makefile-bw.GD32 +++ b/gd32_emac_artnet_dmx_multi/Makefile-bw.GD32 @@ -1,34 +1,21 @@ BOARD=BOARD_BW_OPIDMX4 -DEFINES =NODE_ARTNET_MULTI ARTNET_VERSION=4 LIGHTSET_PORTS=4 -DEFINES+=ARTNET_PAGE_SIZE=1 -DEFINES+=ARTNET_HAVE_DMXIN -DEFINES+=ARTNET_HAVE_FAILSAFE_RECORD - -DEFINES+=RDM_CONTROLLER - -DEFINES+=OUTPUT_DMX_SEND_MULTI -DEFINES+=OUTPUT_HAVE_STYLESWITCH +DEFINES=LIGHTSET_PORTS=4 DEFINES+=ENET_RXBUF_NUM=16 ENET_TXBUF_NUM=4 -DEFINES+=DISPLAY_UDF - -DEFINES+=ENABLE_HTTPD ENABLE_CONTENT - -DEFINES+=CONFIG_STORE_USE_SPI +# DEFINES+=CONSOLE_NULL -DEFINES+=DISABLE_RTC -DEFINES+=DISABLE_FS - +DEFINES+=DEBUG_STACK DEFINES+=NDEBUG LIBS= SRCDIR=firmware lib +include Common.mk include ../firmware-template-gd32/Rules.mk prerequisites: diff --git a/gd32_emac_artnet_dmx_multi/Makefile-dmx3.GD32 b/gd32_emac_artnet_dmx_multi/Makefile-dmx3.GD32 index 9ff19d78..78ce4ffa 100644 --- a/gd32_emac_artnet_dmx_multi/Makefile-dmx3.GD32 +++ b/gd32_emac_artnet_dmx_multi/Makefile-dmx3.GD32 @@ -1,32 +1,21 @@ BOARD=BOARD_DMX3 -DEFINES =NODE_ARTNET_MULTI ARTNET_VERSION=4 LIGHTSET_PORTS=3 -DEFINES+=ARTNET_PAGE_SIZE=1 -DEFINES+=ARTNET_HAVE_DMXIN -DEFINES+=ARTNET_HAVE_FAILSAFE_RECORD - -DEFINES+=RDM_CONTROLLER - -DEFINES+=OUTPUT_DMX_SEND_MULTI -DEFINES+=OUTPUT_HAVE_STYLESWITCH +DEFINES=LIGHTSET_PORTS=3 DEFINES+=ENET_RXBUF_NUM=16 ENET_TXBUF_NUM=4 -DEFINES+=DISPLAY_UDF - -DEFINES+=ENABLE_HTTPD ENABLE_CONTENT - -DEFINES+=CONFIG_STORE_USE_SPI +# -DEFINES+=DISABLE_RTC -DEFINES+=DISABLE_FS +# +DEFINES+=DEBUG_STACK DEFINES+=NDEBUG LIBS= SRCDIR=firmware lib +include Common.mk include ../firmware-template-gd32/Rules.mk prerequisites: diff --git a/gd32_emac_artnet_dmx_multi/Makefile-dmx4-softuart0.GD32 b/gd32_emac_artnet_dmx_multi/Makefile-dmx4-softuart0.GD32 index 77a4601f..28dab1bf 100644 --- a/gd32_emac_artnet_dmx_multi/Makefile-dmx4-softuart0.GD32 +++ b/gd32_emac_artnet_dmx_multi/Makefile-dmx4-softuart0.GD32 @@ -1,35 +1,21 @@ BOARD=BOARD_DMX4 -DEFINES =NODE_ARTNET_MULTI ARTNET_VERSION=4 LIGHTSET_PORTS=4 -DEFINES+=ARTNET_PAGE_SIZE=1 -DEFINES+=ARTNET_HAVE_DMXIN -DEFINES+=ARTNET_HAVE_FAILSAFE_RECORD - -DEFINES+=RDM_CONTROLLER - -DEFINES+=OUTPUT_DMX_SEND_MULTI -DEFINES+=OUTPUT_HAVE_STYLESWITCH +DEFINES=LIGHTSET_PORTS=4 DEFINES+=ENET_RXBUF_NUM=16 ENET_TXBUF_NUM=4 -DEFINES+=DISPLAY_UDF - -DEFINES+=ENABLE_HTTPD ENABLE_CONTENT +DEFINES+=LEDPANEL_595_COUNT=2 -DEFINES+=CONFIG_STORE_USE_SPI DEFINES+=CONFIG_USE_SOFTUART0 -DEFINES+=DISABLE_RTC -DEFINES+=DISABLE_FS - DEFINES+=DEBUG_STACK - DEFINES+=NDEBUG LIBS= SRCDIR=firmware lib +include Common.mk include ../firmware-template-gd32/Rules.mk prerequisites: diff --git a/gd32_emac_artnet_dmx_multi/Makefile-dmx4.GD32 b/gd32_emac_artnet_dmx_multi/Makefile-dmx4.GD32 index 8b1f27b6..8cb4d0ac 100644 --- a/gd32_emac_artnet_dmx_multi/Makefile-dmx4.GD32 +++ b/gd32_emac_artnet_dmx_multi/Makefile-dmx4.GD32 @@ -1,36 +1,21 @@ BOARD=BOARD_DMX4 -DEFINES =NODE_ARTNET_MULTI ARTNET_VERSION=4 LIGHTSET_PORTS=4 -DEFINES+=ARTNET_PAGE_SIZE=1 -DEFINES+=ARTNET_HAVE_DMXIN -DEFINES+=ARTNET_HAVE_FAILSAFE_RECORD - -DEFINES+=RDM_CONTROLLER - -DEFINES+=OUTPUT_DMX_SEND_MULTI -DEFINES+=OUTPUT_HAVE_STYLESWITCH +DEFINES=LIGHTSET_PORTS=4 DEFINES+=ENET_RXBUF_NUM=16 ENET_TXBUF_NUM=4 -DEFINES+=DISPLAY_UDF - -DEFINES+=ENABLE_HTTPD ENABLE_CONTENT - -DEFINES+=CONFIG_STORE_USE_SPI +DEFINES+=LEDPANEL_595_COUNT=2 DEFINES+=CONSOLE_NULL -DEFINES+=DISABLE_RTC -DEFINES+=DISABLE_FS - DEFINES+=DEBUG_STACK - DEFINES+=NDEBUG LIBS= SRCDIR=firmware lib +include Common.mk include ../firmware-template-gd32/Rules.mk prerequisites: diff --git a/gd32_emac_artnet_dmx_multi/Makefile.GD32 b/gd32_emac_artnet_dmx_multi/Makefile.GD32 index e0d4c574..32823fe5 100644 --- a/gd32_emac_artnet_dmx_multi/Makefile.GD32 +++ b/gd32_emac_artnet_dmx_multi/Makefile.GD32 @@ -1,31 +1,21 @@ BOARD=BOARD_GD32F207RG -DEFINES =NODE_ARTNET_MULTI ARTNET_VERSION=4 LIGHTSET_PORTS=2 -DEFINES+=ARTNET_HAVE_DMXIN -DEFINES+=ARTNET_HAVE_FAILSAFE_RECORD - -DEFINES+=RDM_CONTROLLER - -DEFINES+=OUTPUT_DMX_SEND_MULTI -DEFINES+=OUTPUT_HAVE_STYLESWITCH +DEFINES=LIGHTSET_PORTS=2 DEFINES+=ENET_RXBUF_NUM=8 ENET_TXBUF_NUM=4 -DEFINES+=DISPLAY_UDF - -DEFINES+=ENABLE_HTTPD ENABLE_CONTENT - -DEFINES+=CONFIG_STORE_USE_SPI +# -DEFINES+=DISABLE_RTC -DEFINES+=DISABLE_FS +# +DEFINES+=DEBUG_STACK DEFINES+=NDEBUG LIBS= SRCDIR=firmware lib +include Common.mk include ../firmware-template-gd32/Rules.mk prerequisites: diff --git a/gd32_emac_artnet_dmx_multi/do-tftp.sh b/gd32_emac_artnet_dmx_multi/do-tftp.sh index 8066e8dc..66bc49c3 100755 --- a/gd32_emac_artnet_dmx_multi/do-tftp.sh +++ b/gd32_emac_artnet_dmx_multi/do-tftp.sh @@ -11,6 +11,15 @@ echo '!tftp#1' | udp_send $1 ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true echo [$ON_LINE] +while [ "$ON_LINE" == "" ] + do + sleep 1 + echo '!tftp#1' | udp_send $1 + ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true +done + +echo [$ON_LINE] + while [ "$ON_LINE" == "tftp:Off" ] do sleep 1 @@ -18,6 +27,8 @@ while [ "$ON_LINE" == "tftp:Off" ] ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true done +echo [$ON_LINE] + sleep 1 echo -e "Rebooting..." echo '?reboot##' | udp_send $1 @@ -30,7 +41,26 @@ while [ "$ON_LINE" == "" ] done echo '!tftp#1' | udp_send $1 -echo '?tftp#' | udp_send $1 +ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true +echo [$ON_LINE] + +while [ "$ON_LINE" == "" ] + do + sleep 1 + echo '!tftp#1' | udp_send $1 + ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true +done + +echo [$ON_LINE] + +while [ "$ON_LINE" == "tftp:Off" ] + do + sleep 1 + echo '!tftp#1' | udp_send $1 + ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true +done + +echo [$ON_LINE] tftp $1 << -EOF binary @@ -39,9 +69,27 @@ quit -EOF echo '!tftp#0' | udp_send $1 -sleep 1 -echo '?tftp#' | udp_send $1 -sleep 2 +ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true +echo [$ON_LINE] + +while [ "$ON_LINE" == "" ] + do + sleep 1 + echo '!tftp#0' | udp_send $1 + ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true +done + +echo [$ON_LINE] + +while [ "$ON_LINE" == "tftp:On" ] + do + sleep 1 + echo '!tftp#0' | udp_send $1 + ON_LINE=$(echo '?tftp#' | udp_send $1 ) || true +done + +echo [$ON_LINE] + echo -e "Rebooting..." echo '?reboot##' | udp_send $1 diff --git a/gd32_emac_artnet_dmx_multi/firmware/main.cpp b/gd32_emac_artnet_dmx_multi/firmware/main.cpp index 0439baa4..842d13ed 100644 --- a/gd32_emac_artnet_dmx_multi/firmware/main.cpp +++ b/gd32_emac_artnet_dmx_multi/firmware/main.cpp @@ -2,7 +2,7 @@ * @file main.cpp * */ -/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -30,16 +30,15 @@ #include "network.h" #include "networkconst.h" -#include "mdns.h" +#include "net/apps/mdns.h" -#if defined (ENABLE_HTTPD) -# include "httpd/httpd.h" +#if defined (ENABLE_NTP_CLIENT) +# include "net/apps/ntpclient.h" #endif #include "displayudf.h" #include "displayudfparams.h" #include "displayhandler.h" -#include "display_timeout.h" #include "artnetnode.h" #include "artnetparams.h" @@ -51,83 +50,66 @@ #include "rdmdeviceparams.h" #include "dmxconfigudp.h" +#if defined (NODE_SHOWFILE) +# include "showfile.h" +# include "showfileparams.h" +#endif + #include "remoteconfig.h" #include "remoteconfigparams.h" #include "configstore.h" -#include "storeartnet.h" -#include "storedisplayudf.h" -#include "storedmxsend.h" -#include "storenetwork.h" -#include "storerdmdevice.h" -#include "storeremoteconfig.h" #include "firmwareversion.h" #include "software_version.h" -static constexpr uint32_t DMXPORT_OFFSET = 0; +namespace artnetnode { +namespace configstore { +uint32_t DMXPORT_OFFSET = 0; +} // namespace configstore +} // namespace artnetnode void Hardware::RebootHandler() { Dmx::Get()->Blackout(); ArtNetNode::Get()->Stop(); } -void main() { +int main() { Hardware hw; DisplayUdf display; ConfigStore configStore; - display.TextStatus(NetworkConst::MSG_NETWORK_INIT, Display7SegmentMessage::INFO_NETWORK_INIT, CONSOLE_YELLOW); - StoreNetwork storeNetwork; - Network nw(&storeNetwork); - display.TextStatus(NetworkConst::MSG_NETWORK_STARTED, Display7SegmentMessage::INFO_NONE, CONSOLE_GREEN); + display.TextStatus(NetworkConst::MSG_NETWORK_INIT, CONSOLE_YELLOW); + Network nw; + MDNS mDns; + display.TextStatus(NetworkConst::MSG_NETWORK_STARTED, CONSOLE_GREEN); FirmwareVersion fw(SOFTWARE_VERSION, __DATE__, __TIME__); fw.Print("Art-Net 4 DMX/RDM controller {" STR(LIGHTSET_PORTS) " Universes}"); - nw.Print(); - - display.TextStatus(NetworkConst::MSG_MDNS_CONFIG, Display7SegmentMessage::INFO_MDNS_CONFIG, CONSOLE_YELLOW); - - MDNS mDns; - mDns.AddServiceRecord(nullptr, mdns::Services::CONFIG, "node=Art-Net 4 DMX/RDM"); -#if defined (ENABLE_HTTPD) - mDns.AddServiceRecord(nullptr, mdns::Services::HTTP); -#endif - mDns.Print(); -#if defined (ENABLE_HTTPD) - HttpDaemon httpDaemon; +#if defined (ENABLE_NTP_CLIENT) + NtpClient ntpClient; + ntpClient.Start(); + ntpClient.Print(); #endif - display.TextStatus(ArtNetMsgConst::PARAMS, Display7SegmentMessage::INFO_NODE_PARMAMS, CONSOLE_YELLOW); - ArtNetNode node; - StoreArtNet storeArtNet(DMXPORT_OFFSET); - node.SetArtNetStore(&storeArtNet); - - ArtNetParams artnetParams(&storeArtNet); - - if (artnetParams.Load()) { - artnetParams.Dump(); - artnetParams.Set(DMXPORT_OFFSET); - } + ArtNetParams artnetParams; + artnetParams.Load(); + artnetParams.Set(); for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { node.SetUniverse(nPortIndex, artnetParams.GetDirection(nPortIndex), artnetParams.GetUniverse(nPortIndex)); } - StoreDmxSend storeDmxSend; - DmxParams dmxparams(&storeDmxSend); - Dmx dmx; - if (dmxparams.Load()) { - dmxparams.Dump(); - dmxparams.Set(&dmx); - } + DmxParams dmxparams; + dmxparams.Load(); + dmxparams.Set(&dmx); - for (uint32_t nPortIndex = DMXPORT_OFFSET; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { - const auto nDmxPortIndex = nPortIndex - DMXPORT_OFFSET; + for (uint32_t nPortIndex = artnetnode::configstore::DMXPORT_OFFSET; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { + const auto nDmxPortIndex = nPortIndex - artnetnode::configstore::DMXPORT_OFFSET; const auto portDirection = (node.GetPortDirection(nPortIndex) == lightset::PortDir::OUTPUT ? dmx::PortDirection::OUTP : dmx::PortDirection::INP); dmx.SetPortDirection(nDmxPortIndex, portDirection , false); } @@ -137,33 +119,26 @@ void main() { node.SetOutput(&dmxSend); - DmxConfigUdp dmxConfigUdp; - - StoreRDMDevice storeRdmDevice; - + RDMDeviceParams rdmDeviceParams; ArtNetRdmController artNetRdmController; - if (artnetParams.IsRdm()) { - RDMDeviceParams rdmDeviceParams(&storeRdmDevice); + rdmDeviceParams.Load(); + rdmDeviceParams.Set(&artNetRdmController); - if (rdmDeviceParams.Load()) { - rdmDeviceParams.Dump(); - rdmDeviceParams.Set(&artNetRdmController); - } + artNetRdmController.Init(); + artNetRdmController.Print(); - artNetRdmController.Init(); - artNetRdmController.Print(); + node.SetRdmController(&artNetRdmController, artnetParams.IsRdm()); - display.TextStatus(ArtNetMsgConst::RDM_RUN, Display7SegmentMessage::INFO_RDM_RUN, CONSOLE_YELLOW); +#if defined (NODE_SHOWFILE) + ShowFile showFile; - for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { - if (node.GetRdm(nPortIndex) && (node.GetPortDirection(nPortIndex) == lightset::PortDir::OUTPUT)) { - artNetRdmController.Full(nPortIndex); - } - } + ShowFileParams showFileParams; + showFileParams.Load(); + showFileParams.Set(); - node.SetRdmHandler(&artNetRdmController); - } + showFile.Print(); +#endif node.Print(); @@ -175,34 +150,29 @@ void main() { display.Set(4, displayudf::Labels::UNIVERSE_PORT_A); display.Set(5, displayudf::Labels::UNIVERSE_PORT_B); - StoreDisplayUdf storeDisplayUdf; - DisplayUdfParams displayUdfParams(&storeDisplayUdf); + DisplayUdfParams displayUdfParams; - if (displayUdfParams.Load()) { - displayUdfParams.Dump(); - displayUdfParams.Set(&display); - } + displayUdfParams.Load(); + displayUdfParams.Set(&display); - display.Show(&node); + display.Show(); RemoteConfig remoteConfig(remoteconfig::Node::ARTNET, artnetParams.IsRdm() ? remoteconfig::Output::RDM : remoteconfig::Output::DMX, nActivePorts); - StoreRemoteConfig storeRemoteConfig; - RemoteConfigParams remoteConfigParams(&storeRemoteConfig); - - if (remoteConfigParams.Load()) { - remoteConfigParams.Dump(); - remoteConfigParams.Set(&remoteConfig); - } + RemoteConfigParams remoteConfigParams; + remoteConfigParams.Load(); + remoteConfigParams.Set(&remoteConfig); while (configStore.Flash()) ; - display.TextStatus(ArtNetMsgConst::START, Display7SegmentMessage::INFO_NODE_START, CONSOLE_YELLOW); + mDns.Print(); + + display.TextStatus(ArtNetMsgConst::START, CONSOLE_YELLOW); node.Start(); - display.TextStatus(ArtNetMsgConst::STARTED, Display7SegmentMessage::INFO_NODE_STARTED, CONSOLE_GREEN); + display.TextStatus(ArtNetMsgConst::STARTED, CONSOLE_GREEN); hw.WatchdogInit(); @@ -210,14 +180,14 @@ void main() { hw.WatchdogFeed(); nw.Run(); node.Run(); +#if defined (NODE_SHOWFILE) + showFile.Run(); +#endif remoteConfig.Run(); configStore.Flash(); - if (node.GetActiveOutputPorts() != 0) { - dmxConfigUdp.Run(); - } mDns.Run(); -#if defined (ENABLE_HTTPD) - httpDaemon.Run(); +#if defined (ENABLE_NTP_CLIENT) + ntpClient.Run(); #endif display.Run(); hw.Run(); diff --git a/gd32_emac_artnet_dmx_multi/include/display_timeout.h b/gd32_emac_artnet_dmx_multi/include/display_timeout.h deleted file mode 100644 index c7ab4f3d..00000000 --- a/gd32_emac_artnet_dmx_multi/include/display_timeout.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - * @file display_timeout.h - * - */ -/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@gd32-dmx.org - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef DISPLAY_TIMEOUT_H_ -#define DISPLAY_TIMEOUT_H_ - -#include "gd32.h" - -namespace display { -namespace timeout { - -void gpio_init() { - gpio_fsel(KEY2_GPIOx, KEY2_PINx, GPIO_FSEL_INPUT); -} - -bool gpio_renew() { - return (GPIO_ISTAT(KEY2_GPIOx) & KEY2_PINx) == 0; -} - -} // namespace timeout -} // namespace display - -#endif /* DISPLAY_TIMEOUT_H_ */ diff --git a/gd32_emac_artnet_dmx_multi/lib/rdmsoftwareversion.cpp b/gd32_emac_artnet_dmx_multi/lib/rdmsoftwareversion.cpp index 5149f9a1..94271597 100644 --- a/gd32_emac_artnet_dmx_multi/lib/rdmsoftwareversion.cpp +++ b/gd32_emac_artnet_dmx_multi/lib/rdmsoftwareversion.cpp @@ -29,7 +29,7 @@ #include "rdmsoftwareversion.h" #include "software_version.h" -#include "sofware_version_id.h" +#include "software_version_id.h" const char *RDMSoftwareVersion::GetVersion() { return SOFTWARE_VERSION; diff --git a/lib-configstore/src/pixel/storepixeldmx.cpp b/gd32_emac_artnet_dmx_multi/lib/showfileusb.cpp similarity index 68% rename from lib-configstore/src/pixel/storepixeldmx.cpp rename to gd32_emac_artnet_dmx_multi/lib/showfileusb.cpp index a76ec476..657929f1 100644 --- a/lib-configstore/src/pixel/storepixeldmx.cpp +++ b/gd32_emac_artnet_dmx_multi/lib/showfileusb.cpp @@ -1,8 +1,9 @@ +#if defined (NODE_SHOWFILE) /** - * @file storewpixeldmx.cpp + * @file showfileusb.cpp * */ -/* Copyright (C) 2018-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,20 +24,32 @@ * THE SOFTWARE. */ -#include - -#include "storepixeldmx.h" +#include "showfile.h" #include "debug.h" -StorePixelDmx *StorePixelDmx::s_pThis; +namespace showfile { +void usb_ready() { + DEBUG_ENTRY + + ShowFile::Get()->SetPlayerShowFileCurrent(ShowFile::Get()->GetShowFileCurrent()); + + if (ShowFile::Get()->IsAutoStart()) { + ShowFile::Get()->Play(); + } else { + ShowFile::Get()->LoadShows(); + } + + DEBUG_EXIT +} -StorePixelDmx::StorePixelDmx() { +void usb_disconnected() { DEBUG_ENTRY - assert(s_pThis == nullptr); - s_pThis = this; + ShowFile::Get()->Stop(); + ShowFile::Get()->UnloadShows(); - DEBUG_PRINTF("%p", reinterpret_cast(s_pThis)); DEBUG_EXIT } +} // namespace showfile +#endif diff --git a/gd32_emac_artnet_pixel_multi/.cproject b/gd32_emac_artnet_pixel_multi/.cproject index f4797d14..a43372bb 100644 --- a/gd32_emac_artnet_pixel_multi/.cproject +++ b/gd32_emac_artnet_pixel_multi/.cproject @@ -22,22 +22,8 @@ - + - + - diff --git a/gd32_emac_artnet_pixel_multi/Makefile-softuart0.GD32 b/gd32_emac_artnet_pixel_multi/Makefile-softuart0.GD32 new file mode 100644 index 00000000..a83a1c33 --- /dev/null +++ b/gd32_emac_artnet_pixel_multi/Makefile-softuart0.GD32 @@ -0,0 +1,36 @@ +DEFINES =NODE_ARTNET_MULTI ARTNET_VERSION=4 LIGHTSET_PORTS=32 +DEFINES+=ARTNET_HAVE_TRIGGER +DEFINES+=ARTNET_HAVE_FAILSAFE_RECORD + +DEFINES+=NODE_RDMNET_LLRP_ONLY + +DEFINES+=OUTPUT_DMX_PIXEL_MULTI PIXELPATTERNS_MULTI +DEFINES+=CONFIG_PIXELDMX_MAX_PORTS=8 + +DEFINES+=ENET_RXBUF_NUM=34 ENET_TXBUF_NUM=3 +DEFINES+=RTL8201F_LED1_LINK_ALL + +DEFINES+=DISPLAY_UDF + +DEFINES+=ENABLE_HTTPD ENABLE_CONTENT + +DEFINES+=CONFIG_MDNS_DOMAIN_REVERSE +DEFINES+=CONFIG_STORE_USE_SPI +DEFINES+=CONFIG_USE_SOFTUART0 + +DEFINES+=DISABLE_RTC +DEFINES+=DISABLE_FS + +DEFINES+=DEBUG_STACK + +DEFINES+=NDEBUG + +LIBS= + +SRCDIR=firmware lib + +include ../firmware-template-gd32/Rules.mk + +prerequisites: + @echo "constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID="$(shell date "+%s")";" > ./include/software_version_id.h + diff --git a/gd32_emac_artnet_pixel_multi/Makefile.GD32 b/gd32_emac_artnet_pixel_multi/Makefile.GD32 index 21451f7c..5792cc9a 100644 --- a/gd32_emac_artnet_pixel_multi/Makefile.GD32 +++ b/gd32_emac_artnet_pixel_multi/Makefile.GD32 @@ -8,17 +8,21 @@ DEFINES+=OUTPUT_DMX_PIXEL_MULTI PIXELPATTERNS_MULTI DEFINES+=CONFIG_PIXELDMX_MAX_PORTS=8 DEFINES+=ENET_RXBUF_NUM=34 ENET_TXBUF_NUM=3 +DEFINES+=RTL8201F_LED1_LINK_ALL DEFINES+=DISPLAY_UDF DEFINES+=ENABLE_HTTPD ENABLE_CONTENT +DEFINES+=CONFIG_STORE_USE_SPI +DEFINES+=CONFIG_MDNS_DOMAIN_REVERSE + DEFINES+=DISABLE_RTC DEFINES+=DISABLE_FS -DEFINES+=CONFIG_STORE_USE_SPI - +DEFINES+=DEBUG_HEAP DEFINES+=DEBUG_STACK +DEFINES+=DEBUG_EMAC DEFINES+=NDEBUG @@ -29,4 +33,5 @@ SRCDIR=firmware lib include ../firmware-template-gd32/Rules.mk prerequisites: - ./generate_sofware_version_id.sh + @echo "constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID="$(shell date "+%s")";" > ./include/software_version_id.h + diff --git a/gd32_emac_artnet_pixel_multi/firmware/main.cpp b/gd32_emac_artnet_pixel_multi/firmware/main.cpp index 992c7fe3..cd41f706 100644 --- a/gd32_emac_artnet_pixel_multi/firmware/main.cpp +++ b/gd32_emac_artnet_pixel_multi/firmware/main.cpp @@ -2,7 +2,7 @@ * @file main.cpp * */ -/* Copyright (C) 2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -30,16 +30,19 @@ #include "network.h" #include "networkconst.h" -#include "mdns.h" +#include "net/apps/mdns.h" -#if defined (ENABLE_HTTPD) -# include "httpd/httpd.h" +#if defined (ENABLE_NTP_CLIENT) +# include "net/apps/ntpclient.h" +#endif + +#if defined (ENABLE_SHELL) +# include "shell/shell.h" #endif #include "displayudf.h" #include "displayudfparams.h" #include "displayhandler.h" -#include "display_timeout.h" #include "artnetnode.h" #include "artnetparams.h" @@ -50,7 +53,7 @@ #include "pixeltype.h" #include "pixeltestpattern.h" #include "pixeldmxparams.h" -#include "pixeldmxstartstop.h" + #include "ws28xxmulti.h" #include "ws28xxdmxmulti.h" @@ -62,84 +65,64 @@ # include "rdm_e120.h" #endif +#if defined (NODE_SHOWFILE) +# include "showfile.h" +# include "showfileparams.h" +#endif + #include "remoteconfig.h" #include "remoteconfigparams.h" #include "configstore.h" -#include "storeartnet.h" -#include "storedisplayudf.h" -#include "storenetwork.h" -#if defined (NODE_RDMNET_LLRP_ONLY) -# include "storerdmdevice.h" -#endif -#include "storeremoteconfig.h" -#include "storepixeldmx.h" #include "firmwareversion.h" #include "software_version.h" -static constexpr uint32_t DMXPORT_OFFSET = LIGHTSET_PORTS; +namespace artnetnode { +namespace configstore { +uint32_t DMXPORT_OFFSET = LIGHTSET_PORTS; +} // namespace configstore +} // namespace artnetnode void Hardware::RebootHandler() { WS28xxMulti::Get()->Blackout(); ArtNetNode::Get()->Stop(); } -void main() { +int main() { Hardware hw; DisplayUdf display; ConfigStore configStore; - display.TextStatus(NetworkConst::MSG_NETWORK_INIT, Display7SegmentMessage::INFO_NETWORK_INIT, CONSOLE_YELLOW); - StoreNetwork storeNetwork; - Network nw(&storeNetwork); - display.TextStatus(NetworkConst::MSG_NETWORK_STARTED, Display7SegmentMessage::INFO_NONE, CONSOLE_GREEN); - FirmwareVersion fw(SOFTWARE_VERSION, __DATE__, __TIME__); - - fw.Print("Art-Net 4 Pixel controller {8x 4 Universes}"); - nw.Print(); - - display.TextStatus(NetworkConst::MSG_MDNS_CONFIG, Display7SegmentMessage::INFO_MDNS_CONFIG, CONSOLE_YELLOW); - + display.TextStatus(NetworkConst::MSG_NETWORK_INIT, CONSOLE_YELLOW); + Network nw; MDNS mDns; - mDns.AddServiceRecord(nullptr, mdns::Services::CONFIG, "node=Art-Net Pixel"); -#if defined (ENABLE_HTTPD) - mDns.AddServiceRecord(nullptr, mdns::Services::HTTP); -#endif - mDns.Print(); + display.TextStatus(NetworkConst::MSG_NETWORK_STARTED, CONSOLE_GREEN); + FirmwareVersion fw(SOFTWARE_VERSION, __DATE__, __TIME__); -#if defined (ENABLE_HTTPD) - HttpDaemon httpDaemon; + fw.Print("Art-Net 4 Pixel controller"); + +#if defined (ENABLE_NTP_CLIENT) + NtpClient ntpClient; + ntpClient.Start(); + ntpClient.Print(); #endif - display.TextStatus(ArtNetMsgConst::PARAMS, Display7SegmentMessage::INFO_NODE_PARMAMS, CONSOLE_YELLOW); - ArtNetNode node; - StoreArtNet storeArtNet(DMXPORT_OFFSET); - node.SetArtNetStore(&storeArtNet); - - ArtNetParams artnetParams(&storeArtNet); - - if (artnetParams.Load()) { - artnetParams.Dump(); - artnetParams.Set(DMXPORT_OFFSET); - } + ArtNetParams artnetParams; + artnetParams.Load(); + artnetParams.Set(); PixelDmxConfiguration pixelDmxConfiguration; - StorePixelDmx storePixelDmx; - PixelDmxParams pixelDmxParams(&storePixelDmx); + PixelDmxParams pixelDmxParams; + pixelDmxParams.Load(); + pixelDmxParams.Set(); - if (pixelDmxParams.Load()) { - pixelDmxParams.Dump(); - pixelDmxParams.Set(&pixelDmxConfiguration); - } + WS28xxDmxMulti pixelDmxMulti; - WS28xxDmxMulti pixelDmxMulti(pixelDmxConfiguration); - pixelDmxMulti.SetPixelDmxHandler(new PixelDmxStartStop); - - const auto nPixelActivePorts = pixelDmxMulti.GetOutputPorts(); - const auto nUniverses = pixelDmxMulti.GetUniverses(); + const auto nPixelActivePorts = pixelDmxConfiguration.GetOutputPorts(); + const auto nUniverses = pixelDmxConfiguration.GetUniverses(); uint32_t nPortProtocolIndex = 0; @@ -160,7 +143,7 @@ void main() { const auto nTestPattern = static_cast(pixelDmxParams.GetTestPattern()); PixelTestPattern pixelTestPattern(nTestPattern, nPixelActivePorts); - if (PixelTestPattern::GetPattern() != pixelpatterns::Pattern::NONE) { + if (PixelTestPattern::Get()->GetPattern() != pixelpatterns::Pattern::NONE) { node.SetOutput(nullptr); } else { node.SetOutput(&pixelDmxMulti); @@ -169,9 +152,9 @@ void main() { ArtNetTriggerHandler triggerHandler(&pixelDmxMulti); #if defined (NODE_RDMNET_LLRP_ONLY) - display.TextStatus(RDMNetConst::MSG_CONFIG, Display7SegmentMessage::INFO_RDMNET_CONFIG, CONSOLE_YELLOW); + display.TextStatus(RDMNetConst::MSG_CONFIG, CONSOLE_YELLOW); char aDescription[rdm::personality::DESCRIPTION_MAX_LENGTH + 1]; - snprintf(aDescription, sizeof(aDescription) - 1, "Art-Net 4 Pixel %d-%s:%d", nPixelActivePorts, PixelType::GetType(WS28xxMulti::Get()->GetType()), WS28xxMulti::Get()->GetCount()); + snprintf(aDescription, sizeof(aDescription) - 1, "Art-Net 4 Pixel %d-%s:%d", nPixelActivePorts, pixel::pixel_get_type(pixelDmxConfiguration.GetType()), pixelDmxConfiguration.GetCount()); char aLabel[RDM_DEVICE_LABEL_MAX_LENGTH + 1]; const auto nLength = snprintf(aLabel, sizeof(aLabel) - 1, GD32_BOARD_NAME " Pixel"); @@ -187,41 +170,44 @@ void main() { llrpOnlyDevice.Init(); - StoreRDMDevice storeRdmDevice; - RDMDeviceParams rdmDeviceParams(&storeRdmDevice); + RDMDeviceParams rdmDeviceParams; - if (rdmDeviceParams.Load()) { - rdmDeviceParams.Dump(); - rdmDeviceParams.Set(&llrpOnlyDevice); - } + rdmDeviceParams.Load(); + rdmDeviceParams.Set(&llrpOnlyDevice); - llrpOnlyDevice.SetRDMDeviceStore(&storeRdmDevice); llrpOnlyDevice.Print(); #endif +#if defined (NODE_SHOWFILE) + ShowFile showFile; + + ShowFileParams showFileParams; + showFileParams.Load(); + showFileParams.Set(); + + showFile.Print(); +#endif + node.Print(); pixelDmxMulti.Print(); - display.SetTitle("ArtNet 4 Pixel %dx%d", nPixelActivePorts, WS28xxMulti::Get()->GetCount()); + display.SetTitle("ArtNet 4 Pixel %dx%d", nPixelActivePorts, pixelDmxConfiguration.GetCount()); display.Set(2, displayudf::Labels::IP); - display.Set(3, displayudf::Labels::VERSION); - display.Set(4, displayudf::Labels::UNIVERSE_PORT_A); + display.Set(3, displayudf::Labels::HOSTNAME); + display.Set(4, displayudf::Labels::VERSION); display.Set(5, displayudf::Labels::BOARDNAME); - StoreDisplayUdf storeDisplayUdf; - DisplayUdfParams displayUdfParams(&storeDisplayUdf); + DisplayUdfParams displayUdfParams; - if (displayUdfParams.Load()) { - displayUdfParams.Dump(); - displayUdfParams.Set(&display); - } + displayUdfParams.Load(); + displayUdfParams.Set(&display); - display.Show(&node, DMXPORT_OFFSET); + display.Show(); display.Printf(7, "%s:%d G%d %s", - PixelType::GetType(pixelDmxConfiguration.GetType()), + pixel::pixel_get_type(pixelDmxConfiguration.GetType()), pixelDmxConfiguration.GetCount(), pixelDmxConfiguration.GetGroupingCount(), - PixelType::GetMap(pixelDmxConfiguration.GetMap())); + pixel::pixel_get_map(pixelDmxConfiguration.GetMap())); if (nTestPattern != pixelpatterns::Pattern::NONE) { display.ClearLine(6); @@ -230,22 +216,24 @@ void main() { RemoteConfig remoteConfig(remoteconfig::Node::ARTNET, remoteconfig::Output::PIXEL, node.GetActiveOutputPorts()); - StoreRemoteConfig storeRemoteConfig; - RemoteConfigParams remoteConfigParams(&storeRemoteConfig); - - if(remoteConfigParams.Load()) { - remoteConfigParams.Dump(); - remoteConfigParams.Set(&remoteConfig); - } + RemoteConfigParams remoteConfigParams; + remoteConfigParams.Load(); + remoteConfigParams.Set(&remoteConfig); while (configStore.Flash()) ; - display.TextStatus(ArtNetMsgConst::START, Display7SegmentMessage::INFO_NODE_START, CONSOLE_YELLOW); + mDns.Print(); + +#if defined (ENABLE_SHELL) + Shell shell; +#endif + + display.TextStatus(ArtNetMsgConst::START, CONSOLE_YELLOW); node.Start(); - display.TextStatus(ArtNetMsgConst::STARTED, Display7SegmentMessage::INFO_NODE_STARTED, CONSOLE_GREEN); + display.TextStatus(ArtNetMsgConst::STARTED, CONSOLE_GREEN); hw.WatchdogInit(); @@ -253,19 +241,23 @@ void main() { hw.WatchdogFeed(); nw.Run(); node.Run(); +#if defined (NODE_SHOWFILE) + showFile.Run(); +#endif remoteConfig.Run(); configStore.Flash(); - if (__builtin_expect((PixelTestPattern::GetPattern() != pixelpatterns::Pattern::NONE), 0)) { - pixelTestPattern.Run(); - } + pixelTestPattern.Run(); mDns.Run(); +#if defined (ENABLE_NTP_CLIENT) + ntpClient.Run(); +#endif #if defined (NODE_RDMNET_LLRP_ONLY) llrpOnlyDevice.Run(); -#endif -#if defined (ENABLE_HTTPD) - httpDaemon.Run(); #endif display.Run(); hw.Run(); +#if defined (ENABLE_SHELL) + shell.Run(); +#endif } } diff --git a/gd32_emac_artnet_pixel_multi/generate_sofware_version_id.sh b/gd32_emac_artnet_pixel_multi/generate_sofware_version_id.sh deleted file mode 100755 index 2f453f59..00000000 --- a/gd32_emac_artnet_pixel_multi/generate_sofware_version_id.sh +++ /dev/null @@ -1,4 +0,0 @@ -echo "// Generated "$(date) > ./include/sofware_version_id.h -var="$(date +%s)" -echo "constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID="$var";" >> ./include/sofware_version_id.h - diff --git a/gd32_emac_artnet_pixel_multi/include/display_timeout.h b/gd32_emac_artnet_pixel_multi/include/display_timeout.h deleted file mode 100644 index a8556629..00000000 --- a/gd32_emac_artnet_pixel_multi/include/display_timeout.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - * @file display_timeout.h - * - */ -/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@gd32-dmx.org - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef DISPLAY_TIMEOUT_H_ -#define DISPLAY_TIMEOUT_H_ - -#include "gd32.h" - -namespace display { -namespace timeout { - -void gpio_init() { - gpio_fsel(KEY2_GPIOx, KEY2_PINx, GPIO_FSEL_INPUT); -} - -bool gpio_renew() { - return (GPIO_ISTAT(KEY2_GPIOx) & KEY2_PINx) == 0; -} - -} // namespace timeout -} // namespace display - -#endif /* DISPLAY_TIMEOUT_H_ */ diff --git a/gd32_emac_artnet_pixel_multi/include/pixeldmxstartstop.h b/gd32_emac_artnet_pixel_multi/include/pixeldmxstartstop.h deleted file mode 100644 index bca3ee30..00000000 --- a/gd32_emac_artnet_pixel_multi/include/pixeldmxstartstop.h +++ /dev/null @@ -1,53 +0,0 @@ -/** - * @file pixeldmxstartstop.h - * - */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@gd32-dmx.org - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef PIXELDMXSTARTSTOP_H_ -#define PIXELDMXSTARTSTOP_H_ - -#include "pixeldmxhandler.h" - -#include "gd32.h" -#include "gd32_gpio.h" - -class PixelDmxStartStop final: public PixelDmxHandler { -public: - PixelDmxStartStop() { - gd32_gpio_fsel(GD32_BOARD_LED2, GPIO_FSEL_OUTPUT); - gd32_gpio_clr(GD32_BOARD_LED2); - } - - ~PixelDmxStartStop() override { - } - - void Start() override { - gd32_gpio_set(GD32_BOARD_LED2); - } - - void Stop() override { - gd32_gpio_clr(GD32_BOARD_LED2); - } -}; - -#endif /* PIXELDMXSTARTSTOP_H_ */ diff --git a/gd32_emac_artnet_pixel_multi/include/sofware_version_id.h b/gd32_emac_artnet_pixel_multi/include/sofware_version_id.h deleted file mode 100644 index 76d37b26..00000000 --- a/gd32_emac_artnet_pixel_multi/include/sofware_version_id.h +++ /dev/null @@ -1,2 +0,0 @@ -// Generated wo 18 okt 2023 15:47:21 CEST -constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID=1697636842; diff --git a/gd32_emac_artnet_pixel_multi/lib/factorydefaults.cpp b/gd32_emac_artnet_pixel_multi/lib/factorydefaults.cpp index 971fc158..1741e5e2 100644 --- a/gd32_emac_artnet_pixel_multi/lib/factorydefaults.cpp +++ b/gd32_emac_artnet_pixel_multi/lib/factorydefaults.cpp @@ -28,7 +28,7 @@ #include "remoteconfig.h" #include "configstore.h" -#include "storenetwork.h" +#include "networkstore.h" namespace rdm { namespace device { @@ -37,7 +37,7 @@ namespace responder { void factorydefaults() { RemoteConfig::Get()->SetDisable(false); ConfigStore::Get()->ResetSetList(configstore::Store::RDMDEVICE); - StoreNetwork::Get()->SaveDhcp(true); + NetworkStore::SaveDhcp(true); } } // namespace responder diff --git a/gd32_emac_artnet_pixel_multi/lib/rdmsoftwareversion.cpp b/gd32_emac_artnet_pixel_multi/lib/rdmsoftwareversion.cpp index 5149f9a1..94271597 100644 --- a/gd32_emac_artnet_pixel_multi/lib/rdmsoftwareversion.cpp +++ b/gd32_emac_artnet_pixel_multi/lib/rdmsoftwareversion.cpp @@ -29,7 +29,7 @@ #include "rdmsoftwareversion.h" #include "software_version.h" -#include "sofware_version_id.h" +#include "software_version_id.h" const char *RDMSoftwareVersion::GetVersion() { return SOFTWARE_VERSION; diff --git a/gd32_emac_artnet_pixel_multi/lib/showfileusb.cpp b/gd32_emac_artnet_pixel_multi/lib/showfileusb.cpp new file mode 100644 index 00000000..657929f1 --- /dev/null +++ b/gd32_emac_artnet_pixel_multi/lib/showfileusb.cpp @@ -0,0 +1,55 @@ +#if defined (NODE_SHOWFILE) +/** + * @file showfileusb.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "showfile.h" + +#include "debug.h" + +namespace showfile { +void usb_ready() { + DEBUG_ENTRY + + ShowFile::Get()->SetPlayerShowFileCurrent(ShowFile::Get()->GetShowFileCurrent()); + + if (ShowFile::Get()->IsAutoStart()) { + ShowFile::Get()->Play(); + } else { + ShowFile::Get()->LoadShows(); + } + + DEBUG_EXIT +} + +void usb_disconnected() { + DEBUG_ENTRY + + ShowFile::Get()->Stop(); + ShowFile::Get()->UnloadShows(); + + DEBUG_EXIT +} +} // namespace showfile +#endif diff --git a/gd32_emac_ddp_pixel_multi/.cproject b/gd32_emac_ddp_pixel_multi/.cproject index 9f2741b0..1fbb09a0 100755 --- a/gd32_emac_ddp_pixel_multi/.cproject +++ b/gd32_emac_ddp_pixel_multi/.cproject @@ -23,7 +23,6 @@ - + @@ -99,20 +80,7 @@ - + diff --git a/gd32_emac_ddp_pixel_multi/.settings/language.settings.xml b/gd32_emac_ddp_pixel_multi/.settings/language.settings.xml index 6c30e852..96cd3e7a 100755 --- a/gd32_emac_ddp_pixel_multi/.settings/language.settings.xml +++ b/gd32_emac_ddp_pixel_multi/.settings/language.settings.xml @@ -5,7 +5,7 @@ - + diff --git a/gd32_emac_ddp_pixel_multi/Makefile.GD32 b/gd32_emac_ddp_pixel_multi/Makefile.GD32 index 498bca12..e52c6828 100755 --- a/gd32_emac_ddp_pixel_multi/Makefile.GD32 +++ b/gd32_emac_ddp_pixel_multi/Makefile.GD32 @@ -26,4 +26,5 @@ SRCDIR=firmware lib include ../firmware-template-gd32/Rules.mk prerequisites: - ./generate_sofware_version_id.sh + @echo "constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID="$(shell date "+%s")";" > ./include/software_version_id.h + diff --git a/gd32_emac_ddp_pixel_multi/firmware/main.cpp b/gd32_emac_ddp_pixel_multi/firmware/main.cpp index 17b62f87..b4a2ddbb 100644 --- a/gd32_emac_ddp_pixel_multi/firmware/main.cpp +++ b/gd32_emac_ddp_pixel_multi/firmware/main.cpp @@ -2,7 +2,7 @@ * @file main.cpp * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -31,16 +31,15 @@ #include "network.h" #include "networkconst.h" -#include "mdns.h" +#include "net/apps/mdns.h" -#if defined (ENABLE_HTTPD) -# include "httpd/httpd.h" +#if defined (ENABLE_NTP_CLIENT) +# include "net/apps/ntpclient.h" #endif #include "displayudf.h" #include "displayudfparams.h" #include "displayhandler.h" -#include "display_timeout.h" #include "ddpdisplay.h" @@ -48,9 +47,9 @@ #include "pixeltype.h" #include "pixeltestpattern.h" #include "pixeldmxparams.h" + #include "ws28xxmulti.h" #include "ws28xxdmxmulti.h" -#include "ws28xxdmxstartstop.h" #if defined (NODE_RDMNET_LLRP_ONLY) # include "rdmdeviceparams.h" @@ -64,13 +63,7 @@ #include "remoteconfigparams.h" #include "configstore.h" -#include "storedisplayudf.h" -#include "storenetwork.h" -#if defined (NODE_RDMNET_LLRP_ONLY) -# include "storerdmdevice.h" -#endif -#include "storeremoteconfig.h" -#include "storepixeldmx.h" + #include "firmwareversion.h" #include "software_version.h" @@ -80,51 +73,41 @@ void Hardware::RebootHandler() { DdpDisplay::Get()->Stop(); } -void main() { +int main() { Hardware hw; DisplayUdf display; ConfigStore configStore; - display.TextStatus(NetworkConst::MSG_NETWORK_INIT, Display7SegmentMessage::INFO_NETWORK_INIT, CONSOLE_YELLOW); - StoreNetwork storeNetwork; - Network nw(&storeNetwork); - display.TextStatus(NetworkConst::MSG_NETWORK_STARTED, Display7SegmentMessage::INFO_NONE, CONSOLE_GREEN); + display.TextStatus(NetworkConst::MSG_NETWORK_INIT, CONSOLE_YELLOW); + Network nw; + display.TextStatus(NetworkConst::MSG_NETWORK_STARTED, CONSOLE_GREEN); FirmwareVersion fw(SOFTWARE_VERSION, __DATE__, __TIME__); fw.Print("DDP Pixel controller {8x 4 Universes}"); - nw.Print(); + - display.TextStatus(NetworkConst::MSG_MDNS_CONFIG, Display7SegmentMessage::INFO_MDNS_CONFIG, CONSOLE_YELLOW); +#if defined (ENABLE_NTP_CLIENT) + NtpClient ntpClient; + ntpClient.Start(); + ntpClient.Print(); +#endif MDNS mDns; - mDns.AddServiceRecord(nullptr, mdns::Services::CONFIG, "node=DDP Pixel"); - mDns.AddServiceRecord(nullptr, mdns::Services::DDP, "type=display"); -#if defined (ENABLE_HTTPD) - mDns.AddServiceRecord(nullptr, mdns::Services::HTTP); -#endif + mDns.ServiceRecordAdd(nullptr, mdns::Services::DDP, "type=display"); mDns.Print(); -#if defined (ENABLE_HTTPD) - HttpDaemon httpDaemon; -#endif - PixelDmxConfiguration pixelDmxConfiguration; - StorePixelDmx storePixelDmx; - PixelDmxParams pixelDmxParams(&storePixelDmx); + PixelDmxParams pixelDmxParams; + pixelDmxParams.Load(); + pixelDmxParams.Set(); - if (pixelDmxParams.Load()) { - pixelDmxParams.Dump(); - pixelDmxParams.Set(&pixelDmxConfiguration); - } - - WS28xxDmxMulti pixelDmxMulti(pixelDmxConfiguration); - pixelDmxMulti.SetPixelDmxHandler(new PixelDmxStartStop); + WS28xxDmxMulti pixelDmxMulti; DdpDisplay ddpDisplay; - const auto nActivePorts = pixelDmxMulti.GetOutputPorts(); + const auto nActivePorts = pixelDmxConfiguration.GetOutputPorts(); - ddpDisplay.SetCount(pixelDmxMulti.GetGroups(), pixelDmxMulti.GetChannelsPerPixel(), nActivePorts); + ddpDisplay.SetCount(pixelDmxConfiguration.GetGroups(), pixelDmxConfiguration.GetLedsPerPixel(), nActivePorts); const auto nTestPattern = static_cast(pixelDmxParams.GetTestPattern()); PixelTestPattern pixelTestPattern(nTestPattern, nActivePorts); @@ -133,10 +116,10 @@ void main() { ddpDisplay.Print(); #if defined (NODE_RDMNET_LLRP_ONLY) - display.TextStatus(RDMNetConst::MSG_CONFIG, Display7SegmentMessage::INFO_RDMNET_CONFIG, CONSOLE_YELLOW); + display.TextStatus(RDMNetConst::MSG_CONFIG, CONSOLE_YELLOW); char aDescription[rdm::personality::DESCRIPTION_MAX_LENGTH + 1]; - snprintf(aDescription, sizeof(aDescription) - 1, "DDP Display %u-%s:%d", nActivePorts, PixelType::GetType(WS28xxMulti::Get()->GetType()), WS28xxMulti::Get()->GetCount()); + snprintf(aDescription, sizeof(aDescription) - 1, "DDP Display %u-%s:%d", nActivePorts, pixel::pixel_get_type(pixelDmxConfiguration.GetType()), pixelDmxConfiguration.GetCount()); char aLabel[RDM_DEVICE_LABEL_MAX_LENGTH + 1]; const auto nLength = snprintf(aLabel, sizeof(aLabel) - 1, "Orange Pi Zero Pixel"); @@ -149,15 +132,11 @@ void main() { llrpOnlyDevice.SetProductDetail(E120_PRODUCT_DETAIL_LED); llrpOnlyDevice.Init(); - StoreRDMDevice storeRdmDevice; - RDMDeviceParams rdmDeviceParams(&storeRdmDevice); + RDMDeviceParams rdmDeviceParams; - if (rdmDeviceParams.Load()) { - rdmDeviceParams.Dump(); - rdmDeviceParams.Set(&llrpOnlyDevice); - } + rdmDeviceParams.Load(); + rdmDeviceParams.Set(&llrpOnlyDevice); - llrpOnlyDevice.SetRDMDeviceStore(&storeRdmDevice); llrpOnlyDevice.Print(); #endif @@ -168,20 +147,17 @@ void main() { display.Set(5, displayudf::Labels::DEFAULT_GATEWAY); display.Set(6, displayudf::Labels::BOARDNAME); - StoreDisplayUdf storeDisplayUdf; - DisplayUdfParams displayUdfParams(&storeDisplayUdf); + DisplayUdfParams displayUdfParams; - if (displayUdfParams.Load()) { - displayUdfParams.Dump(); - displayUdfParams.Set(&display); - } + displayUdfParams.Load(); + displayUdfParams.Set(&display); display.Show(); display.Printf(7, "%s:%d G%d %s", - PixelType::GetType(pixelDmxConfiguration.GetType()), + pixel::pixel_get_type(pixelDmxConfiguration.GetType()), pixelDmxConfiguration.GetCount(), pixelDmxConfiguration.GetGroupingCount(), - PixelType::GetMap(pixelDmxConfiguration.GetMap())); + pixel::pixel_get_map(pixelDmxConfiguration.GetMap())); if (nTestPattern != pixelpatterns::Pattern::NONE) { display.ClearLine(6); @@ -190,22 +166,18 @@ void main() { RemoteConfig remoteConfig(remoteconfig::Node::DDP, remoteconfig::Output::PIXEL, nActivePorts); - StoreRemoteConfig storeRemoteConfig; - RemoteConfigParams remoteConfigParams(&storeRemoteConfig); - - if(remoteConfigParams.Load()) { - remoteConfigParams.Dump(); - remoteConfigParams.Set(&remoteConfig); - } + RemoteConfigParams remoteConfigParams; + remoteConfigParams.Load(); + remoteConfigParams.Set(&remoteConfig); while (configStore.Flash()) ; - display.TextStatus("Starting DDP Display", Display7SegmentMessage::INFO_BRIDGE_START, CONSOLE_YELLOW); + display.TextStatus("Starting DDP Display", CONSOLE_YELLOW); ddpDisplay.Start(); - display.TextStatus("DDP Display Started", Display7SegmentMessage::INFO_BRIDGE_START, CONSOLE_GREEN); + display.TextStatus("DDP Display Started", CONSOLE_GREEN); hw.WatchdogInit(); @@ -215,15 +187,13 @@ void main() { ddpDisplay.Run(); remoteConfig.Run(); configStore.Flash(); - if (__builtin_expect((PixelTestPattern::GetPattern() != pixelpatterns::Pattern::NONE), 0)) { - pixelTestPattern.Run(); - } + pixelTestPattern.Run(); mDns.Run(); +#if defined (ENABLE_NTP_CLIENT) + ntpClient.Run(); +#endif #if defined (NODE_RDMNET_LLRP_ONLY) llrpOnlyDevice.Run(); -#endif -#if defined (ENABLE_HTTPD) - httpDaemon.Run(); #endif display.Run(); hw.Run(); diff --git a/gd32_emac_ddp_pixel_multi/generate_sofware_version_id.sh b/gd32_emac_ddp_pixel_multi/generate_sofware_version_id.sh deleted file mode 100755 index 2f453f59..00000000 --- a/gd32_emac_ddp_pixel_multi/generate_sofware_version_id.sh +++ /dev/null @@ -1,4 +0,0 @@ -echo "// Generated "$(date) > ./include/sofware_version_id.h -var="$(date +%s)" -echo "constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID="$var";" >> ./include/sofware_version_id.h - diff --git a/gd32_emac_ddp_pixel_multi/include/sofware_version_id.h b/gd32_emac_ddp_pixel_multi/include/sofware_version_id.h deleted file mode 100644 index b6751745..00000000 --- a/gd32_emac_ddp_pixel_multi/include/sofware_version_id.h +++ /dev/null @@ -1,2 +0,0 @@ -// Generated wo 18 okt 2023 15:47:29 CEST -constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID=1697636849; diff --git a/gd32_emac_ddp_pixel_multi/lib/factorydefaults.cpp b/gd32_emac_ddp_pixel_multi/lib/factorydefaults.cpp index 971fc158..1741e5e2 100644 --- a/gd32_emac_ddp_pixel_multi/lib/factorydefaults.cpp +++ b/gd32_emac_ddp_pixel_multi/lib/factorydefaults.cpp @@ -28,7 +28,7 @@ #include "remoteconfig.h" #include "configstore.h" -#include "storenetwork.h" +#include "networkstore.h" namespace rdm { namespace device { @@ -37,7 +37,7 @@ namespace responder { void factorydefaults() { RemoteConfig::Get()->SetDisable(false); ConfigStore::Get()->ResetSetList(configstore::Store::RDMDEVICE); - StoreNetwork::Get()->SaveDhcp(true); + NetworkStore::SaveDhcp(true); } } // namespace responder diff --git a/gd32_emac_ddp_pixel_multi/lib/rdmsoftwareversion.cpp b/gd32_emac_ddp_pixel_multi/lib/rdmsoftwareversion.cpp index 906bb504..1f6d4aa4 100644 --- a/gd32_emac_ddp_pixel_multi/lib/rdmsoftwareversion.cpp +++ b/gd32_emac_ddp_pixel_multi/lib/rdmsoftwareversion.cpp @@ -28,7 +28,7 @@ #include "rdmsoftwareversion.h" #include "software_version.h" -#include "sofware_version_id.h" +#include "software_version_id.h" const char *RDMSoftwareVersion::GetVersion() { return SOFTWARE_VERSION; diff --git a/gd32_emac_e131_dmx_multi/.cproject b/gd32_emac_e131_dmx_multi/.cproject index d8886bc0..751c7249 100644 --- a/gd32_emac_e131_dmx_multi/.cproject +++ b/gd32_emac_e131_dmx_multi/.cproject @@ -31,11 +31,9 @@ - - diff --git a/gd32_emac_e131_dmx_multi/Common.mk b/gd32_emac_e131_dmx_multi/Common.mk new file mode 100644 index 00000000..a0da208a --- /dev/null +++ b/gd32_emac_e131_dmx_multi/Common.mk @@ -0,0 +1,10 @@ +DEFINES+=CONFIG_STORE_USE_SPI + +DEFINES+=RTL8201F_LED1_LINK_ALL + +DEFINES+=DISPLAY_UDF + +DEFINES+=ENABLE_HTTPD ENABLE_CONTENT + +DEFINES+=DISABLE_RTC +DEFINES+=DISABLE_FS \ No newline at end of file diff --git a/gd32_emac_e131_dmx_multi/Makefile.GD32 b/gd32_emac_e131_dmx_multi/Makefile.GD32 index d69a953c..e942f995 100644 --- a/gd32_emac_e131_dmx_multi/Makefile.GD32 +++ b/gd32_emac_e131_dmx_multi/Makefile.GD32 @@ -7,6 +7,7 @@ DEFINES+=OUTPUT_DMX_SEND_MULTI DEFINES+=OUTPUT_HAVE_STYLESWITCH DEFINES+=ENET_RXBUF_NUM=8 ENET_TXBUF_NUM=2 +DEFINES+=RTL8201F_LED1_LINK_ALL DEFINES+=DISPLAY_UDF @@ -28,5 +29,6 @@ SRCDIR=firmware lib include ../firmware-template-gd32/Rules.mk prerequisites: - ./generate_sofware_version_id.sh + @echo "constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID="$(shell date "+%s")";" > ./include/software_version_id.h + diff --git a/gd32_emac_e131_dmx_multi/firmware/main.cpp b/gd32_emac_e131_dmx_multi/firmware/main.cpp index f1e28bb3..56247075 100644 --- a/gd32_emac_e131_dmx_multi/firmware/main.cpp +++ b/gd32_emac_e131_dmx_multi/firmware/main.cpp @@ -2,7 +2,7 @@ * @file main.cpp * */ -/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,16 +29,15 @@ #include "network.h" #include "networkconst.h" -#include "mdns.h" +#include "net/apps/mdns.h" -#if defined (ENABLE_HTTPD) -# include "httpd/httpd.h" +#if defined (ENABLE_NTP_CLIENT) +# include "net/apps/ntpclient.h" #endif #include "displayudf.h" #include "displayudfparams.h" #include "displayhandler.h" -#include "display_timeout.h" #include "e131.h" #include "e131bridge.h" @@ -57,66 +56,53 @@ # include "rdm_e120.h" #endif +#if defined (NODE_SHOWFILE) +# include "showfile.h" +# include "showfileparams.h" +#endif + #include "remoteconfig.h" #include "remoteconfigparams.h" #include "configstore.h" -#include "storedisplayudf.h" -#include "storedmxsend.h" -#include "storee131.h" -#include "storenetwork.h" -#if defined (NODE_RDMNET_LLRP_ONLY) -# include "storerdmdevice.h" -#endif -#include "storeremoteconfig.h" #include "firmwareversion.h" #include "software_version.h" -static constexpr uint32_t DMXPORT_OFFSET = 0; +namespace e131bridge { +namespace configstore { +uint32_t DMXPORT_OFFSET = 0; +} // namespace configstore +} // namespace e131bridge void Hardware::RebootHandler() { Dmx::Get()->Blackout(); E131Bridge::Get()->Stop(); } -void main() { +int main() { Hardware hw; DisplayUdf display; ConfigStore configStore; - display.TextStatus(NetworkConst::MSG_NETWORK_INIT, Display7SegmentMessage::INFO_NETWORK_INIT, CONSOLE_YELLOW); - StoreNetwork storeNetwork; - Network nw(&storeNetwork); - display.TextStatus(NetworkConst::MSG_NETWORK_STARTED, Display7SegmentMessage::INFO_NONE, CONSOLE_GREEN); + display.TextStatus(NetworkConst::MSG_NETWORK_INIT, CONSOLE_YELLOW); + Network nw; + MDNS mDns; + display.TextStatus(NetworkConst::MSG_NETWORK_STARTED, CONSOLE_GREEN); FirmwareVersion fw(SOFTWARE_VERSION, __DATE__, __TIME__); fw.Print("sACN E1.31 DMX {" STR(LIGHTSET_PORTS) " Universes}"); - nw.Print(); - - display.TextStatus(NetworkConst::MSG_MDNS_CONFIG, Display7SegmentMessage::INFO_MDNS_CONFIG, CONSOLE_YELLOW); - - MDNS mDns; - mDns.AddServiceRecord(nullptr, mdns::Services::CONFIG, "node=sACN E1.31 DMX"); -#if defined (ENABLE_HTTPD) - mDns.AddServiceRecord(nullptr, mdns::Services::HTTP); -#endif - mDns.Print(); -#if defined (ENABLE_HTTPD) - HttpDaemon httpDaemon; +#if defined (ENABLE_NTP_CLIENT) + NtpClient ntpClient; + ntpClient.Start(); + ntpClient.Print(); #endif - display.TextStatus(E131MsgConst::PARAMS, Display7SegmentMessage::INFO_BRIDGE_PARMAMS, CONSOLE_YELLOW); - - StoreE131 storeE131; - E131Params e131params(&storeE131); - E131Bridge bridge; - if (e131params.Load()) { - e131params.Dump(); - e131params.Set(DMXPORT_OFFSET); - } + E131Params e131params; + e131params.Load(); + e131params.Set(); for (uint32_t nPortIndex = 0; nPortIndex < e131bridge::MAX_PORTS; nPortIndex++) { bool bIsSet; @@ -124,19 +110,15 @@ void main() { bridge.SetUniverse(nPortIndex, e131params.GetDirection(nPortIndex), nUniverse); } - StoreDmxSend storeDmxSend; - DmxParams dmxparams(&storeDmxSend); - Dmx dmx; - if (dmxparams.Load()) { - dmxparams.Dump(); - dmxparams.Set(&dmx); - } + DmxParams dmxparams; + dmxparams.Load(); + dmxparams.Set(&dmx); - for (uint32_t nPortIndex = DMXPORT_OFFSET; nPortIndex < e131bridge::MAX_PORTS; nPortIndex++) { + for (uint32_t nPortIndex = e131bridge::configstore::DMXPORT_OFFSET; nPortIndex < e131bridge::MAX_PORTS; nPortIndex++) { uint16_t nUniverse; - const auto nDmxPortIndex = nPortIndex - DMXPORT_OFFSET; + const auto nDmxPortIndex = nPortIndex - e131bridge::configstore::DMXPORT_OFFSET; if (bridge.GetUniverse(nPortIndex, nUniverse, lightset::PortDir::OUTPUT)) { dmx.SetPortDirection(nDmxPortIndex, dmx::PortDirection::OUTP, false); @@ -150,12 +132,10 @@ void main() { bridge.SetOutput(&dmxSend); - DmxConfigUdp dmxConfigUdp; - const auto nActivePorts = static_cast(bridge.GetActiveInputPorts() + bridge.GetActiveOutputPorts()); #if defined (NODE_RDMNET_LLRP_ONLY) - display.TextStatus(RDMNetConst::MSG_CONFIG, Display7SegmentMessage::INFO_RDMNET_CONFIG, CONSOLE_YELLOW); + display.TextStatus(RDMNetConst::MSG_CONFIG, CONSOLE_YELLOW); char aDescription[rdm::personality::DESCRIPTION_MAX_LENGTH + 1]; snprintf(aDescription, sizeof(aDescription) - 1, "sACN E1.31 DMX %d", nActivePorts); @@ -170,18 +150,24 @@ void main() { llrpOnlyDevice.SetProductDetail(E120_PRODUCT_DETAIL_ETHERNET_NODE); llrpOnlyDevice.Init(); - StoreRDMDevice storeRdmDevice; - RDMDeviceParams rdmDeviceParams(&storeRdmDevice); + RDMDeviceParams rdmDeviceParams; - if (rdmDeviceParams.Load()) { - rdmDeviceParams.Dump(); - rdmDeviceParams.Set(&llrpOnlyDevice); - } - - llrpOnlyDevice.SetRDMDeviceStore(&storeRdmDevice); + rdmDeviceParams.Load(); + rdmDeviceParams.Set(&llrpOnlyDevice); + llrpOnlyDevice.Print(); #endif +#if defined (NODE_SHOWFILE) + ShowFile showFile; + + ShowFileParams showFileParams; + showFileParams.Load(); + showFileParams.Set(); + + showFile.Print(); +#endif + bridge.Print(); display.SetTitle("sACN E1.31 DMX %u", nActivePorts); @@ -191,34 +177,29 @@ void main() { display.Set(5, displayudf::Labels::UNIVERSE_PORT_B); display.Set(6, displayudf::Labels::BOARDNAME); - StoreDisplayUdf storeDisplayUdf; - DisplayUdfParams displayUdfParams(&storeDisplayUdf); + DisplayUdfParams displayUdfParams; - if(displayUdfParams.Load()) { - displayUdfParams.Dump(); - displayUdfParams.Set(&display); - } + displayUdfParams.Load(); + displayUdfParams.Set(&display); - display.Show(&bridge); + display.Show(); RemoteConfig remoteConfig(remoteconfig::Node::E131, remoteconfig::Output::DMX, nActivePorts); - StoreRemoteConfig storeRemoteConfig; - RemoteConfigParams remoteConfigParams(&storeRemoteConfig); - - if (remoteConfigParams.Load()) { - remoteConfigParams.Dump(); - remoteConfigParams.Set(&remoteConfig); - } + RemoteConfigParams remoteConfigParams; + remoteConfigParams.Load(); + remoteConfigParams.Set(&remoteConfig); while (configStore.Flash()) ; - display.TextStatus(E131MsgConst::START, Display7SegmentMessage::INFO_BRIDGE_START, CONSOLE_YELLOW); + mDns.Print(); + + display.TextStatus(E131MsgConst::START, CONSOLE_YELLOW); bridge.Start(); - display.TextStatus(E131MsgConst::STARTED, Display7SegmentMessage::INFO_BRIDGE_STARTED, CONSOLE_GREEN); + display.TextStatus(E131MsgConst::STARTED, CONSOLE_GREEN); hw.WatchdogInit(); @@ -226,17 +207,17 @@ void main() { hw.WatchdogFeed(); nw.Run(); bridge.Run(); +#if defined (NODE_SHOWFILE) + showFile.Run(); +#endif remoteConfig.Run(); configStore.Flash(); - if (bridge.GetActiveOutputPorts() != 0) { - dmxConfigUdp.Run(); - } mDns.Run(); +#if defined (ENABLE_NTP_CLIENT) + ntpClient.Run(); +#endif #if defined (NODE_RDMNET_LLRP_ONLY) llrpOnlyDevice.Run(); -#endif -#if defined (ENABLE_HTTPD) - httpDaemon.Run(); #endif display.Run(); hw.Run(); diff --git a/gd32_emac_e131_dmx_multi/generate_sofware_version_id.sh b/gd32_emac_e131_dmx_multi/generate_sofware_version_id.sh deleted file mode 100755 index 2f453f59..00000000 --- a/gd32_emac_e131_dmx_multi/generate_sofware_version_id.sh +++ /dev/null @@ -1,4 +0,0 @@ -echo "// Generated "$(date) > ./include/sofware_version_id.h -var="$(date +%s)" -echo "constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID="$var";" >> ./include/sofware_version_id.h - diff --git a/gd32_emac_e131_dmx_multi/include/sofware_version_id.h b/gd32_emac_e131_dmx_multi/include/sofware_version_id.h deleted file mode 100644 index 08e1c733..00000000 --- a/gd32_emac_e131_dmx_multi/include/sofware_version_id.h +++ /dev/null @@ -1,2 +0,0 @@ -// Generated wo 18 okt 2023 15:47:37 CEST -constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID=1697636857; diff --git a/gd32_emac_e131_dmx_multi/lib/factorydefaults.cpp b/gd32_emac_e131_dmx_multi/lib/factorydefaults.cpp index 971fc158..1741e5e2 100644 --- a/gd32_emac_e131_dmx_multi/lib/factorydefaults.cpp +++ b/gd32_emac_e131_dmx_multi/lib/factorydefaults.cpp @@ -28,7 +28,7 @@ #include "remoteconfig.h" #include "configstore.h" -#include "storenetwork.h" +#include "networkstore.h" namespace rdm { namespace device { @@ -37,7 +37,7 @@ namespace responder { void factorydefaults() { RemoteConfig::Get()->SetDisable(false); ConfigStore::Get()->ResetSetList(configstore::Store::RDMDEVICE); - StoreNetwork::Get()->SaveDhcp(true); + NetworkStore::SaveDhcp(true); } } // namespace responder diff --git a/gd32_emac_e131_dmx_multi/lib/rdmsoftwareversion.cpp b/gd32_emac_e131_dmx_multi/lib/rdmsoftwareversion.cpp index 5149f9a1..94271597 100644 --- a/gd32_emac_e131_dmx_multi/lib/rdmsoftwareversion.cpp +++ b/gd32_emac_e131_dmx_multi/lib/rdmsoftwareversion.cpp @@ -29,7 +29,7 @@ #include "rdmsoftwareversion.h" #include "software_version.h" -#include "sofware_version_id.h" +#include "software_version_id.h" const char *RDMSoftwareVersion::GetVersion() { return SOFTWARE_VERSION; diff --git a/gd32_emac_e131_dmx_multi/lib/showfileusb.cpp b/gd32_emac_e131_dmx_multi/lib/showfileusb.cpp new file mode 100644 index 00000000..657929f1 --- /dev/null +++ b/gd32_emac_e131_dmx_multi/lib/showfileusb.cpp @@ -0,0 +1,55 @@ +#if defined (NODE_SHOWFILE) +/** + * @file showfileusb.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "showfile.h" + +#include "debug.h" + +namespace showfile { +void usb_ready() { + DEBUG_ENTRY + + ShowFile::Get()->SetPlayerShowFileCurrent(ShowFile::Get()->GetShowFileCurrent()); + + if (ShowFile::Get()->IsAutoStart()) { + ShowFile::Get()->Play(); + } else { + ShowFile::Get()->LoadShows(); + } + + DEBUG_EXIT +} + +void usb_disconnected() { + DEBUG_ENTRY + + ShowFile::Get()->Stop(); + ShowFile::Get()->UnloadShows(); + + DEBUG_EXIT +} +} // namespace showfile +#endif diff --git a/gd32_emac_e131_pixel_multi/.cproject b/gd32_emac_e131_pixel_multi/.cproject index f0890e8f..37455288 100644 --- a/gd32_emac_e131_pixel_multi/.cproject +++ b/gd32_emac_e131_pixel_multi/.cproject @@ -31,11 +31,9 @@ - - diff --git a/gd32_emac_e131_pixel_multi/Makefile.GD32 b/gd32_emac_e131_pixel_multi/Makefile.GD32 index edd8d64a..f89876c0 100644 --- a/gd32_emac_e131_pixel_multi/Makefile.GD32 +++ b/gd32_emac_e131_pixel_multi/Makefile.GD32 @@ -8,6 +8,8 @@ DEFINES+=OUTPUT_DMX_PIXEL_MULTI PIXELPATTERNS_MULTI DEFINES+=ENET_RXBUF_NUM=34 ENET_TXBUF_NUM=2 DEFINES+=ENABLE_HTTPD ENABLE_CONTENT +DEFINES+=RTL8201F_LED1_LINK_ALL + DEFINES+=DISPLAY_UDF DEFINES+=DISABLE_RTC @@ -26,5 +28,6 @@ SRCDIR=firmware lib include ../firmware-template-gd32/Rules.mk prerequisites: - ./generate_sofware_version_id.sh + @echo "constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID="$(shell date "+%s")";" > ./include/software_version_id.h + diff --git a/gd32_emac_e131_pixel_multi/firmware/main.cpp b/gd32_emac_e131_pixel_multi/firmware/main.cpp index ddc3689e..85fb1814 100644 --- a/gd32_emac_e131_pixel_multi/firmware/main.cpp +++ b/gd32_emac_e131_pixel_multi/firmware/main.cpp @@ -2,7 +2,7 @@ * @file main.cpp * */ -/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,16 +29,19 @@ #include "network.h" #include "networkconst.h" -#include "mdns.h" +#include "net/apps/mdns.h" -#if defined (ENABLE_HTTPD) -# include "httpd/httpd.h" +#if defined (ENABLE_NTP_CLIENT) +# include "net/apps/ntpclient.h" +#endif + +#if defined (ENABLE_SHELL) +# include "shell/shell.h" #endif #include "displayudf.h" #include "displayudfparams.h" #include "displayhandler.h" -#include "display_timeout.h" #include "e131.h" #include "e131bridge.h" @@ -49,7 +52,7 @@ #include "pixeltype.h" #include "pixeltestpattern.h" #include "pixeldmxparams.h" -#include "pixeldmxstartstop.h" + #include "ws28xxmulti.h" #include "ws28xxdmxmulti.h" @@ -61,82 +64,65 @@ # include "rdm_e120.h" #endif +#if defined (NODE_SHOWFILE) +# include "showfile.h" +# include "showfileparams.h" +#endif + #include "remoteconfig.h" #include "remoteconfigparams.h" #include "configstore.h" -#include "storedisplayudf.h" -#include "storee131.h" -#include "storenetwork.h" -#if defined (NODE_RDMNET_LLRP_ONLY) -# include "storerdmdevice.h" -#endif -#include "storeremoteconfig.h" -#include "storepixeldmx.h" + #include "firmwareversion.h" #include "software_version.h" -static constexpr uint32_t DMXPORT_OFFSET = 32; +namespace e131bridge { +namespace configstore { +uint32_t DMXPORT_OFFSET = LIGHTSET_PORTS; +} // namespace configstore +} // namespace e131bridge void Hardware::RebootHandler() { WS28xxMulti::Get()->Blackout(); E131Bridge::Get()->Stop(); } -void main() { +int main() { Hardware hw; DisplayUdf display; ConfigStore configStore; - display.TextStatus(NetworkConst::MSG_NETWORK_INIT, Display7SegmentMessage::INFO_NETWORK_INIT, CONSOLE_YELLOW); - StoreNetwork storeNetwork; - Network nw(&storeNetwork); - display.TextStatus(NetworkConst::MSG_NETWORK_STARTED, Display7SegmentMessage::INFO_NONE, CONSOLE_GREEN); + display.TextStatus(NetworkConst::MSG_NETWORK_INIT, CONSOLE_YELLOW); + Network nw; + MDNS mDns; + display.TextStatus(NetworkConst::MSG_NETWORK_STARTED, CONSOLE_GREEN); FirmwareVersion fw(SOFTWARE_VERSION, __DATE__, __TIME__); - fw.Print("sACN E1.31 Pixel controller {8x 4 Universes}"); - nw.Print(); + fw.Print("sACN E1.31 Pixel controller"); - display.TextStatus(NetworkConst::MSG_MDNS_CONFIG, Display7SegmentMessage::INFO_MDNS_CONFIG, CONSOLE_YELLOW); - - MDNS mDns; - mDns.AddServiceRecord(nullptr, mdns::Services::CONFIG, "node=sACN E1.31 Pixel"); -#if defined (ENABLE_HTTPD) - mDns.AddServiceRecord(nullptr, mdns::Services::HTTP); -#endif - mDns.Print(); - -#if defined (ENABLE_HTTPD) - HttpDaemon httpDaemon; +#if defined (ENABLE_NTP_CLIENT) + NtpClient ntpClient; + ntpClient.Start(); + ntpClient.Print(); #endif - display.TextStatus(E131MsgConst::PARAMS, Display7SegmentMessage::INFO_BRIDGE_PARMAMS, CONSOLE_YELLOW); - - StoreE131 storeE131; - E131Params e131params(&storeE131); - E131Bridge bridge; - if (e131params.Load()) { - e131params.Dump(); - e131params.Set(DMXPORT_OFFSET); - } + E131Params e131params; + e131params.Load(); + e131params.Set(); PixelDmxConfiguration pixelDmxConfiguration; - StorePixelDmx storePixelDmx; - PixelDmxParams pixelDmxParams(&storePixelDmx); - - if (pixelDmxParams.Load()) { - pixelDmxParams.Dump(); - pixelDmxParams.Set(&pixelDmxConfiguration); - } + PixelDmxParams pixelDmxParams; + pixelDmxParams.Load(); + pixelDmxParams.Set(); - WS28xxDmxMulti pixelDmxMulti(pixelDmxConfiguration); - pixelDmxMulti.SetPixelDmxHandler(new PixelDmxStartStop); + WS28xxDmxMulti pixelDmxMulti; - const auto nUniverses = pixelDmxMulti.GetUniverses(); - const auto nActivePorts = pixelDmxMulti.GetOutputPorts(); + const auto nUniverses = pixelDmxConfiguration.GetUniverses(); + const auto nActivePorts = pixelDmxConfiguration.GetOutputPorts(); uint32_t nPortProtocolIndex = 0; @@ -163,9 +149,9 @@ void main() { } #if defined (NODE_RDMNET_LLRP_ONLY) - display.TextStatus(RDMNetConst::MSG_CONFIG, Display7SegmentMessage::INFO_RDMNET_CONFIG, CONSOLE_YELLOW); + display.TextStatus(RDMNetConst::MSG_CONFIG, CONSOLE_YELLOW); char aDescription[rdm::personality::DESCRIPTION_MAX_LENGTH + 1]; - snprintf(aDescription, sizeof(aDescription) - 1, "sACN Pixel %d-%s:%d", nActivePorts, PixelType::GetType(WS28xxMulti::Get()->GetType()), WS28xxMulti::Get()->GetCount()); + snprintf(aDescription, sizeof(aDescription) - 1, "sACN Pixel %d-%s:%d", nActivePorts, pixel::pixel_get_type(pixelDmxConfiguration.GetType()), pixelDmxConfiguration.GetCount()); char aLabel[RDM_DEVICE_LABEL_MAX_LENGTH + 1]; const auto nLength = snprintf(aLabel, sizeof(aLabel) - 1, GD32_BOARD_NAME " Pixel"); @@ -178,42 +164,44 @@ void main() { llrpOnlyDevice.SetProductDetail(E120_PRODUCT_DETAIL_LED); llrpOnlyDevice.Init(); - StoreRDMDevice storeRdmDevice; - RDMDeviceParams rdmDeviceParams(&storeRdmDevice); - - if (rdmDeviceParams.Load()) { - rdmDeviceParams.Dump(); - rdmDeviceParams.Set(&llrpOnlyDevice); - } + RDMDeviceParams rdmDeviceParams; - llrpOnlyDevice.SetRDMDeviceStore(&storeRdmDevice); + rdmDeviceParams.Load(); + rdmDeviceParams.Set(&llrpOnlyDevice); + llrpOnlyDevice.Print(); #endif +#if defined (NODE_SHOWFILE) + ShowFile showFile; + + ShowFileParams showFileParams; + showFileParams.Load(); + showFileParams.Set(); + + showFile.Print(); +#endif + bridge.Print(); pixelDmxMulti.Print(); - display.SetTitle("sACN Pixel 8:%dx%d", nActivePorts, WS28xxMulti::Get()->GetCount()); + display.SetTitle("sACN Pixel 8:%dx%d", nActivePorts, pixelDmxConfiguration.GetCount()); display.Set(2, displayudf::Labels::IP); display.Set(3, displayudf::Labels::HOSTNAME); display.Set(4, displayudf::Labels::VERSION); - display.Set(5, displayudf::Labels::UNIVERSE_PORT_A); - display.Set(6, displayudf::Labels::BOARDNAME); + display.Set(5, displayudf::Labels::BOARDNAME); - StoreDisplayUdf storeDisplayUdf; - DisplayUdfParams displayUdfParams(&storeDisplayUdf); + DisplayUdfParams displayUdfParams; - if (displayUdfParams.Load()) { - displayUdfParams.Dump(); - displayUdfParams.Set(&display); - } + displayUdfParams.Load(); + displayUdfParams.Set(&display); - display.Show(&bridge); + display.Show(); display.Printf(7, "%s:%d G%d %s", - PixelType::GetType(pixelDmxConfiguration.GetType()), + pixel::pixel_get_type(pixelDmxConfiguration.GetType()), pixelDmxConfiguration.GetCount(), pixelDmxConfiguration.GetGroupingCount(), - PixelType::GetMap(pixelDmxConfiguration.GetMap())); + pixel::pixel_get_map(pixelDmxConfiguration.GetMap())); if (nTestPattern != pixelpatterns::Pattern::NONE) { display.ClearLine(6); @@ -222,22 +210,24 @@ void main() { RemoteConfig remoteConfig(remoteconfig::Node::E131, remoteconfig::Output::PIXEL, bridge.GetActiveOutputPorts()); - StoreRemoteConfig storeRemoteConfig; - RemoteConfigParams remoteConfigParams(&storeRemoteConfig); - - if (remoteConfigParams.Load()) { - remoteConfigParams.Dump(); - remoteConfigParams.Set(&remoteConfig); - } + RemoteConfigParams remoteConfigParams; + remoteConfigParams.Load(); + remoteConfigParams.Set(&remoteConfig); while (configStore.Flash()) ; - display.TextStatus(E131MsgConst::START, Display7SegmentMessage::INFO_BRIDGE_START, CONSOLE_YELLOW); + mDns.Print(); + +#if defined (ENABLE_SHELL) + Shell shell; +#endif + + display.TextStatus(E131MsgConst::START, CONSOLE_YELLOW); bridge.Start(); - display.TextStatus(E131MsgConst::STARTED, Display7SegmentMessage::INFO_BRIDGE_STARTED, CONSOLE_GREEN); + display.TextStatus(E131MsgConst::STARTED, CONSOLE_GREEN); hw.WatchdogInit(); @@ -245,19 +235,25 @@ void main() { hw.WatchdogFeed(); nw.Run(); bridge.Run(); +#if defined (NODE_SHOWFILE) + showFile.Run(); +#endif remoteConfig.Run(); configStore.Flash(); if (__builtin_expect((pPixelTestPattern != nullptr), 0)) { pPixelTestPattern->Run(); } mDns.Run(); +#if defined (ENABLE_NTP_CLIENT) + ntpClient.Run(); +#endif #if defined (NODE_RDMNET_LLRP_ONLY) llrpOnlyDevice.Run(); -#endif -#if defined (ENABLE_HTTPD) - httpDaemon.Run(); #endif display.Run(); hw.Run(); +#if defined (ENABLE_SHELL) + shell.Run(); +#endif } } diff --git a/gd32_emac_e131_pixel_multi/generate_sofware_version_id.sh b/gd32_emac_e131_pixel_multi/generate_sofware_version_id.sh deleted file mode 100755 index 2f453f59..00000000 --- a/gd32_emac_e131_pixel_multi/generate_sofware_version_id.sh +++ /dev/null @@ -1,4 +0,0 @@ -echo "// Generated "$(date) > ./include/sofware_version_id.h -var="$(date +%s)" -echo "constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID="$var";" >> ./include/sofware_version_id.h - diff --git a/gd32_emac_e131_pixel_multi/include/display_timeout.h b/gd32_emac_e131_pixel_multi/include/display_timeout.h deleted file mode 100644 index a8556629..00000000 --- a/gd32_emac_e131_pixel_multi/include/display_timeout.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - * @file display_timeout.h - * - */ -/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@gd32-dmx.org - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef DISPLAY_TIMEOUT_H_ -#define DISPLAY_TIMEOUT_H_ - -#include "gd32.h" - -namespace display { -namespace timeout { - -void gpio_init() { - gpio_fsel(KEY2_GPIOx, KEY2_PINx, GPIO_FSEL_INPUT); -} - -bool gpio_renew() { - return (GPIO_ISTAT(KEY2_GPIOx) & KEY2_PINx) == 0; -} - -} // namespace timeout -} // namespace display - -#endif /* DISPLAY_TIMEOUT_H_ */ diff --git a/gd32_emac_e131_pixel_multi/include/sofware_version_id.h b/gd32_emac_e131_pixel_multi/include/sofware_version_id.h deleted file mode 100644 index 8aeaced5..00000000 --- a/gd32_emac_e131_pixel_multi/include/sofware_version_id.h +++ /dev/null @@ -1,2 +0,0 @@ -// Generated wo 18 okt 2023 15:47:45 CEST -constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID=1697636865; diff --git a/gd32_emac_e131_pixel_multi/lib/factorydefaults.cpp b/gd32_emac_e131_pixel_multi/lib/factorydefaults.cpp index 971fc158..1741e5e2 100644 --- a/gd32_emac_e131_pixel_multi/lib/factorydefaults.cpp +++ b/gd32_emac_e131_pixel_multi/lib/factorydefaults.cpp @@ -28,7 +28,7 @@ #include "remoteconfig.h" #include "configstore.h" -#include "storenetwork.h" +#include "networkstore.h" namespace rdm { namespace device { @@ -37,7 +37,7 @@ namespace responder { void factorydefaults() { RemoteConfig::Get()->SetDisable(false); ConfigStore::Get()->ResetSetList(configstore::Store::RDMDEVICE); - StoreNetwork::Get()->SaveDhcp(true); + NetworkStore::SaveDhcp(true); } } // namespace responder diff --git a/gd32_emac_e131_pixel_multi/lib/rdmsoftwareversion.cpp b/gd32_emac_e131_pixel_multi/lib/rdmsoftwareversion.cpp index 5149f9a1..94271597 100644 --- a/gd32_emac_e131_pixel_multi/lib/rdmsoftwareversion.cpp +++ b/gd32_emac_e131_pixel_multi/lib/rdmsoftwareversion.cpp @@ -29,7 +29,7 @@ #include "rdmsoftwareversion.h" #include "software_version.h" -#include "sofware_version_id.h" +#include "software_version_id.h" const char *RDMSoftwareVersion::GetVersion() { return SOFTWARE_VERSION; diff --git a/gd32_emac_e131_pixel_multi/lib/showfileusb.cpp b/gd32_emac_e131_pixel_multi/lib/showfileusb.cpp new file mode 100644 index 00000000..657929f1 --- /dev/null +++ b/gd32_emac_e131_pixel_multi/lib/showfileusb.cpp @@ -0,0 +1,55 @@ +#if defined (NODE_SHOWFILE) +/** + * @file showfileusb.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "showfile.h" + +#include "debug.h" + +namespace showfile { +void usb_ready() { + DEBUG_ENTRY + + ShowFile::Get()->SetPlayerShowFileCurrent(ShowFile::Get()->GetShowFileCurrent()); + + if (ShowFile::Get()->IsAutoStart()) { + ShowFile::Get()->Play(); + } else { + ShowFile::Get()->LoadShows(); + } + + DEBUG_EXIT +} + +void usb_disconnected() { + DEBUG_ENTRY + + ShowFile::Get()->Stop(); + ShowFile::Get()->UnloadShows(); + + DEBUG_EXIT +} +} // namespace showfile +#endif diff --git a/gd32_emac_llrp/.cproject b/gd32_emac_llrp/.cproject new file mode 100644 index 00000000..20833c75 --- /dev/null +++ b/gd32_emac_llrp/.cproject @@ -0,0 +1,132 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/gd32_rdm_responder/.project b/gd32_emac_llrp/.project similarity index 84% rename from gd32_rdm_responder/.project rename to gd32_emac_llrp/.project index 6bb46e37..b8bfa912 100644 --- a/gd32_rdm_responder/.project +++ b/gd32_emac_llrp/.project @@ -1,27 +1,32 @@ - - - gd32_rdm_responder - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - + + + gd32_emac_llrp + + + + + + org.python.pydev.PyDevBuilder + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/gd32_emac_llrp/.pydevproject b/gd32_emac_llrp/.pydevproject new file mode 100644 index 00000000..2b045655 --- /dev/null +++ b/gd32_emac_llrp/.pydevproject @@ -0,0 +1,5 @@ + + + Default + python interpreter + diff --git a/gd32_rdm_responder/.settings/language.settings.xml b/gd32_emac_llrp/.settings/language.settings.xml similarity index 89% rename from gd32_rdm_responder/.settings/language.settings.xml rename to gd32_emac_llrp/.settings/language.settings.xml index d0a369db..e562b391 100644 --- a/gd32_rdm_responder/.settings/language.settings.xml +++ b/gd32_emac_llrp/.settings/language.settings.xml @@ -1,6 +1,6 @@ - + diff --git a/lib-c++/.settings/org.eclipse.core.resources.prefs b/gd32_emac_llrp/.settings/org.eclipse.core.resources.prefs similarity index 100% rename from lib-c++/.settings/org.eclipse.core.resources.prefs rename to gd32_emac_llrp/.settings/org.eclipse.core.resources.prefs diff --git a/gd32_emac_llrp/Makefile.GD32 b/gd32_emac_llrp/Makefile.GD32 new file mode 100644 index 00000000..2867c983 --- /dev/null +++ b/gd32_emac_llrp/Makefile.GD32 @@ -0,0 +1,33 @@ +BOARD=BOARD_GD32F207RG +ENET_PHY=RTL8201F + +DEFINES =NODE_RDMNET_LLRP_ONLY + +DEFINES+=DISPLAY_UDF +DEFINES+=ENABLE_SSD1311 + +DEFINES+=ENABLE_HTTPD ENABLE_CONTENT + +DEFINES+=ENABLE_NTP_CLIENT + +DEFINES+=ENET_LINK_CHECK_REG_POLL +DEFINES+=RTL8201F_LED1_LINK_ALL + +DEFINES+=DISABLE_FS + +DEFINES+=DEBUG_ + +DEFINES+=DEBUG_NTP_CLIENT +DEFINES+=DEBUG_I2C +DEFINES+=DEBUG_STACK + +#DEFINES+=NDEBUG + +LIBS= + +SRCDIR=firmware lib + +include ../firmware-template-gd32/Rules.mk +prerequisites: + @echo "constexpr uint32_t DEVICE_SOFTWARE_VERSION_ID="$(shell date "+%s")";" > ./include/software_version_id.h + diff --git a/gd32_emac_llrp/firmware/main.cpp b/gd32_emac_llrp/firmware/main.cpp new file mode 100644 index 00000000..b246f0b7 --- /dev/null +++ b/gd32_emac_llrp/firmware/main.cpp @@ -0,0 +1,151 @@ +/** + * @file main.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#if !defined (NODE_RDMNET_LLRP_ONLY) +# error +#endif + +#include +#include +#include + +#include "hardware.h" +#include "network.h" +#include "networkconst.h" + +#include "net/apps/mdns.h" + +#if defined (ENABLE_NTP_CLIENT) +# include "net/apps/ntpclient.h" +#endif + +#include "displayudf.h" +#include "displayudfparams.h" + +#include "configstore.h" + +#include "remoteconfig.h" +#include "remoteconfigparams.h" + +#include "rdmnetllrponly.h" +#include "factorydefaults.h" + +#include "firmwareversion.h" +#include "software_version.h" + +#include "debug.h" + +void Hardware::RebootHandler() { + HwClock::Get()->SysToHc(); +} + +int main() { + Hardware hw; + DisplayUdf display; + ConfigStore configStore; + display.TextStatus(NetworkConst::MSG_NETWORK_INIT, CONSOLE_YELLOW); + Network nw; + MDNS mDns; + display.TextStatus(NetworkConst::MSG_NETWORK_STARTED, CONSOLE_GREEN); + FirmwareVersion fw(SOFTWARE_VERSION, __DATE__, __TIME__); + + fw.Print("RDMNet LLRP device only"); + + +#if defined (ENABLE_NTP_CLIENT) + NtpClient ntpClient; + ntpClient.Start(); + ntpClient.Print(); +#endif + + RDMNetLLRPOnly device; + device.Init(); + device.Print(); + + RemoteConfig remoteConfig(remoteconfig::Node::RDMNET_LLRP_ONLY, remoteconfig::Output::CONFIG, 0); + + RemoteConfigParams remoteConfigParams; + remoteConfigParams.Load(); + remoteConfigParams.Set(&remoteConfig); + + while (configStore.Flash()) + ; + + mDns.Print(); + + display.SetTitle("LLRP Only - TFTP"); + display.Set(2, displayudf::Labels::HOSTNAME); + display.Set(3, displayudf::Labels::IP); + display.Set(4, displayudf::Labels::DEFAULT_GATEWAY); + display.Set(5, displayudf::Labels::VERSION); + + DisplayUdfParams displayUdfParams; + displayUdfParams.Load(); + displayUdfParams.Set(&display); + + display.Show(); + display.Write(6, "mDNS enabled"); + display.TextStatus("Device running", CONSOLE_GREEN); + + hw.SetMode(hardware::ledblink::Mode::NORMAL); + + hw.WatchdogInit(); + + auto nTime1 = time(nullptr); + + for (;;) { + hw.WatchdogFeed(); + nw.Run(); + mDns.Run(); + device.Run(); + remoteConfig.Run(); +#if defined (ENABLE_NTP_CLIENT) + ntpClient.Run(); +#endif + configStore.Flash(); + display.Run(); + hw.Run(); + + const auto nTime2 = time(nullptr); + + if (nTime1 != nTime2) { + nTime1 = nTime2; + + auto *tm = localtime(&nTime2); + struct tm tmlocal; + memcpy(&tmlocal, tm, sizeof(struct tm)); + + struct tm tmHwClock; + HwClock::Get()->Get(&tmHwClock); + + display.Printf(7, "%.2d:%.2d:%.2d %.2d:%.2d:%.2d", + tmlocal.tm_hour, tmlocal.tm_min, tmlocal.tm_sec, + tmHwClock.tm_hour, tmHwClock.tm_min, tmHwClock.tm_sec); + printf("%.2d:%.2d:%.2d %.2d:%.2d:%.2d\n", + tmlocal.tm_hour, tmlocal.tm_min, tmlocal.tm_sec, + tmHwClock.tm_hour, tmHwClock.tm_min, tmHwClock.tm_sec); + } + } +} diff --git a/gd32_rdm_responder/lib/factorydefaults.cpp b/gd32_emac_llrp/include/factorydefaults.h similarity index 86% rename from gd32_rdm_responder/lib/factorydefaults.cpp rename to gd32_emac_llrp/include/factorydefaults.h index 5d72733b..9d9111a3 100644 --- a/gd32_rdm_responder/lib/factorydefaults.cpp +++ b/gd32_emac_llrp/include/factorydefaults.h @@ -1,8 +1,8 @@ /** - * @file factorydefaults.cpp + * @file factorydefaults.h * */ -/* Copyright (C) 2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,14 +26,18 @@ #ifndef FACTORYDEFAULTS_H_ #define FACTORYDEFAULTS_H_ +#include "remoteconfig.h" #include "configstore.h" +#include "networkstore.h" namespace rdm { namespace device { namespace responder { void factorydefaults() { + RemoteConfig::Get()->SetDisable(false); ConfigStore::Get()->ResetSetList(configstore::Store::RDMDEVICE); + NetworkStore::SaveDhcp(true); } } // namespace responder diff --git a/gd32_rdm_responder/lib/rdmsoftwareversion.cpp b/gd32_emac_llrp/lib/rdmsoftwareversion.cpp similarity index 96% rename from gd32_rdm_responder/lib/rdmsoftwareversion.cpp rename to gd32_emac_llrp/lib/rdmsoftwareversion.cpp index 2e5b2a03..82d38bc4 100644 --- a/gd32_rdm_responder/lib/rdmsoftwareversion.cpp +++ b/gd32_emac_llrp/lib/rdmsoftwareversion.cpp @@ -23,12 +23,12 @@ * THE SOFTWARE. */ -#include +#include #include "rdmsoftwareversion.h" #include "software_version.h" -#include "sofware_version_id.h" +#include "software_version_id.h" const char *RDMSoftwareVersion::GetVersion() { return SOFTWARE_VERSION; diff --git a/gd32_emac_pp_pixel_multi/.cproject b/gd32_emac_pp_pixel_multi/.cproject index 80b61de7..7fd357a0 100755 --- a/gd32_emac_pp_pixel_multi/.cproject +++ b/gd32_emac_pp_pixel_multi/.cproject @@ -31,14 +31,12 @@ - @@ -54,19 +56,21 @@ - + + @@ -87,9 +91,10 @@ - + + diff --git a/lib-artnet/Rules.mk b/lib-artnet/Rules.mk old mode 100644 new mode 100755 index e9d9ac2d..03b0003c --- a/lib-artnet/Rules.mk +++ b/lib-artnet/Rules.mk @@ -1,3 +1,5 @@ +EXTRA_INCLUDES+=../lib-lightset/include ../lib-properties/include ../lib-network/include + ifneq ($(MAKE_FLAGS),) ifeq ($(findstring NODE_ARTNET,$(MAKE_FLAGS)), NODE_ARTNET) EXTRA_SRCDIR+=src/node @@ -7,14 +9,17 @@ ifneq ($(MAKE_FLAGS),) EXTRA_SRCDIR+=src/node/dmxin EXTRA_INCLUDES+=../lib-dmx/include endif + ifeq ($(findstring RDM_CONTROLLER,$(MAKE_FLAGS)), RDM_CONTROLLER) EXTRA_SRCDIR+=src/node/rdm + EXTRA_SRCDIR+=src/node/rdm/controller + EXTRA_INCLUDES+=../lib-rdm/include ../lib-dmx/include endif + ifeq ($(findstring RDM_RESPONDER,$(MAKE_FLAGS)), RDM_RESPONDER) EXTRA_SRCDIR+=src/node/rdm - endif - ifeq ($(findstring ARTNET_HAVE_TIMECODE,$(MAKE_FLAGS)), ARTNET_HAVE_TIMECODE) - EXTRA_SRCDIR+=src/node/timecode + EXTRA_SRCDIR+=src/node/rdm/responder + EXTRA_INCLUDES+=../lib-rdm/include endif ifeq ($(findstring ARTNET_CONTROLLER,$(MAKE_FLAGS)), ARTNET_CONTROLLER) @@ -34,13 +39,21 @@ ifneq ($(MAKE_FLAGS),) EXTRA_SRCDIR+=src/node/4 EXTRA_INCLUDES+=../lib-e131/include endif + + ifeq ($(findstring OUTPUT_DMX_SEND,$(MAKE_FLAGS)), OUTPUT_DMX_SEND) + EXTRA_INCLUDES+=../lib-dmx/include + endif + + ifneq (,$(findstring CONFIG_STORE_USE_ROM,$(MAKE_FLAGS))) + EXTRA_INCLUDES+=../lib-flashcode/include + endif else - EXTRA_SRCDIR+=src/node src/node/failsafe src/node/dmxin src/node/rdm src/node/timecode - EXTRA_SRCDIR+=src/controller + EXTRA_SRCDIR+=src/node src/node/failsafe src/node/dmxin src/node/rdm src/node/rdm/controller src/node/timecode EXTRA_SRCDIR+=src/node/4 EXTRA_INCLUDES+=src/node/failsafe EXTRA_INCLUDES+=../lib-e131/include EXTRA_INCLUDES+=../lib-dmx/include + EXTRA_INCLUDES+=../lib-rdm/include DEFINES+=ARTNET_HAVE_TIMECODE DEFINES+=ARTNET_HAVE_FAILSAFE_RECORD DEFINES+=ARTNET_HAVE_DMXIN E131_HAVE_DMXIN @@ -50,4 +63,6 @@ else DEFINES+=RDM_CONTROLLER DEFINES+=ARTNET_VERSION=4 DEFINES+=LIGHTSET_PORTS=1 + DEFINES+=NODE_SHOWFILE + DEFINES+=CONFIG_SHOWFILE_PROTOCOL_NODE_ARTNET endif \ No newline at end of file diff --git a/lib-artnet/include/artnet.h b/lib-artnet/include/artnet.h index 0157144d..4e17fb1a 100644 --- a/lib-artnet/include/artnet.h +++ b/lib-artnet/include/artnet.h @@ -5,7 +5,7 @@ /** * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. */ -/* Copyright (C) 2016-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2016-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -62,6 +62,34 @@ enum class PortProtocol { SACN ///< Output DMX512 data from the sACN protocol and RDM data from the Art-Net protocol. }; +/** + * Table 3 – NodeReport Codes + * The NodeReport code defines generic error, advisory and status messages for both Nodes and Controllers. + * The NodeReport is returned in ArtPollReply. + */ +enum class ReportCode : uint8_t { + RCDEBUG, + RCPOWEROK, + RCPOWERFAIL, + RCSOCKETWR1, + RCPARSEFAIL, + RCUDPFAIL, + RCSHNAMEOK, + RCLONAMEOK, + RCDMXERROR, + RCDMXUDPFULL, + RCDMXRXFULL, + RCSWITCHERR, + RCCONFIGERR, + RCDMXSHORT, + RCFIRMWAREFAIL, + RCUSERFAIL +}; + +enum class Status : uint8_t { + OFF, STANDBY, ON +}; + /** * Table 4 – Style Codes * The Style code defines the general functionality of a Controller. @@ -171,6 +199,14 @@ struct PortCommand { static constexpr uint8_t RDM_DISABLE3 = 0xd3; ///< Disable RDM on output port 3 }; +struct TodControlCommand { + static constexpr uint8_t ATC_NONE = 0x00; ///< No action. + static constexpr uint8_t ATC_FLUSH = 0x01; ///< The port flushes its TOD and instigates full discovery. + static constexpr uint8_t ATC_END = 0x02; ///< The port ends current discovery but does not flush ToD. + static constexpr uint8_t ATC_INCON = 0x03; ///< The port enables incremental discovery. + static constexpr uint8_t ATC_INCOFF = 0x04; ///< The port disables incremental discovery. +}; + struct Program { static constexpr uint8_t NO_CHANGE = 0x7F; static constexpr uint8_t DEFAULTS = 0x00; @@ -211,16 +247,19 @@ struct Status2 { }; struct Status3 { - static constexpr uint8_t NETWORKLOSS_MASK = (3U << 6); ///< bit 76 - static constexpr uint8_t NETWORKLOSS_LAST_STATE = (0 << 6); ///< bit 76 = 00 If network data is lost, it will hold last state - static constexpr uint8_t NETWORKLOSS_OFF_STATE = (1U << 6); ///< bit 76 = 01 If network data is lost, it will set all outputs to off state - static constexpr uint8_t NETWORKLOSS_ON_STATE = (2U << 6); ///< bit 76 = 10 If network data is lost, it will set all outputs to full on - static constexpr uint8_t NETWORKLOSS_PLAYBACK = (3U << 6); ///< bit 76 = 11 If network data is lost, it will playback the fail-over scene - static constexpr uint8_t FAILSAFE_NO_CONTROL = (0 << 5); ///< bit 5 = 0 Node is not able to control failsafe mode by ArtCommand - static constexpr uint8_t FAILSAFE_CONTROL = (1U << 5); ///< bit 5 = 1 Node is able to control failsafe mode by ArtCommand - static constexpr uint8_t SUPPORTS_LLRP = (1U << 4); ///< bit 4 = 1 Node supports LLRP (Low Level Recovery Protocol - static constexpr uint8_t OUTPUT_NO_SWITCH = (0 << 3); ///< bit 3 = 0 Outputs cannot be switched to an input - static constexpr uint8_t OUTPUT_SWITCH = (1U << 3); ///< bit 3 = 1 Outputs can be switched to an input + static constexpr uint8_t NETWORKLOSS_MASK = (3U << 6); ///< bit 76 + static constexpr uint8_t NETWORKLOSS_LAST_STATE = (0 << 6); ///< bit 76 = 00 If network data is lost, it will hold last state + static constexpr uint8_t NETWORKLOSS_OFF_STATE = (1U << 6); ///< bit 76 = 01 If network data is lost, it will set all outputs to off state + static constexpr uint8_t NETWORKLOSS_ON_STATE = (2U << 6); ///< bit 76 = 10 If network data is lost, it will set all outputs to full on + static constexpr uint8_t NETWORKLOSS_PLAYBACK = (3U << 6); ///< bit 76 = 11 If network data is lost, it will playback the fail-over scene + static constexpr uint8_t FAILSAFE_NO_CONTROL = (0 << 5); ///< bit 5 = 0 Node is not able to control failsafe mode by ArtCommand + static constexpr uint8_t FAILSAFE_CONTROL = (1U << 5); ///< bit 5 = 1 Node is able to control failsafe mode by ArtCommand + static constexpr uint8_t SUPPORTS_LLRP = (1U << 4); ///< bit 4 = 1 Node supports LLRP (Low Level Recovery Protocol + static constexpr uint8_t OUTPUT_NO_SWITCH = (0 << 3); ///< bit 3 = 0 Outputs cannot be switched to an input + static constexpr uint8_t OUTPUT_SWITCH = (1U << 3); ///< bit 3 = 1 Outputs can be switched to an input + static constexpr uint8_t SUPPORTS_RDMNET = (1U << 2); ///< bit 2 = 1 Node supports RDMnet + static constexpr uint8_t SUPPORTS_BACKGROUNDQUEUE = (1U << 1); ///< bit 1 = 1 BackgroundQueue is supported + static constexpr uint8_t SUPPORTS_BACKGROUNDDISCOVERY = (1U << 0); ///< bit 0 = 1 Programmable background discovery is supported. }; struct Flags { @@ -253,6 +292,10 @@ struct GoodOutputB { static constexpr uint8_t RDM_ENABLED = (0 << 7); ///< bit 7 = 0 RDM is enabled. static constexpr uint8_t STYLE_CONSTANT = (1U << 6); ///< bit 6 = 1 Output style is continuous. static constexpr uint8_t STYLE_DELTA = (0 << 6); ///< bit 6 = 0 Output style is delta. + static constexpr uint8_t DISCOVERY_NOT_RUNNING = (1U << 5); ///< bit 5 = 1 Discovery is currently not running. + static constexpr uint8_t DISCOVERY_IS_RUNNING = (0 << 5); ///< bit 5 = 0 Discovery is currently running. + static constexpr uint8_t DISCOVERY_DISABLED = (1U << 4); ///< bit 4 = 1 Background discovery is disabled. + static constexpr uint8_t DISCOVERY_ENABLED = (0 << 4); ///< bit 4 = 0 Background Discovery is enabled. }; struct GoodInput { @@ -312,6 +355,7 @@ enum class OpCodes: uint16_t { OP_TODDATA = 0x8100, ///< This is an ArtTodData packet. It is used to send a Table of Devices (ToD) for RDM discovery. OP_TODCONTROL = 0x8200, ///< This is an ArtTodControl packet. It is used to send RDM discovery control messages OP_RDM = 0x8300, ///< This is an ArtRdm packet. It is used to send all non discovery RDM messages. + OP_RDMSUB = 0x8400, ///< This is an ArtRdmSub packet. It is used to send compressed, RDM Sub-Device data. OP_TIMECODE = 0x9700, ///< This is an ArtTimeCode packet. It is used to transport time code over the network. OP_TIMESYNC = 0x9800, ///< Used to synchronize real time date and clock OP_TRIGGER = 0x9900, ///< Used to send trigger macros @@ -372,7 +416,15 @@ struct ArtPollReply { uint8_t GoodOutputB[artnet::PORTS]; ///< This array defines output status of the node. uint8_t Status3; ///< General Status register uint8_t DefaultUidResponder[6]; ///< RDMnet & LLRP UID - uint8_t Filler[15]; ///< Transmit as zero. For future expansion. + uint8_t UserHi; ///< Available for user specific data + uint8_t UserLo; ///< Available for user specific data + uint8_t RefreshRateHi; ///< Hi byte of RefreshRate + uint8_t RefreshRateLo; ///< Lo Byte of RefreshRate. + ///< RefreshRate allows the device to specify the maximum refresh rate, expressed in Hz, at which it can process ArtDmx. + ///< This is designed to allow refresh rates above DMX512 rates, for gateways that implement other protocols such as SPI. + ///< A value of 0 to 44 represents the maximum DMX512 rate of 44Hz. + uint8_t BackgroundQueuePolicy; ///< The BackgroundQueuePolicy defines the method by with the node retrieves STATUS_MESSAGE and QUEUED_MESSAGE pids from the connected RDM devices. + uint8_t Filler[10]; ///< Transmit as zero. For future expansion. }PACKED; /** @@ -592,7 +644,30 @@ struct ArtRdm { uint8_t Net; ///< The top 7 bits of the 15 bit Port-Address of Nodes that must respond to this packet. uint8_t Command; ///< 0x00 ArProcess Process RDM Packet0x00 AtcNone No action. 0x01 AtcFlush The node flushes its TOD and instigates full discovery. uint8_t Address; ///< The low 8 bits of the Port-Address that should action this command. - uint8_t RdmPacket[255]; ///< The RDM data packet excluding the DMX StartCode. + uint8_t RdmPacket[256]; ///< The RDM data packet excluding the DMX StartCode with Checksum +}PACKED; + +/** + * The ArtRdmSub packet is used to transfer Get, Set, GetResponse and SetResponse data to and from multiple sub-devices within an RDM device. + */ +struct ArtRdmSub { + uint8_t Id[8]; ///< Array of 8 characters, the final character is a null termination. Value = ‘A’ ‘r’ ‘t’ ‘-‘ ‘N’ ‘e’ ‘t’ 0x00 + uint16_t OpCode; ///< OpAddress \ref TOpCodes + uint8_t ProtVerHi; ///< High byte of the Art-Net protocol revision number. + uint8_t ProtVerLo; ///< Low byte of the Art-Net protocol revision number. Current value 14. + uint8_t RdmVer; ///< Art-Net Devices that only support RDM DRAFT V1.0 set field to 0x00. Devices that support RDM STANDARD V1.0 set field to 0x01. + uint8_t Filler2; ///< Transmit as zero, receivers don’t test. + uint8_t UID[6]; ///< UID of target RDM device. + uint8_t Spare1; ///< Transmit as zero, receivers don’t test. + uint8_t CommandClass; ///< As per RDM specification. This field defines whether this is a Get, Set, GetResponse, SetResponse. + uint8_t ParameterId[2]; ///< As per RDM specification. This field defines the type of parameter contained in this packet. Big- endian. + uint8_t SubDevice[2]; ///< Defines the first device information contained in packet. This follows the RDM convention that 0 = root device and 1 = first subdevice. Big-endian. + uint8_t SubCount[2]; ///< The number of sub devices packed into packet. Zero is illegal. Big-endian. + uint8_t Spare2; ///< Transmit as zero, receivers don’t test. + uint8_t Spare3; ///< Transmit as zero, receivers don’t test. + uint8_t Spare4; ///< Transmit as zero, receivers don’t test. + uint8_t Spare5; ///< Transmit as zero, receivers don’t test. + uint8_t Data[231]; }PACKED; struct ArtIpProg { @@ -711,6 +786,15 @@ union UArtPacket { struct ArtDirectory ArtDirectory; ///< ArtDirectory packet struct ArtDirectoryReply ArtDirectoryReply;///< ArtDirectoryReply packet }; + +struct ArtPollQueue { + uint32_t ArtPollMillis; + uint32_t ArtPollReplyIpAddress; + struct { + uint16_t TargetPortAddressTop; + uint16_t TargetPortAddressBottom; + } ArtPollReply; +}; } // namespace artnet #endif /* ARTNET_H_ */ diff --git a/lib-artnet/include/artnetconst.h b/lib-artnet/include/artnetconst.h index a895d239..90ff54c9 100644 --- a/lib-artnet/include/artnetconst.h +++ b/lib-artnet/include/artnetconst.h @@ -5,7 +5,7 @@ /** * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. */ -/* Copyright (C) 2019-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-artnet/include/artnetcontroller.h b/lib-artnet/include/artnetcontroller.h index 8141b95e..689bc292 100644 --- a/lib-artnet/include/artnetcontroller.h +++ b/lib-artnet/include/artnetcontroller.h @@ -5,7 +5,7 @@ /** * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. */ -/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -41,6 +41,15 @@ #define DMX_MAX_VALUE 255 #endif +struct State { + uint32_t ArtPollIpAddress; + uint32_t ArtPollReplyCount; + uint32_t ArtPollReplyDelayMillis; + artnet::ArtPollQueue ArtPollReplyQueue[4]; + artnet::ReportCode reportCode; + artnet::Status status; +}; + struct TArtNetController { uint32_t nIPAddressLocal; uint32_t nIPAddressBroadcast; @@ -52,6 +61,12 @@ class ArtNetController: public ArtNetPollTable { ArtNetController(); ~ArtNetController(); + void GetShortNameDefault(char *pShortName); + void SetShortName(const char *pShortName); + + void GetLongNameDefault(char *pLongName); + void SetLongName(const char *pLongName); + void Start(); void Stop(); void Run(); @@ -62,24 +77,32 @@ class ArtNetController: public ArtNetPollTable { void HandleSync(); void HandleBlackout(); - void SetRunTableCleanup(bool bDoTableCleanup) { + void SetRunTableCleanup(const bool bDoTableCleanup) { m_bDoTableCleanup = bDoTableCleanup; } - void SetSynchronization(bool bSynchronization) { + void SetSynchronization(const bool bSynchronization) { m_bSynchronization = bSynchronization; } bool GetSynchronization() const { return m_bSynchronization; } - void SetUnicast(bool bUnicast) { + void SetUnicast(const bool bUnicast) { m_bUnicast = bUnicast; } bool GetUnicast() const { return m_bUnicast; } + void SetForceBroadcast(const bool bForceBroadcast) { + m_bForceBroadcast = bForceBroadcast; + } + bool GetForceBroadcast() const { + return m_bForceBroadcast; + } + +#ifdef CONFIG_ARTNET_CONTROLLER_ENABLE_MASTER void SetMaster(uint32_t nMaster = DMX_MAX_VALUE) { if (nMaster < DMX_MAX_VALUE) { m_nMaster = nMaster; @@ -90,6 +113,7 @@ class ArtNetController: public ArtNetPollTable { uint32_t GetMaster() const { return m_nMaster; } +#endif // Handler void SetArtNetTrigger(ArtNetTrigger *pArtNetTrigger) { @@ -106,6 +130,7 @@ class ArtNetController: public ArtNetPollTable { } private: + void ProcessPoll(); void HandlePoll(); void HandlePollReply(); void HandleTrigger(); @@ -113,10 +138,8 @@ class ArtNetController: public ArtNetPollTable { void ActiveUniversesClear(); private: - struct TArtNetController m_tArtNetController; - bool m_bSynchronization { true }; - bool m_bUnicast { true }; - int32_t m_nHandle { -1 }; + TArtNetController m_ArtNetController; + State m_State; struct TArtNetPacket { union artnet::UArtPacket ArtPacket; @@ -125,17 +148,27 @@ class ArtNetController: public ArtNetPollTable { artnet::OpCodes OpCode; }; - struct TArtNetPacket *m_pArtNetPacket; artnet::ArtPoll m_ArtNetPoll; + artnet::ArtPollReply m_ArtPollReply; + + TArtNetPacket *m_pArtNetPacket; + artnet::ArtDmx *m_pArtDmx; artnet::ArtSync *m_pArtSync; ArtNetTrigger *m_pArtNetTrigger { nullptr }; // Trigger handler - uint32_t m_nLastPollMillis { 0 }; + + bool m_bSynchronization { true }; + bool m_bUnicast { true }; + bool m_bForceBroadcast { false }; bool m_bDoTableCleanup { true }; bool m_bDmxHandled { false }; + + int32_t m_nHandle { -1 }; + uint32_t m_nLastPollMillis { 0 }; uint32_t m_nActiveUniverses { 0 }; +#ifdef CONFIG_ARTNET_CONTROLLER_ENABLE_MASTER uint32_t m_nMaster { DMX_MAX_VALUE }; - +#endif static ArtNetController *s_pThis; }; diff --git a/lib-artnet/include/artnetmsgconst.h b/lib-artnet/include/artnetmsgconst.h index d82df31b..18c540ee 100644 --- a/lib-artnet/include/artnetmsgconst.h +++ b/lib-artnet/include/artnetmsgconst.h @@ -2,10 +2,7 @@ * @file artnetmsgconst.h * */ -/** - * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. - */ -/* Copyright (C) 2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -31,7 +28,6 @@ class ArtNetMsgConst { public: - static const char PARAMS[]; static const char START[]; static const char STARTED[]; static const char RDM_RUN[]; diff --git a/lib-artnet/include/artnetnode.h b/lib-artnet/include/artnetnode.h old mode 100644 new mode 100755 index 7b354711..566fc61c --- a/lib-artnet/include/artnetnode.h +++ b/lib-artnet/include/artnetnode.h @@ -5,7 +5,7 @@ /** * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. */ -/* Copyright (C) 2016-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2016-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -30,8 +30,8 @@ #define ARTNETNODE_H_ #include -#include #include +#include #include #include @@ -45,85 +45,58 @@ # endif #endif +#if defined (NODE_SHOWFILE) && defined (CONFIG_SHOWFILE_PROTOCOL_NODE_ARTNET) +# define ARTNET_SHOWFILE +#endif + #include "artnet.h" +#include "artnetnode_ports.h" #include "artnettimecode.h" -#include "artnetrdm.h" -#include "artnetstore.h" #include "artnetdisplay.h" #include "artnettrigger.h" - +#if defined (RDM_CONTROLLER) +# include "artnetrdmcontroller.h" +#endif +#if defined (RDM_RESPONDER) +# include "artnetrdmresponder.h" +#endif #if (ARTNET_VERSION >= 4) # include "e131bridge.h" #endif +#if defined(OUTPUT_DMX_SEND) || defined(OUTPUT_DMX_SEND_MULTI) +# if !defined(ARTNET_DISABLE_DMX_CONFIG_UDP) +# include "dmxconfigudp.h" +# endif +#endif + #include "lightset.h" #include "hardware.h" #include "network.h" -#include "debug.h" +#include "panel_led.h" -namespace artnetnode { -#if !defined(LIGHTSET_PORTS) -# define LIGHTSET_PORTS 0 -#endif +#include "debug.h" -#if (LIGHTSET_PORTS == 0) - static constexpr uint32_t MAX_PORTS = 1; // ISO C++ forbids zero-size array -#else - static constexpr uint32_t MAX_PORTS = LIGHTSET_PORTS; +#ifndef ALIGNED +# define ALIGNED __attribute__ ((aligned (4))) #endif +namespace artnetnode { enum class FailSafe : uint8_t { LAST = 0x08, OFF= 0x09, ON = 0x0a, PLAYBACK = 0x0b, RECORD = 0x0c }; -/** - * Table 3 – NodeReport Codes - * The NodeReport code defines generic error, advisory and status messages for both Nodes and Controllers. - * The NodeReport is returned in ArtPollReply. - */ -enum class ReportCode : uint8_t { - RCDEBUG, - RCPOWEROK, - RCPOWERFAIL, - RCSOCKETWR1, - RCPARSEFAIL, - RCUDPFAIL, - RCSHNAMEOK, - RCLONAMEOK, - RCDMXERROR, - RCDMXUDPFULL, - RCDMXRXFULL, - RCSWITCHERR, - RCCONFIGERR, - RCDMXSHORT, - RCFIRMWAREFAIL, - RCUSERFAIL -}; - -enum class Status : uint8_t { - OFF, STANDBY, ON -}; - -struct ArtPollQueue { - uint32_t ArtPollMillis; - uint32_t ArtPollReplyIpAddress; - struct { - uint16_t TargetPortAddressTop; - uint16_t TargetPortAddressBottom; - } ArtPollReply; -}; - struct State { uint32_t ArtDiagIpAddress; uint32_t ArtPollIpAddress; uint32_t ArtPollReplyCount; uint32_t ArtPollReplyDelayMillis; - ArtPollQueue ArtPollReplyQueue[4]; uint32_t ArtDmxIpAddress; uint32_t ArtSyncMillis; ///< Latest ArtSync received time - ReportCode reportCode; - Status status; + artnet::ArtPollQueue ArtPollReplyQueue[4]; + artnet::ReportCode reportCode; + artnet::Status status; bool SendArtPollReplyOnChange; ///< ArtPoll : Flags Bit 1 : 1 = Send ArtPollReply whenever Node conditions change. bool SendArtDiagData; ///< ArtPoll : Flags Bit 2 : 1 = Send me diagnostics messages. bool IsMultipleControllersReqDiag; ///< ArtPoll : Multiple controllers requesting diagnostics @@ -131,18 +104,21 @@ struct State { bool IsMergeMode; bool IsChanged; bool bDisableMergeTimeout; + bool DoRecord; uint8_t nReceivingDmx; uint8_t nEnabledOutputPorts; uint8_t nEnabledInputPorts; uint8_t DiagPriority; ///< ArtPoll : Field 6 : The lowest priority of diagnostics message that should be sent. + struct { + uint32_t nDiscoveryMillis; + uint32_t nDiscoveryPortIndex; + bool IsDiscoveryRunning; + bool IsEnabled; + } rdm; }; struct Node { - uint32_t IPAddressTimeCode; - bool IsRdmResponder; - bool bMapUniverse0; ///< Art-Net 4 struct { - char ShortName[artnet::SHORT_NAME_LENGTH]; uint16_t PortAddress; ///< The Port-Address is a 15 bit number composed of Net+Sub-Net+Universe. uint8_t DefaultAddress; uint8_t NetSwitch; ///< Bits 14-8 of the 15 bit Port-Address are encoded into the bottom 7 bits of this field. @@ -150,7 +126,11 @@ struct Node { lightset::PortDir direction; artnet::PortProtocol protocol; ///< Art-Net 4 bool bLocalMerge; - } Port[artnetnode::MAX_PORTS]; + char ShortName[artnet::SHORT_NAME_LENGTH] ALIGNED; + } Port[artnetnode::MAX_PORTS] ALIGNED; + + uint32_t IPAddressTimeCode; + bool bMapUniverse0; ///< Art-Net 4 }; struct Source { @@ -160,8 +140,9 @@ struct Source { }; struct OutputPort { - Source SourceA; - Source SourceB; + Source SourceA ALIGNED; + Source SourceB ALIGNED; + uint32_t nIpRdm; uint8_t GoodOutput; uint8_t GoodOutputB; uint8_t nPollReplyIndex; @@ -178,15 +159,19 @@ struct InputPort { }; inline artnetnode::FailSafe convert_failsafe(const lightset::FailSafe failsafe) { - const auto fs = static_cast(static_cast(failsafe) + static_cast(FailSafe::LAST)); - DEBUG_PRINTF("failsafe=%u, fs=%u", static_cast(failsafe), static_cast(fs)); - return fs; + if (failsafe > lightset::FailSafe::PLAYBACK) { + return artnetnode::FailSafe::LAST; + } + + return static_cast(static_cast(failsafe) + static_cast(artnetnode::FailSafe::LAST)); } inline lightset::FailSafe convert_failsafe(const artnetnode::FailSafe failsafe) { - const auto fs = static_cast(static_cast(failsafe) - static_cast(FailSafe::LAST)); - DEBUG_PRINTF("failsafe=%u, fs=%u", static_cast(failsafe), static_cast(fs)); - return fs; + if (failsafe > artnetnode::FailSafe::RECORD) { + return lightset::FailSafe::HOLD; + } + + return static_cast(static_cast(failsafe) - static_cast(artnetnode::FailSafe::LAST)); } } // namespace artnetnode @@ -204,7 +189,7 @@ class ArtNetNode { void Run() { uint16_t nForeignPort; - const auto nBytesReceived = Network::Get()->RecvFrom(m_nHandle, const_cast(reinterpret_cast(&m_pReceiveBuffer)), &m_nIpAddressFrom, &nForeignPort); + const auto nBytesReceived = Network::Get()->RecvFrom(m_nHandle, const_cast(reinterpret_cast(&m_pReceiveBuffer)), &m_nIpAddressFrom, &nForeignPort); m_nCurrentPacketMillis = Hardware::Get()->Millis(); Process(nBytesReceived); @@ -212,15 +197,84 @@ class ArtNetNode { #if (ARTNET_VERSION >= 4) E131Bridge::Run(); #endif -#if defined (LIGHTSET_HAVE_RUN) - m_pLightSet->Run(); +#if defined (RDM_CONTROLLER) + if (__builtin_expect((m_State.rdm.IsEnabled), 0)) { + assert(m_pArtNetRdmController != nullptr); + m_pArtNetRdmController->Run(); + + if (__builtin_expect((!m_State.rdm.IsDiscoveryRunning && ((m_nCurrentPacketMillis - m_State.rdm.nDiscoveryMillis) > (1000 * 60 * 15))), 0)) { + DEBUG_PUTS("RDM Discovery -> START"); + m_State.rdm.IsDiscoveryRunning = true; + } + + if (__builtin_expect((m_State.rdm.IsDiscoveryRunning), 0)) { + m_State.rdm.IsDiscoveryRunning = RdmDiscoveryRun(); + + if (!m_State.rdm.IsDiscoveryRunning) { + DEBUG_PUTS("RDM Discovery -> DONE"); + m_State.rdm.nDiscoveryPortIndex = 0; + m_State.rdm.nDiscoveryMillis = m_nCurrentPacketMillis; + } + } else { + uint32_t nPortIndex; + bool bIsIncremental; + if (m_pArtNetRdmController->IsFinished(nPortIndex, bIsIncremental)) { + SendTod(nPortIndex); + + DEBUG_PRINTF("TOD sent -> %u", static_cast(nPortIndex)); + + if (m_OutputPort[nPortIndex].IsTransmitting) { + DEBUG_PUTS("m_pLightSet->Stop/Start"); + m_pLightSet->Stop(nPortIndex); + m_pLightSet->Start(nPortIndex); + } + } + } + } +#endif + if ((m_nCurrentPacketMillis - m_nPreviousLedpanelMillis) > 200) { + m_nPreviousLedpanelMillis = m_nCurrentPacketMillis; + for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { + hal::panel_led_off(hal::panelled::PORT_A_TX << nPortIndex); +#if defined (ARTNET_HAVE_DMXIN) + hal::panel_led_off(hal::panelled::PORT_A_RX << nPortIndex); +#endif +#if defined(CONFIG_PANELLED_RDM_PORT) + hal::panel_led_off(hal::panelled::PORT_A_RDM << nPortIndex); +#elif defined(CONFIG_PANELLED_RDM_NO_PORT) + hal::panel_led_off(hal::panelled::RDM << nPortIndex); +#endif + } + } + +#if defined (DMXCONFIGUDP_H) + m_DmxConfigUdp.Run(); #endif } +#if defined (ARTNET_SHOWFILE) + void HandleShowFile(const artnet::ArtDmx *pArtDmx) { + m_nCurrentPacketMillis = Hardware::Get()->Millis(); + m_nIpAddressFrom = Network::Get()->GetIp(); + m_pReceiveBuffer = reinterpret_cast(const_cast(pArtDmx)); + HandleDmx(); + } +#endif + + void SetRecordShowfile(const bool doRecord) { + m_State.DoRecord = doRecord; + } + bool GetRecordShowfile() const { + return m_State.DoRecord; + } + uint8_t GetVersion() const { return artnet::VERSION; } + void SetOutputStyle(const uint32_t nPortIndex, lightset::OutputStyle outputStyle); + lightset::OutputStyle GetOutputStyle(const uint32_t nPortIndex) const; + void SetFailSafe(const artnetnode::FailSafe failsafe); artnetnode::FailSafe GetFailSafe() { @@ -248,58 +302,6 @@ class ArtNetNode { return artnetnode::FailSafe::OFF; } -#if defined (OUTPUT_HAVE_STYLESWITCH) - void SetOutputStyle(const uint32_t nPortIndex, lightset::OutputStyle outputStyle) { - assert(nPortIndex < artnetnode::MAX_PORTS); - - if (outputStyle == GetOutputStyle(nPortIndex)) { - return; - } - - if ((m_State.status == artnetnode::Status::ON) && (m_pLightSet != nullptr)) { - m_pLightSet->SetOutputStyle(nPortIndex, outputStyle); - outputStyle = m_pLightSet->GetOutputStyle(nPortIndex); - } - - if (outputStyle == lightset::OutputStyle::CONSTANT) { - m_OutputPort[nPortIndex].GoodOutputB |= artnet::GoodOutputB::STYLE_CONSTANT; - } else { - m_OutputPort[nPortIndex].GoodOutputB &= static_cast(~artnet::GoodOutputB::STYLE_CONSTANT); - } - -#if defined (OUTPUT_DMX_SEND) || defined (OUTPUT_DMX_SEND_MULTI) - /** - * FIXME I do not like this hack. It should be handled in dmx.cpp - */ - if ((m_Node.Port[nPortIndex].direction == lightset::PortDir::OUTPUT) - && (outputStyle == lightset::OutputStyle::CONSTANT) - && (m_pLightSet != nullptr)) { - if (m_OutputPort[nPortIndex].IsTransmitting) { - m_OutputPort[nPortIndex].IsTransmitting = false; - m_pLightSet->Stop(nPortIndex); - } - } -#endif - - m_State.IsSynchronousMode = false; - - if (m_State.status == artnetnode::Status::ON) { - if (m_pArtNetStore != nullptr) { - m_pArtNetStore->SaveOutputStyle(nPortIndex, outputStyle); - } - - artnet::display_outputstyle(nPortIndex, outputStyle); - } - } - - lightset::OutputStyle GetOutputStyle(const uint32_t nPortIndex) const { - assert(nPortIndex < artnetnode::MAX_PORTS); - - const auto isStyleConstant = (m_OutputPort[nPortIndex].GoodOutputB & artnet::GoodOutputB::STYLE_CONSTANT) == artnet::GoodOutputB::STYLE_CONSTANT; - return isStyleConstant ? lightset::OutputStyle::CONSTANT : lightset::OutputStyle::DELTA; - } -#endif - void SetOutput(LightSet *pLightSet) { m_pLightSet = pLightSet; #if (ARTNET_VERSION >= 4) @@ -382,12 +384,69 @@ class ArtNetNode { return lightset::MergeMode::HTP; } - void SetRmd(const uint32_t nPortIndex, const bool bEnable); + void SetRdm(const bool doEnable); + bool GetRdm() const { + return m_State.rdm.IsEnabled; + } + + void SetRdm(const uint32_t nPortIndex, const bool bEnable); bool GetRdm(const uint32_t nPortIndex) const { assert(nPortIndex < artnetnode::MAX_PORTS); return !((m_OutputPort[nPortIndex].GoodOutputB & artnet::GoodOutputB::RDM_DISABLED) == artnet::GoodOutputB::RDM_DISABLED); } + void SetRdmDiscovery(const uint32_t nPortIndex, const bool bEnable); + bool GetRdmDiscovery(const uint32_t nPortIndex) const { + assert(nPortIndex < artnetnode::MAX_PORTS); + return !((m_OutputPort[nPortIndex].GoodOutputB & artnet::GoodOutputB::DISCOVERY_DISABLED) == artnet::GoodOutputB::DISCOVERY_DISABLED); + } + +#if defined (RDM_CONTROLLER) + void SetRdmController(ArtNetRdmController *pArtNetRdmController, const bool doEnable = true); + + uint32_t RdmCopyWorkingQueue(char *pOutBuffer, const uint32_t nOutBufferSize) { + if (m_pArtNetRdmController != nullptr) { + return m_pArtNetRdmController->CopyWorkingQueue(pOutBuffer, nOutBufferSize); + } + + return 0; + } + + uint32_t RdmGetUidCount(const uint32_t nPortIndex) { + if (m_pArtNetRdmController != nullptr) { + return m_pArtNetRdmController->GetUidCount(nPortIndex); + } + + return 0; + } + + uint32_t RdmCopyTod(const uint32_t nPortIndex, char *pOutBuffer, const uint32_t nOutBufferSize) { + if (m_pArtNetRdmController != nullptr) { + return m_pArtNetRdmController->CopyTod(nPortIndex, pOutBuffer, nOutBufferSize); + } + + return 0; + } + + bool RdmIsRunning(const uint32_t nPortIndex, bool& bIsIncremental) { + uint32_t nRdmnPortIndex; + if (m_pArtNetRdmController->IsRunning(nRdmnPortIndex, bIsIncremental)) { + const auto isRunning = (nRdmnPortIndex == nPortIndex); + if (isRunning) { + assert(!((m_OutputPort[nPortIndex].GoodOutputB & artnet::GoodOutputB::DISCOVERY_NOT_RUNNING) == artnet::GoodOutputB::DISCOVERY_NOT_RUNNING)); + } + return isRunning; + } + + return false; + } + +#endif + +#if defined (RDM_RESPONDER) + void SetRdmResponder(ArtNetRdmResponder *pArtNetRdmResponder, const bool doEnable = true); +#endif + void SetDisableMergeTimeout(bool bDisable) { m_State.bDisableMergeTimeout = bDisable; #if (ARTNET_VERSION >= 4) @@ -399,19 +458,27 @@ class ArtNetNode { return m_State.bDisableMergeTimeout; } - void SendTimeCode(const struct TArtNetTimeCode *); +#if defined (ARTNET_HAVE_TIMECODE) + void SendTimeCode(const struct artnet::TimeCode *pArtNetTimeCode) { + assert(pArtNetTimeCode != nullptr); + assert(pArtNetTimeCode->Frames < 30); + assert(pArtNetTimeCode->Hours < 60); + assert(pArtNetTimeCode->Minutes < 60); + assert(pArtNetTimeCode->Seconds < 60); + assert(pArtNetTimeCode->Type < 4); + + memcpy(&m_ArtTimeCode.Frames, pArtNetTimeCode, sizeof(struct artnet::TimeCode)); + Network::Get()->SendTo(m_nHandle, &m_ArtTimeCode, sizeof(struct artnet::ArtTimeCode), m_Node.IPAddressTimeCode, artnet::UDP_PORT); + } void SetTimeCodeHandler(ArtNetTimeCode *pArtNetTimeCode) { m_pArtNetTimeCode = pArtNetTimeCode; } - void SetTimeCodeIp(uint32_t nDestinationIp); - - void SetRdmHandler(ArtNetRdm *, bool isResponder = false); - - void SetArtNetStore(ArtNetStore *pArtNetStore) { - m_pArtNetStore = pArtNetStore; + void SetTimeCodeIp(const uint32_t nDestinationIp) { + m_Node.IPAddressTimeCode = nDestinationIp; } +#endif void SetArtNetTrigger(ArtNetTrigger *pArtNetTrigger) { m_pArtNetTrigger = pArtNetTrigger; @@ -419,13 +486,8 @@ class ArtNetNode { void SetDestinationIp(const uint32_t nPortIndex, const uint32_t nDestinationIp) { if (nPortIndex < artnetnode::MAX_PORTS) { - if (Network::Get()->IsValidIp(nDestinationIp)) { - m_InputPort[nPortIndex].nDestinationIp = nDestinationIp; - } else { - m_InputPort[nPortIndex].nDestinationIp = Network::Get()->GetBroadcastIp(); - } - - DEBUG_PRINTF("m_nDestinationIp=" IPSTR, IP2STR(m_InputPort[nPortIndex].nDestinationIp)); + m_InputPort[nPortIndex].nDestinationIp = nDestinationIp; + DEBUG_PRINTF("nDestinationIp=" IPSTR, IP2STR(m_InputPort[nPortIndex].nDestinationIp)); } } @@ -516,13 +578,7 @@ class ArtNetNode { void SetNetSwitch(const uint32_t nPortIndex, const uint8_t nNetSwitch); void SetSubnetSwitch(const uint32_t nPortIndex, const uint8_t nSubnetSwitch); -#if defined (ARTNET_ENABLE_SENDDIAG) -# define UNUSED -#else -# define UNUSED __attribute__((unused)) -#endif - - void SendDiag(UNUSED const artnet::PriorityCodes priorityCode, UNUSED const char *format, ...) { + void SendDiag([[maybe_unused]] const artnet::PriorityCodes priorityCode, [[maybe_unused]] const char *format, ...) { #if defined (ARTNET_ENABLE_SENDDIAG) if (!m_State.SendArtDiagData) { return; @@ -551,10 +607,6 @@ class ArtNetNode { #endif } -#if defined (ARTNET_ENABLE_SENDDIAG) -# undef UNUSED -#endif - void HandlePoll(); void HandleDmx(); void HandleSync(); @@ -565,6 +617,7 @@ class ArtNetNode { void HandleTodData(); void HandleTodRequest(); void HandleRdm(); + void HandleRdmSub(); void HandleIpProg(); void HandleDmxIn(); void HandleInput(); @@ -572,13 +625,15 @@ class ArtNetNode { void HandleRdmIn(); void HandleTrigger(); - uint16_t MakePortAddress(const uint16_t nUniverse, const uint32_t nPage); + uint16_t MakePortAddress(const uint16_t nUniverse, const uint32_t nPage) { + return artnet::make_port_address(m_Node.Port[nPage].NetSwitch, m_Node.Port[nPage].SubSwitch, nUniverse); + } void UpdateMergeStatus(const uint32_t nPortIndex); void CheckMergeTimeouts(const uint32_t nPortIndex); void ProcessPollRelply(const uint32_t nPortIndex, uint32_t& NumPortsInput, uint32_t& NumPortsOutput); - void SendPollRelply(const uint32_t nBindIndex, const uint32_t nDestinationIp, artnetnode::ArtPollQueue *pQueue = nullptr); + void SendPollRelply(const uint32_t nBindIndex, const uint32_t nDestinationIp, artnet::ArtPollQueue *pQueue = nullptr); void SendTod(uint32_t nPortIndex); void SendTodRequest(uint32_t nPortIndex); @@ -588,20 +643,62 @@ class ArtNetNode { void FailSafeRecord(); void FailSafePlayback(); - void Process(const uint16_t); + void Process(const uint32_t); + +#if defined (RDM_CONTROLLER) + bool RdmDiscoveryRun() { + if ((GetPortDirection(m_State.rdm.nDiscoveryPortIndex) == lightset::PortDir::OUTPUT) + && (GetRdm(m_State.rdm.nDiscoveryPortIndex)) + && (GetRdmDiscovery(m_State.rdm.nDiscoveryPortIndex))) + { + uint32_t nPortIndex; + bool bIsIncremental; + + if (m_pArtNetRdmController->IsFinished(nPortIndex, bIsIncremental)) { + assert(m_State.rdm.nDiscoveryPortIndex == nPortIndex); + + SendTod(nPortIndex); + + DEBUG_PUTS("TOD sent"); + + if (m_OutputPort[nPortIndex].IsTransmitting) { + DEBUG_PUTS("m_pLightSet->Stop/Start"); + m_pLightSet->Stop(nPortIndex); + m_pLightSet->Start(nPortIndex); + } + + m_OutputPort[m_State.rdm.nDiscoveryPortIndex].GoodOutputB |= artnet::GoodOutputB::DISCOVERY_NOT_RUNNING; + + m_State.rdm.nDiscoveryPortIndex++; + return (m_State.rdm.nDiscoveryPortIndex != artnetnode::MAX_PORTS); + } + + if (!m_pArtNetRdmController->IsRunning(nPortIndex, bIsIncremental)) { + DEBUG_PRINTF("RDM Discovery Incremental -> %u", static_cast(m_State.rdm.nDiscoveryPortIndex)); + m_pArtNetRdmController->Incremental(m_State.rdm.nDiscoveryPortIndex); + m_OutputPort[m_State.rdm.nDiscoveryPortIndex].GoodOutputB &= static_cast(~artnet::GoodOutputB::DISCOVERY_NOT_RUNNING); + } + + return true; + } + + m_State.rdm.nDiscoveryPortIndex++; + return (m_State.rdm.nDiscoveryPortIndex != artnetnode::MAX_PORTS); + } +#endif + private: int32_t m_nHandle { -1 }; uint8_t *m_pReceiveBuffer { nullptr }; uint32_t m_nIpAddressFrom; uint32_t m_nCurrentPacketMillis { 0 }; uint32_t m_nPreviousPacketMillis { 0 }; + uint32_t m_nPreviousLedpanelMillis { 0 }; LightSet *m_pLightSet { nullptr }; ArtNetTimeCode *m_pArtNetTimeCode { nullptr }; - ArtNetRdm *m_pArtNetRdm { nullptr }; ArtNetTrigger *m_pArtNetTrigger { nullptr }; - ArtNetStore *m_pArtNetStore { nullptr }; artnetnode::Node m_Node; artnetnode::State m_State; @@ -619,6 +716,12 @@ class ArtNetNode { artnet::ArtRdm ArtRdm; }; UArtTodPacket m_ArtTodPacket; +# if defined (RDM_CONTROLLER) + ArtNetRdmController *m_pArtNetRdmController; +# endif +# if defined (RDM_RESPONDER) + ArtNetRdmResponder *m_pArtNetRdmResponder; +# endif #endif #if defined (ARTNET_HAVE_TIMECODE) artnet::ArtTimeCode m_ArtTimeCode; @@ -626,6 +729,9 @@ class ArtNetNode { #if defined (ARTNET_ENABLE_SENDDIAG) artnet::ArtDiagData m_DiagData; #endif +#if defined (DMXCONFIGUDP_H_) + DmxConfigUdp m_DmxConfigUdp; +#endif static ArtNetNode *s_pThis; }; diff --git a/lib-rdmsensor/include/rdmsensorstore.h b/lib-artnet/include/artnetnode_ports.h similarity index 74% rename from lib-rdmsensor/include/rdmsensorstore.h rename to lib-artnet/include/artnetnode_ports.h index 59826cc3..8317f753 100755 --- a/lib-rdmsensor/include/rdmsensorstore.h +++ b/lib-artnet/include/artnetnode_ports.h @@ -1,5 +1,5 @@ /** - * @file rdmsensorstore.h + * @file artnetnode_ports.h * */ /* Copyright (C) 2023 by Arjan van Vught mailto:info@orangepi-dmx.nl @@ -23,14 +23,19 @@ * THE SOFTWARE. */ -#ifndef RDMSENSORSTORE_H_ -#define RDMSENSORSTORE_H_ +#ifndef ARTNETNODE_PORTS_H_ +#define ARTNETNODE_PORTS_H_ -class RDMSensorStore { -public: - virtual ~RDMSensorStore() {} +namespace artnetnode { +#if !defined(LIGHTSET_PORTS) +# define LIGHTSET_PORTS 0 +#endif - virtual void SaveCalibration(uint32_t nSensor, int32_t nCalibration)=0; -}; +#if (LIGHTSET_PORTS == 0) + static constexpr uint32_t MAX_PORTS = 1; // ISO C++ forbids zero-size array +#else + static constexpr uint32_t MAX_PORTS = LIGHTSET_PORTS; +#endif +} // namespace artnetnode -#endif /* RDMSENSORSTORE_H_ */ +#endif /* IARTNETNODE_PORTS_H_ */ diff --git a/lib-artnet/include/artnetparams.h b/lib-artnet/include/artnetparams.h index 825380ba..300eec83 100644 --- a/lib-artnet/include/artnetparams.h +++ b/lib-artnet/include/artnetparams.h @@ -5,7 +5,7 @@ /** * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. */ -/* Copyright (C) 2016-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2016-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"); to deal @@ -34,7 +34,7 @@ #include #include "artnet.h" - +#include "configstore.h" #include "lightset.h" namespace artnetparams { @@ -122,27 +122,28 @@ struct Mask { class ArtNetParamsStore { public: - virtual ~ArtNetParamsStore() {} + static void Update(const struct artnetparams::Params *pParams) { + ConfigStore::Get()->Update(configstore::Store::NODE, pParams, sizeof(struct artnetparams::Params)); + } - virtual void Update(const artnetparams::Params *pArtNetParams)=0; - virtual void Copy(artnetparams::Params *pArtNetParams)=0; + static void Copy(struct artnetparams::Params *pParams) { + ConfigStore::Get()->Copy(configstore::Store::NODE, pParams, sizeof(struct artnetparams::Params)); + } }; class ArtNetParams { public: - ArtNetParams(ArtNetParamsStore *pArtNetParamsStore); + ArtNetParams(); bool Load(); void Load(const char *pBuffer, uint32_t nLength); - void Builder(const struct artnetparams::Params *pArtNetParams, char *pBuffer, uint32_t nLength, uint32_t& nSize); + void Builder(const struct artnetparams::Params *pParams, char *pBuffer, uint32_t nLength, uint32_t& nSize); void Save(char *pBuffer, uint32_t nLength, uint32_t& nSize) { Builder(nullptr, pBuffer, nLength, nSize); } - void Set(uint32_t nPortIndexOffset); - - void Dump(); + void Set(); bool IsRdm() const { return isMaskSet(artnetparams::Mask::ENABLE_RDM); @@ -162,12 +163,6 @@ class ArtNetParams { return lightset::PortDir::DISABLE; } -#if defined (ESP8266) - lightset::OutputType GetOutputType() const { - return static_cast(m_Params.Filler1); - } -#endif - static void staticCallbackFunction(void *p, const char *s); private: @@ -187,6 +182,7 @@ class ArtNetParams { return static_cast((m_Params.nProtocol >> (nPortIndex * 2)) & 0x3); } + void Dump(); void callbackFunction(const char *pLine); void SetBool(const uint8_t nValue, const uint32_t nMask); bool isMaskSet(uint32_t nMask) const { @@ -197,7 +193,6 @@ class ArtNetParams { } private: - ArtNetParamsStore *m_pArtNetParamsStore; artnetparams::Params m_Params; }; diff --git a/lib-artnet/include/artnetpolltable.h b/lib-artnet/include/artnetpolltable.h index 5e38eeb2..70d18b9b 100644 --- a/lib-artnet/include/artnetpolltable.h +++ b/lib-artnet/include/artnetpolltable.h @@ -5,7 +5,7 @@ /** * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. */ -/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,70 +33,71 @@ #include "artnet.h" -enum TArtNetPollInterval { - ARTNET_POLL_INTERVAL_SECONDS = 8, - ARTNET_POLL_INTERVAL_MILLIS = (ARTNET_POLL_INTERVAL_SECONDS * 1000) -}; - -enum TArtNetPollTableSizes { - ARTNET_POLL_TABLE_SIZE_ENRIES = 255, - ARTNET_POLL_TABLE_SIZE_NODE_UNIVERSES = 64, - ARTNET_POLL_TABLE_SIZE_UNIVERSES = 512 -}; +namespace artnet { +static constexpr uint32_t POLL_INTERVAL_SECONDS = 8; +static constexpr uint32_t POLL_INTERVAL_MILLIS = (POLL_INTERVAL_SECONDS * 1000U); +static constexpr uint32_t POLL_TABLE_SIZE_ENRIES = 255; +static constexpr uint32_t POLL_TABLE_SIZE_NODE_UNIVERSES = 64; +static constexpr uint32_t POLL_TABLE_SIZE_UNIVERSES = 512; -struct TArtNetNodeEntryUniverse { +struct NodeEntryUniverse { + uint8_t ShortName[artnet::SHORT_NAME_LENGTH]; uint32_t nLastUpdateMillis; uint16_t nUniverse; }; -struct TArtNetNodeEntry { +struct NodeEntry { uint32_t IPAddress; uint8_t Mac[artnet::MAC_SIZE]; - uint8_t ShortName[artnet::SHORT_NAME_LENGTH]; uint8_t LongName[artnet::LONG_NAME_LENGTH]; uint16_t nUniversesCount; - struct TArtNetNodeEntryUniverse Universe[ARTNET_POLL_TABLE_SIZE_NODE_UNIVERSES]; + struct NodeEntryUniverse Universe[artnet::POLL_TABLE_SIZE_NODE_UNIVERSES]; }; -struct TArtNetPollTableUniverses { +struct PollTableUniverses { uint16_t nUniverse; uint16_t nCount; uint32_t *pIpAddresses; }; -struct TArtNetPollTableClean { +struct PollTableClean { uint32_t nTableIndex; uint16_t nUniverseIndex; bool bOffLine; }; +} // namespace artnet class ArtNetPollTable { public: ArtNetPollTable(); ~ArtNetPollTable(); - uint32_t GetEntries() const { + const artnet::NodeEntry *GetPollTable() const { + return m_pPollTable; + } + + uint32_t GetPollTableEntries() const { return m_nPollTableEntries; } void Add(const struct artnet::ArtPollReply *ptArtPollReply); void Clean(); - const struct TArtNetPollTableUniverses *GetIpAddress(uint16_t nUniverse) const; + const struct artnet::PollTableUniverses *GetIpAddress(uint16_t nUniverse) const; void Dump(); void DumpTableUniverses(); private: - void ProcessUniverse(uint32_t nIpAddress, uint16_t nUniverse); - void RemoveIpAddress(uint16_t nUniverse, uint32_t nIpAddress); + void ProcessUniverse(const uint32_t nIpAddress, const uint16_t nUniverse); + void RemoveIpAddress(const uint16_t nUniverse, const uint32_t nIpAddress); private: - TArtNetNodeEntry *m_pPollTable; - uint32_t m_nPollTableEntries{0}; - TArtNetPollTableUniverses *m_pTableUniverses; - uint32_t m_nTableUniversesEntries{0}; - TArtNetPollTableClean m_tTableClean; + artnet::NodeEntry *m_pPollTable; + artnet::PollTableUniverses *m_pTableUniverses; + uint32_t m_nPollTableEntries { 0 }; + uint32_t m_nTableUniversesEntries { 0 }; + artnet::PollTableClean m_PollTableClean; }; #endif /* ARTNETPOLLTABLE_H_ */ diff --git a/lib-artnet/include/artnetrdmcontroller.h b/lib-artnet/include/artnetrdmcontroller.h new file mode 100755 index 00000000..437c0e1f --- /dev/null +++ b/lib-artnet/include/artnetrdmcontroller.h @@ -0,0 +1,165 @@ +/** + * @file artnetrdmcontroller.h + * + */ +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef ARTNETRDMCONTROLLER_H_ +#define ARTNETRDMCONTROLLER_H_ + +#include +#include +#include + +#include "rdmdiscovery.h" +#include "rdmdevicecontroller.h" +#include "rdm.h" + +#include "artnetnode_ports.h" + +#include "debug.h" + +class ArtNetRdmController final: public RDMDeviceController, RDMDiscovery { +public: + ArtNetRdmController(): RDMDiscovery(RDMDeviceController::GetUID()) { + DEBUG_ENTRY + DEBUG_EXIT + } + + // Discovery + + void Full(const uint32_t nPortIndex) { + DEBUG_ENTRY + assert(nPortIndex < artnetnode::MAX_PORTS); + RDMDiscovery::Full(nPortIndex, &m_pRDMTod[nPortIndex]); + DEBUG_EXIT + } + + void Incremental(const uint32_t nPortIndex) { + DEBUG_ENTRY + assert(nPortIndex < artnetnode::MAX_PORTS); + RDMDiscovery::Incremental(nPortIndex, &m_pRDMTod[nPortIndex]); + DEBUG_EXIT + } + + void Stop(const uint32_t nPortIndex) { + DEBUG_ENTRY + assert(nPortIndex < artnetnode::MAX_PORTS); + bool bIsIncremental; + uint32_t _nPortIndex; + if (IsRunning(_nPortIndex, bIsIncremental)) { + if (_nPortIndex == nPortIndex) { + RDMDiscovery::Stop(); + } + } + DEBUG_EXIT + } + + uint32_t GetUidCount(const uint32_t nPortIndex) { + assert(nPortIndex < artnetnode::MAX_PORTS); + return m_pRDMTod[nPortIndex].GetUidCount(); + } + + void TodCopy(const uint32_t nPortIndex, uint8_t *pTod) { + DEBUG_ENTRY + assert(nPortIndex < artnetnode::MAX_PORTS); + m_pRDMTod[nPortIndex].Copy(pTod); + DEBUG_EXIT + } + + void Run() { + RDMDiscovery::Run(); + } + + bool IsRunning(uint32_t& nPortIndex, bool& bIsIncremental) { + return RDMDiscovery::IsRunning(nPortIndex, bIsIncremental); + } + + bool IsFinished(uint32_t& nPortIndex, bool& bIsIncremental) { + return RDMDiscovery::IsFinished(nPortIndex, bIsIncremental); + } + + uint32_t CopyWorkingQueue(char *pOutBuffer, const uint32_t nOutBufferSize) { + return RDMDiscovery::CopyWorkingQueue(pOutBuffer, nOutBufferSize); + } + + uint32_t CopyTod(const uint32_t nPortIndex, char *pOutBuffer, const uint32_t nOutBufferSize) { + assert(nPortIndex < artnetnode::MAX_PORTS); + + const auto nSize = static_cast(nOutBufferSize); + int32_t nLength = 0; + + for (uint32_t nCount = 0; nCount < m_pRDMTod[nPortIndex].GetUidCount(); nCount++) { + uint8_t uid[RDM_UID_SIZE]; + + m_pRDMTod[nPortIndex].CopyUidEntry(nCount, uid); + + nLength += snprintf(&pOutBuffer[nLength], static_cast(nSize - nLength), + "\"%.2x%.2x:%.2x%.2x%.2x%.2x\",", + uid[0], uid[1], uid[2], uid[3], uid[4], uid[5]); + } + + if (nLength == 0) { + return 0; + } + + pOutBuffer[nLength - 1] = '\0'; + + return static_cast(nLength - 1); + + } + + // Gateway + + bool RdmReceive(const uint32_t nPortIndex, const uint8_t *pRdmData); + + void TodReset(const uint32_t nPortIndex) { + assert(nPortIndex < artnetnode::MAX_PORTS); + m_pRDMTod[nPortIndex].Reset(); + } + + bool TodAddUid(const uint32_t nPortIndex, const uint8_t *pUid) { + return m_pRDMTod[nPortIndex].AddUid(pUid); + } + + // Generic + + bool CopyTodEntry(const uint32_t nPortIndex, uint32_t nIndex, uint8_t uid[RDM_UID_SIZE]) { + assert(nPortIndex < artnetnode::MAX_PORTS); + return m_pRDMTod[nPortIndex].CopyUidEntry(nIndex, uid); + } + + void TodDump(const uint32_t nPortIndex) { + assert(nPortIndex < artnetnode::MAX_PORTS); + m_pRDMTod[nPortIndex].Dump(); + } + + RDMTod *GetTod(const uint32_t nPortIndex) { + assert(nPortIndex < artnetnode::MAX_PORTS); + return &m_pRDMTod[nPortIndex]; + } + +private: + static RDMTod m_pRDMTod[artnetnode::MAX_PORTS]; +}; + +#endif /* ARTNETRDMCONTROLLER_H_ */ diff --git a/lib-rdmresponder/include/artnetrdmresponder.h b/lib-artnet/include/artnetrdmresponder.h similarity index 55% rename from lib-rdmresponder/include/artnetrdmresponder.h rename to lib-artnet/include/artnetrdmresponder.h index de5e92c8..fa2d4845 100644 --- a/lib-rdmresponder/include/artnetrdmresponder.h +++ b/lib-artnet/include/artnetrdmresponder.h @@ -2,7 +2,7 @@ * @file artnetrdmresponder.h * */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -30,35 +30,37 @@ #include #include -#include "artnetrdm.h" - #include "rdmdeviceresponder.h" #include "rdmpersonality.h" #include "rdmhandler.h" -#include "rdm.h" +#include "rdmconst.h" +#include "rdm_message_print.h" #include "lightset.h" +#include "debug.h" + #if defined (NODE_RDMNET_LLRP_ONLY) # error "Cannot be both RDMNet Device and RDM Responder" #endif -class ArtNetRdmResponder: public ArtNetRdm, public RDMDeviceResponder, RDMHandler { +class ArtNetRdmResponder final: public RDMDeviceResponder, RDMHandler { public: - ArtNetRdmResponder(RDMPersonality **pRDMPersonalities, uint32_t nPersonalityCount); - ~ArtNetRdmResponder() override; - - void Full(__attribute__((unused)) uint32_t nPortIndex) override { - // We are a Responder - no code needed + ArtNetRdmResponder(RDMPersonality **pRDMPersonalities, const uint32_t nPersonalityCount) : + RDMDeviceResponder(pRDMPersonalities, nPersonalityCount) + { + DEBUG_ENTRY + DEBUG_EXIT } - uint32_t GetUidCount(const uint32_t nPortIndex) override { - DEBUG_PRINTF("nPortIndex=%u", nPortIndex); - return nPortIndex == 0 ? 1 : 0; // We are a Responder + ~ArtNetRdmResponder() { + DEBUG_ENTRY + DEBUG_EXIT } - void TodCopy(const uint32_t nPortIndex, unsigned char *tod) override { + void TodCopy(const uint32_t nPortIndex, unsigned char *tod) { DEBUG_PRINTF("nPortIndex=%u", nPortIndex); + if (nPortIndex == 0) { memcpy(tod, RDMDeviceResponder::GetUID(), RDM_UID_SIZE); } else { @@ -66,31 +68,39 @@ class ArtNetRdmResponder: public ArtNetRdm, public RDMDeviceResponder, RDMHandle } } - void TodReset(__attribute__((unused)) uint32_t nPortIndex) override {} - bool TodAddUid(__attribute__((unused)) uint32_t nPortIndex, __attribute__((unused)) const uint8_t *pUid) override { return false;} + const uint8_t *Handler(const uint32_t nPortIndex, const uint8_t *pRdmDataNoSC) { + DEBUG_ENTRY - const uint8_t *Handler(uint32_t nPortIndex, const uint8_t *) override; + if (nPortIndex != 0) { + DEBUG_EXIT + return nullptr; + } - uint16_t GetDmxStartAddress(uint16_t nSubDevice = RDM_ROOT_DEVICE) { - return RDMDeviceResponder::GetDmxStartAddress(nSubDevice); - } + if (pRdmDataNoSC == nullptr) { + DEBUG_EXIT + return nullptr; + } - uint16_t GetDmxFootPrint(uint16_t nSubDevice = RDM_ROOT_DEVICE) { - return RDMDeviceResponder::GetDmxFootPrint(nSubDevice); - } +#ifndef NDEBUG + rdm::message_print_no_sc(pRdmDataNoSC); +#endif - // + RDMHandler::HandleData(pRdmDataNoSC, reinterpret_cast(&s_RdmCommand)); - bool RdmReceive(__attribute__((unused)) uint32_t nPortIndex, __attribute__((unused)) uint8_t *pRdmData) override { - return false; - } + if (s_RdmCommand.start_code != E120_SC_RDM) { + DEBUG_EXIT + return nullptr; + } + +#ifndef NDEBUG + rdm::message_print(reinterpret_cast(&s_RdmCommand)); +#endif - static ArtNetRdmResponder* Get() { - return s_pThis; + DEBUG_EXIT + return reinterpret_cast(&s_RdmCommand); } private: - static ArtNetRdmResponder *s_pThis; static TRdmMessage s_RdmCommand; }; diff --git a/lib-artnet/include/artnetstore.h b/lib-artnet/include/artnetstore.h index 23749de5..c627eb01 100644 --- a/lib-artnet/include/artnetstore.h +++ b/lib-artnet/include/artnetstore.h @@ -5,7 +5,7 @@ /** * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -30,28 +30,226 @@ #define ARTNETSTORE_H_ #include +#include -#include "artnet.h" -#include "lightset.h" +#include "artnetparams.h" +#include "configstore.h" +#include "artnetnode.h" + +#include "debug.h" + +namespace artnetnode { +namespace configstore { +extern uint32_t DMXPORT_OFFSET; +} // namespace configstore +} // namespace artnetnode class ArtNetStore { public: - virtual ~ArtNetStore() {} + static void SaveLongName(const char *pLongName) { + DEBUG_ENTRY + ConfigStore::Get()->Update(configstore::Store::NODE, offsetof(struct artnetparams::Params, aLongName), pLongName, artnet::LONG_NAME_LENGTH, artnetparams::Mask::LONG_NAME); + DEBUG_EXIT + + } + + static void SaveShortName(uint32_t nPortIndex, const char *pShortName) { + DEBUG_ENTRY + DEBUG_PRINTF("%u, %s", nPortIndex, pShortName); + + if (nPortIndex >= artnetnode::configstore::DMXPORT_OFFSET) { + nPortIndex -= artnetnode::configstore::DMXPORT_OFFSET; + } else { + DEBUG_EXIT + return; + } + + DEBUG_PRINTF("nPortIndex=%u", nPortIndex); + + if (nPortIndex >= artnet::PORTS) { + DEBUG_EXIT + return; + } + + ConfigStore::Get()->Update(configstore::Store::NODE, (artnet::SHORT_NAME_LENGTH * nPortIndex) + offsetof(struct artnetparams::Params, aLabel), pShortName, artnet::SHORT_NAME_LENGTH, artnetparams::Mask::LABEL_A << nPortIndex); + + DEBUG_EXIT + } + + static void SaveUniverseSwitch(const uint32_t nPortIndex, [[maybe_unused]] const uint8_t nUniverseSwitch) { + DEBUG_ENTRY + SaveUniverse(nPortIndex); + DEBUG_EXIT + } + + static void SaveNetSwitch(const uint32_t nPortIndex, [[maybe_unused]] const uint8_t nNetSwitch) { + DEBUG_ENTRY + SaveUniverse(nPortIndex); + DEBUG_EXIT + } + + static void SaveSubnetSwitch(const uint32_t nPortIndex, [[maybe_unused]] const uint8_t nSubnetSwitch) { + DEBUG_ENTRY + SaveUniverse(nPortIndex); + DEBUG_EXIT + } + + static void SaveMergeMode(uint32_t nPortIndex, const lightset::MergeMode mergeMode) { + DEBUG_ENTRY + DEBUG_PRINTF("%u, %u", nPortIndex, static_cast(mergeMode)); + + if (nPortIndex >= artnetnode::configstore::DMXPORT_OFFSET) { + nPortIndex -= artnetnode::configstore::DMXPORT_OFFSET; + } else { + DEBUG_EXIT + return; + } + + DEBUG_PRINTF("nPortIndex=%u", nPortIndex); + + if (nPortIndex >= artnet::PORTS) { + DEBUG_EXIT + return; + } + + uint16_t nMergeMode; + ConfigStore::Get()->Copy(configstore::Store::NODE, &nMergeMode, sizeof(uint16_t), offsetof(struct artnetparams::Params, nMergeMode), false); + + nMergeMode &= artnetparams::mergemode_clear(nPortIndex); + nMergeMode |= artnetparams::mergemode_set(nPortIndex, mergeMode); + + ConfigStore::Get()->Update(configstore::Store::NODE, offsetof(struct artnetparams::Params, nMergeMode), &nMergeMode, sizeof(uint16_t)); + + DEBUG_EXIT + } + + static void SavePortProtocol(uint32_t nPortIndex, const artnet::PortProtocol portProtocol) { + DEBUG_ENTRY + DEBUG_PRINTF("artnetnode::configstore::DMXPORT_OFFSET=%u, nPortIndex=%u, portProtocol=%u", artnetnode::configstore::DMXPORT_OFFSET, nPortIndex, static_cast(portProtocol)); + + if (nPortIndex >= artnetnode::configstore::DMXPORT_OFFSET) { + nPortIndex -= artnetnode::configstore::DMXPORT_OFFSET; + } else { + DEBUG_EXIT + return; + } + + DEBUG_PRINTF("nPortIndex=%u", nPortIndex); + + if (nPortIndex >= artnet::PORTS) { + DEBUG_EXIT + return; + } + + uint16_t nPortProtocol; + ConfigStore::Get()->Copy(configstore::Store::NODE, &nPortProtocol, sizeof(uint16_t), offsetof(struct artnetparams::Params, nProtocol), false); + + nPortProtocol &= artnetparams::protocol_clear(nPortIndex); + nPortProtocol |= artnetparams::protocol_set(nPortIndex, portProtocol); + + ConfigStore::Get()->Update(configstore::Store::NODE, offsetof(struct artnetparams::Params, nProtocol), &nPortProtocol, sizeof(uint16_t)); + DEBUG_EXIT + } + + static void SaveOutputStyle(uint32_t nPortIndex, const lightset::OutputStyle outputStyle) { + DEBUG_ENTRY + DEBUG_PRINTF("artnetnode::configstore::DMXPORT_OFFSET=%u, nPortIndex=%u, outputStyle=%u", artnetnode::configstore::DMXPORT_OFFSET, nPortIndex, static_cast(outputStyle)); + + if (nPortIndex >= artnetnode::configstore::DMXPORT_OFFSET) { + nPortIndex -= artnetnode::configstore::DMXPORT_OFFSET; + } else { + DEBUG_EXIT + return; + } + + DEBUG_PRINTF("nPortIndex=%u", nPortIndex); + + if (nPortIndex >= artnet::PORTS) { + DEBUG_EXIT + return; + } + + uint8_t nOutputStyle; + ConfigStore::Get()->Copy(configstore::Store::NODE, &nOutputStyle, sizeof(uint8_t), offsetof(struct artnetparams::Params, nOutputStyle), false); + + if (outputStyle == lightset::OutputStyle::CONSTANT) { + nOutputStyle |= static_cast(1U << nPortIndex); + } else { + nOutputStyle &= static_cast(~(1U << nPortIndex)); + } + + ConfigStore::Get()->Update(configstore::Store::NODE, offsetof(struct artnetparams::Params, nOutputStyle), &nOutputStyle, sizeof(uint8_t)); + + DEBUG_EXIT + } + + static void SaveRdmEnabled(uint32_t nPortIndex, const bool isEnabled) { + DEBUG_ENTRY + DEBUG_PRINTF("artnetnode::configstore::DMXPORT_OFFSET=%u, nPortIndex=%u, isEnabled=%d", artnetnode::configstore::DMXPORT_OFFSET, nPortIndex, isEnabled); + + if (nPortIndex >= artnetnode::configstore::DMXPORT_OFFSET) { + nPortIndex -= artnetnode::configstore::DMXPORT_OFFSET; + } else { + DEBUG_EXIT + return; + } + + DEBUG_PRINTF("nPortIndex=%u", nPortIndex); + + if (nPortIndex >= artnet::PORTS) { + DEBUG_EXIT + return; + } + + uint16_t nRdm; + ConfigStore::Get()->Copy(configstore::Store::NODE, &nRdm, sizeof(uint16_t), offsetof(struct artnetparams::Params, nRdm), false); + + nRdm &= artnetparams::clear_mask(nPortIndex); + + if (isEnabled) { + nRdm |= artnetparams::shift_left(1, nPortIndex); + nRdm |= static_cast(1U << (nPortIndex + 8)); + } + + ConfigStore::Get()->Update(configstore::Store::NODE, offsetof(struct artnetparams::Params, nRdm), &nRdm, sizeof(uint16_t)); + + DEBUG_EXIT + } + + static void SaveFailSafe(uint8_t nFailSafe) { + DEBUG_ENTRY + ConfigStore::Get()->Update(configstore::Store::NODE, offsetof(struct artnetparams::Params, nFailSafe), &nFailSafe, sizeof(uint8_t), artnetparams::Mask::FAILSAFE); + DEBUG_EXIT + } + +private: + void static SaveUniverse(uint32_t nPortIndex) { + DEBUG_ENTRY + DEBUG_PRINTF("artnetnode::configstore::DMXPORT_OFFSET=%u, nPortIndex=%u", artnetnode::configstore::DMXPORT_OFFSET, nPortIndex); + + uint16_t nUniverse; - virtual void SaveLongName(const char *pLongName)=0; + if (ArtNetNode::Get()->GetPortAddress(nPortIndex, nUniverse)) { + if (nPortIndex >= artnetnode::configstore::DMXPORT_OFFSET) { + nPortIndex -= artnetnode::configstore::DMXPORT_OFFSET; + } else { + DEBUG_EXIT + return; + } - virtual void SaveShortName(const uint32_t nPortIndex, const char *pShortName)=0; + DEBUG_PRINTF("nPortIndex=%u", nPortIndex); - virtual void SaveUniverseSwitch(const uint32_t nPortIndex, const uint8_t nAddress)=0; - virtual void SaveNetSwitch(const uint32_t nPage, const uint8_t nAddress)=0; - virtual void SaveSubnetSwitch(const uint32_t nPage, const uint8_t nAddress)=0; + if (nPortIndex >= artnet::PORTS) { + DEBUG_EXIT + return; + } - virtual void SaveMergeMode(const uint32_t nPortIndex, const lightset::MergeMode mergeMode)=0; - virtual void SavePortProtocol(const uint32_t nPortIndex, const artnet::PortProtocol portProtocol)=0; - virtual void SaveOutputStyle(const uint32_t nPortIndex, const lightset::OutputStyle outputStyle)=0; - virtual void SaveRdmEnabled(const uint32_t nPortIndex, const bool isEnabled)=0; + DEBUG_PRINTF("nPortIndex=%u, nUniverse=%u", nPortIndex, nUniverse); + ConfigStore::Get()->Update(configstore::Store::NODE, (sizeof(uint16_t) * nPortIndex) + offsetof(struct artnetparams::Params, nUniverse), &nUniverse, sizeof(uint16_t), artnetparams::Mask::UNIVERSE_A << nPortIndex); + } - virtual void SaveFailSafe(const uint8_t nFailsafe)=0; + DEBUG_EXIT + } }; #endif /* ARTNETSTORE_H_ */ diff --git a/lib-artnet/include/artnettimecode.h b/lib-artnet/include/artnettimecode.h old mode 100644 new mode 100755 index 5238fa3a..980e7891 --- a/lib-artnet/include/artnettimecode.h +++ b/lib-artnet/include/artnettimecode.h @@ -5,7 +5,7 @@ /** * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. */ -/* Copyright (C) 2016-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2016-2024 by Arjan van Vught mailto:info@gd332-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -31,23 +31,20 @@ #include -struct TArtNetTimeCode { +namespace artnet { +struct TimeCode { uint8_t Frames; ///< Frames time. 0 – 29 depending on mode. uint8_t Seconds; ///< Seconds. 0 - 59. uint8_t Minutes; ///< Minutes. 0 - 59. uint8_t Hours; ///< Hours. 0 - 59. uint8_t Type; ///< 0 = Film (24fps) , 1 = EBU (25fps), 2 = DF (29.97fps), 3 = SMPTE (30fps) } __attribute__((packed)); +} // namespace artnet class ArtNetTimeCode { public: - virtual ~ArtNetTimeCode() { - } - - virtual void Start()= 0; - virtual void Stop()= 0; - - virtual void Handler(const struct TArtNetTimeCode*)= 0; + virtual ~ArtNetTimeCode() = default; + virtual void Handler(const struct artnet::TimeCode *)= 0; }; #endif /* ARTNETTIMECODE_H_ */ diff --git a/lib-artnet/include/artnettrigger.h b/lib-artnet/include/artnettrigger.h index a5f7d81f..98efd7bc 100644 --- a/lib-artnet/include/artnettrigger.h +++ b/lib-artnet/include/artnettrigger.h @@ -5,7 +5,7 @@ /** * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. */ -/* Copyright (C) 2019-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -50,8 +50,7 @@ struct TArtNetTrigger { class ArtNetTrigger { public: - virtual ~ArtNetTrigger() {} - + virtual ~ArtNetTrigger() = default; virtual void Handler(const struct TArtNetTrigger *ptArtNetTrigger)= 0; }; diff --git a/lib-artnet/src/artnetconst.cpp b/lib-artnet/src/artnetconst.cpp index ba6b0211..5e36a9fb 100644 --- a/lib-artnet/src/artnetconst.cpp +++ b/lib-artnet/src/artnetconst.cpp @@ -2,10 +2,7 @@ * @file artnetconst.cpp * */ -/** - * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. - */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -31,7 +28,7 @@ #include "artnetconst.h" #include "artnet.h" -const uint8_t ArtNetConst::VERSION[] = { 1, 58 }; +const uint8_t ArtNetConst::VERSION[] = { 1, 60 }; const uint8_t ArtNetConst::ESTA_ID[artnet::ESTA_SIZE] = { 0x50, 0x00 }; ///< https://tsp.esta.org/tsp/working_groups/CP/mfctrIDs.php const uint8_t ArtNetConst::OEM_ID[] = { 0xff, 0xff }; ///< Waiting OEM from Artistic Licence Holdings Ltd. diff --git a/lib-artnet/src/controller/artnetcontroller.cpp b/lib-artnet/src/controller/artnetcontroller.cpp index d13785ca..9c8f56bd 100644 --- a/lib-artnet/src/controller/artnetcontroller.cpp +++ b/lib-artnet/src/controller/artnetcontroller.cpp @@ -1,11 +1,11 @@ /** - * @file artnetcontroller.h + * @file artnetcontroller.cpp * */ /** * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. */ -/* Copyright (C) 2017-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -36,34 +36,89 @@ #include "artnet.h" #include "artnetconst.h" +#if (ARTNET_VERSION >= 4) +# include "e131.h" +#endif + #include "hardware.h" #include "network.h" #include "debug.h" -#define ARTNET_MIN_HEADER_SIZE 12 - -static uint16_t s_ActiveUniverses[ARTNET_POLL_TABLE_SIZE_UNIVERSES] __attribute__ ((aligned (4))); - ArtNetController *ArtNetController::s_pThis; using namespace artnet; +static constexpr uint32_t ARTNET_MIN_HEADER_SIZE = 12; +static uint16_t s_ActiveUniverses[POLL_TABLE_SIZE_UNIVERSES] __attribute__ ((aligned (4))); + ArtNetController::ArtNetController() { DEBUG_ENTRY + union uip { + uint32_t u32; + uint8_t u8[4]; + } ip; + assert(s_pThis == nullptr); s_pThis = this; m_pArtNetPacket = new struct TArtNetPacket; assert(m_pArtNetPacket != nullptr); + memset(&m_State, 0, sizeof(struct State)); + m_State.reportCode = artnet::ReportCode::RCPOWEROK; + m_State.status = artnet::Status::STANDBY; + memset(&m_ArtNetPoll, 0, sizeof(struct ArtPoll)); memcpy(&m_ArtNetPoll, artnet::NODE_ID, 8); m_ArtNetPoll.OpCode = static_cast(artnet::OpCodes::OP_POLL); m_ArtNetPoll.ProtVerLo = artnet::PROTOCOL_REVISION; m_ArtNetPoll.Flags = Flags::SEND_ARTP_ON_CHANGE; + memset(&m_ArtPollReply, 0, sizeof(struct ArtPollReply)); + memcpy(&m_ArtPollReply, artnet::NODE_ID, 8); + m_ArtPollReply.OpCode = static_cast(artnet::OpCodes::OP_POLLREPLY); + m_ArtPollReply.Port = artnet::UDP_PORT; + m_ArtPollReply.VersInfoH = ArtNetConst::VERSION[0]; + m_ArtPollReply.VersInfoL = ArtNetConst::VERSION[1]; + m_ArtPollReply.OemHi = ArtNetConst::OEM_ID[0]; + m_ArtPollReply.Oem = ArtNetConst::OEM_ID[1]; + m_ArtPollReply.EstaMan[0] = ArtNetConst::ESTA_ID[1]; + m_ArtPollReply.EstaMan[1] = ArtNetConst::ESTA_ID[0]; + m_ArtPollReply.Style = static_cast(StyleCode::SERVER); + Network::Get()->MacAddressCopyTo(m_ArtPollReply.MAC); + m_ArtPollReply.BindIndex = 1; + ip.u32 = Network::Get()->GetIp(); + memcpy(m_ArtPollReply.IPAddress, ip.u8, sizeof(m_ArtPollReply.IPAddress)); +#if (ARTNET_VERSION >= 4) + memcpy(m_ArtPollReply.BindIp, ip.u8, sizeof(m_ArtPollReply.BindIp)); + m_ArtPollReply.AcnPriority = e131::priority::DEFAULT; +#endif + /* + * Status 1 + */ + m_ArtPollReply.Status1 |= artnet::Status1::INDICATOR_NORMAL_MODE | artnet::Status1::PAP_NETWORK; + /* + * Status 2 + */ + m_ArtPollReply.Status2 &= static_cast(~artnet::Status2::SACN_ABLE_TO_SWITCH); + m_ArtPollReply.Status2 |= artnet::Status2::PORT_ADDRESS_15BIT | (artnet::VERSION >= 4 ? artnet::Status2::SACN_ABLE_TO_SWITCH : artnet::Status2::SACN_NO_SWITCH); + m_ArtPollReply.Status2 &= static_cast(~artnet::Status2::IP_DHCP); + m_ArtPollReply.Status2 |= Network::Get()->IsDhcpUsed() ? artnet::Status2::IP_DHCP : artnet::Status2::IP_MANUALY; + m_ArtPollReply.Status2 &= static_cast(~artnet::Status2::DHCP_CAPABLE); + m_ArtPollReply.Status2 |= Network::Get()->IsDhcpCapable() ? artnet::Status2::DHCP_CAPABLE : static_cast(0); + +#if defined (ENABLE_HTTPD) && defined (ENABLE_CONTENT) + m_ArtPollReply.Status2 |= artnet::Status2::WEB_BROWSER_SUPPORT; +#endif + + m_ArtPollReply.PortTypes[0] = artnet::PortType::OUTPUT_ARTNET; + m_ArtPollReply.PortTypes[1] = artnet::PortType::INPUT_ARTNET; + m_ArtPollReply.GoodOutput[0] = artnet::GoodOutput::DATA_IS_BEING_TRANSMITTED; + m_ArtPollReply.GoodInput[0] = artnet::GoodInput::DATA_RECIEVED; + m_ArtPollReply.NumPortsLo = 2; + m_pArtDmx = new struct ArtDmx; assert(m_pArtDmx != nullptr); @@ -80,11 +135,14 @@ ArtNetController::ArtNetController() { m_pArtSync->OpCode = static_cast(artnet::OpCodes::OP_SYNC); m_pArtSync->ProtVerLo = artnet::PROTOCOL_REVISION; - m_tArtNetController.Oem[0] = ArtNetConst::OEM_ID[0]; - m_tArtNetController.Oem[1] = ArtNetConst::OEM_ID[1]; + m_ArtNetController.Oem[0] = ArtNetConst::OEM_ID[0]; + m_ArtNetController.Oem[1] = ArtNetConst::OEM_ID[1]; ActiveUniversesClear(); + SetShortName(nullptr); + SetLongName(nullptr); + DEBUG_EXIT } @@ -97,16 +155,91 @@ ArtNetController::~ArtNetController() { DEBUG_EXIT } +void ArtNetController::GetShortNameDefault(char *ShortName) { +#if !defined (ARTNET_SHORT_NAME) + uint8_t nBoardNameLength; + const auto *const pBoardName = Hardware::Get()->GetBoardName(nBoardNameLength); + const auto *const pWebsiteUrl = Hardware::Get()->GetWebsiteUrl(); + snprintf(ShortName, artnet::LONG_NAME_LENGTH - 1, "%s %s %u %s", pBoardName, artnet::NODE_ID, static_cast(artnet::VERSION), pWebsiteUrl); +#else + uint32_t i; + + for (i = 0; i < (sizeof(ARTNET_SHORT_NAME) - 1) && i < (artnet::SHORT_NAME_LENGTH - 1) ; i++ ) { + if (ARTNET_SHORT_NAME[i] == '_') { + ShortName[i] = ' '; + } else { + ShortName[i] = ARTNET_SHORT_NAME[i]; + } + } + + ShortName[i] = '\0'; +#endif +} + +void ArtNetController::SetShortName(const char *ShortName) { + DEBUG_ENTRY + + if (ShortName == nullptr) { + GetShortNameDefault(reinterpret_cast(m_ArtPollReply.ShortName)); + } else { + strncpy(reinterpret_cast(m_ArtPollReply.ShortName), ShortName, artnet::SHORT_NAME_LENGTH - 1); + } + + m_ArtPollReply.LongName[artnet::SHORT_NAME_LENGTH - 1] = '\0'; + + DEBUG_PUTS(reinterpret_cast(m_ArtPollReply.ShortName)); + DEBUG_EXIT +} + +void ArtNetController::GetLongNameDefault(char *pLongName) { +#if !defined (ARTNET_LONG_NAME) + uint8_t nBoardNameLength; + const auto *const pBoardName = Hardware::Get()->GetBoardName(nBoardNameLength); + const auto *const pWebsiteUrl = Hardware::Get()->GetWebsiteUrl(); + snprintf(pLongName, artnet::LONG_NAME_LENGTH - 1, "%s %s %u %s", pBoardName, artnet::NODE_ID, static_cast(artnet::VERSION), pWebsiteUrl); +#else + uint32_t i; + + for (i = 0; i < (sizeof(ARTNET_LONG_NAME) - 1) && i < (artnet::LONG_NAME_LENGTH - 1) ; i++ ) { + if (ARTNET_LONG_NAME[i] == '_') { + pLongName[i] = ' '; + } else { + pLongName[i] = ARTNET_LONG_NAME[i]; + } + } + + pLongName[i] = '\0'; +#endif +} + +void ArtNetController::SetLongName(const char *pLongName) { + DEBUG_ENTRY + + if (pLongName == nullptr) { + GetLongNameDefault(reinterpret_cast(m_ArtPollReply.LongName)); + } else { + strncpy(reinterpret_cast(m_ArtPollReply.LongName), pLongName, artnet::LONG_NAME_LENGTH - 1); + } + + m_ArtPollReply.LongName[artnet::LONG_NAME_LENGTH - 1] = '\0'; + + DEBUG_PUTS(reinterpret_cast(m_ArtPollReply.LongName)); + DEBUG_EXIT +} + void ArtNetController::Start() { DEBUG_ENTRY - m_tArtNetController.nIPAddressLocal = Network::Get()->GetIp(); - m_tArtNetController.nIPAddressBroadcast = Network::Get()->GetBroadcastIp(); + m_ArtNetController.nIPAddressLocal = Network::Get()->GetIp(); + m_ArtNetController.nIPAddressBroadcast = Network::Get()->GetBroadcastIp(); + assert(m_nHandle == -1); m_nHandle = Network::Get()->Begin(artnet::UDP_PORT); assert(m_nHandle != -1); - Network::Get()->SendTo(m_nHandle, &m_ArtNetPoll, sizeof(struct ArtPoll), m_tArtNetController.nIPAddressBroadcast, artnet::UDP_PORT); + Network::Get()->SendTo(m_nHandle, &m_ArtNetPoll, sizeof(struct ArtPoll), m_ArtNetController.nIPAddressBroadcast, artnet::UDP_PORT); + + m_State.status = artnet::Status::ON; DEBUG_EXIT } @@ -114,7 +247,12 @@ void ArtNetController::Start() { void ArtNetController::Stop() { DEBUG_ENTRY - //FIXME ArtNetController::Stop +// FIXME ArtNetController::Stop +// +// Network::Get()->End(artnet::UDP_PORT); +// m_nHandle = -1; +// +// m_State.status = artnet::Status::OFF; DEBUG_EXIT } @@ -137,8 +275,11 @@ void ArtNetController::HandleDmxOut(uint16_t nUniverse, const uint8_t *pDmxData, m_pArtDmx->Sequence = 1; } +#if defined(CONFIG_ARTNET_CONTROLLER_ENABLE_MASTER) if (__builtin_expect((m_nMaster == DMX_MAX_VALUE), 1)) { +#endif memcpy(m_pArtDmx->Data, pDmxData, nLength); +#if defined(CONFIG_ARTNET_CONTROLLER_ENABLE_MASTER) } else if (m_nMaster == 0) { memset(m_pArtDmx->Data, 0, nLength); } else { @@ -146,11 +287,12 @@ void ArtNetController::HandleDmxOut(uint16_t nUniverse, const uint8_t *pDmxData, m_pArtDmx->Data[i] = ((m_nMaster * static_cast(pDmxData[i])) / DMX_MAX_VALUE) & 0xFF; } } +#endif uint32_t nCount = 0; - auto IpAddresses = const_cast(GetIpAddress(nUniverse)); + auto IpAddresses = const_cast(GetIpAddress(nUniverse)); - if (m_bUnicast) { + if (m_bUnicast && !m_bForceBroadcast) { if (IpAddresses != nullptr) { nCount = IpAddresses->nCount; } else { @@ -161,7 +303,7 @@ void ArtNetController::HandleDmxOut(uint16_t nUniverse, const uint8_t *pDmxData, // If the number of universe subscribers exceeds 40 for a given universe, the transmitting device may broadcast. - if (m_bUnicast && (nCount <= 40)) { + if (m_bUnicast && (nCount <= 40) && !m_bForceBroadcast) { for (uint32_t nIndex = 0; nIndex < nCount; nIndex++) { Network::Get()->SendTo(m_nHandle, m_pArtDmx, sizeof(struct ArtDmx), IpAddresses->pIpAddresses[nIndex], artnet::UDP_PORT); } @@ -172,8 +314,8 @@ void ArtNetController::HandleDmxOut(uint16_t nUniverse, const uint8_t *pDmxData, return; } - if (!m_bUnicast || (nCount > 40)) { - Network::Get()->SendTo(m_nHandle, m_pArtDmx, sizeof(struct ArtDmx), m_tArtNetController.nIPAddressBroadcast, artnet::UDP_PORT); + if (!m_bUnicast || (nCount > 40) || !m_bForceBroadcast) { + Network::Get()->SendTo(m_nHandle, m_pArtDmx, sizeof(struct ArtDmx), m_ArtNetController.nIPAddressBroadcast, artnet::UDP_PORT); m_bDmxHandled = true; } @@ -184,7 +326,7 @@ void ArtNetController::HandleDmxOut(uint16_t nUniverse, const uint8_t *pDmxData, void ArtNetController::HandleSync() { if (m_bSynchronization && m_bDmxHandled) { m_bDmxHandled = false; - Network::Get()->SendTo(m_nHandle, m_pArtSync, sizeof(struct ArtSync), m_tArtNetController.nIPAddressBroadcast, artnet::UDP_PORT); + Network::Get()->SendTo(m_nHandle, m_pArtSync, sizeof(struct ArtSync), m_ArtNetController.nIPAddressBroadcast, artnet::UDP_PORT); } } @@ -200,7 +342,7 @@ void ArtNetController::HandleBlackout() { uint32_t nCount = 0; const auto *IpAddresses = GetIpAddress(s_ActiveUniverses[nIndex]); - if (m_bUnicast) { + if (m_bUnicast && !m_bForceBroadcast) { if (IpAddresses != nullptr) { nCount = IpAddresses->nCount; } else { @@ -208,7 +350,7 @@ void ArtNetController::HandleBlackout() { } } - if (m_bUnicast && (nCount <= 40)) { + if (m_bUnicast && (nCount <= 40) && !m_bForceBroadcast) { // The sequence number is used to ensure that ArtDmx packets are used in the correct order. // This field is incremented in the range 0x01 to 0xff to allow the receiving node to resequence packets. m_pArtDmx->Sequence++; @@ -224,7 +366,7 @@ void ArtNetController::HandleBlackout() { continue; } - if (!m_bUnicast || (nCount > 40)) { + if (!m_bUnicast || (nCount > 40) || !m_bForceBroadcast) { // The sequence number is used to ensure that ArtDmx packets are used in the correct order. // This field is incremented in the range 0x01 to 0xff to allow the receiving node to resequence packets. m_pArtDmx->Sequence++; @@ -233,7 +375,7 @@ void ArtNetController::HandleBlackout() { m_pArtDmx->Sequence = 1; } - Network::Get()->SendTo(m_nHandle, m_pArtDmx, sizeof(struct ArtDmx), m_tArtNetController.nIPAddressBroadcast, artnet::UDP_PORT); + Network::Get()->SendTo(m_nHandle, m_pArtDmx, sizeof(struct ArtDmx), m_ArtNetController.nIPAddressBroadcast, artnet::UDP_PORT); } } @@ -246,7 +388,7 @@ void ArtNetController::HandleTrigger() { DEBUG_ENTRY const ArtTrigger *pArtTrigger = &m_pArtNetPacket->ArtPacket.ArtTrigger; - if ((pArtTrigger->OemCodeHi == 0xFF && pArtTrigger->OemCodeLo == 0xFF) || (pArtTrigger->OemCodeHi == m_tArtNetController.Oem[0] && pArtTrigger->OemCodeLo == m_tArtNetController.Oem[1])) { + if ((pArtTrigger->OemCodeHi == 0xFF && pArtTrigger->OemCodeLo == 0xFF) || (pArtTrigger->OemCodeHi == m_ArtNetController.Oem[0] && pArtTrigger->OemCodeLo == m_ArtNetController.Oem[1])) { DEBUG_PRINTF("Key=%d, SubKey=%d, Data[0]=%d", pArtTrigger->Key, pArtTrigger->SubKey, pArtTrigger->Data[0]); m_pArtNetTrigger->Handler(reinterpret_cast(&pArtTrigger->Key)); @@ -255,11 +397,11 @@ void ArtNetController::HandleTrigger() { DEBUG_EXIT } -void ArtNetController::HandlePoll() { +void ArtNetController::ProcessPoll() { const auto nCurrentMillis = Hardware::Get()->Millis(); - if (__builtin_expect((nCurrentMillis - m_nLastPollMillis > ARTNET_POLL_INTERVAL_MILLIS), 0)) { - Network::Get()->SendTo(m_nHandle, &m_ArtNetPoll, sizeof(struct ArtPoll), m_tArtNetController.nIPAddressBroadcast, artnet::UDP_PORT); + if (__builtin_expect((nCurrentMillis - m_nLastPollMillis > POLL_INTERVAL_MILLIS), 0)) { + Network::Get()->SendTo(m_nHandle, &m_ArtNetPoll, sizeof(struct ArtPoll), m_ArtNetController.nIPAddressBroadcast, artnet::UDP_PORT); m_nLastPollMillis= nCurrentMillis; #ifndef NDEBUG @@ -268,28 +410,45 @@ void ArtNetController::HandlePoll() { #endif } - if (m_bDoTableCleanup && (__builtin_expect((nCurrentMillis - m_nLastPollMillis > ARTNET_POLL_INTERVAL_MILLIS/4), 0))) { + if (m_bDoTableCleanup && (__builtin_expect((nCurrentMillis - m_nLastPollMillis > POLL_INTERVAL_MILLIS/4), 0))) { Clean(); } } +void ArtNetController::HandlePoll() { + DEBUG_ENTRY + + snprintf(reinterpret_cast(m_ArtPollReply.NodeReport), artnet::REPORT_LENGTH, "#%04x [%u]", static_cast(m_State.reportCode), static_cast(m_State.ArtPollReplyCount++)); + + Network::Get()->SendTo(m_nHandle, &m_ArtPollReply, sizeof(artnet::ArtPollReply), m_pArtNetPacket->IPAddressFrom, artnet::UDP_PORT); + + DEBUG_PRINTF(IPSTR, IP2STR(m_pArtNetPacket->IPAddressFrom)); + DEBUG_EXIT +} + void ArtNetController::HandlePollReply() { DEBUG_ENTRY + DEBUG_PRINTF(IPSTR, IP2STR(m_pArtNetPacket->IPAddressFrom)); - Add(&m_pArtNetPacket->ArtPacket.ArtPollReply); + if (m_pArtNetPacket->IPAddressFrom != Network::Get()->GetIp()) { + Add(&m_pArtNetPacket->ArtPacket.ArtPollReply); + + DEBUG_EXIT + return; + } DEBUG_EXIT } void ArtNetController::Run() { - char *pArtPacket = reinterpret_cast(&m_pArtNetPacket->ArtPacket); + auto *pArtPacket = reinterpret_cast(&m_pArtNetPacket->ArtPacket); uint16_t nForeignPort; if (m_bUnicast) { - HandlePoll(); + ProcessPoll(); } - const int nBytesReceived = Network::Get()->RecvFrom(m_nHandle, pArtPacket, sizeof(struct TArtNetPacket), &m_pArtNetPacket->IPAddressFrom, &nForeignPort) ; + const auto nBytesReceived = Network::Get()->RecvFrom(m_nHandle, pArtPacket, sizeof(struct TArtNetPacket), &m_pArtNetPacket->IPAddressFrom, &nForeignPort) ; if (__builtin_expect((nBytesReceived < ARTNET_MIN_HEADER_SIZE), 1)) { return; @@ -305,6 +464,9 @@ void ArtNetController::Run() { case artnet::OpCodes::OP_POLLREPLY: HandlePollReply(); break; + case artnet::OpCodes::OP_POLL: + HandlePoll(); + break; case artnet::OpCodes::OP_TRIGGER: if (m_pArtNetTrigger != nullptr) { HandleTrigger(); @@ -376,12 +538,15 @@ void ArtNetController::ActiveUniversesAdd(uint16_t nUniverse) { } void ArtNetController::Print() { - printf("Art-Net Controller\n"); - printf(" Max Node's : %u\n", ARTNET_POLL_TABLE_SIZE_ENRIES); - printf(" Max Universes : %u\n", ARTNET_POLL_TABLE_SIZE_UNIVERSES); + puts("Art-Net Controller"); + printf(" Max Node's : %u\n", POLL_TABLE_SIZE_ENRIES); + printf(" Max Universes : %u\n", POLL_TABLE_SIZE_UNIVERSES); if (!m_bUnicast) { puts(" Unicast is disabled"); } + if (!m_bForceBroadcast) { + puts(" Force broadcast is enabled"); + } if (!m_bSynchronization) { puts(" Synchronization is disabled"); } diff --git a/lib-artnet/src/controller/artnetpolltable.cpp b/lib-artnet/src/controller/artnetpolltable.cpp index 73c48d49..8b0251a1 100644 --- a/lib-artnet/src/controller/artnetpolltable.cpp +++ b/lib-artnet/src/controller/artnetpolltable.cpp @@ -5,7 +5,7 @@ /** * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. */ -/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -45,39 +45,40 @@ #include "debug.h" -using namespace artnet; - union uip { uint32_t u32; uint8_t u8[4]; } static ip; ArtNetPollTable::ArtNetPollTable() { - m_pPollTable = new TArtNetNodeEntry[ARTNET_POLL_TABLE_SIZE_ENRIES]; + DEBUG_ENTRY + + m_pPollTable = new artnet::NodeEntry[artnet::POLL_TABLE_SIZE_ENRIES]; assert(m_pPollTable != nullptr); - memset(m_pPollTable, 0, sizeof(TArtNetNodeEntry[ARTNET_POLL_TABLE_SIZE_ENRIES])); + memset(m_pPollTable, 0, sizeof(artnet::NodeEntry[artnet::POLL_TABLE_SIZE_ENRIES])); - m_pTableUniverses = new TArtNetPollTableUniverses[ARTNET_POLL_TABLE_SIZE_UNIVERSES]; + m_pTableUniverses = new artnet::PollTableUniverses[artnet::POLL_TABLE_SIZE_UNIVERSES]; assert(m_pTableUniverses != nullptr); - memset(m_pTableUniverses, 0, sizeof(TArtNetPollTableUniverses[ARTNET_POLL_TABLE_SIZE_UNIVERSES])); + memset(m_pTableUniverses, 0, sizeof(artnet::PollTableUniverses[artnet::POLL_TABLE_SIZE_UNIVERSES])); - for (uint32_t nIndex = 0; nIndex < ARTNET_POLL_TABLE_SIZE_UNIVERSES; nIndex++) { - m_pTableUniverses[nIndex].pIpAddresses = new uint32_t[ARTNET_POLL_TABLE_SIZE_ENRIES]; + for (uint32_t nIndex = 0; nIndex < artnet::POLL_TABLE_SIZE_UNIVERSES; nIndex++) { + m_pTableUniverses[nIndex].pIpAddresses = new uint32_t[artnet::POLL_TABLE_SIZE_ENRIES]; assert(m_pTableUniverses[nIndex].pIpAddresses != nullptr); } -// DEBUG_PRINTF("TArtNetNodeEntry[%d] = %u bytes [%u Kb]", ARTNET_POLL_TABLE_SIZE_ENRIES, (sizeof(TArtNetNodeEntry[ARTNET_POLL_TABLE_SIZE_ENRIES])), (sizeof(TArtNetNodeEntry[ARTNET_POLL_TABLE_SIZE_ENRIES])) / 1024); -// DEBUG_PRINTF("TArtNetPollTableUniverses[%d] = %u bytes [%u Kb]", ARTNET_POLL_TABLE_SIZE_UNIVERSES, (sizeof(TArtNetPollTableUniverses[ARTNET_POLL_TABLE_SIZE_UNIVERSES])), (sizeof(TArtNetPollTableUniverses[ARTNET_POLL_TABLE_SIZE_UNIVERSES])) / 1024); + m_PollTableClean.nTableIndex = 0; + m_PollTableClean.nUniverseIndex = 0; + m_PollTableClean.bOffLine = true; - m_tTableClean.nTableIndex = 0; - m_tTableClean.nUniverseIndex = 0; - m_tTableClean.bOffLine = true; + DEBUG_PRINTF("NodeEntry[%d] = %u bytes [%u Kb]", artnet::POLL_TABLE_SIZE_ENRIES, static_cast(sizeof(artnet::NodeEntry[artnet::POLL_TABLE_SIZE_ENRIES])), static_cast(sizeof(artnet::NodeEntry[artnet::POLL_TABLE_SIZE_ENRIES])) / 1024U); + DEBUG_PRINTF("PollTableUniverses[%d] = %u bytes [%u Kb]", artnet::POLL_TABLE_SIZE_UNIVERSES, static_cast(sizeof(artnet::PollTableUniverses[artnet::POLL_TABLE_SIZE_UNIVERSES])), static_cast(sizeof(artnet::PollTableUniverses[artnet::POLL_TABLE_SIZE_UNIVERSES])) / 1024U); + DEBUG_EXIT } ArtNetPollTable::~ArtNetPollTable() { - for (uint32_t nIndex = 0; nIndex < ARTNET_POLL_TABLE_SIZE_UNIVERSES; nIndex++) { + for (uint32_t nIndex = 0; nIndex < artnet::POLL_TABLE_SIZE_UNIVERSES; nIndex++) { delete[] m_pTableUniverses[nIndex].pIpAddresses; m_pTableUniverses[nIndex].pIpAddresses = nullptr; } @@ -89,14 +90,14 @@ ArtNetPollTable::~ArtNetPollTable() { m_pPollTable = nullptr; } -const struct TArtNetPollTableUniverses *ArtNetPollTable::GetIpAddress(uint16_t nUniverse) const { +const struct artnet::PollTableUniverses *ArtNetPollTable::GetIpAddress(uint16_t nUniverse) const { if (m_nTableUniversesEntries == 0) { return nullptr; } // FIXME Universe lookup for (uint32_t nEntry = 0; nEntry < m_nTableUniversesEntries; nEntry++) { - TArtNetPollTableUniverses *pTableUniverses = &m_pTableUniverses[nEntry]; + artnet::PollTableUniverses *pTableUniverses = &m_pTableUniverses[nEntry]; assert(pTableUniverses != nullptr); if (pTableUniverses->nUniverse == nUniverse) { @@ -108,7 +109,7 @@ const struct TArtNetPollTableUniverses *ArtNetPollTable::GetIpAddress(uint16_t n } -void ArtNetPollTable::RemoveIpAddress(uint16_t nUniverse, uint32_t nIpAddress) { +void ArtNetPollTable::RemoveIpAddress(const uint16_t nUniverse, const uint32_t nIpAddress) { if (m_nTableUniversesEntries == 0) { return; } @@ -117,7 +118,7 @@ void ArtNetPollTable::RemoveIpAddress(uint16_t nUniverse, uint32_t nIpAddress) { // FIXME Universe lookup for (nEntry = 0; nEntry < m_nTableUniversesEntries; nEntry++) { - TArtNetPollTableUniverses *pTableUniverses = &m_pTableUniverses[nEntry]; + artnet::PollTableUniverses *pTableUniverses = &m_pTableUniverses[nEntry]; assert(pTableUniverses != nullptr); if (pTableUniverses->nUniverse == nUniverse) { @@ -130,7 +131,7 @@ void ArtNetPollTable::RemoveIpAddress(uint16_t nUniverse, uint32_t nIpAddress) { return; } - TArtNetPollTableUniverses *pTableUniverses = &m_pTableUniverses[nEntry]; + artnet::PollTableUniverses *pTableUniverses = &m_pTableUniverses[nEntry]; assert(pTableUniverses->nCount > 0); uint32_t nIpAddressIndex = 0; @@ -142,7 +143,7 @@ void ArtNetPollTable::RemoveIpAddress(uint16_t nUniverse, uint32_t nIpAddress) { } } - uint32_t *p32 = pTableUniverses->pIpAddresses; + auto *p32 = pTableUniverses->pIpAddresses; int32_t i; for (i = static_cast(nIpAddressIndex); i < static_cast(pTableUniverses->nCount) - 1; i++) { @@ -156,7 +157,7 @@ void ArtNetPollTable::RemoveIpAddress(uint16_t nUniverse, uint32_t nIpAddress) { if (pTableUniverses->nCount == 0) { DEBUG_PRINTF("Delete Universe -> m_nTableUniversesEntries=%u, nEntry=%u", m_nTableUniversesEntries, nEntry); - TArtNetPollTableUniverses *p = m_pTableUniverses; + artnet::PollTableUniverses *p = m_pTableUniverses; for (i = static_cast(nEntry); i < static_cast(m_nTableUniversesEntries) - 1; i++) { p[i].nUniverse = p[i + 1].nUniverse; @@ -171,21 +172,21 @@ void ArtNetPollTable::RemoveIpAddress(uint16_t nUniverse, uint32_t nIpAddress) { } } -void ArtNetPollTable::ProcessUniverse(uint32_t nIpAddress, uint16_t nUniverse) { +void ArtNetPollTable::ProcessUniverse(const uint32_t nIpAddress, const uint16_t nUniverse) { DEBUG_ENTRY - if (ARTNET_POLL_TABLE_SIZE_UNIVERSES == m_nTableUniversesEntries) { + if (artnet::POLL_TABLE_SIZE_UNIVERSES == m_nTableUniversesEntries) { DEBUG_PUTS("m_pTableUniverses is full"); DEBUG_EXIT return; } // FIXME Universe lookup - bool bFoundUniverse = false; + auto bFoundUniverse = false; uint32_t nEntry = 0; for (nEntry = 0; nEntry < m_nTableUniversesEntries; nEntry++) { - TArtNetPollTableUniverses *pTableUniverses = &m_pTableUniverses[nEntry]; + auto *pTableUniverses = &m_pTableUniverses[nEntry]; assert(pTableUniverses != nullptr); if (pTableUniverses->nUniverse == nUniverse) { @@ -195,9 +196,8 @@ void ArtNetPollTable::ProcessUniverse(uint32_t nIpAddress, uint16_t nUniverse) { } } - TArtNetPollTableUniverses *pTableUniverses = &m_pTableUniverses[nEntry]; - - bool bFoundIp = false; + auto *pTableUniverses = &m_pTableUniverses[nEntry]; + auto bFoundIp = false; uint32_t nCount = 0; if (bFoundUniverse) { @@ -217,7 +217,7 @@ void ArtNetPollTable::ProcessUniverse(uint32_t nIpAddress, uint16_t nUniverse) { } if (!bFoundIp) { - if (pTableUniverses->nCount < ARTNET_POLL_TABLE_SIZE_ENRIES) { + if (pTableUniverses->nCount < artnet::POLL_TABLE_SIZE_ENRIES) { pTableUniverses->pIpAddresses[pTableUniverses->nCount] = nIpAddress; pTableUniverses->nCount++; DEBUG_PUTS("It is a new IP for the Universe"); @@ -232,7 +232,7 @@ void ArtNetPollTable::ProcessUniverse(uint32_t nIpAddress, uint16_t nUniverse) { void ArtNetPollTable::Add(const struct artnet::ArtPollReply *ptArtPollReply) { DEBUG_ENTRY - bool bFound = false; + auto bFound = false; memcpy(ip.u8, ptArtPollReply->IPAddress, 4); @@ -259,7 +259,7 @@ void ArtNetPollTable::Add(const struct artnet::ArtPollReply *ptArtPollReply) { } if (!bFound) { - if (m_nPollTableEntries == ARTNET_POLL_TABLE_SIZE_ENRIES) { + if (m_nPollTableEntries == artnet::POLL_TABLE_SIZE_ENRIES) { DEBUG_PUTS("Full"); return; } @@ -267,19 +267,19 @@ void ArtNetPollTable::Add(const struct artnet::ArtPollReply *ptArtPollReply) { if (m_nPollTableEntries != static_cast(nHigh)) { DEBUG_PUTS("Move"); - struct TArtNetNodeEntry *pArtNetNodeEntry = m_pPollTable; // TODO + auto *pArtNetNodeEntry = m_pPollTable; // TODO assert(m_nPollTableEntries >= 1); assert(nLow >= 0); for (int32_t i = static_cast(m_nPollTableEntries) - 1;i >= nLow; i--) { - const struct TArtNetNodeEntry *pSrc = &pArtNetNodeEntry[i]; - struct TArtNetNodeEntry *pDst = &pArtNetNodeEntry[i + 1]; - memcpy(pDst, pSrc, sizeof(struct TArtNetNodeEntry)); + const struct artnet::NodeEntry *pSrc = &pArtNetNodeEntry[i]; + struct artnet::NodeEntry *pDst = &pArtNetNodeEntry[i + 1]; + memcpy(pDst, pSrc, sizeof(struct artnet::NodeEntry)); } - struct TArtNetNodeEntry *pDst = &pArtNetNodeEntry[nLow]; - memset(pDst, 0, sizeof(struct TArtNetNodeEntry)); + auto *pDst = &pArtNetNodeEntry[nLow]; + memset(pDst, 0, sizeof(struct artnet::NodeEntry)); i = nLow; } else { @@ -291,20 +291,17 @@ void ArtNetPollTable::Add(const struct artnet::ArtPollReply *ptArtPollReply) { m_nPollTableEntries++; } -#ifndef NDEBUG if (ptArtPollReply->BindIndex <= 1) { memcpy(m_pPollTable[i].Mac, ptArtPollReply->MAC, artnet::MAC_SIZE); - - const uint8_t *pSrc = ptArtPollReply->ShortName; - uint8_t *pDst = m_pPollTable[i].ShortName; - memcpy(pDst, pSrc, artnet::SHORT_NAME_LENGTH + artnet::LONG_NAME_LENGTH); + const uint8_t *pSrc = ptArtPollReply->LongName; + uint8_t *pDst = m_pPollTable[i].LongName; + memcpy(pDst, pSrc, artnet::LONG_NAME_LENGTH); } -#endif - const uint32_t nMillis = Hardware::Get()->Millis(); + const auto nMillis = Hardware::Get()->Millis(); for (uint32_t nIndex = 0; nIndex < artnet::PORTS; nIndex++) { - const uint8_t nPortAddress = ptArtPollReply->SwOut[nIndex]; + const auto nPortAddress = ptArtPollReply->SwOut[nIndex]; if (ptArtPollReply->PortTypes[nIndex] == static_cast(artnet::PortType::OUTPUT_ARTNET)) { const auto nUniverse = artnet::make_port_address(ptArtPollReply->NetSwitch, ptArtPollReply->SubSwitch, nPortAddress); @@ -319,9 +316,12 @@ void ArtNetPollTable::Add(const struct artnet::ArtPollReply *ptArtPollReply) { if (nIndexUniverse == m_pPollTable[i].nUniversesCount) { // Not found - if (m_pPollTable[i].nUniversesCount < ARTNET_POLL_TABLE_SIZE_NODE_UNIVERSES) { + if (m_pPollTable[i].nUniversesCount < artnet::POLL_TABLE_SIZE_NODE_UNIVERSES) { m_pPollTable[i].nUniversesCount++; m_pPollTable[i].Universe[nIndexUniverse].nUniverse = nUniverse; + const uint8_t *pSrc = ptArtPollReply->ShortName; + uint8_t *pDst = m_pPollTable[i].Universe[nIndexUniverse].ShortName; + memcpy(pDst, pSrc, artnet::SHORT_NAME_LENGTH); ProcessUniverse(ip.u32, nUniverse); } else { // No room @@ -341,56 +341,55 @@ void ArtNetPollTable::Clean() { return; } - assert(m_tTableClean.nTableIndex < m_nPollTableEntries); - assert(m_tTableClean.nUniverseIndex < ARTNET_POLL_TABLE_SIZE_NODE_UNIVERSES); + assert(m_PollTableClean.nTableIndex < m_nPollTableEntries); + assert(m_PollTableClean.nUniverseIndex < artnet::POLL_TABLE_SIZE_NODE_UNIVERSES); - if (m_tTableClean.nUniverseIndex == 0) { - m_tTableClean.bOffLine = true; + if (m_PollTableClean.nUniverseIndex == 0) { + m_PollTableClean.bOffLine = true; } - struct TArtNetNodeEntryUniverse *pArtNetNodeEntryBind = &m_pPollTable[m_tTableClean.nTableIndex].Universe[m_tTableClean.nUniverseIndex]; + auto *pArtNetNodeEntryBind = &m_pPollTable[m_PollTableClean.nTableIndex].Universe[m_PollTableClean.nUniverseIndex]; if (pArtNetNodeEntryBind->nLastUpdateMillis != 0) { - if ((Hardware::Get()->Millis() - pArtNetNodeEntryBind->nLastUpdateMillis) > (1.5 * ARTNET_POLL_INTERVAL_MILLIS)) { + if ((Hardware::Get()->Millis() - pArtNetNodeEntryBind->nLastUpdateMillis) > (1.5 * artnet::POLL_INTERVAL_MILLIS)) { pArtNetNodeEntryBind->nLastUpdateMillis = 0; - RemoveIpAddress(pArtNetNodeEntryBind->nUniverse, m_pPollTable[m_tTableClean.nTableIndex].IPAddress); + RemoveIpAddress(pArtNetNodeEntryBind->nUniverse, m_pPollTable[m_PollTableClean.nTableIndex].IPAddress); } else { - m_tTableClean.bOffLine = false; + m_PollTableClean.bOffLine = false; } } - m_tTableClean.nUniverseIndex++; + m_PollTableClean.nUniverseIndex++; - if (m_tTableClean.nUniverseIndex == ARTNET_POLL_TABLE_SIZE_NODE_UNIVERSES) { - if (m_tTableClean.bOffLine) { + if (m_PollTableClean.nUniverseIndex == artnet::POLL_TABLE_SIZE_NODE_UNIVERSES) { + if (m_PollTableClean.bOffLine) { DEBUG_PUTS("Node is off-line"); - struct TArtNetNodeEntry *pArtNetNodeEntry = m_pPollTable; + auto *pArtNetNodeEntry = m_pPollTable; // Move - for (uint32_t i = m_tTableClean.nTableIndex; i < (m_nPollTableEntries - 1); i++) { - const struct TArtNetNodeEntry *pSrc = &pArtNetNodeEntry[i + 1]; - struct TArtNetNodeEntry *pDst = &pArtNetNodeEntry[i]; - - memcpy(pDst, pSrc, sizeof(struct TArtNetNodeEntry)); + for (uint32_t i = m_PollTableClean.nTableIndex; i < (m_nPollTableEntries - 1); i++) { + const auto *pSrc = &pArtNetNodeEntry[i + 1]; + auto *pDst = &pArtNetNodeEntry[i]; + memcpy(pDst, pSrc, sizeof(struct artnet::NodeEntry)); } m_nPollTableEntries--; - struct TArtNetNodeEntry *pDst = &pArtNetNodeEntry[m_nPollTableEntries]; + auto *pDst = &pArtNetNodeEntry[m_nPollTableEntries]; pDst->IPAddress = 0; pDst->nUniversesCount = 0; - memset(pDst->Universe, 0, sizeof(struct TArtNetNodeEntryUniverse[ARTNET_POLL_TABLE_SIZE_NODE_UNIVERSES])); + memset(pDst->Universe, 0, sizeof(struct artnet::NodeEntryUniverse[artnet::POLL_TABLE_SIZE_NODE_UNIVERSES])); #ifndef NDEBUG - memset(pDst->Mac, 0, artnet::MAC_SIZE + artnet::SHORT_NAME_LENGTH + artnet::LONG_NAME_LENGTH); + memset(pDst->Mac, 0, artnet::MAC_SIZE + artnet::LONG_NAME_LENGTH); #endif } - m_tTableClean.nUniverseIndex = 0; - m_tTableClean.bOffLine = true; - m_tTableClean.nTableIndex++; + m_PollTableClean.nUniverseIndex = 0; + m_PollTableClean.bOffLine = true; + m_PollTableClean.nTableIndex++; - if (m_tTableClean.nTableIndex >= m_nPollTableEntries) { - m_tTableClean.nTableIndex = 0; + if (m_PollTableClean.nTableIndex >= m_nPollTableEntries) { + m_PollTableClean.nTableIndex = 0; } } } @@ -400,11 +399,11 @@ void ArtNetPollTable::Dump() { printf("Entries : %d\n", m_nPollTableEntries); for (uint32_t i = 0; i < m_nPollTableEntries; i++) { - printf("\t" IPSTR " [" MACSTR "] |%-18s|%-64s|\n", IP2STR(m_pPollTable[i].IPAddress), MAC2STR(m_pPollTable[i].Mac), m_pPollTable[i].ShortName, m_pPollTable[i].LongName); + printf("\t" IPSTR " [" MACSTR "] |%-64s|\n", IP2STR(m_pPollTable[i].IPAddress), MAC2STR(m_pPollTable[i].Mac), m_pPollTable[i].LongName); for (uint32_t nUniverse = 0; nUniverse < m_pPollTable[i].nUniversesCount; nUniverse++) { - struct TArtNetNodeEntryUniverse *pArtNetNodeEntryUniverse = &m_pPollTable[i].Universe[nUniverse]; - printf("\t %u [%u]\n", pArtNetNodeEntryUniverse->nUniverse, (Hardware::Get()->Millis() - pArtNetNodeEntryUniverse->nLastUpdateMillis) / 1000U); + auto *pArtNetNodeEntryUniverse = &m_pPollTable[i].Universe[nUniverse]; + printf("\t %u [%u] |%-18s|\n", pArtNetNodeEntryUniverse->nUniverse, (Hardware::Get()->Millis() - pArtNetNodeEntryUniverse->nLastUpdateMillis) / 1000U, pArtNetNodeEntryUniverse->ShortName); } puts(""); } @@ -416,12 +415,12 @@ void ArtNetPollTable::DumpTableUniverses() { printf("Entries : %d\n", m_nTableUniversesEntries); for (uint32_t nEntry = 0; nEntry < m_nTableUniversesEntries; nEntry++) { - const TArtNetPollTableUniverses *pTableUniverses = &m_pTableUniverses[nEntry]; + const auto *pTableUniverses = &m_pTableUniverses[nEntry]; assert(pTableUniverses != nullptr); printf("%3d |%4u | %d ", nEntry, pTableUniverses->nUniverse, pTableUniverses->nCount); - const uint32_t *pIpAddresses = pTableUniverses->pIpAddresses; + const auto *pIpAddresses = pTableUniverses->pIpAddresses; assert(pIpAddresses != nullptr); for (uint32_t nCount = 0; nCount < pTableUniverses->nCount; nCount++) { diff --git a/lib-artnet/src/controller/json_get_polltable.cpp b/lib-artnet/src/controller/json_get_polltable.cpp new file mode 100755 index 00000000..1c8b300a --- /dev/null +++ b/lib-artnet/src/controller/json_get_polltable.cpp @@ -0,0 +1,93 @@ +/** + * @file json_status.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include + +#include "artnetcontroller.h" +#include "artnet.h" +#include "network.h" + +namespace remoteconfig { +namespace artnet { +namespace controller { +static uint32_t get_port(const struct ::artnet::NodeEntryUniverse *pArtNetNodeEntryUniverse, char *pOutBuffer, const uint32_t nOutBufferSize) { + const auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, + "{\"name\":\"%s\",\"universe\":%u},", + pArtNetNodeEntryUniverse->ShortName, pArtNetNodeEntryUniverse->nUniverse)); + + if (nLength <= nOutBufferSize) { + return nLength; + } + + return 0; +} + +static uint32_t get_entry(const uint32_t nIndex, char *pOutBuffer, const uint32_t nOutBufferSize) { + const auto *pPollTable = ArtNetController::Get()->GetPollTable(); + auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, + "{\"name\":\"%s\",\"ip\":\"" IPSTR "\",\"mac\":\"" MACSTR "\",\"ports\":[", + pPollTable[nIndex].LongName, IP2STR(pPollTable[nIndex].IPAddress), MAC2STR(pPollTable[nIndex].Mac))); + + for (uint32_t nUniverse = 0; nUniverse < pPollTable[nIndex].nUniversesCount; nUniverse++) { + const auto *pArtNetNodeEntryUniverse = &pPollTable[nIndex].Universe[nUniverse]; + nLength += get_port(pArtNetNodeEntryUniverse, &pOutBuffer[nLength], nLength); + } + + nLength--; + nLength += static_cast(snprintf(&pOutBuffer[nLength], nOutBufferSize - nLength, "]},")); + + if (nLength <= nOutBufferSize) { + return nLength; + } + + return 0; +} + +uint32_t json_get_polltable(char *pOutBuffer, const uint32_t nOutBufferSize) { + const auto nBufferSize = nOutBufferSize - 2U; + pOutBuffer[0] = '['; + + auto nLength = 1U; + + for (uint32_t nIndex = 0; (nIndex < ArtNetController::Get()->GetPollTableEntries()) && (nLength < nOutBufferSize); nIndex++) { + const auto nSize = nBufferSize - nLength; + nLength += get_entry(nIndex, &pOutBuffer[nLength], nSize); + } + + if (nLength != 1) { + pOutBuffer[nLength - 1] = ']'; + } else { + pOutBuffer[1] = ']'; + nLength = 2; + } + + assert(nLength <= nOutBufferSize); + return nLength; +} +} // namespace controller +} // namespace artnet +} // namespace remoteconfig diff --git a/lib-artnet/src/node/4/artnetnode.cpp b/lib-artnet/src/node/4/artnetnode.cpp index 4e04c7eb..2b6e6471 100755 --- a/lib-artnet/src/node/4/artnetnode.cpp +++ b/lib-artnet/src/node/4/artnetnode.cpp @@ -5,7 +5,7 @@ /** * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,6 +34,7 @@ #include "artnetnode.h" #include "artnet.h" +#include "artnetstore.h" #include "e131bridge.h" @@ -57,11 +58,8 @@ void ArtNetNode::SetPortProtocol4(const uint32_t nPortIndex, const artnet::PortP m_OutputPort[nPortIndex].GoodOutput &= static_cast(~artnet::GoodOutput::OUTPUT_IS_SACN); } - if (m_State.status == artnetnode::Status::ON) { - if (m_pArtNetStore != nullptr) { - m_pArtNetStore->SavePortProtocol(nPortIndex, portProtocol); - } - + if (m_State.status == artnet::Status::ON) { + ArtNetStore::SavePortProtocol(nPortIndex, portProtocol); artnet::display_port_protocol(nPortIndex, portProtocol); } diff --git a/lib-artnet/src/node/artnetmsgconst.cpp b/lib-artnet/src/node/artnetmsgconst.cpp index f697afc5..7e07038b 100644 --- a/lib-artnet/src/node/artnetmsgconst.cpp +++ b/lib-artnet/src/node/artnetmsgconst.cpp @@ -2,10 +2,7 @@ * @file artnetmsgconst.cpp * */ -/** - * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. - */ -/* Copyright (C) 2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,9 +25,6 @@ #include "artnetmsgconst.h" -const char ArtNetMsgConst::PARAMS[] = "Configuring Art-Net"; const char ArtNetMsgConst::START[] = "Starting Art-Net"; const char ArtNetMsgConst::STARTED[] = "Art-Net started"; const char ArtNetMsgConst::RDM_RUN[] = "Running RDM Discovery"; - - diff --git a/lib-artnet/src/node/artnetnode.cpp b/lib-artnet/src/node/artnetnode.cpp old mode 100644 new mode 100755 index 983b39d2..13f84124 --- a/lib-artnet/src/node/artnetnode.cpp +++ b/lib-artnet/src/node/artnetnode.cpp @@ -5,7 +5,7 @@ /** * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. */ -/* Copyright (C) 2016-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2016-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,6 +34,7 @@ #include "artnetnode.h" #include "artnetconst.h" #include "artnet.h" +#include "artnetstore.h" #if defined (ARTNET_HAVE_DMXIN) # include "dmx.h" @@ -43,6 +44,13 @@ # include "e131.h" #endif +#if defined (ARTNET_SHOWFILE) +namespace showfile { +void record(const struct artnet::ArtDmx *pArtDmx, const uint32_t nMillis); +void record(const struct artnet::ArtSync *pArtSync, const uint32_t nMillis); +} // namespace showfile +#endif + #include "lightset.h" #include "lightsetdata.h" @@ -82,6 +90,12 @@ ArtNetNode::ArtNetNode() { m_ArtPollReply.AcnPriority = e131::priority::DEFAULT; #endif + memset(&m_State, 0, sizeof(struct artnetnode::State)); + m_State.reportCode = artnet::ReportCode::RCPOWEROK; + m_State.status = artnet::Status::STANDBY; + // The device should wait for a random delay of up to 1s before sending the reply. + m_State.ArtPollReplyDelayMillis = (m_ArtPollReply.MAC[5] | (static_cast(m_ArtPollReply.MAC[4]) << 8)) % 1000; + SetLongName(nullptr); // Set default long name memset(&m_Node, 0, sizeof(struct artnetnode::Node)); @@ -95,17 +109,11 @@ ArtNetNode::ArtNetNode() { SetShortName(nPortIndex, nullptr); // Set default port label } - memset(&m_State, 0, sizeof(struct artnetnode::State)); - m_State.reportCode = artnetnode::ReportCode::RCPOWEROK; - m_State.status = artnetnode::Status::STANDBY; - // The device should wait for a random delay of up to 1s before sending the reply. - m_State.ArtPollReplyDelayMillis = (m_ArtPollReply.MAC[5] | (static_cast(m_ArtPollReply.MAC[4]) << 8)) % 1000; - for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { memset(&m_OutputPort[nPortIndex], 0, sizeof(struct artnetnode::OutputPort)); m_OutputPort[nPortIndex].SourceA.nPhysical = 0x100; m_OutputPort[nPortIndex].SourceB.nPhysical = 0x100; - m_OutputPort[nPortIndex].GoodOutputB = artnet::GoodOutputB::RDM_DISABLED; + m_OutputPort[nPortIndex].GoodOutputB = artnet::GoodOutputB::RDM_DISABLED | artnet::GoodOutputB::DISCOVERY_NOT_RUNNING; memset(&m_InputPort[nPortIndex], 0, sizeof(struct artnetnode::InputPort)); m_InputPort[nPortIndex].nDestinationIp = Network::Get()->GetBroadcastIp(); } @@ -167,7 +175,7 @@ void ArtNetNode::Start() { m_ArtPollReply.Status2 &= static_cast(~artnet::Status2::DHCP_CAPABLE); m_ArtPollReply.Status2 |= Network::Get()->IsDhcpCapable() ? artnet::Status2::DHCP_CAPABLE : static_cast(0); - #if defined (ENABLE_HTTPD) && defined (ENABLE_CONTENT) +#if defined (ENABLE_HTTPD) && defined (ENABLE_CONTENT) m_ArtPollReply.Status2 |= artnet::Status2::WEB_BROWSER_SUPPORT; #endif #if defined (OUTPUT_HAVE_STYLESWITCH) @@ -179,7 +187,7 @@ void ArtNetNode::Start() { /* * Status 3 */ - m_ArtPollReply.Status3 = artnet::Status3::NETWORKLOSS_LAST_STATE | artnet::Status3::FAILSAFE_CONTROL; + m_ArtPollReply.Status3 = artnet::Status3::NETWORKLOSS_LAST_STATE | artnet::Status3::FAILSAFE_CONTROL | artnet::Status3::SUPPORTS_BACKGROUNDDISCOVERY; #if defined (ARTNET_HAVE_DMXIN) m_ArtPollReply.Status3 |= artnet::Status3::OUTPUT_SWITCH; #endif @@ -211,15 +219,11 @@ void ArtNetNode::Start() { } #endif -#if defined (RDM_CONTROLLER) || defined (RDM_RESPONDER) - if (m_pArtNetRdm != nullptr) { - for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { - const auto isRdmDisabled = ((m_OutputPort[nPortIndex].GoodOutputB & artnet::GoodOutputB::RDM_DISABLED) == artnet::GoodOutputB::RDM_DISABLED); - - if (!isRdmDisabled && (m_Node.Port[nPortIndex].direction == lightset::PortDir::OUTPUT)) { - SendTod(nPortIndex); - } +#if defined (RDM_CONTROLLER) + if (m_State.rdm.IsEnabled) { + m_State.rdm.IsDiscoveryRunning = true; + for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { if (m_Node.Port[nPortIndex].direction == lightset::PortDir::INPUT) { SendTodRequest(nPortIndex); } @@ -228,10 +232,10 @@ void ArtNetNode::Start() { #endif #if (ARTNET_VERSION >= 4) - E131Bridge::Start(); + E131Bridge::Start(); #endif - m_State.status = artnetnode::Status::ON; + m_State.status = artnet::Status::ON; Hardware::Get()->SetMode(hardware::ledblink::Mode::NORMAL); DEBUG_EXIT @@ -266,7 +270,7 @@ void ArtNetNode::Stop() { hal::panel_led_off(hal::panelled::ARTNET); m_ArtPollReply.Status1 = static_cast((m_ArtPollReply.Status1 & ~artnet::Status1::INDICATOR_MASK) | artnet::Status1::INDICATOR_MUTE_MODE); - m_State.status = artnetnode::Status::STANDBY; + m_State.status = artnet::Status::STANDBY; DEBUG_EXIT } @@ -284,10 +288,8 @@ void ArtNetNode::SetShortName(const uint32_t nPortIndex, const char *pShortName) m_Node.Port[nPortIndex].ShortName[artnet::SHORT_NAME_LENGTH - 1] = '\0'; - if (m_State.status == artnetnode::Status::ON) { - if (m_pArtNetStore != nullptr) { - m_pArtNetStore->SaveShortName(nPortIndex, m_Node.Port[nPortIndex].ShortName); - } + if (m_State.status == artnet::Status::ON) { + ArtNetStore::SaveShortName(nPortIndex, m_Node.Port[nPortIndex].ShortName); } DEBUG_PUTS(m_Node.Port[nPortIndex].ShortName); @@ -299,7 +301,7 @@ void ArtNetNode::GetLongNameDefault(char *pLongName) { uint8_t nBoardNameLength; const auto *const pBoardName = Hardware::Get()->GetBoardName(nBoardNameLength); const auto *const pWebsiteUrl = Hardware::Get()->GetWebsiteUrl(); - snprintf(pLongName, artnet::LONG_NAME_LENGTH - 1, "%s %s %d %s", pBoardName, artnet::NODE_ID, artnet::VERSION, pWebsiteUrl); + snprintf(pLongName, artnet::LONG_NAME_LENGTH - 1, "%s %s %u %s", pBoardName, artnet::NODE_ID, static_cast(artnet::VERSION), pWebsiteUrl); #else uint32_t i; @@ -326,11 +328,8 @@ void ArtNetNode::SetLongName(const char *pLongName) { m_ArtPollReply.LongName[artnet::LONG_NAME_LENGTH - 1] = '\0'; - if (m_State.status == artnetnode::Status::ON) { - if (m_pArtNetStore != nullptr) { - m_pArtNetStore->SaveLongName(reinterpret_cast(m_ArtPollReply.LongName)); - } - + if (m_State.status == artnet::Status::ON) { + ArtNetStore::SaveLongName(reinterpret_cast(m_ArtPollReply.LongName)); artnet::display_longname(reinterpret_cast(m_ArtPollReply.LongName)); } @@ -338,6 +337,41 @@ void ArtNetNode::SetLongName(const char *pLongName) { DEBUG_EXIT } +#if defined (OUTPUT_HAVE_STYLESWITCH) +void ArtNetNode::SetOutputStyle(const uint32_t nPortIndex, lightset::OutputStyle outputStyle) { + assert(nPortIndex < artnetnode::MAX_PORTS); + + if ((outputStyle == GetOutputStyle(nPortIndex)) && (m_State.status == artnet::Status::ON)) { + return; + } + + if (m_pLightSet != nullptr) { + m_pLightSet->SetOutputStyle(nPortIndex, outputStyle); + outputStyle = m_pLightSet->GetOutputStyle(nPortIndex); + } + + if (outputStyle == lightset::OutputStyle::CONSTANT) { + m_OutputPort[nPortIndex].GoodOutputB |= artnet::GoodOutputB::STYLE_CONSTANT; + } else { + m_OutputPort[nPortIndex].GoodOutputB &= static_cast(~artnet::GoodOutputB::STYLE_CONSTANT); + } + + m_State.IsSynchronousMode = false; + + if (m_State.status == artnet::Status::ON) { + ArtNetStore::SaveOutputStyle(nPortIndex, outputStyle); + artnet::display_outputstyle(nPortIndex, outputStyle); + } +} + +lightset::OutputStyle ArtNetNode::GetOutputStyle(const uint32_t nPortIndex) const { + assert(nPortIndex < artnetnode::MAX_PORTS); + + const auto isStyleConstant = (m_OutputPort[nPortIndex].GoodOutputB & artnet::GoodOutputB::STYLE_CONSTANT) == artnet::GoodOutputB::STYLE_CONSTANT; + return isStyleConstant ? lightset::OutputStyle::CONSTANT : lightset::OutputStyle::DELTA; +} +#endif + void ArtNetNode::SetNetworkDataLossCondition() { m_State.IsMergeMode = false; m_State.IsSynchronousMode = false; @@ -411,7 +445,7 @@ static artnet::OpCodes get_op_code(const uint32_t nBytesReceived, const uint8_t return artnet::OpCodes::OP_NOT_DEFINED; } -void ArtNetNode::Process(const uint16_t nBytesReceived) { +void ArtNetNode::Process(const uint32_t nBytesReceived) { if (__builtin_expect((nBytesReceived == 0), 1)) { const auto nDeltaMillis = m_nCurrentPacketMillis - m_nPreviousPacketMillis; @@ -429,7 +463,7 @@ void ArtNetNode::Process(const uint16_t nBytesReceived) { #endif #if defined (RDM_CONTROLLER) - if (m_pArtNetRdm != nullptr) { + if (m_State.rdm.IsEnabled) { HandleRdmIn(); } #endif @@ -478,6 +512,11 @@ void ArtNetNode::Process(const uint16_t nBytesReceived) { if (m_pLightSet != nullptr) { HandleDmx(); m_State.ArtDmxIpAddress = m_nIpAddressFrom; +#if defined (ARTNET_SHOWFILE) + if (m_State.DoRecord) { + showfile::record(reinterpret_cast(m_pReceiveBuffer), m_nCurrentPacketMillis); + } +#endif } break; case artnet::OpCodes::OP_SYNC: @@ -496,6 +535,11 @@ void ArtNetNode::Process(const uint16_t nBytesReceived) { m_State.ArtSyncMillis = Hardware::Get()->Millis(); HandleSync(); } +#if defined (ARTNET_SHOWFILE) + if (m_State.DoRecord) { + showfile::record(reinterpret_cast(m_pReceiveBuffer), m_nCurrentPacketMillis); + } +#endif } break; #endif @@ -505,7 +549,8 @@ void ArtNetNode::Process(const uint16_t nBytesReceived) { #if defined (ARTNET_HAVE_TIMECODE) case artnet::OpCodes::OP_TIMECODE: if (m_pArtNetTimeCode != nullptr) { - HandleTimeCode(); + const auto *const pArtTimeCode = reinterpret_cast(m_pReceiveBuffer); + m_pArtNetTimeCode->Handler(reinterpret_cast(&pArtTimeCode->Frames)); } break; #endif @@ -514,25 +559,30 @@ void ArtNetNode::Process(const uint16_t nBytesReceived) { break; #if defined (RDM_CONTROLLER) || defined (RDM_RESPONDER) case artnet::OpCodes::OP_TODREQUEST: - if (m_pArtNetRdm != nullptr) { + if (m_State.rdm.IsEnabled) { HandleTodRequest(); } break; case artnet::OpCodes::OP_TODDATA: - if (m_pArtNetRdm != nullptr) { + if (m_State.rdm.IsEnabled) { HandleTodData(); } break; case artnet::OpCodes::OP_TODCONTROL: - if (m_pArtNetRdm != nullptr) { + if (m_State.rdm.IsEnabled) { HandleTodControl(); } break; case artnet::OpCodes::OP_RDM: - if (m_pArtNetRdm != nullptr) { + if (m_State.rdm.IsEnabled) { HandleRdm(); } break; + case artnet::OpCodes::OP_RDMSUB: + if (m_State.rdm.IsEnabled) { + HandleRdmSub(); + } + break; #endif case artnet::OpCodes::OP_IPPROG: HandleIpProg(); @@ -561,7 +611,7 @@ void ArtNetNode::Process(const uint16_t nBytesReceived) { #endif #if defined (RDM_CONTROLLER) - if (m_pArtNetRdm != nullptr) { + if (m_State.rdm.IsEnabled) { HandleRdmIn(); } #endif diff --git a/lib-artnet/src/node/artnetnodehandleaddress.cpp b/lib-artnet/src/node/artnetnodehandleaddress.cpp index e1d0b3c7..24d98326 100644 --- a/lib-artnet/src/node/artnetnodehandleaddress.cpp +++ b/lib-artnet/src/node/artnetnodehandleaddress.cpp @@ -5,7 +5,7 @@ /** * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,6 +33,7 @@ #include "artnetnode.h" #include "artnetconst.h" #include "artnetnode_internal.h" +#include "artnetstore.h" #include "lightsetdata.h" #include "hardware.h" @@ -86,10 +87,6 @@ void ArtNetNode::SetLocalMerging() { DEBUG_EXIT } -uint16_t ArtNetNode::MakePortAddress(const uint16_t nUniverse, const uint32_t nPage) { - return artnet::make_port_address(m_Node.Port[nPage].NetSwitch, m_Node.Port[nPage].SubSwitch, nUniverse); -} - void ArtNetNode::SetUniverse(const uint32_t nPortIndex, const lightset::PortDir dir, const uint16_t nUniverse) { assert(nPortIndex < artnetnode::MAX_PORTS); @@ -162,11 +159,8 @@ void ArtNetNode::SetUniverseSwitch(const uint32_t nPortIndex, const lightset::Po SetUniverse4(nPortIndex, dir); #endif - if (m_State.status == artnetnode::Status::ON) { - if (m_pArtNetStore != nullptr) { - m_pArtNetStore->SaveUniverseSwitch(nPortIndex, nAddress); - } - + if (m_State.status == artnet::Status::ON) { + ArtNetStore::SaveUniverseSwitch(nPortIndex, nAddress); artnet::display_universe_switch(nPortIndex, nAddress); #if defined (ARTNET_HAVE_DMXIN) @@ -184,8 +178,8 @@ void ArtNetNode::SetSubnetSwitch(const uint32_t nPortIndex, const uint8_t nSubne m_Node.Port[nPortIndex].SubSwitch = nSubnetSwitch; m_Node.Port[nPortIndex].PortAddress = MakePortAddress(m_Node.Port[nPortIndex].PortAddress, nPortIndex); - if ((m_pArtNetStore != nullptr) && (m_State.status == artnetnode::Status::ON)) { - m_pArtNetStore->SaveSubnetSwitch(nPortIndex, nSubnetSwitch); + if (m_State.status == artnet::Status::ON) { + ArtNetStore::SaveSubnetSwitch(nPortIndex, nSubnetSwitch); } DEBUG_EXIT @@ -198,8 +192,8 @@ void ArtNetNode::SetNetSwitch(const uint32_t nPortIndex, const uint8_t nNetSwitc m_Node.Port[nPortIndex].NetSwitch = nNetSwitch; m_Node.Port[nPortIndex].PortAddress = MakePortAddress(m_Node.Port[nPortIndex].PortAddress, nPortIndex); - if ((m_pArtNetStore != nullptr) && (m_State.status == artnetnode::Status::ON)) { - m_pArtNetStore->SaveNetSwitch(nPortIndex, nNetSwitch); + if (m_State.status == artnet::Status::ON) { + ArtNetStore::SaveNetSwitch(nPortIndex, nNetSwitch); } DEBUG_EXIT @@ -218,11 +212,8 @@ void ArtNetNode::SetMergeMode(const uint32_t nPortIndex, const lightset::MergeMo E131Bridge::SetMergeMode(nPortIndex, mergeMode); #endif - if (m_State.status == artnetnode::Status::ON) { - if (m_pArtNetStore != nullptr) { - m_pArtNetStore->SaveMergeMode(nPortIndex, mergeMode); - } - + if (m_State.status == artnet::Status::ON) { + ArtNetStore::SaveMergeMode(nPortIndex, mergeMode); artnet::display_merge_mode(nPortIndex, mergeMode); } } @@ -231,7 +222,7 @@ void ArtNetNode::SetFailSafe(const artnetnode::FailSafe failsafe) { DEBUG_PRINTF("failsafe=%u", static_cast(failsafe)); #if defined(ARTNET_HAVE_FAILSAFE_RECORD) - if ((m_State.status == artnetnode::Status::ON) && (failsafe == artnetnode::FailSafe::RECORD)) { + if ((m_State.status == artnet::Status::ON) && (failsafe == artnetnode::FailSafe::RECORD)) { FailSafeRecord(); return; } @@ -275,13 +266,9 @@ void ArtNetNode::SetFailSafe(const artnetnode::FailSafe failsafe) { E131Bridge::SetFailSafe(static_cast(static_cast(failsafe) & 0x3)); #endif - if (m_State.status == artnetnode::Status::ON) { + if (m_State.status == artnet::Status::ON) { const auto nFailSafe = static_cast(static_cast(failsafe) & 0x3); - - if (m_pArtNetStore != nullptr) { - m_pArtNetStore->SaveFailSafe(nFailSafe); - } - + ArtNetStore::SaveFailSafe(nFailSafe); artnet::display_failsafe(nFailSafe); } @@ -290,7 +277,7 @@ void ArtNetNode::SetFailSafe(const artnetnode::FailSafe failsafe) { void ArtNetNode::HandleAddress() { const auto *const pArtAddress = reinterpret_cast(m_pReceiveBuffer); - m_State.reportCode = artnetnode::ReportCode::RCPOWEROK; + m_State.reportCode = artnet::ReportCode::RCPOWEROK; const auto nPage = static_cast(pArtAddress->BindIndex > 0 ? pArtAddress->BindIndex - 1 : 0); @@ -298,12 +285,12 @@ void ArtNetNode::HandleAddress() { if (pArtAddress->ShortName[0] != 0) { SetShortName(nPage, reinterpret_cast(pArtAddress->ShortName)); - m_State.reportCode = artnetnode::ReportCode::RCSHNAMEOK; + m_State.reportCode = artnet::ReportCode::RCSHNAMEOK; } if (pArtAddress->LongName[0] != 0) { SetLongName(reinterpret_cast(pArtAddress->LongName)); - m_State.reportCode = artnetnode::ReportCode::RCLONAMEOK; + m_State.reportCode = artnet::ReportCode::RCLONAMEOK; } if (pArtAddress->SubSwitch == artnet::Program::DEFAULTS) { @@ -483,14 +470,14 @@ void ArtNetNode::HandleAddress() { case artnet::PortCommand::RDM_ENABLE1: case artnet::PortCommand::RDM_ENABLE2: case artnet::PortCommand::RDM_ENABLE3: - SetRmd(nPage, true); + SetRdm(nPage, true); break; case artnet::PortCommand::RDM_DISABLE0: case artnet::PortCommand::RDM_DISABLE1: case artnet::PortCommand::RDM_DISABLE2: case artnet::PortCommand::RDM_DISABLE3: - SetRmd(nPage, false); + SetRdm(nPage, false); break; #endif default: diff --git a/lib-artnet/src/node/artnetnodehandledmx.cpp b/lib-artnet/src/node/artnetnodehandledmx.cpp index 8b5546a8..c1547917 100755 --- a/lib-artnet/src/node/artnetnodehandledmx.cpp +++ b/lib-artnet/src/node/artnetnodehandledmx.cpp @@ -26,6 +26,12 @@ * THE SOFTWARE. */ +#if !defined(__clang__) +# pragma GCC push_options +# pragma GCC optimize ("O2") +# pragma GCC optimize ("no-tree-loop-distribute-patterns") +#endif + #include #include #include diff --git a/lib-artnet/src/node/artnetnodehandlepoll.cpp b/lib-artnet/src/node/artnetnodehandlepoll.cpp index 3b567f64..28360a1c 100644 --- a/lib-artnet/src/node/artnetnodehandlepoll.cpp +++ b/lib-artnet/src/node/artnetnodehandlepoll.cpp @@ -48,7 +48,7 @@ union uip { uint8_t u8[4]; } static ip; -void ArtNetNode::ProcessPollRelply(const uint32_t nPortIndex, __attribute__((unused)) uint32_t& NumPortsInput, uint32_t& NumPortsOutput) { +void ArtNetNode::ProcessPollRelply(const uint32_t nPortIndex, [[maybe_unused]] uint32_t& NumPortsInput, uint32_t& NumPortsOutput) { if (m_Node.Port[nPortIndex].direction == lightset::PortDir::OUTPUT) { #if (ARTNET_VERSION >= 4) if (m_Node.Port[nPortIndex].protocol == artnet::PortProtocol::SACN) { @@ -87,7 +87,7 @@ void ArtNetNode::ProcessPollRelply(const uint32_t nPortIndex, __attribute__((unu #endif } -void ArtNetNode::SendPollRelply(const uint32_t nBindIndex, const uint32_t nDestinationIp, artnetnode::ArtPollQueue *pQueue) { +void ArtNetNode::SendPollRelply(const uint32_t nBindIndex, const uint32_t nDestinationIp, artnet::ArtPollQueue *pQueue) { DEBUG_PRINTF("nBindIndex=%u", nBindIndex); ip.u32 = Network::Get()->GetIp(); @@ -130,7 +130,14 @@ void ArtNetNode::SendPollRelply(const uint32_t nBindIndex, const uint32_t nDesti ProcessPollRelply(nPortIndex, nPortsInput, nPortsOutput); + if (__builtin_expect((m_pLightSet != nullptr), 1)) { + const auto nRefreshRate = m_pLightSet->GetRefreshRate(); + m_ArtPollReply.RefreshRateLo = static_cast(nRefreshRate); + m_ArtPollReply.RefreshRateHi = static_cast(nRefreshRate >> 8); + } + m_ArtPollReply.NumPortsLo = static_cast(std::max(nPortsInput, nPortsOutput)); + m_State.ArtPollReplyCount++; uint8_t nSysNameLenght; diff --git a/lib-artnet/src/node/artnetnodehandlesync.cpp b/lib-artnet/src/node/artnetnodehandlesync.cpp index 39e6323f..17c5f0ff 100755 --- a/lib-artnet/src/node/artnetnodehandlesync.cpp +++ b/lib-artnet/src/node/artnetnodehandlesync.cpp @@ -41,12 +41,6 @@ void ArtNetNode::HandleSync() { if (!m_State.IsSynchronousMode) { m_State.IsSynchronousMode = true; - /* - * As the ArtSync is after the ArtDmx which are already processed - * we need to do a forced sync - */ - m_pLightSet->Sync(true); - SendDiag(artnet::PriorityCodes::DIAG_LOW, "Sync forced"); return; } diff --git a/lib-artnet/src/node/artnetnodeprint.cpp b/lib-artnet/src/node/artnetnodeprint.cpp index 116bfc79..06f617a7 100644 --- a/lib-artnet/src/node/artnetnodeprint.cpp +++ b/lib-artnet/src/node/artnetnodeprint.cpp @@ -45,8 +45,11 @@ #include "network.h" void ArtNetNode::Print() { - printf("Art-Net %d V%d.%d\n", artnet::VERSION, ArtNetConst::VERSION[0], ArtNetConst::VERSION[1]); - printf(" Long name : %s\n", reinterpret_cast(m_ArtPollReply.LongName)); + printf("Art-Net %u V%u.%u\n", + static_cast(artnet::VERSION), + static_cast(ArtNetConst::VERSION[0]), + static_cast(ArtNetConst::VERSION[1])); + printf(" Long name : %s\n", reinterpret_cast(m_ArtPollReply.LongName)); #if defined (ARTNET_HAVE_TIMECODE) printf(" TimeCode IP: " IPSTR "\n", IP2STR(m_Node.IPAddressTimeCode)); #endif @@ -58,15 +61,14 @@ void ArtNetNode::Print() { uint16_t nUniverse; if (GetPortAddress(nPortIndex, nUniverse, lightset::PortDir::OUTPUT)) { const auto mergeMode = ((m_OutputPort[nPortIndex].GoodOutput & artnet::GoodOutput::MERGE_MODE_LTP) == artnet::GoodOutput::MERGE_MODE_LTP) ? lightset::MergeMode::LTP : lightset::MergeMode::HTP; - printf(" Port %-2d %-4u %s %s", nPortIndex, nUniverse, lightset::get_merge_mode(mergeMode, true), GetRdm(0) ? "RDM" : ""); + printf(" Port %-2u %-4u %s", static_cast(nPortIndex), static_cast(nUniverse), lightset::get_merge_mode(mergeMode, true)); #if defined (OUTPUT_HAVE_STYLESWITCH) printf(" %s", lightset::get_output_style(GetOutputStyle(nPortIndex), true)); #endif #if (ARTNET_VERSION >= 4) - printf(" %s\n", artnet::get_protocol_mode(m_Node.Port[nPortIndex].protocol, true)); -#else - printf("\n"); + printf(" %s", artnet::get_protocol_mode(m_Node.Port[nPortIndex].protocol, true)); #endif + printf(" %s\n", GetRdm(nPortIndex) ? "RDM" : " "); } } } @@ -79,7 +81,7 @@ void ArtNetNode::Print() { uint16_t nUniverse; if (GetPortAddress(nPortIndex, nUniverse, lightset::PortDir::INPUT)) { - printf(" Port %-2d %-4u", nPortIndex, nUniverse); + printf(" Port %-2u %-4u", static_cast(nPortIndex), static_cast(nUniverse)); if (m_Node.Port[nPortIndex].protocol == artnet::PortProtocol::ARTNET) { const auto nDestinationIp = (m_InputPort[nPortIndex].nDestinationIp == 0 ? Network::Get()->GetBroadcastIp() : m_InputPort[nPortIndex].nDestinationIp); printf(" -> " IPSTR, IP2STR(nDestinationIp)); @@ -87,7 +89,7 @@ void ArtNetNode::Print() { #if (ARTNET_VERSION >= 4) printf(" %s\n", artnet::get_protocol_mode(m_Node.Port[nPortIndex].protocol, true)); #else - printf("\n"); + puts(""); #endif } } diff --git a/lib-artnet/src/node/artnetparams.cpp b/lib-artnet/src/node/artnetparams.cpp index 0c13dc27..65f593de 100644 --- a/lib-artnet/src/node/artnetparams.cpp +++ b/lib-artnet/src/node/artnetparams.cpp @@ -33,6 +33,7 @@ #include #include +#include #include #include #include @@ -58,6 +59,12 @@ #include "debug.h" +namespace artnetnode { +namespace configstore { +extern uint32_t DMXPORT_OFFSET; +} // namespace configstore +} // namespace artnetnode + static uint32_t s_nPortsMax; namespace artnetparams { @@ -70,7 +77,7 @@ static constexpr bool is_set(const uint16_t nValue, const uint32_t i) { using namespace artnetparams; -ArtNetParams::ArtNetParams(ArtNetParamsStore *pArtNetParamsStore): m_pArtNetParamsStore(pArtNetParamsStore) { +ArtNetParams::ArtNetParams() { DEBUG_ENTRY auto *const pArtnetNode = ArtNetNode::Get(); @@ -101,18 +108,14 @@ bool ArtNetParams::Load() { ReadConfigFile configfile(ArtNetParams::staticCallbackFunction, this); if (configfile.Read(ArtNetParamsConst::FILE_NAME)) { - // There is a configuration file - if (m_pArtNetParamsStore != nullptr) { - m_pArtNetParamsStore->Update(&m_Params); - } + ArtNetParamsStore::Update(&m_Params); } else #endif - if (m_pArtNetParamsStore != nullptr) { - m_pArtNetParamsStore->Copy(&m_Params); - } else { - return false; - } + ArtNetParamsStore::Copy(&m_Params); +#ifndef NDEBUG + Dump(); +#endif return true; } @@ -128,8 +131,11 @@ void ArtNetParams::Load(const char *pBuffer, uint32_t nLength) { config.Read(pBuffer, nLength); - assert(m_pArtNetParamsStore != nullptr); - m_pArtNetParamsStore->Update(&m_Params); + ArtNetParamsStore::Update(&m_Params); + +#ifndef NDEBUG + Dump(); +#endif DEBUG_EXIT } @@ -335,13 +341,6 @@ void ArtNetParams::callbackFunction(const char *pLine) { } } -void ArtNetParams::staticCallbackFunction(void *p, const char *s) { - assert(p != nullptr); - assert(s != nullptr); - - (static_cast(p))->callbackFunction(s); -} - void ArtNetParams::Builder(const struct Params *pParams, char *pBuffer, uint32_t nLength, uint32_t& nSize) { DEBUG_ENTRY DEBUG_PRINTF("s_nPortsMax=%u", s_nPortsMax); @@ -351,14 +350,13 @@ void ArtNetParams::Builder(const struct Params *pParams, char *pBuffer, uint32_t if (pParams != nullptr) { memcpy(&m_Params, pParams, sizeof(struct Params)); } else { - assert(m_pArtNetParamsStore != nullptr); - m_pArtNetParamsStore->Copy(&m_Params); + ArtNetParamsStore::Copy(&m_Params); } PropertiesBuilder builder(ArtNetParamsConst::FILE_NAME, pBuffer, nLength); if (!isMaskSet(Mask::LONG_NAME)) { - memcpy(m_Params.aLongName, ArtNetNode::Get()->GetLongName(), artnet::LONG_NAME_LENGTH); + ArtNetNode::Get()->GetLongNameDefault(reinterpret_cast(m_Params.aLongName)); } builder.Add(LightSetParamsConst::NODE_LONG_NAME, reinterpret_cast(m_Params.aLongName), isMaskSet(Mask::LONG_NAME)); @@ -368,6 +366,13 @@ void ArtNetParams::Builder(const struct Params *pParams, char *pBuffer, uint32_t builder.Add(LightSetParamsConst::FAILSAFE, lightset::get_failsafe(static_cast(m_Params.nFailSafe)), isMaskSet(Mask::FAILSAFE)); for (uint32_t nPortIndex = 0; nPortIndex < s_nPortsMax; nPortIndex++) { + const auto nOffset = nPortIndex + artnetnode::configstore::DMXPORT_OFFSET; + + if (nOffset >= artnetnode::MAX_PORTS) { + DEBUG_PUTS("break"); + break; + } + builder.Add(LightSetParamsConst::UNIVERSE_PORT[nPortIndex], m_Params.nUniverse[nPortIndex], isMaskSet(Mask::UNIVERSE_A << nPortIndex)); const auto portDir = portdir_get(nPortIndex); const auto isDefault = (portDir == lightset::PortDir::OUTPUT); @@ -376,8 +381,9 @@ void ArtNetParams::Builder(const struct Params *pParams, char *pBuffer, uint32_t const auto isLabelSet = isMaskSet(Mask::LABEL_A << nPortIndex); if (!isLabelSet) { - memcpy(m_Params.aLabel[nPortIndex], ArtNetNode::Get()->GetShortName(nPortIndex), artnet::SHORT_NAME_LENGTH); + memcpy(m_Params.aLabel[nPortIndex], ArtNetNode::Get()->GetShortName(nOffset), artnet::SHORT_NAME_LENGTH); } + builder.Add(LightSetParamsConst::NODE_LABEL[nPortIndex], reinterpret_cast(m_Params.aLabel[nPortIndex]), isLabelSet); } @@ -428,14 +434,14 @@ void ArtNetParams::Builder(const struct Params *pParams, char *pBuffer, uint32_t DEBUG_EXIT } -void ArtNetParams::Set(uint32_t nPortIndexOffset) { +void ArtNetParams::Set() { DEBUG_ENTRY - if (nPortIndexOffset <= artnetnode::MAX_PORTS) { - s_nPortsMax = std::min(artnet::PORTS, artnetnode::MAX_PORTS - nPortIndexOffset); + if (artnetnode::configstore::DMXPORT_OFFSET <= artnetnode::MAX_PORTS) { + s_nPortsMax = std::min(artnet::PORTS, artnetnode::MAX_PORTS - artnetnode::configstore::DMXPORT_OFFSET); } - DEBUG_PRINTF("artnetnode::MAX_PORTS=%u, nPortIndexOffset=%u, s_nPortsMax=%u", artnetnode::MAX_PORTS, nPortIndexOffset, s_nPortsMax); + DEBUG_PRINTF("artnetnode::MAX_PORTS=%u, artnetnode::configstore::DMXPORT_OFFSET=%u, s_nPortsMax=%u", artnetnode::MAX_PORTS, artnetnode::configstore::DMXPORT_OFFSET, s_nPortsMax); auto *const p = ArtNetNode::Get(); assert(p != nullptr); @@ -445,7 +451,7 @@ void ArtNetParams::Set(uint32_t nPortIndexOffset) { } for (uint32_t nPortIndex = 0; nPortIndex < s_nPortsMax; nPortIndex++) { - const auto nOffset = nPortIndex + nPortIndexOffset; + const auto nOffset = nPortIndex + artnetnode::configstore::DMXPORT_OFFSET; if (nOffset >= artnetnode::MAX_PORTS) { DEBUG_PUTS("break"); @@ -476,7 +482,7 @@ void ArtNetParams::Set(uint32_t nPortIndexOffset) { #if defined (RDM_CONTROLLER) if (artnetparams::is_set(m_Params.nRdm, nPortIndex)) { - p->SetRmd(nOffset, true); + p->SetRdm(nOffset, true); } #endif @@ -505,3 +511,67 @@ void ArtNetParams::Set(uint32_t nPortIndexOffset) { DEBUG_EXIT } + +void ArtNetParams::staticCallbackFunction(void *p, const char *s) { + assert(p != nullptr); + assert(s != nullptr); + + (static_cast(p))->callbackFunction(s); +} + +void ArtNetParams::Dump() { + printf("%s::%s \'%s\':\n", __FILE__, __FUNCTION__, ArtNetParamsConst::FILE_NAME); + + printf(" %s=%d [%s]\n", LightSetParamsConst::FAILSAFE, m_Params.nFailSafe, lightset::get_failsafe(static_cast(m_Params.nFailSafe))); + + for (uint32_t i = 0; i < artnet::PORTS; i++) { + printf(" %s=%s\n", LightSetParamsConst::NODE_LABEL[i], m_Params.aLabel[i]); + } + + printf(" %s=%s\n", LightSetParamsConst::NODE_LONG_NAME, m_Params.aLongName); + printf(" %s=1 [Yes]\n", ArtNetParamsConst::ENABLE_RDM); + + + for (uint32_t i = 0; i < artnet::PORTS; i++) { + printf(" %s=%d\n", LightSetParamsConst::UNIVERSE_PORT[i], m_Params.nUniverse[i]); + } + + for (uint32_t i = 0; i < artnet::PORTS; i++) { + printf(" %s=%s\n", LightSetParamsConst::MERGE_MODE_PORT[i], lightset::get_merge_mode(mergemode_get(i))); + } + + for (uint32_t i = 0; i < artnet::PORTS; i++) { + printf(" %s=%s\n", ArtNetParamsConst::PROTOCOL_PORT[i], artnet::get_protocol_mode(i)); + } + + for (uint32_t i = 0; i < artnet::PORTS; i++) { + const auto portDir = portdir_get(i); + printf(" %s=%u [%s]\n", LightSetParamsConst::DIRECTION[i], static_cast(portDir), lightset::get_direction(portDir)); + } + + for (uint32_t i = 0; i < artnet::PORTS; i++) { + printf(" %s=" IPSTR "\n", ArtNetParamsConst::DESTINATION_IP_PORT[i], IP2STR(m_Params.nDestinationIp[i])); + + } + + for (uint32_t i = 0; i < artnet::PORTS; i++) { + const auto nOutputStyle = static_cast(isOutputStyleSet(1U << i)); + printf(" %s=%u [%s]\n", LightSetParamsConst::OUTPUT_STYLE[i], static_cast(nOutputStyle), lightset::get_output_style(static_cast(nOutputStyle))); + } + + /** + * Art-Net 4 + */ + + printf(" %s=1 [Yes]\n", ArtNetParamsConst::MAP_UNIVERSE0); + + for (uint32_t i = 0; i < artnet::PORTS; i++) { + printf(" %s=%u\n", LightSetParamsConst::PRIORITY[i], m_Params.nPriority[i]); + } + + /** + * Extra's + */ + + printf(" %s=1 [Yes]\n", LightSetParamsConst::DISABLE_MERGE_TIMEOUT); +} diff --git a/lib-artnet/src/node/artnetparamsdump.cpp b/lib-artnet/src/node/artnetparamsdump.cpp deleted file mode 100644 index 43596554..00000000 --- a/lib-artnet/src/node/artnetparamsdump.cpp +++ /dev/null @@ -1,124 +0,0 @@ -/** - * @file artnetparamsdump.cpp - * - */ -/** - * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. - */ -/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#if !defined(__clang__) // Needed for compiling on MacOS -# pragma GCC push_options -# pragma GCC optimize ("Os") -#endif - -#include - -#include "artnetparams.h" -#include "artnetparamsconst.h" - -#include "lightsetparamsconst.h" - -#include "network.h" - -void ArtNetParams::Dump() { -#ifndef NDEBUG - printf("%s::%s \'%s\':\n", __FILE__, __FUNCTION__, ArtNetParamsConst::FILE_NAME); - - if (isMaskSet(artnetparams::Mask::FAILSAFE)) { - printf(" %s=%d [%s]\n", LightSetParamsConst::FAILSAFE, m_Params.nFailSafe, lightset::get_failsafe(static_cast(m_Params.nFailSafe))); - } - - for (uint32_t i = 0; i < artnet::PORTS; i++) { - if (isMaskSet(artnetparams::Mask::LABEL_A << i)) { - printf(" %s=%s\n", LightSetParamsConst::NODE_LABEL[i], m_Params.aLabel[i]); - } - } - - if (isMaskSet(artnetparams::Mask::LONG_NAME)) { - printf(" %s=%s\n", LightSetParamsConst::NODE_LONG_NAME, m_Params.aLongName); - } - - if (isMaskSet(artnetparams::Mask::ENABLE_RDM)) { - printf(" %s=1 [Yes]\n", ArtNetParamsConst::ENABLE_RDM); - } - - for (uint32_t i = 0; i < artnet::PORTS; i++) { - if (isMaskSet(artnetparams::Mask::UNIVERSE_A << i)) { - printf(" %s=%d\n", LightSetParamsConst::UNIVERSE_PORT[i], m_Params.nUniverse[i]); - } - } - - for (uint32_t i = 0; i < artnet::PORTS; i++) { - printf(" %s=%s\n", LightSetParamsConst::MERGE_MODE_PORT[i], lightset::get_merge_mode(mergemode_get(i))); - } - - for (uint32_t i = 0; i < artnet::PORTS; i++) { - const auto portProtocol = protocol_get(i); - const auto isDefault = (portProtocol == artnet::PortProtocol::ARTNET); - if (!isDefault) { - printf(" %s=%s\n", ArtNetParamsConst::PROTOCOL_PORT[i], artnet::get_protocol_mode(i)); - } - } - - for (uint32_t i = 0; i < artnet::PORTS; i++) { - const auto portDir = portdir_get(i); - const auto isDefault = (portDir == lightset::PortDir::OUTPUT); - if (!isDefault) { - printf(" %s=%u [%s]\n", LightSetParamsConst::DIRECTION[i], static_cast(portDir), lightset::get_direction(portDir)); - } - } - - for (uint32_t i = 0; i < artnet::PORTS; i++) { - if (isMaskSet(artnetparams::Mask::DESTINATION_IP_A << i)) { - printf(" %s=" IPSTR "\n", ArtNetParamsConst::DESTINATION_IP_PORT[i], IP2STR(m_Params.nDestinationIp[i])); - } - } - - for (uint32_t i = 0; i < artnet::PORTS; i++) { - const auto nOutputStyle = static_cast(isOutputStyleSet(1U << i)); - printf(" %s=%u [%s]\n", LightSetParamsConst::OUTPUT_STYLE[i], nOutputStyle, lightset::get_output_style(static_cast(nOutputStyle))); - } - - /** - * Art-Net 4 - */ - - if (isMaskSet(artnetparams::Mask::MAP_UNIVERSE0)) { - printf(" %s=1 [Yes]\n", ArtNetParamsConst::MAP_UNIVERSE0); - } - - for (uint32_t i = 0; i < artnet::PORTS; i++) { - if (isMaskSet(artnetparams::Mask::PRIORITY_A << i)) { - printf(" %s=%u\n", LightSetParamsConst::PRIORITY[i], m_Params.nPriority[i]); - } - } - - /** - * Extra's - */ - - if (isMaskSet(artnetparams::Mask::DISABLE_MERGE_TIMEOUT)) { - printf(" %s=1 [Yes]\n", LightSetParamsConst::DISABLE_MERGE_TIMEOUT); - } -#endif -} diff --git a/lib-artnet/src/node/dmxin/handledmxin.cpp b/lib-artnet/src/node/dmxin/handledmxin.cpp index 61a7d26f..38122538 100644 --- a/lib-artnet/src/node/dmxin/handledmxin.cpp +++ b/lib-artnet/src/node/dmxin/handledmxin.cpp @@ -5,7 +5,7 @@ /** * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,6 +26,12 @@ * THE SOFTWARE. */ +#if !defined(__clang__) +# pragma GCC push_options +# pragma GCC optimize ("O2") +# pragma GCC optimize ("no-tree-loop-distribute-patterns") +#endif + #include #include #include @@ -47,8 +53,8 @@ static uint32_t s_ReceivingMask = 0; void ArtNetNode::HandleDmxIn() { for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { if ((m_Node.Port[nPortIndex].direction == lightset::PortDir::INPUT) - && (m_Node.Port[nPortIndex].protocol == artnet::PortProtocol::ARTNET) - && ((m_InputPort[nPortIndex].GoodInput & artnet::GoodInput::DISABLED) != artnet::GoodInput::DISABLED)) { + && (m_Node.Port[nPortIndex].protocol == artnet::PortProtocol::ARTNET) + && ((m_InputPort[nPortIndex].GoodInput & artnet::GoodInput::DISABLED) != artnet::GoodInput::DISABLED)) { const auto *const pDmxData = reinterpret_cast(Dmx::Get()->GetDmxChanged(nPortIndex)); @@ -73,6 +79,8 @@ void ArtNetNode::HandleDmxIn() { Network::Get()->SendTo(m_nHandle, &m_ArtDmx, sizeof(struct artnet::ArtDmx), m_InputPort[nPortIndex].nDestinationIp, artnet::UDP_PORT); + SendDiag(artnet::PriorityCodes::DIAG_LOW, "%u: Input DMX sent", nPortIndex); + if (m_Node.Port[nPortIndex].bLocalMerge) { m_pReceiveBuffer = reinterpret_cast(&m_ArtDmx); m_nIpAddressFrom = Network::Get()->GetIp(); @@ -148,7 +156,6 @@ void ArtNetNode::HandleDmxIn() { } } } - } } } diff --git a/lib-rdmdiscovery/src/artnet/artnetrdmcontroller.cpp b/lib-artnet/src/node/rdm/controller/artnetrdmcontroller.cpp similarity index 56% rename from lib-rdmdiscovery/src/artnet/artnetrdmcontroller.cpp rename to lib-artnet/src/node/rdm/controller/artnetrdmcontroller.cpp index 5789b50f..6ecdd327 100755 --- a/lib-rdmdiscovery/src/artnet/artnetrdmcontroller.cpp +++ b/lib-artnet/src/node/rdm/controller/artnetrdmcontroller.cpp @@ -2,7 +2,7 @@ * @file artnetrdmcontroller.cpp * */ -/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,83 +23,72 @@ * THE SOFTWARE. */ +#if !defined(__clang__) +# pragma GCC push_options +# pragma GCC optimize ("O2") +# pragma GCC optimize ("no-tree-loop-distribute-patterns") +#endif + #include #include #include -#include "hardware.h" - #include "artnetnode.h" #include "artnetrdmcontroller.h" #include "rdm.h" +#include "rdmconst.h" #include "rdm_e120.h" -#include "rdmdevicecontroller.h" -#include "rdmdiscovery.h" #include "debug.h" RDMTod ArtNetRdmController::m_pRDMTod[artnetnode::MAX_PORTS]; -TRdmMessage ArtNetRdmController::s_rdmMessage; - -ArtNetRdmController::ArtNetRdmController(): RDMDiscovery(RDMDeviceController::GetUID()) { - DEBUG_ENTRY - s_rdmMessage.start_code = E120_SC_RDM; - DEBUG_EXIT -} -const uint8_t *ArtNetRdmController::Handler(uint32_t nPortIndex, const uint8_t *pRdmData) { - assert(nPortIndex < artnetnode::MAX_PORTS); - - if (pRdmData == nullptr) { - return nullptr; - } +static void respond_message_ack(const uint32_t nPortIndex, struct TRdmMessage *pRdmMessage) { + assert(pRdmMessage->start_code == E120_SC_RDM); - Hardware::Get()->WatchdogFeed(); + pRdmMessage->message_count = 0; + pRdmMessage->command_class = static_cast(pRdmMessage->command_class + 1U); + pRdmMessage->message_length = static_cast(RDM_MESSAGE_MINIMUM_SIZE + pRdmMessage->param_data_length); + pRdmMessage->slot16.response_type = E120_RESPONSE_TYPE_ACK; - while (nullptr != Rdm::Receive(nPortIndex)) { - // Discard late responses - Hardware::Get()->WatchdogFeed(); + for (uint32_t i = 0; i < RDM_UID_SIZE; i++) { + auto nUid = pRdmMessage->destination_uid[i]; + pRdmMessage->destination_uid[i] = pRdmMessage->source_uid[i]; + pRdmMessage->source_uid[i] = nUid; } - const auto *pRdmMessageNoSc = reinterpret_cast(const_cast(pRdmData)); - auto *pRdmCommand = reinterpret_cast(&s_rdmMessage); - - memcpy(&pRdmCommand[1], pRdmData, static_cast(pRdmMessageNoSc->message_length + 2)); + uint16_t nChecksum = 0; + uint32_t i; -#ifndef NDEBUG - RDMMessage::Print(pRdmCommand); -#endif + auto *pRdmData = reinterpret_cast(pRdmMessage); - Rdm::SendRaw(nPortIndex, pRdmCommand, pRdmMessageNoSc->message_length + 2U); + for (i = 0; i < pRdmMessage->message_length; i++) { + nChecksum = static_cast(nChecksum + pRdmData[i]); + } - const auto *pResponse = Rdm::ReceiveTimeOut(nPortIndex, 60000); + pRdmData[i++] = static_cast(nChecksum >> 8); + pRdmData[i++] = static_cast(nChecksum & 0XFF); -#ifndef NDEBUG - RDMMessage::Print(pResponse); -#endif - return pResponse; + Rdm::SendRawRespondMessage(nPortIndex, reinterpret_cast(pRdmMessage), i); } -bool ArtNetRdmController::RdmReceive(uint32_t nPortIndex, uint8_t *pRdmData) { +bool ArtNetRdmController::RdmReceive(const uint32_t nPortIndex, const uint8_t *pRdmData) { assert(nPortIndex < artnetnode::MAX_PORTS); assert(pRdmData != nullptr); - auto *pData = Rdm::Receive(nPortIndex); - - if (pData == nullptr) { - return false; - } - - auto *pRdmMessage = reinterpret_cast(pData); - + auto *pRdmMessage = reinterpret_cast(pRdmData); auto *pUid = pRdmMessage->destination_uid; + auto bIsRdmPacketForMe = false; auto bIsRdmPacketBroadcast = (memcmp(pUid, UID_ALL, RDM_UID_SIZE) == 0); - auto bIsRdmPacketForMe = false; if (!bIsRdmPacketBroadcast) { - bIsRdmPacketForMe = m_pRDMTod[nPortIndex].Exist(pUid); + bIsRdmPacketBroadcast = (memcmp(&pRdmMessage->destination_uid[2], UID_ALL, 4) == 0); + + if (!bIsRdmPacketBroadcast) { + bIsRdmPacketForMe = m_pRDMTod[nPortIndex].Exist(pUid); + } } if ((!bIsRdmPacketForMe) && (!bIsRdmPacketBroadcast)) { @@ -107,7 +96,6 @@ bool ArtNetRdmController::RdmReceive(uint32_t nPortIndex, uint8_t *pRdmData) { } if ((pRdmMessage->command_class == E120_GET_COMMAND) || (pRdmMessage->command_class == E120_SET_COMMAND) ) { - memcpy(pRdmData, &pData[1], pRdmMessage->message_length); return true; } @@ -121,7 +109,7 @@ bool ArtNetRdmController::RdmReceive(uint32_t nPortIndex, uint8_t *pRdmData) { if (nParamId == E120_DISC_UNIQUE_BRANCH) { if (!m_pRDMTod[nPortIndex].IsMuted()) { if ((memcmp(pRdmMessage->param_data, pUid, RDM_UID_SIZE) <= 0) && (memcmp(pUid, pRdmMessage->param_data + 6, RDM_UID_SIZE) <= 0)) { - auto *pResponse = reinterpret_cast(&s_rdmMessage); + auto *pResponse = reinterpret_cast(const_cast(pRdmData)); uint16_t nChecksum = 6 * 0xFF; @@ -157,11 +145,13 @@ bool ArtNetRdmController::RdmReceive(uint32_t nPortIndex, uint8_t *pRdmData) { if (!bIsRdmPacketBroadcast && bIsRdmPacketForMe) { m_pRDMTod[nPortIndex].UnMute(); - s_rdmMessage.param_data_length = 2; - s_rdmMessage.param_data[0] = 0x00; // Control Field - s_rdmMessage.param_data[1] = 0x00; // Control Field + auto *pRdmMessage = reinterpret_cast(const_cast(pRdmData)); + + pRdmMessage->param_data_length = 2; + pRdmMessage->param_data[0] = 0x00; // Control Field + pRdmMessage->param_data[1] = 0x00; // Control Field - RespondMessageAck(nPortIndex, pUid, pRdmMessage); + respond_message_ack(nPortIndex, pRdmMessage); } else { m_pRDMTod[nPortIndex].UnMuteAll(); } @@ -178,11 +168,13 @@ bool ArtNetRdmController::RdmReceive(uint32_t nPortIndex, uint8_t *pRdmData) { if (bIsRdmPacketForMe) { m_pRDMTod[nPortIndex].Mute(); - s_rdmMessage.param_data_length = 2; - s_rdmMessage.param_data[0] = 0x00; // Control Field - s_rdmMessage.param_data[1] = 0x00; // Control Field + auto *pRdmMessage = reinterpret_cast(const_cast(pRdmData)); - RespondMessageAck(nPortIndex, pUid, pRdmMessage);; + pRdmMessage->param_data_length = 2; + pRdmMessage->param_data[0] = 0x00; // Control Field + pRdmMessage->param_data[1] = 0x00; // Control Field + + respond_message_ack(nPortIndex, pRdmMessage);; return false; } } @@ -190,38 +182,3 @@ bool ArtNetRdmController::RdmReceive(uint32_t nPortIndex, uint8_t *pRdmData) { return false; } - -void ArtNetRdmController::RespondMessageAck(uint32_t nPortIndex, const uint8_t *pUid, const struct TRdmMessage *pRdmMessage) { - s_rdmMessage.start_code = E120_SC_RDM; - s_rdmMessage.sub_start_code = pRdmMessage->sub_start_code; - s_rdmMessage.transaction_number = pRdmMessage->transaction_number; - s_rdmMessage.message_count = 0; - s_rdmMessage.sub_device[0] = pRdmMessage->sub_device[0]; - s_rdmMessage.sub_device[1] = pRdmMessage->sub_device[1]; - s_rdmMessage.command_class = static_cast(pRdmMessage->command_class + 1); - s_rdmMessage.param_id[0] = pRdmMessage->param_id[0]; - s_rdmMessage.param_id[1] = pRdmMessage->param_id[1]; - s_rdmMessage.message_length = static_cast(RDM_MESSAGE_MINIMUM_SIZE + s_rdmMessage.param_data_length); - s_rdmMessage.slot16.response_type = E120_RESPONSE_TYPE_ACK; - - for (uint32_t i = 0; i < RDM_UID_SIZE; i++) { - s_rdmMessage.destination_uid[i] = pRdmMessage->source_uid[i]; - s_rdmMessage.source_uid[i] = pUid[i]; - } - - auto *pResponse = reinterpret_cast(&s_rdmMessage); - - uint16_t nChecksum = 0; - uint32_t i; - - for (i = 0; i < s_rdmMessage.message_length; i++) { - nChecksum = static_cast(nChecksum + pResponse[i]); - } - - pResponse[i++] = static_cast(nChecksum >> 8); - pResponse[i] = static_cast(nChecksum & 0XFF); - - const auto nLength = static_cast(s_rdmMessage.message_length + RDM_MESSAGE_CHECKSUM_SIZE); - - Rdm::SendRawRespondMessage(nPortIndex, pResponse, nLength); -} diff --git a/lib-artnet/src/node/rdm/controller/handlerdm.cpp b/lib-artnet/src/node/rdm/controller/handlerdm.cpp new file mode 100755 index 00000000..a1d76007 --- /dev/null +++ b/lib-artnet/src/node/rdm/controller/handlerdm.cpp @@ -0,0 +1,265 @@ +/** + * @file handlerdm.cpp + * + */ +/** + * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. + */ +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include + +#include "artnetnode.h" +#include "rdm.h" +#include "network.h" +#include "panel_led.h" + +#include "debug.h" + +/** + * ArtTodControl is used to for an Output Gateway to flush its ToD and commence full discovery. + * If the Output Gateway has physical DMX512 ports, discovery could take minutes. + */ +void ArtNetNode::HandleTodControl() { + DEBUG_ENTRY + + const auto *const pArtTodControl = reinterpret_cast(m_pReceiveBuffer); + + if (pArtTodControl->Command == artnet::TodControlCommand::ATC_NONE) { + DEBUG_EXIT + return; + } + + const auto portAddress = static_cast((pArtTodControl->Net << 8)) | static_cast((pArtTodControl->Address)); + + for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { + if (portAddress != m_Node.Port[nPortIndex].PortAddress) { + continue; + } + + if ((m_Node.Port[nPortIndex].direction == lightset::PortDir::OUTPUT) && + ((m_OutputPort[nPortIndex].GoodOutputB & artnet::GoodOutputB::RDM_DISABLED) != artnet::GoodOutputB::RDM_DISABLED)) { + switch (pArtTodControl->Command) { + case artnet::TodControlCommand::ATC_FLUSH: + m_pArtNetRdmController->Full(nPortIndex); + m_OutputPort[nPortIndex].GoodOutputB &= static_cast(~artnet::GoodOutputB::DISCOVERY_NOT_RUNNING); + break; + case artnet::TodControlCommand::ATC_END: + m_pArtNetRdmController->Stop(nPortIndex); + m_OutputPort[nPortIndex].GoodOutputB |= artnet::GoodOutputB::DISCOVERY_NOT_RUNNING; + break; + case artnet::TodControlCommand::ATC_INCON: + m_OutputPort[nPortIndex].GoodOutputB &= static_cast(~artnet::GoodOutputB::DISCOVERY_DISABLED); + break; + case artnet::TodControlCommand::ATC_INCOFF: + m_OutputPort[nPortIndex].GoodOutputB |= artnet::GoodOutputB::DISCOVERY_DISABLED; + break; + default: + break; + } + } else if (m_Node.Port[nPortIndex].direction == lightset::PortDir::INPUT) { + if (pArtTodControl->Command == artnet::TodControlCommand::ATC_FLUSH) { + m_pArtNetRdmController->TodReset(nPortIndex); + } + } + } + + DEBUG_EXIT +} + +void ArtNetNode::HandleTodData() { + DEBUG_ENTRY + + const auto *const pArtTodData = reinterpret_cast(m_pReceiveBuffer); + + if (pArtTodData->RdmVer != 0x01) { + DEBUG_EXIT + return; + } + + const auto portAddress = static_cast((pArtTodData->Net << 8)) | static_cast((pArtTodData->Address)); + + for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { + if (m_Node.Port[nPortIndex].direction != lightset::PortDir::INPUT) { + continue; + } + + if (m_Node.Port[nPortIndex].PortAddress == portAddress) { + DEBUG_PRINTF("nPortIndex=%u, portAddress=%u, pArtTodData->UidCount=%u",nPortIndex, portAddress, pArtTodData->UidCount); + + for (uint32_t nUidIndex = 0; nUidIndex < pArtTodData->UidCount; nUidIndex++) { + const uint8_t *pUid = pArtTodData->Tod[nUidIndex]; + m_pArtNetRdmController->TodAddUid(nPortIndex, pUid); + } + } + } + + DEBUG_EXIT +} + +/** + * Output Gateway always Directed Broadcasts this packet. + */ +void ArtNetNode::SendTod(uint32_t nPortIndex) { + DEBUG_ENTRY + DEBUG_PRINTF("nPortIndex=%u", nPortIndex); + assert(nPortIndex < artnetnode::MAX_PORTS); + + auto *pTodData = &m_ArtTodPacket.ArtTodData; + const auto nPage = nPortIndex; + + memcpy(pTodData->Id, artnet::NODE_ID, sizeof(pTodData->Id)); + pTodData->OpCode = static_cast(artnet::OpCodes::OP_TODDATA); + pTodData->ProtVerHi = 0; + pTodData->ProtVerLo = artnet::PROTOCOL_REVISION; + pTodData->RdmVer = 0x01; // Devices that support RDM STANDARD V1.0 set field to 0x01. + + const auto nDiscovered = static_cast(m_pArtNetRdmController->GetUidCount(nPortIndex)); + + /** + * Physical Port = (BindIndex-1) * ArtPollReply- >NumPortsLo + ArtTodData->Port + * As most modern Art-Net gateways implement one universe per ArtPollReply, + * ArtTodData->Port will usually be set to a value of 1. + */ + pTodData->Port = static_cast(1U + (nPortIndex & 0x3)); + pTodData->Spare1 = 0; + pTodData->Spare2 = 0; + pTodData->Spare3 = 0; + pTodData->Spare4 = 0; + pTodData->Spare5 = 0; + pTodData->Spare6 = 0; + pTodData->BindIndex = static_cast(nPage + 1U); ///< ArtPollReplyData->BindIndex == ArtTodData- >BindIndex + pTodData->Net = m_Node.Port[nPage].NetSwitch; + pTodData->CommandResponse = 0; ///< The packet contains the entire TOD or is the first packet in a sequence of packets that contains the entire TOD. + pTodData->Address = m_Node.Port[nPortIndex].DefaultAddress; + pTodData->UidTotalHi = 0; + pTodData->UidTotalLo = nDiscovered; + pTodData->BlockCount = 0; + pTodData->UidCount = nDiscovered; + + m_pArtNetRdmController->TodCopy(nPortIndex, reinterpret_cast(pTodData->Tod)); + + const auto nLength = sizeof(struct artnet::ArtTodData) - (sizeof(pTodData->Tod)) + (nDiscovered * 6U); + + Network::Get()->SendTo(m_nHandle, pTodData, static_cast(nLength), Network::Get()->GetBroadcastIp(), artnet::UDP_PORT); + + DEBUG_EXIT +} + +void ArtNetNode::SendTodRequest(uint32_t nPortIndex) { + DEBUG_ENTRY + assert(nPortIndex < artnetnode::MAX_PORTS); + + m_pArtNetRdmController->TodReset(nPortIndex); + + auto *pTodRequest = &m_ArtTodPacket.ArtTodRequest; + const auto nPage = nPortIndex; + + memcpy(pTodRequest->Id, artnet::NODE_ID, sizeof(pTodRequest->Id)); + pTodRequest->OpCode = static_cast(artnet::OpCodes::OP_TODREQUEST); + pTodRequest->ProtVerHi = 0; + pTodRequest->ProtVerLo = artnet::PROTOCOL_REVISION; + pTodRequest->Spare1 = 0; + pTodRequest->Spare2 = 0; + pTodRequest->Spare3 = 0; + pTodRequest->Spare4 = 0; + pTodRequest->Spare5 = 0; + pTodRequest->Spare6 = 0; + pTodRequest->Spare7 = 0; + pTodRequest->Net = m_Node.Port[nPage].NetSwitch; + pTodRequest->Command = 0; + pTodRequest->AddCount = 1; + pTodRequest->Address[0] = m_Node.Port[nPortIndex].DefaultAddress; + + const auto nLength = sizeof(struct artnet::ArtTodRequest) - (sizeof(pTodRequest->Address)) + pTodRequest->AddCount; + + Network::Get()->SendTo(m_nHandle, pTodRequest, static_cast(nLength), Network::Get()->GetBroadcastIp(), artnet::UDP_PORT); + + DEBUG_EXIT +} + +void ArtNetNode::HandleRdm() { + auto *const pArtRdm = reinterpret_cast(m_pReceiveBuffer); + + if (pArtRdm->RdmVer != 0x01) { + DEBUG_EXIT + return; + } + + const auto portAddress = static_cast((pArtRdm->Net << 8)) | static_cast((pArtRdm->Address)); + + for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { + if (m_Node.Port[nPortIndex].PortAddress != portAddress) { + continue; + } + + if ((m_Node.Port[nPortIndex].direction == lightset::PortDir::OUTPUT) && + ((m_OutputPort[nPortIndex].GoodOutputB & artnet::GoodOutputB::RDM_DISABLED) != artnet::GoodOutputB::RDM_DISABLED)) { +# if (ARTNET_VERSION >= 4) + if (m_Node.Port[nPortIndex].protocol == artnet::PortProtocol::SACN) { + constexpr auto nMask = artnet::GoodOutput::OUTPUT_IS_MERGING | artnet::GoodOutput::DATA_IS_BEING_TRANSMITTED | artnet::GoodOutput::OUTPUT_IS_SACN; + m_OutputPort[nPortIndex].IsTransmitting = (GetGoodOutput4(nPortIndex) & nMask) != 0; + } +# endif + if (m_OutputPort[nPortIndex].IsTransmitting) { + m_OutputPort[nPortIndex].IsTransmitting = false; + m_pLightSet->Stop(nPortIndex); // Stop DMX if was running + } + + m_OutputPort[nPortIndex].nIpRdm = m_nIpAddressFrom; + + auto *pRdmMessage = reinterpret_cast(&pArtRdm->Address); + + pArtRdm->Address = E120_SC_RDM; + Rdm::SendRaw(nPortIndex, &pArtRdm->Address, pRdmMessage->message_length + RDM_MESSAGE_CHECKSUM_SIZE); + +#ifndef NDEBUG + rdm::message_print(reinterpret_cast(pRdmMessage)); +#endif + +#if defined(CONFIG_PANELLED_RDM_PORT) + hal::panel_led_on(hal::panelled::PORT_A_RDM << nPortIndex); +#elif defined(CONFIG_PANELLED_RDM_NO_PORT) + hal::panel_led_on(hal::panelled::RDM << nPortIndex); +#endif + } else if (m_Node.Port[nPortIndex].direction == lightset::PortDir::INPUT) { + auto *pRdmMessage = reinterpret_cast(&pArtRdm->Address); + + if ((pRdmMessage->command_class == E120_GET_COMMAND_RESPONSE) || (pRdmMessage->command_class == E120_SET_COMMAND_RESPONSE)) { + pArtRdm->Address = E120_SC_RDM; + Rdm::SendRaw(nPortIndex, reinterpret_cast(pRdmMessage), pRdmMessage->message_length + RDM_MESSAGE_CHECKSUM_SIZE); + +#ifndef NDEBUG + rdm::message_print(reinterpret_cast(pRdmMessage)); +#endif + } + +#if defined(CONFIG_PANELLED_RDM_PORT) + hal::panel_led_on(hal::panelled::PORT_A_RDM << nPortIndex); +#elif defined(CONFIG_PANELLED_RDM_NO_PORT) + hal::panel_led_on(hal::panelled::RDM << nPortIndex); +#endif + } + } +} diff --git a/lib-artnet/src/node/rdm/controller/handlerdmin.cpp b/lib-artnet/src/node/rdm/controller/handlerdmin.cpp new file mode 100644 index 00000000..89ec7229 --- /dev/null +++ b/lib-artnet/src/node/rdm/controller/handlerdmin.cpp @@ -0,0 +1,106 @@ +/** + * @file handlerdmin.cpp + * + */ +/** + * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. + */ +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#if !defined(__clang__) +# pragma GCC push_options +# pragma GCC optimize ("O2") +# pragma GCC optimize ("no-tree-loop-distribute-patterns") +#endif + +#include +#include +#include + +#include "artnetnode.h" +#include "artnet.h" +#include "artnetrdmcontroller.h" + +#include "rdm.h" +#include "network.h" +#include "hardware.h" +#include "panel_led.h" + +#include "debug.h" + +void ArtNetNode::HandleRdmIn() { + for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { + auto *const pArtRdm = &m_ArtTodPacket.ArtRdm; + + if (m_Node.Port[nPortIndex].direction == lightset::PortDir::INPUT) { + const auto *pRdmData = Rdm::Receive(nPortIndex); + if (pRdmData != nullptr) { + if (m_pArtNetRdmController->RdmReceive(nPortIndex, pRdmData)) { + pArtRdm->OpCode = static_cast(artnet::OpCodes::OP_RDM); + pArtRdm->RdmVer = 0x01; + pArtRdm->Net = m_Node.Port[nPortIndex].NetSwitch; + pArtRdm->Command = 0; + pArtRdm->Address = m_Node.Port[nPortIndex].DefaultAddress; + + auto *pMessage = reinterpret_cast(pRdmData); + memcpy(pArtRdm->RdmPacket, &pRdmData[1], pMessage->message_length + 1U); + + const auto *pRdmMessage = reinterpret_cast(pArtRdm->RdmPacket); + + Network::Get()->SendTo(m_nHandle, pArtRdm, ((sizeof(struct artnet::ArtRdm)) - 256) + pRdmMessage->message_length + 1 , m_InputPort[nPortIndex].nDestinationIp, artnet::UDP_PORT); + +#if defined(CONFIG_PANELLED_RDM_PORT) + hal::panel_led_on(hal::panelled::PORT_A_RDM << nPortIndex); +#elif defined(CONFIG_PANELLED_RDM_NO_PORT) + hal::panel_led_on(hal::panelled::RDM << nPortIndex); +#endif + } + } + } else if (m_Node.Port[nPortIndex].direction == lightset::PortDir::OUTPUT) { + if (m_OutputPort[nPortIndex].nIpRdm != 0) { + const auto *pRdmData = Rdm::Receive(nPortIndex); + if (pRdmData != nullptr) { + pArtRdm->OpCode = static_cast(artnet::OpCodes::OP_RDM); + pArtRdm->RdmVer = 0x01; + pArtRdm->Net = m_Node.Port[nPortIndex].NetSwitch; + pArtRdm->Command = 0; + pArtRdm->Address = m_Node.Port[nPortIndex].DefaultAddress; + + auto *pMessage = reinterpret_cast(pRdmData); + memcpy(pArtRdm->RdmPacket, &pRdmData[1], pMessage->message_length + 1U); + + const auto *pRdmMessage = reinterpret_cast(pArtRdm->RdmPacket); + + Network::Get()->SendTo(m_nHandle, pArtRdm, ((sizeof(struct artnet::ArtRdm)) - 256) + pRdmMessage->message_length + 1 , m_OutputPort[nPortIndex].nIpRdm, artnet::UDP_PORT); + + m_OutputPort[nPortIndex].nIpRdm = 0; + +#if defined(CONFIG_PANELLED_RDM_PORT) + hal::panel_led_on(hal::panelled::PORT_A_RDM << nPortIndex); +#elif defined(CONFIG_PANELLED_RDM_NO_PORT) + hal::panel_led_on(hal::panelled::RDM << nPortIndex); +#endif + } + } + } + } +} diff --git a/lib-rdmsubdevice/src/rdmsubdevicesadd.cpp b/lib-artnet/src/node/rdm/controller/handlerdmsub.cpp old mode 100644 new mode 100755 similarity index 73% rename from lib-rdmsubdevice/src/rdmsubdevicesadd.cpp rename to lib-artnet/src/node/rdm/controller/handlerdmsub.cpp index 797add9d..bd59d845 --- a/lib-rdmsubdevice/src/rdmsubdevicesadd.cpp +++ b/lib-artnet/src/node/rdm/controller/handlerdmsub.cpp @@ -1,8 +1,11 @@ /** - * @file rdmsubdevicesadd.cpp + * @file handlerdmsub.cpp * */ -/* Copyright (C) 2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/** + * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. + */ +/* Copyright (C) 2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,29 +26,27 @@ * THE SOFTWARE. */ +#include +#include #include -#include "rdmsubdevices.h" +#include "artnetnode.h" + +#include "network.h" + +#include "panel_led.h" #include "debug.h" -bool RDMSubDevices::Add(RDMSubDevice *pRDMSubDevice) { +void ArtNetNode::HandleRdmSub() { DEBUG_ENTRY - assert(m_pRDMSubDevice != nullptr); + auto *const pArtRdmSub = reinterpret_cast(m_pReceiveBuffer); - if (m_pRDMSubDevice == nullptr) { - return false; - } - - if (m_nCount == rdm::subdevices::MAX) { + if (pArtRdmSub->RdmVer != 0x01) { DEBUG_EXIT - return false; + return; } - assert(pRDMSubDevice != nullptr); - m_pRDMSubDevice[m_nCount++] = pRDMSubDevice; - DEBUG_EXIT - return true; } diff --git a/lib-artnet/src/node/rdm/controller/json_get_portstatus.cpp b/lib-artnet/src/node/rdm/controller/json_get_portstatus.cpp new file mode 100755 index 00000000..446a96a7 --- /dev/null +++ b/lib-artnet/src/node/rdm/controller/json_get_portstatus.cpp @@ -0,0 +1,89 @@ +/** + * @file json_get_portstatus.cpp + * + */ +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "artnetnode.h" +#include "lightset.h" + +namespace remoteconfig { +namespace rdm { +static uint32_t get_portstatus(const uint32_t nPortIndex, char *pOutBuffer, const uint32_t nOutBufferSize) { + const auto direction = ArtNetNode::Get()->GetPortDirection(nPortIndex); + const char *status; + + if (direction == lightset::PortDir::OUTPUT) { + if (ArtNetNode::Get()->GetRdm(nPortIndex)) { + if (ArtNetNode::Get()->GetRdmDiscovery(nPortIndex)) { + bool bIsIncremental; + if (ArtNetNode::Get()->RdmIsRunning(nPortIndex, bIsIncremental)) { + status = bIsIncremental ? "Incremental" : "Full"; + } else { + status = "Idle"; + } + } else { + status = "Disabled"; + } + } else { + return 0; + } + } else if (direction == lightset::PortDir::INPUT) { + if (ArtNetNode::Get()->RdmGetUidCount(nPortIndex) != 0) { + status = "TOD"; + } else { + return 0; + } + } else { + return 0; + } + + auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, + "{\"port\":\"%c\",\"direction\":\"%s\",\"status\":\"%s\"},", + static_cast('A' + nPortIndex), + lightset::get_direction(direction), + status)); + + return nLength; +} + +uint32_t json_get_portstatus(char *pOutBuffer, const uint32_t nOutBufferSize) { + pOutBuffer[0] = '['; + uint32_t nLength = 1; + + for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { + nLength += get_portstatus(nPortIndex, &pOutBuffer[nLength], nOutBufferSize - nLength); + } + + if (nLength == 1) { + nLength++; + } + + pOutBuffer[nLength - 1] = ']'; + + return nLength; +} +} // namespace rdm +} // namespace remoteconfig diff --git a/lib-rdmnet/src/rdmnetdevice.cpp b/lib-artnet/src/node/rdm/controller/json_get_queue.cpp old mode 100644 new mode 100755 similarity index 63% rename from lib-rdmnet/src/rdmnetdevice.cpp rename to lib-artnet/src/node/rdm/controller/json_get_queue.cpp index 60ef49c1..caa1122d --- a/lib-rdmnet/src/rdmnetdevice.cpp +++ b/lib-artnet/src/node/rdm/controller/json_get_queue.cpp @@ -1,8 +1,8 @@ /** - * @file rdmnetdevice.cpp + * @file json_get_queue.cpp * */ -/* Copyright (C) 2019-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -25,29 +25,25 @@ #include #include -#include +#include -#include "rdmnetdevice.h" +#include "artnetnode.h" -#include "llrpdevice.h" -#include "rdmpersonality.h" -#include "lightset.h" -#include "rdmdeviceresponder.h" -#include "rdmhandler.h" +namespace remoteconfig { +namespace rdm { +uint32_t json_get_queue(char *pOutBuffer, const uint32_t nOutBufferSize) { + const auto nBufferSize = nOutBufferSize - 2U; + auto nLength = static_cast(snprintf(pOutBuffer, nBufferSize, "{\"uid\":[" )); -static constexpr auto UUID_STRING_LENGTH = 36; + nLength += ArtNetNode::Get()->RdmCopyWorkingQueue(&pOutBuffer[nLength], nBufferSize - nLength); -TRdmMessage RDMNetDevice::s_RdmCommand; -uint8_t RDMNetDevice::s_Cid[e131::CID_LENGTH]; + pOutBuffer[nLength++] = ']'; + pOutBuffer[nLength++] = '}'; -void RDMNetDevice::Print() { - char uuid_str[UUID_STRING_LENGTH + 1]; - uuid_str[UUID_STRING_LENGTH] = '\0'; - uuid_unparse(s_Cid, uuid_str); + assert(nLength <= nOutBufferSize); + return nLength; +} +} // namespace rdm +} // namespace remoteconfig - printf("RDMNet\n"); - printf(" CID : %s\n", uuid_str); - LLRPDevice::Print(); - RDMDeviceResponder::Print(); -} diff --git a/lib-artnet/src/node/rdm/controller/json_get_rdm.cpp b/lib-artnet/src/node/rdm/controller/json_get_rdm.cpp new file mode 100755 index 00000000..06931c49 --- /dev/null +++ b/lib-artnet/src/node/rdm/controller/json_get_rdm.cpp @@ -0,0 +1,38 @@ +/** + * @file json_get_rdm.cpp + * + */ +/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "artnetnode.h" + +namespace remoteconfig { +namespace rdm { +uint32_t json_get_rdm(char *pOutBuffer, const uint32_t nOutBufferSize) { + auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, "{\"rdm\":\"%u\"}", ArtNetNode::Get()->GetRdm())); + return nLength; +} +} // namespace rdm +} // namespace remoteconfig diff --git a/lib-dmx/src/rdm.cpp b/lib-artnet/src/node/rdm/controller/json_get_tod.cpp old mode 100644 new mode 100755 similarity index 57% rename from lib-dmx/src/rdm.cpp rename to lib-artnet/src/node/rdm/controller/json_get_tod.cpp index 914cd716..5c19dde3 --- a/lib-dmx/src/rdm.cpp +++ b/lib-artnet/src/node/rdm/controller/json_get_tod.cpp @@ -1,8 +1,8 @@ /** - * @file rdm.cpp + * @file json_get_tod.cpp * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -24,34 +24,30 @@ */ #include +#include #include -#include "rdm.h" -#include "dmx.h" +#include "artnetnode.h" -#include "hardware.h" +namespace remoteconfig { +namespace rdm { +uint32_t json_get_tod(const char cPort, char *pOutBuffer, const uint32_t nOutBufferSize) { + const uint32_t nPortIndex = (cPort | 0x20) - 'a'; -#include "debug.h" + if (nPortIndex < artnetnode::MAX_PORTS) { + const auto nBufferSize = nOutBufferSize - 2U; + auto nLength = static_cast(snprintf(pOutBuffer, nBufferSize, "{\"port\":\"%c\",\"tod\":[" , static_cast(nPortIndex + 'A'))); -const uint8_t *Rdm::Receive(uint32_t nPortIndex) { - return Dmx::Get()->RdmReceive(nPortIndex); -} - -const uint8_t *Rdm::ReceiveTimeOut(uint32_t nPortIndex, uint16_t nTimeOut) { - return Dmx::Get()->RdmReceiveTimeOut(nPortIndex, nTimeOut); -} - -void Rdm::SendRaw(uint32_t nPortIndex, const uint8_t *pRdmData, uint32_t nLength) { - assert(pRdmData != nullptr); - assert(nLength != 0); - - DEBUG_PRINTF("nPortIndex=%u", nPortIndex); - - Dmx::Get()->SetPortDirection(nPortIndex, dmx::PortDirection::OUTP, false); + nLength += ArtNetNode::Get()->RdmCopyTod(nPortIndex, &pOutBuffer[nLength], nBufferSize - nLength); - Dmx::Get()->RdmSendRaw(nPortIndex, pRdmData, nLength); + pOutBuffer[nLength++] = ']'; + pOutBuffer[nLength++] = '}'; - udelay(RDM_RESPONDER_DATA_DIRECTION_DELAY); + assert(nLength <= nOutBufferSize); + return nLength; + } - Dmx::Get()->SetPortDirection(nPortIndex, dmx::PortDirection::INP, true); + return 0; } +} // namespace rdm +} // namespace remoteconfig diff --git a/lib-artnet/src/node/rdm/controller/setrdm.cpp b/lib-artnet/src/node/rdm/controller/setrdm.cpp new file mode 100755 index 00000000..48a78720 --- /dev/null +++ b/lib-artnet/src/node/rdm/controller/setrdm.cpp @@ -0,0 +1,56 @@ +/** + * @file setrdm.cpp + * + */ +/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#include "artnetnode.h" +#include "artnetrdmcontroller.h" + +#include "debug.h" + +void ArtNetNode::SetRdm(const bool doEnable) { + DEBUG_ENTRY + + SetRdmController(m_pArtNetRdmController, doEnable); + + DEBUG_EXIT +} + +void ArtNetNode::SetRdmController(ArtNetRdmController *pArtNetRdmController, const bool doEnable) { + DEBUG_ENTRY + + m_pArtNetRdmController = pArtNetRdmController; + m_State.rdm.IsEnabled = ((pArtNetRdmController != nullptr) & doEnable); + + if (m_State.rdm.IsEnabled) { + m_ArtPollReply.Status1 |= artnet::Status1::RDM_CAPABLE; + m_State.rdm.IsDiscoveryRunning = true; + } else { + m_ArtPollReply.Status1 &= static_cast(~artnet::Status1::RDM_CAPABLE); + } + + DEBUG_PRINTF("m_State.rdm.IsEnabled=%c", m_State.rdm.IsEnabled ? 'Y' : 'N'); + DEBUG_EXIT +} diff --git a/lib-artnet/src/node/rdm/handlerdm.cpp b/lib-artnet/src/node/rdm/handlerdm.cpp index 2f9af34a..7e875370 100755 --- a/lib-artnet/src/node/rdm/handlerdm.cpp +++ b/lib-artnet/src/node/rdm/handlerdm.cpp @@ -1,11 +1,8 @@ /** - * @file handlerdm.h + * @file handlerdm.cpp * */ -/** - * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. - */ -/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,86 +23,12 @@ * THE SOFTWARE. */ -#include -#include -#include +#include #include "artnetnode.h" -#include "artnetrdm.h" - -#include "network.h" #include "debug.h" -void ArtNetNode::SetRmd(const uint32_t nPortIndex, const bool bEnable) { - DEBUG_ENTRY - assert(nPortIndex < artnetnode::MAX_PORTS); - - const auto isEnabled = !((m_OutputPort[nPortIndex].GoodOutputB & artnet::GoodOutputB::RDM_DISABLED) == artnet::GoodOutputB::RDM_DISABLED); - - if (isEnabled == bEnable) { - DEBUG_EXIT - return; - } - - if (!bEnable) { - m_OutputPort[nPortIndex].GoodOutputB |= artnet::GoodOutputB::RDM_DISABLED; - } else { - m_OutputPort[nPortIndex].GoodOutputB &= static_cast(~artnet::GoodOutputB::RDM_DISABLED); - } - - if (m_State.status == artnetnode::Status::ON) { - if (m_pArtNetStore != nullptr) { - m_pArtNetStore->SaveRdmEnabled(nPortIndex, bEnable); - } - - artnet::display_rdm_enabled(nPortIndex, bEnable); - } - - - DEBUG_EXIT -} - -//TODO Make RDM discovery a state-machine. - -/** - * ArtTodControl is used to for an Output Gateway to flush its ToD and commence full discovery. - * If the Output Gateway has physical DMX512 ports, discovery could take minutes. - */ -void ArtNetNode::HandleTodControl() { - DEBUG_ENTRY - - const auto *const pArtTodControl = reinterpret_cast(m_pReceiveBuffer); - const auto portAddress = static_cast((pArtTodControl->Net << 8)) | static_cast((pArtTodControl->Address)); - - for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { - if ((m_OutputPort[nPortIndex].GoodOutputB & artnet::GoodOutputB::RDM_DISABLED) == artnet::GoodOutputB::RDM_DISABLED) { - DEBUG_EXIT - continue; - } - - if ((portAddress == m_Node.Port[nPortIndex].PortAddress) - && (m_Node.Port[nPortIndex].direction == lightset::PortDir::OUTPUT)) { - - if (m_OutputPort[nPortIndex].IsTransmitting && (!m_Node.IsRdmResponder)) { - m_pLightSet->Stop(nPortIndex); - } - - if (pArtTodControl->Command == 0x01) { // AtcFlush - m_pArtNetRdm->Full(nPortIndex); - } - - SendTod(nPortIndex); - - if (m_OutputPort[nPortIndex].IsTransmitting && (!m_Node.IsRdmResponder)) { - m_pLightSet->Start(nPortIndex); - } - } - } - - DEBUG_EXIT -} - /** * An Output Gateway must not interpret receipt of an ArtTodRequest * as an instruction to perform full RDM Discovery on the DMX512 physical layer; @@ -125,8 +48,7 @@ void ArtNetNode::HandleTodRequest() { continue; } - if ((portAddress == m_Node.Port[nPortIndex].PortAddress) - && (m_Node.Port[nPortIndex].direction == lightset::PortDir::OUTPUT)) { + if ((portAddress == m_Node.Port[nPortIndex].PortAddress) && (m_Node.Port[nPortIndex].direction == lightset::PortDir::OUTPUT)) { SendTod(nPortIndex); } } @@ -134,195 +56,3 @@ void ArtNetNode::HandleTodRequest() { DEBUG_EXIT } - -void ArtNetNode::HandleTodData() { - DEBUG_ENTRY - - const auto *const pArtTodData = reinterpret_cast(m_pReceiveBuffer); - - if (pArtTodData->RdmVer != 0x01) { - DEBUG_EXIT - return; - } - - const auto portAddress = static_cast((pArtTodData->Net << 8)) | static_cast((pArtTodData->Address)); - - for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { - if (m_Node.Port[nPortIndex].direction != lightset::PortDir::INPUT) { - continue; - } - - if (m_Node.Port[nPortIndex].PortAddress == portAddress) { - DEBUG_PRINTF("nPortIndex=%u, portAddress=%u, pArtTodData->UidCount=%u",nPortIndex, portAddress, pArtTodData->UidCount); - - for (uint32_t nUidIndex = 0; nUidIndex < pArtTodData->UidCount; nUidIndex++) { - const uint8_t *pUid = pArtTodData->Tod[nUidIndex]; - m_pArtNetRdm->TodAddUid(nPortIndex, pUid); - } - } - } - - DEBUG_EXIT -} - -/** - * Output Gateway always Directed Broadcasts this packet. - */ -void ArtNetNode::SendTod(uint32_t nPortIndex) { - DEBUG_ENTRY - DEBUG_PRINTF("nPortIndex=%u", nPortIndex); - assert(nPortIndex < artnetnode::MAX_PORTS); - - auto *pTodData = &m_ArtTodPacket.ArtTodData; - const auto nPage = nPortIndex; - - memcpy(pTodData->Id, artnet::NODE_ID, sizeof(pTodData->Id)); - pTodData->OpCode = static_cast(artnet::OpCodes::OP_TODDATA); - pTodData->ProtVerHi = 0; - pTodData->ProtVerLo = artnet::PROTOCOL_REVISION; - pTodData->RdmVer = 0x01; // Devices that support RDM STANDARD V1.0 set field to 0x01. - - const auto nDiscovered = static_cast(m_pArtNetRdm->GetUidCount(nPortIndex)); - - /** - * Physical Port = (BindIndex-1) * ArtPollReply- >NumPortsLo + ArtTodData->Port - * As most modern Art-Net gateways implement one universe per ArtPollReply, - * ArtTodData->Port will usually be set to a value of 1. - */ - pTodData->Port = static_cast(1U + (nPortIndex & 0x3)); - pTodData->Spare1 = 0; - pTodData->Spare2 = 0; - pTodData->Spare3 = 0; - pTodData->Spare4 = 0; - pTodData->Spare5 = 0; - pTodData->Spare6 = 0; - pTodData->BindIndex = static_cast(nPage + 1U); ///< ArtPollReplyData->BindIndex == ArtTodData- >BindIndex - pTodData->Net = m_Node.Port[nPage].NetSwitch; - pTodData->CommandResponse = 0; ///< The packet contains the entire TOD or is the first packet in a sequence of packets that contains the entire TOD. - pTodData->Address = m_Node.Port[nPortIndex].DefaultAddress; - pTodData->UidTotalHi = 0; - pTodData->UidTotalLo = nDiscovered; - pTodData->BlockCount = 0; - pTodData->UidCount = nDiscovered; - - m_pArtNetRdm->TodCopy(nPortIndex, reinterpret_cast(pTodData->Tod)); - - const auto nLength = sizeof(struct artnet::ArtTodData) - (sizeof(pTodData->Tod)) + (nDiscovered * 6U); - - Network::Get()->SendTo(m_nHandle, pTodData, static_cast(nLength), Network::Get()->GetBroadcastIp(), artnet::UDP_PORT); - - DEBUG_EXIT -} - -void ArtNetNode::SendTodRequest(uint32_t nPortIndex) { - DEBUG_ENTRY - assert(nPortIndex < artnetnode::MAX_PORTS); - - m_pArtNetRdm->TodReset(nPortIndex); - - auto *pTodRequest = &m_ArtTodPacket.ArtTodRequest; - const auto nPage = nPortIndex; - - memcpy(pTodRequest->Id, artnet::NODE_ID, sizeof(pTodRequest->Id)); - pTodRequest->OpCode = static_cast(artnet::OpCodes::OP_TODREQUEST); - pTodRequest->ProtVerHi = 0; - pTodRequest->ProtVerLo = artnet::PROTOCOL_REVISION; - pTodRequest->Spare1 = 0; - pTodRequest->Spare2 = 0; - pTodRequest->Spare3 = 0; - pTodRequest->Spare4 = 0; - pTodRequest->Spare5 = 0; - pTodRequest->Spare6 = 0; - pTodRequest->Spare7 = 0; - pTodRequest->Net = m_Node.Port[nPage].NetSwitch; - pTodRequest->Command = 0; - pTodRequest->AddCount = 1; - pTodRequest->Address[0] = m_Node.Port[nPortIndex].DefaultAddress; - - const auto nLength = sizeof(struct artnet::ArtTodRequest) - (sizeof(pTodRequest->Address)) + pTodRequest->AddCount; - - Network::Get()->SendTo(m_nHandle, pTodRequest, static_cast(nLength), Network::Get()->GetBroadcastIp(), artnet::UDP_PORT); - - DEBUG_EXIT -} - -void ArtNetNode::SetRdmHandler(ArtNetRdm *pArtNetTRdm, bool IsResponder) { - DEBUG_ENTRY - - m_pArtNetRdm = pArtNetTRdm; - - if (m_pArtNetRdm != nullptr) { - m_Node.IsRdmResponder = IsResponder; - m_ArtPollReply.Status1 |= artnet::Status1::RDM_CAPABLE; - } else { - m_ArtPollReply.Status1 &= static_cast(~artnet::Status1::RDM_CAPABLE); - } - - DEBUG_EXIT -} - -void ArtNetNode::HandleRdm() { - auto *const pArtRdm = reinterpret_cast(m_pReceiveBuffer); - - if (pArtRdm->RdmVer != 0x01) { - DEBUG_EXIT - return; - } - - const auto portAddress = static_cast((pArtRdm->Net << 8)) | static_cast((pArtRdm->Address)); - - // Output ports - for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { - if ((m_OutputPort[nPortIndex].GoodOutputB & artnet::GoodOutputB::RDM_DISABLED) == artnet::GoodOutputB::RDM_DISABLED) { - continue; - } - - if ((portAddress == m_Node.Port[nPortIndex].PortAddress) && (m_Node.Port[nPortIndex].direction == lightset::PortDir::OUTPUT)) { -#if defined (RDM_CONTROLLER) -# if (ARTNET_VERSION >= 4) - if (m_Node.Port[nPortIndex].protocol == artnet::PortProtocol::SACN) { - constexpr auto nMask = artnet::GoodOutput::OUTPUT_IS_MERGING | artnet::GoodOutput::DATA_IS_BEING_TRANSMITTED | artnet::GoodOutput::OUTPUT_IS_SACN; - m_OutputPort[nPortIndex].IsTransmitting = (GetGoodOutput4(nPortIndex) & nMask) != 0; - } -# endif - if (m_OutputPort[nPortIndex].IsTransmitting) { - m_pLightSet->Stop(nPortIndex); // Stop DMX if was running - } -#endif - const auto *pRdmResponse = const_cast(m_pArtNetRdm->Handler(nPortIndex, pArtRdm->RdmPacket)); - - if (pRdmResponse != nullptr) { - pArtRdm->RdmVer = 0x01; - - const auto nMessageLength = static_cast(pRdmResponse[2] + 1); - memcpy(pArtRdm->RdmPacket, &pRdmResponse[1], nMessageLength); - - const auto nLength = sizeof(struct artnet::ArtRdm) - sizeof(pArtRdm->RdmPacket) + nMessageLength; - - Network::Get()->SendTo(m_nHandle, m_pReceiveBuffer, static_cast(nLength), m_nIpAddressFrom, artnet::UDP_PORT); - } else { - DEBUG_PUTS("No RDM response"); - } - -#if defined (RDM_CONTROLLER) - if (m_OutputPort[nPortIndex].IsTransmitting) { - m_pLightSet->Start(nPortIndex); // Start DMX if was running - } -#endif - } - } - -#if defined (RDM_CONTROLLER) - // Input ports - for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { - if ((m_Node.Port[nPortIndex].direction != lightset::PortDir::INPUT)) { - continue; - } - - if (m_Node.Port[nPortIndex].PortAddress == portAddress) { - DEBUG_PRINTF("nPortIndex=%u, portAddress=%u", nPortIndex, portAddress); - artnet::rdm_send(nPortIndex, pArtRdm->RdmPacket); - } - } -#endif -} diff --git a/lib-artnet/src/node/rdm/handlerdmin.cpp b/lib-artnet/src/node/rdm/handlerdmin.cpp deleted file mode 100644 index 200af546..00000000 --- a/lib-artnet/src/node/rdm/handlerdmin.cpp +++ /dev/null @@ -1,67 +0,0 @@ -/** - * @file handlerdmin.cpp - * - */ -/** - * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. - */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#include - -#include "artnetnode.h" -#include "artnet.h" -#include "artnetrdm.h" - -#include "network.h" -#include "hardware.h" - -#include "panel_led.h" - -#include "debug.h" - -void ArtNetNode::HandleRdmIn() { - auto *const pArtRdm = &m_ArtTodPacket.ArtRdm; - - for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { - if ((m_Node.Port[nPortIndex].direction != lightset::PortDir::INPUT)) { - continue; - } - - const auto nPage = nPortIndex; - - if (m_pArtNetRdm->RdmReceive(nPortIndex, pArtRdm->RdmPacket)) { - memcpy(pArtRdm->Id, artnet::NODE_ID, sizeof(pArtRdm->Id)); - pArtRdm->OpCode = static_cast(artnet::OpCodes::OP_RDM); - pArtRdm->ProtVerHi = 0; - pArtRdm->ProtVerLo = artnet::PROTOCOL_REVISION; - pArtRdm->RdmVer = 0x01; - pArtRdm->Net = m_Node.Port[nPage].NetSwitch; - pArtRdm->Command = 0; - pArtRdm->Address = m_Node.Port[nPortIndex].DefaultAddress; - - Network::Get()->SendTo(m_nHandle, pArtRdm, sizeof(struct artnet::ArtRdm), m_InputPort[nPortIndex].nDestinationIp, artnet::UDP_PORT); - } - } -} diff --git a/lib-network/src/net/ntp_internal.h b/lib-artnet/src/node/rdm/responder/artnetrdmresponder.cpp similarity index 84% rename from lib-network/src/net/ntp_internal.h rename to lib-artnet/src/node/rdm/responder/artnetrdmresponder.cpp index 328dafab..a831f94e 100644 --- a/lib-network/src/net/ntp_internal.h +++ b/lib-artnet/src/node/rdm/responder/artnetrdmresponder.cpp @@ -1,8 +1,8 @@ /** - * @file ntp_internal.h + * @file artnetrdmresponder.cpp * */ -/* Copyright (C) 2019-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,11 +23,6 @@ * THE SOFTWARE. */ -#ifndef NTP_INTERNAL_H_ -#define NTP_INTERNAL_H_ +#include "artnetrdmresponder.h" -enum { - NTP_PORT_SERVER = 123 -}; - -#endif /* NTP_INTERNAL_H_ */ +TRdmMessage ArtNetRdmResponder::s_RdmCommand; diff --git a/lib-artnet/src/node/rdm/responder/handlerdm.cpp b/lib-artnet/src/node/rdm/responder/handlerdm.cpp new file mode 100755 index 00000000..8398b921 --- /dev/null +++ b/lib-artnet/src/node/rdm/responder/handlerdm.cpp @@ -0,0 +1,147 @@ +/** + * @file handlerdm.h + * + */ +/** + * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. + */ +/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include + +#include "artnetnode.h" +#include "artnetrdmresponder.h" + +#include "debug.h" + +void ArtNetNode::HandleRdm() { + auto *const pArtRdm = reinterpret_cast(m_pReceiveBuffer); + + if (pArtRdm->RdmVer != 0x01) { + DEBUG_EXIT + return; + } + + const auto portAddress = static_cast((pArtRdm->Net << 8)) | static_cast((pArtRdm->Address)); + + for (uint32_t nPortIndex = 0; nPortIndex < artnetnode::MAX_PORTS; nPortIndex++) { + if ((m_OutputPort[nPortIndex].GoodOutputB & artnet::GoodOutputB::RDM_DISABLED) == artnet::GoodOutputB::RDM_DISABLED) { + continue; + } + + if ((portAddress == m_Node.Port[nPortIndex].PortAddress) && (m_Node.Port[nPortIndex].direction == lightset::PortDir::OUTPUT)) { + const auto *pRdmResponse = const_cast(m_pArtNetRdmResponder->Handler(nPortIndex, pArtRdm->RdmPacket)); + + if (pRdmResponse != nullptr) { + pArtRdm->RdmVer = 0x01; + + const auto nMessageLength = static_cast(pRdmResponse[2] + 1); + memcpy(pArtRdm->RdmPacket, &pRdmResponse[1], nMessageLength); + + const auto nLength = sizeof(struct artnet::ArtRdm) - sizeof(pArtRdm->RdmPacket) + nMessageLength; + + Network::Get()->SendTo(m_nHandle, m_pReceiveBuffer, nLength, m_nIpAddressFrom, artnet::UDP_PORT); + } else { + DEBUG_PUTS("No RDM response"); + } + } + } +} + +void ArtNetNode::HandleTodControl() { + DEBUG_ENTRY + + const auto *const pArtTodControl = reinterpret_cast(m_pReceiveBuffer); + const auto portAddress = static_cast((pArtTodControl->Net << 8)) | static_cast((pArtTodControl->Address)); + + const uint32_t nPortIndex = 0; + + if ((m_OutputPort[nPortIndex].GoodOutputB & artnet::GoodOutputB::RDM_DISABLED) == artnet::GoodOutputB::RDM_DISABLED) { + DEBUG_EXIT + return; + } + + if ((portAddress == m_Node.Port[nPortIndex].PortAddress) && (m_Node.Port[nPortIndex].direction == lightset::PortDir::OUTPUT)) { + if (pArtTodControl->Command == 0x01) { // AtcFlush + SendTod(nPortIndex); + } + } + + DEBUG_EXIT +} + +/** + * Output Gateway always Directed Broadcasts this packet. + */ +void ArtNetNode::SendTod(uint32_t nPortIndex) { + DEBUG_ENTRY + DEBUG_PRINTF("nPortIndex=%u", nPortIndex); + assert(nPortIndex < artnetnode::MAX_PORTS); + + auto *pTodData = &m_ArtTodPacket.ArtTodData; + const auto nPage = nPortIndex; + + memcpy(pTodData->Id, artnet::NODE_ID, sizeof(pTodData->Id)); + pTodData->OpCode = static_cast(artnet::OpCodes::OP_TODDATA); + pTodData->ProtVerHi = 0; + pTodData->ProtVerLo = artnet::PROTOCOL_REVISION; + pTodData->RdmVer = 0x01; // Devices that support RDM STANDARD V1.0 set field to 0x01. + + const auto nDiscovered = static_cast(nPortIndex == 0 ? 1 : 0); + + /** + * Physical Port = (BindIndex-1) * ArtPollReply- >NumPortsLo + ArtTodData->Port + * As most modern Art-Net gateways implement one universe per ArtPollReply, + * ArtTodData->Port will usually be set to a value of 1. + */ + pTodData->Port = static_cast(1U + (nPortIndex & 0x3)); + pTodData->Spare1 = 0; + pTodData->Spare2 = 0; + pTodData->Spare3 = 0; + pTodData->Spare4 = 0; + pTodData->Spare5 = 0; + pTodData->Spare6 = 0; + pTodData->BindIndex = static_cast(nPage + 1U); ///< ArtPollReplyData->BindIndex == ArtTodData- >BindIndex + pTodData->Net = m_Node.Port[nPage].NetSwitch; + pTodData->CommandResponse = 0; ///< The packet contains the entire TOD or is the first packet in a sequence of packets that contains the entire TOD. + pTodData->Address = m_Node.Port[nPortIndex].DefaultAddress; + pTodData->UidTotalHi = 0; + pTodData->UidTotalLo = nDiscovered; + pTodData->BlockCount = 0; + pTodData->UidCount = nDiscovered; + + m_pArtNetRdmResponder->TodCopy(nPortIndex, reinterpret_cast(pTodData->Tod)); + + const auto nLength = sizeof(struct artnet::ArtTodData) - (sizeof(pTodData->Tod)) + (nDiscovered * 6U); + + Network::Get()->SendTo(m_nHandle, pTodData, nLength, Network::Get()->GetBroadcastIp(), artnet::UDP_PORT); + + DEBUG_EXIT +} + +void ArtNetNode::HandleTodData() { + DEBUG_ENTRY + + DEBUG_EXIT +} diff --git a/lib-hal/console/null/console.c b/lib-artnet/src/node/rdm/responder/handlerdmsub.cpp similarity index 72% rename from lib-hal/console/null/console.c rename to lib-artnet/src/node/rdm/responder/handlerdmsub.cpp index 49df7118..bd59d845 100755 --- a/lib-hal/console/null/console.c +++ b/lib-artnet/src/node/rdm/responder/handlerdmsub.cpp @@ -1,7 +1,10 @@ /** - * @file console.c + * @file handlerdmsub.cpp * */ +/** + * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. + */ /* Copyright (C) 2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy @@ -23,22 +26,27 @@ * THE SOFTWARE. */ -#include +#include +#include +#include -void console_init(void) { -} +#include "artnetnode.h" -void console_putc(__attribute__((unused)) int i) { -} +#include "network.h" -void console_puts(__attribute__((unused)) const char *p) { -} +#include "panel_led.h" -void console_write(__attribute__((unused)) const char *p, __attribute__((unused)) unsigned int i) { -} +#include "debug.h" -void console_status(__attribute__((unused)) uint32_t i, __attribute__((unused)) const char *p) { -} +void ArtNetNode::HandleRdmSub() { + DEBUG_ENTRY + + auto *const pArtRdmSub = reinterpret_cast(m_pReceiveBuffer); + + if (pArtRdmSub->RdmVer != 0x01) { + DEBUG_EXIT + return; + } -void console_error(__attribute__((unused)) const char *p) { + DEBUG_EXIT } diff --git a/lib-artnet/src/node/rdm/responder/setrdm.cpp b/lib-artnet/src/node/rdm/responder/setrdm.cpp new file mode 100755 index 00000000..db3912e4 --- /dev/null +++ b/lib-artnet/src/node/rdm/responder/setrdm.cpp @@ -0,0 +1,55 @@ +/** + * @file setrdm.cpp + * + */ +/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#include "artnetnode.h" +#include "artnetrdmresponder.h" + +#include "debug.h" + +void ArtNetNode::SetRdm(const bool doEnable) { + DEBUG_ENTRY + + SetRdmResponder(m_pArtNetRdmResponder, doEnable); + + DEBUG_EXIT +} + +void ArtNetNode::SetRdmResponder(ArtNetRdmResponder *pArtNetRdmResponder, const bool doEnable) { + DEBUG_ENTRY + + m_pArtNetRdmResponder = pArtNetRdmResponder; + m_State.rdm.IsEnabled = ((pArtNetRdmResponder != nullptr) & doEnable); + + if (m_State.rdm.IsEnabled) { + m_ArtPollReply.Status1 |= artnet::Status1::RDM_CAPABLE; + } else { + m_ArtPollReply.Status1 &= static_cast(~artnet::Status1::RDM_CAPABLE); + } + + DEBUG_PRINTF("m_State.rdm.IsEnabled=%c", m_State.rdm.IsEnabled ? 'Y' : 'N'); + DEBUG_EXIT +} diff --git a/lib-artnet/src/node/rdm/setrdm.cpp b/lib-artnet/src/node/rdm/setrdm.cpp new file mode 100755 index 00000000..ffa774de --- /dev/null +++ b/lib-artnet/src/node/rdm/setrdm.cpp @@ -0,0 +1,76 @@ +/** + * @file setrdm.cpp + * + */ +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#include "artnetnode.h" +#include "artnetstore.h" + +#include "debug.h" + +void ArtNetNode::SetRdm(const uint32_t nPortIndex, const bool bEnable) { + DEBUG_ENTRY + assert(nPortIndex < artnetnode::MAX_PORTS); + + const auto isEnabled = !((m_OutputPort[nPortIndex].GoodOutputB & artnet::GoodOutputB::RDM_DISABLED) == artnet::GoodOutputB::RDM_DISABLED); + + if (isEnabled == bEnable) { + DEBUG_EXIT + return; + } + + if (!bEnable) { + m_OutputPort[nPortIndex].GoodOutputB |= artnet::GoodOutputB::RDM_DISABLED; + } else { + m_OutputPort[nPortIndex].GoodOutputB &= static_cast(~artnet::GoodOutputB::RDM_DISABLED); + } + + if (m_State.status == artnet::Status::ON) { + ArtNetStore::SaveRdmEnabled(nPortIndex, bEnable); + artnet::display_rdm_enabled(nPortIndex, bEnable); + } + + DEBUG_EXIT +} + +void ArtNetNode::SetRdmDiscovery(const uint32_t nPortIndex, const bool bEnable) { + DEBUG_ENTRY + assert(nPortIndex < artnetnode::MAX_PORTS); + + const auto isEnabled = !((m_OutputPort[nPortIndex].GoodOutputB & artnet::GoodOutputB::DISCOVERY_DISABLED) == artnet::GoodOutputB::DISCOVERY_DISABLED); + + if (isEnabled == bEnable) { + DEBUG_EXIT + return; + } + + if (!bEnable) { + m_OutputPort[nPortIndex].GoodOutputB |= artnet::GoodOutputB::DISCOVERY_DISABLED; + } else { + m_OutputPort[nPortIndex].GoodOutputB &= static_cast(~artnet::GoodOutputB::DISCOVERY_DISABLED); + } + + DEBUG_EXIT +} diff --git a/lib-artnet/src/node/timecode/handletimecode.cpp b/lib-artnet/src/node/timecode/handletimecode.cpp deleted file mode 100644 index 38c21137..00000000 --- a/lib-artnet/src/node/timecode/handletimecode.cpp +++ /dev/null @@ -1,67 +0,0 @@ -/** - * @file artnetnodetimecode.cpp - * - */ -/** - * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. - */ -/* Copyright (C) 2016-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include - -#include "artnetnode.h" -#include "artnet.h" -#include "artnettimecode.h" - -#include "network.h" - -#include "debug.h" - -void ArtNetNode::HandleTimeCode() { - const auto *const pArtTimeCode = reinterpret_cast(m_pReceiveBuffer); - - m_pArtNetTimeCode->Handler(reinterpret_cast(&pArtTimeCode->Frames)); -} - -void ArtNetNode::SetTimeCodeIp(uint32_t nDestinationIp) { - if (Network::Get()->IsValidIp(nDestinationIp)) { - m_Node.IPAddressTimeCode = nDestinationIp; - } else { - m_Node.IPAddressTimeCode = Network::Get()->GetBroadcastIp(); - } - - DEBUG_PRINTF("m_Node.IPAddressTimeCode=" IPSTR, IP2STR(m_Node.IPAddressTimeCode)); -} - -void ArtNetNode::SendTimeCode(const struct TArtNetTimeCode *pArtNetTimeCode) { - assert(pArtNetTimeCode != nullptr); - assert(pArtNetTimeCode->Frames < 30); - assert(pArtNetTimeCode->Hours < 60); - assert(pArtNetTimeCode->Minutes < 60); - assert(pArtNetTimeCode->Seconds < 60); - assert(pArtNetTimeCode->Type < 4); - - memcpy(&m_ArtTimeCode.Frames, pArtNetTimeCode, sizeof(struct TArtNetTimeCode)); - - Network::Get()->SendTo(m_nHandle, &m_ArtTimeCode, sizeof(struct artnet::ArtTimeCode), m_Node.IPAddressTimeCode, artnet::UDP_PORT); -} diff --git a/lib-c++/.cproject b/lib-c++/.cproject deleted file mode 100644 index 6e28cb0d..00000000 --- a/lib-c++/.cproject +++ /dev/null @@ -1,94 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/lib-c++/.settings/language.settings.xml b/lib-c++/.settings/language.settings.xml deleted file mode 100644 index 96fdf9df..00000000 --- a/lib-c++/.settings/language.settings.xml +++ /dev/null @@ -1,12 +0,0 @@ - - - - - - - - - - - - \ No newline at end of file diff --git a/lib-c++/Makefile.GD32 b/lib-c++/Makefile.GD32 deleted file mode 100644 index ff29a8db..00000000 --- a/lib-c++/Makefile.GD32 +++ /dev/null @@ -1,2 +0,0 @@ - -include ../firmware-template-gd32/lib/Rules.mk \ No newline at end of file diff --git a/lib-c/.cproject b/lib-c/.cproject deleted file mode 100644 index feebeb53..00000000 --- a/lib-c/.cproject +++ /dev/null @@ -1,81 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/lib-c/.settings/org.eclipse.cdt.core.prefs b/lib-c/.settings/org.eclipse.cdt.core.prefs deleted file mode 100644 index c8ec5df2..00000000 --- a/lib-c/.settings/org.eclipse.cdt.core.prefs +++ /dev/null @@ -1,6 +0,0 @@ -doxygen/doxygen_new_line_after_brief=true -doxygen/doxygen_use_brief_tag=false -doxygen/doxygen_use_javadoc_tags=true -doxygen/doxygen_use_pre_tag=false -doxygen/doxygen_use_structural_commands=false -eclipse.preferences.version=1 diff --git a/lib-c/Makefile.GD32 b/lib-c/Makefile.GD32 deleted file mode 100644 index b54ecb29..00000000 --- a/lib-c/Makefile.GD32 +++ /dev/null @@ -1,3 +0,0 @@ -#DEFINES=MEM_DEBUG - -include ../firmware-template-gd32/lib/Rules.mk \ No newline at end of file diff --git a/lib-clib/.cproject b/lib-clib/.cproject new file mode 100755 index 00000000..5ae28943 --- /dev/null +++ b/lib-clib/.cproject @@ -0,0 +1,161 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/lib-c/.project b/lib-clib/.project old mode 100644 new mode 100755 similarity index 97% rename from lib-c/.project rename to lib-clib/.project index 3adc2f41..47d0f02c --- a/lib-c/.project +++ b/lib-clib/.project @@ -1,6 +1,6 @@ - lib-c + lib-clib diff --git a/lib-clib/.settings/language.settings.xml b/lib-clib/.settings/language.settings.xml new file mode 100755 index 00000000..238d3a32 --- /dev/null +++ b/lib-clib/.settings/language.settings.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/lib-c/.settings/org.eclipse.core.resources.prefs b/lib-clib/.settings/org.eclipse.core.resources.prefs old mode 100644 new mode 100755 similarity index 100% rename from lib-c/.settings/org.eclipse.core.resources.prefs rename to lib-clib/.settings/org.eclipse.core.resources.prefs diff --git a/lib-clib/Makefile.GD32 b/lib-clib/Makefile.GD32 new file mode 100755 index 00000000..0502e1a0 --- /dev/null +++ b/lib-clib/Makefile.GD32 @@ -0,0 +1,25 @@ +DEFINES=NDEBUG + +EXTRA_INCLUDES= + +EXTRA_SRCDIR= + +ifneq ($(MAKE_FLAGS),) + ifeq ($(findstring CONFIG_ENET_ENABLE_PTP,$(MAKE_FLAGS)), CONFIG_ENET_ENABLE_PTP) + EXTRA_SRCDIR+=src/gd32/time_ptp + else + ifeq ($(findstring CONFIG_TIME_USE_TIMER,$(MAKE_FLAGS)), CONFIG_TIME_USE_TIMER) + EXTRA_SRCDIR+=src/gd32/time_timer + else + EXTRA_SRCDIR+=src/gd32/time_systick + endif + endif +else + EXTRA_SRCDIR+=src/gd32/time_systick + + EXTRA_SRCDIR+=src/gd32/time_timer + DEFINES+=CONFIG_TIME_USE_TIMER +endif + +include Rules.mk +include ../firmware-template-gd32/lib/Rules.mk \ No newline at end of file diff --git a/lib-clib/Rules.mk b/lib-clib/Rules.mk new file mode 100755 index 00000000..821b5db7 --- /dev/null +++ b/lib-clib/Rules.mk @@ -0,0 +1,2 @@ + +EXTRA_SRCDIR+=src/c++ \ No newline at end of file diff --git a/lib-clib/src/abort.c b/lib-clib/src/abort.c new file mode 100755 index 00000000..7680b690 --- /dev/null +++ b/lib-clib/src/abort.c @@ -0,0 +1,15 @@ +/* + * abort.c + */ + + +#ifdef NDEBUG +# undef NDEBUG +#endif + +#include + +void abort(void) { + assert(0); + for(;;); +} diff --git a/lib-c/src/asctime.c b/lib-clib/src/asctime.c old mode 100644 new mode 100755 similarity index 100% rename from lib-c/src/asctime.c rename to lib-clib/src/asctime.c diff --git a/lib-clib/src/c++/cxa_atexit.cpp b/lib-clib/src/c++/cxa_atexit.cpp new file mode 100755 index 00000000..cae8031d --- /dev/null +++ b/lib-clib/src/c++/cxa_atexit.cpp @@ -0,0 +1,26 @@ +/* + * cxa_atexit.cpp + */ + +#include + +typedef void (*exitfunc_t)(); + +static exitfunc_t atexit_funcs[32]; +static size_t atexit_count = 0; + +extern "C" int __cxa_atexit(exitfunc_t func, [[maybe_unused]] void *arg, [[maybe_unused]] void *dso_handle) { + if (atexit_count >= sizeof(atexit_funcs) / sizeof(atexit_funcs[0])) + return -1; + + atexit_funcs[atexit_count++] = func; + return 0; // Success +} + +extern "C" void __call_atexit_funcs() { + for (size_t i = atexit_count; i > 0; --i) { + exitfunc_t func = atexit_funcs[i - 1]; + if (func) + func(); + } +} diff --git a/lib-c++/src/delete.cpp b/lib-clib/src/c++/delete.cpp old mode 100644 new mode 100755 similarity index 78% rename from lib-c++/src/delete.cpp rename to lib-clib/src/c++/delete.cpp index 4f5019c3..72c4aa95 --- a/lib-c++/src/delete.cpp +++ b/lib-clib/src/c++/delete.cpp @@ -2,7 +2,7 @@ * @file delete.cpp * */ -/* Copyright (C) 2017-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,7 +23,8 @@ * THE SOFTWARE. */ -#include +#include +#include void operator delete(void *p) { free(p); @@ -32,3 +33,15 @@ void operator delete(void *p) { void operator delete[](void *p) { free(p); } + +/* + * C++14 and above + */ + +void operator delete(void *p, [[maybe_unused]] std::size_t size) noexcept { + free(p); +} + +void operator delete[](void *p, [[maybe_unused]]std::size_t size) noexcept { + free(p); +} diff --git a/lib-c++/src/dso_handle.cpp b/lib-clib/src/c++/dso_handle.cpp old mode 100644 new mode 100755 similarity index 80% rename from lib-c++/src/dso_handle.cpp rename to lib-clib/src/c++/dso_handle.cpp index c6d7a803..2b06c2e4 --- a/lib-c++/src/dso_handle.cpp +++ b/lib-clib/src/c++/dso_handle.cpp @@ -2,7 +2,7 @@ * @file dso_handle.cpp * */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2023 by Arjan van Vught mailto:info@info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,11 +23,11 @@ * THE SOFTWARE. */ -extern "C" int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) { - static_cast(object); - static_cast(destructor); - static_cast(dso_handle); - return 0; -} +//extern "C" int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) { +// static_cast(object); +// static_cast(destructor); +// static_cast(dso_handle); +// return 0; +//} void *__dso_handle = nullptr; diff --git a/lib-clib/src/c++/impure_prt.cpp b/lib-clib/src/c++/impure_prt.cpp new file mode 100755 index 00000000..98bc95e5 --- /dev/null +++ b/lib-clib/src/c++/impure_prt.cpp @@ -0,0 +1,11 @@ +/* + * impure_prt.cpp + */ + +typedef struct _reent { + int _errno; // Placeholder for the actual contents of _reent +} _reent; + +// Define the global _impure_ptr. Normally points to reentrant data. +static struct _reent _reent_data = {0}; +struct _reent *_impure_ptr = &_reent_data; diff --git a/lib-c++/src/new.cpp b/lib-clib/src/c++/new.cpp old mode 100644 new mode 100755 similarity index 92% rename from lib-c++/src/new.cpp rename to lib-clib/src/c++/new.cpp index 6cf0eb0b..64b61cca --- a/lib-c++/src/new.cpp +++ b/lib-clib/src/c++/new.cpp @@ -2,7 +2,7 @@ * @file new.cpp * */ -/* Copyright (C) 2017-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,7 +23,7 @@ * THE SOFTWARE. */ -#include +#include void *operator new(unsigned size) { return malloc(size); diff --git a/lib-c++/src/purecall.cpp b/lib-clib/src/c++/purecall.cpp old mode 100644 new mode 100755 similarity index 94% rename from lib-c++/src/purecall.cpp rename to lib-clib/src/c++/purecall.cpp index b6c1dcb9..d4ff1c39 --- a/lib-c++/src/purecall.cpp +++ b/lib-clib/src/c++/purecall.cpp @@ -2,7 +2,7 @@ * @file purecall.cpp * */ -/* Copyright (C) 2017-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-c/src/errno.c b/lib-clib/src/errno.c old mode 100644 new mode 100755 similarity index 100% rename from lib-c/src/errno.c rename to lib-clib/src/errno.c diff --git a/lib-c/src/assert.c b/lib-clib/src/gd32/assert.c similarity index 100% rename from lib-c/src/assert.c rename to lib-clib/src/gd32/assert.c diff --git a/lib-configstore/src/rdm/storerdmsubdevices.cpp b/lib-clib/src/gd32/malloc.h old mode 100644 new mode 100755 similarity index 74% rename from lib-configstore/src/rdm/storerdmsubdevices.cpp rename to lib-clib/src/gd32/malloc.h index 5b200425..7a4109ab --- a/lib-configstore/src/rdm/storerdmsubdevices.cpp +++ b/lib-clib/src/gd32/malloc.h @@ -1,8 +1,8 @@ /** - * @file storerdmsubdevices.cpp + * @file malloc.h * */ -/* Copyright (C) 2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,20 +23,9 @@ * THE SOFTWARE. */ -#include +#ifndef GD32_MALLOC_H_ +#define GD32_MALLOC_H_ -#include "storerdmsubdevices.h" +static struct block_bucket s_block_bucket[] __attribute__((aligned(4))) = {{0x10, 0}, {0x20, 0}, {0x40, 0}, {0x60, 0}, {0x80,0}, {0x100,0}, {0x140,0}, {0x180,0}, {0x200,0}, {0x300,0}, {0x400,0}, {0x500,0}, {0,0}}; -#include "debug.h" - -StoreRDMSubDevices *StoreRDMSubDevices::s_pThis = nullptr; - -StoreRDMSubDevices::StoreRDMSubDevices() { - DEBUG_ENTRY - - assert(s_pThis == nullptr); - s_pThis = this; - - DEBUG_PRINTF("%p", reinterpret_cast(s_pThis)); - DEBUG_EXIT -} +#endif /* GD32_MALLOC_H_ */ diff --git a/lib-clib/src/gd32/time_ptp/time.cpp b/lib-clib/src/gd32/time_ptp/time.cpp new file mode 100644 index 00000000..a418f743 --- /dev/null +++ b/lib-clib/src/gd32/time_ptp/time.cpp @@ -0,0 +1,99 @@ +/** + * @file time.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#pragma GCC push_options +#pragma GCC optimize ("O2") + +#include +#include +#include +#include + +#include "gd32.h" +#include "gd32_ptp.h" + +#if defined (GD32H7XX) +# define enet_ptp_timestamp_function_config(x) enet_ptp_timestamp_function_config(ENETx, x) +# define enet_ptp_timestamp_update_config(x,y,z) enet_ptp_timestamp_update_config(ENETx, x, y, z) +# define enet_ptp_system_time_get(x) enet_ptp_system_time_get(ENETx, x) +#endif + +extern "C" { +/* + * number of seconds and microseconds since the Epoch, + * 1970-01-01 00:00:00 +0000 (UTC). + */ + +int gettimeofday(struct timeval *tv, [[maybe_unused]] struct timezone *tz) { + assert(tv != 0); + + enet_ptp_systime_struct systime; + enet_ptp_system_time_get(&systime); + + tv->tv_sec = systime.second; + +#if !defined (GD32F4XX) + const auto nNanoSecond = systime.nanosecond; +#else + const auto nNanoSecond = gd32::ptp_subsecond_2_nanosecond(systime.subsecond); +#endif + + tv->tv_usec = nNanoSecond / 1000U; + + return 0; +} + +int settimeofday(const struct timeval *tv, [[maybe_unused]] const struct timezone *tz) { + assert(tv != 0); + + const uint32_t nSign = ENET_PTP_ADD_TO_TIME; + const uint32_t nSecond = tv->tv_sec; + const uint32_t nNanoSecond = tv->tv_usec * 1000U; + const auto nSubSecond = gd32::ptp_nanosecond_2_subsecond(nNanoSecond); + + enet_ptp_timestamp_update_config(nSign, nSecond, nSubSecond); + + if (SUCCESS == enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT)) { + return 0; + } + + return -1; +} + +/* + * time() returns the time as the number of seconds since the Epoch, + 1970-01-01 00:00:00 +0000 (UTC). + */ +time_t time(time_t *__timer) { + struct timeval tv; + gettimeofday(&tv, 0); + + if (__timer != nullptr) { + *__timer = tv.tv_sec; + } + + return tv.tv_sec; +} +} diff --git a/lib-c/src/gd32/time.c b/lib-clib/src/gd32/time_systick/time.cpp similarity index 54% rename from lib-c/src/gd32/time.c rename to lib-clib/src/gd32/time_systick/time.cpp index b754cc25..024803bf 100644 --- a/lib-c/src/gd32/time.c +++ b/lib-clib/src/gd32/time_systick/time.cpp @@ -2,7 +2,7 @@ * @file time.c * */ -/* Copyright (C) 2021 by Arjan van Vught mailto:info@gd32-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,50 +23,67 @@ * THE SOFTWARE. */ -#include -#include -#include -#include +#pragma GCC push_options +#pragma GCC optimize ("O2") -extern volatile uint32_t s_nSysTickMillis; +#include +#include +#include +#include -static uint32_t set_timer = 0; -static uint64_t s_micros = 0; +extern volatile uint32_t gv_nSysTickMillis; -#define MICROS_SECONDS 1000000 +static uint32_t nPreviousSysTickMillis; +static struct timeval s_tv; +extern "C" { /* * number of seconds and microseconds since the Epoch, * 1970-01-01 00:00:00 +0000 (UTC). */ -int gettimeofday(struct timeval *tv, __attribute__((unused)) struct timezone *tz) { +int gettimeofday(struct timeval *tv, __attribute__((unused)) struct timezone *tz) { assert(tv != 0); - const uint32_t timer = s_nSysTickMillis; // Millis timer + const auto nCurrentSysTickMillis = gv_nSysTickMillis; - uint32_t timer_elapsed; + uint32_t nMillisElapsed; - if (set_timer >= timer) { - timer_elapsed = set_timer - timer; + if (nCurrentSysTickMillis >= nPreviousSysTickMillis) { + nMillisElapsed = nCurrentSysTickMillis - nPreviousSysTickMillis; } else { - timer_elapsed = timer - set_timer; + nMillisElapsed = (UINT32_MAX - nPreviousSysTickMillis) + nCurrentSysTickMillis + 1; } - set_timer = timer; - s_micros += (timer_elapsed * 1000); + nPreviousSysTickMillis = nCurrentSysTickMillis; + + const auto nSeconds = nMillisElapsed / 1000U; + const auto nMicroSeconds = (nMillisElapsed % 1000U) * 1000U; - tv->tv_sec = (time_t)(s_micros / MICROS_SECONDS); - tv->tv_usec = (suseconds_t) (s_micros - ((uint64_t) tv->tv_sec * MICROS_SECONDS)); + s_tv.tv_sec += static_cast(nSeconds); + s_tv.tv_usec += static_cast(nMicroSeconds); + + if (s_tv.tv_usec >= 1000000) { + s_tv.tv_sec++; + s_tv.tv_usec -= 1000000; + } + + tv->tv_sec = s_tv.tv_sec; + tv->tv_usec = s_tv.tv_usec; return 0; } -int settimeofday(const struct timeval *tv, __attribute__((unused)) const struct timezone *tz) { +int settimeofday(const struct timeval *tv, __attribute__((unused)) const struct timezone *tz) { assert(tv != 0); - set_timer = s_nSysTickMillis; - s_micros = ((uint64_t) tv->tv_sec * MICROS_SECONDS) + (uint64_t) tv->tv_usec; + struct timeval g; + gettimeofday(&g, nullptr); + + nPreviousSysTickMillis = gv_nSysTickMillis; + + s_tv.tv_sec = tv->tv_sec; + s_tv.tv_usec = tv->tv_usec; return 0; } @@ -77,11 +94,12 @@ int settimeofday(const struct timeval *tv, __attribute__((unused)) const struct */ time_t time(time_t *__timer) { struct timeval tv; - gettimeofday(&tv, 0); + gettimeofday(&tv, nullptr); - if (__timer != NULL) { + if (__timer != nullptr) { *__timer = tv.tv_sec; } return tv.tv_sec; } +} diff --git a/lib-clib/src/gd32/time_timer/time.cpp b/lib-clib/src/gd32/time_timer/time.cpp new file mode 100644 index 00000000..8782a953 --- /dev/null +++ b/lib-clib/src/gd32/time_timer/time.cpp @@ -0,0 +1,157 @@ +/** + * @file time.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#pragma GCC push_options +#pragma GCC optimize ("O2") + +#include +#include +#include +#include + +#include "gd32.h" + +#if defined(GD32H7XX) +# define TIMERx TIMER16 +# define RCU_TIMERx RCU_TIMER16 +# define TIMERx_IRQn TIMER16_IRQn +#else +# define TIMERx TIMER7 +# define RCU_TIMERx RCU_TIMER7 +# if defined (GD32F10X) || defined (GD32F30X) +# define TIMERx_IRQn TIMER7_IRQn +# else +# define TIMERx_IRQn TIMER7_UP_TIMER12_IRQn +# endif +#endif + +extern struct HwTimersSeconds g_Seconds; + +extern "C" { +#if !defined (CONFIG_ENET_ENABLE_PTP) +# if defined (CONFIG_TIME_USE_TIMER) +# if defined(GD32H7XX) +void TIMER16_IRQHandler() { +# elif defined (GD32F10X) || defined (GD32F30X) +void TIMER7_IRQHandler() { +# else +void TIMER7_UP_TIMER12_IRQHandler() { +# endif + const auto nIntFlag = TIMER_INTF(TIMERx); + + if ((nIntFlag & TIMER_INT_FLAG_UP) == TIMER_INT_FLAG_UP) { + g_Seconds.nTimeval++; + } + + TIMER_INTF(TIMERx) = static_cast(~nIntFlag); +} +# endif +#endif +} + +#if defined(GD32H7XX) +void timer16_config() { +#else +void timer7_config() { +#endif + g_Seconds.nTimeval = 0; + + rcu_periph_clock_enable(RCU_TIMERx); + timer_deinit(TIMERx); + + timer_parameter_struct timer_initpara; + timer_struct_para_init(&timer_initpara); + + timer_initpara.prescaler = TIMER_PSC_10KHZ; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = (10000 - 1); // 1 second + timer_init(TIMERx, &timer_initpara); + + timer_interrupt_flag_clear(TIMERx, ~0); + + timer_interrupt_enable(TIMERx, TIMER_INT_UP); + + NVIC_SetPriority(TIMERx_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); // Lowest priority + NVIC_EnableIRQ(TIMERx_IRQn); + + timer_enable(TIMERx); +} + +extern "C" { +/* + * number of seconds and microseconds since the Epoch, + * 1970-01-01 00:00:00 +0000 (UTC). + */ + +int gettimeofday(struct timeval *tv, __attribute__((unused)) struct timezone *tz) { + assert(tv != 0); + +#if __CORTEX_M == 7 + __DMB(); +#endif + + tv->tv_sec = g_Seconds.nTimeval; + tv->tv_usec = TIMER_CNT(TIMERx) * 100U; + +#if __CORTEX_M == 7 + __ISB(); +#endif + + return 0; +} + +int settimeofday(const struct timeval *tv, __attribute__((unused)) const struct timezone *tz) { + assert(tv != 0); + + // Disable the timer interrupt to prevent it from triggering while we adjust the counter + TIMER_DMAINTEN(TIMERx) &= static_cast(~TIMER_INT_UP); + TIMER_CTL0(TIMERx) &= static_cast(~TIMER_CTL0_CEN); + + g_Seconds.nTimeval = tv->tv_sec; + TIMER_CNT(TIMERx) = (tv->tv_usec / 100U) % 10000; + + TIMER_INTF(TIMERx) = static_cast(~0); + TIMER_DMAINTEN(TIMERx) |= TIMER_INT_UP; + TIMER_CTL0(TIMERx) |= TIMER_CTL0_CEN; + + return 0; +} + +/* + * time() returns the time as the number of seconds since the Epoch, + 1970-01-01 00:00:00 +0000 (UTC). + */ +time_t time(time_t *__timer) { + struct timeval tv; + gettimeofday(&tv, nullptr); + + if (__timer != nullptr) { + *__timer = tv.tv_sec; + } + + return tv.tv_sec; +} +} diff --git a/lib-clib/src/gd32/uuid.cpp b/lib-clib/src/gd32/uuid.cpp new file mode 100644 index 00000000..89f9772f --- /dev/null +++ b/lib-clib/src/gd32/uuid.cpp @@ -0,0 +1,58 @@ +/** + * @file uuid.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of thnDmxDataDirecte Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include + +#include "gd32.h" + +namespace hal { +typedef union pcast32 { + uuid_t uuid; + uint32_t u32[4]; +} _pcast32; + +void uuid_init(uuid_t out) { + _pcast32 cast; + +#if defined (GD32H7XX) + cast.u32[0] = REG32(0x1FF0F7E8); + cast.u32[1] = REG32(0x1FF0F7EC); + cast.u32[2] = REG32(0x1FF0F7F0); +#elif defined (GD32F4XX) + cast.u32[0] = REG32(0x1FFF7A10); + cast.u32[1] = REG32(0x1FFF7A14); + cast.u32[2] = REG32(0x1FFF7A18); +#else + cast.u32[0] = REG32(0x1FFFF7E8); + cast.u32[1] = REG32(0x1FFFF7EC); + cast.u32[2] = REG32(0x1FFFF7F0); +#endif + cast.u32[3] = cast.u32[0] + cast.u32[1] + cast.u32[2]; + + memcpy(out, cast.uuid, sizeof(uuid_t)); +} +} // namespace hal diff --git a/lib-c/src/inet_aton.c b/lib-clib/src/inet_aton.c old mode 100644 new mode 100755 similarity index 94% rename from lib-c/src/inet_aton.c rename to lib-clib/src/inet_aton.c index 52dbfc3d..cc83bb53 --- a/lib-c/src/inet_aton.c +++ b/lib-clib/src/inet_aton.c @@ -25,13 +25,14 @@ #include #include +#include typedef union pcast32 { uint32_t u32; uint8_t u8[4]; } _pcast32; -int inet_aton(const char *cp, uint32_t *ip_address) { +int inet_aton(const char *cp, struct in_addr *ip_address) { const char *b = cp; int i, j, k; _pcast32 cast32; @@ -79,7 +80,7 @@ int inet_aton(const char *cp, uint32_t *ip_address) { cast32.u8[i] = (uint8_t)k; if (ip_address != 0) { - *ip_address = cast32.u32; + ip_address->s_addr = cast32.u32; } return 1; diff --git a/lib-c/src/init.c b/lib-clib/src/init.c similarity index 100% rename from lib-c/src/init.c rename to lib-clib/src/init.c diff --git a/lib-c/src/log.c b/lib-clib/src/log.c old mode 100644 new mode 100755 similarity index 100% rename from lib-c/src/log.c rename to lib-clib/src/log.c diff --git a/lib-c/src/malloc.c b/lib-clib/src/malloc.c old mode 100644 new mode 100755 similarity index 90% rename from lib-c/src/malloc.c rename to lib-clib/src/malloc.c index e6af3cb8..58676778 --- a/lib-c/src/malloc.c +++ b/lib-clib/src/malloc.c @@ -8,7 +8,7 @@ * Copyright (C) 2014-2016 R. Stange * https://github.com/rsta2/circle/blob/master/lib/alloc.cpp */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,15 +32,18 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpointer-arith" // FIXME ignored "-Wpointer-arith" #pragma GCC diagnostic ignored "-Wpedantic" // FIXME ignored "-Wpedantic" +#pragma GCC diagnostic ignored "-Wmissing-field-initializers" #include #include #include -#ifdef MEM_DEBUG +#ifdef DEBUG_HEAP #include #endif +extern void console_error(const char *); + extern unsigned char heap_low; /* Defined by the linker */ extern unsigned char heap_top; /* Defined by the linker */ @@ -58,14 +61,20 @@ struct block_header { struct block_bucket { unsigned int size; -#ifdef MEM_DEBUG +#ifdef DEBUG_HEAP unsigned int count; unsigned int max_count; #endif struct block_header *free_list; }; -static struct block_bucket s_block_bucket[] __attribute__((aligned(4))) = {{0x10, 0}, {0x20, 0}, {0x40, 0}, {0x60, 0}, {0x80,0}, {0x100,0}, {0x140,0}, {0x180,0}, {0x200,0}, {0x300,0}, {0x400,0}, {0x500,0}, {0,0}}; +#if defined (H3) +# include "h3/malloc.h" +#elif defined (GD32) +# include "gd32/malloc.h" +#else +# include "rpi/malloc.h" +#endif size_t get_allocated(void *p) { if (p == 0) { @@ -83,9 +92,6 @@ size_t get_allocated(void *p) { } void *malloc(size_t size) { -#ifdef MEM_DEBUG - printf("malloc: %u\n", size); -#endif struct block_bucket *bucket; struct block_header *header; @@ -96,7 +102,7 @@ void *malloc(size_t size) { for (bucket = s_block_bucket; bucket->size > 0; bucket++) { if (size <= bucket->size) { size = bucket->size; -#ifdef MEM_DEBUG +#ifdef DEBUG_HEAP if (++bucket->count > bucket->max_count) { bucket->max_count = bucket->count; } @@ -120,9 +126,7 @@ void *malloc(size_t size) { assert(((unsigned)next & (unsigned)3) == 0); if (next > block_limit) { -#ifdef MEM_DEBUG - printf("malloc: next > block_limit\n"); -#endif + console_error("next > block_limit\n"); return NULL; } else { next_block = next; @@ -133,8 +137,8 @@ void *malloc(size_t size) { } header->next = 0; -#ifdef MEM_DEBUG - printf("malloc: pBlockHeader=%p, size=%d, data=%p\n", header, (int) size, (void *)header->data); +#ifdef DEBUG_HEAP + printf("malloc: pBlockHeader = %p, size = %d\n", header, (int) size); #endif assert(((unsigned)header->data & (unsigned)3) == 0); @@ -150,7 +154,7 @@ void free(void *p) { struct block_header *header = (struct block_header *) ((void *) p - sizeof(struct block_header)); -#ifdef MEM_DEBUG +#ifdef DEBUG_HEAP printf("free: pBlockHeader = %p, pBlock = %p\n", header, p); #endif @@ -164,7 +168,7 @@ void free(void *p) { header->next = bucket->free_list; bucket->free_list = header; -#ifdef MEM_DEBUG +#ifdef DEBUG_HEAP bucket->count--; #endif break; @@ -258,8 +262,8 @@ void *realloc(void *ptr, size_t size) { return newblk; } -void mem_info(void) { -#ifdef MEM_DEBUG +void debug_heap(void) { +#ifdef DEBUG_HEAP struct block_bucket *pBucket; struct block_header *pBlockHeader; printf("s_pNextBlock = %p\n", next_block); diff --git a/lib-clib/src/memchr.c b/lib-clib/src/memchr.c new file mode 100755 index 00000000..ca055d21 --- /dev/null +++ b/lib-clib/src/memchr.c @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +void* memchr(const void *src, int c, size_t len) { + const unsigned char *s = src; + + while (len--) { + if (*s == (unsigned char) c) + return (void*) s; + s++; + } + + return NULL; +} diff --git a/lib-clib/src/memcmp.c b/lib-clib/src/memcmp.c new file mode 100755 index 00000000..7b1a185a --- /dev/null +++ b/lib-clib/src/memcmp.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +int memcmp(const void *s1, const void *s2, size_t len) +{ + const unsigned char *s = s1; + const unsigned char *d = s2; + unsigned char sc; + unsigned char dc; + + while (len--) { + sc = *s++; + dc = *d++; + if (sc - dc) + return (sc - dc); + } + + return 0; +} diff --git a/lib-c/src/memcpy.c b/lib-clib/src/memcpy.c old mode 100644 new mode 100755 similarity index 100% rename from lib-c/src/memcpy.c rename to lib-clib/src/memcpy.c diff --git a/lib-c/src/memmove.c b/lib-clib/src/memmove.c old mode 100644 new mode 100755 similarity index 100% rename from lib-c/src/memmove.c rename to lib-clib/src/memmove.c diff --git a/lib-c/src/memset.c b/lib-clib/src/memset.c old mode 100644 new mode 100755 similarity index 100% rename from lib-c/src/memset.c rename to lib-clib/src/memset.c diff --git a/lib-c/src/perror.c b/lib-clib/src/perror.c old mode 100644 new mode 100755 similarity index 100% rename from lib-c/src/perror.c rename to lib-clib/src/perror.c diff --git a/lib-c/src/printf.c b/lib-clib/src/printf.c old mode 100644 new mode 100755 similarity index 92% rename from lib-c/src/printf.c rename to lib-clib/src/printf.c index 24b240b2..0ba67569 --- a/lib-c/src/printf.c +++ b/lib-clib/src/printf.c @@ -2,7 +2,7 @@ * @file printf.c * */ -/* Copyright (C) 2016-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2016-2023 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,7 +29,6 @@ #include #include #include -#include extern int console_putc(int); @@ -53,7 +52,7 @@ enum { static char *outptr = NULL; -inline static void _xputch(struct context *ctx, int c) { +inline static void _xputch(struct context *ctx, const int c) { ctx->total++; if (outptr != NULL) { @@ -78,7 +77,7 @@ static int _pow10(int n) { return r; } -static int _itostr(int x, /*@out@*/char *s, int d) { +static int _itostr(int x, char *s, int d) { char buffer[64]; char *p = buffer + (sizeof(buffer) / sizeof(buffer[0])) - 1; char *o = p; @@ -123,7 +122,7 @@ static int _itostr(int x, /*@out@*/char *s, int d) { return i + 1; } -static void _round_float(/*@out@*/char *dest, int *size) { +static void _round_float(char *dest, int *size) { int i = *size - 1; char *q = (char *) dest + i; bool round_int = false; @@ -175,7 +174,7 @@ static void _round_float(/*@out@*/char *dest, int *size) { #endif static void _format_hex(struct context *ctx, unsigned int arg) { - char buffer[64] __attribute__((aligned(4))); + char buffer[64]; char *p = buffer + (sizeof(buffer) / sizeof(buffer[0])) - 1; char *o = p; char alpha; @@ -227,7 +226,7 @@ static void _format_hex(struct context *ctx, unsigned int arg) { } } -static void _format_int(struct context *ctx, uint64_t arg) { +static void _format_int(struct context *ctx, unsigned long int arg) { char buffer[64]; char *p = buffer + (sizeof(buffer) / sizeof(buffer[0])) - 1; char *o = p; @@ -281,7 +280,7 @@ static void _format_int(struct context *ctx, uint64_t arg) { #if !defined (DISABLE_PRINTF_FLOAT) static void _format_float(struct context *ctx, float f) { - char buffer[64] __attribute__((aligned(4))); + char buffer[64]; char *dest = (char *) buffer; int ipart; int precision; @@ -366,8 +365,8 @@ static int _vprintf(const int size, const char *fmt, va_list va) { #if !defined (DISABLE_PRINTF_FLOAT) float f; #endif - int64_t l; - uint64_t lu; + long int l; + unsigned long int lu; const char *s; ctx.total = 0; @@ -433,12 +432,12 @@ static int _vprintf(const int size, const char *fmt, va_list va) { /*@fallthrough@*/ /* no break */ case 'i': - l = ((ctx.flag & FLAG_LONG) != 0) ? va_arg(va, int64_t) : (int64_t) va_arg(va, int32_t); + l = ((ctx.flag & FLAG_LONG) != 0) ? va_arg(va, long int) : (long int) va_arg(va, int); if (l < 0) { ctx.flag |= FLAG_NEGATIVE; l = -l; } - _format_int(&ctx, (uint64_t) l); + _format_int(&ctx, (unsigned long int) l); break; #if !defined (DISABLE_PRINTF_FLOAT) case 'f': @@ -447,14 +446,14 @@ static int _vprintf(const int size, const char *fmt, va_list va) { break; #endif case 'p': - _format_pointer(&ctx, va_arg(va, uint32_t)); + _format_pointer(&ctx, va_arg(va, unsigned int)); break; case 's': s = va_arg(va, const char *); _format_string(&ctx, s); break; case 'u': - lu = ((ctx.flag & FLAG_LONG) != 0) ? va_arg(va, uint64_t) : va_arg(va,uint32_t); + lu = ((ctx.flag & FLAG_LONG) != 0) ? va_arg(va, unsigned long int) : va_arg(va, unsigned int); _format_int(&ctx, lu); break; case 'X': @@ -462,7 +461,7 @@ static int _vprintf(const int size, const char *fmt, va_list va) { /*@fallthrough@*/ /* no break */ case 'x': - _format_hex(&ctx, va_arg(va, uint32_t)); + _format_hex(&ctx, va_arg(va, unsigned int)); break; default: _xputch(&ctx, (int) *fmt); diff --git a/lib-c/src/putchar.c b/lib-clib/src/putchar.c old mode 100644 new mode 100755 similarity index 100% rename from lib-c/src/putchar.c rename to lib-clib/src/putchar.c diff --git a/lib-c/src/puts.c b/lib-clib/src/puts.c old mode 100644 new mode 100755 similarity index 100% rename from lib-c/src/puts.c rename to lib-clib/src/puts.c diff --git a/lib-c/src/random.c b/lib-clib/src/random.c old mode 100644 new mode 100755 similarity index 100% rename from lib-c/src/random.c rename to lib-clib/src/random.c diff --git a/lib-clib/src/strchr.c b/lib-clib/src/strchr.c new file mode 100755 index 00000000..750a42dc --- /dev/null +++ b/lib-clib/src/strchr.c @@ -0,0 +1,55 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include + +/* + * strchr -- + * + * PUBLIC: #ifndef HAVE_STRCHR + * PUBLIC: char *strchr __P((const char *, int)); + * PUBLIC: #endif + */ +char *strchr(const char *p, int ch) +{ + char c; + + c = (char) ch; + for (;; ++p) { + if (*p == c) + return ((char *)p); + if (*p == '\0') + return (NULL); + } + /* NOTREACHED */ +} diff --git a/lib-c/src/strlen.c b/lib-clib/src/strlen.c similarity index 100% rename from lib-c/src/strlen.c rename to lib-clib/src/strlen.c diff --git a/lib-clib/src/strncmp.c b/lib-clib/src/strncmp.c new file mode 100755 index 00000000..77d962a4 --- /dev/null +++ b/lib-clib/src/strncmp.c @@ -0,0 +1,51 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1989, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Portions copyright (c) 2018, Arm Limited and Contributors. + * All rights reserved. + */ + +#include + +int strncmp(const char *s1, const char *s2, size_t n) { + + if (n == 0) + return (0); + do { + if (*s1 != *s2++) + return (*(const unsigned char*) s1 + - *(const unsigned char*) (s2 - 1)); + if (*s1++ == '\0') + break; + } while (--n != 0); + return (0); +} diff --git a/lib-clib/src/strstr.c b/lib-clib/src/strstr.c new file mode 100755 index 00000000..29d74bbb --- /dev/null +++ b/lib-clib/src/strstr.c @@ -0,0 +1,71 @@ +/* + * strstr.c -- + * + * Source code for the "strstr" library routine. + * + * Copyright (c) 1988-1993 The Regents of the University of California. + * Copyright (c) 1994 Sun Microsystems, Inc. + * + * See the file "license.terms" for information on usage and redistribution + * of this file, and for a DISCLAIMER OF ALL WARRANTIES. + * + * RCS: @(#) $Id: strstr.c,v 1.1.1.3 2003/03/06 00:09:04 landonf Exp $ + */ + +/* + *---------------------------------------------------------------------- + * + * strstr -- + * + * Locate the first instance of a substring in a string. + * + * Results: + * If string contains substring, the return value is the + * location of the first matching instance of substring + * in string. If string doesn't contain substring, the + * return value is 0. Matching is done on an exact + * character-for-character basis with no wildcards or special + * characters. + * + * Side effects: + * None. + * + *---------------------------------------------------------------------- + */ + +#include + +char *strstr(const char *string, const char *substring) { + /* First scan quickly through the two strings looking for a + * single-character match. When it's found, then compare the + * rest of the substring. + */ + + const char *b = substring; + + if (*b == 0) { + return (char *)string; + } + + for (; *string != 0; string += 1) { + if (*string != *b) { + continue; + } + + const char *a = string; + + while (1) { + if (*b == 0) { + return (char *)string; + } + + if (*a++ != *b++) { + break; + } + } + + b = substring; + } + + return NULL; +} diff --git a/lib-c/src/strtok.c b/lib-clib/src/strtok.c old mode 100644 new mode 100755 similarity index 100% rename from lib-c/src/strtok.c rename to lib-clib/src/strtok.c diff --git a/lib-clib/src/strtoul.c b/lib-clib/src/strtoul.c new file mode 100755 index 00000000..2581ed15 --- /dev/null +++ b/lib-clib/src/strtoul.c @@ -0,0 +1,118 @@ +#pragma GCC push_options +#pragma GCC diagnostic ignored "-Wsign-conversion" +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Copyright (c) 2011 The FreeBSD Foundation + * All rights reserved. + * Portions of this software were developed by David Chisnall + * under sponsorship from the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include +#include +#include + +static int isspace(int c) { + return (c == '\t' || c == '\n' || c == '\v' || c == '\f' || c == '\r' || c == ' ' ? 1 : 0); +} + +/* + * Convert a string to an unsigned long integer. + * + * Assumes that the upper and lower case + * alphabets and digits are each contiguous. + */ +unsigned long strtoul(const char *nptr, char **endptr, int base) +{ + const char *s; + unsigned long acc; + char c; + unsigned long cutoff; + int neg, any, cutlim; + + /* + * See strtol for comments as to the logic used. + */ + s = nptr; + do { + c = *s++; + } while (isspace((unsigned char)c)); + if (c == '-') { + neg = 1; + c = *s++; + } else { + neg = 0; + if (c == '+') + c = *s++; + } + if ((base == 0 || base == 16) && + c == '0' && (*s == 'x' || *s == 'X') && + ((s[1] >= '0' && s[1] <= '9') || + (s[1] >= 'A' && s[1] <= 'F') || + (s[1] >= 'a' && s[1] <= 'f'))) { + c = s[1]; + s += 2; + base = 16; + } + if (base == 0) + base = c == '0' ? 8 : 10; + acc = any = 0; + + cutoff = ULONG_MAX / base; + cutlim = ULONG_MAX % base; + for ( ; ; c = *s++) { + if (c >= '0' && c <= '9') + c -= '0'; + else if (c >= 'A' && c <= 'Z') + c -= 'A' - 10; + else if (c >= 'a' && c <= 'z') + c -= 'a' - 10; + else + break; + if (c >= base) + break; + if (any < 0 || acc > cutoff || (acc == cutoff && c > cutlim)) + any = -1; + else { + any = 1; + acc *= base; + acc += c; + } + } + if (any < 0) { + acc = ULONG_MAX; + } else if (neg) + acc = -acc; + if (endptr != NULL) + *endptr = (char *)(any ? s - 1 : nptr); + return (acc); +} diff --git a/lib-c/src/time.c b/lib-clib/src/time.cpp old mode 100644 new mode 100755 similarity index 54% rename from lib-c/src/time.c rename to lib-clib/src/time.cpp index 0f08b958..86fe621b --- a/lib-c/src/time.c +++ b/lib-clib/src/time.cpp @@ -1,8 +1,8 @@ /** - * @file time.c + * @file time.cpp * */ -/* Copyright (C) 2016-2019 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2016-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,12 +23,19 @@ * THE SOFTWARE. */ -#include +#include + +#include +#include #include -static const int days_of_month[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; +namespace global { +int32_t *gp_nUtcOffset; +} // namespace global + +static constexpr int days_of_month[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; -static int isleapyear(int year) { +static int isleapyear(const int year) { if (year % 100 == 0) { return year % 400 == 0; } @@ -36,7 +43,7 @@ static int isleapyear(int year) { return year % 4 == 0; } -static int getdaysofmonth(int month, int year) { +static int getdaysofmonth(const int month, const int year) { if ((month == 1) && isleapyear(year)) { return 29; } @@ -46,106 +53,120 @@ static int getdaysofmonth(int month, int year) { static struct tm Tm; +extern "C" { + struct tm *localtime(const time_t *pTime) { - int nYear; - int nMonth; + if (pTime == nullptr) { + return nullptr; + } + + auto nTime = *pTime + *global::gp_nUtcOffset; + return gmtime(&nTime); +} - if (pTime == 0) { - return NULL; +struct tm *gmtime(const time_t *pTime) { + if (pTime == nullptr) { + return nullptr; } - time_t Time = *pTime; + auto nTime = *pTime; - Tm.tm_sec = Time % 60; - Time /= 60; - Tm.tm_min = Time % 60; - Time /= 60; - Tm.tm_hour = Time % 24; - Time /= 24; + Tm.tm_sec = nTime % 60; + nTime /= 60; + Tm.tm_min = nTime % 60; + nTime /= 60; + Tm.tm_hour = nTime % 24; + nTime /= 24; - Tm.tm_wday = (Time + 4) % 7; + Tm.tm_wday = (nTime + 4) % 7; + + int nYear = 1970; - nYear = 1970; while (1) { - int nDaysOfYear = isleapyear(nYear) ? 366 : 365; - if (Time < nDaysOfYear) { + const time_t nDaysOfYear = isleapyear(nYear) ? 366 : 365; + if (nTime < nDaysOfYear) { break; } - Time -= nDaysOfYear; + nTime -= nDaysOfYear; nYear++; } Tm.tm_year = nYear - 1900; - Tm.tm_yday = Time; + Tm.tm_yday = nTime; + + int nMonth = 0; - nMonth = 0; while (1) { - int nDaysOfMonth = getdaysofmonth(nMonth, nYear); - if (Time < nDaysOfMonth) { + const time_t nDaysOfMonth = getdaysofmonth(nMonth, nYear); + if (nTime < nDaysOfMonth) { break; } - Time -= nDaysOfMonth; + nTime -= nDaysOfMonth; nMonth++; } Tm.tm_mon = nMonth; - Tm.tm_mday = Time + 1; + Tm.tm_mday = nTime + 1; return &Tm; } time_t mktime(struct tm *pTm) { - int year, month; - time_t result = 0; + time_t nResult = 0; - if (pTm == NULL) { - return (time_t) -1; + if (pTm == nullptr) { + return -1; } if (pTm->tm_year < 70 || pTm->tm_year > 139) { - return (time_t) -1; + return -1; } - for (year = 1970; year < 1900 + pTm->tm_year; year++) { - result += isleapyear(year) ? 366 : 365; + int nYear; + + for (nYear = 1970; nYear < 1900 + pTm->tm_year; nYear++) { + nResult += isleapyear(nYear) ? 366 : 365; } if (pTm->tm_mon < 0 || pTm->tm_mon > 11) { - return (time_t) -1; + return -1; } - for (month = 0; month < pTm->tm_mon; month++) { - result += getdaysofmonth(month, pTm->tm_year); + int nMonth; + + for (nMonth = 0; nMonth < pTm->tm_mon; nMonth++) { + nResult += getdaysofmonth(nMonth, pTm->tm_year); } if (pTm->tm_mday < 1 || pTm->tm_mday > getdaysofmonth(pTm->tm_mon, pTm->tm_year)) { - return (time_t) -1; + return -1; } - result += pTm->tm_mday - 1; - result *= 24; + nResult += pTm->tm_mday - 1; + nResult *= 24; if (pTm->tm_hour < 0 || pTm->tm_hour > 23) { - return (time_t) -1; + return -1; } - result += pTm->tm_hour; - result *= 60; + nResult += pTm->tm_hour; + nResult *= 60; if (pTm->tm_min < 0 || pTm->tm_min > 59) { - return (time_t) -1; + return -1; } - result += pTm->tm_min; - result *= 60; + nResult += pTm->tm_min; + nResult *= 60; if (pTm->tm_sec < 0 || pTm->tm_sec > 59) { - return (time_t) -1; + return -1; } - result += pTm->tm_sec; + nResult += pTm->tm_sec; - return result; + return nResult; +} } diff --git a/lib-uuid/src/uuid_internal.h b/lib-clib/src/uuid_internal.h old mode 100644 new mode 100755 similarity index 100% rename from lib-uuid/src/uuid_internal.h rename to lib-clib/src/uuid_internal.h diff --git a/lib-uuid/src/uuid_parse.c b/lib-clib/src/uuid_parse.c old mode 100644 new mode 100755 similarity index 100% rename from lib-uuid/src/uuid_parse.c rename to lib-clib/src/uuid_parse.c diff --git a/lib-uuid/src/uuid_unparse.c b/lib-clib/src/uuid_unparse.c old mode 100644 new mode 100755 similarity index 100% rename from lib-uuid/src/uuid_unparse.c rename to lib-clib/src/uuid_unparse.c diff --git a/lib-configstore/.cproject b/lib-configstore/.cproject index 03798c82..b20e7f9f 100755 --- a/lib-configstore/.cproject +++ b/lib-configstore/.cproject @@ -30,13 +30,10 @@ - - @@ -114,13 +106,10 @@ - - - diff --git a/lib-configstore/.settings/language.settings.xml b/lib-configstore/.settings/language.settings.xml index 04d74f25..797b2f1b 100755 --- a/lib-configstore/.settings/language.settings.xml +++ b/lib-configstore/.settings/language.settings.xml @@ -2,7 +2,7 @@ - + diff --git a/lib-configstore/Rules.mk b/lib-configstore/Rules.mk old mode 100644 new mode 100755 index 31498ee5..af700683 --- a/lib-configstore/Rules.mk +++ b/lib-configstore/Rules.mk @@ -1,7 +1,6 @@ $(info $$MAKE_FLAGS [${MAKE_FLAGS}]) -EXTRA_INCLUDES =../lib-flashcode/include ../lib-flash/include -EXTRA_INCLUDES+=../lib-hal/include ../lib-properties/include ../lib-lightset/include ../lib-network/include +EXTRA_INCLUDES+=../lib-properties/include ifneq ($(MAKE_FLAGS),) ifneq (,$(findstring CONFIG_STORE_USE_FILE,$(MAKE_FLAGS))) @@ -23,153 +22,10 @@ ifneq ($(MAKE_FLAGS),) ifneq (,$(findstring CONFIG_STORE_USE_SPI,$(MAKE_FLAGS))) EXTRA_SRCDIR+=device/spi endif - - RDM= - - ifneq (,$(findstring ESP8266,$(MAKE_FLAGS))) - EXTRA_SRCDIR+=src/network - EXTRA_INCLUDES+=../lib-network/include - # Remote config is not used with ESP8266 - EXTRA_INCLUDES+=../lib-remoteconfig/include - endif - - ifeq (,$(findstring NO_EMAC,$(MAKE_FLAGS))) - EXTRA_SRCDIR+=src/network - EXTRA_INCLUDES+=../lib-network/include - EXTRA_INCLUDES+=../lib-remoteconfig/include - endif - - ifeq ($(findstring DISPLAY_UDF,$(MAKE_FLAGS)), DISPLAY_UDF) - EXTRA_SRCDIR+=src/displayudf - EXTRA_INCLUDES+=../lib-displayudf/include - endif - - ifeq ($(findstring NODE_ARTNET,$(MAKE_FLAGS)), NODE_ARTNET) - EXTRA_SRCDIR+=src/artnet - EXTRA_INCLUDES+=../lib-artnet/include - EXTRA_SRCDIR+=src/rdm - RDM=1 - EXTRA_INCLUDES+=../lib-rdm/include ../lib-rdmsensor/include ../lib-rdmsubdevice/include - ifeq ($(findstring ARTNET_VERSION=4,$(MAKE_FLAGS)), ARTNET_VERSION=4) - EXTRA_INCLUDES+=../lib-e131/include - endif - endif - - ifeq ($(findstring NODE_E131,$(MAKE_FLAGS)), NODE_E131) - EXTRA_SRCDIR+=src/e131 - EXTRA_INCLUDES+=../lib-e131/include - endif - - ifeq ($(findstring NODE_LTC_SMPTE,$(MAKE_FLAGS)), NODE_LTC_SMPTE) - EXTRA_SRCDIR+=src/ltc - EXTRA_INCLUDES+=../lib-ltc/include ../lib-tcnet/include - EXTRA_INCLUDES+=../lib-gps/include - EXTRA_INCLUDES+=../lib-rgbpanel/include - EXTRA_INCLUDES+=../lib-ws28xx/include - endif - - ifeq ($(findstring NODE_NODE,$(MAKE_FLAGS)), NODE_NODE) - EXTRA_SRCDIR+=src/node - EXTRA_INCLUDES+=../lib-node/include - EXTRA_INCLUDES+=../lib-artnet/include ../lib-rdmdiscovery/include - EXTRA_INCLUDES+=../lib-e131/include - endif - - ifeq ($(findstring NODE_OSC_CLIENT,$(MAKE_FLAGS)), NODE_OSC_CLIENT) - EXTRA_SRCDIR+=src/oscclient - EXTRA_INCLUDES+=../lib-oscclient/include - endif - - ifeq ($(findstring OUTPUT_DMX_SEND,$(MAKE_FLAGS)),OUTPUT_DMX_SEND) - EXTRA_SRCDIR+=src/dmx - EXTRA_INCLUDES+=../lib-dmx/include - endif - - ifeq ($(findstring OUTPUT_DMX_PIXEL,$(MAKE_FLAGS)), OUTPUT_DMX_PIXEL) - EXTRA_SRCDIR+=src/pixel - EXTRA_INCLUDES+=../lib-ws28xxdmx/include ../lib-ws28xx/include - endif - - ifeq ($(findstring OUTPUT_DMX_SHOWFILE,$(MAKE_FLAGS)), OUTPUT_DMX_SHOWFILE) - EXTRA_SRCDIR+=src/showfile - EXTRA_INCLUDES+=../lib-showfile/include - endif - - ifeq ($(findstring OUTPUT_DMX_SERIAL,$(MAKE_FLAGS)), OUTPUT_DMX_SERIAL) - EXTRA_SRCDIR+=src/dmxserial - EXTRA_INCLUDES+=../lib-dmxserial/include - endif - - ifeq ($(findstring OUTPUT_DMX_STEPPER,$(MAKE_FLAGS)), OUTPUT_DMX_STEPPER) - EXTRA_SRCDIR+=src/stepper - EXTRA_INCLUDES+=../lib-l6470dmx/include ../lib-l6470/include - endif - - ifeq ($(findstring OUTPUT_DMX_TLC59711,$(MAKE_FLAGS)), OUTPUT_DMX_TLC59711) - EXTRA_SRCDIR+=src/tlc59711 - EXTRA_INCLUDES+=../lib-tlc59711dmx/include ../lib-tlc59711/include - endif - - ifeq ($(findstring RDM_CONTROLLER,$(MAKE_FLAGS)), RDM_CONTROLLER) - ifdef RDM - else - EXTRA_SRCDIR+=src/rdm - RDM=1 - endif - endif - - ifeq ($(findstring RDM_RESPONDER,$(MAKE_FLAGS)), RDM_RESPONDER) - ifdef RDM - else - EXTRA_SRCDIR+=src/rdm - RDM=1 - endif - EXTRA_INCLUDES+=../lib-rdmresponder/include - endif - - ifeq ($(findstring NODE_RDMNET_LLRP_ONLY,$(MAKE_FLAGS)), NODE_RDMNET_LLRP_ONLY) - ifdef RDM - else - EXTRA_SRCDIR+=src/rdm - RDM=1 - endif - EXTRA_INCLUDES+=../lib-rdm/include ../lib-rdmsensor/include ../lib-rdmsubdevice/include - endif - - ifeq ($(findstring WIDGET_HAVE_FLASHROM,$(MAKE_FLAGS)), WIDGET_HAVE_FLASHROM) - EXTRA_SRCDIR+=src/widget - EXTRA_INCLUDES+=../lib-widget/include - endif else - EXTRA_SRCDIR+=src/artnet - EXTRA_INCLUDES+=../lib-artnet/include - EXTRA_SRCDIR+=src/e131 - EXTRA_INCLUDES+=../lib-e131/include - EXTRA_SRCDIR+=src/node - EXTRA_INCLUDES+=../lib-node/include ../lib-rdmdiscovery/include - EXTRA_SRCDIR+=src/ltc - EXTRA_INCLUDES+=../lib-ltc/include ../lib-tcnet/include - EXTRA_INCLUDES+=../lib-gps/include - EXTRA_INCLUDES+=../lib-rgbpanel/include - EXTRA_INCLUDES+=../lib-ws28xx/include - EXTRA_SRCDIR+=src/rdm - EXTRA_INCLUDES+=../lib-rdm/include ../lib-rdmsensor/include ../lib-rdmsubdevice/include - EXTRA_SRCDIR+=src/stepper - EXTRA_INCLUDES+=../lib-l6470dmx/include ../lib-l6470/include - EXTRA_INCLUDES+=../lib-tlc59711dmx/include ../lib-tlc59711/include - - DEFINES+=ARTNET_VERSION=4 - DEFINES+=LIGHTSET_PORTS=4 - DEFINES+=CONFIG_PIXELDMX_MAX_PORTS=8 - DEFINES+=CONFIG_DDPDISPLAY_MAX_PORTS=8 + EXTRA_SRCDIR+=device/file + EXTRA_SRCDIR+=device/i2c + EXTRA_SRCDIR+=device/ram + EXTRA_SRCDIR+=device/rom + EXTRA_SRCDIR+=device/spi endif - -EXTRA_INCLUDES+=../lib-displayudf/include ../lib-display/include -EXTRA_INCLUDES+=../lib-dmxsend/include -EXTRA_INCLUDES+=../lib-dmxmonitor/include -EXTRA_INCLUDES+=../lib-dmxreceiver/include ../lib-dmx/include -EXTRA_INCLUDES+=../lib-oscserver/include -EXTRA_INCLUDES+=../lib-rdm/include ../lib-rdmsensor/include ../lib-rdmsubdevice/include -EXTRA_INCLUDES+=../lib-spiflashinstall/include -EXTRA_INCLUDES+=../lib-device/include -EXTRA_INCLUDES+=../lib-midi/include \ No newline at end of file diff --git a/lib-configstore/device/rom/storedevice.cpp b/lib-configstore/device/rom/storedevice.cpp old mode 100644 new mode 100755 index d9be65d9..f06bad45 --- a/lib-configstore/device/rom/storedevice.cpp +++ b/lib-configstore/device/rom/storedevice.cpp @@ -26,8 +26,7 @@ #include #include -#include "storedevice.h" - +#include "configstoredevice.h" #include "flashcode.h" #include "debug.h" diff --git a/lib-configstore/device/spi/storedevice.cpp b/lib-configstore/device/spi/storedevice.cpp old mode 100644 new mode 100755 index 4f3cb7f5..cb3078f6 --- a/lib-configstore/device/spi/storedevice.cpp +++ b/lib-configstore/device/spi/storedevice.cpp @@ -2,7 +2,7 @@ * @file storedevice.cpp * */ -/* Copyright (C) 2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,8 +26,9 @@ #include #include -#include "storedevice.h" +#include "configstoredevice.h" #include "spi/spi_flash.h" + #include "debug.h" StoreDevice::StoreDevice() { @@ -38,9 +39,9 @@ StoreDevice::StoreDevice() { } else { printf("StoreDevice: Detected %s with sector size %u total %u bytes [%u kB]\n", spi_flash_get_name(), - spi_flash_get_sector_size(), - spi_flash_get_size(), - spi_flash_get_size() / 1024U); + static_cast(spi_flash_get_sector_size()), + static_cast(spi_flash_get_size()), + static_cast(spi_flash_get_size() / 1024U)); m_IsDetected = true; } diff --git a/lib-configstore/include/configstore.h b/lib-configstore/include/configstore.h index 73b23ae1..bb69861c 100644 --- a/lib-configstore/include/configstore.h +++ b/lib-configstore/include/configstore.h @@ -2,7 +2,7 @@ * @file configstore.h * */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,8 +27,14 @@ #define CONFIGSTORE_H_ #include +#include +#include -#include "storedevice.h" +#include "configstoredevice.h" + +#include "utc.h" + +#include "debug.h" namespace configstore { enum class Store { @@ -58,13 +64,13 @@ enum class Store { GPS, RGBPANEL, NODE, + PCA9685, LAST }; enum class State { IDLE, CHANGED, CHANGED_WAITING, ERASING, ERASED, ERASED_WAITING, WRITING }; - } // namespace configstore class ConfigStore: StoreDevice { @@ -75,18 +81,19 @@ class ConfigStore: StoreDevice { ; } - bool HaveFlashChip() const { - return s_bHaveFlashChip; - } - void Update(configstore::Store store, uint32_t nOffset, const void *pData, uint32_t nDataLength, uint32_t nSetList = 0, uint32_t nOffsetSetList = 0); void Update(configstore::Store store, const void *pData, uint32_t nDataLength) { Update(store, 0, pData, nDataLength); } - void Copy(const configstore::Store store, void *pData, uint32_t nDataLength, uint32_t nOffset = 0); + void Copy(const configstore::Store store, void *pData, uint32_t nDataLength, uint32_t nOffset = 0, const bool doUpdate = true); void ResetSetList(configstore::Store store); + void ResetSetListAll() { + for (uint32_t i = 0; i < static_cast(configstore::Store::LAST); i++) { + ResetSetList(static_cast(i)); + } + } bool Flash(); @@ -94,6 +101,53 @@ class ConfigStore: StoreDevice { void Delay(); + /* + * Environment + */ + + bool SetEnvUtcOffset(const int8_t nHours, const uint8_t nMinutes) { + int32_t nUtcOffset; + + DEBUG_PRINTF("nHours=%d, nMinutes =%u", nHours, nMinutes); + + if (hal::utc_validate(nHours, nMinutes, nUtcOffset)) { + auto *p = reinterpret_cast(&s_SpiFlashData[FlashStore::SIGNATURE_SIZE]); + + if (p->nUtcOffset != nUtcOffset) { + p->nUtcOffset = nUtcOffset; + s_State = configstore::State::CHANGED; + } + + DEBUG_EXIT + return true; + } + + DEBUG_EXIT + return false; + } + + void GetEnvUtcOffset(int8_t& nHours, uint8_t& nMinutes) { + const auto *p = reinterpret_cast(&s_SpiFlashData[FlashStore::SIGNATURE_SIZE]); + + DEBUG_PRINTF("p->nUtcOffset=%d", p->nUtcOffset); + + assert((p->nUtcOffset / 3600) <= INT8_MAX); + assert((p->nUtcOffset / 3600) >= INT8_MIN); + + nHours = static_cast(p->nUtcOffset / 3600); + + if (nHours > 0) { + nMinutes = static_cast(static_cast(p->nUtcOffset - (nHours * 3600)) / 60U); + } else { + nMinutes = static_cast(static_cast((nHours * 3600) - p->nUtcOffset) / 60U); + } + } + + int32_t GetEnvUtcOffset() const { + const auto *p = reinterpret_cast(&s_SpiFlashData[FlashStore::SIGNATURE_SIZE]); + return p->nUtcOffset; + } + static ConfigStore *Get() { return s_pThis; } @@ -102,10 +156,20 @@ class ConfigStore: StoreDevice { uint32_t GetStoreOffset(configstore::Store tStore); private: + struct Env { + int32_t nUtcOffset; + uint8_t filler[12]; + }; + struct FlashStore { - static constexpr auto SIZE = 4096U; + static constexpr uint32_t SIGNATURE_SIZE = 16; + static constexpr uint32_t ENV_SIZE = 16; + static constexpr uint32_t OFFSET_STORES = SIGNATURE_SIZE + ENV_SIZE; + static constexpr uint32_t SIZE = 4096; }; + static_assert(sizeof(struct Env) == FlashStore::ENV_SIZE, ""); + static bool s_bHaveFlashChip; static configstore::State s_State; diff --git a/lib-configstore/include/storedevice.h b/lib-configstore/include/configstoredevice.h old mode 100644 new mode 100755 similarity index 100% rename from lib-configstore/include/storedevice.h rename to lib-configstore/include/configstoredevice.h diff --git a/lib-configstore/include/envparams.h b/lib-configstore/include/envparams.h new file mode 100755 index 00000000..63333890 --- /dev/null +++ b/lib-configstore/include/envparams.h @@ -0,0 +1,48 @@ +/** + * @file envparams.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef ENVPARAMS_H_ +#define ENVPARAMS_H_ + +#include + +class EnvParams { +public: + EnvParams(); + + void LoadAndSet(); + void LoadAndSet(const char *pBuffer, uint32_t nLength); + + void Builder(char *pBuffer, uint32_t nLength, uint32_t& nSize); + +public: + static void staticCallbackFunction(void *p, const char *s); + +private: + void Dump(); + void callbackFunction(const char *s); +}; + +#endif /* ENVPARAMS_H_ */ diff --git a/lib-configstore/include/envparamsconst.h b/lib-configstore/include/envparamsconst.h new file mode 100755 index 00000000..dcc2ea25 --- /dev/null +++ b/lib-configstore/include/envparamsconst.h @@ -0,0 +1,35 @@ +/** + * @file envparamsconst.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef ENVPARAMSCONST_H_ +#define ENVPARAMSCONST_H_ + +struct EnvParamsConst { + static const char FILE_NAME[]; + + static const char UTC_OFFSET[]; +}; + +#endif /* ENVPARAMSCONST_H_ */ diff --git a/lib-configstore/include/storeartnet.h b/lib-configstore/include/storeartnet.h deleted file mode 100644 index ab90a6ba..00000000 --- a/lib-configstore/include/storeartnet.h +++ /dev/null @@ -1,113 +0,0 @@ -/** - * @file storeartnet.h - * - */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef STOREARTNET_H_ -#define STOREARTNET_H_ - -#include "artnetparams.h" -#include "artnetstore.h" -#include "configstore.h" - -#include "debug.h" - -class StoreArtNet final: public ArtNetParamsStore, public ArtNetStore { -public: - StoreArtNet(uint32_t nPortIndexOffset); - - void Update(const struct artnetparams::Params* pArtNetParams) override { - DEBUG_ENTRY - - ConfigStore::Get()->Update(configstore::Store::NODE, pArtNetParams, sizeof(struct artnetparams::Params)); - - DEBUG_EXIT - } - - void Copy(struct artnetparams::Params* pArtNetParams) override { - DEBUG_ENTRY - - ConfigStore::Get()->Copy(configstore::Store::NODE, pArtNetParams, sizeof(struct artnetparams::Params)); - - DEBUG_EXIT - } - - void SaveLongName(const char* pLongName) override { - DEBUG_ENTRY - - ConfigStore::Get()->Update(configstore::Store::NODE, __builtin_offsetof(struct artnetparams::Params, aLongName), pLongName, artnet::LONG_NAME_LENGTH, artnetparams::Mask::LONG_NAME); - - DEBUG_EXIT - } - - void SaveFailSafe(const uint8_t nFailSafe) override { - DEBUG_ENTRY - - ConfigStore::Get()->Update(configstore::Store::NODE, __builtin_offsetof(struct artnetparams::Params, nFailSafe), &nFailSafe, sizeof(uint8_t), artnetparams::Mask::FAILSAFE); - - DEBUG_EXIT - } - - void SaveUniverseSwitch(const uint32_t nPortIndex, __attribute__((unused)) const uint8_t nAddress) override { - DEBUG_ENTRY - - SaveUniverse(nPortIndex); - - DEBUG_EXIT - } - - void SaveNetSwitch(const uint32_t nPortIndex, __attribute__((unused)) const uint8_t nAddress) override { - DEBUG_ENTRY - - SaveUniverse(nPortIndex); - - DEBUG_EXIT - } - - void SaveSubnetSwitch(const uint32_t nPortIndex, __attribute__((unused)) const uint8_t nAddress) override { - DEBUG_ENTRY - - SaveUniverse(nPortIndex); - - DEBUG_EXIT - } - - void SaveShortName(uint32_t nPortIndex, const char *pShortName) override; - void SaveMergeMode(uint32_t nPortIndex, const lightset::MergeMode tMerge) override; - void SavePortProtocol(uint32_t nPortIndex, const artnet::PortProtocol tPortProtocol) override; - void SaveOutputStyle(uint32_t nPortIndex, const lightset::OutputStyle outputStyle) override; - void SaveRdmEnabled(uint32_t nPortIndex, bool isEnabled) override; - - static StoreArtNet *Get() { - return s_pThis; - } - -private: - void SaveUniverse(uint32_t nPortIndex); - -private: - static uint32_t s_nPortIndexOffset; - static StoreArtNet *s_pThis; -}; - -#endif /* STOREARTNET_H_ */ diff --git a/lib-configstore/include/storedisplayudf.h b/lib-configstore/include/storedisplayudf.h deleted file mode 100644 index 51241259..00000000 --- a/lib-configstore/include/storedisplayudf.h +++ /dev/null @@ -1,53 +0,0 @@ -/** - * @file storedisplayudf.h - * - */ -/* Copyright (C) 2019-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef STOREDISPLAYUDF_H_ -#define STOREDISPLAYUDF_H_ - -#include "displayudfparams.h" - -#include "configstore.h" - -class StoreDisplayUdf final: public DisplayUdfParamsStore { -public: - StoreDisplayUdf(); - - void Update(const struct displayudfparams::Params *pDisplayUdfParams) override { - ConfigStore::Get()->Update(configstore::Store::DISPLAYUDF, pDisplayUdfParams, sizeof(struct displayudfparams::Params)); - } - - void Copy(struct displayudfparams::Params *pDisplayUdfParams) override { - ConfigStore::Get()->Copy(configstore::Store::DISPLAYUDF, pDisplayUdfParams, sizeof(struct displayudfparams::Params)); - } - - static StoreDisplayUdf *Get() { - return s_pThis; - } - -private: - static StoreDisplayUdf *s_pThis; -}; - -#endif /* STOREDISPLAYUDF_H_ */ diff --git a/lib-configstore/include/storedmxsend.h b/lib-configstore/include/storedmxsend.h deleted file mode 100644 index 778db640..00000000 --- a/lib-configstore/include/storedmxsend.h +++ /dev/null @@ -1,53 +0,0 @@ -/** - * @file storedmxsend.h - * - */ -/* Copyright (C) 2018-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef STOREDMXSEND_H_ -#define STOREDMXSEND_H_ - -#include "dmxparams.h" - -#include "configstore.h" - -class StoreDmxSend final: public DmxParamsStore { -public: - StoreDmxSend(); - - void Update(const struct TDmxParams *pDmxParams) override { - ConfigStore::Get()->Update(configstore::Store::DMXSEND, pDmxParams, sizeof(struct TDmxParams)); - } - - void Copy(struct TDmxParams *pDmxParams) override { - ConfigStore::Get()->Copy(configstore::Store::DMXSEND, pDmxParams, sizeof(struct TDmxParams)); - } - - static StoreDmxSend *Get() { - return s_pThis; - } - -private: - static StoreDmxSend *s_pThis; -}; - -#endif /* STOREDMXSEND_H_ */ diff --git a/lib-configstore/include/storee131.h b/lib-configstore/include/storee131.h deleted file mode 100644 index dcfb131e..00000000 --- a/lib-configstore/include/storee131.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * @file storee131.h - * - */ -/* Copyright (C) 2018-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef STOREE131_H_ -#define STOREE131_H_ - -#include "e131params.h" -#include "configstore.h" - -class StoreE131 final: public E131ParamsStore { -public: - StoreE131(); - - void Update(const struct e131params::Params *pParams) override { - ConfigStore::Get()->Update(configstore::Store::NODE, pParams, sizeof(struct e131params::Params)); - } - - void Copy(struct e131params::Params *pParams) override { - ConfigStore::Get()->Copy(configstore::Store::NODE, pParams, sizeof(struct e131params::Params)); - } - - static StoreE131* Get() { - return s_pThis; - } - -private: - static StoreE131 *s_pThis; -}; - -#endif /* STOREE131_H_ */ diff --git a/lib-configstore/include/storenetwork.h b/lib-configstore/include/storenetwork.h deleted file mode 100644 index 427c05b5..00000000 --- a/lib-configstore/include/storenetwork.h +++ /dev/null @@ -1,76 +0,0 @@ -/** - * @file storenetwork.h - * - */ -/* Copyright (C) 2018-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef STORENETWORK_H_ -#define STORENETWORK_H_ - -#include - -#include "network.h" -#include "networkparams.h" -#include "configstore.h" - -class StoreNetwork final: public NetworkParamsStore, public NetworkStore { -public: - StoreNetwork(); - - void Update(const struct networkparams::Params *pNetworkParams) override { - ConfigStore::Get()->Update(configstore::Store::NETWORK, pNetworkParams, sizeof(struct networkparams::Params)); - } - - void Copy(struct networkparams::Params *pNetworkParams) override { - ConfigStore::Get()->Copy(configstore::Store::NETWORK, pNetworkParams, sizeof(struct networkparams::Params)); - } - - void SaveIp(uint32_t nIp) override { - ConfigStore::Get()->Update(configstore::Store::NETWORK, __builtin_offsetof(struct networkparams::Params, nLocalIp), &nIp, sizeof(uint32_t), networkparams::Mask::IP_ADDRESS); - } - - void SaveNetMask(uint32_t nNetMask) override { - ConfigStore::Get()->Update(configstore::Store::NETWORK, __builtin_offsetof(struct networkparams::Params, nNetmask), &nNetMask, sizeof(uint32_t), networkparams::Mask::NET_MASK); - } - - void SaveGatewayIp(uint32_t nGatewayIp) override { - ConfigStore::Get()->Update(configstore::Store::NETWORK, __builtin_offsetof(struct networkparams::Params, nGatewayIp), &nGatewayIp, sizeof(uint32_t), networkparams::Mask::DEFAULT_GATEWAY); - } - - void SaveHostName(const char *pHostName, uint32_t nLength) override { - nLength = std::min(nLength,static_cast(network::HOSTNAME_SIZE)); - ConfigStore::Get()->Update(configstore::Store::NETWORK, __builtin_offsetof(struct networkparams::Params, aHostName), pHostName, nLength, networkparams::Mask::HOSTNAME); - } - - void SaveDhcp(bool bIsDhcpUsed) override { - ConfigStore::Get()->Update(configstore::Store::NETWORK, __builtin_offsetof(struct networkparams::Params, bIsDhcpUsed), &bIsDhcpUsed, sizeof(bool), networkparams::Mask::DHCP); - } - - static StoreNetwork *Get() { - return s_pThis; - } - -private: - static StoreNetwork *s_pThis; -}; - -#endif /* STORENETWORK_H_ */ diff --git a/lib-configstore/include/storepixeldmx.h b/lib-configstore/include/storepixeldmx.h deleted file mode 100644 index 653e6fc1..00000000 --- a/lib-configstore/include/storepixeldmx.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - * @file storepixeldmx.h - * - */ -/* Copyright (C) 2018-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef STOREPIXELDMX_H_ -#define STOREPIXELDMX_H_ - -#include -#include -#include - -#include "pixeldmxstore.h" -#include "configstore.h" - -class StorePixelDmx final: public PixelDmxParamsStore, public PixelDmxStore { -public: - StorePixelDmx(); - - void Update(const struct pixeldmxparams::Params *pWS28xxDmxParams) override { - ConfigStore::Get()->Update(configstore::Store::WS28XXDMX, pWS28xxDmxParams, sizeof(struct pixeldmxparams::Params)); - } - - void Copy(struct pixeldmxparams::Params *pWS28xxDmxParams) override { - ConfigStore::Get()->Copy(configstore::Store::WS28XXDMX, pWS28xxDmxParams, sizeof(struct pixeldmxparams::Params)); - } - - void SaveType(uint8_t nType) override { - ConfigStore::Get()->Update(configstore::Store::WS28XXDMX, __builtin_offsetof(struct pixeldmxparams::Params, nType), &nType, sizeof(uint8_t), pixeldmxparams::Mask::TYPE); - } - - void SaveCount(uint16_t nCount) override { - ConfigStore::Get()->Update(configstore::Store::WS28XXDMX, __builtin_offsetof(struct pixeldmxparams::Params, nCount), &nCount, sizeof(uint16_t), pixeldmxparams::Mask::COUNT); - } - - void SaveGroupingCount(uint16_t nGroupingCount) override { - ConfigStore::Get()->Update(configstore::Store::WS28XXDMX, __builtin_offsetof(struct pixeldmxparams::Params, nGroupingCount), &nGroupingCount, sizeof(uint16_t), pixeldmxparams::Mask::GROUPING_COUNT); - } - - void SaveMap(uint8_t nMap) override { - ConfigStore::Get()->Update(configstore::Store::WS28XXDMX, __builtin_offsetof(struct pixeldmxparams::Params, nMap), &nMap, sizeof(uint8_t), pixeldmxparams::Mask::MAP); - } - - void SaveTestPattern(uint8_t nTestPattern) override { - ConfigStore::Get()->Update(configstore::Store::WS28XXDMX, __builtin_offsetof(struct pixeldmxparams::Params, nTestPattern), &nTestPattern, sizeof(uint8_t), pixeldmxparams::Mask::TEST_PATTERN); - } - - void SaveDmxStartAddress(uint16_t nDmxStartAddress) override { - ConfigStore::Get()->Update(configstore::Store::WS28XXDMX, __builtin_offsetof(struct pixeldmxparams::Params, nDmxStartAddress), &nDmxStartAddress, sizeof(uint16_t), pixeldmxparams::Mask::DMX_START_ADDRESS); - } - - static StorePixelDmx *Get() { - return s_pThis; - } - -private: - static StorePixelDmx *s_pThis; -}; - -#endif /* STOREPIXELDMX_H_ */ diff --git a/lib-configstore/include/storerdmdevice.h b/lib-configstore/include/storerdmdevice.h deleted file mode 100644 index 59269875..00000000 --- a/lib-configstore/include/storerdmdevice.h +++ /dev/null @@ -1,61 +0,0 @@ -/** - * @file storerdmdevice.h - * - */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef STORERDMDEVICE_H_ -#define STORERDMDEVICE_H_ - -#include - -#include "rdmdeviceparams.h" -#include "rdmdevicestore.h" - -#include "configstore.h" - -class StoreRDMDevice final: public RDMDeviceParamsStore, public RDMDeviceStore { -public: - StoreRDMDevice(); - - void Update(const struct rdm::deviceparams::Params *pParams) override { - ConfigStore::Get()->Update(configstore::Store::RDMDEVICE, pParams, sizeof(struct rdm::deviceparams::Params)); - } - - void Copy(struct rdm::deviceparams::Params *pRDMDeviceParams) override { - ConfigStore::Get()->Copy(configstore::Store::RDMDEVICE, pRDMDeviceParams, sizeof(struct rdm::deviceparams::Params)); - } - - void SaveLabel(const char *pLabel, uint8_t nLength) override { - ConfigStore::Get()->Update(configstore::Store::RDMDEVICE, __builtin_offsetof(struct rdm::deviceparams::Params, aDeviceRootLabel), pLabel, nLength, rdm::deviceparams::Mask::LABEL); - ConfigStore::Get()->Update(configstore::Store::RDMDEVICE, __builtin_offsetof(struct rdm::deviceparams::Params, nDeviceRootLabelLength), &nLength, sizeof(uint8_t), rdm::deviceparams::Mask::LABEL); - } - - static StoreRDMDevice *Get() { - return s_pThis; - } - -private: - static StoreRDMDevice *s_pThis; -}; - -#endif /* STORERDMDEVICE_H_ */ diff --git a/lib-configstore/include/storerdmsensors.h b/lib-configstore/include/storerdmsensors.h deleted file mode 100644 index d3b36a08..00000000 --- a/lib-configstore/include/storerdmsensors.h +++ /dev/null @@ -1,67 +0,0 @@ -/** - * @file storerdmsensors.h - * - */ -/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef STORERDMSENSORS_H_ -#define STORERDMSENSORS_H_ - -#include -#include - -#include "rdmsensorsparams.h" -#include "rdmsensorstore.h" -#include "rdmsensors.h" - -#include "configstore.h" - -#include "debug.h" //FIXME Remove - -class StoreRDMSensors final: public RDMSensorsParamsStore, public RDMSensorStore { -public: - StoreRDMSensors(); - - void Update(const rdm::sensorsparams::Params *pParams) override { - ConfigStore::Get()->Update(configstore::Store::RDMSENSORS, pParams, sizeof(struct rdm::sensorsparams::Params)); - } - - void Copy(rdm::sensorsparams::Params *pParams) override { - ConfigStore::Get()->Copy(configstore::Store::RDMSENSORS, pParams, sizeof(struct rdm::sensorsparams::Params)); - } - - void SaveCalibration(uint32_t nSensor, int32_t nCalibration) override { - assert(nSensor < rdm::sensors::MAX); - DEBUG_PRINTF("nSensor=%u, nCalibration=%d", nSensor, nCalibration); - auto c = static_cast(nCalibration); - ConfigStore::Get()->Update(configstore::Store::RDMSENSORS, (nSensor * sizeof(int16_t)) + __builtin_offsetof(struct rdm::sensorsparams::Params, nCalibrate), &c, sizeof(int16_t)); - } - - static StoreRDMSensors *Get() { - return s_pThis; - } - -private: - static StoreRDMSensors *s_pThis; -}; - -#endif /* STORERDMSENSORS_H_ */ diff --git a/lib-configstore/include/storeremoteconfig.h b/lib-configstore/include/storeremoteconfig.h deleted file mode 100644 index 46360d40..00000000 --- a/lib-configstore/include/storeremoteconfig.h +++ /dev/null @@ -1,53 +0,0 @@ -/** - * @file storeremoteconfig.h - * - */ -/* Copyright (C) 2019-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef STOREREMOTECONFIG_H_ -#define STOREREMOTECONFIG_H_ - -#include "remoteconfigparams.h" - -#include "configstore.h" - -class StoreRemoteConfig final: public RemoteConfigParamsStore { -public: - StoreRemoteConfig(); - - void Update(const struct TRemoteConfigParams *pRemoteConfigParams) override { - ConfigStore::Get()->Update(configstore::Store::RCONFIG, pRemoteConfigParams, sizeof(struct TRemoteConfigParams)); - } - - void Copy(struct TRemoteConfigParams *pRemoteConfigParams) override { - ConfigStore::Get()->Copy(configstore::Store::RCONFIG, pRemoteConfigParams, sizeof(struct TRemoteConfigParams)); - } - - static StoreRemoteConfig *Get() { - return s_pThis; - } - -private: - static StoreRemoteConfig *s_pThis; -}; - -#endif /* STOREREMOTECONFIG_H_ */ diff --git a/lib-configstore/include/storetlc59711.h b/lib-configstore/include/storetlc59711.h deleted file mode 100644 index e96e036a..00000000 --- a/lib-configstore/include/storetlc59711.h +++ /dev/null @@ -1,60 +0,0 @@ -/** - * @file storetlc59711.h - * - */ -/* Copyright (C) 2019-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef STORETLC59711_H_ -#define STORETLC59711_H_ - -#include - -#include "tlc59711dmxparams.h" -#include "tlc59711dmxstore.h" - -#include "configstore.h" - -class StoreTLC59711 final: public TLC59711DmxParamsStore, public TLC59711DmxStore { -public: - StoreTLC59711(); - - void Update(const struct TTLC59711DmxParams *pTLC59711DmxParams) override { - ConfigStore::Get()->Update(configstore::Store::TLC5711DMX, pTLC59711DmxParams, sizeof(struct TTLC59711DmxParams)); - } - - void Copy(struct TTLC59711DmxParams *pTLC59711DmxParams) override { - ConfigStore::Get()->Copy(configstore::Store::TLC5711DMX, pTLC59711DmxParams, sizeof(struct TTLC59711DmxParams)); - } - - void SaveDmxStartAddress(uint16_t nDmxStartAddress) override { - ConfigStore::Get()->Update(configstore::Store::TLC5711DMX, __builtin_offsetof(struct TTLC59711DmxParams, nDmxStartAddress), &nDmxStartAddress, sizeof(uint32_t), TLC59711DmxParamsMask::START_ADDRESS); - } - - static StoreTLC59711 *Get() { - return s_pThis; - } - -private: - static StoreTLC59711 *s_pThis; -}; - -#endif /* STORETLC59711_H_ */ diff --git a/lib-configstore/src/artnet/storeartnet.cpp b/lib-configstore/src/artnet/storeartnet.cpp deleted file mode 100644 index f26d8ea9..00000000 --- a/lib-configstore/src/artnet/storeartnet.cpp +++ /dev/null @@ -1,232 +0,0 @@ -/** - * @file storeartnet.cpp - * - */ -/** - * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. - */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include - -#include "storeartnet.h" - -#include "artnetstore.h" -#include "artnetparams.h" -#include "artnet.h" -#include "artnetnode.h" - -#include "configstore.h" - -#include "debug.h" - -#define UNUSED __attribute__((unused)) - -uint32_t StoreArtNet::s_nPortIndexOffset; -StoreArtNet *StoreArtNet::s_pThis; - -StoreArtNet::StoreArtNet(uint32_t nPortIndexOffset) { - DEBUG_ENTRY - DEBUG_PRINTF("nPortIndexOffset=%u", nPortIndexOffset); - - assert(s_pThis == nullptr); - s_pThis = this; - - s_nPortIndexOffset = nPortIndexOffset; - - DEBUG_PRINTF("%p", reinterpret_cast(s_pThis)); - DEBUG_EXIT -} - -void StoreArtNet::SaveShortName(uint32_t nPortIndex, const char *pShortName) { - DEBUG_ENTRY - DEBUG_PRINTF("%u, %s", nPortIndex, pShortName); - - if (nPortIndex >= s_nPortIndexOffset) { - nPortIndex -= s_nPortIndexOffset; - } else { - DEBUG_EXIT - return; - } - - DEBUG_PRINTF("nPortIndex=%u", nPortIndex); - - if (nPortIndex >= artnet::PORTS) { - DEBUG_EXIT - return; - } - - ConfigStore::Get()->Update(configstore::Store::NODE, (artnet::SHORT_NAME_LENGTH * nPortIndex) + __builtin_offsetof(struct artnetparams::Params, aLabel), pShortName, artnet::SHORT_NAME_LENGTH, artnetparams::Mask::LABEL_A << nPortIndex); - - DEBUG_EXIT -} - -void StoreArtNet::SaveUniverse(uint32_t nPortIndex) { - DEBUG_ENTRY - DEBUG_PRINTF("s_nPortIndexOffset=%u, nPortIndex=%u", s_nPortIndexOffset, nPortIndex); - - if (nPortIndex >= s_nPortIndexOffset) { - nPortIndex -= s_nPortIndexOffset; - } else { - DEBUG_EXIT - return; - } - - DEBUG_PRINTF("nPortIndex=%u", nPortIndex); - - if (nPortIndex >= artnet::PORTS) { - DEBUG_EXIT - return; - } - - uint16_t nUniverse; - - if (ArtNetNode::Get()->GetPortAddress(nPortIndex, nUniverse)) { - DEBUG_PRINTF("nPortIndex=%u, nUniverse=%u", nPortIndex, nUniverse); - ConfigStore::Get()->Update(configstore::Store::NODE, (sizeof(uint16_t) * nPortIndex) + __builtin_offsetof(struct artnetparams::Params, nUniverse), &nUniverse, sizeof(uint16_t), artnetparams::Mask::UNIVERSE_A << nPortIndex); - } - - DEBUG_EXIT -} - -void StoreArtNet::SaveMergeMode(uint32_t nPortIndex, const lightset::MergeMode mergeMode) { - DEBUG_ENTRY - DEBUG_PRINTF("%u, %u", nPortIndex, static_cast(mergeMode)); - - if (nPortIndex >= s_nPortIndexOffset) { - nPortIndex -= s_nPortIndexOffset; - } else { - DEBUG_EXIT - return; - } - - DEBUG_PRINTF("nPortIndex=%u", nPortIndex); - - if (nPortIndex >= artnet::PORTS) { - DEBUG_EXIT - return; - } - - uint16_t nMergeMode; - ConfigStore::Get()->Copy(configstore::Store::NODE, &nMergeMode, sizeof(uint16_t), __builtin_offsetof(struct artnetparams::Params, nMergeMode)); - - nMergeMode &= artnetparams::mergemode_clear(nPortIndex); - nMergeMode |= artnetparams::mergemode_set(nPortIndex, mergeMode); - - ConfigStore::Get()->Update(configstore::Store::NODE, __builtin_offsetof(struct artnetparams::Params, nMergeMode), &nMergeMode, sizeof(uint16_t)); - - DEBUG_EXIT -} - -void StoreArtNet::SavePortProtocol(uint32_t nPortIndex, const artnet::PortProtocol portProtocol) { - DEBUG_ENTRY - DEBUG_PRINTF("s_nPortIndexOffset=%u, nPortIndex=%u, portProtocol=%u", s_nPortIndexOffset, nPortIndex, static_cast(portProtocol)); - - if (nPortIndex >= s_nPortIndexOffset) { - nPortIndex -= s_nPortIndexOffset; - } else { - DEBUG_EXIT - return; - } - - DEBUG_PRINTF("nPortIndex=%u", nPortIndex); - - if (nPortIndex >= artnet::PORTS) { - DEBUG_EXIT - return; - } - - uint16_t nPortProtocol; - ConfigStore::Get()->Copy(configstore::Store::NODE, &nPortProtocol, sizeof(uint16_t), __builtin_offsetof(struct artnetparams::Params, nProtocol)); - - nPortProtocol &= artnetparams::protocol_clear(nPortIndex); - nPortProtocol |= artnetparams::protocol_set(nPortIndex, portProtocol); - - ConfigStore::Get()->Update(configstore::Store::NODE, __builtin_offsetof(struct artnetparams::Params, nProtocol), &nPortProtocol, sizeof(uint16_t)); - DEBUG_EXIT -} - -void StoreArtNet::SaveOutputStyle(uint32_t nPortIndex, const lightset::OutputStyle outputStyle) { - DEBUG_ENTRY - DEBUG_PRINTF("s_nPortIndexOffset=%u, nPortIndex=%u, outputStyle=%u", s_nPortIndexOffset, nPortIndex, static_cast(outputStyle)); - - if (nPortIndex >= s_nPortIndexOffset) { - nPortIndex -= s_nPortIndexOffset; - } else { - DEBUG_EXIT - return; - } - - DEBUG_PRINTF("nPortIndex=%u", nPortIndex); - - if (nPortIndex >= artnet::PORTS) { - DEBUG_EXIT - return; - } - - uint8_t nOutputStyle; - ConfigStore::Get()->Copy(configstore::Store::NODE, &nOutputStyle, sizeof(uint8_t), __builtin_offsetof(struct artnetparams::Params, nOutputStyle)); - - if (outputStyle == lightset::OutputStyle::CONSTANT) { - nOutputStyle |= static_cast(1U << nPortIndex); - } else { - nOutputStyle &= static_cast(~(1U << nPortIndex)); - } - - ConfigStore::Get()->Update(configstore::Store::NODE, __builtin_offsetof(struct artnetparams::Params, nOutputStyle), &nOutputStyle, sizeof(uint8_t)); - - DEBUG_EXIT -} - -void StoreArtNet::SaveRdmEnabled(uint32_t nPortIndex, const bool isEnabled) { - DEBUG_ENTRY - DEBUG_PRINTF("s_nPortIndexOffset=%u, nPortIndex=%u, isEnabled=%d", s_nPortIndexOffset, nPortIndex, isEnabled); - - if (nPortIndex >= s_nPortIndexOffset) { - nPortIndex -= s_nPortIndexOffset; - } else { - DEBUG_EXIT - return; - } - - DEBUG_PRINTF("nPortIndex=%u", nPortIndex); - - if (nPortIndex >= artnet::PORTS) { - DEBUG_EXIT - return; - } - - uint16_t nRdm; - ConfigStore::Get()->Copy(configstore::Store::NODE, &nRdm, sizeof(uint16_t), __builtin_offsetof(struct artnetparams::Params, nRdm)); - - nRdm &= artnetparams::clear_mask(nPortIndex); - - if (isEnabled) { - nRdm |= artnetparams::shift_left(1, nPortIndex); - nRdm |= static_cast(1U << (nPortIndex + 8)); - } - - ConfigStore::Get()->Update(configstore::Store::NODE, __builtin_offsetof(struct artnetparams::Params, nRdm), &nRdm, sizeof(uint16_t)); - - DEBUG_EXIT -} diff --git a/lib-configstore/src/configstore.cpp b/lib-configstore/src/configstore.cpp old mode 100644 new mode 100755 index 5e325d4a..4b6bbf26 --- a/lib-configstore/src/configstore.cpp +++ b/lib-configstore/src/configstore.cpp @@ -2,7 +2,7 @@ * @file configstore.cpp * */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -36,13 +36,16 @@ #include "debug.h" +namespace global { +extern int32_t *gp_nUtcOffset; +} // namespace global + using namespace configstore; static constexpr uint8_t s_aSignature[] = {'A', 'v', 'V', 0x01}; -static constexpr auto OFFSET_STORES = ((((sizeof(s_aSignature) + 15) / 16) * 16) + 16); // +16 is reserved for future use -static constexpr uint32_t s_aStorSize[static_cast(Store::LAST)] = {96, 32, 64, 64, 32, 32, 480, 64, 32, 96, 48, 32, 944, 48, 64, 32, 96, 32, 1024, 32, 32, 64, 96, 32, 32, 320}; +static constexpr uint32_t s_aStorSize[static_cast(Store::LAST)] = {96, 32, 64, 64, 32, 32, 480, 64, 32, 96, 48, 32, 944, 48, 64, 32, 96, 32, 1024, 32, 32, 64, 96, 32, 32, 320, 32}; #ifndef NDEBUG -static constexpr char s_aStoreName[static_cast(Store::LAST)][16] = {"Network", "DMX", "Pixel", "LTC", "MIDI", "LTC ETC", "OSC Server", "TLC59711", "USB Pro", "RDM Device", "RConfig", "TCNet", "OSC Client", "Display", "LTC Display", "Monitor", "SparkFun", "Slush", "Motors", "Show", "Serial", "RDM Sensors", "RDM SubDevices", "GPS", "RGB Panel", "Node"}; +static constexpr char s_aStoreName[static_cast(Store::LAST)][16] = {"Network", "DMX", "Pixel", "LTC", "MIDI", "LTC ETC", "OSC Server", "TLC59711", "USB Pro", "RDM Device", "RConfig", "TCNet", "OSC Client", "Display", "LTC Display", "Monitor", "SparkFun", "Slush", "Motors", "Show", "Serial", "RDM Sensors", "RDM SubDevices", "GPS", "RGB Panel", "Node", "PCA9685"}; #endif bool ConfigStore::s_bHaveFlashChip; @@ -57,9 +60,13 @@ ConfigStore *ConfigStore::s_pThis; ConfigStore::ConfigStore() { DEBUG_ENTRY + static_assert(sizeof(s_aSignature) <= FlashStore::SIGNATURE_SIZE); + assert(s_pThis == nullptr); s_pThis = this; + global::gp_nUtcOffset = reinterpret_cast(&s_SpiFlashData[FlashStore::SIGNATURE_SIZE]); + s_bHaveFlashChip = StoreDevice::IsDetected(); assert(FlashStore::SIZE <= StoreDevice::GetSize()); @@ -94,20 +101,32 @@ ConfigStore::ConfigStore() { if (!bSignatureOK) { DEBUG_PUTS("No signature"); - memset(&s_SpiFlashData[OFFSET_STORES], 0, FlashStore::SIZE - OFFSET_STORES); + memset(&s_SpiFlashData[FlashStore::SIGNATURE_SIZE], 0, FlashStore::SIZE - FlashStore::SIGNATURE_SIZE); s_State = State::CHANGED; } - s_nSpiFlashStoreSize = OFFSET_STORES; + s_nSpiFlashStoreSize = FlashStore::OFFSET_STORES; for (uint32_t j = 0; j < static_cast(Store::LAST); j++) { s_nSpiFlashStoreSize += s_aStorSize[j]; } - DEBUG_PRINTF("OFFSET_STORES=%d, m_nSpiFlashStoreSize=%d", static_cast(OFFSET_STORES), s_nSpiFlashStoreSize); + DEBUG_PRINTF("FlashStore::OFFSET_STORES=%d, m_nSpiFlashStoreSize=%d", static_cast(FlashStore::OFFSET_STORES), s_nSpiFlashStoreSize); assert(s_nSpiFlashStoreSize <= FlashStore::SIZE); + for (uint32_t nStore = 0; nStore < static_cast(Store::LAST); nStore++) { + auto *pSet = reinterpret_cast((&s_SpiFlashData[GetStoreOffset(static_cast(nStore))])); + if (*pSet == UINT32_MAX) { + *pSet = 0; + } + } + + auto *p = reinterpret_cast(&s_SpiFlashData[FlashStore::SIGNATURE_SIZE]); + if (p->nUtcOffset == -1) { + p->nUtcOffset = 0; + } + DEBUG_PUTS(""); debug_dump(s_SpiFlashData, FlashStore::SIZE); @@ -117,7 +136,7 @@ ConfigStore::ConfigStore() { uint32_t ConfigStore::GetStoreOffset(Store store) { assert(store < Store::LAST); - uint32_t nOffset = OFFSET_STORES; + uint32_t nOffset = FlashStore::OFFSET_STORES; for (uint32_t i = 0; i < static_cast(store); i++) { nOffset += s_aStorSize[i]; @@ -171,9 +190,8 @@ void ConfigStore::Update(Store store, uint32_t nOffset, const void *pData, uint3 pSrc++; } - if ((0 != nOffset) && (bIsChanged) && (nSetList != 0)) { - auto *pSet = reinterpret_cast((&s_SpiFlashData[GetStoreOffset(store)] + nOffsetSetList)); - + if (bIsChanged){ + auto *pSet = reinterpret_cast((&s_SpiFlashData[GetStoreOffset(store)] + nOffsetSetList)); *pSet |= nSetList; } @@ -181,12 +199,13 @@ void ConfigStore::Update(Store store, uint32_t nOffset, const void *pData, uint3 s_State = State::CHANGED; } + debug_dump(&s_SpiFlashData[GetStoreOffset(store)] + nOffsetSetList, 8); DEBUG_EXIT } -void ConfigStore::Copy(const Store store, void *pData, uint32_t nDataLength, uint32_t nOffset) { +void ConfigStore::Copy(const Store store, void *pData, uint32_t nDataLength, uint32_t nOffset, const bool doUpdate) { DEBUG_ENTRY - DEBUG_PRINTF("[%s]:%u pData=%p, nDataLength=%u, nOffset=%u", s_aStoreName[static_cast(store)], static_cast(store), pData, nDataLength, nOffset); + DEBUG_PRINTF("[%s]:%u pData=%p, nDataLength=%u, nOffset=%u, doUpdate=%u", s_aStoreName[static_cast(store)], static_cast(store), pData, nDataLength, nOffset, doUpdate); assert(store < Store::LAST); assert(pData != nullptr); @@ -210,7 +229,9 @@ void ConfigStore::Copy(const Store store, void *pData, uint32_t nDataLength, uin return; } - Update(store, pData, nDataLength); + if (doUpdate) { + Update(store, pData, nDataLength); + } DEBUG_EXIT } @@ -293,8 +314,8 @@ void ConfigStore::Dump() { Hardware::Get()->WatchdogStop(); } - debug_dump(s_SpiFlashData, OFFSET_STORES); - printf("\n"); + debug_dump(s_SpiFlashData, FlashStore::OFFSET_STORES); + puts(""); for (uint32_t j = 0; j < static_cast(Store::LAST); j++) { printf("Store [%s]:%d\n", s_aStoreName[j], j); @@ -302,7 +323,7 @@ void ConfigStore::Dump() { auto *p = &s_SpiFlashData[GetStoreOffset(static_cast(j))]; debug_dump(p, static_cast(s_aStorSize[j])); - printf("\n"); + puts(""); } if (IsWatchDog) { diff --git a/lib-configstore/src/envparams.cpp b/lib-configstore/src/envparams.cpp new file mode 100755 index 00000000..cead222f --- /dev/null +++ b/lib-configstore/src/envparams.cpp @@ -0,0 +1,132 @@ +/** + * @file envparams.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#if !defined(__clang__) // Needed for compiling on MacOS +# pragma GCC push_options +# pragma GCC optimize ("Os") +#endif + +#include +#include +#include + +#include "envparams.h" +#include "envparamsconst.h" + +#include "readconfigfile.h" +#include "sscan.h" + +#include "propertiesbuilder.h" + +#include "configstore.h" + +#include "debug.h" + +EnvParams::EnvParams() { + DEBUG_ENTRY + + DEBUG_EXIT +} + +void EnvParams::LoadAndSet() { + DEBUG_ENTRY + + assert(ConfigStore::Get() != nullptr); + +#if !defined(DISABLE_FS) + ReadConfigFile configfile(EnvParams::staticCallbackFunction, this); + configfile.Read(EnvParamsConst::FILE_NAME); +#endif + +#ifndef NDEBUG + Dump(); +#endif + + DEBUG_EXIT +} + +void EnvParams::LoadAndSet(const char *pBuffer, uint32_t nLength) { + DEBUG_ENTRY + + assert(ConfigStore::Get() != nullptr); + + assert(pBuffer != nullptr); + assert(nLength != 0); + + ReadConfigFile config(EnvParams::staticCallbackFunction, this); + config.Read(pBuffer, nLength); + +#ifndef NDEBUG + Dump(); +#endif + DEBUG_EXIT +} + +void EnvParams::callbackFunction(const char *pLine) { + assert(pLine != nullptr); + + int8_t nHours; + uint8_t nMinutes; + + if (Sscan::UtcOffset(pLine, EnvParamsConst::UTC_OFFSET, nHours, nMinutes) == Sscan::OK) { + ConfigStore::Get()->SetEnvUtcOffset(nHours, nMinutes); + return; + } +} + +void EnvParams::staticCallbackFunction(void *p, const char *s) { + assert(p != nullptr); + assert(s != nullptr); + + (static_cast(p))->callbackFunction(s); +} + +void EnvParams::Builder(char *pBuffer, uint32_t nLength, uint32_t& nSize) { + DEBUG_ENTRY + + assert(pBuffer != nullptr); + + PropertiesBuilder builder(EnvParamsConst::FILE_NAME, pBuffer, nLength); + + int8_t nHours; + uint8_t nMinutes; + ConfigStore::Get()->GetEnvUtcOffset(nHours, nMinutes); + builder.AddUtcOffset(EnvParamsConst::UTC_OFFSET, nHours, nMinutes); + + nSize = builder.GetSize(); + + DEBUG_PRINTF("nSize=%d", nSize); + DEBUG_EXIT +} + +void EnvParams::Dump() { + printf("%s::%s \'%s\':\n", __FILE__, __FUNCTION__, EnvParamsConst::FILE_NAME); + + puts("UTC Offset"); + int8_t nHours; + uint8_t nMinutes; + ConfigStore::Get()->GetEnvUtcOffset(nHours, nMinutes); + printf(" %s=%.2d:%.2u [%d]\n", EnvParamsConst::UTC_OFFSET, nHours, nMinutes, ConfigStore::Get()->GetEnvUtcOffset()); +} diff --git a/lib-configstore/src/envparamsconst.cpp b/lib-configstore/src/envparamsconst.cpp new file mode 100755 index 00000000..37880705 --- /dev/null +++ b/lib-configstore/src/envparamsconst.cpp @@ -0,0 +1,30 @@ +/** + * @file envparamsconst.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "envparamsconst.h" + +const char EnvParamsConst::FILE_NAME[] = "env.txt"; + +const char EnvParamsConst::UTC_OFFSET[] = "utc_offset"; diff --git a/lib-configstore/src/platform_configstore.h b/lib-configstore/src/platform_configstore.h old mode 100644 new mode 100755 diff --git a/lib-configstore/src/storenetwork.cpp b/lib-configstore/src/storenetwork.cpp deleted file mode 100644 index 0ed3c4a4..00000000 --- a/lib-configstore/src/storenetwork.cpp +++ /dev/null @@ -1,41 +0,0 @@ -/** - * @file storenetwork.cpp - * - */ -/* Copyright (C) 2018-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include - -#include "storenetwork.h" -#include "debug.h" - -StoreNetwork *StoreNetwork::s_pThis = nullptr; - -StoreNetwork::StoreNetwork() { - DEBUG_ENTRY - - assert(s_pThis == nullptr); - s_pThis = this; - - DEBUG_PRINTF("%p", reinterpret_cast(s_pThis)); - DEBUG_EXIT -} diff --git a/lib-ddp/.cproject b/lib-ddp/.cproject index ccec8dad..e0b1ea2d 100755 --- a/lib-ddp/.cproject +++ b/lib-ddp/.cproject @@ -31,13 +31,11 @@ - @@ -177,7 +170,6 @@ - diff --git a/lib-ddp/Rules.mk b/lib-ddp/Rules.mk index 801e1e34..aa2f9f54 100644 --- a/lib-ddp/Rules.mk +++ b/lib-ddp/Rules.mk @@ -4,5 +4,4 @@ else DEFINES+=LIGHTSET_PORTS=32 endif -EXTRA_INCLUDES =../lib-properties/include ../lib-hal/include ../lib-network/include -EXTRA_INCLUDES+=../lib-lightset/include +EXTRA_INCLUDES =../lib-properties/include ../lib-network/include ../lib-lightset/include diff --git a/lib-ddp/include/ddp.h b/lib-ddp/include/ddp.h index 96a00177..f0cc9a73 100644 --- a/lib-ddp/include/ddp.h +++ b/lib-ddp/include/ddp.h @@ -3,7 +3,7 @@ * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-ddp/src/ddpdisplay.cpp b/lib-ddp/src/ddpdisplay.cpp index eb4cc814..13c4a6f8 100644 --- a/lib-ddp/src/ddpdisplay.cpp +++ b/lib-ddp/src/ddpdisplay.cpp @@ -2,7 +2,7 @@ * @file ddpdisplay.h * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -169,7 +169,7 @@ void DdpDisplay::HandleQuery() { m_Packet.header.len[0] = static_cast(nLength >> 8); m_Packet.header.len[1] = static_cast(nLength); - Network::Get()->SendTo(m_nHandle, &m_Packet, static_cast(HEADER_LEN + static_cast(nLength)), Network::Get()->GetIp() | ~(Network::Get()->GetNetmask()), ddp::UDP_PORT); + Network::Get()->SendTo(m_nHandle, &m_Packet, (HEADER_LEN + static_cast(nLength)), Network::Get()->GetIp() | ~(Network::Get()->GetNetmask()), ddp::UDP_PORT); } if ((m_Packet.header.id & id::STATUS) == id::CONFIG) { @@ -206,9 +206,9 @@ void DdpDisplay::HandleQuery() { m_Packet.header.len[0] = static_cast(nLength >> 8); m_Packet.header.len[1] = static_cast(nLength); - Network::Get()->SendTo(m_nHandle, &m_Packet, static_cast(HEADER_LEN + static_cast(nLength)), m_nFromIp, ddp::UDP_PORT); + Network::Get()->SendTo(m_nHandle, &m_Packet, HEADER_LEN + nLength, m_nFromIp, ddp::UDP_PORT); - debug_dump(&m_Packet, static_cast(HEADER_LEN + static_cast(nLength))); + debug_dump(&m_Packet, HEADER_LEN + nLength); } DEBUG_EXIT @@ -318,7 +318,7 @@ void DdpDisplay::Run() { } void DdpDisplay::Print() { - puts("DDP Display:"); + puts("DDP Display"); printf(" Count : %u\n", m_nCount); printf(" Channels per pixel: %u\n", GetChannelsPerPixel()); printf(" Active ports : %u\n", m_nActivePorts); diff --git a/lib-debug/.cproject b/lib-debug/.cproject deleted file mode 100644 index d6b8345f..00000000 --- a/lib-debug/.cproject +++ /dev/null @@ -1,80 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/lib-debug/.settings/language.settings.xml b/lib-debug/.settings/language.settings.xml deleted file mode 100644 index e2081f3a..00000000 --- a/lib-debug/.settings/language.settings.xml +++ /dev/null @@ -1,12 +0,0 @@ - - - - - - - - - - - - \ No newline at end of file diff --git a/lib-debug/Makefile.GD32 b/lib-debug/Makefile.GD32 deleted file mode 100644 index e62a5089..00000000 --- a/lib-debug/Makefile.GD32 +++ /dev/null @@ -1,3 +0,0 @@ -EXTRA_SRCDIR= - -include ../firmware-template-gd32/lib/Rules.mk \ No newline at end of file diff --git a/lib-device/.cproject b/lib-device/.cproject index 86026fac..5011551b 100644 --- a/lib-device/.cproject +++ b/lib-device/.cproject @@ -30,12 +30,10 @@ - diff --git a/lib-device/include/ema.h b/lib-device/include/ema.h new file mode 100755 index 00000000..169d8763 --- /dev/null +++ b/lib-device/include/ema.h @@ -0,0 +1,77 @@ +/** + * @file ema.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef EMA_H_ +#define EMA_H_ + +#include + +/** + * @brief + * The EMA class template implements an Exponential Moving Average (EMA) filter in a compact and efficient manner, + * suitable for real-time applications where resource constraints may be a consideration. + * The class uses unsigned integer arithmetic to achieve the filtering, + * which is beneficial for systems that do not have floating-point units or where performance is critical. + * + * @tparam K + * A compile-time constant that determines the weight of the EMA. + * Higher K values mean a slower response to changes in the input, making the EMA smoother. + */ + +template +class EMA { +public: + EMA(uint16_t nIntitial = 0) : nState(static_cast(nIntitial << K) - nIntitial) {} + + /** + * @brief + * This method allows resetting the internal state nState of the filter to a specific value nValue. + * It sets the state in the same way as the constructor, + * preparing the filter to start processing new inputs from the given value. + * @param nValue + */ + void Reset(const uint16_t nValue = 0) { + nState = static_cast(nValue << K) - nValue; + } + + uint16_t Filter(const uint16_t nInput) { + nState += nInput; + const auto nOutput = static_cast((nState + nHalf) >> K); + nState -= nOutput; + return nOutput; + } + + /* + * This static constant is used for rounding during the shift operation. + * It ensures that when you shift the value right by K bits, + * it rounds to the nearest integer rather than truncating. + */ + static constexpr uint16_t nHalf = K > 0 ? 1 << (K - 1) : 0; + +private: + uint16_t nState; +}; + +#endif /* EMA_H_ */ diff --git a/lib-device/include/max7219.h b/lib-device/include/max7219.h index e23fa9b6..b7e57e42 100644 --- a/lib-device/include/max7219.h +++ b/lib-device/include/max7219.h @@ -2,7 +2,7 @@ * @file max7219.h * */ -/* Copyright (C) 2020-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-device/include/mcp23s17.h b/lib-device/include/mcp23s17.h index d0c36ad2..d9641037 100644 --- a/lib-device/include/mcp23s17.h +++ b/lib-device/include/mcp23s17.h @@ -2,7 +2,7 @@ * @file mcp23s17.h * */ -/* Copyright (C) 2020-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-hal/src/utc.cpp b/lib-device/include/mcp23x08.h old mode 100644 new mode 100755 similarity index 61% rename from lib-hal/src/utc.cpp rename to lib-device/include/mcp23x08.h index ba6e01b2..b05a33ab --- a/lib-hal/src/utc.cpp +++ b/lib-device/include/mcp23x08.h @@ -1,8 +1,8 @@ /** - * @file utc.cpp + * @file mcp23x08.h * */ -/* Copyright (C) 2019-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -10,8 +10,10 @@ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: + * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE @@ -21,28 +23,23 @@ * THE SOFTWARE. */ -#include - -#include "utc.h" +#ifndef MCP23X08_H_ +#define MCP23X08_H_ -// https://en.wikipedia.org/wiki/List_of_UTC_time_offsets - -static const float s_ValidOffets[] = { -9.5, -3.5, 3.5, 4.5, 5.5, 5.75, 6.5, 8.75, 9.5, 10.5, 12.75 }; - -int32_t Utc::Validate(float fOffset) { - auto nInt = static_cast(fOffset); +#include - if ((nInt >= -12) && (nInt <= 14)) { - if (fOffset == static_cast(nInt)) { - return (nInt * 3600); - } else { - for (uint32_t i = 0; i < sizeof(s_ValidOffets) / sizeof(s_ValidOffets[0]); i++) { - if (fOffset == s_ValidOffets[i]) { - return static_cast(fOffset * 3600.0f); - } - } - } - } +namespace mcp23x08 { +static constexpr uint8_t REG_IODIR = 0x00; +static constexpr uint8_t REG_IPOL = 0x01; +static constexpr uint8_t REG_GPINTEN = 0x02; +static constexpr uint8_t REG_DEFVAL = 0x03; +static constexpr uint8_t REG_INTCON = 0x04; +static constexpr uint8_t REG_IOCON = 0x05; +static constexpr uint8_t REG_GPPU = 0x06; +static constexpr uint8_t REG_INTF = 0x07; +static constexpr uint8_t REG_INTCAP = 0x08; +static constexpr uint8_t REG_GPIO = 0x09; +static constexpr uint8_t REG_OLAT = 0x0A; +} // namespace mcp23x08 - return 0; -} +#endif /* MCP23X08_H_ */ diff --git a/lib-device/include/mcp23x17.h b/lib-device/include/mcp23x17.h index 489b0ea6..4b6f2ef2 100644 --- a/lib-device/include/mcp23x17.h +++ b/lib-device/include/mcp23x17.h @@ -2,7 +2,7 @@ * @file mcp23x17.h * */ -/* Copyright (C) 2020-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,6 +27,7 @@ #include namespace mcp23x17 { +///< IOCON.BANK = 0 static constexpr uint8_t REG_IODIRA = 0x00; ///< I/O DIRECTION (IODIRA) REGISTER, 1 = Input (default), 0 = Output static constexpr uint8_t REG_IODIRB = 0x01; ///< I/O DIRECTION (IODIRB) REGISTER, 1 = Input (default), 0 = Output static constexpr uint8_t REG_IPOLA = 0x02; ///< INPUT POLARITY (IPOLA) REGISTER, 0 = Normal (default)(low reads as 0), 1 = Inverted (low reads as 1) @@ -51,6 +52,7 @@ static constexpr uint8_t REG_OLATA = 0x14; ///< OUTPUT LATCH REGISTER (OLATA), static constexpr uint8_t REG_OLATB = 0x15; ///< OUTPUT LATCH REGISTER (OLATB), 1 = Latch High, 0 = Latch Low (default) Reading Returns Latch State, Not Port Value static constexpr uint8_t IOCON_HAEN = (1U << 3); +static constexpr uint8_t IOCON_BANK = (1U << 7); static constexpr uint8_t DEFAULT_I2C_ADDRESS = 0x20; diff --git a/lib-device/include/mcp49x2.h b/lib-device/include/mcp49x2.h index 977a8dbf..9d48e184 100644 --- a/lib-device/include/mcp49x2.h +++ b/lib-device/include/mcp49x2.h @@ -2,7 +2,7 @@ * @file mcp49x2.h * */ -/* Copyright (C) 2014-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2014-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-device/include/sc16is740.h b/lib-device/include/sc16is740.h index 2313ceee..903ab353 100644 --- a/lib-device/include/sc16is740.h +++ b/lib-device/include/sc16is740.h @@ -2,7 +2,7 @@ * @file sc16is740.h * */ -/* Copyright (C) 2020-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -49,7 +49,7 @@ class SC16IS740: HAL_I2C { }; SC16IS740(uint8_t nAddress = sc16is740::I2C_ADDRESS, uint32_t nOnBoardCrystal = sc16is740::CRISTAL_HZ); - ~SC16IS740() {} + ~SC16IS740() = default; void SetOnBoardCrystal(uint32_t nOnBoardCrystalHz) { m_nOnBoardCrystal = nOnBoardCrystalHz; diff --git a/lib-device/include/sc16is7x0.h b/lib-device/include/sc16is7x0.h index 13a8736c..2df3ad32 100644 --- a/lib-device/include/sc16is7x0.h +++ b/lib-device/include/sc16is7x0.h @@ -2,7 +2,7 @@ * @file sc16is7x0.h * */ -/* Copyright (C) 2020-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-device/src/sc16is740.cpp b/lib-device/src/sc16is740.cpp index b803b770..381b234b 100644 --- a/lib-device/src/sc16is740.cpp +++ b/lib-device/src/sc16is740.cpp @@ -2,7 +2,7 @@ * @file sc16is740.cpp * */ -/* Copyright (C) 2020-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-display/.cproject b/lib-display/.cproject index 6a561161..a86bfdbf 100644 --- a/lib-display/.cproject +++ b/lib-display/.cproject @@ -30,12 +30,10 @@ - diff --git a/lib-display/include/display.h b/lib-display/include/display.h index c8d92152..ab4d374b 100644 --- a/lib-display/include/display.h +++ b/lib-display/include/display.h @@ -2,7 +2,7 @@ * @file display.h * */ -/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,17 +26,14 @@ #ifndef DISPLAY_H_ #define DISPLAY_H_ -#include "display7segment.h" +#include + #include "console.h" namespace display { struct Defaults { - static constexpr auto SEEP_TIMEOUT = 5; + static constexpr uint32_t SEEP_TIMEOUT = 5; }; -namespace timeout { -void gpio_init(); -bool gpio_renew(); -} // namespace timeout } // namespace display #if !defined (CONFIG_DISPLAY_USE_CUSTOM) diff --git a/lib-display/include/display7segment.h b/lib-display/include/display7segment.h deleted file mode 100644 index cbc545b2..00000000 --- a/lib-display/include/display7segment.h +++ /dev/null @@ -1,145 +0,0 @@ -/** - * @file display7segment.h - * - */ -/* Copyright (C) 2019-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef DISPLAY7SEGMENT_H_ -#define DISPLAY7SEGMENT_H_ - -#include - -namespace display7segment { -static constexpr uint8_t CH_0 = 0x3F; // 0b00111111 -static constexpr uint8_t CH_1 = 0x06; // 0b00000110 -static constexpr uint8_t CH_2 = 0x5B; // 0b01011011 -static constexpr uint8_t CH_3 = 0x4F; // 0b01001111 -static constexpr uint8_t CH_4 = 0x66; // 0b01100110 -static constexpr uint8_t CH_5 = 0x6D; // 0b01101101 -static constexpr uint8_t CH_6 = 0x7D; // 0b01111101 -static constexpr uint8_t CH_7 = 0x07; // 0b00000111 -static constexpr uint8_t CH_8 = 0x7F; // 0b01111111 -static constexpr uint8_t CH_9 = 0x6F; // 0b01101111 -static constexpr uint8_t CH_A = 0x77; // 0b01110111 -static constexpr uint8_t CH_B = 0x7C; // 0b01111100 -static constexpr uint8_t CH_C = 0x39; // 0b00111001 -static constexpr uint8_t CH_D = 0x5E; // 0b01011110 -static constexpr uint8_t CH_E = 0x79; // 0b01111001 -static constexpr uint8_t CH_F = 0x71; // 0b01110001 -static constexpr uint8_t CH_P = 0x73; // 0b01110011 -static constexpr uint8_t CH_MIN = 0x40; // 0b01000000 -static constexpr uint8_t CH_DP = 0x80; // 0b10000000 -static constexpr uint8_t CH_BLANK = 0x00; // 0b00000000 - -static constexpr uint16_t Msg(uint8_t nDigitRight, uint8_t nDigitLeft) { - return static_cast((nDigitLeft << 8) | nDigitRight); -} -} // namespace display7segment - -enum class Display7SegmentMessage { - // Generic Digits - GENERIC_0 = display7segment::Msg(display7segment::CH_0, display7segment::CH_BLANK), - GENERIC_1 = display7segment::Msg(display7segment::CH_1, display7segment::CH_BLANK), - GENERIC_2 = display7segment::Msg(display7segment::CH_2, display7segment::CH_BLANK), - GENERIC_3 = display7segment::Msg(display7segment::CH_3, display7segment::CH_BLANK), - GENERIC_4 = display7segment::Msg(display7segment::CH_4, display7segment::CH_BLANK), - GENERIC_5 = display7segment::Msg(display7segment::CH_5, display7segment::CH_BLANK), - GENERIC_6 = display7segment::Msg(display7segment::CH_6, display7segment::CH_BLANK), - GENERIC_7 = display7segment::Msg(display7segment::CH_7, display7segment::CH_BLANK), - GENERIC_8 = display7segment::Msg(display7segment::CH_8, display7segment::CH_BLANK), - GENERIC_9 = display7segment::Msg(display7segment::CH_9, display7segment::CH_BLANK), - // Startup messages - INFO_STARTUP = display7segment::Msg(display7segment::CH_BLANK, display7segment::CH_0), - INFO_NETWORK_INIT = display7segment::Msg(display7segment::CH_BLANK, display7segment::CH_1), - INFO_DHCP = display7segment::Msg(display7segment::CH_BLANK, display7segment::CH_2), - INFO_IP = display7segment::Msg(display7segment::CH_BLANK, display7segment::CH_3), - INFO_NTP = display7segment::Msg(display7segment::CH_BLANK, display7segment::CH_4), - INFO_SPARKFUN = display7segment::Msg(display7segment::CH_BLANK, display7segment::CH_5), - INFO_CPLD = display7segment::Msg(display7segment::CH_BLANK, display7segment::CH_6), - INFO_MDNS_CONFIG = display7segment::Msg(display7segment::CH_BLANK, display7segment::CH_7), - INFO_RDMNET_CONFIG = display7segment::Msg(display7segment::CH_BLANK, display7segment::CH_8), - // - INFO_NETWORK_SHUTDOWN = display7segment::Msg(display7segment::CH_BLANK, display7segment::CH_9), - // - INFO_NODE_PARMAMS = display7segment::Msg(display7segment::CH_BLANK, display7segment::CH_4), - INFO_BRIDGE_PARMAMS = display7segment::Msg(display7segment::CH_BLANK, display7segment::CH_4), - INFO_OSCCLIENT_PARMAMS = display7segment::Msg(display7segment::CH_BLANK, display7segment::CH_4), - // - INFO_RDM_RUN = display7segment::Msg(display7segment::CH_BLANK, display7segment::CH_5), - INFO_NODE_START = display7segment::Msg(display7segment::CH_BLANK, display7segment::CH_6), - INFO_BRIDGE_START = display7segment::Msg(display7segment::CH_BLANK, display7segment::CH_6), - INFO_OSCCLIENT_START = display7segment::Msg(display7segment::CH_BLANK, display7segment::CH_6), - INFO_RDMNET_START = display7segment::Msg(display7segment::CH_BLANK, display7segment::CH_6), - // - INFO_NONE = display7segment::Msg(display7segment::CH_DP, display7segment::CH_DP), - INFO_NODE_STARTED = display7segment::Msg(display7segment::CH_DP, display7segment::CH_DP), - INFO_BRIDGE_STARTED = display7segment::Msg(display7segment::CH_DP, display7segment::CH_DP), - INFO_OSCCLIENT_STARTED = display7segment::Msg(display7segment::CH_DP, display7segment::CH_DP), - INFO_RDMNET_STARTED = display7segment::Msg(display7segment::CH_DP, display7segment::CH_DP), - // SPI Flash messages - INFO_SPI_NONE = display7segment::Msg(display7segment::CH_C, display7segment::CH_MIN), - INFO_SPI_CHECK = display7segment::Msg(display7segment::CH_C, display7segment::CH_0), - INFO_SPI_ERASE = display7segment::Msg(display7segment::CH_C, display7segment::CH_1), - INFO_SPI_WRITING = display7segment::Msg(display7segment::CH_C, display7segment::CH_2), - INFO_SPI_NODIFF = display7segment::Msg(display7segment::CH_C, display7segment::CH_3), - INFO_SPI_DONE = display7segment::Msg(display7segment::CH_C, display7segment::CH_C), - INFO_SPI_UPDATE = display7segment::Msg(display7segment::CH_C, display7segment::CH_F), - // Firmware TFTP messages - INFO_TFTP_ON = display7segment::Msg(display7segment::CH_F, display7segment::CH_MIN), - INFO_TFTP_STARTED = display7segment::Msg(display7segment::CH_F, display7segment::CH_1), - INFO_TFTP_ENDED = display7segment::Msg(display7segment::CH_F, display7segment::CH_2), - INFO_TFTP_OFF = display7segment::Msg(display7segment::CH_F, display7segment::CH_DP), - // Informational / Warning messages - INFO_REBOOTING = display7segment::Msg(display7segment::CH_MIN, display7segment::CH_MIN), - INFO_DATALOSS = display7segment::Msg(display7segment::CH_D, display7segment::CH_MIN), - // Error messages - ERROR_DHCP = display7segment::Msg(display7segment::CH_E, display7segment::CH_2), - ERROR_NTP = display7segment::Msg(display7segment::CH_E, display7segment::CH_4), - ERROR_SPARKFUN = display7segment::Msg(display7segment::CH_E, display7segment::CH_5), - ERROR_MCP23S017 = display7segment::Msg(display7segment::CH_E, display7segment::CH_8), - ERROR_SI5351A = display7segment::Msg(display7segment::CH_E, display7segment::CH_9), - ERROR_NEXTION = display7segment::Msg(display7segment::CH_E, display7segment::CH_A), - ERROR_SPI = display7segment::Msg(display7segment::CH_E, display7segment::CH_C), - ERROR_FATAL = display7segment::Msg(display7segment::CH_E, display7segment::CH_E), - ERROR_TFTP = display7segment::Msg(display7segment::CH_E, display7segment::CH_F), - // LTC messages - LTC_WAITING = display7segment::Msg(display7segment::CH_DP, display7segment::CH_DP), - LTC_FILM = display7segment::Msg(display7segment::CH_2, display7segment::CH_4), - LTC_EBU = display7segment::Msg(display7segment::CH_2, display7segment::CH_5), - LTC_DF = display7segment::Msg(display7segment::CH_2, display7segment::CH_9), - LTC_SMPTE = display7segment::Msg(display7segment::CH_3, display7segment::CH_0), - // OSC Client messages - INFO_OSCCLIENT_PING_PONG = display7segment::Msg(display7segment::CH_P, display7segment::CH_P), - ERROR_OSCCLIENT_PING_PONG = display7segment::Msg(display7segment::CH_P, display7segment::CH_E), - // Apple MIDI - rtpMIDI messages - // TODO Apple MIDI - rtpMIDI messages - // Show File player - INFO_PLAYER_IDLE = display7segment::Msg(display7segment::CH_P, display7segment::CH_0), - INFO_PLAYER_RUNNING = display7segment::Msg(display7segment::CH_P, display7segment::CH_1), - INFO_PLAYER_RUNNING_LOOP = display7segment::Msg(display7segment::CH_P, display7segment::CH_2), - INFO_PLAYER_STOPPED = display7segment::Msg(display7segment::CH_P, display7segment::CH_3), - INFO_PLAYER_STOPPED_LOOP = display7segment::Msg(display7segment::CH_P, display7segment::CH_4), - INFO_PLAYER_ENDED = display7segment::Msg(display7segment::CH_P, display7segment::CH_9), - ERROR_PLAYER = display7segment::Msg(display7segment::CH_P, display7segment::CH_E) -}; - -#endif /* DISPLAY7SEGMENT_H_ */ diff --git a/lib-display/include/displayset.h b/lib-display/include/displayset.h index 52ac2ddb..ee7cbb2f 100644 --- a/lib-display/include/displayset.h +++ b/lib-display/include/displayset.h @@ -39,7 +39,7 @@ static constexpr uint32_t BLINK_ON = (1U << 1); class DisplaySet { public: - virtual ~DisplaySet() {} + virtual ~DisplaySet() = default; uint32_t GetColumns() const { return m_nCols; @@ -66,9 +66,9 @@ class DisplaySet { virtual void SetCursorPos(uint32_t nCol, uint32_t nRow)= 0; virtual void SetCursor(uint32_t)= 0; - virtual void SetSleep(__attribute__((unused)) bool bSleep) {} - virtual void SetContrast(__attribute__((unused)) uint8_t nContrast) {} - virtual void SetFlipVertically(__attribute__((unused)) bool doFlipVertically) {} + virtual void SetSleep([[maybe_unused]] bool bSleep) {} + virtual void SetContrast([[maybe_unused]] uint8_t nContrast) {} + virtual void SetFlipVertically([[maybe_unused]] bool doFlipVertically) {} virtual void PrintInfo() {} diff --git a/lib-display/include/i2c/display.h b/lib-display/include/i2c/display.h index 56ba79d3..24f7671d 100644 --- a/lib-display/include/i2c/display.h +++ b/lib-display/include/i2c/display.h @@ -2,7 +2,7 @@ * @file display.h * */ -/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -36,11 +36,14 @@ #include #include "displayset.h" -#include "display7segment.h" -#include "hal_i2c.h" #include "hardware.h" +#include "hal_i2c.h" +#if defined (DISPLAYTIMEOUT_GPIO) +# include "hal_gpio.h" +#endif + namespace display { enum class Type { PCF8574T_1602, PCF8574T_2004, SSD1306, SSD1311, UNKNOWN @@ -182,9 +185,8 @@ class Display { Write(nRows, pText); } - void TextStatus(const char *pText, Display7SegmentMessage message, uint32_t nConsoleColor = UINT32_MAX) { + void TextStatus(const char *pText, uint32_t nConsoleColor) { TextStatus(pText); - Status(message); if (nConsoleColor == UINT32_MAX) { return; @@ -193,11 +195,6 @@ class Display { console_status(nConsoleColor, pText); } - void TextStatus(const char *pText, uint32_t nValue7Segment, bool bHex = false) { - TextStatus(pText); - Status(nValue7Segment, bHex); - } - void SetCursor(uint32_t nMode) { if (m_LcdDisplay == nullptr) { return; @@ -274,28 +271,6 @@ class Display { return m_LcdDisplay->GetRows(); } - void Status(Display7SegmentMessage nData) { - if (m_bHave7Segment) { - m_I2C.WriteRegister(display::segment7::MCP23017_GPIOA, static_cast(~static_cast(nData))); - } - } - - void Status(uint32_t nValue, bool bHex) { - if (m_bHave7Segment) { - uint16_t nData; - - if (!bHex) { - nData = GetData(nValue / 10); - nData = static_cast(nData | GetData(nValue % 10) << 8U); - } else { - nData = GetData(nValue & 0x0F); - nData = static_cast(nData | GetData((nValue >> 4) & 0x0F) << 8U); - } - - m_I2C.WriteRegister(display::segment7::MCP23017_GPIOA, static_cast(~nData)); - } - } - void Progress() { static constexpr char SYMBOLS[] = { '/' , '-', '\\' , '|' }; static uint32_t nSymbolsIndex; @@ -336,9 +311,11 @@ class Display { SetSleep(true); } } else { - if (__builtin_expect((display::timeout::gpio_renew()), 0)) { +#if defined (DISPLAYTIMEOUT_GPIO) + if (__builtin_expect(((FUNC_PREFIX(gpio_lev(DISPLAYTIMEOUT_GPIO)) == LOW)), 0)) { SetSleep(false); } +#endif } } @@ -349,82 +326,19 @@ class Display { private: void Detect(display::Type tDisplayType); void Detect(uint32_t nRows); - void Detect7Segment() { - m_bHave7Segment = m_I2C.IsConnected(); - - if (m_bHave7Segment) { - m_I2C.WriteRegister(display::segment7::MCP23017_IODIRA, static_cast(0x0000)); // All output - Status(Display7SegmentMessage::INFO_STARTUP); - } - } - - uint16_t GetData(const uint32_t nHexValue) const { - switch (nHexValue) { - case 0: - return display7segment::CH_0; - break; - case 1: - return display7segment::CH_1; - break; - case 2: - return display7segment::CH_2; - break; - case 3: - return display7segment::CH_3; - break; - case 4: - return display7segment::CH_4; - break; - case 5: - return display7segment::CH_5; - break; - case 6: - return display7segment::CH_6; - break; - case 7: - return display7segment::CH_7; - break; - case 8: - return display7segment::CH_8; - break; - case 9: - return display7segment::CH_9; - break; - case 0xa: - return display7segment::CH_A; - break; - case 0xb: - return display7segment::CH_B; - break; - case 0xc: - return display7segment::CH_C; - break; - case 0xd: - return display7segment::CH_D; - break; - case 0xe: - return display7segment::CH_E; - break; - case 0xf: - return display7segment::CH_F; - break; - default: - break; - } - - return display7segment::CH_BLANK; - } private: display::Type m_tType { display::Type::UNKNOWN }; uint32_t m_nMillis { 0 }; HAL_I2C m_I2C; - bool m_bIsSleep { false }; - bool m_bHave7Segment { false }; uint32_t m_nSleepTimeout { 1000 * 60 * display::Defaults::SEEP_TIMEOUT }; - uint8_t m_nContrast { 0x7F }; + + bool m_bIsSleep { false }; bool m_bIsFlippedVertically { false }; +#if defined (CONFIG_DISPLAY_HAVE_7SEGMENT) + bool m_bHave7Segment { false }; +#endif DisplaySet *m_LcdDisplay { nullptr }; static Display *s_pThis; diff --git a/lib-display/include/i2c/ssd1311.h b/lib-display/include/i2c/ssd1311.h index 667f1249..d3d50e40 100644 --- a/lib-display/include/i2c/ssd1311.h +++ b/lib-display/include/i2c/ssd1311.h @@ -34,7 +34,7 @@ class Ssd1311 final: public DisplaySet { public: Ssd1311 (); - ~Ssd1311 () override {} + ~Ssd1311 () override = default; bool Start() override; diff --git a/lib-display/include/spi/config.h b/lib-display/include/spi/config.h index 5cfe2729..1cccce64 100755 --- a/lib-display/include/spi/config.h +++ b/lib-display/include/spi/config.h @@ -2,7 +2,7 @@ * @file config.h * */ -/* Copyright (C) 2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,33 +26,35 @@ #ifndef CONFIG_H #define CONFIG_H +#include + namespace config { #if defined (SPI_LCD_240X240) -static constexpr auto WIDTH = 240U; -static constexpr auto HEIGHT = 240U; +static constexpr uint32_t WIDTH = 240; +static constexpr uint32_t HEIGHT = 240; #elif defined (SPI_LCD_240X320) -static constexpr auto WIDTH = 240U; -static constexpr auto HEIGHT = 320U; +static constexpr uint32_t WIDTH = 240; +static constexpr uint32_t HEIGHT = 320; #else # error lib-display spi config #endif } // namespace config #if defined (H3) -# define SPI_LCD_RST_PIN GPIO_EXT_7 // GPIO6 -# define SPI_LCD_DC_PIN GPIO_EXT_26 // GPIO10 -# define SPI_LCD_BL_PIN GPIO_EXT_22 // GPIO2 -# if defined(SPI_LCD_HAVE_CS_PIN) -# define SPI_LCD_CS_PIN GPIO_EXT_24 // GPIO13 / SPI CS0 +# define SPI_LCD_RST_GPIO GPIO_EXT_7 // GPIO6 +# define SPI_LCD_DC_GPIO GPIO_EXT_26 // GPIO10 +# define SPI_LCD_BL_GPIO GPIO_EXT_22 // GPIO2 +# if defined(SPI_LCD_HAVE_CS_GPIO) +# define SPI_LCD_CS_GPIO GPIO_EXT_24 // GPIO13 / SPI CS0 # endif -#elif defined (GD32) //See board file +#elif defined (GD32) //See board file #else # include "bcm2835.h" -# define SPI_LCD_RST_PIN RPI_V2_GPIO_P1_07 // GPIO4 -# define SPI_LCD_DC_PIN RPI_V2_GPIO_P1_31 // GPIO6 -# define SPI_LCD_BL_PIN RPI_V2_GPIO_P1_29 // GPIO5 -# if defined(SPI_LCD_HAVE_CS_PIN) -# define SPI_LCD_CS_PIN RPI_V2_GPIO_P1_24 // GPIO8 / SPI CS0 +# define SPI_LCD_RST_GPIO RPI_V2_GPIO_P1_07 // GPIO4 +# define SPI_LCD_DC_GPIO RPI_V2_GPIO_P1_31 // GPIO6 +# define SPI_LCD_BL_GPIO RPI_V2_GPIO_P1_29 // GPIO5 +# if defined(SPI_LCD_HAVE_CS_GPIO) +# define SPI_LCD_CS_GPIO RPI_V2_GPIO_P1_24 // GPIO8 / SPI CS0 # endif #endif diff --git a/lib-display/include/spi/display.h b/lib-display/include/spi/display.h index 6ecee92d..0db5ee37 100644 --- a/lib-display/include/spi/display.h +++ b/lib-display/include/spi/display.h @@ -2,7 +2,7 @@ * @file display.h * */ -/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -41,6 +41,10 @@ # include "spi/st7789.h" #endif +#if defined (DISPLAYTIMEOUT_GPIO) +# include "hal_gpio.h" +#endif + #include "hardware.h" class Display { @@ -101,10 +105,6 @@ class Display { m_bClearEndOfLine = true; } - void Status(__attribute__((unused)) Display7SegmentMessage nValue) { } - - void Status(__attribute__((unused)) uint8_t nValue, __attribute__((unused)) bool bHex) {} - void Text(const char *pData, uint32_t nLength) { if (nLength > m_nCols) { nLength = m_nCols; @@ -158,9 +158,8 @@ class Display { Write(m_nRows, pText); } - void TextStatus(const char *pText, Display7SegmentMessage message, uint32_t nConsoleColor = UINT32_MAX) { + void TextStatus(const char *pText, uint32_t nConsoleColor) { TextStatus(pText); - Status(message); if (nConsoleColor == UINT32_MAX) { return; @@ -169,11 +168,6 @@ class Display { console_status(nConsoleColor, pText); } - void TextStatus(const char *pText, uint8_t nValue7Segment, bool bHex = false) { - TextStatus(pText); - Status(nValue7Segment, bHex); - } - void Progress() { static constexpr char SYMBOLS[] = { '/' , '-', '\\' , '|' }; static uint32_t nSymbolsIndex; @@ -242,9 +236,11 @@ class Display { SetSleep(true); } } else { - if (__builtin_expect((display::timeout::gpio_renew()), 0)) { +#if defined (DISPLAYTIMEOUT_GPIO) + if (__builtin_expect(((FUNC_PREFIX(gpio_lev(DISPLAYTIMEOUT_GPIO)) == LOW)), 0)) { SetSleep(false); } +#endif } } diff --git a/lib-display/include/spi/ili9341.h b/lib-display/include/spi/ili9341.h index fe72a20e..ea0eccca 100644 --- a/lib-display/include/spi/ili9341.h +++ b/lib-display/include/spi/ili9341.h @@ -2,7 +2,7 @@ * @file ili9341.h * */ -/* Copyright (C) 2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,25 +32,25 @@ namespace ili9341 { namespace cmd { -static constexpr uint8_t NOP = 0x00; -static constexpr uint8_t SWRESET = 0x01; -static constexpr uint8_t RDDID = 0x04; -static constexpr uint8_t RDDST = 0x09; -static constexpr uint8_t SLPIN = 0x10; -static constexpr uint8_t SLPOUT = 0x11; -static constexpr uint8_t PTLON = 0x12; -static constexpr uint8_t NORON = 0x13; -static constexpr uint8_t INVOFF = 0x20; -static constexpr uint8_t INVON = 0x21; -static constexpr uint8_t DISPOFF = 0x28; -static constexpr uint8_t DISPON = 0x29; -static constexpr uint8_t CASET = 0x2A; -static constexpr uint8_t RASET = 0x2B; -static constexpr uint8_t RAMWR = 0x2C; -static constexpr uint8_t RAMRD = 0x2E; -static constexpr uint8_t PTLAR = 0x30; -static constexpr uint8_t MADCTL = 0x36; -static constexpr uint8_t PIXFMT = 0x3A; +static constexpr uint8_t NOP = 0x00; +static constexpr uint8_t SWRESET = 0x01; +static constexpr uint8_t RDDID = 0x04; +static constexpr uint8_t RDDST = 0x09; +static constexpr uint8_t SLPIN = 0x10; +static constexpr uint8_t SLPOUT = 0x11; +static constexpr uint8_t PTLON = 0x12; +static constexpr uint8_t NORON = 0x13; +static constexpr uint8_t INVOFF = 0x20; +static constexpr uint8_t INVON = 0x21; +static constexpr uint8_t DISPOFF = 0x28; +static constexpr uint8_t DISPON = 0x29; +static constexpr uint8_t CASET = 0x2A; +static constexpr uint8_t RASET = 0x2B; +static constexpr uint8_t RAMWR = 0x2C; +static constexpr uint8_t RAMRD = 0x2E; +static constexpr uint8_t PTLAR = 0x30; +static constexpr uint8_t MADCTL = 0x36; +static constexpr uint8_t PIXFMT = 0x3A; } // namespace cmd namespace data { /** @@ -59,27 +59,26 @@ namespace data { * param: MY MX MV ML RGB MH - - * */ -static constexpr uint8_t MADCTL_MY = 0x80; ///< Page Address Order ('0': Top to Bottom, '1': the opposite) -static constexpr uint8_t MADCTL_MX = 0x40; ///< Column Address Order ('0': Left to Right, '1': the opposite) -static constexpr uint8_t MADCTL_MV = 0x20; ///< Page/Column Order ('0' = Normal Mode, '1' = Reverse Mode) -static constexpr uint8_t MADCTL_ML = 0x10; ///< Line Address Order ('0' = LCD Refresh Top to Bottom, '1' = the opposite) -static constexpr uint8_t MADCTL_RGB = 0x00; ///< Red-Green-Blue pixel order -static constexpr uint8_t MADCTL_BGR = 0x08; ///< Blue-Green-Red pixel order +static constexpr uint8_t MADCTL_MY = 0x80; ///< Page Address Order ('0': Top to Bottom, '1': the opposite) +static constexpr uint8_t MADCTL_MX = 0x40; ///< Column Address Order ('0': Left to Right, '1': the opposite) +static constexpr uint8_t MADCTL_MV = 0x20; ///< Page/Column Order ('0' = Normal Mode, '1' = Reverse Mode) +static constexpr uint8_t MADCTL_ML = 0x10; ///< Line Address Order ('0' = LCD Refresh Top to Bottom, '1' = the opposite) +static constexpr uint8_t MADCTL_RGB = 0x00; ///< Red-Green-Blue pixel order +static constexpr uint8_t MADCTL_BGR = 0x08; ///< Blue-Green-Red pixel order } // namespace data -//TODO Need to sort here namespace colour { -static constexpr uint16_t BLACK = 0x0000; -static constexpr uint16_t WHITE = 0xFFFF; -static constexpr uint16_t RED = 0xF800; -static constexpr uint16_t GREEN = 0x07E0; -static constexpr uint16_t BLUE = 0x001F; -static constexpr uint16_t DARKBLUE = 0X01CF; -static constexpr uint16_t CYAN = 0x07FF; -static constexpr uint16_t MAGENTA = 0xF81F; -static constexpr uint16_t YELLOW = 0xFFE0; -static constexpr uint16_t ORANGE = 0xFC00; -static constexpr uint16_t GRAY = 0X8430; +static constexpr uint16_t BLACK = 0x0000; +static constexpr uint16_t BLUE = 0x001F; +static constexpr uint16_t CYAN = 0x07FF; +static constexpr uint16_t DARKBLUE = 0X01CF; +static constexpr uint16_t GRAY = 0X8430; +static constexpr uint16_t GREEN = 0x07E0; +static constexpr uint16_t MAGENTA = 0xF81F; +static constexpr uint16_t ORANGE = 0xFC00; +static constexpr uint16_t RED = 0xF800; +static constexpr uint16_t WHITE = 0xFFFF; +static constexpr uint16_t YELLOW = 0xFFE0; } // namespace colour } // namespace ili9341 diff --git a/lib-display/include/spi/spi_lcd.h b/lib-display/include/spi/spi_lcd.h index b15481a0..9e379148 100644 --- a/lib-display/include/spi/spi_lcd.h +++ b/lib-display/include/spi/spi_lcd.h @@ -38,31 +38,31 @@ inline static void ms_delay(const uint32_t ms) { } inline static void CS_Set() { -#if defined(SPI_LCD_HAVE_CS_PIN) - FUNC_PREFIX(gpio_set(SPI_LCD_CS_PIN)); +#if defined(SPI_LCD_HAVE_CS_GPIO) + FUNC_PREFIX(gpio_set(SPI_LCD_CS_GPIO)); #endif } inline static void CS_Clear() { -#if defined(SPI_LCD_HAVE_CS_PIN) - FUNC_PREFIX(gpio_clr(SPI_LCD_CS_PIN)); +#if defined(SPI_LCD_HAVE_CS_GPIO) + FUNC_PREFIX(gpio_clr(SPI_LCD_CS_GPIO)); #endif } inline static void DC_Set() { - FUNC_PREFIX(gpio_set(SPI_LCD_DC_PIN)); + FUNC_PREFIX(gpio_set(SPI_LCD_DC_GPIO)); } inline static void DC_Clear() { - FUNC_PREFIX(gpio_clr(SPI_LCD_DC_PIN)); + FUNC_PREFIX(gpio_clr(SPI_LCD_DC_GPIO)); } inline static void HW_Reset() { -#if defined (SPI_LCD_RST_PIN) +#if defined (SPI_LCD_RST_GPIO) ms_delay(200); - FUNC_PREFIX(gpio_clr(SPI_LCD_RST_PIN)); + FUNC_PREFIX(gpio_clr(SPI_LCD_RST_GPIO)); ms_delay(200); - FUNC_PREFIX(gpio_set(SPI_LCD_RST_PIN)); + FUNC_PREFIX(gpio_set(SPI_LCD_RST_GPIO)); ms_delay(200); #endif } diff --git a/lib-display/include/spi/st77xx.h b/lib-display/include/spi/st77xx.h index 0371d4ab..af61b9b7 100644 --- a/lib-display/include/spi/st77xx.h +++ b/lib-display/include/spi/st77xx.h @@ -2,7 +2,7 @@ * @file st77xx.h * */ -/* Copyright (C) 2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,27 +34,27 @@ namespace st77xx { namespace cmd { -static constexpr uint8_t NOP = 0x00; -static constexpr uint8_t SWRESET = 0x01; -static constexpr uint8_t RDDID = 0x04; -static constexpr uint8_t RDDST = 0x09; -static constexpr uint8_t SLPIN = 0x10; -static constexpr uint8_t SLPOUT = 0x11; -static constexpr uint8_t PTLON = 0x12; -static constexpr uint8_t NORON = 0x13; -static constexpr uint8_t INVOFF = 0x20; -static constexpr uint8_t INVON = 0x21; -static constexpr uint8_t DISPOFF = 0x28; -static constexpr uint8_t DISPON = 0x29; -static constexpr uint8_t CASET = 0x2A; -static constexpr uint8_t RASET = 0x2B; -static constexpr uint8_t RAMWR = 0x2C; -static constexpr uint8_t RAMRD = 0x2E; -static constexpr uint8_t PTLAR = 0x30; -static constexpr uint8_t TEOFF = 0x34; -static constexpr uint8_t TEON = 0x35; -static constexpr uint8_t MADCTL = 0x36; -static constexpr uint8_t COLMOD = 0x3A; +static constexpr uint8_t NOP = 0x00; +static constexpr uint8_t SWRESET = 0x01; +static constexpr uint8_t RDDID = 0x04; +static constexpr uint8_t RDDST = 0x09; +static constexpr uint8_t SLPIN = 0x10; +static constexpr uint8_t SLPOUT = 0x11; +static constexpr uint8_t PTLON = 0x12; +static constexpr uint8_t NORON = 0x13; +static constexpr uint8_t INVOFF = 0x20; +static constexpr uint8_t INVON = 0x21; +static constexpr uint8_t DISPOFF = 0x28; +static constexpr uint8_t DISPON = 0x29; +static constexpr uint8_t CASET = 0x2A; +static constexpr uint8_t RASET = 0x2B; +static constexpr uint8_t RAMWR = 0x2C; +static constexpr uint8_t RAMRD = 0x2E; +static constexpr uint8_t PTLAR = 0x30; +static constexpr uint8_t TEOFF = 0x34; +static constexpr uint8_t TEON = 0x35; +static constexpr uint8_t MADCTL = 0x36; +static constexpr uint8_t COLMOD = 0x3A; } // namespace cmd namespace data { /** @@ -64,30 +64,29 @@ namespace data { * */ /* Page Address Order ('0': Top to Bottom, '1': the opposite) */ -static constexpr uint8_t MADCTL_MY = 0x80; +static constexpr uint8_t MADCTL_MY = 0x80; /* Column Address Order ('0': Left to Right, '1': the opposite) */ -static constexpr uint8_t MADCTL_MX = 0x40; +static constexpr uint8_t MADCTL_MX = 0x40; /* Page/Column Order ('0' = Normal Mode, '1' = Reverse Mode) */ -static constexpr uint8_t MADCTL_MV = 0x20; +static constexpr uint8_t MADCTL_MV = 0x20; /* Line Address Order ('0' = LCD Refresh Top to Bottom, '1' = the opposite) */ -static constexpr uint8_t MADCTL_ML = 0x10; +static constexpr uint8_t MADCTL_ML = 0x10; /* RGB/BGR Order ('0' = RGB, '1' = BGR) */ -static constexpr uint8_t MADCTL_RGB = 0x00; +static constexpr uint8_t MADCTL_RGB = 0x00; } // namespace data -//TODO Need to sort here namespace colour { -static constexpr uint16_t BLACK = 0x0000; -static constexpr uint16_t WHITE = 0xFFFF; -static constexpr uint16_t RED = 0xF800; -static constexpr uint16_t GREEN = 0x07E0; -static constexpr uint16_t BLUE = 0x001F; -static constexpr uint16_t DARKBLUE = 0X01CF; -static constexpr uint16_t CYAN = 0x07FF; -static constexpr uint16_t MAGENTA = 0xF81F; -static constexpr uint16_t YELLOW = 0xFFE0; -static constexpr uint16_t ORANGE = 0xFC00; -static constexpr uint16_t GRAY = 0X8430; +static constexpr uint16_t BLACK = 0x0000; +static constexpr uint16_t BLUE = 0x001F; +static constexpr uint16_t CYAN = 0x07FF; +static constexpr uint16_t DARKBLUE = 0X01CF; +static constexpr uint16_t GRAY = 0X8430; +static constexpr uint16_t GREEN = 0x07E0; +static constexpr uint16_t MAGENTA = 0xF81F; +static constexpr uint16_t ORANGE = 0xFC00; +static constexpr uint16_t RED = 0xF800; +static constexpr uint16_t WHITE = 0xFFFF; +static constexpr uint16_t YELLOW = 0xFFE0; } // namespace colour } // namespace st77xx diff --git a/lib-display/src/i2c/display.cpp b/lib-display/src/i2c/display.cpp index 649b43b9..ba2efcb1 100644 --- a/lib-display/src/i2c/display.cpp +++ b/lib-display/src/i2c/display.cpp @@ -2,7 +2,7 @@ * @file display.cpp * */ -/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,17 +29,27 @@ #include "display.h" #include "displayset.h" -#if defined(CONFIG_DISPLAY_ENABLE_HD44780) -# include "i2c/hd44780.h" -#endif #include "i2c/ssd1306.h" #if defined(CONFIG_DISPLAY_ENABLE_SSD1311) # include "i2c/ssd1311.h" #endif - -#include "display7segment.h" +#if defined(CONFIG_DISPLAY_ENABLE_HD44780) +# include "i2c/hd44780.h" +#endif #include "hal_i2c.h" +#include "hal_gpio.h" + +namespace display { +namespace timeout { +static void gpio_init() { +#if defined (DISPLAYTIMEOUT_GPIO) + FUNC_PREFIX(gpio_fsel(DISPLAYTIMEOUT_GPIO, GPIO_FSEL_INPUT)); + FUNC_PREFIX(gpio_set_pud(DISPLAYTIMEOUT_GPIO, GPIO_PULL_UP)); +#endif +} +} // namespace timeout +} // namespace display Display *Display::s_pThis; @@ -55,8 +65,6 @@ Display::Display() : m_nMillis(Hardware::Get()->Millis()), m_I2C(display::segmen Detect(display::Type::SSD1306); } - Detect7Segment(); - if (m_LcdDisplay != nullptr) { display::timeout::gpio_init(); } @@ -70,8 +78,6 @@ Display::Display(uint32_t nRows) : m_nMillis(Hardware::Get()->Millis()), m_I2C(d Detect(nRows); - Detect7Segment(); - if (m_LcdDisplay != nullptr) { display::timeout::gpio_init(); } @@ -85,8 +91,6 @@ Display::Display(display::Type type): m_tType(type), m_nMillis(Hardware::Get()-> Detect(type); - Detect7Segment(); - if (m_LcdDisplay != nullptr) { display::timeout::gpio_init(); } diff --git a/lib-display/src/i2c/hd44780.cpp b/lib-display/src/i2c/hd44780.cpp index 070476ec..43990fc2 100644 --- a/lib-display/src/i2c/hd44780.cpp +++ b/lib-display/src/i2c/hd44780.cpp @@ -2,7 +2,7 @@ * @file hd44780.cpp * */ -/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -168,7 +168,7 @@ void Hd44780::ClearLine(uint32_t nLine) { } void Hd44780::PrintInfo() { - printf("HD44780 [PCF8574T] (%d,%d)\n", m_nRows, m_nCols); + printf("HD44780 [PCF8574T] (%u,%u)\n", static_cast(m_nRows), static_cast(m_nCols)); } void Hd44780::SetCursorPos(uint32_t nCol, uint32_t nRow) { @@ -200,7 +200,7 @@ void Hd44780::WriteReg(const uint8_t nReg) { #if defined(CONFIG_DISPLAY_ENABLE_CURSOR_MODE) # define UNUSED #else -# define UNUSED __attribute__((unused)) +# define UNUSED [[maybe_unused]] #endif void Hd44780::SetCursor(UNUSED uint32_t nMode) { diff --git a/lib-display/src/i2c/ssd1306.cpp b/lib-display/src/i2c/ssd1306.cpp index 5281a4fe..1829c105 100644 --- a/lib-display/src/i2c/ssd1306.cpp +++ b/lib-display/src/i2c/ssd1306.cpp @@ -233,7 +233,7 @@ Ssd1306::Ssd1306(uint8_t nSlaveAddress, TOledPanel tOledPanel) : m_I2C(nSlaveAdd } void Ssd1306::PrintInfo() { - printf("%s (%d,%d)\n", m_bHaveSH1106 ? "SH1106" : "SSD1306", m_nRows, m_nCols); + printf("%s (%u,%u)\n", m_bHaveSH1106 ? "SH1106" : "SSD1306", static_cast(m_nRows), static_cast(m_nCols)); } void Ssd1306::CheckSH1106() { @@ -513,7 +513,7 @@ void Ssd1306::SendData(const uint8_t *pData, uint32_t nLength) { #if defined(CONFIG_DISPLAY_ENABLE_CURSOR_MODE) # define UNUSED #else -# define UNUSED __attribute__((unused)) +# define UNUSED [[maybe_unused]] #endif void Ssd1306::SetCursor(UNUSED uint32_t nCursorMode) { diff --git a/lib-display/src/i2c/ssd1311.cpp b/lib-display/src/i2c/ssd1311.cpp index 5c9c76d8..712e48ad 100644 --- a/lib-display/src/i2c/ssd1311.cpp +++ b/lib-display/src/i2c/ssd1311.cpp @@ -101,7 +101,7 @@ bool Ssd1311::Start() { } void Ssd1311::PrintInfo() { - printf("SSD1311 (%d,%d)\n", m_nRows, m_nCols); + printf("SSD1311 (%u,%u)\n", static_cast(m_nRows), static_cast(m_nCols)); } void Ssd1311::Cls() { @@ -338,7 +338,7 @@ void Ssd1311::SetContrast(uint8_t nContrast) { #if defined(CONFIG_DISPLAY_ENABLE_CURSOR_MODE) # define UNUSED #else -# define UNUSED __attribute__((unused)) +# define UNUSED [[maybe_unused]] #endif void Ssd1311::SetCursor(UNUSED uint32_t nMode) { diff --git a/lib-display/src/spi/display.cpp b/lib-display/src/spi/display.cpp index 23f91db0..33018c23 100644 --- a/lib-display/src/spi/display.cpp +++ b/lib-display/src/spi/display.cpp @@ -2,7 +2,7 @@ * @file display.cpp * */ -/* Copyright (C) 2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -58,13 +58,13 @@ Display::Display() : m_nMillis(Hardware::Get()->Millis()) { FUNC_PREFIX(spi_set_speed_hz(20000000)); FUNC_PREFIX(spi_setDataMode(SPI_MODE0)); -#if defined (SPI_LCD_RST_PIN) - FUNC_PREFIX(gpio_fsel(SPI_LCD_RST_PIN, GPIO_FSEL_OUTPUT)); +#if defined (SPI_LCD_RST_GPIO) + FUNC_PREFIX(gpio_fsel(SPI_LCD_RST_GPIO, GPIO_FSEL_OUTPUT)); #endif - FUNC_PREFIX(gpio_fsel(SPI_LCD_DC_PIN, GPIO_FSEL_OUTPUT)); - FUNC_PREFIX(gpio_fsel(SPI_LCD_BL_PIN, GPIO_FSEL_OUTPUT)); -#if defined(SPI_LCD_HAVE_CS_PIN) - FUNC_PREFIX(gpio_fsel(SPI_LCD_CS_PIN, GPIO_FSEL_OUTPUT)); + FUNC_PREFIX(gpio_fsel(SPI_LCD_DC_GPIO, GPIO_FSEL_OUTPUT)); + FUNC_PREFIX(gpio_fsel(SPI_LCD_BL_GPIO, GPIO_FSEL_OUTPUT)); +#if defined(SPI_LCD_HAVE_CS_GPIO) + FUNC_PREFIX(gpio_fsel(SPI_LCD_CS_GPIO, GPIO_FSEL_OUTPUT)); #endif SpiLcd.SetBackLight(1); @@ -75,7 +75,10 @@ Display::Display() : m_nMillis(Hardware::Get()->Millis()) { m_nCols = static_cast(SpiLcd.GetWidth() / s_pFONT->Width); m_nRows = static_cast(SpiLcd.GetHeight() / s_pFONT->Height); - display::timeout::gpio_init(); +#if defined (DISPLAYTIMEOUT_GPIO) + FUNC_PREFIX(gpio_fsel(DISPLAYTIMEOUT_GPIO, GPIO_FSEL_INPUT)); + FUNC_PREFIX(gpio_set_pud(DISPLAYTIMEOUT_GPIO, GPIO_PULL_UP)); +#endif PrintInfo(); DEBUG_EXIT diff --git a/lib-display/src/spi/ili9341.cpp b/lib-display/src/spi/ili9341.cpp index f79903ed..2a9b40f1 100644 --- a/lib-display/src/spi/ili9341.cpp +++ b/lib-display/src/spi/ili9341.cpp @@ -50,7 +50,7 @@ ILI9341::~ILI9341() { void ILI9341::Init() { DEBUG_ENTRY -#if defined(SPI_LCD_RST_PIN) +#if defined(SPI_LCD_RST_GPIO) HW_Reset(); #endif @@ -161,7 +161,7 @@ void ILI9341::SetRotation(uint32_t nRotation) { } void ILI9341::SetBackLight(uint32_t nValue) { - FUNC_PREFIX(gpio_write(SPI_LCD_BL_PIN, nValue == 0 ? LOW : HIGH)); + FUNC_PREFIX(gpio_write(SPI_LCD_BL_GPIO, nValue == 0 ? LOW : HIGH)); } void ILI9341::EnableDisplay(bool bEnable) { diff --git a/lib-display/src/spi/st7789.cpp b/lib-display/src/spi/st7789.cpp index 4a340097..0a25be27 100644 --- a/lib-display/src/spi/st7789.cpp +++ b/lib-display/src/spi/st7789.cpp @@ -51,7 +51,7 @@ ST7789::~ST7789() { void ST7789::Init() { DEBUG_ENTRY -#if defined(SPI_LCD_RST_PIN) +#if defined(SPI_LCD_RST_GPIO) HW_Reset(); #endif diff --git a/lib-display/src/spi/st7xx.cpp b/lib-display/src/spi/st7xx.cpp index d4ddaefc..cf613c97 100644 --- a/lib-display/src/spi/st7xx.cpp +++ b/lib-display/src/spi/st7xx.cpp @@ -58,7 +58,7 @@ void ST77XX::EnableSleep(bool bEnable) { //TODO This should be a PWM pin void ST77XX::SetBackLight(uint32_t nValue) { - FUNC_PREFIX(gpio_write(SPI_LCD_BL_PIN, nValue == 0 ? LOW : HIGH)); + FUNC_PREFIX(gpio_write(SPI_LCD_BL_GPIO, nValue == 0 ? LOW : HIGH)); } void ST77XX::SetAddressWindow(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1) { diff --git a/lib-displayudf/.cproject b/lib-displayudf/.cproject index ed8e9c9d..73bad53a 100644 --- a/lib-displayudf/.cproject +++ b/lib-displayudf/.cproject @@ -30,12 +30,10 @@ - diff --git a/lib-displayudf/Rules.mk b/lib-displayudf/Rules.mk index 582d95d9..4ef90723 100644 --- a/lib-displayudf/Rules.mk +++ b/lib-displayudf/Rules.mk @@ -6,21 +6,31 @@ ifneq ($(MAKE_FLAGS),) EXTRA_INCLUDES+=../lib-rdm/include ../lib-rdmdiscovery/include EXTRA_SRCDIR+=src/node endif + ifneq (,$(findstring NODE_ARTNET,$(MAKE_FLAGS))) EXTRA_INCLUDES+=../lib-artnet/include EXTRA_SRCDIR+=src/artnet ifeq ($(findstring ARTNET_VERSION=4,$(MAKE_FLAGS)), ARTNET_VERSION=4) EXTRA_INCLUDES+=../lib-e131/include endif + EXTRA_INCLUDES+=../lib-dmx/include endif + ifneq (,$(findstring NODE_E131,$(MAKE_FLAGS))) EXTRA_INCLUDES+=../lib-e131/include + EXTRA_INCLUDES+=../lib-dmx/include EXTRA_SRCDIR+=src/e131 endif + ifeq (,$(findstring NO_EMAC,$(MAKE_FLAGS))) EXTRA_INCLUDES+=../lib-network/include EXTRA_SRCDIR+=src/network endif + + ifneq (,$(findstring RDM_CONTROLLER,$(MAKE_FLAGS))) + EXTRA_INCLUDES+=../lib-rdm/include + endif + ifneq (,$(findstring RDM_RESPONDER,$(MAKE_FLAGS))) EXTRA_INCLUDES+=../lib-rdmresponder/include ../lib-rdm/include ../lib-rdmsensor/include ../lib-rdmsubdevice/include ifneq (,$(findstring NODE_ARTNET,$(MAKE_FLAGS))) @@ -28,16 +38,25 @@ ifneq ($(MAKE_FLAGS),) EXTRA_INCLUDES+=../lib-dmxreceiver/include ../lib-dmx/include endif endif + + ifneq (,$(findstring CONFIG_STORE_USE_ROM,$(MAKE_FLAGS))) + EXTRA_INCLUDES+=../lib-flashcode/include + endif else - DEFINES+=NODE_ARTNET NODE_E131 OUTPUT_DMX_ARTNET RDM_RESPONDER + ifneq (, $(shell test -d '../lib-network/src/noemac' && echo -n yes)) + DEFINES+=NO_EMAC + else + DEFINES+=NODE_ARTNET NODE_E131 OUTPUT_DMX_ARTNET + DEFINES+=ARTNET_VERSION=4 + EXTRA_SRCDIR+=src/artnet src/e131 src/network + EXTRA_INCLUDES+=../lib-artnet/include ../lib-e131/include ../lib-network/include + EXTRA_INCLUDES+=../lib-node/include + endif + + DEFINES+=RDM_RESPONDER DEFINES+=LIGHTSET_PORTS=4 - DEFINES+=ARTNET_VERSION=4 - EXTRA_INCLUDES+=../lib-node/include - EXTRA_INCLUDES+=../lib-artnet/include ../lib-e131/include ../lib-network/include EXTRA_INCLUDES+=../lib-dmxreceiver/include ../lib-dmx/include EXTRA_INCLUDES+=../lib-rdmdiscovery/include - EXTRA_INCLUDES+=../lib-rdmresponder/include ../lib-rdm/include ../lib-rdmsensor/include ../lib-rdmsubdevice/include - - EXTRA_SRCDIR+=src/artnet src/e131 src/network + EXTRA_INCLUDES+=../lib-rdm/include ../lib-rdmsensor/include ../lib-rdmsubdevice/include endif \ No newline at end of file diff --git a/lib-displayudf/include/displayudf.h b/lib-displayudf/include/displayudf.h index 1aae9355..d36ac873 100644 --- a/lib-displayudf/include/displayudf.h +++ b/lib-displayudf/include/displayudf.h @@ -2,7 +2,7 @@ * @file displayudf.h * */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,6 +33,7 @@ #if !defined (NO_EMAC) # include "network.h" +# include "net/protocol/dhcp.h" #endif #if defined (NODE_ARTNET_MULTI) @@ -60,11 +61,7 @@ #endif #if defined (RDM_RESPONDER) -# if defined (NODE_ARTNET) -# include "artnetrdmresponder.h" -# else -# include "rdmresponder.h" -# endif +# include "rdmdeviceresponder.h" #endif namespace displayudf { @@ -164,33 +161,12 @@ class DisplayUdf final: public Display { void Show(); - /** - * Node - */ - -#if defined (NODE_NODE) - void Show(Node *pNode); - void ShowNodeName(); - void ShowUniverse(); - void ShowDestinationIp(); -#endif - /** * Art-Net */ #if defined (NODE_ARTNET) - void Show(ArtNetNode *pArtNetNode, uint32_t nPortIndexOffset = 0); - void ShowUniverse(ArtNetNode *pArtNetNode); - void ShowDestinationIp(ArtNetNode *pArtNetNode); -#endif - - /** - * sACN E1.31 - */ - -#if defined (NODE_E131) - void Show(E131Bridge *pE131Bridge, uint32_t nPortIndexOffset = 0); + void ShowUniverseArtNetNode(); #endif /** @@ -219,13 +195,8 @@ class DisplayUdf final: public Display { #if defined (RDM_RESPONDER) void ShowDmxStartAddress() { -# if defined (NODE_ARTNET) - const auto nDmxStartAddress = ArtNetRdmResponder::Get()->GetDmxStartAddress(); - const auto nDmxFootprint = ArtNetRdmResponder::Get()->GetDmxFootPrint(); -# else - const auto nDmxStartAddress = RDMResponder::Get()->GetDmxStartAddress(); - const auto nDmxFootprint = RDMResponder::Get()->GetDmxFootPrint(); -# endif + const auto nDmxStartAddress = RDMDeviceResponder::Get()->GetDmxStartAddress(); + const auto nDmxFootprint = RDMDeviceResponder::Get()->GetDmxFootPrint(); Printf(m_aLabels[static_cast(displayudf::Labels::DMX_START_ADDRESS)], "DMX S:%3u F:%3u", nDmxStartAddress, nDmxFootprint); } #endif @@ -271,25 +242,15 @@ class DisplayUdf final: public Display { Write(m_aLabels[static_cast(displayudf::Labels::HOSTNAME)], Network::Get()->GetHostName()); } - void ShowDhcpStatus(network::dhcp::ClientStatus nStatus) { - switch (nStatus) { - case network::dhcp::ClientStatus::IDLE: + void ShowDhcpStatus(net::dhcp::State state) { + switch (state) { + case net::dhcp::State::STATE_OFF: break; - case network::dhcp::ClientStatus::RENEW: - Display::Get()->Status(Display7SegmentMessage::INFO_DHCP); + case net::dhcp::State::STATE_RENEWING: ClearEndOfLine(); Printf(m_aLabels[static_cast(displayudf::Labels::IP)], "DHCP renewing"); break; - case network::dhcp::ClientStatus::GOT_IP: - Display::Get()->Status(Display7SegmentMessage::INFO_NONE); - break; - case network::dhcp::ClientStatus::RETRYING: - Display::Get()->Status(Display7SegmentMessage::INFO_DHCP); - ClearEndOfLine(); - Printf(m_aLabels[static_cast(displayudf::Labels::IP)], "DHCP retrying"); - break; - case network::dhcp::ClientStatus::FAILED: - Display::Get()->Status(Display7SegmentMessage::ERROR_DHCP); + case net::dhcp::State::STATE_BOUND: break; default: break; @@ -297,7 +258,7 @@ class DisplayUdf final: public Display { } void ShowShutdown() { - TextStatus("Network shutdown", Display7SegmentMessage::INFO_NETWORK_SHUTDOWN); + TextStatus("Network shutdown"); } #endif @@ -305,12 +266,38 @@ class DisplayUdf final: public Display { return s_pThis; } +private: + /** + * Art-Net + */ + +#if defined (NODE_ARTNET) + void ShowArtNetNode(); + void ShowDestinationIpArtNetNode(); +#endif + + /** + * sACN E1.31 + */ + +#if defined (NODE_E131) + void ShowE131Bridge(); +#endif + + /** + * Node + */ + +#if defined (NODE_NODE) + void ShowNode(); + void ShowNodeNameNode(); + void ShowUniverseNode(); + void ShowDestinationIpNode(); +#endif + private: char m_aTitle[32]; uint8_t m_aLabels[static_cast(displayudf::Labels::UNKNOWN)]; -#if defined (NODE_ARTNET) || defined (NODE_E131) - uint32_t m_nPortIndexOffset { 0 }; -#endif #if defined (DISPLAYUDF_DMX_INFO) struct DmxInfo { displayudf::dmx::PortDir portDir; diff --git a/lib-displayudf/include/displayudfparams.h b/lib-displayudf/include/displayudfparams.h index f50d4a66..b2c85c5b 100644 --- a/lib-displayudf/include/displayudfparams.h +++ b/lib-displayudf/include/displayudfparams.h @@ -29,6 +29,7 @@ #include #include "displayudf.h" +#include "configstore.h" namespace displayudfparams { struct Params { @@ -50,39 +51,40 @@ struct Mask { class DisplayUdfParamsStore { public: - virtual ~DisplayUdfParamsStore() {} + static void Update(const struct displayudfparams::Params *pParams) { + ConfigStore::Get()->Update(configstore::Store::DISPLAYUDF, pParams, sizeof(struct displayudfparams::Params)); + } - virtual void Update(const struct displayudfparams::Params *ptDisplayUdfParams)=0; - virtual void Copy(struct displayudfparams::Params *ptDisplayUdfParams)=0; + static void Copy(struct displayudfparams::Params *pParams) { + ConfigStore::Get()->Copy(configstore::Store::DISPLAYUDF, pParams, sizeof(struct displayudfparams::Params)); + } }; class DisplayUdfParams { public: - DisplayUdfParams(DisplayUdfParamsStore *pDisplayUdfParamsStore); + DisplayUdfParams(); - bool Load(); + void Load(); void Load(const char *pBuffer, uint32_t nLength); - void Builder(const struct displayudfparams::Params *ptDisplayUdfParams, char *pBuffer, uint32_t nLength, uint32_t& nSize); + void Builder(const struct displayudfparams::Params *pParams, char *pBuffer, uint32_t nLength, uint32_t& nSize); void Save(char *pBuffer, uint32_t nLength, uint32_t& nSize) { Builder(nullptr, pBuffer, nLength, nSize); } void Set(DisplayUdf *pDisplayUdf); - void Dump(); - static void staticCallbackFunction(void *p, const char *s); private: + void Dump(); void callbackFunction(const char *s); bool isMaskSet(uint32_t nMask) const { - return (m_tDisplayUdfParams.nSetList & nMask) == nMask; + return (m_Params.nSetList & nMask) == nMask; } private: - DisplayUdfParamsStore *m_pDisplayUdfParamsStore; - displayudfparams::Params m_tDisplayUdfParams; + displayudfparams::Params m_Params; }; #endif /* DISPLAYUDFPARAMS_H_ */ diff --git a/lib-displayudf/include/displayudfparamsconst.h b/lib-displayudf/include/displayudfparamsconst.h index bb5c9a22..993f92c5 100644 --- a/lib-displayudf/include/displayudfparamsconst.h +++ b/lib-displayudf/include/displayudfparamsconst.h @@ -2,7 +2,7 @@ * @file displayudfparamsconst.h * */ -/* Copyright (C) 2019-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-displayudf/src/artnet/artnetdisplay.cpp b/lib-displayudf/src/artnet/artnetdisplay.cpp index d173f76d..2a73757e 100644 --- a/lib-displayudf/src/artnet/artnetdisplay.cpp +++ b/lib-displayudf/src/artnet/artnetdisplay.cpp @@ -2,7 +2,7 @@ * @file artnetdisplay.cpp * */ -/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -30,38 +30,38 @@ #include "lightset.h" namespace artnet { -void display_longname(__attribute__((unused)) const char *pLongName) { +void display_longname([[maybe_unused]] const char *pLongName) { } -void display_universe_switch(__attribute__((unused)) uint32_t nPortIndex, __attribute__((unused)) uint8_t nAddress) { - DisplayUdf::Get()->ShowUniverse(ArtNetNode::Get()); +void display_universe_switch([[maybe_unused]] uint32_t nPortIndex, [[maybe_unused]] uint8_t nAddress) { + DisplayUdf::Get()->ShowUniverseArtNetNode(); } -void display_net_switch(__attribute__((unused)) uint8_t nAddress) { - DisplayUdf::Get()->ShowUniverse(ArtNetNode::Get()); +void display_net_switch([[maybe_unused]] uint8_t nAddress) { + DisplayUdf::Get()->ShowUniverseArtNetNode(); } -void display_subnet_switch(__attribute__((unused)) uint8_t nAddress) { - DisplayUdf::Get()->ShowUniverse(ArtNetNode::Get()); +void display_subnet_switch([[maybe_unused]] uint8_t nAddress) { + DisplayUdf::Get()->ShowUniverseArtNetNode(); } -void display_merge_mode(__attribute__((unused)) uint32_t nPortIndex, __attribute__((unused)) lightset::MergeMode mergeMode) { - DisplayUdf::Get()->ShowUniverse(ArtNetNode::Get()); +void display_merge_mode([[maybe_unused]] uint32_t nPortIndex, [[maybe_unused]] lightset::MergeMode mergeMode) { + DisplayUdf::Get()->ShowUniverseArtNetNode(); } -void display_outputstyle(__attribute__((unused)) const uint32_t nPortIndex, __attribute__((unused)) const lightset::OutputStyle outputStyle) { - DisplayUdf::Get()->ShowUniverse(ArtNetNode::Get()); +void display_outputstyle([[maybe_unused]] const uint32_t nPortIndex, [[maybe_unused]] const lightset::OutputStyle outputStyle) { + DisplayUdf::Get()->ShowUniverseArtNetNode(); } -void display_port_protocol(__attribute__((unused)) uint32_t nPortIndex, __attribute__((unused)) artnet::PortProtocol tPortProtocol) { - DisplayUdf::Get()->ShowUniverse(ArtNetNode::Get()); +void display_port_protocol([[maybe_unused]] uint32_t nPortIndex, [[maybe_unused]] artnet::PortProtocol tPortProtocol) { + DisplayUdf::Get()->ShowUniverseArtNetNode(); } -void display_rdm_enabled(__attribute__((unused)) uint32_t nPortIndex, __attribute__((unused)) bool isEnabled) { - DisplayUdf::Get()->ShowUniverse(ArtNetNode::Get()); +void display_rdm_enabled([[maybe_unused]] uint32_t nPortIndex, [[maybe_unused]] bool isEnabled) { + DisplayUdf::Get()->ShowUniverseArtNetNode(); } -void display_failsafe(__attribute__((unused)) uint8_t nFailsafe) { +void display_failsafe([[maybe_unused]] uint8_t nFailsafe) { //TODO ShowFailSafe } } // namespace artnet diff --git a/lib-displayudf/src/artnet/displayudfshowartnet.cpp b/lib-displayudf/src/artnet/displayudfshowartnet.cpp index 93195b16..3f4039ed 100644 --- a/lib-displayudf/src/artnet/displayudfshowartnet.cpp +++ b/lib-displayudf/src/artnet/displayudfshowartnet.cpp @@ -2,7 +2,7 @@ * @file displayudfshowartnet.cpp * */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -35,18 +35,21 @@ #include "debug.h" -void DisplayUdf::Show(ArtNetNode *pArtNetNode, uint32_t nDmxPortIndexOffset) { - DEBUG_ENTRY - - m_nPortIndexOffset = nDmxPortIndexOffset; +namespace artnetnode { +namespace configstore { +extern uint32_t DMXPORT_OFFSET; +} // namespace configstore +} // namespace artnetnode - DEBUG_PRINTF("m_nPortIndexOffset=%u", m_nPortIndexOffset); +void DisplayUdf::ShowArtNetNode() { + DEBUG_ENTRY + DEBUG_PRINTF("artnetnode::configstore::DMXPORT_OFFSET=%u", artnetnode::configstore::DMXPORT_OFFSET); - Show(); + auto *pArtNetNode = ArtNetNode::Get(); - ShowUniverse(pArtNetNode); + ShowUniverseArtNetNode(); #if defined (ARTNET_HAVE_DMXIN) - ShowDestinationIp(pArtNetNode); + ShowDestinationIpArtNetNode(); #endif Printf(m_aLabels[static_cast(displayudf::Labels::AP)], "AP: %d", pArtNetNode->GetActiveOutputPorts() + pArtNetNode->GetActiveInputPorts()); @@ -55,12 +58,14 @@ void DisplayUdf::Show(ArtNetNode *pArtNetNode, uint32_t nDmxPortIndexOffset) { DEBUG_EXIT } -void DisplayUdf::ShowUniverse(ArtNetNode *pArtNetNode) { +void DisplayUdf::ShowUniverseArtNetNode() { DEBUG_ENTRY + + auto *pArtNetNode = ArtNetNode::Get(); uint16_t nUniverse; for (uint32_t nArtNetPortIndex = 0; nArtNetPortIndex < std::min(artnet::PORTS, artnetnode::MAX_PORTS); nArtNetPortIndex++) { - const auto nPortIndex = nArtNetPortIndex + m_nPortIndexOffset; + const auto nPortIndex = nArtNetPortIndex + artnetnode::configstore::DMXPORT_OFFSET; if (nPortIndex >= std::min(artnet::PORTS, artnetnode::MAX_PORTS)) { break; @@ -80,7 +85,11 @@ void DisplayUdf::ShowUniverse(ArtNetNode *pArtNetNode) { 'A' + nArtNetPortIndex, nUniverse, lightset::get_merge_mode(pArtNetNode->GetMergeMode(nPortIndex), true), +#if (ARTNET_VERSION >= 4) artnet::get_protocol_mode(pArtNetNode->GetPortProtocol4(nPortIndex), true), +#else + "Art-Net", +#endif #if defined (OUTPUT_HAVE_STYLESWITCH) pArtNetNode->GetOutputStyle(nPortIndex) == lightset::OutputStyle::CONSTANT ? 'C' : 'D', #endif @@ -93,9 +102,11 @@ void DisplayUdf::ShowUniverse(ArtNetNode *pArtNetNode) { DEBUG_EXIT } -void DisplayUdf::ShowDestinationIp(ArtNetNode *pArtNetNode) { +void DisplayUdf::ShowDestinationIpArtNetNode() { DEBUG_ENTRY + auto *pArtNetNode = ArtNetNode::Get(); + for (uint32_t nPortIndex = 0; nPortIndex < std::min(artnet::PORTS, artnetnode::MAX_PORTS); nPortIndex++) { Printf(m_aLabels[static_cast(displayudf::Labels::DESTINATION_IP_PORT_A) + nPortIndex], "%c: " IPSTR, 'A' + nPortIndex, IP2STR(pArtNetNode->GetDestinationIp(nPortIndex))); } diff --git a/lib-displayudf/src/displayudf.cpp b/lib-displayudf/src/displayudf.cpp index 4917c844..2548254e 100644 --- a/lib-displayudf/src/displayudf.cpp +++ b/lib-displayudf/src/displayudf.cpp @@ -29,9 +29,7 @@ #include #include "displayudf.h" - #include "display.h" -#include "display7segment.h" #include "lightset.h" #include "network.h" @@ -87,6 +85,14 @@ void DisplayUdf::Set(uint32_t nLine, Labels label) { } void DisplayUdf::Show() { +#if defined (NODE_ARTNET) + ShowArtNetNode(); +#elif defined (NODE_E131) + ShowE131Bridge(); +#elif defined (NODE_NODE) + ShowNode(); +#endif + for (uint32_t i = 0; i < static_cast(Labels::UNKNOWN); i++) { if (m_aLabels[i] > LABEL_MAX_ROWS) { m_aLabels[i] = 0xFF; diff --git a/lib-displayudf/src/displayudfparams.cpp b/lib-displayudf/src/displayudfparams.cpp index 00e122a6..50081b1b 100644 --- a/lib-displayudf/src/displayudfparams.cpp +++ b/lib-displayudf/src/displayudfparams.cpp @@ -51,7 +51,6 @@ #include "readconfigfile.h" #include "sscan.h" - #include "propertiesbuilder.h" #include "display.h" @@ -140,31 +139,34 @@ static constexpr const char *pArray[static_cast(Labels::UNKNOWN)] = { # undef MAX_ARRAY #endif -DisplayUdfParams::DisplayUdfParams(DisplayUdfParamsStore *pDisplayUdfParamsStore): m_pDisplayUdfParamsStore(pDisplayUdfParamsStore) { - memset(&m_tDisplayUdfParams, 0, sizeof(struct displayudfparams::Params)); - m_tDisplayUdfParams.nSleepTimeout = display::Defaults::SEEP_TIMEOUT; - m_tDisplayUdfParams.nIntensity = defaults::INTENSITY; +DisplayUdfParams::DisplayUdfParams() { + DEBUG_ENTRY + + memset(&m_Params, 0, sizeof(struct displayudfparams::Params)); + m_Params.nSleepTimeout = display::Defaults::SEEP_TIMEOUT; + m_Params.nIntensity = defaults::INTENSITY; + + DEBUG_EXIT } -bool DisplayUdfParams::Load() { - m_tDisplayUdfParams.nSetList = 0; +void DisplayUdfParams::Load() { + DEBUG_ENTRY + + m_Params.nSetList = 0; #if !defined(DISABLE_FS) ReadConfigFile configfile(DisplayUdfParams::staticCallbackFunction, this); if (configfile.Read(DisplayUdfParamsConst::FILE_NAME)) { - if (m_pDisplayUdfParamsStore != nullptr) { - m_pDisplayUdfParamsStore->Update(&m_tDisplayUdfParams); - } + DisplayUdfParamsStore::Update(&m_Params); } else #endif - if (m_pDisplayUdfParamsStore != nullptr) { - m_pDisplayUdfParamsStore->Copy(&m_tDisplayUdfParams); - } else { - return false; - } + DisplayUdfParamsStore::Copy(&m_Params); - return true; +#ifndef NDEBUG + Dump(); +#endif + DEBUG_EXIT } void DisplayUdfParams::Load(const char *pBuffer, uint32_t nLength) { @@ -173,15 +175,17 @@ void DisplayUdfParams::Load(const char *pBuffer, uint32_t nLength) { assert(pBuffer != nullptr); assert(nLength != 0); - m_tDisplayUdfParams.nSetList = 0; + m_Params.nSetList = 0; ReadConfigFile config(DisplayUdfParams::staticCallbackFunction, this); config.Read(pBuffer, nLength); - assert(m_pDisplayUdfParamsStore != nullptr); - m_pDisplayUdfParamsStore->Update(&m_tDisplayUdfParams); + DisplayUdfParamsStore::Update(&m_Params); +#ifndef NDEBUG + Dump(); +#endif DEBUG_EXIT } @@ -190,32 +194,32 @@ void DisplayUdfParams::callbackFunction(const char *pLine) { uint8_t value8; if (Sscan::Uint8(pLine, DisplayUdfParamsConst::INTENSITY, value8) == Sscan::OK) { - m_tDisplayUdfParams.nIntensity = value8; + m_Params.nIntensity = value8; if (value8 != defaults::INTENSITY) { - m_tDisplayUdfParams.nSetList |= displayudfparams::Mask::INTENSITY; + m_Params.nSetList |= displayudfparams::Mask::INTENSITY; } else { - m_tDisplayUdfParams.nSetList &= ~displayudfparams::Mask::INTENSITY; + m_Params.nSetList &= ~displayudfparams::Mask::INTENSITY; } return; } if (Sscan::Uint8(pLine, DisplayUdfParamsConst::SLEEP_TIMEOUT, value8) == Sscan::OK) { - m_tDisplayUdfParams.nSleepTimeout = value8; + m_Params.nSleepTimeout = value8; if (value8 != display::Defaults::SEEP_TIMEOUT) { - m_tDisplayUdfParams.nSetList |= displayudfparams::Mask::SLEEP_TIMEOUT; + m_Params.nSetList |= displayudfparams::Mask::SLEEP_TIMEOUT; } else { - m_tDisplayUdfParams.nSetList &= ~displayudfparams::Mask::SLEEP_TIMEOUT; + m_Params.nSetList &= ~displayudfparams::Mask::SLEEP_TIMEOUT; } return; } if (Sscan::Uint8(pLine, DisplayUdfParamsConst::FLIP_VERTICALLY, value8) == Sscan::OK) { if (value8 != 0) { - m_tDisplayUdfParams.nSetList |= displayudfparams::Mask::FLIP_VERTICALLY; + m_Params.nSetList |= displayudfparams::Mask::FLIP_VERTICALLY; } else { - m_tDisplayUdfParams.nSetList &= ~displayudfparams::Mask::FLIP_VERTICALLY; + m_Params.nSetList &= ~displayudfparams::Mask::FLIP_VERTICALLY; } return; } @@ -223,11 +227,11 @@ void DisplayUdfParams::callbackFunction(const char *pLine) { for (uint32_t i = 0; i < static_cast(Labels::UNKNOWN); i++) { if (Sscan::Uint8(pLine, pArray[i], value8) == Sscan::OK) { if ((value8 > 0) && (value8 <= LABEL_MAX_ROWS)) { - m_tDisplayUdfParams.nLabelIndex[i] = value8; - m_tDisplayUdfParams.nSetList |= (1U << i); + m_Params.nLabelIndex[i] = value8; + m_Params.nSetList |= (1U << i); } else { - m_tDisplayUdfParams.nLabelIndex[i] = 0; - m_tDisplayUdfParams.nSetList &= ~(1U << i); + m_Params.nLabelIndex[i] = 0; + m_Params.nSetList &= ~(1U << i); } return; } @@ -238,21 +242,21 @@ void DisplayUdfParams::Builder(const struct displayudfparams::Params *ptDisplayU assert(pBuffer != nullptr); if (ptDisplayUdfParams != nullptr) { - memcpy(&m_tDisplayUdfParams, ptDisplayUdfParams, sizeof(struct displayudfparams::Params)); + memcpy(&m_Params, ptDisplayUdfParams, sizeof(struct displayudfparams::Params)); } else { assert(m_pDisplayUdfParamsStore != nullptr); - m_pDisplayUdfParamsStore->Copy(&m_tDisplayUdfParams); + DisplayUdfParamsStore::Copy(&m_Params); } PropertiesBuilder builder(DisplayUdfParamsConst::FILE_NAME, pBuffer, nLength); - builder.Add(DisplayUdfParamsConst::INTENSITY, m_tDisplayUdfParams.nIntensity , isMaskSet(displayudfparams::Mask::INTENSITY)); - builder.Add(DisplayUdfParamsConst::SLEEP_TIMEOUT, m_tDisplayUdfParams.nSleepTimeout , isMaskSet(displayudfparams::Mask::SLEEP_TIMEOUT)); + builder.Add(DisplayUdfParamsConst::INTENSITY, m_Params.nIntensity , isMaskSet(displayudfparams::Mask::INTENSITY)); + builder.Add(DisplayUdfParamsConst::SLEEP_TIMEOUT, m_Params.nSleepTimeout , isMaskSet(displayudfparams::Mask::SLEEP_TIMEOUT)); builder.Add(DisplayUdfParamsConst::FLIP_VERTICALLY, isMaskSet(displayudfparams::Mask::FLIP_VERTICALLY) , isMaskSet(displayudfparams::Mask::FLIP_VERTICALLY)); for (uint32_t i = 0; i < static_cast(Labels::UNKNOWN); i++) { if (pArray[i][0] != '\0') { - builder.Add(pArray[i], m_tDisplayUdfParams.nLabelIndex[i] , isMaskSet(1U << i)); + builder.Add(pArray[i], m_Params.nLabelIndex[i] , isMaskSet(1U << i)); } } @@ -263,18 +267,18 @@ void DisplayUdfParams::Set(DisplayUdf *pDisplayUdf) { assert(pDisplayUdf != nullptr); if (isMaskSet(displayudfparams::Mask::INTENSITY)) { - pDisplayUdf->SetContrast(m_tDisplayUdfParams.nIntensity); + pDisplayUdf->SetContrast(m_Params.nIntensity); } if (isMaskSet(displayudfparams::Mask::SLEEP_TIMEOUT)) { - pDisplayUdf->SetSleepTimeout(m_tDisplayUdfParams.nSleepTimeout); + pDisplayUdf->SetSleepTimeout(m_Params.nSleepTimeout); } pDisplayUdf->SetFlipVertically(isMaskSet(displayudfparams::Mask::FLIP_VERTICALLY)); for (uint32_t i = 0; i < static_cast(Labels::UNKNOWN); i++) { if (isMaskSet(1U << i)) { - pDisplayUdf->Set(m_tDisplayUdfParams.nLabelIndex[i], static_cast(i)); + pDisplayUdf->Set(m_Params.nLabelIndex[i], static_cast(i)); } } } @@ -287,15 +291,14 @@ void DisplayUdfParams::staticCallbackFunction(void *p, const char *s) { } void DisplayUdfParams::Dump() { -#ifndef NDEBUG printf("%s::%s \'%s\':\n", __FILE__, __FUNCTION__, DisplayUdfParamsConst::FILE_NAME); if (isMaskSet(displayudfparams::Mask::INTENSITY)) { - printf(" %s=%d\n", DisplayUdfParamsConst::INTENSITY, m_tDisplayUdfParams.nIntensity); + printf(" %s=%d\n", DisplayUdfParamsConst::INTENSITY, m_Params.nIntensity); } if (isMaskSet(displayudfparams::Mask::SLEEP_TIMEOUT)) { - printf(" %s=%d\n", DisplayUdfParamsConst::SLEEP_TIMEOUT, m_tDisplayUdfParams.nSleepTimeout); + printf(" %s=%d\n", DisplayUdfParamsConst::SLEEP_TIMEOUT, m_Params.nSleepTimeout); } if (isMaskSet(displayudfparams::Mask::FLIP_VERTICALLY)) { @@ -304,8 +307,7 @@ void DisplayUdfParams::Dump() { for (uint32_t i = 0; i < static_cast(Labels::UNKNOWN); i++) { if (isMaskSet(1U << i)) { - printf(" %s=%d\n", pArray[i], m_tDisplayUdfParams.nLabelIndex[i]); + printf(" %s=%d\n", pArray[i], m_Params.nLabelIndex[i]); } } -#endif } diff --git a/lib-displayudf/src/e131/displayudfshowe131.cpp b/lib-displayudf/src/e131/displayudfshowe131.cpp index 3dced559..52dac38d 100644 --- a/lib-displayudf/src/e131/displayudfshowe131.cpp +++ b/lib-displayudf/src/e131/displayudfshowe131.cpp @@ -2,7 +2,7 @@ * @file displayudfshowe131.cpp * */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,19 +32,22 @@ #include "debug.h" -void DisplayUdf::Show(E131Bridge *pE131Bridge, uint32_t nDmxPortIndexOffset) { - DEBUG_ENTRY - - m_nPortIndexOffset = nDmxPortIndexOffset; +namespace e131bridge { +namespace configstore { +extern uint32_t DMXPORT_OFFSET; +} // namespace configstore +} // namespace e131bridge - DEBUG_PRINTF("m_nDmxPortIndexOffset=%u", m_nPortIndexOffset); +void DisplayUdf::ShowE131Bridge() { + DEBUG_ENTRY + DEBUG_PRINTF("e131bridge::configstore::DMXPORT_OFFSET=%u", e131bridge::configstore::DMXPORT_OFFSET); - Show(); + auto *pE131Bridge = E131Bridge::Get(); Printf(m_aLabels[static_cast(displayudf::Labels::AP)], "AP: %d", pE131Bridge->GetActiveOutputPorts() + pE131Bridge->GetActiveInputPorts()); for (uint32_t nBridgePortIndex = 0; nBridgePortIndex < std::min(static_cast(4), e131bridge::MAX_PORTS); nBridgePortIndex++) { - const auto nPortIndex = nBridgePortIndex + m_nPortIndexOffset; + const auto nPortIndex = nBridgePortIndex + e131bridge::configstore::DMXPORT_OFFSET; if (nPortIndex >= std::min(static_cast(4), e131bridge::MAX_PORTS)) { break; diff --git a/lib-displayudf/src/network/network.cpp b/lib-displayudf/src/network/network.cpp index 2dd21847..4e4aa13e 100644 --- a/lib-displayudf/src/network/network.cpp +++ b/lib-displayudf/src/network/network.cpp @@ -2,7 +2,7 @@ * @file network.cpp * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,10 +23,12 @@ * THE SOFTWARE. */ -#include "network.h" +#undef NDEBUG + #include "displayudf.h" +#include "net/protocol/dhcp.h" -namespace network { +namespace net { void display_emac_config() { DisplayUdf::Get()->ShowEmacInit(); } @@ -59,7 +61,7 @@ void display_emac_shutdown() { DisplayUdf::Get()->ShowShutdown(); } -void display_dhcp_status(network::dhcp::ClientStatus status) { - DisplayUdf::Get()->ShowDhcpStatus(status); +void display_dhcp_status(net::dhcp::State state) { + DisplayUdf::Get()->ShowDhcpStatus(state); } } // namespace network diff --git a/lib-displayudf/src/network/ntpclient.cpp b/lib-displayudf/src/network/ntpclient.cpp index a6b8c76f..6d9d9149 100644 --- a/lib-displayudf/src/network/ntpclient.cpp +++ b/lib-displayudf/src/network/ntpclient.cpp @@ -2,7 +2,7 @@ * @file ntpclient.cpp * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,19 +23,23 @@ * THE SOFTWARE. */ -#include "ntpclient.h" +#include "net/protocol/ntp.h" #include "display.h" namespace ntpclient { -void display_status(ntpclient::Status status) { - if (status == ntpclient::Status::IDLE) { - Display::Get()->TextStatus("NTP Client", Display7SegmentMessage::INFO_NTP); - return; - } - - if (status == ntpclient::Status::FAILED) { - Display::Get()->TextStatus("Error: NTP", Display7SegmentMessage::ERROR_NTP); - return; +void display_status(const ::ntp::Status status) { + switch (status) { + case ::ntp::Status::STOPPED: + Display::Get()->TextStatus("No NTP Client"); + break; + case ::ntp::Status::IDLE: + Display::Get()->TextStatus("NTP Client"); + break; + case ::ntp::Status::FAILED: + Display::Get()->TextStatus("Error: NTP"); + break; + default: + break; } } } // namespace ntpclient diff --git a/lib-displayudf/src/node/displayudfshownode.cpp b/lib-displayudf/src/node/displayudfshownode.cpp index 0f178e9b..515667a8 100644 --- a/lib-displayudf/src/node/displayudfshownode.cpp +++ b/lib-displayudf/src/node/displayudfshownode.cpp @@ -2,7 +2,7 @@ * @file displayudfshownode.cpp * */ -/* Copyright (C) 2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -35,30 +35,28 @@ static constexpr auto MAX_PORTS = LIGHTSET_PORTS > 4U ? 4U : LIGHTSET_PORTS; -void DisplayUdf::Show(__attribute__((unused)) Node *pNode) { +void DisplayUdf::ShowNode() { DEBUG_ENTRY - Show(); - - ShowNodeName(); - ShowUniverse(); - ShowDestinationIp(); + ShowNodeNameNode(); + ShowUniverseNode(); + ShowDestinationIpNode(); DEBUG_EXIT } -void DisplayUdf::ShowNodeName() { +void DisplayUdf::ShowNodeNameNode() { ClearEndOfLine(); Write(m_aLabels[static_cast(displayudf::Labels::NODE_NAME)], Node::Get()->GetShortName()); } -void DisplayUdf::ShowUniverse() { +void DisplayUdf::ShowUniverseNode() { for (uint32_t nPortIndex = 0; nPortIndex < MAX_PORTS; nPortIndex++) { } } -void DisplayUdf::ShowDestinationIp() { +void DisplayUdf::ShowDestinationIpNode() { for (uint32_t i = 0; i < MAX_PORTS; i++) { Printf(m_aLabels[static_cast(displayudf::Labels::DESTINATION_IP_PORT_A) + i], "%c: " IPSTR, 'A' + i, IP2STR(Node::Get()->GetDestinationIp(i))); } diff --git a/lib-dmx/.cproject b/lib-dmx/.cproject index 6be7f39b..4520a6e3 100644 --- a/lib-dmx/.cproject +++ b/lib-dmx/.cproject @@ -5,7 +5,7 @@ - + @@ -14,15 +14,87 @@ - + - - @@ -113,10 +203,10 @@ - + - + @@ -128,25 +218,28 @@ - + - + - + - + - + - + + + + @@ -155,7 +248,10 @@ - + + + + diff --git a/lib-dmx/Makefile.GD32 b/lib-dmx/Makefile.GD32 index 3463847f..aef96da3 100644 --- a/lib-dmx/Makefile.GD32 +++ b/lib-dmx/Makefile.GD32 @@ -1,7 +1,11 @@ -DEFINES=OUTPUT_DMX_SEND_MULTI -DEFINES+=NDEBUG +DEFINES=NDEBUG EXTRA_INCLUDES=../lib-rdm/include ../lib-properties/include +ifneq ($(MAKE_FLAGS),) +else + DEFINES+=OUTPUT_DMX_SEND +endif + include Rules.mk include ../firmware-template-gd32/lib/Rules.mk diff --git a/lib-dmx/Rules.mk b/lib-dmx/Rules.mk old mode 100755 new mode 100644 index b51fbc3d..908ae815 --- a/lib-dmx/Rules.mk +++ b/lib-dmx/Rules.mk @@ -1,20 +1,3 @@ $(info $$MAKE_FLAGS [${MAKE_FLAGS}]) -ifneq ($(MAKE_FLAGS),) - ifeq ($(findstring NO_EMAC,$(MAKE_FLAGS)), NO_EMAC) - else - EXTRA_SRCDIR+=src/emac - EXTRA_INCLUDES+=../lib-network/include - endif - ifeq ($(findstring ARTNET_HAVE_DMXIN,$(MAKE_FLAGS)), ARTNET_HAVE_DMXIN) - EXTRA_SRCDIR+=src/artnet - endif - ifeq ($(findstring E131_HAVE_DMXIN,$(MAKE_FLAGS)), E131_HAVE_DMXIN) - EXTRA_SRCDIR+=src/e131 - endif -else - EXTRA_SRCDIR+=src/emac - EXTRA_SRCDIR+=src/artnet - EXTRA_SRCDIR+=src/e131 - EXTRA_INCLUDES+=../lib-network/include -endif +EXTRA_INCLUDES+=../lib-lightset/include \ No newline at end of file diff --git a/lib-dmx/include/dmxconfigudp.h b/lib-dmx/include/dmxconfigudp.h index 8de7f409..a0b92831 100755 --- a/lib-dmx/include/dmxconfigudp.h +++ b/lib-dmx/include/dmxconfigudp.h @@ -2,7 +2,7 @@ * @file dmxconfigudp.h * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -83,7 +83,7 @@ class DmxConfigUdp { uint16_t nForeignPort; auto nBytesReceived = Network::Get()->RecvFrom(s_nHandle, const_cast(reinterpret_cast(&s_pUdpBuffer)), &nIPAddressFrom, &nForeignPort); - if (__builtin_expect((!dmxconfigudp::validate(static_cast(nBytesReceived), dmxconfigudp::MIN_SIZE, dmxconfigudp::MAX_SIZE)), 1)) { + if (__builtin_expect((!dmxconfigudp::validate(nBytesReceived, dmxconfigudp::MIN_SIZE, dmxconfigudp::MAX_SIZE)), 1)) { return; } @@ -99,24 +99,24 @@ class DmxConfigUdp { const auto *pCmd = &s_pUdpBuffer[4]; - if (dmxconfigudp::validate(nBytesReceived, static_cast(12), static_cast(13)) && (memcmp("break#", pCmd, 6) == 0)) { - const auto nBreakTime = dmxconfigudp::atoi(reinterpret_cast(&s_pUdpBuffer[10]), nBytesReceived - 10); + if (dmxconfigudp::validate(nBytesReceived, static_cast(12), static_cast(13)) && (memcmp("break#", pCmd, 6) == 0)) { + const auto nBreakTime = dmxconfigudp::atoi(reinterpret_cast(&s_pUdpBuffer[10]), nBytesReceived - 10U); if (nBreakTime >= dmx::transmit::BREAK_TIME_MIN) { Dmx::Get()->SetDmxBreakTime(nBreakTime); } return; } - if (dmxconfigudp::validate(nBytesReceived, static_cast(10), static_cast(16)) && (memcmp("mab#", pCmd, 4) == 0)) { - const auto nMapTime = dmxconfigudp::atoi(reinterpret_cast(&s_pUdpBuffer[8]), nBytesReceived - 8); + if (dmxconfigudp::validate(nBytesReceived, static_cast(10), static_cast(16)) && (memcmp("mab#", pCmd, 4) == 0)) { + const auto nMapTime = dmxconfigudp::atoi(reinterpret_cast(&s_pUdpBuffer[8]), nBytesReceived - 8U); if (dmxconfigudp::validate(nMapTime, dmx::transmit::MAB_TIME_MIN, dmx::transmit::MAB_TIME_MAX)) { Dmx::Get()->SetDmxMabTime(nMapTime); } return; } - if (dmxconfigudp::validate(nBytesReceived, static_cast(13), static_cast(14)) && (memcmp("refresh#", pCmd, 8) == 0)) { - const auto nRefreshRate = dmxconfigudp::atoi(reinterpret_cast(&s_pUdpBuffer[12]), nBytesReceived - 12); + if (dmxconfigudp::validate(nBytesReceived, static_cast(13), static_cast(14)) && (memcmp("refresh#", pCmd, 8) == 0)) { + const auto nRefreshRate = dmxconfigudp::atoi(reinterpret_cast(&s_pUdpBuffer[12]), nBytesReceived - 12U); uint32_t nPeriodTime = 0; if (nRefreshRate != 0) { nPeriodTime = 1000000U / nRefreshRate; @@ -125,8 +125,8 @@ class DmxConfigUdp { return; } - if (dmxconfigudp::validate(nBytesReceived, static_cast(11), static_cast(13)) && (memcmp("slots#", pCmd, 6) == 0)) { - const auto nSlots = dmxconfigudp::atoi(reinterpret_cast(&s_pUdpBuffer[10]), nBytesReceived - 10); + if (dmxconfigudp::validate(nBytesReceived, static_cast(11), static_cast(13)) && (memcmp("slots#", pCmd, 6) == 0)) { + const auto nSlots = dmxconfigudp::atoi(reinterpret_cast(&s_pUdpBuffer[10]), nBytesReceived - 10U); if (dmxconfigudp::validate(nSlots, dmx::min::CHANNELS, dmx::max::CHANNELS)) { Dmx::Get()->SetDmxSlots(static_cast(nSlots)); } @@ -135,8 +135,8 @@ class DmxConfigUdp { } private: - static int32_t s_nHandle; - static char *s_pUdpBuffer; + int32_t s_nHandle { -1 }; + char *s_pUdpBuffer { nullptr }; }; #endif /* DMXCONFIGUDP_H_ */ diff --git a/lib-dmx/include/dmxparams.h b/lib-dmx/include/dmxparams.h index ec403189..c5a3f434 100644 --- a/lib-dmx/include/dmxparams.h +++ b/lib-dmx/include/dmxparams.h @@ -29,8 +29,10 @@ #include #include "dmx.h" +#include "configstore.h" -struct TDmxParams { +namespace dmxsendparams { +struct Params { uint32_t nSetList; uint16_t nBreakTime; uint16_t nMabTime; @@ -38,59 +40,59 @@ struct TDmxParams { uint8_t nSlotsCount; }__attribute__((packed)); -static_assert(sizeof(struct TDmxParams) <= 32, "struct TDmxParams is too large"); +static_assert(sizeof(struct Params) <= 32, "struct Params is too large"); -struct DmxParamsMask { - static constexpr auto BREAK_TIME = (1U << 0); - static constexpr auto MAB_TIME = (1U << 1); - static constexpr auto REFRESH_RATE = (1U << 2); - static constexpr auto SLOTS_COUNT = (1U << 3); +struct Mask { + static constexpr uint32_t BREAK_TIME = (1U << 0); + static constexpr uint32_t MAB_TIME = (1U << 1); + static constexpr uint32_t REFRESH_RATE = (1U << 2); + static constexpr uint32_t SLOTS_COUNT = (1U << 3); }; -namespace dmxparams { static constexpr uint8_t rounddown_slots(uint16_t n) { return static_cast((n / 2U) - 1); } static constexpr uint16_t roundup_slots(uint8_t n) { return static_cast((n + 1U) * 2U); } -} // namespace dmxparams +} // namespace dmxsendparams] -class DmxParamsStore { +class StoreDmxSend { public: - virtual ~DmxParamsStore() {} + static void Update(const struct dmxsendparams::Params *pParams) { + ConfigStore::Get()->Update(configstore::Store::DMXSEND, pParams, sizeof(struct dmxsendparams::Params)); + } - virtual void Update(const struct TDmxParams *pDmxParams)=0; - virtual void Copy(struct TDmxParams *pDmxParams)=0; + static void Copy(struct dmxsendparams::Params *pParams) { + ConfigStore::Get()->Copy(configstore::Store::DMXSEND, pParams, sizeof(struct dmxsendparams::Params)); + } }; class DmxParams { public: - DmxParams(DmxParamsStore *pDMXParamsStore); + DmxParams(); - bool Load(); + void Load(); void Load(const char *pBuffer, uint32_t nLength); - void Builder(const struct TDmxParams *pTDmxParams, char *pBuffer, uint32_t nLength, uint32_t& nSize); + void Builder(const struct dmxsendparams::Params *pTDmxParams, char *pBuffer, uint32_t nLength, uint32_t& nSize); void Save(char *pBuffer, uint32_t nLength, uint32_t& nSize) { Builder(nullptr, pBuffer, nLength, nSize); } void Set(Dmx *); - void Dump(); - static void staticCallbackFunction(void *p, const char *s); private: + void Dump(); void callbackFunction(const char *s); bool isMaskSet(uint32_t nMask) const { - return (m_tDmxParams.nSetList & nMask) == nMask; + return (m_Params.nSetList & nMask) == nMask; } private: - DmxParamsStore *m_pDmxParamsStore; - struct TDmxParams m_tDmxParams; + dmxsendparams::Params m_Params; }; #endif /* DMXPARAMS_H_ */ diff --git a/lib-dmx/include/dmxparamsconst.h b/lib-dmx/include/dmxparamsconst.h index 0ff53d36..e96041a7 100644 --- a/lib-dmx/include/dmxparamsconst.h +++ b/lib-dmx/include/dmxparamsconst.h @@ -3,7 +3,7 @@ * * */ -/* Copyright (C) 2019-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-dmxreceiver/include/dmxreceiver.h b/lib-dmx/include/dmxreceiver.h old mode 100644 new mode 100755 similarity index 72% rename from lib-dmxreceiver/include/dmxreceiver.h rename to lib-dmx/include/dmxreceiver.h index e0d7fa01..63543f2e --- a/lib-dmxreceiver/include/dmxreceiver.h +++ b/lib-dmx/include/dmxreceiver.h @@ -2,7 +2,7 @@ * @file dmxreceiver.h * */ -/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -39,12 +39,12 @@ class DMXReceiver: Dmx { public: DMXReceiver(LightSet *pLightSet) { - s_pLightSet = pLightSet; + m_pLightSet = pLightSet; } ~DMXReceiver() { DMXReceiver::Stop(); - s_IsActive = false; + m_IsActive = false; } void Start() { @@ -53,28 +53,28 @@ class DMXReceiver: Dmx { void Stop() { Dmx::SetPortDirection(0, dmx::PortDirection::INP, false); - s_pLightSet->Stop(0); + m_pLightSet->Stop(0); } void SetLightSet(LightSet *pLightSet) { - if (pLightSet != s_pLightSet) { - s_pLightSet->Stop(0); - s_pLightSet = pLightSet; - s_IsActive = false; + if (pLightSet != m_pLightSet) { + m_pLightSet->Stop(0); + m_pLightSet = pLightSet; + m_IsActive = false; } } - const uint8_t* Run(int16_t &nLength) { - if (__builtin_expect((s_bDisableOutput), 0)) { + const uint8_t *Run(int16_t &nLength) { + if (__builtin_expect((m_bDisableOutput), 0)) { nLength = 0; return nullptr; } if (Dmx::GetDmxUpdatesPerSecond(0) == 0) { - if (s_IsActive) { - s_pLightSet->Stop(0); - s_IsActive = false; + if (m_IsActive) { + m_pLightSet->Stop(0); + m_IsActive = false; Hardware::Get()->SetMode(hardware::ledblink::Mode::NORMAL); } @@ -83,21 +83,21 @@ class DMXReceiver: Dmx { } else { const auto *pDmx = Dmx::GetDmxAvailable(0); - if (pDmx != nullptr) { - const auto *pDmxStatistics = reinterpret_cast(pDmx); + if (__builtin_expect((pDmx != nullptr), 0)) { + const auto *pDmxStatistics = reinterpret_cast(pDmx); nLength = static_cast(pDmxStatistics->Statistics.nSlotsInPacket); ++pDmx; - s_pLightSet->SetData(0, pDmx, static_cast(nLength)); + m_pLightSet->SetData(0, pDmx, static_cast(nLength)); - if (!s_IsActive) { - s_pLightSet->Start(0); - s_IsActive = true; + if (!m_IsActive) { + m_pLightSet->Start(0); + m_IsActive = true; Hardware::Get()->SetMode(hardware::ledblink::Mode::DATA); } - return const_cast(pDmx); + return const_cast(pDmx); } } @@ -106,25 +106,25 @@ class DMXReceiver: Dmx { } void SetDisableOutput(const bool bDisable = true) { - s_bDisableOutput = bDisable; + m_bDisableOutput = bDisable; } uint32_t GetUpdatesPerSecond(const uint32_t nPortIndex) { return Dmx::GetDmxUpdatesPerSecond(nPortIndex); } - const uint8_t* GetDmxCurrentData(const uint32_t nPortIndex) { + const uint8_t *GetDmxCurrentData(const uint32_t nPortIndex) { return Dmx::GetDmxCurrentData(nPortIndex); } void Print() { - printf(" Output %s\n", s_bDisableOutput ? "disabled" : "enabled"); + printf(" Output %s\n", m_bDisableOutput ? "disabled" : "enabled"); } private: - static LightSet *s_pLightSet; - static bool s_IsActive; - static bool s_bDisableOutput; + LightSet *m_pLightSet { nullptr }; + bool m_IsActive { false }; + bool m_bDisableOutput { false }; }; #endif /* DMXRECEIVER_H */ diff --git a/lib-dmx/include/dmxsend.h b/lib-dmx/include/dmxsend.h new file mode 100755 index 00000000..ed44a85d --- /dev/null +++ b/lib-dmx/include/dmxsend.h @@ -0,0 +1,156 @@ +/** + * @file dmxsend.h + * + */ +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef DMXSEND_H_ +#define DMXSEND_H_ + +#include +#include +#include + +#include "lightset.h" +#include "lightsetdata.h" + +#include "dmx.h" +#include "panel_led.h" +#include "hardware.h" + +#include "debug.h" + +class DmxSend final: public LightSet { +public: + void Start(const uint32_t nPortIndex) override { + DEBUG_ENTRY + DEBUG_PRINTF("nPortIndex=%d", nPortIndex); + + assert(nPortIndex < CHAR_BIT); + + if (is_started(m_nStarted, nPortIndex)) { + DEBUG_EXIT + return; + } + + m_nStarted = static_cast(m_nStarted | (1U << nPortIndex)); + + Dmx::Get()->SetPortDirection(nPortIndex, dmx::PortDirection::OUTP, true); + + if (Dmx::Get()->GetOutputStyle(nPortIndex) == dmx::OutputStyle::CONTINOUS) { + hal::panel_led_on(hal::panelled::PORT_A_TX << nPortIndex); + } + + DEBUG_EXIT + } + + void Stop(const uint32_t nPortIndex) override { + DEBUG_ENTRY + DEBUG_PRINTF("nPortIndex=%d -> %u", nPortIndex, is_started(m_nStarted, static_cast(nPortIndex))); + + assert(nPortIndex < CHAR_BIT); + + if (!is_started(m_nStarted, nPortIndex)) { + DEBUG_EXIT + return; + } + + m_nStarted = static_cast(m_nStarted & ~(1U << nPortIndex)); + + Dmx::Get()->SetPortDirection(nPortIndex, dmx::PortDirection::OUTP, false); + + hal::panel_led_off(hal::panelled::PORT_A_TX << nPortIndex); + + DEBUG_EXIT + } + + void SetData(const uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength, const bool doUpdate) override { + assert(nPortIndex < CHAR_BIT); + assert(pData != nullptr); + assert(nLength != 0); + + if (doUpdate) { + Dmx::Get()->SetSendDataWithoutSC(nPortIndex, pData, nLength); + Dmx::Get()->StartOutput(nPortIndex); + hal::panel_led_on(hal::panelled::PORT_A_TX << nPortIndex); + } + } + + void Sync(uint32_t const nPortIndex) override { + assert(lightset::Data::GetLength(nPortIndex) != 0); + Dmx::Get()->SetSendDataWithoutSC(nPortIndex, lightset::Data::Backup(nPortIndex), lightset::Data::GetLength(nPortIndex)); + } + + void Sync() override { + Dmx::Get()->Sync(); + + for (uint32_t nPortIndex = 0; nPortIndex < dmx::config::max::PORTS; nPortIndex++) { + if (lightset::Data::GetLength(nPortIndex) != 0) { + lightset::Data::ClearLength(nPortIndex); + hal::panel_led_on(hal::panelled::PORT_A_TX << nPortIndex); + if (!is_started(m_nStarted, nPortIndex)) { + Start(nPortIndex); + } + } + } + } + +#if defined (OUTPUT_HAVE_STYLESWITCH) + void SetOutputStyle(const uint32_t nPortIndex, const lightset::OutputStyle outputStyle) override { + Dmx::Get()->SetOutputStyle(nPortIndex, outputStyle == lightset::OutputStyle::CONSTANT ? dmx::OutputStyle::CONTINOUS : dmx::OutputStyle::DELTA); + } + + lightset::OutputStyle GetOutputStyle(const uint32_t nPortIndex) const override { + return Dmx::Get()->GetOutputStyle(nPortIndex) == dmx::OutputStyle::CONTINOUS ? lightset::OutputStyle::CONSTANT : lightset::OutputStyle::DELTA; + } +#endif + + uint32_t GetRefreshRate() override { + return 1000000U / Dmx::Get()->GetDmxPeriodTime(); + } + + void Blackout([[maybe_unused]] bool bBlackout) override { + Dmx::Get()->Blackout(); + } + + void FullOn() override { + Dmx::Get()->FullOn(); + } + + void Print() override { + puts("DMX Send"); + printf(" Break time : %u\n", static_cast(Dmx::Get()->GetDmxBreakTime())); + printf(" MAB time : %u\n", static_cast(Dmx::Get()->GetDmxMabTime())); + printf(" Refresh rate : %u\n", static_cast(1000000U / Dmx::Get()->GetDmxPeriodTime())); + printf(" Slots : %u\n", Dmx::Get()->GetDmxSlots()); + } + +private: + static constexpr bool is_started(const uint8_t v, const uint32_t p) { + return (v & (1U << p)) == (1U << p); + } + +private: + uint8_t m_nStarted { 0 }; +}; + +#endif /* DMXSEND_H_ */ diff --git a/lib-dmx/include/dmxstatistics.h b/lib-dmx/include/dmxstatistics.h new file mode 100755 index 00000000..7bc1615b --- /dev/null +++ b/lib-dmx/include/dmxstatistics.h @@ -0,0 +1,52 @@ +/** + * @file dmxstatistics.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef DMXSTATISTICS_H_ +#define DMXSTATISTICS_H_ + +#include + +namespace dmx { +struct TotalStatistics { + struct { + uint32_t Sent; + uint32_t Received; + } Dmx; + + struct { + struct { + uint32_t Good; + uint32_t Bad; + uint32_t DiscoveryResponse; + } Received; + struct { + uint32_t Class; + uint32_t DiscoveryResponse; + } Sent; + } Rdm; +}; +} // namespace dmx + +#endif /* DMXSTATISTICS_H_ */ diff --git a/lib-dmx/include/gd32/board_bw_opidmx4.h b/lib-dmx/include/gd32/board_bw_opidmx4.h index 22946a62..1c084248 100644 --- a/lib-dmx/include/gd32/board_bw_opidmx4.h +++ b/lib-dmx/include/gd32/board_bw_opidmx4.h @@ -26,15 +26,16 @@ #ifndef GD32_BOARD_BW_OPIDMX4_H_ #define GD32_BOARD_BW_OPIDMX4_H_ +#include + #include "gd32_board.h" +#define DMX_MAX_PORTS 4 + namespace max { -static constexpr auto OUT = 4U; -static constexpr auto IN = 4U; + static const uint32_t PORTS = DMX_MAX_PORTS; } // namespace max -#define DMX_MAX_PORTS 4 - #define DMX_USE_USART0 #define DMX_USE_USART2 #define DMX_USE_UART4 diff --git a/lib-dmx/include/gd32/board_dmx3.h b/lib-dmx/include/gd32/board_dmx3.h index e2c0a716..e781db03 100644 --- a/lib-dmx/include/gd32/board_dmx3.h +++ b/lib-dmx/include/gd32/board_dmx3.h @@ -28,13 +28,12 @@ #include "gd32_board.h" +#define DMX_MAX_PORTS 3 + namespace max { -static constexpr auto OUT = 3U; -static constexpr auto IN = 3U; + static const uint32_t PORTS = DMX_MAX_PORTS; } // namespace max -#define DMX_MAX_PORTS 3 - #define DMX_USE_USART2 #define DMX_USE_UART4 #define DMX_USE_USART5 diff --git a/lib-dmx/include/gd32/board_dmx4.h b/lib-dmx/include/gd32/board_dmx4.h index 64c2a6f8..42d98a2d 100644 --- a/lib-dmx/include/gd32/board_dmx4.h +++ b/lib-dmx/include/gd32/board_dmx4.h @@ -28,13 +28,12 @@ #include "gd32_board.h" +#define DMX_MAX_PORTS 4 + namespace max { -static constexpr auto OUT = 4U; -static constexpr auto IN = 4U; + static const uint32_t PORTS = DMX_MAX_PORTS; } // namespace max -#define DMX_MAX_PORTS 4 - #define DMX_USE_USART0 #define DMX_USE_USART2 #define DMX_USE_UART4 diff --git a/lib-dmx/include/gd32/board_gd32f207rg.h b/lib-dmx/include/gd32/board_gd32f207rg.h index 19a28957..82aa812f 100644 --- a/lib-dmx/include/gd32/board_gd32f207rg.h +++ b/lib-dmx/include/gd32/board_gd32f207rg.h @@ -28,13 +28,12 @@ #include "gd32_board.h" -namespace max { -static constexpr auto OUT = 2U; -static constexpr auto IN = 2U; -} - #define DMX_MAX_PORTS 2 +namespace max { + static const uint32_t PORTS = DMX_MAX_PORTS; +} // namespace max + #define DMX_USE_USART2 #define DMX_USE_USART5 diff --git a/lib-dmx/include/gd32/dmx.h b/lib-dmx/include/gd32/dmx.h index cfca1402..0d3c60a2 100644 --- a/lib-dmx/include/gd32/dmx.h +++ b/lib-dmx/include/gd32/dmx.h @@ -2,7 +2,7 @@ * @file dmx.h * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -30,10 +30,10 @@ #include "dmxconst.h" #include "dmx_config.h" +#include "dmxstatistics.h" struct Statistics { uint32_t nSlotsInPacket; - uint32_t nSlotToSlot; }; struct Data { @@ -50,40 +50,27 @@ class Dmx { return m_dmxPortDirection[nPortIndex]; } - void ClearData(uint32_t nPortIndex = 0); + void ClearData(const uint32_t nPortIndex); + + volatile dmx::TotalStatistics& GetTotalStatistics(const uint32_t nPortIndex); // RDM Send - void RdmSendRaw(uint32_t nPortIndex, const uint8_t *pRdmData, uint32_t nLength); + void RdmSendRaw(const uint32_t nPortIndex, const uint8_t *pRdmData, uint32_t nLength); + void RdmSendDiscoveryRespondMessage(const uint32_t nPortIndex, const uint8_t *pRdmData, uint32_t nLength); // RDM Receive - const uint8_t *RdmReceive(uint32_t nPortIndex); - const uint8_t *RdmReceiveTimeOut(uint32_t nPortIndex, uint16_t nTimeOut); + const uint8_t *RdmReceive(const uint32_t nPortIndex); + const uint8_t *RdmReceiveTimeOut(const uint32_t nPortIndex, uint16_t nTimeOut); // DMX Send - void SetSendData(uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength); - void SetSendDataWithoutSC(uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength); - - void StartOutput(const uint32_t nPortIndex); - void SetOutput(const bool doForce); - - void SetOutputStyle(const uint32_t nPortIndex, const dmx::OutputStyle outputStyle); - dmx::OutputStyle GetOutputStyle(const uint32_t nPortIndex) const; - - void Blackout(); - void FullOn(); - void SetDmxBreakTime(uint32_t nBreakTime); - uint32_t GetDmxBreakTime() const { - return m_nDmxTransmitBreakTime; - } + uint32_t GetDmxBreakTime() const; void SetDmxMabTime(uint32_t nMabTime); - uint32_t GetDmxMabTime() const { - return m_nDmxTransmitMabTime; - } + uint32_t GetDmxMabTime() const; void SetDmxPeriodTime(uint32_t nPeriodTime); uint32_t GetDmxPeriodTime() const { @@ -95,6 +82,18 @@ class Dmx { return m_nDmxTransmitSlots; } + void SetSendData(const uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength); + void SetSendDataWithoutSC(const uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength); + + void StartOutput(const uint32_t nPortIndex); + void Sync(); + + void SetOutputStyle(const uint32_t nPortIndex, const dmx::OutputStyle outputStyle); + dmx::OutputStyle GetOutputStyle(const uint32_t nPortIndex) const; + + void Blackout(); + void FullOn(); + // DMX Receive const uint8_t *GetDmxAvailable(const uint32_t nPortIndex); @@ -102,25 +101,23 @@ class Dmx { const uint8_t *GetDmxCurrentData(const uint32_t nPortIndex); uint32_t GetDmxUpdatesPerSecond(const uint32_t nPortIndex); - uint32_t GetDmxReceivedCount(const uint32_t nPortIndex); static Dmx* Get() { return s_pThis; } private: - void StartData(const uint32_t nUart, const uint32_t nPortIndex); - void StopData(const uint32_t nUart, const uint32_t nPortIndex); + void StartData(const uint32_t nPortIndex); + void StopData(const uint32_t nPortIndex); void StartDmxOutput(const uint32_t nPortIndex); private: - uint32_t m_nDmxTransmitBreakTime { dmx::transmit::BREAK_TIME_MIN }; - uint32_t m_nDmxTransmitMabTime { dmx::transmit::MAB_TIME_MIN }; uint32_t m_nDmxTransmitPeriod { dmx::transmit::PERIOD_DEFAULT }; uint32_t m_nDmxTransmitPeriodRequested { dmx::transmit::PERIOD_DEFAULT }; - uint32_t m_nDmxTransmissionLength[dmx::config::max::OUT]; - uint16_t m_nDmxTransmitSlots { dmx::max::CHANNELS }; - dmx::PortDirection m_dmxPortDirection[dmx::config::max::OUT]; + uint32_t m_nDmxTransmissionLength[dmx::config::max::PORTS]; + uint32_t m_nDmxTransmitSlots { dmx::max::CHANNELS }; + dmx::PortDirection m_dmxPortDirection[dmx::config::max::PORTS]; + bool m_bHasContinuosOutput { false }; static Dmx *s_pThis; }; diff --git a/lib-dmx/include/gd32/dmx_config.h b/lib-dmx/include/gd32/dmx_config.h index a5350a96..440a29ca 100644 --- a/lib-dmx/include/gd32/dmx_config.h +++ b/lib-dmx/include/gd32/dmx_config.h @@ -2,7 +2,7 @@ * @file dmx_config.h * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -48,8 +48,12 @@ namespace config { # include "board_gd32f450ve.h" #elif defined (BOARD_GD32F450VI) # include "board_gd32f450vi.h" +#elif defined (BOARD_GD32F470Z_EVAL) +# include "board_gd32f470z_eval.h" #elif defined (BOARD_GD32F207C_EVAL) # include "board_gd32f207c_eval.h" +#elif defined (BOARD_GD32H759I_EVAL) +# include "board_gd32h759i_eval.h" #elif defined (BOARD_BW_OPIDMX4) # include "board_bw_opidmx4.h" #elif defined (BOARD_DMX3) @@ -64,19 +68,16 @@ namespace config { namespace dmx { namespace buffer { -static constexpr auto SIZE = 514; // multiple of uint16_t +static constexpr auto SIZE = 516; // multiple of uint32_t } // namespace buffer } // namespace dmx -/** - * PORTs check - */ -static_assert(DMX_MAX_PORTS <= dmx::config::max::IN, "IN: DMX_MAX_PORTS"); -static_assert(DMX_MAX_PORTS <= dmx::config::max::OUT, "OUT: DMX_MAX_PORTS"); - #if defined(GD32F10X_HD) || defined (GD32F10X_CL) static_assert(DMX_MAX_PORTS <= 4, "Too many ports defined"); #endif +#if defined (GD32F20X_CL) + static_assert(DMX_MAX_PORTS <= 6, "Too many ports defined"); +#endif /** * DMA channel check diff --git a/lib-dmx/src/artnet/dmxinput.cpp b/lib-dmx/src/artnet/dmxinput.cpp deleted file mode 100644 index 6e9a1495..00000000 --- a/lib-dmx/src/artnet/dmxinput.cpp +++ /dev/null @@ -1,95 +0,0 @@ -/** - * @file dmxinput.cpp - * - */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#include - -#include "dmx.h" - -#include "debug.h" - -namespace artnet { -static uint8_t s_nStarted; - -static constexpr bool is_started(const uint8_t v, const uint32_t p) { - return (v & (1U << p)) == (1U << p); -} - -void dmx_start(const uint32_t nPortIndex) { - DEBUG_ENTRY - - assert(nPortIndex < CHAR_BIT); - - DEBUG_PRINTF("nPortIndex=%d", nPortIndex); - - if (is_started(s_nStarted, nPortIndex)) { - DEBUG_EXIT - return; - } - - s_nStarted = static_cast(s_nStarted | (1U << nPortIndex)); - - Dmx::Get()->SetPortDirection(nPortIndex, dmx::PortDirection::INP, true); - - DEBUG_EXIT -} - -void dmx_stop(const uint32_t nPortIndex) { - DEBUG_ENTRY - - assert(nPortIndex < CHAR_BIT); - - DEBUG_PRINTF("nPortIndex=%d -> %u", nPortIndex, is_started(s_nStarted, nPortIndex)); - - if (!is_started(s_nStarted, nPortIndex)) { - DEBUG_EXIT - return; - } - - s_nStarted = static_cast(s_nStarted & ~(1U << nPortIndex)); - - Dmx::Get()->SetPortDirection(nPortIndex, dmx::PortDirection::INP, false); - - DEBUG_EXIT -} - -const uint8_t *dmx_handler(const uint32_t nPortIndex, uint32_t& nLength, uint32_t& nUpdatesPerSecond) { - assert(nPortIndex < CHAR_BIT); - - const auto *pDmx = Dmx::Get()->GetDmxAvailable(nPortIndex); - - nUpdatesPerSecond = Dmx::Get()->GetDmxUpdatesPerSecond(nPortIndex); - - if (pDmx != nullptr) { - const auto *pDmxData = reinterpret_cast(pDmx); - nLength = pDmxData->Statistics.nSlotsInPacket; - return (pDmx + 1); - } - - nLength = 0; - return nullptr; -} -} // namespace artnet diff --git a/lib-dmx/src/dmxparams.cpp b/lib-dmx/src/dmxparams.cpp index 755147e1..36856ff9 100644 --- a/lib-dmx/src/dmxparams.cpp +++ b/lib-dmx/src/dmxparams.cpp @@ -2,7 +2,7 @@ * @file dmxparams.cpp * */ -/* Copyright (C) 2017-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -46,36 +46,34 @@ #include "debug.h" -DmxParams::DmxParams(DmxParamsStore *pDMXParamsStore) : m_pDmxParamsStore(pDMXParamsStore) { - m_tDmxParams.nSetList = 0; - m_tDmxParams.nBreakTime = dmx::transmit::BREAK_TIME_TYPICAL; - m_tDmxParams.nMabTime = dmx::transmit::MAB_TIME_MIN; - m_tDmxParams.nRefreshRate = dmx::transmit::REFRESH_RATE_DEFAULT; - m_tDmxParams.nSlotsCount = dmxparams::rounddown_slots(dmx::max::CHANNELS); +DmxParams::DmxParams() { + m_Params.nSetList = 0; + m_Params.nBreakTime = dmx::transmit::BREAK_TIME_TYPICAL; + m_Params.nMabTime = dmx::transmit::MAB_TIME_MIN; + m_Params.nRefreshRate = dmx::transmit::REFRESH_RATE_DEFAULT; + m_Params.nSlotsCount = dmxsendparams::rounddown_slots(dmx::max::CHANNELS); - DEBUG_PRINTF("m_tDmxParams.nSlotsCount=%d", m_tDmxParams.nSlotsCount); + DEBUG_PRINTF("m_Params.nSlotsCount=%d", m_Params.nSlotsCount); } -bool DmxParams::Load() { - m_tDmxParams.nSetList = 0; +void DmxParams::Load() { + DEBUG_ENTRY + + m_Params.nSetList = 0; #if !defined(DISABLE_FS) ReadConfigFile configfile(DmxParams::staticCallbackFunction, this); if (configfile.Read(DmxParamsConst::FILE_NAME)) { - // There is a configuration file - if (m_pDmxParamsStore != nullptr) { - m_pDmxParamsStore->Update(&m_tDmxParams); - } + StoreDmxSend::Update(&m_Params); } else #endif - if (m_pDmxParamsStore != nullptr) { - m_pDmxParamsStore->Copy(&m_tDmxParams); - } else { - return false; - } + StoreDmxSend::Copy(&m_Params); - return true; +#ifndef NDEBUG + Dump(); +#endif + DEBUG_EXIT } void DmxParams::Load(const char* pBuffer, uint32_t nLength) { @@ -84,15 +82,17 @@ void DmxParams::Load(const char* pBuffer, uint32_t nLength) { assert(pBuffer != nullptr); assert(nLength != 0); - m_tDmxParams.nSetList = 0; + m_Params.nSetList = 0; ReadConfigFile config(DmxParams::staticCallbackFunction, this); config.Read(pBuffer, nLength); - assert(m_pDmxParamsStore != nullptr); - m_pDmxParamsStore->Update(&m_tDmxParams); + StoreDmxSend::Update(&m_Params); +#ifndef NDEBUG + Dump(); +#endif DEBUG_EXIT } @@ -103,22 +103,22 @@ void DmxParams::callbackFunction(const char *pLine) { if (Sscan::Uint16(pLine, DmxParamsConst::BREAK_TIME, nValue16) == Sscan::OK) { if ((nValue16 >= dmx::transmit::BREAK_TIME_MIN) && (nValue16 != dmx::transmit::BREAK_TIME_TYPICAL)) { - m_tDmxParams.nBreakTime = nValue16; - m_tDmxParams.nSetList |= DmxParamsMask::BREAK_TIME; + m_Params.nBreakTime = nValue16; + m_Params.nSetList |= dmxsendparams::Mask::BREAK_TIME; } else { - m_tDmxParams.nBreakTime = dmx::transmit::BREAK_TIME_TYPICAL; - m_tDmxParams.nSetList &= ~DmxParamsMask::BREAK_TIME; + m_Params.nBreakTime = dmx::transmit::BREAK_TIME_TYPICAL; + m_Params.nSetList &= ~dmxsendparams::Mask::BREAK_TIME; } return; } if (Sscan::Uint16(pLine, DmxParamsConst::MAB_TIME, nValue16) == Sscan::OK) { if (nValue16 > dmx::transmit::MAB_TIME_MIN) { // && (nValue32 <= dmx::transmit::MAB_TIME_MAX)) { - m_tDmxParams.nMabTime = nValue16; - m_tDmxParams.nSetList |= DmxParamsMask::MAB_TIME; + m_Params.nMabTime = nValue16; + m_Params.nSetList |= dmxsendparams::Mask::MAB_TIME; } else { - m_tDmxParams.nMabTime = dmx::transmit::MAB_TIME_MIN; - m_tDmxParams.nSetList &= ~DmxParamsMask::MAB_TIME; + m_Params.nMabTime = dmx::transmit::MAB_TIME_MIN; + m_Params.nSetList &= ~dmxsendparams::Mask::MAB_TIME; } return; } @@ -127,45 +127,44 @@ void DmxParams::callbackFunction(const char *pLine) { if (Sscan::Uint8(pLine, DmxParamsConst::REFRESH_RATE, nValue8) == Sscan::OK) { if (nValue8 != dmx::transmit::REFRESH_RATE_DEFAULT) { - m_tDmxParams.nRefreshRate = nValue8; - m_tDmxParams.nSetList |= DmxParamsMask::REFRESH_RATE; + m_Params.nRefreshRate = nValue8; + m_Params.nSetList |= dmxsendparams::Mask::REFRESH_RATE; } else { - m_tDmxParams.nRefreshRate = dmx::transmit::REFRESH_RATE_DEFAULT; - m_tDmxParams.nSetList &= ~DmxParamsMask::REFRESH_RATE; + m_Params.nRefreshRate = dmx::transmit::REFRESH_RATE_DEFAULT; + m_Params.nSetList &= ~dmxsendparams::Mask::REFRESH_RATE; } return; } if (Sscan::Uint16(pLine, DmxParamsConst::SLOTS_COUNT, nValue16) == Sscan::OK) { if ((nValue16 >= 2) && (nValue16 < dmx::max::CHANNELS)) { - m_tDmxParams.nSlotsCount = dmxparams::rounddown_slots(nValue16); - m_tDmxParams.nSetList |= DmxParamsMask::SLOTS_COUNT; + m_Params.nSlotsCount = dmxsendparams::rounddown_slots(nValue16); + m_Params.nSetList |= dmxsendparams::Mask::SLOTS_COUNT; } else { - m_tDmxParams.nSlotsCount = dmxparams::rounddown_slots(dmx::max::CHANNELS); - m_tDmxParams.nSetList &= ~DmxParamsMask::SLOTS_COUNT; + m_Params.nSlotsCount = dmxsendparams::rounddown_slots(dmx::max::CHANNELS); + m_Params.nSetList &= ~dmxsendparams::Mask::SLOTS_COUNT; } return; } } -void DmxParams::Builder(const struct TDmxParams *ptDMXParams, char *pBuffer, uint32_t nLength, uint32_t& nSize) { +void DmxParams::Builder(const struct dmxsendparams::Params *ptDMXParams, char *pBuffer, uint32_t nLength, uint32_t& nSize) { DEBUG_ENTRY assert(pBuffer != nullptr); if (ptDMXParams != nullptr) { - memcpy(&m_tDmxParams, ptDMXParams, sizeof(struct TDmxParams)); + memcpy(&m_Params, ptDMXParams, sizeof(struct dmxsendparams::Params)); } else { - assert(m_pDmxParamsStore != nullptr); - m_pDmxParamsStore->Copy(&m_tDmxParams); + StoreDmxSend::Copy(&m_Params); } PropertiesBuilder builder(DmxParamsConst::FILE_NAME, pBuffer, nLength); - builder.Add(DmxParamsConst::BREAK_TIME, m_tDmxParams.nBreakTime, isMaskSet(DmxParamsMask::BREAK_TIME)); - builder.Add(DmxParamsConst::MAB_TIME, m_tDmxParams.nMabTime, isMaskSet(DmxParamsMask::MAB_TIME)); - builder.Add(DmxParamsConst::REFRESH_RATE, m_tDmxParams.nRefreshRate, isMaskSet(DmxParamsMask::REFRESH_RATE)); - builder.Add(DmxParamsConst::SLOTS_COUNT, dmxparams::roundup_slots(m_tDmxParams.nSlotsCount), isMaskSet(DmxParamsMask::SLOTS_COUNT)); + builder.Add(DmxParamsConst::BREAK_TIME, m_Params.nBreakTime, isMaskSet(dmxsendparams::Mask::BREAK_TIME)); + builder.Add(DmxParamsConst::MAB_TIME, m_Params.nMabTime, isMaskSet(dmxsendparams::Mask::MAB_TIME)); + builder.Add(DmxParamsConst::REFRESH_RATE, m_Params.nRefreshRate, isMaskSet(dmxsendparams::Mask::REFRESH_RATE)); + builder.Add(DmxParamsConst::SLOTS_COUNT, dmxsendparams::roundup_slots(m_Params.nSlotsCount), isMaskSet(dmxsendparams::Mask::SLOTS_COUNT)); nSize = builder.GetSize(); @@ -176,52 +175,50 @@ void DmxParams::Builder(const struct TDmxParams *ptDMXParams, char *pBuffer, uin void DmxParams::Set(Dmx *p) { assert(p != nullptr); - if (isMaskSet(DmxParamsMask::BREAK_TIME)) { - p->SetDmxBreakTime(m_tDmxParams.nBreakTime); + if (isMaskSet(dmxsendparams::Mask::BREAK_TIME)) { + p->SetDmxBreakTime(m_Params.nBreakTime); } - if (isMaskSet(DmxParamsMask::MAB_TIME)) { - p->SetDmxMabTime(m_tDmxParams.nMabTime); + if (isMaskSet(dmxsendparams::Mask::MAB_TIME)) { + p->SetDmxMabTime(m_Params.nMabTime); } - if (isMaskSet(DmxParamsMask::REFRESH_RATE)) { + if (isMaskSet(dmxsendparams::Mask::REFRESH_RATE)) { uint32_t period = 0; - if (m_tDmxParams.nRefreshRate != 0) { - period = 1000000U / m_tDmxParams.nRefreshRate; + if (m_Params.nRefreshRate != 0) { + period = 1000000U / m_Params.nRefreshRate; } p->SetDmxPeriodTime(period); } - if (isMaskSet(DmxParamsMask::SLOTS_COUNT)) { - p->SetDmxSlots(dmxparams::roundup_slots(m_tDmxParams.nSlotsCount)); + if (isMaskSet(dmxsendparams::Mask::SLOTS_COUNT)) { + p->SetDmxSlots(dmxsendparams::roundup_slots(m_Params.nSlotsCount)); } } +void DmxParams::staticCallbackFunction(void *p, const char *s) { + assert(p != nullptr); + assert(s != nullptr); + + (static_cast(p))->callbackFunction(s); +} + void DmxParams::Dump() { -#ifndef NDEBUG printf("%s::%s \'%s\':\n", __FILE__, __FUNCTION__, DmxParamsConst::FILE_NAME); - if (isMaskSet(DmxParamsMask::BREAK_TIME)) { - printf(" %s=%d\n", DmxParamsConst::BREAK_TIME, m_tDmxParams.nBreakTime); + if (isMaskSet(dmxsendparams::Mask::BREAK_TIME)) { + printf(" %s=%d\n", DmxParamsConst::BREAK_TIME, m_Params.nBreakTime); } - if (isMaskSet(DmxParamsMask::MAB_TIME)) { - printf(" %s=%d\n", DmxParamsConst::MAB_TIME, m_tDmxParams.nMabTime); + if (isMaskSet(dmxsendparams::Mask::MAB_TIME)) { + printf(" %s=%d\n", DmxParamsConst::MAB_TIME, m_Params.nMabTime); } - if (isMaskSet(DmxParamsMask::REFRESH_RATE)) { - printf(" %s=%d\n", DmxParamsConst::REFRESH_RATE, m_tDmxParams.nRefreshRate); + if (isMaskSet(dmxsendparams::Mask::REFRESH_RATE)) { + printf(" %s=%d\n", DmxParamsConst::REFRESH_RATE, m_Params.nRefreshRate); } - if (isMaskSet(DmxParamsMask::SLOTS_COUNT)) { - printf(" %s=%d [%d]\n", DmxParamsConst::SLOTS_COUNT, m_tDmxParams.nSlotsCount, dmxparams::roundup_slots(m_tDmxParams.nSlotsCount)); + if (isMaskSet(dmxsendparams::Mask::SLOTS_COUNT)) { + printf(" %s=%d [%d]\n", DmxParamsConst::SLOTS_COUNT, m_Params.nSlotsCount, dmxsendparams::roundup_slots(m_Params.nSlotsCount)); } -#endif -} - -void DmxParams::staticCallbackFunction(void *p, const char *s) { - assert(p != nullptr); - assert(s != nullptr); - - (static_cast(p))->callbackFunction(s); } diff --git a/lib-dmx/src/e131/dmxinput.cpp b/lib-dmx/src/e131/dmxinput.cpp deleted file mode 100644 index 10d35ef7..00000000 --- a/lib-dmx/src/e131/dmxinput.cpp +++ /dev/null @@ -1,92 +0,0 @@ -/** - * @file dmxinput.cpp - * - */ -/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#include - -#include "dmx.h" - -#include "debug.h" - -namespace e131 { -static uint8_t s_nStarted; - -static constexpr bool is_started(const uint8_t v, const uint32_t p) { - return (v & (1U << p)) == (1U << p); -} - -void dmx_start(const uint32_t nPortIndex) { - DEBUG_ENTRY - - assert(nPortIndex < CHAR_BIT); - - DEBUG_PRINTF("nPortIndex=%d", nPortIndex); - - if (is_started(s_nStarted, nPortIndex)) { - DEBUG_EXIT - return; - } - - s_nStarted = static_cast(s_nStarted | (1U << nPortIndex)); - - Dmx::Get()->SetPortDirection(nPortIndex, dmx::PortDirection::INP, true); - - DEBUG_EXIT -} - -void dmx_stop(const uint32_t nPortIndex) { - DEBUG_ENTRY - assert(nPortIndex < CHAR_BIT); - - DEBUG_PRINTF("nPortIndex=%d -> %u", nPortIndex, is_started(s_nStarted, nPortIndex)); - - if (!is_started(s_nStarted, nPortIndex)) { - DEBUG_EXIT - return; - } - - s_nStarted = static_cast(s_nStarted & ~(1U << nPortIndex)); - - Dmx::Get()->SetPortDirection(nPortIndex, dmx::PortDirection::INP, false); - - DEBUG_EXIT -} - -const uint8_t *dmx_handler(const uint32_t nPortIndex, uint32_t& nLength, uint32_t &nUpdatesPerSecond) { - const auto *pDmx = Dmx::Get()->GetDmxAvailable(nPortIndex); - - nUpdatesPerSecond = Dmx::Get()->GetDmxUpdatesPerSecond(nPortIndex); - - if (pDmx != nullptr) { - const auto *pDmxData = reinterpret_cast(pDmx); - nLength = (1U + pDmxData->Statistics.nSlotsInPacket); // Add 1 for SC - return pDmx; - } - - nLength = 0; - return nullptr; -} -} // namespace e131 diff --git a/lib-dmx/src/gd32/dmx.cpp b/lib-dmx/src/gd32/dmx.cpp index 67ab9dd6..67d5b2b9 100644 --- a/lib-dmx/src/gd32/dmx.cpp +++ b/lib-dmx/src/gd32/dmx.cpp @@ -1,8 +1,7 @@ /** * @file dmx.cpp - * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,24 +22,14 @@ * THE SOFTWARE. */ +#if defined (CONFIG_TIMER6_HAVE_NO_IRQ_HANDLER) +# error +#endif + #pragma GCC push_options #pragma GCC optimize ("O3") -#pragma GCC optimize ("-funroll-loops") #pragma GCC optimize ("-fprefetch-loop-arrays") -#if 0 -# if defined (GD32F207RG) -# define LOGIC_ANALYZER -# if defined (NDEBUG) -# undef NDEBUG -# endif -# endif -#endif - -extern "C" { -void console_error(const char *); -} - #include #include #include @@ -53,6 +42,7 @@ void console_error(const char *); #include "rdm_e120.h" #include "gd32.h" +#include "gd32_dma.h" #include "gd32_uart.h" #include "gd32/dmx_config.h" #include "dmx_internal.h" @@ -61,24 +51,7 @@ void console_error(const char *); #include "debug.h" -#ifndef ALIGNED -# define ALIGNED __attribute__ ((aligned (4))) -#endif - -#if !defined(CONFIG_DMX_TRANSMIT_ONLY) -# define UNUSED -# else -# define UNUSED __attribute__((unused)) -#endif - -/** - * https://www.gd32-dmx.org/memory.html - */ -#if defined (GD32F20X) ||defined (GD32F4XX) -# define SECTION_DMA_BUFFER __attribute__ ((section (".dmx"))) -#else -# define SECTION_DMA_BUFFER -#endif +extern struct HwTimersSeconds g_Seconds; namespace dmx { enum class TxRxState { @@ -90,37 +63,45 @@ enum class PortState { }; struct TxDmxPacket { - uint8_t data[dmx::buffer::SIZE]; // multiple of uint16_t - uint16_t nLength; + uint8_t data[dmx::buffer::SIZE]; // multiple of uint32_t + uint32_t nLength; + bool bDataPending; }; struct TxData { - struct TxDmxPacket dmx; - OutputStyle outputStyle; + TxDmxPacket dmx; + OutputStyle outputStyle ALIGNED; volatile TxRxState State; }; +struct DmxTransmit { + uint32_t nBreakTime; + uint32_t nMabTime; + uint32_t nInterTime; +}; + struct RxDmxPackets { uint32_t nPerSecond; uint32_t nCount; uint32_t nCountPrevious; - uint16_t nTimerCounterPrevious; }; -struct RxRdmPackets { - uint32_t nIndex; - uint16_t nChecksum; // This must be uint16_t - uint16_t nDiscIndex; +struct RxDmxData { + uint8_t data[dmx::buffer::SIZE] ALIGNED; // multiple of uint32_t + uint32_t nSlotsInPacket; }; struct RxData { - uint8_t data[dmx::buffer::SIZE]; // multiple of uint16_t - union { - volatile RxRdmPackets Rdm; - volatile Statistics Dmx; - }; + struct { + volatile RxDmxData current; + RxDmxData previous; + } Dmx ALIGNED; + struct { + volatile uint8_t data[sizeof(struct TRdmMessage)] ALIGNED; + volatile uint32_t nIndex; + } Rdm ALIGNED; volatile TxRxState State; -}; +} ALIGNED; struct DirGpio { uint32_t nPort; @@ -155,272 +136,157 @@ static constexpr DirGpio s_DirGpio[DMX_MAX_PORTS] = { #endif }; -static volatile PortState sv_PortState[config::max::OUT] ALIGNED; +static volatile PortState sv_PortState[dmx::config::max::PORTS] ALIGNED; + +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) +static volatile dmx::TotalStatistics sv_TotalStatistics[dmx::config::max::PORTS] ALIGNED; +#endif // DMX RX -static uint8_t UNUSED s_RxDmxPrevious[config::max::IN][dmx::buffer::SIZE] ALIGNED; -static volatile RxDmxPackets sv_nRxDmxPackets[config::max::IN] ALIGNED; +static volatile RxDmxPackets sv_nRxDmxPackets[dmx::config::max::PORTS] ALIGNED; // RDM RX -volatile uint32_t gv_RdmDataReceiveEnd; +volatile uint32_t gsv_RdmDataReceiveEnd; // DMX RDM RX -static RxData s_RxBuffer[config::max::IN] ALIGNED; +static RxData sv_RxBuffer[dmx::config::max::PORTS] ALIGNED; // DMX TX -static TxData s_TxBuffer[config::max::OUT] ALIGNED SECTION_DMA_BUFFER; +static TxData s_TxBuffer[dmx::config::max::PORTS] ALIGNED SECTION_DMA_BUFFER; +static DmxTransmit s_nDmxTransmit; -static uint32_t s_nDmxTransmitBreakTime { dmx::transmit::BREAK_TIME_TYPICAL }; -static uint32_t s_nDmxTransmitMabTime { dmx::transmit::MAB_TIME_MIN }; ///< MAB_TIME_MAX = 1000000U; -static uint32_t s_nDmxTransmitInterTime { dmx::transmit::PERIOD_DEFAULT - dmx::transmit::MAB_TIME_MIN - dmx::transmit::BREAK_TIME_TYPICAL - (dmx::max::CHANNELS * 44) - 44 }; +template +void irq_handler_dmx_rdm_input() { + const auto isFlagIdleFrame = (USART_REG_VAL(uart, USART_FLAG_IDLE) & BIT(USART_BIT_POS(USART_FLAG_IDLE))) == BIT(USART_BIT_POS(USART_FLAG_IDLE)); + /* + * Software can clear this bit by reading the USART_STAT and USART_DATA registers one by one. + */ + if (isFlagIdleFrame) { + static_cast(GET_BITS(USART_RDATA(uart), 0U, 8U)); + + if (sv_RxBuffer[nPortIndex].State == TxRxState::DMXDATA) { + sv_RxBuffer[nPortIndex].State = TxRxState::IDLE; + sv_RxBuffer[nPortIndex].Dmx.current.nSlotsInPacket |= 0x8000; -static void irq_handler_dmx_rdm_input(const uint32_t uart, const uint32_t nPortIndex) { - uint32_t nIndex; - uint16_t nCounter; + return; + } + + if (sv_RxBuffer[0].State == TxRxState::RDMDISC) { + sv_RxBuffer[nPortIndex].State = TxRxState::IDLE; + sv_RxBuffer[nPortIndex].Rdm.nIndex |= 0x4000; - if (RESET != (USART_REG_VAL(uart, USART_FLAG_FERR) & BIT(USART_BIT_POS(USART_FLAG_FERR)))) { - USART_REG_VAL(uart, USART_FLAG_FERR) &= ~BIT(USART_BIT_POS(USART_FLAG_FERR)); - static_cast(GET_BITS(USART_DATA(uart), 0U, 8U)); - if (s_RxBuffer[nPortIndex].State == TxRxState::IDLE) { - s_RxBuffer[nPortIndex].Dmx.nSlotsInPacket = 0; - s_RxBuffer[nPortIndex].State = TxRxState::BREAK; + return; } + return; } - const auto data = static_cast(GET_BITS(USART_DATA(uart), 0U, 8U)); + const auto isFlagFrameError = (USART_REG_VAL(uart, USART_FLAG_FERR) & BIT(USART_BIT_POS(USART_FLAG_FERR))) == BIT(USART_BIT_POS(USART_FLAG_FERR)); + /* + * Software can clear this bit by reading the USART_STAT and USART_DATA registers one by one. + */ + if (isFlagFrameError) { + static_cast(GET_BITS(USART_RDATA(uart), 0U, 8U)); - switch (s_RxBuffer[nPortIndex].State) { - case TxRxState::IDLE: - s_RxBuffer[nPortIndex].State = TxRxState::RDMDISC; - s_RxBuffer[nPortIndex].data[0] = data; - s_RxBuffer[nPortIndex].Rdm.nIndex = 1; -#if DMX_MAX_PORTS >= 5 - if (nPortIndex < 4) { -#endif - sv_nRxDmxPackets[nPortIndex].nTimerCounterPrevious = static_cast(TIMER_CNT(TIMER2)); -#if DMX_MAX_PORTS >= 5 - } else { - sv_nRxDmxPackets[nPortIndex].nTimerCounterPrevious = static_cast(TIMER_CNT(TIMER3)); + if (sv_RxBuffer[nPortIndex].State == TxRxState::IDLE) { + sv_RxBuffer[nPortIndex].State = TxRxState::BREAK; } -#endif + + return; + } + + const auto data = static_cast(GET_BITS(USART_RDATA(uart), 0U, 8U)); + + switch (sv_RxBuffer[nPortIndex].State) { + case TxRxState::IDLE: + sv_RxBuffer[nPortIndex].State = TxRxState::RDMDISC; + sv_RxBuffer[nPortIndex].Rdm.data[0] = data; + sv_RxBuffer[nPortIndex].Rdm.nIndex = 1; break; case TxRxState::BREAK: switch (data) { case START_CODE: - s_RxBuffer[nPortIndex].data[0] = START_CODE; - s_RxBuffer[nPortIndex].Dmx.nSlotsInPacket = 1; + sv_RxBuffer[nPortIndex].Dmx.current.data[0] = START_CODE; + sv_RxBuffer[nPortIndex].Dmx.current.nSlotsInPacket = 1; sv_nRxDmxPackets[nPortIndex].nCount++; - s_RxBuffer[nPortIndex].State = TxRxState::DMXDATA; -#if DMX_MAX_PORTS >= 5 - if (nPortIndex < 4) { -#endif - sv_nRxDmxPackets[nPortIndex].nTimerCounterPrevious = static_cast(TIMER_CNT(TIMER2)); -#if DMX_MAX_PORTS >= 5 - } else { - sv_nRxDmxPackets[nPortIndex].nTimerCounterPrevious = static_cast(TIMER_CNT(TIMER3)); - } -#endif + sv_RxBuffer[nPortIndex].State = TxRxState::DMXDATA; break; case E120_SC_RDM: - s_RxBuffer[nPortIndex].data[0] = E120_SC_RDM; - s_RxBuffer[nPortIndex].Rdm.nChecksum = E120_SC_RDM; - s_RxBuffer[nPortIndex].Rdm.nIndex = 1; - s_RxBuffer[nPortIndex].State = TxRxState::RDMDATA; + sv_RxBuffer[nPortIndex].Rdm.data[0] = E120_SC_RDM; + sv_RxBuffer[nPortIndex].Rdm.nIndex = 1; + sv_RxBuffer[nPortIndex].State = TxRxState::RDMDATA; break; default: - s_RxBuffer[nPortIndex].State = TxRxState::IDLE; + sv_RxBuffer[nPortIndex].Dmx.current.nSlotsInPacket = 0; + sv_RxBuffer[nPortIndex].Rdm.nIndex = 0; + sv_RxBuffer[nPortIndex].State = TxRxState::IDLE; break; } break; - case TxRxState::DMXDATA: - nIndex = s_RxBuffer[nPortIndex].Dmx.nSlotsInPacket; - s_RxBuffer[nPortIndex].data[nIndex] = data; - s_RxBuffer[nPortIndex].Dmx.nSlotsInPacket++; - - if (s_RxBuffer[nPortIndex].Dmx.nSlotsInPacket > dmx::max::CHANNELS) { - s_RxBuffer[nPortIndex].Dmx.nSlotsInPacket |= 0x8000; - s_RxBuffer[nPortIndex].State = TxRxState::IDLE; - break; - } -#if DMX_MAX_PORTS >= 5 - if (nPortIndex < 4) { -#endif - nCounter = static_cast(TIMER_CNT(TIMER2)); -#if DMX_MAX_PORTS >= 5 - } else { - nCounter = static_cast(TIMER_CNT(TIMER3)); - } -#endif - { - const uint16_t nDelta = nCounter - sv_nRxDmxPackets[nPortIndex].nTimerCounterPrevious; - sv_nRxDmxPackets[nPortIndex].nTimerCounterPrevious = nCounter; - const auto nPulse = static_cast(nCounter + nDelta + 4); - - switch(nPortIndex){ - case 0: - TIMER_CH0CV(TIMER2) = nPulse; - break; -#if DMX_MAX_PORTS >= 2 - case 1: - TIMER_CH1CV(TIMER2) = nPulse; - break; -#endif -#if DMX_MAX_PORTS >= 3 - case 2: - TIMER_CH2CV(TIMER2) = nPulse; - break; -#endif -#if DMX_MAX_PORTS >= 4 - case 3: - TIMER_CH3CV(TIMER2) = nPulse; - break; -#endif -#if DMX_MAX_PORTS >= 5 - case 4: - TIMER_CH0CV(TIMER3) = nPulse; - break; -#endif -#if DMX_MAX_PORTS >= 6 - case 5: - TIMER_CH1CV(TIMER3) = nPulse; - break; -#endif -#if DMX_MAX_PORTS >= 7 - case 6: - TIMER_CH2CV(TIMER3) = nPulse; - break; -#endif -#if DMX_MAX_PORTS == 8 - case 7: - TIMER_CH3CV(TIMER3) = nPulse; - break; -#endif - default: - assert(0); - __builtin_unreachable(); - break; - } - } + case TxRxState::DMXDATA: { + auto nIndex = sv_RxBuffer[nPortIndex].Dmx.current.nSlotsInPacket; + sv_RxBuffer[nPortIndex].Dmx.current.data[nIndex] = data; + nIndex++; + sv_RxBuffer[nPortIndex].Dmx.current.nSlotsInPacket = nIndex; + + if (nIndex > dmx::max::CHANNELS) { + nIndex |= 0x8000; + sv_RxBuffer[nPortIndex].Dmx.current.nSlotsInPacket = nIndex; + sv_RxBuffer[nPortIndex].State = TxRxState::IDLE; break; - case TxRxState::RDMDATA: { - nIndex = s_RxBuffer[nPortIndex].Rdm.nIndex; - s_RxBuffer[nPortIndex].data[nIndex] = data; - s_RxBuffer[nPortIndex].Rdm.nIndex++; - - s_RxBuffer[nPortIndex].Rdm.nChecksum = static_cast(s_RxBuffer[nPortIndex].Rdm.nChecksum + data); - - const auto *p = reinterpret_cast(&s_RxBuffer[nPortIndex].data[0]); - - nIndex = s_RxBuffer[nPortIndex].Rdm.nIndex; - - if ((nIndex >= 24) && (nIndex <= sizeof(struct TRdmMessage)) && (nIndex == p->message_length)) { - s_RxBuffer[nPortIndex].State = TxRxState::CHECKSUMH; - } else if (nIndex > sizeof(struct TRdmMessage)) { - s_RxBuffer[nPortIndex].State = TxRxState::IDLE; - } } + } break; - case TxRxState::CHECKSUMH: - nIndex = s_RxBuffer[nPortIndex].Rdm.nIndex; - s_RxBuffer[nPortIndex].data[nIndex] = data; - s_RxBuffer[nPortIndex].Rdm.nIndex++; - s_RxBuffer[nPortIndex].Rdm.nChecksum = static_cast(s_RxBuffer[nPortIndex].Rdm.nChecksum - static_cast(data << 8)); - s_RxBuffer[nPortIndex].State = TxRxState::CHECKSUML; - break; - case TxRxState::CHECKSUML: { - nIndex = s_RxBuffer[nPortIndex].Rdm.nIndex; - s_RxBuffer[nPortIndex].data[nIndex] = data; - s_RxBuffer[nPortIndex].Rdm.nIndex++; - s_RxBuffer[nPortIndex].Rdm.nChecksum = static_cast(s_RxBuffer[nPortIndex].Rdm.nChecksum - data); - - const auto *p = reinterpret_cast(&s_RxBuffer[nPortIndex].data[0]); - - if (!((s_RxBuffer[nPortIndex].Rdm.nChecksum == 0) && (p->sub_start_code == E120_SC_SUB_MESSAGE))) { - s_RxBuffer[nPortIndex].Dmx.nSlotsInPacket= 0; // This is correct. - } else { - s_RxBuffer[nPortIndex].Rdm.nIndex |= 0x4000; - gv_RdmDataReceiveEnd = DWT->CYCCNT; - } - - s_RxBuffer[nPortIndex].State = TxRxState::IDLE; + case TxRxState::RDMDATA: { + auto nIndex = sv_RxBuffer[nPortIndex].Rdm.nIndex; + sv_RxBuffer[nPortIndex].Rdm.data[nIndex] = data; + nIndex++; + sv_RxBuffer[nPortIndex].Rdm.nIndex = nIndex; + + const auto *p = reinterpret_cast(&sv_RxBuffer[nPortIndex].Rdm.data[0]); + + if ((nIndex >= 24) && (nIndex <= sizeof(struct TRdmMessage)) && (nIndex == p->message_length)) { + sv_RxBuffer[nPortIndex].State = TxRxState::CHECKSUMH; + } else if (nIndex > sizeof(struct TRdmMessage)) { + sv_RxBuffer[nPortIndex].State = TxRxState::IDLE; } + } break; - case TxRxState::RDMDISC: - nIndex = s_RxBuffer[nPortIndex].Rdm.nIndex; - - if (nIndex < 24) { - s_RxBuffer[nPortIndex].data[nIndex] = data; - s_RxBuffer[nPortIndex].Rdm.nIndex++; - } - -#if DMX_MAX_PORTS >= 5 - if (nPortIndex < 4) { -#endif - nCounter = static_cast(TIMER_CNT(TIMER2)); -#if DMX_MAX_PORTS >= 5 - } else { - nCounter = static_cast(TIMER_CNT(TIMER3)); - } -#endif - { - const uint16_t nDelta = nCounter - sv_nRxDmxPackets[nPortIndex].nTimerCounterPrevious; - sv_nRxDmxPackets[nPortIndex].nTimerCounterPrevious = nCounter; - const auto nPulse = static_cast(nCounter + nDelta + 4); + case TxRxState::CHECKSUMH: { + auto nIndex = sv_RxBuffer[nPortIndex].Rdm.nIndex; + sv_RxBuffer[nPortIndex].Rdm.data[nIndex] = data; + nIndex++; + sv_RxBuffer[nPortIndex].Rdm.nIndex = nIndex; + sv_RxBuffer[nPortIndex].State = TxRxState::CHECKSUML; + } + break; + case TxRxState::CHECKSUML: { + auto nIndex = sv_RxBuffer[nPortIndex].Rdm.nIndex; + sv_RxBuffer[nPortIndex].Rdm.data[nIndex] = data; + nIndex |= 0x4000; + sv_RxBuffer[nPortIndex].Rdm.nIndex = nIndex; + sv_RxBuffer[nPortIndex].State = TxRxState::IDLE; + gsv_RdmDataReceiveEnd = DWT->CYCCNT; + } + break; + case TxRxState::RDMDISC: { + auto nIndex = sv_RxBuffer[nPortIndex].Rdm.nIndex; - switch(nPortIndex){ - case 0: - TIMER_CH0CV(TIMER2) = nPulse; - break; -#if DMX_MAX_PORTS >= 2 - case 1: - TIMER_CH1CV(TIMER2) = nPulse; - break; -#endif -#if DMX_MAX_PORTS >= 3 - case 2: - TIMER_CH2CV(TIMER2) = nPulse; - break; -#endif -#if DMX_MAX_PORTS >= 4 - case 3: - TIMER_CH3CV(TIMER2) = nPulse; - break; -#endif -#if DMX_MAX_PORTS >= 5 - case 4: - TIMER_CH0CV(TIMER3) = nPulse; - break; -#endif -#if DMX_MAX_PORTS >= 6 - case 5: - TIMER_CH1CV(TIMER3) = nPulse; - break; -#endif -#if DMX_MAX_PORTS >= 7 - case 6: - TIMER_CH2CV(TIMER3) = nPulse; - break; -#endif -#if DMX_MAX_PORTS == 8 - case 7: - TIMER_CH3CV(TIMER3) = nPulse; - break; -#endif - default: - assert(0); - __builtin_unreachable(); - break; - } - } - break; - default: - s_RxBuffer[nPortIndex].Dmx.nSlotsInPacket= 0; // This is correct. - s_RxBuffer[nPortIndex].State = TxRxState::IDLE; - break; + if (nIndex < 24) { + sv_RxBuffer[nPortIndex].Rdm.data[nIndex] = data; + nIndex++; + sv_RxBuffer[nPortIndex].Rdm.nIndex = nIndex; + } + } + break; + default: + sv_RxBuffer[nPortIndex].Dmx.current.nSlotsInPacket = 0; + sv_RxBuffer[nPortIndex].Rdm.nIndex = 0; + sv_RxBuffer[nPortIndex].State = TxRxState::IDLE; + break; } } @@ -428,42 +294,42 @@ extern "C" { #if !defined(CONFIG_DMX_TRANSMIT_ONLY) #if defined (DMX_USE_USART0) void USART0_IRQHandler(void) { - irq_handler_dmx_rdm_input(USART0, config::USART0_PORT); + irq_handler_dmx_rdm_input(); } #endif #if defined (DMX_USE_USART1) void USART1_IRQHandler(void) { - irq_handler_dmx_rdm_input(USART1, config::USART1_PORT); + irq_handler_dmx_rdm_input(); } #endif #if defined (DMX_USE_USART2) void USART2_IRQHandler(void) { - irq_handler_dmx_rdm_input(USART2, config::USART2_PORT); + irq_handler_dmx_rdm_input(); } #endif #if defined (DMX_USE_UART3) void UART3_IRQHandler(void) { - irq_handler_dmx_rdm_input(UART3, config::UART3_PORT); + irq_handler_dmx_rdm_input(); } #endif #if defined (DMX_USE_UART4) void UART4_IRQHandler(void) { - irq_handler_dmx_rdm_input(UART4, config::UART4_PORT); + irq_handler_dmx_rdm_input(); } #endif #if defined (DMX_USE_USART5) void USART5_IRQHandler(void) { - irq_handler_dmx_rdm_input(USART5, config::USART5_PORT); + irq_handler_dmx_rdm_input(); } #endif #if defined (DMX_USE_UART6) void UART6_IRQHandler(void) { - irq_handler_dmx_rdm_input(UART6, config::UART6_PORT); + irq_handler_dmx_rdm_input(); } #endif #if defined (DMX_USE_UART7) void UART7_IRQHandler(void) { - irq_handler_dmx_rdm_input(UART7, config::UART7_PORT); + irq_handler_dmx_rdm_input(); } #endif #endif @@ -474,6 +340,7 @@ static void timer1_config() { timer_deinit(TIMER1); timer_parameter_struct timer_initpara; + timer_struct_para_init(&timer_initpara); timer_initpara.prescaler = TIMER_PSC_1MHZ; timer_initpara.alignedmode = TIMER_COUNTER_EDGE; @@ -489,22 +356,26 @@ static void timer1_config() { #if defined (DMX_USE_USART0) timer_channel_output_mode_config(TIMER1, TIMER_CH_0, TIMER_OC_MODE_ACTIVE); timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_0, ~0); -#endif + timer_interrupt_enable(TIMER1, TIMER_INT_CH0); +#endif /* DMX_USE_USART0 */ #if defined (DMX_USE_USART1) timer_channel_output_mode_config(TIMER1, TIMER_CH_1, TIMER_OC_MODE_ACTIVE); timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, ~0); -#endif + timer_interrupt_enable(TIMER1, TIMER_INT_CH1); +#endif /* DMX_USE_USART1 */ #if defined (DMX_USE_USART2) timer_channel_output_mode_config(TIMER1, TIMER_CH_2, TIMER_OC_MODE_ACTIVE); timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_2, ~0); -#endif + timer_interrupt_enable(TIMER1, TIMER_INT_CH2); +#endif /* DMX_USE_USART2 */ #if defined (DMX_USE_UART3) - timer_channel_output_mode_config(TIMER1, TIMER_CH_2, TIMER_OC_MODE_ACTIVE); + timer_channel_output_mode_config(TIMER1, TIMER_CH_3, TIMER_OC_MODE_ACTIVE); timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_3, ~0); -#endif + timer_interrupt_enable(TIMER1, TIMER_INT_CH3); +#endif /* DMX_USE_UART3 */ NVIC_SetPriority(TIMER1_IRQn, 0); NVIC_EnableIRQ(TIMER1_IRQn); @@ -517,6 +388,7 @@ static void timer4_config() { timer_deinit(TIMER4); timer_parameter_struct timer_initpara; + timer_struct_para_init(&timer_initpara); timer_initpara.prescaler = TIMER_PSC_1MHZ; timer_initpara.alignedmode = TIMER_COUNTER_EDGE; @@ -532,22 +404,26 @@ static void timer4_config() { #if defined (DMX_USE_UART4) timer_channel_output_mode_config(TIMER4, TIMER_CH_0, TIMER_OC_MODE_ACTIVE); timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_0, ~0); -#endif + timer_interrupt_enable(TIMER4, TIMER_INT_CH0); +#endif /* DMX_USE_UART4 */ #if defined (DMX_USE_USART5) timer_channel_output_mode_config(TIMER4, TIMER_CH_1, TIMER_OC_MODE_ACTIVE); timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_1, ~0); -#endif + timer_interrupt_enable(TIMER4, TIMER_INT_CH1); +#endif /* DMX_USE_USART5 */ #if defined (DMX_USE_UART6) timer_channel_output_mode_config(TIMER4, TIMER_CH_2, TIMER_OC_MODE_ACTIVE); timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_2, ~0); -#endif + timer_interrupt_enable(TIMER4, TIMER_INT_CH2); +#endif /* DMX_USE_UART6 */ #if defined (DMX_USE_UART7) timer_channel_output_mode_config(TIMER4, TIMER_CH_3, TIMER_OC_MODE_ACTIVE); timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_3, ~0); -#endif + timer_interrupt_enable(TIMER4, TIMER_INT_CH3); +#endif /* DMX_USE_UART7 */ NVIC_SetPriority(TIMER4_IRQn, 0); NVIC_EnableIRQ(TIMER4_IRQn); @@ -555,116 +431,47 @@ static void timer4_config() { timer_enable(TIMER4); } -#if !defined(CONFIG_DMX_TRANSMIT_ONLY) -static void timer2_config() { - rcu_periph_clock_enable(RCU_TIMER2); - timer_deinit(TIMER2); - - timer_parameter_struct timer_initpara; - - timer_initpara.prescaler = TIMER_PSC_1MHZ; - timer_initpara.alignedmode = TIMER_COUNTER_EDGE; - timer_initpara.counterdirection = TIMER_COUNTER_UP; - timer_initpara.period = static_cast(~0); - timer_initpara.clockdivision = TIMER_CKDIV_DIV1; - timer_initpara.repetitioncounter = 0; - timer_init(TIMER2, &timer_initpara); - - timer_flag_clear(TIMER2, ~0); - timer_interrupt_flag_clear(TIMER2, ~0); - - timer_channel_output_mode_config(TIMER2, TIMER_CH_0, TIMER_OC_MODE_ACTIVE); - timer_channel_output_mode_config(TIMER2, TIMER_CH_1, TIMER_OC_MODE_ACTIVE); - timer_channel_output_mode_config(TIMER2, TIMER_CH_2, TIMER_OC_MODE_ACTIVE); - timer_channel_output_mode_config(TIMER2, TIMER_CH_3, TIMER_OC_MODE_ACTIVE); - - NVIC_SetPriority(TIMER2_IRQn, 1); - NVIC_EnableIRQ(TIMER2_IRQn); - - timer_enable(TIMER2); -} - -static void timer3_config() { -#if DMX_MAX_PORTS >= 5 - rcu_periph_clock_enable(RCU_TIMER3); - timer_deinit(TIMER3); - - timer_parameter_struct timer_initpara; - - timer_initpara.prescaler = TIMER_PSC_1MHZ; - timer_initpara.alignedmode = TIMER_COUNTER_EDGE; - timer_initpara.counterdirection = TIMER_COUNTER_UP; - timer_initpara.period = static_cast(~0); - timer_initpara.clockdivision = TIMER_CKDIV_DIV1; - timer_initpara.repetitioncounter = 0; - timer_init(TIMER3, &timer_initpara); - - timer_flag_clear(TIMER3, ~0); - timer_interrupt_flag_clear(TIMER3, ~0); - - timer_channel_output_mode_config(TIMER3, TIMER_CH_0, TIMER_OC_MODE_ACTIVE); - timer_channel_output_mode_config(TIMER3, TIMER_CH_1, TIMER_OC_MODE_ACTIVE); - timer_channel_output_mode_config(TIMER3, TIMER_CH_2, TIMER_OC_MODE_ACTIVE); - timer_channel_output_mode_config(TIMER3, TIMER_CH_3, TIMER_OC_MODE_ACTIVE); - - NVIC_SetPriority(TIMER3_IRQn, 1); - NVIC_EnableIRQ(TIMER3_IRQn); - - timer_enable(TIMER3); -#endif -} - -static void timer6_config() { - rcu_periph_clock_enable(RCU_TIMER6); - timer_deinit(TIMER6); - - timer_parameter_struct timer_initpara; - timer_initpara.prescaler = TIMER_PSC_10KHZ; - timer_initpara.period = 10000; // 1 second - timer_init(TIMER6, &timer_initpara); - - timer_flag_clear(TIMER6, ~0); - timer_interrupt_flag_clear(TIMER6, ~0); - - timer_interrupt_enable(TIMER6, TIMER_INT_UP); - - NVIC_SetPriority(TIMER6_IRQn, 0); - NVIC_EnableIRQ(TIMER6_IRQn); - - timer_enable(TIMER6); -} -#endif - static void usart_dma_config(void) { DMA_PARAMETER_STRUCT dma_init_struct; rcu_periph_clock_enable(RCU_DMA0); rcu_periph_clock_enable(RCU_DMA1); +#if defined (GD32H7XX) + rcu_periph_clock_enable(RCU_DMAMUX); +#endif +#if defined (DMX_USE_USART0) /* - * USART 0 + * USART 0 TX */ -#if defined (DMX_USE_USART0) - dma_deinit(USART0_DMA, USART0_TX_DMA_CH); + dma_deinit(USART0_DMAx, USART0_TX_DMA_CHx); +# if defined (GD32H7XX) + dma_init_struct.request = DMA_REQUEST_USART0_TX; +# endif dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; -#if !defined (GD32F4XX) +# if defined (GD32F4XX) || defined (GD32H7XX) +# else dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; -#endif +# endif +# if defined (GD32H7XX) + dma_init_struct.periph_addr = (uint32_t) &USART_TDATA(USART0); +# else dma_init_struct.periph_addr = USART0 + 0x04U; +# endif dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; -#if !defined (GD32F4XX) - dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; -#else +# if defined (GD32F4XX) || defined (GD32H7XX) dma_init_struct.periph_memory_width = DMA_PERIPHERAL_WIDTH_8BIT; -#endif +# else + dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; +# endif dma_init_struct.priority = DMA_PRIORITY_HIGH; - dma_init(USART0_DMA, USART0_TX_DMA_CH, &dma_init_struct); + dma_init(USART0_DMAx, USART0_TX_DMA_CHx, &dma_init_struct); /* configure DMA mode */ - dma_circulation_disable(USART0_DMA, USART0_TX_DMA_CH); - dma_memory_to_memory_disable(USART0_DMA, USART0_TX_DMA_CH); + dma_circulation_disable(USART0_DMAx, USART0_TX_DMA_CHx); + dma_memory_to_memory_disable(USART0_DMAx, USART0_TX_DMA_CHx); # if defined (GD32F4XX) - dma_channel_subperipheral_select(USART0_DMA, USART0_TX_DMA_CH, USART0_TX_DMA_SUBPERIx); + dma_channel_subperipheral_select(USART0_DMAx, USART0_TX_DMA_CHx, USART0_TX_DMA_SUBPERIx); # endif - dma_interrupt_disable(USART0_DMA, USART0_TX_DMA_CH, DMA_INTERRUPT_DISABLE); + gd32_dma_interrupt_disable(); # if !defined (GD32F4XX) NVIC_SetPriority(DMA0_Channel3_IRQn, 1); NVIC_EnableIRQ(DMA0_Channel3_IRQn); @@ -672,91 +479,120 @@ static void usart_dma_config(void) { NVIC_SetPriority(DMA1_Channel7_IRQn, 1); NVIC_EnableIRQ(DMA1_Channel7_IRQn); # endif -#endif +#endif /* DMX_USE_USART0 */ +#if defined (DMX_USE_USART1) /* - * USART 1 + * USART 1 TX */ -#if defined (DMX_USE_USART1) - dma_deinit(USART1_DMA, USART1_TX_DMA_CH); + dma_deinit(USART1_DMAx, USART1_TX_DMA_CHx); +# if defined (GD32H7XX) + dma_init_struct.request = DMA_REQUEST_USART1_TX; +# endif dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; -#if !defined (GD32F4XX) +# if defined (GD32F4XX) || defined (GD32H7XX) +# else dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; -#endif +# endif +# if defined (GD32H7XX) + dma_init_struct.periph_addr = (uint32_t) &USART_TDATA(USART1); +# else dma_init_struct.periph_addr = USART1 + 0x04U; +# endif dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; -#if !defined (GD32F4XX) - dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; -#else +# if defined (GD32F4XX) || defined (GD32H7XX) dma_init_struct.periph_memory_width = DMA_PERIPHERAL_WIDTH_8BIT; -#endif +# else + dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; +# endif dma_init_struct.priority = DMA_PRIORITY_HIGH; - dma_init(USART1_DMA, USART1_TX_DMA_CH, &dma_init_struct); + dma_init(USART1_DMAx, USART1_TX_DMA_CHx, &dma_init_struct); /* configure DMA mode */ - dma_circulation_disable(USART1_DMA, USART1_TX_DMA_CH); - dma_memory_to_memory_disable(USART1_DMA, USART1_TX_DMA_CH); + dma_circulation_disable(USART1_DMAx, USART1_TX_DMA_CHx); + dma_memory_to_memory_disable(USART1_DMAx, USART1_TX_DMA_CHx); # if defined (GD32F4XX) - dma_channel_subperipheral_select(USART1_DMA, USART1_TX_DMA_CH, USART1_TX_DMA_SUBPERIx); + dma_channel_subperipheral_select(USART1_DMAx, USART1_TX_DMA_CHx, USART1_TX_DMA_SUBPERIx); # endif - dma_interrupt_disable(USART1_DMA, USART1_TX_DMA_CH, DMA_INTERRUPT_DISABLE); + gd32_dma_interrupt_disable(); NVIC_SetPriority(DMA0_Channel6_IRQn, 1); NVIC_EnableIRQ(DMA0_Channel6_IRQn); -#endif +#endif /* DMX_USE_USART1 */ +#if defined (DMX_USE_USART2) /* - * USART 2 + * USART 2 TX */ -#if defined (DMX_USE_USART2) - dma_deinit(USART2_DMA, USART2_TX_DMA_CH); + dma_deinit(USART2_DMAx, USART2_TX_DMA_CHx); +# if defined (GD32H7XX) + dma_init_struct.request = DMA_REQUEST_USART2_TX; +# endif dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; -# if !defined (GD32F4XX) +# if defined (GD32F4XX) || defined (GD32H7XX) +# else dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; # endif - dma_init_struct.periph_addr = USART2 + 0x04U; +//# if defined (GD32H7XX) + dma_init_struct.periph_addr = (uint32_t) &USART_TDATA(USART2); +//# else +// dma_init_struct.periph_addr = USART2 + 0x04U; +//# endif dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; -# if !defined (GD32F4XX) - dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; -# else +# if defined (GD32F4XX) || defined (GD32H7XX) dma_init_struct.periph_memory_width = DMA_PERIPHERAL_WIDTH_8BIT; +# else + dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; # endif dma_init_struct.priority = DMA_PRIORITY_HIGH; - dma_init(USART2_DMA, USART2_TX_DMA_CH, &dma_init_struct); + dma_init(USART2_DMAx, USART2_TX_DMA_CHx, &dma_init_struct); /* configure DMA mode */ - dma_circulation_disable(USART2_DMA, USART2_TX_DMA_CH); - dma_memory_to_memory_disable(USART2_DMA, USART2_TX_DMA_CH); + dma_circulation_disable(USART2_DMAx, USART2_TX_DMA_CHx); + dma_memory_to_memory_disable(USART2_DMAx, USART2_TX_DMA_CHx); # if defined (GD32F4XX) - dma_channel_subperipheral_select(USART2_DMA, USART2_TX_DMA_CH, USART2_TX_DMA_SUBPERIx); + dma_channel_subperipheral_select(USART2_DMAx, USART2_TX_DMA_CHx, USART2_TX_DMA_SUBPERIx); # endif - dma_interrupt_disable(USART2_DMA, USART2_TX_DMA_CH, DMA_INTERRUPT_DISABLE); + gd32_dma_interrupt_disable(); +#if defined (GD32F4XX) || defined (GD32H7XX) + NVIC_SetPriority(DMA0_Channel3_IRQn, 1); + NVIC_EnableIRQ(DMA0_Channel3_IRQn); +# else NVIC_SetPriority(DMA0_Channel1_IRQn, 1); NVIC_EnableIRQ(DMA0_Channel1_IRQn); -#endif +# endif +#endif /* DMX_USE_USART2 */ +#if defined (DMX_USE_UART3) /* - * UART 3 + * UART 3 TX */ -#if defined (DMX_USE_UART3) - dma_deinit(DMA1, DMA_CH4); + dma_deinit(UART3_DMAx, UART3_TX_DMA_CHx); +# if defined (GD32H7XX) + dma_init_struct.request = DMA_REQUEST_UART3_TX; +# endif dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; -#if !defined (GD32F4XX) +# if defined (GD32F4XX) || defined (GD32H7XX) +# else dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; -#endif +# endif +# if defined (GD32H7XX) + dma_init_struct.periph_addr = (uint32_t) &USART_TDATA(UART3); +# else dma_init_struct.periph_addr = UART3 + 0x04U; +# endif dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; -#if !defined (GD32F4XX) - dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; -#else +# if defined (GD32F4XX) || defined (GD32H7XX) dma_init_struct.periph_memory_width = DMA_PERIPHERAL_WIDTH_8BIT; -#endif +# else + dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; +# endif dma_init_struct.priority = DMA_PRIORITY_HIGH; - dma_init(DMA1, DMA_CH4, &dma_init_struct); + dma_init(UART3_DMAx, UART3_TX_DMA_CHx, &dma_init_struct); /* configure DMA mode */ - dma_circulation_disable(DMA1, DMA_CH4); - dma_memory_to_memory_disable(DMA1, DMA_CH4); + dma_circulation_disable(UART3_DMAx, UART3_TX_DMA_CHx); + dma_memory_to_memory_disable(UART3_DMAx, UART3_TX_DMA_CHx); # if defined (GD32F4XX) - dma_channel_subperipheral_select(UART3_DMA, UART3_TX_DMA_CH, UART3_TX_DMA_SUBPERIx); + dma_channel_subperipheral_select(UART3_DMAx, UART3_TX_DMA_CHx, UART3_TX_DMA_SUBPERIx); # endif - dma_interrupt_disable(USART0_DMA, USART0_TX_DMA_CH, DMA_INTERRUPT_DISABLE); + gd32_dma_interrupt_disable(); # if !defined (GD32F4XX) NVIC_SetPriority(DMA1_Channel4_IRQn, 1); NVIC_EnableIRQ(DMA1_Channel4_IRQn); @@ -764,96 +600,118 @@ static void usart_dma_config(void) { NVIC_SetPriority(DMA0_Channel4_IRQn, 1); NVIC_EnableIRQ(DMA0_Channel4_IRQn); # endif -#endif +#endif /* DMX_USE_UART3 */ +#if defined (DMX_USE_UART4) /* - * UART 4 + * UART 4 TX */ -#if defined (DMX_USE_UART4) - dma_deinit(UART4_DMA, UART4_TX_DMA_CH); + dma_deinit(UART4_DMAx, UART4_TX_DMA_CHx); +# if defined (GD32H7XX) + dma_init_struct.request = DMA_REQUEST_UART4_TX; +# endif dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; -#if !defined (GD32F4XX) +# if defined (GD32F4XX) || defined (GD32H7XX) +# else dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; -#endif +# endif +# if defined (GD32H7XX) + dma_init_struct.periph_addr = (uint32_t) &USART_TDATA(UART4); +# else dma_init_struct.periph_addr = UART4 + 0x04U; +# endif dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; -#if !defined (GD32F4XX) - dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; -#else +#if defined (GD32F4XX) || defined (GD32H7XX) dma_init_struct.periph_memory_width = DMA_PERIPHERAL_WIDTH_8BIT; +#else + dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; #endif dma_init_struct.priority = DMA_PRIORITY_HIGH; - dma_init(UART4_DMA, UART4_TX_DMA_CH, &dma_init_struct); + dma_init(UART4_DMAx, UART4_TX_DMA_CHx, &dma_init_struct); /* configure DMA mode */ - dma_circulation_disable(UART4_DMA, UART4_TX_DMA_CH); - dma_memory_to_memory_disable(UART4_DMA, UART4_TX_DMA_CH); + dma_circulation_disable(UART4_DMAx, UART4_TX_DMA_CHx); + dma_memory_to_memory_disable(UART4_DMAx, UART4_TX_DMA_CHx); # if defined (GD32F4XX) - dma_channel_subperipheral_select(UART4_DMA, UART4_TX_DMA_CH, UART4_TX_DMA_SUBPERIx); + dma_channel_subperipheral_select(UART4_DMAx, UART4_TX_DMA_CHx, UART4_TX_DMA_SUBPERIx); # endif - dma_interrupt_disable(UART4_DMA, UART4_TX_DMA_CH, DMA_INTERRUPT_DISABLE); -# if defined (GD32F20X) + gd32_dma_interrupt_disable(); +# if !defined (GD32F4XX) NVIC_SetPriority(DMA1_Channel3_IRQn, 1); NVIC_EnableIRQ(DMA1_Channel3_IRQn); # else NVIC_SetPriority(DMA0_Channel7_IRQn, 1); NVIC_EnableIRQ(DMA0_Channel7_IRQn); # endif -#endif +#endif /* DMX_USE_UART4 */ +#if defined (DMX_USE_USART5) /* - * USART 5 + * USART 5 TX */ -#if defined (DMX_USE_USART5) - dma_deinit(USART5_DMA, USART5_TX_DMA_CH); + dma_deinit(USART5_DMAx, USART5_TX_DMA_CHx); +# if defined (GD32H7XX) + dma_init_struct.request = DMA_REQUEST_USART5_TX; +# endif dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; -#if !defined (GD32F4XX) +# if defined (GD32F20X) dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; -#endif +# endif +# if defined (GD32H7XX) + dma_init_struct.periph_addr = (uint32_t) &USART_TDATA(USART5); +# else dma_init_struct.periph_addr = USART5 + 0x04U; +# endif dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; -#if !defined (GD32F4XX) +#if defined (GD32F20X) dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; -#else +# else dma_init_struct.periph_memory_width = DMA_PERIPHERAL_WIDTH_8BIT; #endif dma_init_struct.priority = DMA_PRIORITY_HIGH; - dma_init(USART5_DMA, USART5_TX_DMA_CH, &dma_init_struct); + dma_init(USART5_DMAx, USART5_TX_DMA_CHx, &dma_init_struct); /* configure DMA mode */ - dma_circulation_disable(USART5_DMA, USART5_TX_DMA_CH); - dma_memory_to_memory_disable(USART5_DMA, USART5_TX_DMA_CH); + dma_circulation_disable(USART5_DMAx, USART5_TX_DMA_CHx); + dma_memory_to_memory_disable(USART5_DMAx, USART5_TX_DMA_CHx); # if defined (GD32F4XX) - dma_channel_subperipheral_select(USART5_DMA, USART5_TX_DMA_CH, USART5_TX_DMA_SUBPERIx); + dma_channel_subperipheral_select(USART5_DMAx, USART5_TX_DMA_CHx, USART5_TX_DMA_SUBPERIx); # endif - dma_interrupt_disable(USART5_DMA, USART5_TX_DMA_CH, DMA_INTERRUPT_DISABLE); + gd32_dma_interrupt_disable(); NVIC_SetPriority(DMA1_Channel6_IRQn, 1); NVIC_EnableIRQ(DMA1_Channel6_IRQn); -#endif +#endif /* DMX_USE_USART5 */ +#if defined (DMX_USE_UART6) /* - * UART 6 + * UART 6 TX */ -#if defined (DMX_USE_UART6) - dma_deinit(UART6_DMA, UART6_TX_DMA_CH); + dma_deinit(UART6_DMAx, UART6_TX_DMA_CHx); +# if defined (GD32H7XX) + dma_init_struct.request = DMA_REQUEST_UART6_TX; +# endif dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; -#if !defined (GD32F4XX) +# if defined (GD32F20X) dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; -#endif +# endif +# if defined (GD32H7XX) + dma_init_struct.periph_addr = (uint32_t) &USART_TDATA(UART6); +# else dma_init_struct.periph_addr = UART6 + 0x04U; +# endif dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; -#if !defined (GD32F4XX) +# if defined (GD32F20X) dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; -#else +# else dma_init_struct.periph_memory_width = DMA_PERIPHERAL_WIDTH_8BIT; -#endif +# endif dma_init_struct.priority = DMA_PRIORITY_HIGH; - dma_init(UART6_DMA, UART6_TX_DMA_CH, &dma_init_struct); + dma_init(UART6_DMAx, UART6_TX_DMA_CHx, &dma_init_struct); /* configure DMA mode */ - dma_circulation_disable(UART6_DMA, UART6_TX_DMA_CH); - dma_memory_to_memory_disable(UART6_DMA, UART6_TX_DMA_CH); + dma_circulation_disable(UART6_DMAx, UART6_TX_DMA_CHx); + dma_memory_to_memory_disable(UART6_DMAx, UART6_TX_DMA_CHx); # if defined (GD32F4XX) - dma_channel_subperipheral_select(UART6_DMA, UART6_TX_DMA_CH, UART6_TX_DMA_SUBPERIx); + dma_channel_subperipheral_select(UART6_DMAx, UART6_TX_DMA_CHx, UART6_TX_DMA_SUBPERIx); # endif - dma_interrupt_disable(UART6_DMA, UART4_TX_DMA_CH, DMA_INTERRUPT_DISABLE); + gd32_dma_interrupt_disable(); # if defined (GD32F20X) NVIC_SetPriority(DMA1_Channel4_IRQn, 1); NVIC_EnableIRQ(DMA1_Channel4_IRQn); @@ -861,40 +719,47 @@ static void usart_dma_config(void) { NVIC_SetPriority(DMA0_Channel1_IRQn, 1); NVIC_EnableIRQ(DMA0_Channel1_IRQn); # endif -#endif +#endif /* DMX_USE_UART6 */ +#if defined (DMX_USE_UART7) /* - * UART 7 + * UART 7 TX */ -#if defined (DMX_USE_UART7) - dma_deinit(UART7_DMA, UART7_TX_DMA_CH); + dma_deinit(UART7_DMAx, UART7_TX_DMA_CHx); +# if defined (GD32H7XX) + dma_init_struct.request = DMA_REQUEST_UART7_TX; +# endif dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; -#if !defined (GD32F4XX) +# if defined (GD32F20X) dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT; -#endif +# endif +# if defined (GD32H7XX) + dma_init_struct.periph_addr = (uint32_t) &USART_TDATA(UART7); +# else dma_init_struct.periph_addr = UART7 + 0x04U; +# endif dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; -#if !defined (GD32F4XX) +# if defined (GD32F20X) dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT; -#else +# else dma_init_struct.periph_memory_width = DMA_PERIPHERAL_WIDTH_8BIT; -#endif +# endif dma_init_struct.priority = DMA_PRIORITY_HIGH; - dma_init(UART7_DMA, UART7_TX_DMA_CH, &dma_init_struct); + dma_init(UART7_DMAx, UART7_TX_DMA_CHx, &dma_init_struct); /* configure DMA mode */ - dma_circulation_disable(UART7_DMA, UART7_TX_DMA_CH); - dma_memory_to_memory_disable(UART7_DMA, UART7_TX_DMA_CH); + dma_circulation_disable(UART7_DMAx, UART7_TX_DMA_CHx); + dma_memory_to_memory_disable(UART7_DMAx, UART7_TX_DMA_CHx); # if defined (GD32F4XX) - dma_channel_subperipheral_select(UART7_DMA, UART7_TX_DMA_CH, UART7_TX_DMA_SUBPERIx); + dma_channel_subperipheral_select(UART7_DMAx, UART7_TX_DMA_CHx, UART7_TX_DMA_SUBPERIx); # endif -# if defined (GD32F20X) +#if defined (GD32F20X) NVIC_SetPriority(DMA1_Channel3_IRQn, 1); NVIC_EnableIRQ(DMA1_Channel3_IRQn); # else NVIC_SetPriority(DMA0_Channel0_IRQn, 1); NVIC_EnableIRQ(DMA0_Channel0_IRQn); # endif -#endif +#endif /* DMX_USE_UART7 */ } extern "C" { @@ -906,36 +771,35 @@ void TIMER1_IRQHandler() { if ((TIMER_INTF(TIMER1) & TIMER_INT_FLAG_CH0) == TIMER_INT_FLAG_CH0) { switch (s_TxBuffer[dmx::config::USART0_PORT].State) { case TxRxState::DMXINTER: - _gpio_mode_output(USART0_GPIO_PORT, USART0_TX_PIN); - GPIO_BC(USART0_GPIO_PORT) = USART0_TX_PIN; + gd32_gpio_mode_output(); + GPIO_BC(USART0_GPIOx) = USART0_TX_GPIO_PINx; s_TxBuffer[dmx::config::USART0_PORT].State = TxRxState::BREAK; - timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_0, TIMER_CNT(TIMER1) + s_nDmxTransmitBreakTime); + TIMER_CH0CV(TIMER1) = TIMER_CNT(TIMER1) + s_nDmxTransmit.nBreakTime; break; case TxRxState::BREAK: - _gpio_mode_af(USART0_GPIO_PORT, USART0_TX_PIN, USART0); + gd32_gpio_mode_af(); s_TxBuffer[dmx::config::USART0_PORT].State = TxRxState::MAB; - timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_0, TIMER_CNT(TIMER1) + s_nDmxTransmitMabTime); + TIMER_CH0CV(TIMER1) = TIMER_CNT(TIMER1) + s_nDmxTransmit.nMabTime; break; case TxRxState::MAB: { - uint32_t dmaCHCTL = DMA_CHCTL(USART0_DMA, USART0_TX_DMA_CH); + uint32_t dmaCHCTL = DMA_CHCTL(USART0_DMAx, USART0_TX_DMA_CHx); dmaCHCTL &= ~DMA_CHXCTL_CHEN; - DMA_CHCTL(USART0_DMA, USART0_TX_DMA_CH) = dmaCHCTL; - dma_interrupt_flag_clear(USART0_DMA, USART0_TX_DMA_CH, DMA_INTF_FTFIF); + DMA_CHCTL(USART0_DMAx, USART0_TX_DMA_CHx) = dmaCHCTL; + gd32_dma_interrupt_flag_clear(); const auto *p = &s_TxBuffer[dmx::config::USART0_PORT].dmx; - DMA_CHMADDR(USART0_DMA, USART0_TX_DMA_CH) = (uint32_t) p->data; - DMA_CHCNT(USART0_DMA, USART0_TX_DMA_CH) = (p->nLength & DMA_CHXCNT_CNT); + DMA_CHMADDR(USART0_DMAx, USART0_TX_DMA_CHx) = (uint32_t) p->data; + DMA_CHCNT(USART0_DMAx, USART0_TX_DMA_CHx) = (p->nLength & DMA_CHXCNT_CNT); dmaCHCTL |= DMA_CHXCTL_CHEN; dmaCHCTL |= DMA_INTERRUPT_ENABLE; - DMA_CHCTL(USART0_DMA, USART0_TX_DMA_CH) = dmaCHCTL; - usart_dma_transmit_config(USART0, USART_DENT_ENABLE); + DMA_CHCTL(USART0_DMAx, USART0_TX_DMA_CHx) = dmaCHCTL; + USART_CTL2(USART0) |= USART_TRANSMIT_DMA_ENABLE; } - break; + break; default: break; } - timer_interrupt_flag_clear(TIMER1, TIMER_INT_FLAG_CH0); - return; + TIMER_INTF(TIMER1) = static_cast(~TIMER_INT_FLAG_CH0); } #endif /* @@ -945,36 +809,35 @@ void TIMER1_IRQHandler() { if ((TIMER_INTF(TIMER1) & TIMER_INT_FLAG_CH1) == TIMER_INT_FLAG_CH1) { switch (s_TxBuffer[dmx::config::USART1_PORT].State) { case TxRxState::DMXINTER: - _gpio_mode_output(USART1_GPIO_PORT, USART1_TX_PIN); - GPIO_BC(USART1_GPIO_PORT) = USART1_TX_PIN; + gd32_gpio_mode_output(); + GPIO_BC(USART1_GPIOx) = USART1_TX_GPIO_PINx; s_TxBuffer[dmx::config::USART1_PORT].State = TxRxState::BREAK; - timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, TIMER_CNT(TIMER1) + s_nDmxTransmitBreakTime); + TIMER_CH1CV(TIMER1) = TIMER_CNT(TIMER1) + s_nDmxTransmit.nBreakTime; break; case TxRxState::BREAK: - _gpio_mode_af(USART1_GPIO_PORT, USART1_TX_PIN, USART1); + gd32_gpio_mode_af(); s_TxBuffer[dmx::config::USART1_PORT].State = TxRxState::MAB; - timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, TIMER_CNT(TIMER1) + s_nDmxTransmitMabTime); + TIMER_CH1CV(TIMER1) = TIMER_CNT(TIMER1) + s_nDmxTransmit.nMabTime; break; case TxRxState::MAB: { - uint32_t dmaCHCTL = DMA_CHCTL(USART1_DMA, USART1_TX_DMA_CH); + uint32_t dmaCHCTL = DMA_CHCTL(USART1_DMAx, USART1_TX_DMA_CHx); dmaCHCTL &= ~DMA_CHXCTL_CHEN; - DMA_CHCTL(USART1_DMA, USART1_TX_DMA_CH) = dmaCHCTL; - dma_interrupt_flag_clear(USART1_DMA, USART1_TX_DMA_CH, DMA_INTF_FTFIF); + DMA_CHCTL(USART1_DMAx, USART1_TX_DMA_CHx) = dmaCHCTL; + gd32_dma_interrupt_flag_clear(); const auto *p = &s_TxBuffer[dmx::config::USART1_PORT].dmx; - DMA_CHMADDR(USART1_DMA, USART1_TX_DMA_CH) = (uint32_t) p->data; - DMA_CHCNT(USART1_DMA, USART1_TX_DMA_CH) = (p->nLength & DMA_CHXCNT_CNT); + DMA_CHMADDR(USART1_DMAx, USART1_TX_DMA_CHx) = (uint32_t) p->data; + DMA_CHCNT(USART1_DMAx, USART1_TX_DMA_CHx) = (p->nLength & DMA_CHXCNT_CNT); dmaCHCTL |= DMA_CHXCTL_CHEN; dmaCHCTL |= DMA_INTERRUPT_ENABLE; - DMA_CHCTL(USART1_DMA, USART1_TX_DMA_CH) = dmaCHCTL; - usart_dma_transmit_config(USART1, USART_DENT_ENABLE); + DMA_CHCTL(USART1_DMAx, USART1_TX_DMA_CHx) = dmaCHCTL; + USART_CTL2(USART1) |= USART_TRANSMIT_DMA_ENABLE; } - break; + break; default: break; } - timer_interrupt_flag_clear(TIMER1, TIMER_INT_FLAG_CH1); - return; + TIMER_INTF(TIMER1) = static_cast(~TIMER_INT_FLAG_CH1); } #endif /* @@ -984,39 +847,35 @@ void TIMER1_IRQHandler() { if ((TIMER_INTF(TIMER1) & TIMER_INT_FLAG_CH2) == TIMER_INT_FLAG_CH2) { switch (s_TxBuffer[dmx::config::USART2_PORT].State) { case TxRxState::DMXINTER: - _gpio_mode_output(USART2_GPIO_PORT, USART2_TX_PIN); - GPIO_BC(USART2_GPIO_PORT) = USART2_TX_PIN; - timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_2, TIMER_CNT(TIMER1) + s_nDmxTransmitBreakTime); + gd32_gpio_mode_output(); + GPIO_BC(USART2_GPIOx) = USART2_TX_GPIO_PINx; s_TxBuffer[dmx::config::USART2_PORT].State = TxRxState::BREAK; + TIMER_CH2CV(TIMER1) = TIMER_CNT(TIMER1) + s_nDmxTransmit.nBreakTime; break; case TxRxState::BREAK: - _gpio_mode_af(USART2_GPIO_PORT, USART2_TX_PIN, USART2); - timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_2, TIMER_CNT(TIMER1) + s_nDmxTransmitMabTime); + gd32_gpio_mode_af(); s_TxBuffer[dmx::config::USART2_PORT].State = TxRxState::MAB; + TIMER_CH2CV(TIMER1) = TIMER_CNT(TIMER1) + s_nDmxTransmit.nMabTime; break; case TxRxState::MAB: { - uint32_t dmaCHCTL = DMA_CHCTL(USART2_DMA, USART2_TX_DMA_CH); + uint32_t dmaCHCTL = DMA_CHCTL(USART2_DMAx, USART2_TX_DMA_CHx); dmaCHCTL &= ~DMA_CHXCTL_CHEN; - DMA_CHCTL(USART2_DMA, USART2_TX_DMA_CH) = dmaCHCTL; + DMA_CHCTL(USART2_DMAx, USART2_TX_DMA_CHx) = dmaCHCTL; + gd32_dma_interrupt_flag_clear(); const auto *p = &s_TxBuffer[dmx::config::USART2_PORT].dmx; - DMA_CHMADDR(USART2_DMA, USART2_TX_DMA_CH) = (uint32_t) p->data; - DMA_CHCNT(USART2_DMA, USART2_TX_DMA_CH) = (p->nLength & DMA_CHXCNT_CNT); + DMA_CHMADDR(USART2_DMAx, USART2_TX_DMA_CHx) = (uint32_t) p->data; + DMA_CHCNT(USART2_DMAx, USART2_TX_DMA_CHx) = (p->nLength & DMA_CHXCNT_CNT); dmaCHCTL |= DMA_CHXCTL_CHEN; dmaCHCTL |= DMA_INTERRUPT_ENABLE; - DMA_CHCTL(USART2_DMA, USART2_TX_DMA_CH) = dmaCHCTL; - usart_dma_transmit_config(USART2, USART_DENT_ENABLE); - s_TxBuffer[dmx::config::USART2_PORT].State = TxRxState::DMXDATA; + DMA_CHCTL(USART2_DMAx, USART2_TX_DMA_CHx) = dmaCHCTL; + USART_CTL2(USART2) |= USART_TRANSMIT_DMA_ENABLE; } - break; - case TxRxState::DMXDATA: - console_error("DMXDATA:USART2"); - break; + break; default: break; } - timer_interrupt_flag_clear(TIMER1, TIMER_INT_FLAG_CH2); - return; + TIMER_INTF(TIMER1) = static_cast(~TIMER_INT_FLAG_CH2); } #endif /* @@ -1026,38 +885,39 @@ void TIMER1_IRQHandler() { if ((TIMER_INTF(TIMER1) & TIMER_INT_FLAG_CH3) == TIMER_INT_FLAG_CH3) { switch (s_TxBuffer[dmx::config::UART3_PORT].State) { case TxRxState::DMXINTER: - _gpio_mode_output(UART3_GPIO_PORT, UART3_TX_PIN); - GPIO_BC(UART3_GPIO_PORT) = UART3_TX_PIN; + gd32_gpio_mode_output(); + GPIO_BC(UART3_GPIOx) = UART3_TX_GPIO_PINx; s_TxBuffer[dmx::config::UART3_PORT].State = TxRxState::BREAK; - timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_3, TIMER_CNT(TIMER1) + s_nDmxTransmitBreakTime); + TIMER_CH3CV(TIMER1) = TIMER_CNT(TIMER1) + s_nDmxTransmit.nBreakTime; break; case TxRxState::BREAK: - _gpio_mode_af(UART3_GPIO_PORT, UART3_TX_PIN, UART3); + gd32_gpio_mode_af(); s_TxBuffer[dmx::config::UART3_PORT].State = TxRxState::MAB; - timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_3, TIMER_CNT(TIMER1) + s_nDmxTransmitMabTime); + TIMER_CH3CV(TIMER1) = TIMER_CNT(TIMER1) + s_nDmxTransmit.nMabTime; break; case TxRxState::MAB: { - uint32_t dmaCHCTL = DMA_CHCTL(UART3_DMA, UART3_TX_DMA_CH); + uint32_t dmaCHCTL = DMA_CHCTL(UART3_DMAx, UART3_TX_DMA_CHx); dmaCHCTL &= ~DMA_CHXCTL_CHEN; - DMA_CHCTL(UART3_DMA, UART3_TX_DMA_CH) = dmaCHCTL; - dma_interrupt_flag_clear(UART3_DMA, UART3_TX_DMA_CH, DMA_INTF_FTFIF); + DMA_CHCTL(UART3_DMAx, UART3_TX_DMA_CHx) = dmaCHCTL; + gd32_dma_interrupt_flag_clear(); const auto *p = &s_TxBuffer[dmx::config::UART3_PORT].dmx; - DMA_CHMADDR(UART3_DMA, UART3_TX_DMA_CH) = (uint32_t) p->data; - DMA_CHCNT(UART3_DMA, UART3_TX_DMA_CH) = (p->nLength & DMA_CHXCNT_CNT); + DMA_CHMADDR(UART3_DMAx, UART3_TX_DMA_CHx) = (uint32_t) p->data; + DMA_CHCNT(UART3_DMAx, UART3_TX_DMA_CHx) = (p->nLength & DMA_CHXCNT_CNT); dmaCHCTL |= DMA_CHXCTL_CHEN; dmaCHCTL |= DMA_INTERRUPT_ENABLE; - DMA_CHCTL(UART3_DMA, UART3_TX_DMA_CH) = dmaCHCTL; - usart_dma_transmit_config(UART3, USART_DENT_ENABLE); + DMA_CHCTL(UART3_DMAx, UART3_TX_DMA_CHx) = dmaCHCTL; + USART_CTL2(UART3) |= USART_TRANSMIT_DMA_ENABLE; } - break; + break; default: break; } - timer_interrupt_flag_clear(TIMER1, TIMER_INT_FLAG_CH3); - return; + TIMER_INTF(TIMER1) = static_cast(~TIMER_INT_FLAG_CH3); } #endif + // Clear all remaining interrupt flags (safety measure) + TIMER_INTF(TIMER1) = static_cast(~0); } void TIMER4_IRQHandler() { @@ -1068,35 +928,35 @@ void TIMER4_IRQHandler() { if ((TIMER_INTF(TIMER4) & TIMER_INT_FLAG_CH0) == TIMER_INT_FLAG_CH0) { switch (s_TxBuffer[dmx::config::UART4_PORT].State) { case TxRxState::DMXINTER: - _gpio_mode_output(UART4_GPIO_TX_PORT, UART4_TX_PIN); - GPIO_BC(UART4_GPIO_TX_PORT) = UART4_TX_PIN; + gd32_gpio_mode_output(); + GPIO_BC(UART4_TX_GPIOx) = UART4_TX_GPIO_PINx; s_TxBuffer[dmx::config::UART4_PORT].State = TxRxState::BREAK; - timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_0, TIMER_CNT(TIMER4) + s_nDmxTransmitBreakTime); + TIMER_CH0CV(TIMER4) = TIMER_CNT(TIMER4) + s_nDmxTransmit.nBreakTime; break; case TxRxState::BREAK: - _gpio_mode_af(UART4_GPIO_TX_PORT, UART4_TX_PIN, UART4); + gd32_gpio_mode_af(); s_TxBuffer[dmx::config::UART4_PORT].State = TxRxState::MAB; - timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_0, TIMER_CNT(TIMER4) + s_nDmxTransmitMabTime); + TIMER_CH0CV(TIMER4) = TIMER_CNT(TIMER4) + s_nDmxTransmit.nMabTime; break; case TxRxState::MAB: { - uint32_t dmaCHCTL = DMA_CHCTL(UART4_DMA, UART4_TX_DMA_CH); + uint32_t dmaCHCTL = DMA_CHCTL(UART4_DMAx, UART4_TX_DMA_CHx); dmaCHCTL &= ~DMA_CHXCTL_CHEN; - DMA_CHCTL(UART4_DMA, UART4_TX_DMA_CH) = dmaCHCTL; + DMA_CHCTL(UART4_DMAx, UART4_TX_DMA_CHx) = dmaCHCTL; + gd32_dma_interrupt_flag_clear(); const auto *p = &s_TxBuffer[dmx::config::UART4_PORT].dmx; - DMA_CHMADDR(UART4_DMA, UART4_TX_DMA_CH) = (uint32_t) p->data; - DMA_CHCNT(UART4_DMA, UART4_TX_DMA_CH) = (p->nLength & DMA_CHXCNT_CNT); + DMA_CHMADDR(UART4_DMAx, UART4_TX_DMA_CHx) = (uint32_t) p->data; + DMA_CHCNT(UART4_DMAx, UART4_TX_DMA_CHx) = (p->nLength & DMA_CHXCNT_CNT); dmaCHCTL |= DMA_CHXCTL_CHEN; dmaCHCTL |= DMA_INTERRUPT_ENABLE; - DMA_CHCTL(UART4_DMA, UART4_TX_DMA_CH) = dmaCHCTL; - usart_dma_transmit_config(UART4, USART_DENT_ENABLE); + DMA_CHCTL(UART4_DMAx, UART4_TX_DMA_CHx) = dmaCHCTL; + USART_CTL2(UART4) |= USART_TRANSMIT_DMA_ENABLE; } - break; + break; default: break; } - timer_interrupt_flag_clear(TIMER4, TIMER_INT_FLAG_CH0); - return; + TIMER_INTF(TIMER4) = static_cast(~TIMER_INT_FLAG_CH0); } #endif /* @@ -1106,35 +966,35 @@ void TIMER4_IRQHandler() { if ((TIMER_INTF(TIMER4) & TIMER_INT_FLAG_CH1) == TIMER_INT_FLAG_CH1) { switch (s_TxBuffer[dmx::config::USART5_PORT].State) { case TxRxState::DMXINTER: - _gpio_mode_output(USART5_GPIO_PORT, USART5_TX_PIN); - GPIO_BC(USART5_GPIO_PORT) = USART5_TX_PIN; + gd32_gpio_mode_output(); + GPIO_BC(USART5_GPIOx) = USART5_TX_GPIO_PINx; s_TxBuffer[dmx::config::USART5_PORT].State = TxRxState::BREAK; - timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_1, TIMER_CNT(TIMER4) + s_nDmxTransmitBreakTime); + TIMER_CH1CV(TIMER4) = TIMER_CNT(TIMER4) + s_nDmxTransmit.nBreakTime; break; case TxRxState::BREAK: - _gpio_mode_af(USART5_GPIO_PORT, USART5_TX_PIN, USART5); + gd32_gpio_mode_af(); s_TxBuffer[dmx::config::USART5_PORT].State = TxRxState::MAB; - timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_1, TIMER_CNT(TIMER4) + s_nDmxTransmitMabTime); + TIMER_CH1CV(TIMER4) = TIMER_CNT(TIMER4) + s_nDmxTransmit.nMabTime; break; case TxRxState::MAB: { - uint32_t dmaCHCTL = DMA_CHCTL(USART5_DMA, USART5_TX_DMA_CH); + uint32_t dmaCHCTL = DMA_CHCTL(USART5_DMAx, USART5_TX_DMA_CHx); dmaCHCTL &= ~DMA_CHXCTL_CHEN; - DMA_CHCTL(USART5_DMA, USART5_TX_DMA_CH) = dmaCHCTL; + DMA_CHCTL(USART5_DMAx, USART5_TX_DMA_CHx) = dmaCHCTL; + gd32_dma_interrupt_flag_clear(); const auto *p = &s_TxBuffer[dmx::config::USART5_PORT].dmx; - DMA_CHMADDR(USART5_DMA, USART5_TX_DMA_CH) = (uint32_t) p->data; - DMA_CHCNT(USART5_DMA, USART5_TX_DMA_CH) = (p->nLength & DMA_CHXCNT_CNT); + DMA_CHMADDR(USART5_DMAx, USART5_TX_DMA_CHx) = (uint32_t) p->data; + DMA_CHCNT(USART5_DMAx, USART5_TX_DMA_CHx) = (p->nLength & DMA_CHXCNT_CNT); dmaCHCTL |= DMA_CHXCTL_CHEN; dmaCHCTL |= DMA_INTERRUPT_ENABLE; - DMA_CHCTL(USART5_DMA, USART5_TX_DMA_CH) = dmaCHCTL; - usart_dma_transmit_config(USART5, USART_DENT_ENABLE); + DMA_CHCTL(USART5_DMAx, USART5_TX_DMA_CHx) = dmaCHCTL; + USART_CTL2(USART5) |= USART_TRANSMIT_DMA_ENABLE; } - break; + break; default: break; } - timer_interrupt_flag_clear(TIMER4, TIMER_INT_FLAG_CH1); - return; + TIMER_INTF(TIMER4) = static_cast(~TIMER_INT_FLAG_CH1); } #endif /* @@ -1144,36 +1004,35 @@ void TIMER4_IRQHandler() { if ((TIMER_INTF(TIMER4) & TIMER_INT_FLAG_CH2) == TIMER_INT_FLAG_CH2) { switch (s_TxBuffer[dmx::config::UART6_PORT].State) { case TxRxState::DMXINTER: - _gpio_mode_output(UART6_GPIO_PORT, UART6_TX_PIN); - GPIO_BC(UART6_GPIO_PORT) = UART6_TX_PIN; + gd32_gpio_mode_output(); + GPIO_BC(UART6_GPIOx) = UART6_TX_GPIO_PINx; s_TxBuffer[dmx::config::UART6_PORT].State = TxRxState::BREAK; - timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_2, TIMER_CNT(TIMER4) + s_nDmxTransmitBreakTime); + TIMER_CH2CV(TIMER4) = TIMER_CNT(TIMER4) + s_nDmxTransmit.nBreakTime; break; case TxRxState::BREAK: - _gpio_mode_af(UART6_GPIO_PORT, UART6_TX_PIN, UART6); + gd32_gpio_mode_af(); s_TxBuffer[dmx::config::UART6_PORT].State = TxRxState::MAB; - timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_2, TIMER_CNT(TIMER4) + s_nDmxTransmitMabTime); + TIMER_CH2CV(TIMER4) = TIMER_CNT(TIMER4) + s_nDmxTransmit.nMabTime; break; case TxRxState::MAB: { - uint32_t dmaCHCTL = DMA_CHCTL(UART6_DMA, UART6_TX_DMA_CH); + uint32_t dmaCHCTL = DMA_CHCTL(UART6_DMAx, UART6_TX_DMA_CHx); dmaCHCTL &= ~DMA_CHXCTL_CHEN; - DMA_CHCTL(UART6_DMA, UART6_TX_DMA_CH)= dmaCHCTL; - dma_interrupt_flag_clear(UART6_DMA, UART6_TX_DMA_CH, DMA_INTF_FTFIF); + DMA_CHCTL(UART6_DMAx, UART6_TX_DMA_CHx)= dmaCHCTL; + gd32_dma_interrupt_flag_clear(); const auto *p = &s_TxBuffer[dmx::config::UART6_PORT].dmx; - DMA_CHMADDR(UART6_DMA, UART6_TX_DMA_CH) = (uint32_t) p->data; - DMA_CHCNT(UART6_DMA, UART6_TX_DMA_CH) = (p->nLength & DMA_CHXCNT_CNT); + DMA_CHMADDR(UART6_DMAx, UART6_TX_DMA_CHx) = (uint32_t) p->data; + DMA_CHCNT(UART6_DMAx, UART6_TX_DMA_CHx) = (p->nLength & DMA_CHXCNT_CNT); dmaCHCTL |= DMA_CHXCTL_CHEN; dmaCHCTL |= DMA_INTERRUPT_ENABLE; - DMA_CHCTL(UART6_DMA, UART6_TX_DMA_CH)= dmaCHCTL; - usart_dma_transmit_config(UART6, USART_DENT_ENABLE); + DMA_CHCTL(UART6_DMAx, UART6_TX_DMA_CHx)= dmaCHCTL; + USART_CTL2(UART6) |= USART_TRANSMIT_DMA_ENABLE; } - break; + break; default: break; } - timer_interrupt_flag_clear(TIMER4, TIMER_INT_FLAG_CH2); - return; + TIMER_INTF(TIMER4) = static_cast(~TIMER_INT_FLAG_CH2); } #endif /* @@ -1183,184 +1042,102 @@ void TIMER4_IRQHandler() { if ((TIMER_INTF(TIMER4) & TIMER_INT_FLAG_CH3) == TIMER_INT_FLAG_CH3) { switch (s_TxBuffer[dmx::config::UART7_PORT].State) { case TxRxState::DMXINTER: - _gpio_mode_output(UART7_GPIO_PORT, UART7_TX_PIN); - GPIO_BC(UART7_GPIO_PORT) = UART7_TX_PIN; + gd32_gpio_mode_output(); + GPIO_BC(UART7_GPIOx) = UART7_TX_GPIO_PINx; s_TxBuffer[dmx::config::UART7_PORT].State = TxRxState::BREAK; - timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_2, TIMER_CNT(TIMER4) + s_nDmxTransmitBreakTime); + TIMER_CH3CV(TIMER4) = TIMER_CNT(TIMER4) + s_nDmxTransmit.nBreakTime; break; case TxRxState::BREAK: - _gpio_mode_af(UART7_GPIO_PORT, UART7_TX_PIN, UART7); + gd32_gpio_mode_af(); s_TxBuffer[dmx::config::UART7_PORT].State = TxRxState::MAB; - timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_2, TIMER_CNT(TIMER4) + s_nDmxTransmitMabTime); + TIMER_CH3CV(TIMER4) = TIMER_CNT(TIMER4) + s_nDmxTransmit.nMabTime; break; case TxRxState::MAB: { - uint32_t dmaCHCTL = DMA_CHCTL(UART7_DMA, UART7_TX_DMA_CH); + uint32_t dmaCHCTL = DMA_CHCTL(UART7_DMAx, UART7_TX_DMA_CHx); dmaCHCTL &= ~DMA_CHXCTL_CHEN; - DMA_CHCTL(UART7_DMA, UART7_TX_DMA_CH) = dmaCHCTL; - dma_interrupt_flag_clear(UART7_DMA, UART7_TX_DMA_CH, DMA_INTF_FTFIF); + DMA_CHCTL(UART7_DMAx, UART7_TX_DMA_CHx) = dmaCHCTL; + gd32_dma_interrupt_flag_clear(); const auto *p = &s_TxBuffer[dmx::config::UART7_PORT].dmx; - DMA_CHMADDR(UART7_DMA, UART7_TX_DMA_CH) = (uint32_t) p->data; - DMA_CHCNT(UART7_DMA, UART7_TX_DMA_CH) = (p->nLength & DMA_CHXCNT_CNT); + DMA_CHMADDR(UART7_DMAx, UART7_TX_DMA_CHx) = (uint32_t) p->data; + DMA_CHCNT(UART7_DMAx, UART7_TX_DMA_CHx) = (p->nLength & DMA_CHXCNT_CNT); dmaCHCTL |= DMA_CHXCTL_CHEN; dmaCHCTL |= DMA_INTERRUPT_ENABLE; - usart_dma_transmit_config(UART7, USART_DENT_ENABLE); + DMA_CHCTL(UART7_DMAx, UART7_TX_DMA_CHx)= dmaCHCTL; + USART_CTL2(UART7) |= USART_TRANSMIT_DMA_ENABLE; } - break; + break; default: break; } - timer_interrupt_flag_clear(TIMER4, TIMER_INT_FLAG_CH3); - return; + TIMER_INTF(TIMER4) = static_cast(~TIMER_INT_FLAG_CH3); } #endif + // Clear all remaining interrupt flags (safety measure) + TIMER_INTF(TIMER4) = static_cast(~0); } -#if !defined(CONFIG_DMX_TRANSMIT_ONLY) -void TIMER2_IRQHandler() { - const auto nIntFlag = TIMER_INTF(TIMER2); - - if ((nIntFlag & TIMER_INT_FLAG_CH0) == TIMER_INT_FLAG_CH0) { - if (s_RxBuffer[0].State == TxRxState::DMXDATA) { - s_RxBuffer[0].State = TxRxState::IDLE; - s_RxBuffer[0].Dmx.nSlotsInPacket |= 0x8000; - } else if (s_RxBuffer[0].State == TxRxState::RDMDISC) { - s_RxBuffer[0].State = TxRxState::IDLE; - s_RxBuffer[0].Dmx.nSlotsInPacket |= 0x4000; - } - } -#if DMX_MAX_PORTS >= 2 - else if ((nIntFlag & TIMER_INT_FLAG_CH1) == TIMER_INT_FLAG_CH1) { - if (s_RxBuffer[1].State == TxRxState::DMXDATA) { - s_RxBuffer[1].State = TxRxState::IDLE; - s_RxBuffer[1].Dmx.nSlotsInPacket |= 0x8000; - } else if (s_RxBuffer[1].State == TxRxState::RDMDISC) { - s_RxBuffer[1].State = TxRxState::IDLE; - s_RxBuffer[1].Dmx.nSlotsInPacket |= 0x4000; - } - } -#endif -#if DMX_MAX_PORTS >= 3 - else if ((nIntFlag & TIMER_INT_FLAG_CH2) == TIMER_INT_FLAG_CH2) { - if (s_RxBuffer[2].State == TxRxState::DMXDATA) { - s_RxBuffer[2].State = TxRxState::IDLE; - s_RxBuffer[2].Dmx.nSlotsInPacket |= 0x8000; - } else if (s_RxBuffer[2].State == TxRxState::RDMDISC) { - s_RxBuffer[2].State = TxRxState::IDLE; - s_RxBuffer[2].Dmx.nSlotsInPacket |= 0x4000; - } - } -#endif -#if DMX_MAX_PORTS >= 4 - else if ((nIntFlag & TIMER_INT_FLAG_CH3) == TIMER_INT_FLAG_CH3) { - if (s_RxBuffer[3].State == TxRxState::DMXDATA) { - s_RxBuffer[3].State = TxRxState::IDLE; - s_RxBuffer[3].Dmx.nSlotsInPacket |= 0x8000; - } else if (s_RxBuffer[3].State == TxRxState::RDMDISC) { - s_RxBuffer[3].State = TxRxState::IDLE; - s_RxBuffer[3].Dmx.nSlotsInPacket |= 0x4000; - } - } -#endif - timer_interrupt_flag_clear(TIMER2, nIntFlag); -} +void TIMER6_IRQHandler() { + const auto nIntFlag = TIMER_INTF(TIMER6); -void TIMER3_IRQHandler() { - const auto nIntFlag = TIMER_INTF(TIMER3); -#if DMX_MAX_PORTS >= 5 - if ((nIntFlag & TIMER_INT_FLAG_CH0) == TIMER_INT_FLAG_CH0) { - if (s_RxBuffer[4].State == TxRxState::DMXDATA) { - s_RxBuffer[4].State = TxRxState::IDLE; - s_RxBuffer[4].Dmx.nSlotsInPacket |= 0x8000; - } else if (s_RxBuffer[4].State == TxRxState::RDMDISC) { - s_RxBuffer[4].State = TxRxState::IDLE; - s_RxBuffer[4].Dmx.nSlotsInPacket |= 0x4000; - } - } -# if DMX_MAX_PORTS >= 6 - else if ((nIntFlag & TIMER_INT_FLAG_CH1) == TIMER_INT_FLAG_CH1) { - if (s_RxBuffer[5].State == TxRxState::DMXDATA) { - s_RxBuffer[5].State = TxRxState::IDLE; - s_RxBuffer[5].Dmx.nSlotsInPacket |= 0x8000; - } else if (s_RxBuffer[5].State == TxRxState::RDMDISC) { - s_RxBuffer[5].State = TxRxState::IDLE; - s_RxBuffer[5].Dmx.nSlotsInPacket |= 0x4000; - } - } -# endif -# if DMX_MAX_PORTS >= 7 - else if ((nIntFlag & TIMER_INT_FLAG_CH2) == TIMER_INT_FLAG_CH2) { - if (s_RxBuffer[6].State == TxRxState::DMXDATA) { - s_RxBuffer[6].State = TxRxState::IDLE; - s_RxBuffer[6].Dmx.nSlotsInPacket |= 0x8000; - } else if (s_RxBuffer[6].State == TxRxState::RDMDISC) { - s_RxBuffer[6].State = TxRxState::IDLE; - s_RxBuffer[6].Dmx.nSlotsInPacket |= 0x4000; - } - } -# endif -# if DMX_MAX_PORTS == 8 - else if ((nIntFlag & TIMER_INT_FLAG_CH3) == TIMER_INT_FLAG_CH3) { - if (s_RxBuffer[7].State == TxRxState::DMXDATA) { - s_RxBuffer[7].State = TxRxState::IDLE; - s_RxBuffer[7].Dmx.nSlotsInPacket |= 0x8000; - } else if (s_RxBuffer[7].State == TxRxState::RDMDISC) { - s_RxBuffer[7].State = TxRxState::IDLE; - s_RxBuffer[7].Dmx.nSlotsInPacket |= 0x4000; + if ((nIntFlag & TIMER_INT_FLAG_UP) == TIMER_INT_FLAG_UP) { +#if !defined(CONFIG_DMX_TRANSMIT_ONLY) + for (uint32_t i = 0; i < DMX_MAX_PORTS; i++) { + auto &packet = sv_nRxDmxPackets[i]; + packet.nPerSecond = sv_nRxDmxPackets[i].nCount - packet.nCountPrevious; + packet.nCountPrevious = packet.nCount; } - } -# endif #endif - timer_interrupt_flag_clear(TIMER3, nIntFlag); -} - -void TIMER6_IRQHandler() { - for (auto i = 0; i < DMX_MAX_PORTS; i++) { - sv_nRxDmxPackets[i].nPerSecond = sv_nRxDmxPackets[i].nCount - sv_nRxDmxPackets[i].nCountPrevious; - sv_nRxDmxPackets[i].nCountPrevious = sv_nRxDmxPackets[i].nCount; + g_Seconds.nUptime++; } - timer_interrupt_flag_clear(TIMER6, TIMER_INT_FLAG_UP); + // Clear all remaining interrupt flags (safety measure) + TIMER_INTF(TIMER6) = static_cast(~nIntFlag); } -#endif } -#include - extern "C" { /* * USART 0 */ #if defined (DMX_USE_USART0) -# if !defined (GD32F4XX) -void DMA0_Channel3_IRQHandler() { - if (dma_interrupt_flag_get(DMA0, DMA_CH3, DMA_INTERRUPT_FLAG_GET) == SET) { - dma_interrupt_disable(DMA0, DMA_CH3, DMA_INTERRUPT_DISABLE); +# if defined (GD32F4XX) || defined (GD32H7XX) +void DMA1_Channel7_IRQHandler() { + if (gd32_dma_interrupt_flag_get()) { + gd32_dma_interrupt_disable(); if (s_TxBuffer[dmx::config::USART0_PORT].outputStyle == dmx::OutputStyle::DELTA) { s_TxBuffer[dmx::config::USART0_PORT].State = TxRxState::IDLE; } else { - timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_0 , TIMER_CNT(TIMER1) + s_nDmxTransmitInterTime); + timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_0 , TIMER_CNT(TIMER1) + s_nDmxTransmit.nInterTime); s_TxBuffer[dmx::config::USART0_PORT].State = TxRxState::DMXINTER; } + +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) + sv_TotalStatistics[dmx::config::USART0_PORT].Dmx.Sent++; +#endif } - dma_interrupt_flag_clear(DMA0, DMA_CH3, DMA_INTERRUPT_FLAG_CLEAR); + gd32_dma_interrupt_flag_clear(); } # else -void DMA1_Channel7_IRQHandler() { - if (dma_interrupt_flag_get(DMA1, DMA_CH7, DMA_INTERRUPT_FLAG_GET) == SET) { - dma_interrupt_disable(DMA1, DMA_CH7, DMA_INTERRUPT_DISABLE); +void DMA0_Channel3_IRQHandler() { + if (gd32_dma_interrupt_flag_get()) { + gd32_dma_interrupt_disable(); if (s_TxBuffer[dmx::config::USART0_PORT].outputStyle == dmx::OutputStyle::DELTA) { s_TxBuffer[dmx::config::USART0_PORT].State = TxRxState::IDLE; } else { - timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_0 , TIMER_CNT(TIMER1) + s_nDmxTransmitInterTime); + timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_0 , TIMER_CNT(TIMER1) + s_nDmxTransmit.nInterTime); s_TxBuffer[dmx::config::USART0_PORT].State = TxRxState::DMXINTER; } + +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) + sv_TotalStatistics[dmx::config::USART0_PORT].Dmx.Sent++; +#endif } - dma_interrupt_flag_clear(DMA1, DMA_CH7, DMA_INTERRUPT_FLAG_CLEAR); + gd32_dma_interrupt_flag_clear(); } # endif #endif @@ -1369,55 +1146,65 @@ void DMA1_Channel7_IRQHandler() { */ #if defined (DMX_USE_USART1) void DMA0_Channel6_IRQHandler() { - if (dma_interrupt_flag_get(DMA0, DMA_CH6, DMA_INTERRUPT_FLAG_GET) == SET) { - dma_interrupt_disable(DMA0, DMA_CH6, DMA_INTERRUPT_DISABLE); + if (gd32_dma_interrupt_flag_get()) { + gd32_dma_interrupt_disable(); if (s_TxBuffer[dmx::config::USART1_PORT].outputStyle == dmx::OutputStyle::DELTA) { s_TxBuffer[dmx::config::USART1_PORT].State = TxRxState::IDLE; } else { - timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1 , TIMER_CNT(TIMER1) + s_nDmxTransmitInterTime); + timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1 , TIMER_CNT(TIMER1) + s_nDmxTransmit.nInterTime); s_TxBuffer[dmx::config::USART1_PORT].State = TxRxState::DMXINTER; } + +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) + sv_TotalStatistics[dmx::config::USART1_PORT].Dmx.Sent++; +#endif } - dma_interrupt_flag_clear(DMA0, DMA_CH6, DMA_INTERRUPT_FLAG_CLEAR); + gd32_dma_interrupt_flag_clear(); } #endif /* * USART 2 */ #if defined (DMX_USE_USART2) -# if !defined (GD32F4XX) -void DMA0_Channel1_IRQHandler() { - if (dma_interrupt_flag_get(DMA0, DMA_CH1, DMA_INTERRUPT_FLAG_GET) == SET) { - dma_interrupt_disable(DMA0, DMA_CH1, DMA_INTERRUPT_DISABLE); - - usart_flag_clear(USART2, USART_FLAG_TC); +# if defined (GD32F4XX) || defined (GD32H7XX) +void DMA0_Channel3_IRQHandler() { + if (gd32_dma_interrupt_flag_get()) { + gd32_dma_interrupt_disable(); if (s_TxBuffer[dmx::config::USART2_PORT].outputStyle == dmx::OutputStyle::DELTA) { s_TxBuffer[dmx::config::USART2_PORT].State = TxRxState::IDLE; } else { - timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_2 , TIMER_CNT(TIMER1) + s_nDmxTransmitInterTime); + timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_2 , TIMER_CNT(TIMER1) + s_nDmxTransmit.nInterTime); s_TxBuffer[dmx::config::USART2_PORT].State = TxRxState::DMXINTER; } + +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) + sv_TotalStatistics[dmx::config::USART2_PORT].Dmx.Sent++; +#endif } - dma_interrupt_flag_clear(DMA0, DMA_CH1, DMA_INTERRUPT_FLAG_CLEAR); + gd32_dma_interrupt_flag_clear(); } # else -void DMA0_Channel3_IRQHandler() { - if (dma_interrupt_flag_get(DMA0, DMA_CH3, DMA_INTERRUPT_FLAG_GET) == SET) { - dma_interrupt_disable(DMA0, DMA_CH3, DMA_INTERRUPT_DISABLE); +void DMA0_Channel1_IRQHandler() { + if (gd32_dma_interrupt_flag_get()) { + gd32_dma_interrupt_disable(); if (s_TxBuffer[dmx::config::USART2_PORT].outputStyle == dmx::OutputStyle::DELTA) { s_TxBuffer[dmx::config::USART2_PORT].State = TxRxState::IDLE; } else { - timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_2 , TIMER_CNT(TIMER1) + s_nDmxTransmitInterTime); + timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_2 , TIMER_CNT(TIMER1) + s_nDmxTransmit.nInterTime); s_TxBuffer[dmx::config::USART2_PORT].State = TxRxState::DMXINTER; } + +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) + sv_TotalStatistics[dmx::config::USART2_PORT].Dmx.Sent++; +#endif } - dma_interrupt_flag_clear(DMA0, DMA_CH3, DMA_INTERRUPT_FLAG_CLEAR); + gd32_dma_interrupt_flag_clear(); } # endif #endif @@ -1425,36 +1212,43 @@ void DMA0_Channel3_IRQHandler() { * UART 3 */ #if defined (DMX_USE_UART3) -# if !defined (GD32F4XX) -void DMA1_Channel4_IRQHandler() { - if (dma_interrupt_flag_get(DMA1, DMA_CH4, DMA_INTERRUPT_FLAG_GET) == SET) { - dma_interrupt_disable(DMA1, DMA_CH4, DMA_INTERRUPT_DISABLE); +# if defined (GD32F4XX) || defined (GD32H7XX) +void DMA0_Channel4_IRQHandler() { + if (gd32_dma_interrupt_flag_get()) { + gd32_dma_interrupt_disable(); if (s_TxBuffer[dmx::config::UART3_PORT].outputStyle == dmx::OutputStyle::DELTA) { s_TxBuffer[dmx::config::UART3_PORT].State = TxRxState::IDLE; } else { - timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_3 , TIMER_CNT(TIMER1) + s_nDmxTransmitInterTime); + timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_3 , TIMER_CNT(TIMER4) + s_nDmxTransmit.nInterTime); s_TxBuffer[dmx::config::UART3_PORT].State = TxRxState::DMXINTER; } + +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) + sv_TotalStatistics[dmx::config::UART3_PORT].Dmx.Sent++; +#endif } - dma_interrupt_flag_clear(DMA1, DMA_CH4, DMA_INTERRUPT_FLAG_CLEAR); + gd32_dma_interrupt_flag_clear(); } -# endif -# if defined (GD32F4XX) -void DMA0_Channel4_IRQHandler() { - if (dma_interrupt_flag_get(DMA0, DMA_CH4, DMA_INTERRUPT_FLAG_GET) == SET) { - dma_interrupt_disable(DMA0, DMA_CH4, DMA_INTERRUPT_DISABLE); +# else +void DMA1_Channel4_IRQHandler() { + if (gd32_dma_interrupt_flag_get()) { + gd32_dma_interrupt_disable(); if (s_TxBuffer[dmx::config::UART3_PORT].outputStyle == dmx::OutputStyle::DELTA) { s_TxBuffer[dmx::config::UART3_PORT].State = TxRxState::IDLE; } else { - timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_3 , TIMER_CNT(TIMER4) + s_nDmxTransmitInterTime); + timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_3 , TIMER_CNT(TIMER1) + s_nDmxTransmit.nInterTime); s_TxBuffer[dmx::config::UART3_PORT].State = TxRxState::DMXINTER; } + +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) + sv_TotalStatistics[dmx::config::UART3_PORT].Dmx.Sent++; +#endif } - dma_interrupt_flag_clear(DMA0, DMA_CH4, DMA_INTERRUPT_FLAG_CLEAR); + gd32_dma_interrupt_flag_clear(); } # endif #endif @@ -1464,34 +1258,42 @@ void DMA0_Channel4_IRQHandler() { #if defined (DMX_USE_UART4) # if defined (GD32F20X) void DMA1_Channel3_IRQHandler() { - if (dma_interrupt_flag_get(DMA1, DMA_CH3, DMA_INTERRUPT_FLAG_GET) == SET) { - dma_interrupt_disable(DMA1, DMA_CH3, DMA_INTERRUPT_DISABLE); + if (gd32_dma_interrupt_flag_get()) { + gd32_dma_interrupt_disable(); if (s_TxBuffer[dmx::config::UART4_PORT].outputStyle == dmx::OutputStyle::DELTA) { s_TxBuffer[dmx::config::UART4_PORT].State = TxRxState::IDLE; } else { - timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_0 , TIMER_CNT(TIMER4) + s_nDmxTransmitInterTime); + timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_0 , TIMER_CNT(TIMER4) + s_nDmxTransmit.nInterTime); s_TxBuffer[dmx::config::UART4_PORT].State = TxRxState::DMXINTER; } + +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) + sv_TotalStatistics[dmx::config::UART4_PORT].Dmx.Sent++; +#endif } - dma_interrupt_flag_clear(DMA1, DMA_CH3, DMA_INTERRUPT_FLAG_CLEAR); + gd32_dma_interrupt_flag_clear(); } # endif -# if defined (GD32F4XX) +# if defined (GD32F4XX) || defined (GD32H7XX) void DMA0_Channel7_IRQHandler() { - if (dma_interrupt_flag_get(DMA0, DMA_CH7, DMA_INTERRUPT_FLAG_GET) == SET) { - dma_interrupt_disable(DMA0, DMA_CH7, DMA_INTERRUPT_DISABLE); + if (gd32_dma_interrupt_flag_get()) { + gd32_dma_interrupt_disable(); if (s_TxBuffer[dmx::config::UART4_PORT].outputStyle == dmx::OutputStyle::DELTA) { s_TxBuffer[dmx::config::UART4_PORT].State = TxRxState::IDLE; } else { - timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_0 , TIMER_CNT(TIMER4) + s_nDmxTransmitInterTime); + timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_0 , TIMER_CNT(TIMER4) + s_nDmxTransmit.nInterTime); s_TxBuffer[dmx::config::UART4_PORT].State = TxRxState::DMXINTER; } } - dma_interrupt_flag_clear(DMA0, DMA_CH7, DMA_INTERRUPT_FLAG_CLEAR); +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) + sv_TotalStatistics[dmx::config::UART4_PORT].Dmx.Sent++; +#endif + + gd32_dma_interrupt_flag_clear(); } # endif #endif @@ -1500,18 +1302,22 @@ void DMA0_Channel7_IRQHandler() { */ #if defined (DMX_USE_USART5) void DMA1_Channel6_IRQHandler() { - if (dma_interrupt_flag_get(DMA1, DMA_CH6, DMA_INTERRUPT_FLAG_GET) == SET) { - dma_interrupt_disable(DMA1, DMA_CH6, DMA_INTERRUPT_DISABLE); + if (gd32_dma_interrupt_flag_get()) { + gd32_dma_interrupt_disable(); if (s_TxBuffer[dmx::config::USART5_PORT].outputStyle == dmx::OutputStyle::DELTA) { s_TxBuffer[dmx::config::USART5_PORT].State = TxRxState::IDLE; } else { - timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_1 , TIMER_CNT(TIMER4) + s_nDmxTransmitInterTime); + timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_1 , TIMER_CNT(TIMER4) + s_nDmxTransmit.nInterTime); s_TxBuffer[dmx::config::USART5_PORT].State = TxRxState::DMXINTER; } + +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) + sv_TotalStatistics[dmx::config::USART5_PORT].Dmx.Sent++; +#endif } - dma_interrupt_flag_clear(DMA1, DMA_CH6, DMA_INTERRUPT_FLAG_CLEAR); + gd32_dma_interrupt_flag_clear(); } #endif /* @@ -1520,34 +1326,42 @@ void DMA1_Channel6_IRQHandler() { #if defined (DMX_USE_UART6) # if defined (GD32F20X) void DMA1_Channel4_IRQHandler() { - if (dma_interrupt_flag_get(DMA1, DMA_CH4, DMA_INTERRUPT_FLAG_GET) == SET) { - dma_interrupt_disable(DMA1, DMA_CH4, DMA_INTERRUPT_DISABLE); + if (gd32_dma_interrupt_flag_get()) { + gd32_dma_interrupt_disable(); if (s_TxBuffer[dmx::config::UART6_PORT].outputStyle == dmx::OutputStyle::DELTA) { s_TxBuffer[dmx::config::UART6_PORT].State = TxRxState::IDLE; } else { - timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_2 , TIMER_CNT(TIMER4) + s_nDmxTransmitInterTime); + timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_2 , TIMER_CNT(TIMER4) + s_nDmxTransmit.nInterTime); s_TxBuffer[dmx::config::UART6_PORT].State = TxRxState::DMXINTER; } + +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) + sv_TotalStatistics[dmx::config::UART6_PORT].Dmx.Sent++; +#endif } - dma_interrupt_flag_clear(DMA1, DMA_CH4, DMA_INTERRUPT_FLAG_CLEAR); + gd32_dma_interrupt_flag_clear(); } # endif -# if defined (GD32F4XX) +# if defined (GD32F4XX) || defined (GD32H7XX) void DMA0_Channel1_IRQHandler() { - if (dma_interrupt_flag_get(DMA0, DMA_CH1, DMA_INTERRUPT_FLAG_GET) == SET) { - dma_interrupt_disable(DMA0, DMA_CH1, DMA_INTERRUPT_DISABLE); + if (gd32_dma_interrupt_flag_get()) { + gd32_dma_interrupt_disable(); if (s_TxBuffer[dmx::config::UART6_PORT].outputStyle == dmx::OutputStyle::DELTA) { s_TxBuffer[dmx::config::UART6_PORT].State = TxRxState::IDLE; } else { - timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_2 , TIMER_CNT(TIMER4) + s_nDmxTransmitInterTime); + timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_2 , TIMER_CNT(TIMER4) + s_nDmxTransmit.nInterTime); s_TxBuffer[dmx::config::UART6_PORT].State = TxRxState::DMXINTER; } + +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) + sv_TotalStatistics[dmx::config::UART6_PORT].Dmx.Sent++; +#endif } - dma_interrupt_flag_clear(DMA0, DMA_CH1, DMA_INTERRUPT_FLAG_CLEAR); + gd32_dma_interrupt_flag_clear(); } # endif #endif @@ -1557,44 +1371,52 @@ void DMA0_Channel1_IRQHandler() { #if defined (DMX_USE_UART7) # if defined (GD32F20X) void DMA1_Channel3_IRQHandler() { - if (dma_interrupt_flag_get(DMA1, DMA_CH3, DMA_INTERRUPT_FLAG_GET) == SET) { - dma_interrupt_disable(DMA1, DMA_CH3, DMA_INTERRUPT_DISABLE); + if (gd32_dma_interrupt_flag_get()) { + gd32_dma_interrupt_disable(); if (s_TxBuffer[dmx::config::UART7_PORT].outputStyle == dmx::OutputStyle::DELTA) { s_TxBuffer[dmx::config::UART7_PORT].State = TxRxState::IDLE; } else { - timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_3 , TIMER_CNT(TIMER4) + s_nDmxTransmitInterTime); + timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_3 , TIMER_CNT(TIMER4) + s_nDmxTransmit.nInterTime); s_TxBuffer[dmx::config::UART7_PORT].State = TxRxState::DMXINTER; } + +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) + sv_TotalStatistics[dmx::config::UART7_PORT].Dmx.Sent++; +#endif } - dma_interrupt_flag_clear(DMA1, DMA_CH3, DMA_INTERRUPT_FLAG_CLEAR); + gd32_dma_interrupt_flag_clear(); } # endif -# if defined (GD32F4XX) +# if defined (GD32F4XX) || defined (GD32H7XX) void DMA0_Channel0_IRQHandler() { - if (dma_interrupt_flag_get(DMA0, DMA_CH0, DMA_INTERRUPT_FLAG_GET) == SET) { - dma_interrupt_disable(DMA0, DMA_CH0, DMA_INTERRUPT_DISABLE); + if (gd32_dma_interrupt_flag_get()) { + gd32_dma_interrupt_disable(); if (s_TxBuffer[dmx::config::UART7_PORT].outputStyle == dmx::OutputStyle::DELTA) { s_TxBuffer[dmx::config::UART7_PORT].State = TxRxState::IDLE; } else { - timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_3 , TIMER_CNT(TIMER4) + s_nDmxTransmitInterTime); + timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_3 , TIMER_CNT(TIMER4) + s_nDmxTransmit.nInterTime); s_TxBuffer[dmx::config::UART7_PORT].State = TxRxState::DMXINTER; } + +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) + sv_TotalStatistics[dmx::config::UART7_PORT].Dmx.Sent++; +#endif } - dma_interrupt_flag_clear(DMA0, DMA_CH0, DMA_INTERRUPT_FLAG_CLEAR); + gd32_dma_interrupt_flag_clear(); } # endif #endif } -static void uart_dmx_config(uint32_t usart_periph) { +static void uart_dmx_config(const uint32_t usart_periph) { gd32_uart_begin(usart_periph, 250000U, GD32_UART_BITS_8, GD32_UART_PARITY_NONE, GD32_UART_STOP_2BITS); } -Dmx *Dmx::s_pThis = nullptr; +Dmx *Dmx::s_pThis; Dmx::Dmx() { DEBUG_ENTRY @@ -1602,17 +1424,20 @@ Dmx::Dmx() { assert(s_pThis == nullptr); s_pThis = this; + s_nDmxTransmit.nBreakTime = dmx::transmit::BREAK_TIME_TYPICAL; + s_nDmxTransmit.nMabTime = dmx::transmit::MAB_TIME_MIN; + s_nDmxTransmit.nInterTime = dmx::transmit::PERIOD_DEFAULT - s_nDmxTransmit.nBreakTime - s_nDmxTransmit.nMabTime - (dmx::max::CHANNELS * 44) - 44; + for (auto i = 0; i < DMX_MAX_PORTS; i++) { -#if !defined (GD32F4XX) +#if defined (GPIO_INIT) gpio_init(s_DirGpio[i].nPort, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, s_DirGpio[i].nPin); #else gpio_mode_set(s_DirGpio[i].nPort, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLDOWN, s_DirGpio[i].nPin); - gpio_output_options_set(s_DirGpio[i].nPort, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, s_DirGpio[i].nPin); - gpio_af_set(s_DirGpio[i].nPort, GPIO_AF_0, s_DirGpio[i].nPin); + gpio_output_options_set(s_DirGpio[i].nPort, GPIO_OTYPE_PP, GPIO_OSPEED, s_DirGpio[i].nPin); #endif m_nDmxTransmissionLength[i] = dmx::max::CHANNELS; SetPortDirection(i, PortDirection::INP, false); - s_RxBuffer[i].State = TxRxState::IDLE; + sv_RxBuffer[i].State = TxRxState::IDLE; s_TxBuffer[i].State = TxRxState::IDLE; s_TxBuffer[i].outputStyle = dmx::OutputStyle::DELTA; ClearData(i); @@ -1625,59 +1450,58 @@ Dmx::Dmx() { #if defined (DMX_USE_UART4) || defined (DMX_USE_USART5) || defined (DMX_USE_UART6) || defined (DMX_USE_UART7) timer4_config(); // DMX Transmit -> UART4, USART5, UART6, UART7 #endif -#if !defined(CONFIG_DMX_TRANSMIT_ONLY) - timer2_config(); // DMX Receive -> Slot time-out Port 0,1,2,3 - timer3_config(); // DMX Receive -> Slot time-out Port 4,5,6,7 - timer6_config(); // DMX Receive -> Updates per second -#endif #if defined (DMX_USE_USART0) uart_dmx_config(USART0); + NVIC_SetPriority(USART0_IRQn, 0); NVIC_EnableIRQ(USART0_IRQn); #endif #if defined (DMX_USE_USART1) uart_dmx_config(USART1); + NVIC_SetPriority(USART1_IRQn, 0); NVIC_EnableIRQ(USART1_IRQn); #endif #if defined (DMX_USE_USART2) uart_dmx_config(USART2); + NVIC_SetPriority(USART2_IRQn, 0); NVIC_EnableIRQ(USART2_IRQn); #endif #if defined (DMX_USE_UART3) uart_dmx_config(UART3); + NVIC_SetPriority(UART3_IRQn, 0); NVIC_EnableIRQ(UART3_IRQn); #endif #if defined (DMX_USE_UART4) uart_dmx_config(UART4); + NVIC_SetPriority(UART4_IRQn, 0); NVIC_EnableIRQ(UART4_IRQn); #endif #if defined (DMX_USE_USART5) uart_dmx_config(USART5); + NVIC_SetPriority(USART5_IRQn, 0); NVIC_EnableIRQ(USART5_IRQn); #endif #if defined (DMX_USE_UART6) uart_dmx_config(UART6); + NVIC_SetPriority(UART6_IRQn, 0); NVIC_EnableIRQ(UART6_IRQn); #endif #if defined (DMX_USE_UART7) uart_dmx_config(UART7); + NVIC_SetPriority(UART7_IRQn, 0); NVIC_EnableIRQ(UART7_IRQn); #endif - logic_analyzer::init(); DEBUG_EXIT } void Dmx::SetPortDirection(const uint32_t nPortIndex, PortDirection portDirection, bool bEnableData) { -// DEBUG_PRINTF("nPortIndex=%u %s %c", nPortIndex, portDirection == PortDirection::INP ? "Input" : "Output", bEnableData ? 'Y' : 'N'); - assert(nPortIndex < DMX_MAX_PORTS); - - const auto nUart = _port_to_uart(nPortIndex); + assert(nPortIndex < dmx::config::max::PORTS); if (m_dmxPortDirection[nPortIndex] != portDirection) { m_dmxPortDirection[nPortIndex] = portDirection; - StopData(nUart, nPortIndex); + StopData(nPortIndex); if (portDirection == PortDirection::OUTP) { GPIO_BOP(s_DirGpio[nPortIndex].nPort) = s_DirGpio[nPortIndex].nPin; @@ -1687,33 +1511,31 @@ void Dmx::SetPortDirection(const uint32_t nPortIndex, PortDirection portDirectio assert(0); } } else if (!bEnableData) { - StopData(nUart, nPortIndex); + StopData(nPortIndex); } if (bEnableData) { - StartData(nUart, nPortIndex); + StartData(nPortIndex); } } void Dmx::ClearData(const uint32_t nPortIndex) { - assert(nPortIndex < DMX_MAX_PORTS); + assert(nPortIndex < dmx::config::max::PORTS); auto *p = &s_TxBuffer[nPortIndex]; - auto *p16 = reinterpret_cast(p->dmx.data); - - for (auto i = 0; i < dmx::buffer::SIZE / 2; i++) { - *p16++ = 0; - } - p->dmx.nLength = 513; // Including START Code + __builtin_memset(p->dmx.data, 0, dmx::buffer::SIZE); } -void Dmx::StartDmxOutput(const uint32_t nPortIndex) { - logic_analyzer::ch2_set(); - - assert(nPortIndex < dmx::config::max::OUT); - const auto nUart = _port_to_uart(nPortIndex); +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) +volatile dmx::TotalStatistics& Dmx::GetTotalStatistics(const uint32_t nPortIndex) { + sv_TotalStatistics[nPortIndex].Dmx.Received = sv_nRxDmxPackets[nPortIndex].nCount; + return sv_TotalStatistics[nPortIndex]; +} +#endif +template +static void start_dmx_output() { /* * USART_FLAG_TC is set after power on. * The flag is cleared by DMA interrupt when maximum slots - 1 are transmitted. @@ -1727,211 +1549,228 @@ void Dmx::StartDmxOutput(const uint32_t nPortIndex) { /* TIMER 1 */ #if defined (DMX_USE_USART0) case USART0: - _gpio_mode_output(USART0_GPIO_PORT, USART0_TX_PIN); - GPIO_BC(USART0_GPIO_PORT) = USART0_TX_PIN; - timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_0, TIMER_CNT(TIMER1) + s_nDmxTransmitBreakTime); - timer_interrupt_enable(TIMER1, TIMER_INT_CH0); + gd32_gpio_mode_output(); + GPIO_BC(USART0_GPIOx) = USART0_TX_GPIO_PINx; + TIMER_CH0CV(TIMER1) = TIMER_CNT(TIMER1) + s_nDmxTransmit.nBreakTime; + s_TxBuffer[dmx::config::USART0_PORT].State = TxRxState::BREAK; + return; break; #endif #if defined (DMX_USE_USART1) case USART1: - _gpio_mode_output(USART1_GPIO_PORT, USART1_TX_PIN); - GPIO_BC(USART1_GPIO_PORT) = USART1_TX_PIN; - timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, TIMER_CNT(TIMER1) + s_nDmxTransmitBreakTime); - timer_interrupt_enable(TIMER1, TIMER_INT_CH1); + gd32_gpio_mode_output(); + GPIO_BC(USART1_GPIOx) = USART1_TX_GPIO_PINx; + TIMER_CH1CV(TIMER1) = TIMER_CNT(TIMER1) + s_nDmxTransmit.nBreakTime; + s_TxBuffer[dmx::config::USART1_PORT].State = TxRxState::BREAK; + return; break; #endif #if defined (DMX_USE_USART2) case USART2: - _gpio_mode_output(USART2_GPIO_PORT, USART2_TX_PIN); - GPIO_BC(USART2_GPIO_PORT) = USART2_TX_PIN; - timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_2, TIMER_CNT(TIMER1) + s_nDmxTransmitBreakTime); - timer_interrupt_enable(TIMER1, TIMER_INT_CH2); + gd32_gpio_mode_output(); + GPIO_BC(USART2_GPIOx) = USART2_TX_GPIO_PINx; + TIMER_CH2CV(TIMER1) = TIMER_CNT(TIMER1) + s_nDmxTransmit.nBreakTime; + s_TxBuffer[dmx::config::USART2_PORT].State = TxRxState::BREAK; + return; break; #endif #if defined (DMX_USE_UART3) case UART3: - _gpio_mode_output(UART3_GPIO_PORT, UART3_TX_PIN); - GPIO_BC(UART3_GPIO_PORT) = UART3_TX_PIN; - timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_3, TIMER_CNT(TIMER1) + s_nDmxTransmitBreakTime); - timer_interrupt_enable(TIMER1, TIMER_INT_CH3); + gd32_gpio_mode_output(); + GPIO_BC(UART3_GPIOx) = UART3_TX_GPIO_PINx; + TIMER_CH3CV(TIMER1) = TIMER_CNT(TIMER1) + s_nDmxTransmit.nBreakTime; + s_TxBuffer[dmx::config::UART3_PORT].State = TxRxState::BREAK; + return; break; #endif /* TIMER 4 */ #if defined (DMX_USE_UART4) case UART4: - _gpio_mode_output(UART4_GPIO_TX_PORT, UART4_TX_PIN); - GPIO_BC(UART4_GPIO_TX_PORT) = UART4_TX_PIN; - timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_0, TIMER_CNT(TIMER4) + s_nDmxTransmitBreakTime); - timer_interrupt_enable(TIMER4, TIMER_INT_CH0); + gd32_gpio_mode_output(); + GPIO_BC(UART4_TX_GPIOx) = UART4_TX_GPIO_PINx; + TIMER_CH0CV(TIMER4) = TIMER_CNT(TIMER4) + s_nDmxTransmit.nBreakTime; + s_TxBuffer[dmx::config::UART4_PORT].State = TxRxState::BREAK; + return; break; #endif #if defined (DMX_USE_USART5) case USART5: - _gpio_mode_output(USART5_GPIO_PORT, USART5_TX_PIN); - GPIO_BC(USART5_GPIO_PORT) = USART5_TX_PIN; - timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_1, TIMER_CNT(TIMER4) + s_nDmxTransmitBreakTime); - timer_interrupt_enable(TIMER4, TIMER_INT_CH1); + gd32_gpio_mode_output(); + GPIO_BC(USART5_GPIOx) = USART5_TX_GPIO_PINx; + TIMER_CH1CV(TIMER4) = TIMER_CNT(TIMER4) + s_nDmxTransmit.nBreakTime; + s_TxBuffer[dmx::config::USART5_PORT].State = TxRxState::BREAK; + return; break; #endif #if defined (DMX_USE_UART6) case UART6: - _gpio_mode_output(UART6_GPIO_PORT, UART6_TX_PIN); - GPIO_BC(UART6_GPIO_PORT) = UART6_TX_PIN; - timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_2, TIMER_CNT(TIMER4) + s_nDmxTransmitBreakTime); - timer_interrupt_enable(TIMER4, TIMER_INT_CH2); + gd32_gpio_mode_output(); + GPIO_BC(UART6_GPIOx) = UART6_TX_GPIO_PINx; + TIMER_CH2CV(TIMER4) = TIMER_CNT(TIMER4) + s_nDmxTransmit.nBreakTime; + s_TxBuffer[dmx::config::UART6_PORT].State = TxRxState::BREAK; + return; break; #endif #if defined (DMX_USE_UART7) case UART7: - _gpio_mode_output(UART7_GPIO_PORT, UART7_TX_PIN); - GPIO_BC(UART7_GPIO_PORT) = UART7_TX_PIN; - timer_channel_output_pulse_value_config(TIMER4, TIMER_CH_3, TIMER_CNT(TIMER4) + s_nDmxTransmitBreakTime); - timer_interrupt_enable(TIMER4, TIMER_INT_CH3); + gd32_gpio_mode_output(); + GPIO_BC(UART7_GPIOx) = UART7_TX_GPIO_PINx; + TIMER_CH3CV(TIMER4) = TIMER_CNT(TIMER4) + s_nDmxTransmit.nBreakTime; + s_TxBuffer[dmx::config::UART7_PORT].State = TxRxState::BREAK; + return; break; #endif default: assert(0); + __builtin_unreachable(); break; } - s_TxBuffer[nPortIndex].State = TxRxState::BREAK; + assert(0); + __builtin_unreachable(); +} - logic_analyzer::ch2_clear(); +template +static void start_dmx_output_port() { + if constexpr (portIndex < dmx::config::max::PORTS) { + start_dmx_output(); + } } +void Dmx::StartDmxOutput(const uint32_t nPortIndex) { + assert(nPortIndex < dmx::config::max::PORTS); + + switch (nPortIndex) { + case 0: + start_dmx_output_port<0>(); + break; + case 1: + start_dmx_output_port<1>(); + break; + case 2: + start_dmx_output_port<2>(); + break; + case 3: + start_dmx_output_port<3>(); + break; + case 4: + start_dmx_output_port<4>(); + break; + case 5: + start_dmx_output_port<5>(); + break; + case 6: + start_dmx_output_port<6>(); + break; + case 7: + start_dmx_output_port<7>(); + break; + default: + break; + } +} -void Dmx::StopData(const uint32_t nUart, const uint32_t nPortIndex) { - assert(nPortIndex < DMX_MAX_PORTS); +void Dmx::StopData(const uint32_t nPortIndex) { + assert(nPortIndex < dmx::config::max::PORTS); if (sv_PortState[nPortIndex] == PortState::IDLE) { return; } + sv_PortState[nPortIndex] = PortState::IDLE; + + const auto nUart = dmx_port_to_uart(nPortIndex); + if (m_dmxPortDirection[nPortIndex] == PortDirection::OUTP) { do { if (s_TxBuffer[nPortIndex].State == dmx::TxRxState::DMXINTER) { - usart_flag_clear(nUart, USART_FLAG_TC); - while (SET != usart_flag_get(nUart, USART_FLAG_TC)) - ; + gd32_usart_flag_clear(nUart); + do { + __DMB(); + } while (!gd32_usart_flag_get(nUart)); + s_TxBuffer[nPortIndex].State = dmx::TxRxState::IDLE; } } while (s_TxBuffer[nPortIndex].State != dmx::TxRxState::IDLE); - } else if (m_dmxPortDirection[nPortIndex] == PortDirection::INP) { - usart_interrupt_disable(nUart, USART_INT_RBNE); - s_RxBuffer[nPortIndex].State = TxRxState::IDLE; -#if !defined(CONFIG_DMX_TRANSMIT_ONLY) - switch (nPortIndex) { - case 0: - TIMER_DMAINTEN(TIMER2) &= (~(uint32_t) TIMER_INT_CH0); - break; -#if DMX_MAX_PORTS >= 2 - case 1: - TIMER_DMAINTEN(TIMER2) &= (~(uint32_t) TIMER_INT_CH1); - break; -#endif -#if DMX_MAX_PORTS >= 3 - case 2: - TIMER_DMAINTEN(TIMER2) &= (~(uint32_t) TIMER_INT_CH2); - break; -#endif -#if DMX_MAX_PORTS >= 4 - case 3: - TIMER_DMAINTEN(TIMER2) &= (~(uint32_t) TIMER_INT_CH3); - break; -#endif -#if DMX_MAX_PORTS >= 5 - case 4: - TIMER_DMAINTEN(TIMER3) &= (~(uint32_t) TIMER_INT_CH0); - break; -#endif -#if DMX_MAX_PORTS >= 6 - case 5: - TIMER_DMAINTEN(TIMER3) &= (~(uint32_t) TIMER_INT_CH1); - break; -#endif -#if DMX_MAX_PORTS >= 7 - case 6: - TIMER_DMAINTEN(TIMER3) &= (~(uint32_t) TIMER_INT_CH2); - break; -#endif -#if DMX_MAX_PORTS == 8 - case 7: - TIMER_DMAINTEN(TIMER3) &= (~(uint32_t) TIMER_INT_CH3); - break; -#endif - default: - assert(0); - __builtin_unreachable(); - break; - } -#endif - } else { - assert(0); - __builtin_unreachable(); + return; } - sv_PortState[nPortIndex] = PortState::IDLE; + if (m_dmxPortDirection[nPortIndex] == PortDirection::INP) { + gd32_usart_interrupt_disable(nUart); + gd32_usart_interrupt_disable(nUart); + sv_RxBuffer[nPortIndex].State = TxRxState::IDLE; + return; + } + + assert(0); + __builtin_unreachable(); } // DMX Send void Dmx::SetDmxBreakTime(uint32_t nBreakTime) { - s_nDmxTransmitBreakTime = std::max(transmit::BREAK_TIME_MIN, nBreakTime); + s_nDmxTransmit.nBreakTime = std::max(transmit::BREAK_TIME_MIN, nBreakTime); SetDmxPeriodTime(m_nDmxTransmitPeriodRequested); } +uint32_t Dmx::GetDmxBreakTime() const { + return s_nDmxTransmit.nBreakTime; +} + void Dmx::SetDmxMabTime(uint32_t nMabTime) { - s_nDmxTransmitMabTime = std::max(transmit::MAB_TIME_MIN, nMabTime); + s_nDmxTransmit.nMabTime = std::max(transmit::MAB_TIME_MIN, nMabTime); SetDmxPeriodTime(m_nDmxTransmitPeriodRequested); } +uint32_t Dmx::GetDmxMabTime() const { + return s_nDmxTransmit.nMabTime; +} + void Dmx::SetDmxPeriodTime(uint32_t nPeriod) { m_nDmxTransmitPeriodRequested = nPeriod; auto nLengthMax = s_TxBuffer[0].dmx.nLength; - for (uint32_t nPortIndex = 1; nPortIndex < config::max::OUT; nPortIndex++) { + for (uint32_t nPortIndex = 1; nPortIndex < dmx::config::max::PORTS; nPortIndex++) { const auto nLength = s_TxBuffer[nPortIndex].dmx.nLength; if (nLength > nLengthMax) { nLengthMax = nLength; } } - auto nPackageLengthMicroSeconds = s_nDmxTransmitBreakTime + s_nDmxTransmitMabTime + (nLengthMax * 44U); + auto nPackageLengthMicroSeconds = s_nDmxTransmit.nBreakTime + s_nDmxTransmit.nMabTime + (nLengthMax * 44U); - // The GD32F4xx Timer 1 has a 32-bit counter -#if ! defined(GD32F4XX) + // The GD32F4xx/GD32H7XX Timer 1 has a 32-bit counter +#if defined(GD32F4XX) || defined (GD32H7XX) +#else if (nPackageLengthMicroSeconds > (static_cast(~0) - 44U)) { - s_nDmxTransmitBreakTime = std::min(transmit::BREAK_TIME_TYPICAL, s_nDmxTransmitBreakTime); - s_nDmxTransmitMabTime = transmit::MAB_TIME_MIN; - nPackageLengthMicroSeconds = s_nDmxTransmitBreakTime + s_nDmxTransmitMabTime + (nLengthMax * 44U); + s_nDmxTransmit.nBreakTime = std::min(transmit::BREAK_TIME_TYPICAL, s_nDmxTransmit.nBreakTime); + s_nDmxTransmit.nMabTime = transmit::MAB_TIME_MIN; + nPackageLengthMicroSeconds = s_nDmxTransmit.nBreakTime + s_nDmxTransmit.nMabTime + (nLengthMax * 44U); } #endif - uint32_t nDmxTransmitPeriod; - if (nPeriod != 0) { if (nPeriod < nPackageLengthMicroSeconds) { - nDmxTransmitPeriod = std::max(transmit::BREAK_TO_BREAK_TIME_MIN, nPackageLengthMicroSeconds + 44U); + m_nDmxTransmitPeriod = std::max(transmit::BREAK_TO_BREAK_TIME_MIN, nPackageLengthMicroSeconds + 44U); } else { - nDmxTransmitPeriod = nPeriod; + m_nDmxTransmitPeriod = nPeriod; } } else { - nDmxTransmitPeriod = std::max(transmit::BREAK_TO_BREAK_TIME_MIN, nPackageLengthMicroSeconds + 44U); + m_nDmxTransmitPeriod = std::max(transmit::BREAK_TO_BREAK_TIME_MIN, nPackageLengthMicroSeconds + 44U); } - s_nDmxTransmitInterTime = nDmxTransmitPeriod - nPackageLengthMicroSeconds; + s_nDmxTransmit.nInterTime = m_nDmxTransmitPeriod - nPackageLengthMicroSeconds; - DEBUG_PRINTF("nPeriod=%u, nLengthMax=%u, s_nDmxTransmitPeriod=%u, nPackageLengthMicroSeconds=%u -> s_nDmxTransmitInterTime=%u", nPeriod, nLengthMax, nDmxTransmitPeriod, nPackageLengthMicroSeconds, s_nDmxTransmitInterTime); + DEBUG_PRINTF("nPeriod=%u, nLengthMax=%u, m_nDmxTransmitPeriod=%u, nPackageLengthMicroSeconds=%u -> s_nDmxTransmit.nInterTime=%u", nPeriod, nLengthMax, m_nDmxTransmitPeriod, nPackageLengthMicroSeconds, s_nDmxTransmit.nInterTime); } void Dmx::SetDmxSlots(uint16_t nSlots) { if ((nSlots >= 2) && (nSlots <= dmx::max::CHANNELS)) { m_nDmxTransmitSlots = nSlots; - for (uint32_t i = 0; i < config::max::OUT; i++) { + for (uint32_t i = 0; i < dmx::config::max::PORTS; i++) { m_nDmxTransmissionLength[i] = std::min(m_nDmxTransmissionLength[i], static_cast(nSlots)); } @@ -1940,26 +1779,55 @@ void Dmx::SetDmxSlots(uint16_t nSlots) { } void Dmx::SetOutputStyle(const uint32_t nPortIndex, const dmx::OutputStyle outputStyle) { - assert(nPortIndex < dmx::config::max::OUT); - + assert(nPortIndex < dmx::config::max::PORTS); s_TxBuffer[nPortIndex].outputStyle = outputStyle; + + if (outputStyle == dmx::OutputStyle::CONTINOUS) { + if (!m_bHasContinuosOutput) { + m_bHasContinuosOutput = true; + if (m_dmxPortDirection[nPortIndex] == dmx::PortDirection::OUTP) { + StartDmxOutput(nPortIndex); + } + return; + } + + for (uint32_t nIndex = 0; nIndex < dmx::config::max::PORTS; nIndex++) { + if ((s_TxBuffer[nIndex].outputStyle == dmx::OutputStyle::CONTINOUS) && (m_dmxPortDirection[nIndex] == dmx::PortDirection::OUTP)) { + StopData(nIndex); + } + } + + for (uint32_t nIndex = 0; nIndex < dmx::config::max::PORTS; nIndex++) { + if ((s_TxBuffer[nIndex].outputStyle == dmx::OutputStyle::CONTINOUS) && (m_dmxPortDirection[nIndex] == dmx::PortDirection::OUTP)) { + StartDmxOutput(nIndex); + } + } + } else { + m_bHasContinuosOutput = false; + for (uint32_t nIndex = 0; nIndex < dmx::config::max::PORTS; nIndex++) { + if (s_TxBuffer[nIndex].outputStyle == dmx::OutputStyle::CONTINOUS) { + m_bHasContinuosOutput = true; + return; + } + } + } } dmx::OutputStyle Dmx::GetOutputStyle(const uint32_t nPortIndex) const { - assert(nPortIndex < dmx::config::max::OUT); + assert(nPortIndex < dmx::config::max::PORTS); return s_TxBuffer[nPortIndex].outputStyle; } void Dmx::SetSendData(const uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength) { - assert(nPortIndex < DMX_MAX_PORTS); + assert(nPortIndex < dmx::config::max::PORTS); - auto *p = &s_TxBuffer[nPortIndex]; - auto *pDst = p->dmx.data; + auto &p = s_TxBuffer[nPortIndex]; + auto *pDst = p.dmx.data; nLength = std::min(nLength, static_cast(m_nDmxTransmitSlots)); - p->dmx.nLength = static_cast(nLength + 1); + p.dmx.nLength = nLength + 1; - memcpy(pDst, pData, nLength); + memcpy(pDst, pData, nLength); if (nLength != m_nDmxTransmissionLength[nPortIndex]) { m_nDmxTransmissionLength[nPortIndex] = nLength; @@ -1968,25 +1836,22 @@ void Dmx::SetSendData(const uint32_t nPortIndex, const uint8_t *pData, uint32_t } void Dmx::SetSendDataWithoutSC(const uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength) { - logic_analyzer::ch0_set(); + assert(nPortIndex < dmx::config::max::PORTS); - assert(nPortIndex < DMX_MAX_PORTS); - - auto *p = &s_TxBuffer[nPortIndex]; - auto *pDst = p->dmx.data; + auto &p = s_TxBuffer[nPortIndex]; + auto *pDst = p.dmx.data; nLength = std::min(nLength, static_cast(m_nDmxTransmitSlots)); - p->dmx.nLength = static_cast(nLength + 1); + p.dmx.nLength = nLength + 1; + p.dmx.bDataPending = true; pDst[0] = START_CODE; - memcpy(&pDst[1], pData, nLength); + memcpy(&pDst[1], pData, nLength); if (nLength != m_nDmxTransmissionLength[nPortIndex]) { m_nDmxTransmissionLength[nPortIndex] = nLength; SetDmxPeriodTime(m_nDmxTransmitPeriodRequested); } - - logic_analyzer::ch0_clear(); } void Dmx::Blackout() { @@ -1994,11 +1859,9 @@ void Dmx::Blackout() { for (uint32_t nPortIndex = 0; nPortIndex < DMX_MAX_PORTS; nPortIndex++) { if (m_dmxPortDirection[nPortIndex] == dmx::PortDirection::OUTP) { - const auto nUart = _port_to_uart(nPortIndex); - - StopData(nUart, nPortIndex); + StopData(nPortIndex); ClearData(nPortIndex); - StartData(nUart, nPortIndex); + StartData(nPortIndex); } } @@ -2010,21 +1873,19 @@ void Dmx::FullOn() { for (uint32_t nPortIndex = 0; nPortIndex < DMX_MAX_PORTS; nPortIndex++) { if (m_dmxPortDirection[nPortIndex] == dmx::PortDirection::OUTP) { - const auto nUart = _port_to_uart(nPortIndex); + StopData(nPortIndex); - StopData(nUart, nPortIndex); + auto * __restrict__ p = &s_TxBuffer[nPortIndex]; + auto *p32 = reinterpret_cast(p->dmx.data); - auto *p = &s_TxBuffer[nPortIndex]; - auto *p16 = reinterpret_cast(p->dmx.data); - - for (auto i = 0; i < dmx::buffer::SIZE / 2; i++) { - *p16++ = UINT16_MAX; + for (auto i = 0; i < dmx::buffer::SIZE / 4; i++) { + *p32++ = UINT32_MAX; } p->dmx.data[0] = dmx::START_CODE; p->dmx.nLength = 513; - StartData(nUart, nPortIndex); + StartData(nPortIndex); } } @@ -2035,138 +1896,93 @@ void Dmx::StartOutput(const uint32_t nPortIndex) { if ((sv_PortState[nPortIndex] == dmx::PortState::TX) && (s_TxBuffer[nPortIndex].outputStyle == dmx::OutputStyle::DELTA) && (s_TxBuffer[nPortIndex].State == dmx::TxRxState::IDLE)) { - StartDmxOutput(nPortIndex); } } -static bool s_doForce; +void Dmx::Sync() { + for (uint32_t nPortIndex = 0; nPortIndex < dmx::config::max::PORTS; nPortIndex++) { + auto &txBuffer = s_TxBuffer[nPortIndex]; -void Dmx::SetOutput(const bool doForce) { - logic_analyzer::ch1_set(); - - if (doForce) { - s_doForce = true; - for (uint32_t nPortIndex = 0; nPortIndex < dmx::config::max::OUT; nPortIndex++) { - if ((sv_PortState[nPortIndex] == dmx::PortState::TX) - && (s_TxBuffer[nPortIndex].outputStyle == dmx::OutputStyle::CONTINOUS)) { - StopData(_port_to_uart(nPortIndex), nPortIndex); - } + if (!txBuffer.dmx.bDataPending) { + continue; } - logic_analyzer::ch1_clear(); - return; - } + txBuffer.dmx.bDataPending = false; - for (uint32_t nPortIndex = 0; nPortIndex < dmx::config::max::OUT; nPortIndex++) { - if (sv_PortState[nPortIndex] == dmx::PortState::TX) { - const auto b = ((s_TxBuffer[nPortIndex].outputStyle == dmx::OutputStyle::CONTINOUS) && s_doForce); - if (b || ((s_TxBuffer[nPortIndex].outputStyle == dmx::OutputStyle::DELTA) && (s_TxBuffer[nPortIndex].State == dmx::TxRxState::IDLE))) { + if ((sv_PortState[nPortIndex] == dmx::PortState::TX)) { + if ((txBuffer.outputStyle == dmx::OutputStyle::DELTA) && (txBuffer.State == dmx::TxRxState::IDLE)) { StartDmxOutput(nPortIndex); } } } - - s_doForce = false; - logic_analyzer::ch1_clear(); } -void Dmx::StartData(const uint32_t nUart, const uint32_t nPortIndex) { -// DEBUG_PRINTF("sv_PortState[%u]=%u", nPortIndex, sv_PortState[nPortIndex]); - assert(nPortIndex < DMX_MAX_PORTS); +void Dmx::StartData(const uint32_t nPortIndex) { + assert(nPortIndex < dmx::config::max::PORTS); assert(sv_PortState[nPortIndex] == PortState::IDLE); if (m_dmxPortDirection[nPortIndex] == dmx::PortDirection::OUTP) { sv_PortState[nPortIndex] = PortState::TX; - if (s_TxBuffer[nPortIndex].outputStyle == dmx::OutputStyle::CONTINOUS) { - StartDmxOutput(nPortIndex); - } - } else if (m_dmxPortDirection[nPortIndex] == dmx::PortDirection::INP) { - s_RxBuffer[nPortIndex].State = TxRxState::IDLE; + return; + } - while (RESET == usart_flag_get(nUart, USART_FLAG_TBE)) - ; + if (m_dmxPortDirection[nPortIndex] == dmx::PortDirection::INP) { + sv_RxBuffer[nPortIndex].State = TxRxState::IDLE; - usart_interrupt_flag_clear(nUart, USART_INT_FLAG_RBNE); - usart_interrupt_enable(nUart, USART_INT_RBNE); + const auto nUart = dmx_port_to_uart(nPortIndex); - sv_PortState[nPortIndex] = PortState::RX; + do { + __DMB(); + } while (!gd32_usart_flag_get(nUart)); -#if !defined(CONFIG_DMX_TRANSMIT_ONLY) - switch (nPortIndex) { - case 0: - TIMER_DMAINTEN(TIMER2) |= (uint32_t) TIMER_INT_CH0; - break; -#if DMX_MAX_PORTS >= 2 - case 1: - TIMER_DMAINTEN(TIMER2) |= (uint32_t) TIMER_INT_CH1; - break; -#endif -#if DMX_MAX_PORTS >= 3 - case 2: - TIMER_DMAINTEN(TIMER2) |= (uint32_t) TIMER_INT_CH2; - break; -#endif -#if DMX_MAX_PORTS >= 4 - case 3: - TIMER_DMAINTEN(TIMER2) |= (uint32_t) TIMER_INT_CH3; - break; -#endif -#if DMX_MAX_PORTS >= 5 - case 4: - TIMER_DMAINTEN(TIMER3) |= (uint32_t) TIMER_INT_CH0; - break; -#endif -#if DMX_MAX_PORTS >= 6 - case 5: - TIMER_DMAINTEN(TIMER3) |= (uint32_t) TIMER_INT_CH1; - break; -#endif -#if DMX_MAX_PORTS >= 7 - case 6: - TIMER_DMAINTEN(TIMER3) |= (uint32_t) TIMER_INT_CH2; - break; -#endif -#if DMX_MAX_PORTS == 8 - case 7: - TIMER_DMAINTEN(TIMER3) |= (uint32_t) TIMER_INT_CH3; - break; -#endif - default: - assert(0); - __builtin_unreachable(); - break; - } -#endif - } else { - assert(0); - __builtin_unreachable(); + gd32_usart_interrupt_flag_clear(nUart); + gd32_usart_interrupt_flag_clear(nUart); + gd32_usart_interrupt_enable(nUart); + gd32_usart_interrupt_enable(nUart); + + sv_PortState[nPortIndex] = PortState::RX; + return; } + + assert(0); + __builtin_unreachable(); } // DMX Receive -const uint8_t* Dmx::GetDmxChanged(UNUSED uint32_t nPortIndex) { +const uint8_t *Dmx::GetDmxChanged(const uint32_t nPortIndex) { #if !defined(CONFIG_DMX_TRANSMIT_ONLY) - const auto *p = GetDmxAvailable(nPortIndex); + const auto * __restrict__ p = GetDmxAvailable(nPortIndex); if (p == nullptr) { return nullptr; } - const auto *pSrc16 = reinterpret_cast(p); - auto *pDst16 = reinterpret_cast(&s_RxDmxPrevious[nPortIndex][0]); + const auto * __restrict__ pSrc32 = reinterpret_cast(sv_RxBuffer[nPortIndex].Dmx.current.data); + auto * __restrict__ pDst32 = reinterpret_cast(sv_RxBuffer[nPortIndex].Dmx.previous.data); - auto isChanged = false; + if (sv_RxBuffer[nPortIndex].Dmx.current.nSlotsInPacket != sv_RxBuffer[nPortIndex].Dmx.previous.nSlotsInPacket) { + sv_RxBuffer[nPortIndex].Dmx.previous.nSlotsInPacket = sv_RxBuffer[nPortIndex].Dmx.current.nSlotsInPacket; - for (auto i = 0; i < buffer::SIZE / 2; i++) { - if (*pDst16 != *pSrc16) { - *pDst16 = *pSrc16; - isChanged = true; + for (size_t i = 0; i < buffer::SIZE / 4; ++i) { + pDst32[i] = pSrc32[i]; } - pDst16++; - pSrc16++; + + return p; + } + + bool isChanged = false; + + for (size_t i = 0; i < buffer::SIZE / 4; ++i) { + const auto srcVal = pSrc32[i]; + auto dstVal = pDst32[i]; + + if (srcVal != dstVal) { + pDst32[i] = srcVal; + isChanged = true; + } } return (isChanged ? p : nullptr); @@ -2175,28 +1991,31 @@ const uint8_t* Dmx::GetDmxChanged(UNUSED uint32_t nPortIndex) { #endif } -const uint8_t *Dmx::GetDmxAvailable(UNUSED uint32_t nPortIndex) { - assert(nPortIndex < DMX_MAX_PORTS); +const uint8_t *Dmx::GetDmxAvailable([[maybe_unused]] const uint32_t nPortIndex) { + assert(nPortIndex < dmx::config::max::PORTS); #if !defined(CONFIG_DMX_TRANSMIT_ONLY) - if ((s_RxBuffer[nPortIndex].Dmx.nSlotsInPacket & 0x8000) != 0x8000) { + auto nSlotsInPacket = sv_RxBuffer[nPortIndex].Dmx.current.nSlotsInPacket; + + if ((nSlotsInPacket & 0x8000) != 0x8000) { return nullptr; } - s_RxBuffer[nPortIndex].Dmx.nSlotsInPacket &= ~0x8000; - s_RxBuffer[nPortIndex].Dmx.nSlotsInPacket--; // Remove SC from length + nSlotsInPacket &= ~0x8000; + nSlotsInPacket--; // Remove SC from length + sv_RxBuffer[nPortIndex].Dmx.current.nSlotsInPacket = nSlotsInPacket; - return s_RxBuffer[nPortIndex].data; + return const_cast(sv_RxBuffer[nPortIndex].Dmx.current.data); #else return nullptr; #endif } -const uint8_t* Dmx::GetDmxCurrentData(const uint32_t nPortIndex) { - return s_RxBuffer[nPortIndex].data; +const uint8_t *Dmx::GetDmxCurrentData(const uint32_t nPortIndex) { + return const_cast(sv_RxBuffer[nPortIndex].Dmx.current.data); } -uint32_t Dmx::GetDmxUpdatesPerSecond(UNUSED uint32_t nPortIndex) { - assert(nPortIndex < DMX_MAX_PORTS); +uint32_t Dmx::GetDmxUpdatesPerSecond([[maybe_unused]] uint32_t nPortIndex) { + assert(nPortIndex < dmx::config::max::PORTS); #if !defined(CONFIG_DMX_TRANSMIT_ONLY) return sv_nRxDmxPackets[nPortIndex].nPerSecond; #else @@ -2204,74 +2023,61 @@ uint32_t Dmx::GetDmxUpdatesPerSecond(UNUSED uint32_t nPortIndex) { #endif } -uint32_t GetDmxReceivedCount(UNUSED uint32_t nPortIndex) { - assert(nPortIndex < DMX_MAX_PORTS); -#if !defined(CONFIG_DMX_TRANSMIT_ONLY) - return sv_nRxDmxPackets[nPortIndex].nCount; -#else - return 0; -#endif -} - // RDM Send -void Dmx::RdmSendRaw(const uint32_t nPortIndex, const uint8_t* pRdmData, uint32_t nLength) { - assert(nPortIndex < DMX_MAX_PORTS); +template +static void rdm_send_raw(const uint8_t *const pRdmData, const uint32_t nLength) { + assert(nPortIndex < dmx::config::max::PORTS); assert(pRdmData != nullptr); assert(nLength != 0); - const auto nUart = _port_to_uart(nPortIndex); - - while (SET != usart_flag_get(nUart, USART_FLAG_TC)) - ; - switch (nUart) { #if defined (DMX_USE_USART0) case USART0: - _gpio_mode_output(USART0_GPIO_PORT, USART0_TX_PIN); - GPIO_BC(USART0_GPIO_PORT) = USART0_TX_PIN; + gd32_gpio_mode_output(); + GPIO_BC(USART0_GPIOx) = USART0_TX_GPIO_PINx; break; #endif #if defined (DMX_USE_USART1) case USART1: - _gpio_mode_output(USART1_GPIO_PORT, USART1_TX_PIN); - GPIO_BC(USART1_GPIO_PORT) = USART1_TX_PIN; + gd32_gpio_mode_output(); + GPIO_BC(USART1_GPIOx) = USART1_TX_GPIO_PINx; break; #endif #if defined (DMX_USE_USART2) case USART2: - _gpio_mode_output(USART2_GPIO_PORT, USART2_TX_PIN); - GPIO_BC(USART2_GPIO_PORT) = USART2_TX_PIN; + gd32_gpio_mode_output(); + GPIO_BC(USART2_GPIOx) = USART2_TX_GPIO_PINx; break; #endif #if defined (DMX_USE_UART3) case UART3: - _gpio_mode_output(UART3_GPIO_PORT, UART3_TX_PIN); - GPIO_BC(UART3_GPIO_PORT) = UART3_TX_PIN; + gd32_gpio_mode_output(); + GPIO_BC(UART3_GPIOx) = UART3_TX_GPIO_PINx; break; #endif #if defined (DMX_USE_UART4) case UART4: - _gpio_mode_output(UART4_GPIO_TX_PORT, UART4_TX_PIN); - GPIO_BC(UART4_GPIO_TX_PORT) = UART4_TX_PIN; + gd32_gpio_mode_output(); + GPIO_BC(UART4_TX_GPIOx) = UART4_TX_GPIO_PINx; break; #endif #if defined (DMX_USE_USART5) case USART5: - _gpio_mode_output(USART5_GPIO_PORT, USART5_TX_PIN); - GPIO_BC(USART5_GPIO_PORT) = USART5_TX_PIN; + gd32_gpio_mode_output(); + GPIO_BC(USART5_GPIOx) = USART5_TX_GPIO_PINx; break; #endif #if defined (DMX_USE_UART6) case UART6: - _gpio_mode_output(UART6_GPIO_PORT, UART6_TX_PIN); - GPIO_BC(UART6_GPIO_PORT) = UART6_TX_PIN; + gd32_gpio_mode_output(); + GPIO_BC(UART6_GPIOx) = UART6_TX_GPIO_PINx; break; #endif #if defined (DMX_USE_UART7) case UART7: - _gpio_mode_output(UART7_GPIO_PORT, UART7_TX_PIN); - GPIO_BC(UART7_GPIO_PORT) = UART7_TX_PIN; + gd32_gpio_mode_output(); + GPIO_BC(UART7_GPIOx) = UART7_TX_GPIO_PINx; break; #endif default: @@ -2280,47 +2086,50 @@ void Dmx::RdmSendRaw(const uint32_t nPortIndex, const uint8_t* pRdmData, uint32_ break; } - udelay(RDM_TRANSMIT_BREAK_TIME); + TIMER_CNT(TIMER5) = 0; + do { + __DMB(); + } while (TIMER_CNT(TIMER5) < RDM_TRANSMIT_BREAK_TIME); switch (nUart) { #if defined (DMX_USE_USART0) case USART0: - _gpio_mode_af(USART0_GPIO_PORT, USART0_TX_PIN, USART0); + gd32_gpio_mode_af(); break; #endif #if defined (DMX_USE_USART1) case USART1: - _gpio_mode_af(USART1_GPIO_PORT, USART1_TX_PIN, USART1); + gd32_gpio_mode_af(); break; #endif #if defined (DMX_USE_USART2) case USART2: - _gpio_mode_af(USART2_GPIO_PORT, USART2_TX_PIN, USART2); + gd32_gpio_mode_af(); break; #endif #if defined (DMX_USE_UART3) case UART3: - _gpio_mode_af(UART3_GPIO_PORT, UART3_TX_PIN, UART3); + gd32_gpio_mode_af(); break; #endif #if defined (DMX_USE_UART4) case UART4: - _gpio_mode_af(UART4_GPIO_TX_PORT, UART4_TX_PIN, UART4); + gd32_gpio_mode_af(); break; #endif #if defined (DMX_USE_USART5) case USART5: - _gpio_mode_af(USART5_GPIO_PORT, USART5_TX_PIN, USART5); + gd32_gpio_mode_af(); break; #endif #if defined (DMX_USE_UART6) case UART6: - _gpio_mode_af(UART6_GPIO_PORT, UART6_TX_PIN, UART6); + gd32_gpio_mode_af(); break; #endif #if defined (DMX_USE_UART7) case UART7: - _gpio_mode_af(UART7_GPIO_PORT, UART7_TX_PIN, UART7); + gd32_gpio_mode_af(); break; #endif default: @@ -2329,40 +2138,166 @@ void Dmx::RdmSendRaw(const uint32_t nPortIndex, const uint8_t* pRdmData, uint32_ break; } - udelay(RDM_TRANSMIT_MAB_TIME); + TIMER_CNT(TIMER5) = 0; + do { + __DMB(); + } while (TIMER_CNT(TIMER5) < RDM_TRANSMIT_MAB_TIME); + + for (uint32_t i = 0; i < nLength; i++) { + do { + __DMB(); + } while (!gd32_usart_flag_get(nUart)); + + USART_TDATA(nUart) = USART_TDATA_TDATA & pRdmData[i]; + } + + while (!gd32_usart_flag_get(nUart)) { + static_cast(GET_BITS(USART_RDATA(nUart), 0U, 8U)); + } + +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) + sv_TotalStatistics[nPortIndex].Rdm.Sent.Class++; +#endif +} + +void Dmx::RdmSendRaw(const uint32_t nPortIndex, const uint8_t *pRdmData, uint32_t nLength) { + switch (nPortIndex) { + case 0: + rdm_send_raw<0, dmx_port_to_uart(0)>(pRdmData, nLength); + break; +#if DMX_MAX_PORTS >= 2 + case 1: + rdm_send_raw<1, dmx_port_to_uart(1)>(pRdmData, nLength); + break; +#endif +#if DMX_MAX_PORTS >= 3 + case 2: + rdm_send_raw<2, dmx_port_to_uart(2)>(pRdmData, nLength); + break; +#endif +#if DMX_MAX_PORTS >= 4 + case 3: + rdm_send_raw<3, dmx_port_to_uart(3)>(pRdmData, nLength); + break; +#endif +#if DMX_MAX_PORTS >= 5 + case 4: + rdm_send_raw<4, dmx_port_to_uart(4)>(pRdmData, nLength); + break; +#endif +#if DMX_MAX_PORTS >= 6 + case 5: + rdm_send_raw<5, dmx_port_to_uart(5)>(pRdmData, nLength); + break; +#endif +#if DMX_MAX_PORTS >= 7 + case 6: + rdm_send_raw<6, dmx_port_to_uart(6)>(pRdmData, nLength); + break; +#endif +#if DMX_MAX_PORTS == 8 + case 7: + rdm_send_raw<7, dmx_port_to_uart(7)>(pRdmData, nLength); + break; +#endif + default: + break; + } +} + +void Dmx::RdmSendDiscoveryRespondMessage(uint32_t nPortIndex, const uint8_t *pRdmData, uint32_t nLength) { + assert(nPortIndex < dmx::config::max::PORTS); + assert(pRdmData != nullptr); + assert(nLength != 0); + + // 3.2.2 Responder Packet spacing + udelay(RDM_RESPONDER_PACKET_SPACING, gsv_RdmDataReceiveEnd); + + SetPortDirection(nPortIndex, dmx::PortDirection::OUTP, false); + + const auto nUart = dmx_port_to_uart(nPortIndex); for (uint32_t i = 0; i < nLength; i++) { - while (RESET == usart_flag_get(nUart, USART_FLAG_TBE)) - ; - USART_DATA(nUart) = static_cast(USART_DATA_DATA & pRdmData[i]); + do { + __DMB(); + } while (!gd32_usart_flag_get(nUart)); + + USART_TDATA(nUart) = USART_TDATA_TDATA & pRdmData[i]; } - while (SET != usart_flag_get(nUart, USART_FLAG_TC)) { - static_cast(GET_BITS(USART_DATA(nUart), 0U, 8U)); + while (!gd32_usart_flag_get(nUart)) { + static_cast(GET_BITS(USART_RDATA(nUart), 0U, 8U)); } + + TIMER_CNT(TIMER5) = 0; + do { + __DMB(); + } while (TIMER_CNT(TIMER5) < RDM_RESPONDER_DATA_DIRECTION_DELAY); + + + SetPortDirection(nPortIndex, dmx::PortDirection::INP, true); + +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) + sv_TotalStatistics[nPortIndex].Rdm.Sent.DiscoveryResponse++; +#endif } // RDM Receive const uint8_t *Dmx::RdmReceive(const uint32_t nPortIndex) { - assert(nPortIndex < DMX_MAX_PORTS); + assert(nPortIndex < dmx::config::max::PORTS); + + if ((sv_RxBuffer[nPortIndex].Rdm.nIndex & 0x4000) != 0x4000) { + return nullptr; + } + + sv_RxBuffer[nPortIndex].Rdm.nIndex = 0; + + const auto *p = const_cast(sv_RxBuffer[nPortIndex].Rdm.data); + + if (p[0] == E120_SC_RDM) { + const auto *pRdmCommand = reinterpret_cast(p); + + uint32_t i; + uint16_t nChecksum = 0; + + for (i = 0; i < 24; i++) { + nChecksum = static_cast(nChecksum + p[i]); + } - if ((s_RxBuffer[nPortIndex].Rdm.nIndex & 0x4000) != 0x4000) { + for (; i < pRdmCommand->message_length; i++) { + nChecksum = static_cast(nChecksum + p[i]); + } + + if (p[i++] == static_cast(nChecksum >> 8)) { + if (p[i] == static_cast(nChecksum)) { +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) + sv_TotalStatistics[nPortIndex].Rdm.Received.Good++; +#endif + return p; + } + } +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) + sv_TotalStatistics[nPortIndex].Rdm.Received.Bad++; +#endif return nullptr; + } else { +#if !defined (CONFIG_DMX_DISABLE_STATISTICS) + sv_TotalStatistics[nPortIndex].Rdm.Received.DiscoveryResponse++; +#endif } - s_RxBuffer[nPortIndex].Dmx.nSlotsInPacket = 0; // This is correct. - return s_RxBuffer[nPortIndex].data; + return p; } const uint8_t *Dmx::RdmReceiveTimeOut(const uint32_t nPortIndex, uint16_t nTimeOut) { - assert(nPortIndex < DMX_MAX_PORTS); + assert(nPortIndex < dmx::config::max::PORTS); uint8_t *p = nullptr; TIMER_CNT(TIMER5) = 0; do { - if ((p = const_cast(RdmReceive(nPortIndex))) != nullptr) { + if ((p = const_cast(RdmReceive(nPortIndex))) != nullptr) { return p; } } while (TIMER_CNT(TIMER5) < nTimeOut); diff --git a/lib-dmx/src/gd32/dmx_internal.h b/lib-dmx/src/gd32/dmx_internal.h index 8a6dd883..6a298924 100644 --- a/lib-dmx/src/gd32/dmx_internal.h +++ b/lib-dmx/src/gd32/dmx_internal.h @@ -2,7 +2,7 @@ * @file dmx_internal.h * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -30,9 +30,50 @@ #include #include "gd32.h" +#include "gd32_gpio.h" #include "gd32/dmx_config.h" -static uint32_t _port_to_uart(const uint32_t nPort) { +#ifdef ALIGNED +#undef ALIGNED +#endif +#define ALIGNED __attribute__ ((aligned (4))) + +/** + * Needed for older GD32F firmware + */ +#if !defined(USART_TRANSMIT_DMA_ENABLE) +# define USART_TRANSMIT_DMA_ENABLE USART_DENT_ENABLE +#endif + +/** + * GD32F10X is different + */ +#if defined(GD32F10X) +# define USART_FLAG_IDLE USART_FLAG_IDLEF +#endif + +/** + * https://www.gd32-dmx.org/memory.html + */ +#if defined (GD32F20X) || defined (GD32F4XX) || defined (GD32H7XX) +# define SECTION_DMA_BUFFER __attribute__ ((section (".dmx"))) +#else +# define SECTION_DMA_BUFFER +#endif + +#if defined (GD32F4XX) || defined (GD32H7XX) +# define DMA_INTERRUPT_ENABLE (DMA_CHXCTL_FTFIE) +# define DMA_INTERRUPT_DISABLE (DMA_CHXCTL_FTFIE | DMA_CHXCTL_HTFIE | DMA_CHXFCTL_FEEIE) +# define DMA_INTERRUPT_FLAG_GET (DMA_INT_FLAG_FTF) +# define DMA_INTERRUPT_FLAG_CLEAR (DMA_INT_FLAG_FTF | DMA_INT_FLAG_TAE) +#else +# define DMA_INTERRUPT_ENABLE (DMA_INT_FTF) +# define DMA_INTERRUPT_DISABLE (DMA_INT_FTF | DMA_INT_HTF | DMA_INT_ERR) +# define DMA_INTERRUPT_FLAG_GET (DMA_INT_FLAG_FTF) +# define DMA_INTERRUPT_FLAG_CLEAR (DMA_INT_FLAG_FTF | DMA_INT_FLAG_G) +#endif + +inline constexpr uint32_t dmx_port_to_uart(const uint32_t nPort) { switch (nPort) { #if defined (DMX_USE_USART0) case dmx::config::USART0_PORT: @@ -85,79 +126,72 @@ static uint32_t _port_to_uart(const uint32_t nPort) { return 0; } -#if defined (GD32F4XX) -// GPIO -static void _gpio_mode_output(uint32_t gpio_periph, uint32_t pin) { - gpio_af_set(gpio_periph, GPIO_AF_0, pin); //TODO This needs some research. Is it really needed? - gpio_mode_set(gpio_periph, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, pin); -} -static void _gpio_mode_af(const uint32_t gpio_periph, uint32_t pin, const uint32_t usart_periph) { - gpio_mode_set(gpio_periph, GPIO_MODE_AF, GPIO_PUPD_PULLUP, pin); - +#if defined (GD32F4XX) || defined (GD32H7XX) +constexpr uint32_t get_usart_af(const uint32_t usart_periph) { switch (usart_periph) { -#if defined (DMX_USE_USART0) - case USART0: -#endif -#if defined (DMX_USE_USART1) +#if defined(DMX_USE_USART0) + case USART0: return USART0_GPIO_AFx; + #endif +#if defined(DMX_USE_USART1) case USART1: + return USART1_GPIO_AFx; #endif -#if defined (DMX_USE_USART2) +#if defined(DMX_USE_USART2) case USART2: + return USART2_GPIO_AFx; #endif -#if defined (DMX_USE_USART0) || defined (DMX_USE_USART1) || defined(DMX_USE_USART2) - gpio_af_set(gpio_periph, GPIO_AF_7, pin); - break; -#endif -#if defined (DMX_USE_UART3) - case UART3: -#endif -#if defined (DMX_USE_UART4) +#if defined(DMX_USE_UART3) + case UART3: return UART3_GPIO_AFx; + #endif +#if defined(DMX_USE_UART4) case UART4: + return UART4_GPIO_AFx; #endif -#if defined (DMX_USE_USART5) +#if defined(DMX_USE_USART5) case USART5: + return USART5_GPIO_AFx; #endif -#if defined (DMX_USE_UART6) +#if defined(DMX_USE_UART6) case UART6: + return UART6_GPIO_AFx; #endif -#if defined (DMX_USE_UART7) +#if defined(DMX_USE_UART7) case UART7: -#endif -#if defined (DMX_USE_UART3) || defined (DMX_USE_UART4) || defined(DMX_USE_USART5) || defined (DMX_USE_UART6) || defined (DMX_USE_UART7) - gpio_af_set(gpio_periph, GPIO_AF_8, pin); - break; + return UART7_GPIO_AFx; #endif default: - assert(0); __builtin_unreachable(); - break; + return 0; } + + __builtin_unreachable(); + return 0; +} + +template +inline void gd32_gpio_mode_output() { + gd32_gpio_mode_set(); +} + +template +inline void gd32_gpio_mode_af() { + gd32_gpio_mode_set(); + + constexpr uint32_t af = get_usart_af(usart_periph); + static_assert(af != 0, "Invalid USART peripheral"); + + gd32_gpio_af_set(); } -// DMA -# define DMA_PARAMETER_STRUCT dma_single_data_parameter_struct -# define DMA_CHMADDR DMA_CHM0ADDR -# define DMA_MEMORY_TO_PERIPHERAL DMA_MEMORY_TO_PERIPH -# define DMA_PERIPHERAL_WIDTH_8BIT DMA_PERIPH_WIDTH_8BIT -# define dma_init dma_single_data_mode_init -# define dma_memory_to_memory_disable(x,y) -# define DMA_INTERRUPT_ENABLE (DMA_CHXCTL_FTFIE) -# define DMA_INTERRUPT_DISABLE (DMA_CHXCTL_FTFIE | DMA_CHXCTL_HTFIE | DMA_CHXFCTL_FEEIE) -# define DMA_INTERRUPT_FLAG_GET (DMA_INT_FLAG_FTF) -# define DMA_INTERRUPT_FLAG_CLEAR (DMA_INT_FLAG_FTF | DMA_INT_FLAG_TAE) #else -// GPIO -static void _gpio_mode_output(uint32_t gpio_periph, uint32_t pin) { - gpio_init(gpio_periph, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, pin); +template +inline void gd32_gpio_mode_output() { + gd32_gpio_init(); } -static void _gpio_mode_af(uint32_t gpio_periph, uint32_t pin, __attribute__((unused)) const uint32_t usart_periph ) { - gpio_init(gpio_periph, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, pin); + +template +inline void gd32_gpio_mode_af() { + gd32_gpio_init(); } -// DMA -# define DMA_PARAMETER_STRUCT dma_parameter_struct -# define DMA_INTERRUPT_ENABLE (DMA_INT_FTF) -# define DMA_INTERRUPT_DISABLE (DMA_INT_FTF | DMA_INT_HTF | DMA_INT_ERR) -# define DMA_INTERRUPT_FLAG_GET (DMA_INT_FLAG_FTF) -# define DMA_INTERRUPT_FLAG_CLEAR (DMA_INT_FLAG_FTF | DMA_INT_FLAG_G) #endif #endif /* GD32_DMX_INTERNAL_H_ */ diff --git a/lib-dmx/src/gd32/rdm.cpp b/lib-dmx/src/gd32/rdm.cpp deleted file mode 100644 index 67145d60..00000000 --- a/lib-dmx/src/gd32/rdm.cpp +++ /dev/null @@ -1,120 +0,0 @@ -/** - * @file rdm.cpp - * - */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@gd32-dmx.org - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include - -#include "rdm.h" - -#include "dmx.h" -#include "dmxconst.h" -#include "dmx_internal.h" - -#include "gd32.h" -#include "gd32_micros.h" -#include "gd32/dmx_config.h" - -#include "debug.h" - -static uint8_t s_TransactionNumber[dmx::config::max::OUT]; -static uint32_t s_nLastSendMicros[dmx::config::max::OUT]; - -extern volatile uint32_t gv_RdmDataReceiveEnd; - -void Rdm::Send(uint32_t nPort, struct TRdmMessage *pRdmMessage, uint32_t nSpacingMicros) { - DEBUG_PRINTF("nPort=%u, pRdmData=%p, nSpacingMicros=%u", nPort, pRdmMessage, nSpacingMicros); - assert(nPort < DMX_MAX_PORTS); - assert(pRdmMessage != nullptr); - - if (nSpacingMicros != 0) { - const auto nMicros = micros(); - const auto nDeltaMicros = nMicros - s_nLastSendMicros[nPort]; - if (nDeltaMicros < nSpacingMicros) { - const auto nWait = nSpacingMicros - nDeltaMicros; - do { - } while ((micros() - nMicros) < nWait); - } - } - - auto *pData = reinterpret_cast(pRdmMessage); - uint32_t i; - uint16_t nChecksum = 0; - - pRdmMessage->transaction_number = s_TransactionNumber[nPort]; - - for (i = 0; i < pRdmMessage->message_length; i++) { - nChecksum = static_cast(nChecksum + pData[i]); - } - - pData[i++] = static_cast(nChecksum >> 8); - pData[i] = static_cast(nChecksum & 0XFF); - - SendRaw(nPort, reinterpret_cast(pRdmMessage), pRdmMessage->message_length + RDM_MESSAGE_CHECKSUM_SIZE); - - s_nLastSendMicros[nPort] = micros(); - s_TransactionNumber[nPort]++; - - DEBUG_EXIT -} - -void Rdm::SendRawRespondMessage(uint32_t nPort, const uint8_t *pRdmData, uint32_t nLength) { - DEBUG_PRINTF("nPort=%u, pRdmData=%p, nLength=%u", nPort, pRdmData, nLength); - assert(nPort < DMX_MAX_PORTS); - assert(pRdmData != nullptr); - assert(nLength != 0); - - // 3.2.2 Responder Packet spacing - udelay(RDM_RESPONDER_PACKET_SPACING, gv_RdmDataReceiveEnd); - - SendRaw(nPort, pRdmData, nLength); -} - -void Rdm::SendDiscoveryRespondMessage(uint32_t nPort, const uint8_t *pRdmData, uint32_t nLength) { - DEBUG_PRINTF("nPort=%u, pRdmData=%p, nLength=%u", nPort, pRdmData, nLength); - assert(nPort < DMX_MAX_PORTS); - assert(pRdmData != nullptr); - assert(nLength != 0); - - // 3.2.2 Responder Packet spacing - udelay(RDM_RESPONDER_PACKET_SPACING, gv_RdmDataReceiveEnd); - - Dmx::Get()->SetPortDirection(nPort, dmx::PortDirection::OUTP, false); - - const auto nUart = _port_to_uart(nPort); - - for (uint32_t i = 0; i < nLength; i++) { - while (RESET == usart_flag_get(nUart, USART_FLAG_TBE)) - ; - USART_DATA(nUart) = static_cast(USART_DATA_DATA & pRdmData[i]); - } - - while (SET != usart_flag_get(nUart, USART_FLAG_TC)) { - static_cast(GET_BITS(USART_DATA(nUart), 0U, 8U)); - } - - udelay(RDM_RESPONDER_DATA_DIRECTION_DELAY); - - Dmx::Get()->SetPortDirection(nPort, dmx::PortDirection::INP, true); -} diff --git a/lib-dmx/src/json_get_ports.cpp b/lib-dmx/src/json_get_ports.cpp new file mode 100755 index 00000000..bf83b23a --- /dev/null +++ b/lib-dmx/src/json_get_ports.cpp @@ -0,0 +1,58 @@ +/** + * @file json_get_ports.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "dmx.h" +#include "dmxconst.h" +#include "lightset.h" + +namespace remoteconfig { +namespace dmx { +static uint32_t get_portstatus(const uint32_t nPortIndex, char *pOutBuffer, const uint32_t nOutBufferSize) { + const auto direction = Dmx::Get()->GetPortDirection(nPortIndex) == ::dmx::PortDirection::INP ? ::lightset::PortDir::INPUT : ::lightset::PortDir::OUTPUT; + auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, + "{\"port\":\"%c\",\"direction\":\"%s\"},", + static_cast('A' + nPortIndex), + lightset::get_direction(direction))); + + return nLength; +} + +uint32_t json_get_ports(char *pOutBuffer, const uint32_t nOutBufferSize) { + pOutBuffer[0] = '['; + uint32_t nLength = 1; + + for (uint32_t nPortIndex = 0; nPortIndex < ::dmx::config::max::PORTS; nPortIndex++) { + nLength += get_portstatus(nPortIndex, &pOutBuffer[nLength], nOutBufferSize - nLength); + } + + pOutBuffer[nLength - 1] = ']'; + + return nLength; +} +} // namespace dmx +} // namespace remoteconfig diff --git a/lib-dmx/src/json_get_portstatus.cpp b/lib-dmx/src/json_get_portstatus.cpp new file mode 100755 index 00000000..90f5965a --- /dev/null +++ b/lib-dmx/src/json_get_portstatus.cpp @@ -0,0 +1,58 @@ +/** + * @file json_get_portstatus.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "dmx.h" +#include "dmxconst.h" + +namespace remoteconfig { +namespace dmx { +uint32_t json_get_portstatus(const char cPort, char *pOutBuffer, const uint32_t nOutBufferSize) { + const uint32_t nPortIndex = (cPort | 0x20) - 'a'; + + if (nPortIndex < ::dmx::config::max::PORTS) { + auto& statistics = Dmx::Get()->GetTotalStatistics(nPortIndex); + auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, + "{\"port\":\"%c\"," + "\"dmx\":{\"sent\":\"%u\",\"received\":\"%u\"}," + "\"rdm\":{\"sent\":{\"class\":\"%u\",\"discovery\":\"%u\"},\"received\":{\"good\":\"%u\",\"bad\":\"%u\",\"discovery\":\"%u\"}}}", + static_cast('A' + nPortIndex), + static_cast(statistics.Dmx.Sent), + static_cast(statistics.Dmx.Received), + static_cast(statistics.Rdm.Sent.Class), + static_cast(statistics.Rdm.Sent.DiscoveryResponse), + static_cast(statistics.Rdm.Received.Good), + static_cast(statistics.Rdm.Received.Bad), + static_cast(statistics.Rdm.Received.DiscoveryResponse))); + + return nLength; + } + + return 0; +} +} // namespace dmx +} // namespace remoteconfig diff --git a/lib-dmxreceiver/.cproject b/lib-dmxreceiver/.cproject deleted file mode 100644 index 5a1b73db..00000000 --- a/lib-dmxreceiver/.cproject +++ /dev/null @@ -1,111 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/lib-dmxreceiver/.project b/lib-dmxreceiver/.project deleted file mode 100644 index 7e096b38..00000000 --- a/lib-dmxreceiver/.project +++ /dev/null @@ -1,27 +0,0 @@ - - - lib-dmxreceiver - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - diff --git a/lib-dmxreceiver/.settings/language.settings.xml b/lib-dmxreceiver/.settings/language.settings.xml deleted file mode 100644 index 55660b04..00000000 --- a/lib-dmxreceiver/.settings/language.settings.xml +++ /dev/null @@ -1,12 +0,0 @@ - - - - - - - - - - - - \ No newline at end of file diff --git a/lib-dmxreceiver/Makefile.GD32 b/lib-dmxreceiver/Makefile.GD32 deleted file mode 100644 index 08083275..00000000 --- a/lib-dmxreceiver/Makefile.GD32 +++ /dev/null @@ -1,5 +0,0 @@ -DEFINES=NDEBUG - -EXTRA_INCLUDES=../lib-dmx/include ../lib-lightset/include - -include ../firmware-template-gd32/lib/Rules.mk \ No newline at end of file diff --git a/lib-dmxreceiver/src/dmxreceiver.cpp b/lib-dmxreceiver/src/dmxreceiver.cpp deleted file mode 100644 index 3a9da4ca..00000000 --- a/lib-dmxreceiver/src/dmxreceiver.cpp +++ /dev/null @@ -1,30 +0,0 @@ -/** - * @file dmxreceiver.cpp - * - */ -/* Copyright (C) 2017-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEconst uint8_t*MENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "dmxreceiver.h" - -LightSet *DMXReceiver::s_pLightSet; -bool DMXReceiver::s_IsActive; -bool DMXReceiver::s_bDisableOutput; diff --git a/lib-dmxsend/.cproject b/lib-dmxsend/.cproject deleted file mode 100644 index 84e9fc95..00000000 --- a/lib-dmxsend/.cproject +++ /dev/null @@ -1,164 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/lib-dmxsend/.project b/lib-dmxsend/.project deleted file mode 100644 index 505bc290..00000000 --- a/lib-dmxsend/.project +++ /dev/null @@ -1,27 +0,0 @@ - - - lib-dmxsend - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - diff --git a/lib-dmxsend/.settings/language.settings.xml b/lib-dmxsend/.settings/language.settings.xml deleted file mode 100644 index 8e3748f8..00000000 --- a/lib-dmxsend/.settings/language.settings.xml +++ /dev/null @@ -1,12 +0,0 @@ - - - - - - - - - - - - \ No newline at end of file diff --git a/lib-dmxsend/.settings/org.eclipse.cdt.core.prefs b/lib-dmxsend/.settings/org.eclipse.cdt.core.prefs deleted file mode 100644 index c8ec5df2..00000000 --- a/lib-dmxsend/.settings/org.eclipse.cdt.core.prefs +++ /dev/null @@ -1,6 +0,0 @@ -doxygen/doxygen_new_line_after_brief=true -doxygen/doxygen_use_brief_tag=false -doxygen/doxygen_use_javadoc_tags=true -doxygen/doxygen_use_pre_tag=false -doxygen/doxygen_use_structural_commands=false -eclipse.preferences.version=1 diff --git a/lib-dmxsend/.settings/org.eclipse.core.resources.prefs b/lib-dmxsend/.settings/org.eclipse.core.resources.prefs deleted file mode 100644 index 99f26c02..00000000 --- a/lib-dmxsend/.settings/org.eclipse.core.resources.prefs +++ /dev/null @@ -1,2 +0,0 @@ -eclipse.preferences.version=1 -encoding/=UTF-8 diff --git a/lib-dmxsend/Makefile.GD32 b/lib-dmxsend/Makefile.GD32 deleted file mode 100644 index bf629e65..00000000 --- a/lib-dmxsend/Makefile.GD32 +++ /dev/null @@ -1,4 +0,0 @@ -DEFINES=NDEBUG -EXTRA_INCLUDES=../lib-dmx/include ../lib-lightset/include - -include ../firmware-template-gd32/lib/Rules.mk \ No newline at end of file diff --git a/lib-dmxsend/include/dmxsend.h b/lib-dmxsend/include/dmxsend.h deleted file mode 100755 index 340a5728..00000000 --- a/lib-dmxsend/include/dmxsend.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * @file dmxsend.h - * - */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef DMXSEND_H_ -#define DMXSEND_H_ - -#include - -#include "lightset.h" -#include "dmx.h" -#include "hardware.h" - -class DmxSend final: public LightSet { -public: - void Start(const uint32_t nPortIndex) override; - void Stop(const uint32_t nPortIndex) override; - - void SetData(uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength, const bool doUpdate = true) override; - void Sync(const uint32_t nPortIndex) override; - void Sync(const bool doForce = false) override; - -#if defined (OUTPUT_HAVE_STYLESWITCH) - void SetOutputStyle(const uint32_t nPortIndex, const lightset::OutputStyle outputStyle) override { - Dmx::Get()->SetOutputStyle(nPortIndex, outputStyle == lightset::OutputStyle::CONSTANT ? dmx::OutputStyle::CONTINOUS : dmx::OutputStyle::DELTA); - } - - lightset::OutputStyle GetOutputStyle(const uint32_t nPortIndex) const override { - return Dmx::Get()->GetOutputStyle(nPortIndex) == dmx::OutputStyle::CONTINOUS ? lightset::OutputStyle::CONSTANT : lightset::OutputStyle::DELTA; - } -#endif - - void Blackout(__attribute__((unused)) bool bBlackout) override { - Dmx::Get()->Blackout(); - } - - void FullOn() override { - Dmx::Get()->FullOn(); - } - -#if defined(LIGHTSET_HAVE_RUN) - void Run() override { - const auto nMillis = Hardware::Get()->Millis(); - if ((nMillis - s_nMillis) > 200) { - s_nMillis = nMillis; - for (uint32_t nPortIndex = 0; nPortIndex < dmx::config::max::OUT; nPortIndex++) { - hal::panel_led_off(hal::panelled::PORT_A_TX << nPortIndex); - } - } - } -#endif - - void Print() override; - -private: - static uint32_t s_nMillis; - - struct TxData { - uint8_t data[dmx::buffer::SIZE]; - uint32_t nLength; - }; - static struct TxData s_TxData[dmx::config::max::OUT]; - - static uint8_t s_nStarted; -}; - -#endif /* DMXSEND_H_ */ diff --git a/lib-dmxsend/src/dmxsend.cpp b/lib-dmxsend/src/dmxsend.cpp deleted file mode 100755 index 1cdb00dc..00000000 --- a/lib-dmxsend/src/dmxsend.cpp +++ /dev/null @@ -1,148 +0,0 @@ -/** - * @file dmxsend.cpp - * - */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#include -#include - -#include "dmxsend.h" -#include "dmx.h" - -#include "panel_led.h" - -#include "debug.h" - -uint32_t DmxSend::s_nMillis; -uint8_t DmxSend::s_nStarted; -struct DmxSend::TxData DmxSend::s_TxData[dmx::config::max::OUT]; - -static constexpr bool is_started(const uint8_t v, const uint32_t p) { - return (v & (1U << p)) == (1U << p); -} - -void DmxSend::Start(const uint32_t nPortIndex) { - DEBUG_ENTRY - DEBUG_PRINTF("nPortIndex=%d", nPortIndex); - - assert(nPortIndex < CHAR_BIT); - - if (is_started(s_nStarted, nPortIndex)) { - DEBUG_EXIT - return; - } - - s_nStarted = static_cast(s_nStarted | (1U << nPortIndex)); - - Dmx::Get()->SetPortDirection(nPortIndex, dmx::PortDirection::OUTP, true); - - if (Dmx::Get()->GetOutputStyle(nPortIndex) == dmx::OutputStyle::CONTINOUS) { - hal::panel_led_on(hal::panelled::PORT_A_TX << nPortIndex); - } - - DEBUG_EXIT -} - -void DmxSend::Stop(const uint32_t nPortIndex) { - DEBUG_ENTRY - DEBUG_PRINTF("nPortIndex=%d -> %u", nPortIndex, is_started(s_nStarted, static_cast(nPortIndex))); - - assert(nPortIndex < CHAR_BIT); - - if (!is_started(s_nStarted, nPortIndex)) { - DEBUG_EXIT - return; - } - - s_nStarted = static_cast(s_nStarted & ~(1U << nPortIndex)); - - Dmx::Get()->SetPortDirection(nPortIndex, dmx::PortDirection::OUTP, false); - - hal::panel_led_off(hal::panelled::PORT_A_TX << nPortIndex); - - DEBUG_EXIT -} - -/** - * - * @param [in] nPortIndex - * @param [in] pData - * @param [in] nLength - * @param [in] doUpdate - */ -void DmxSend::SetData(uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength, const bool doUpdate) { - assert(nPortIndex < CHAR_BIT); - assert(pData != nullptr); - - if (__builtin_expect((nLength == 0), 0)) { - return; - } - - if (doUpdate) { - Dmx::Get()->SetSendDataWithoutSC(nPortIndex, pData, nLength); - Dmx::Get()->StartOutput(nPortIndex); - hal::panel_led_on(hal::panelled::PORT_A_TX << nPortIndex); - } else { - memcpy(s_TxData[nPortIndex].data, pData, nLength); - s_TxData[nPortIndex].nLength = nLength; - } -} - -/** - * - * @param [in] nPortIndex - */ -void DmxSend::Sync(uint32_t const nPortIndex) { - assert(s_TxData[nPortIndex].nLength != 0); - - Dmx::Get()->SetSendDataWithoutSC(nPortIndex, s_TxData[nPortIndex].data, s_TxData[nPortIndex].nLength); -} - -/** - * - * @param [in] doForce - */ -void DmxSend::Sync(const bool doForce) { - Dmx::Get()->SetOutput(doForce); - - for (uint32_t nPortIndex = 0; nPortIndex < dmx::config::max::OUT; nPortIndex++) { - if (s_TxData[nPortIndex].nLength != 0) { - s_TxData[nPortIndex].nLength = 0; - if (!is_started(s_nStarted, nPortIndex)) { - Start(nPortIndex); - } - } - } -} - -#include - -void DmxSend::Print() { - printf("DMX Send\n"); - printf(" Break time : %u\n", Dmx::Get()->GetDmxBreakTime()); - printf(" MAB time : %u\n", Dmx::Get()->GetDmxMabTime()); - printf(" Refresh rate : %u\n", 1000000U / Dmx::Get()->GetDmxPeriodTime()); - printf(" Slots : %u\n", Dmx::Get()->GetDmxSlots()); -} diff --git a/lib-e131/.cproject b/lib-e131/.cproject index d56bc12c..01631fdf 100644 --- a/lib-e131/.cproject +++ b/lib-e131/.cproject @@ -30,11 +30,9 @@ - diff --git a/lib-e131/Rules.mk b/lib-e131/Rules.mk index 17779edd..4dd754e4 100644 --- a/lib-e131/Rules.mk +++ b/lib-e131/Rules.mk @@ -17,6 +17,9 @@ ifneq ($(MAKE_FLAGS),) ifeq ($(findstring NODE_NODE,$(MAKE_FLAGS)), NODE_NODE) EXTRA_SRCDIR+=src/node endif + ifeq ($(findstring OUTPUT_DMX_SEND,$(MAKE_FLAGS)), OUTPUT_DMX_SEND) + EXTRA_INCLUDES+=../lib-dmx/include + endif else EXTRA_SRCDIR+=src/node src/node/dmxin src/controller DEFINES+=E131_HAVE_DMXIN @@ -24,4 +27,6 @@ else DEFINES+=OUTPUT_DMX_SEND DEFINES+=LIGHTSET_PORTS=4 EXTRA_INCLUDES+=../lib-dmx/include + DEFINES+=NODE_SHOWFILE + DEFINES+=CONFIG_SHOWFILE_PROTOCOL_NODE_E131 endif \ No newline at end of file diff --git a/lib-e131/include/e131bridge.h b/lib-e131/include/e131bridge.h old mode 100644 new mode 100755 index 3c09ca8a..bac902a8 --- a/lib-e131/include/e131bridge.h +++ b/lib-e131/include/e131bridge.h @@ -2,7 +2,7 @@ * @file e131bridge.h * */ -/* Copyright (C) 2016-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2016-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -37,11 +37,24 @@ #include "lightset.h" #include "lightsetdata.h" +#if !(ARTNET_VERSION >= 4) +# if defined(OUTPUT_DMX_SEND) || defined(OUTPUT_DMX_SEND_MULTI) +# if !defined(E131_DISABLE_DMX_CONFIG_UDP) +# include "dmxconfigudp.h" +# endif +# endif +#endif + #include "network.h" #include "hardware.h" +#include "panel_led.h" #include "debug.h" +#ifndef ALIGNED +# define ALIGNED __attribute__ ((aligned (4))) +#endif + namespace e131bridge { #if !defined(LIGHTSET_PORTS) # error LIGHTSET_PORTS is not defined @@ -58,13 +71,6 @@ namespace e131bridge { }; struct State { - bool IsNetworkDataLoss; - bool IsMergeMode; - bool IsSynchronized; - bool IsForcedSynchronized; - bool IsChanged; - bool bDisableMergeTimeout; - bool bDisableSynchronize; uint32_t SynchronizationTime; uint32_t DiscoveryTime; uint16_t DiscoveryPacketLength; @@ -76,6 +82,13 @@ struct State { uint8_t nReceivingDmx; lightset::FailSafe failsafe; e131bridge::Status status; + bool IsNetworkDataLoss; + bool IsMergeMode; + bool IsSynchronized; + bool IsForcedSynchronized; + bool IsChanged; + bool bDisableMergeTimeout; + bool bDisableSynchronize; }; struct Bridge { @@ -83,7 +96,7 @@ struct Bridge { uint16_t nUniverse; lightset::PortDir direction; bool bLocalMerge; - } Port[e131bridge::MAX_PORTS]; + } Port[e131bridge::MAX_PORTS] ALIGNED; }; struct Source { @@ -94,12 +107,13 @@ struct Source { }; struct OutputPort { - Source sourceA; - Source sourceB; + Source sourceA ALIGNED; + Source sourceB ALIGNED; lightset::MergeMode mergeMode; lightset::OutputStyle outputStyle; bool IsMerging; bool IsTransmitting; + bool IsDataPending; }; struct InputPort { @@ -215,19 +229,6 @@ class E131Bridge { m_pE131Sync = pE131Sync; } - const uint8_t *GetCid() const { - return m_Cid; - } - - void SetSourceName(const char *pSourceName) { - assert(pSourceName != nullptr); - strncpy(m_SourceName, pSourceName, e131::SOURCE_NAME_LENGTH - 1); - m_SourceName[e131::SOURCE_NAME_LENGTH - 1] = '\0'; - } - const char *GetSourceName() const { - return m_SourceName; - } - void SetPriority(const uint32_t nPortIndex, uint8_t nPriority) { assert(nPortIndex < e131bridge::MAX_PORTS); if ((nPriority >= e131::priority::LOWEST) && (nPriority <= e131::priority::HIGHEST)) { @@ -251,27 +252,12 @@ class E131Bridge { void SetOutputStyle(const uint32_t nPortIndex, lightset::OutputStyle outputStyle) { assert(nPortIndex < e131bridge::MAX_PORTS); - if ((m_State.status == e131bridge::Status::ON) && (m_pLightSet != nullptr)) { + if (m_pLightSet != nullptr) { m_pLightSet->SetOutputStyle(nPortIndex, outputStyle); outputStyle = m_pLightSet->GetOutputStyle(nPortIndex); } m_OutputPort[nPortIndex].outputStyle = outputStyle; - -#if defined (OUTPUT_DMX_SEND) || defined (OUTPUT_DMX_SEND_MULTI) - /** - * FIXME I do not like this hack. It should be handled in dmx.cpp - */ - if (m_Bridge.Port[nPortIndex].direction == lightset::PortDir::OUTPUT - && (outputStyle == lightset::OutputStyle::CONSTANT) - && (m_pLightSet != nullptr)) { - if (m_OutputPort[nPortIndex].IsTransmitting) { - m_OutputPort[nPortIndex].IsTransmitting = false; - m_pLightSet->Stop(nPortIndex); - } - } -#endif - } lightset::OutputStyle GetOutputStyle(const uint32_t nPortIndex) const { @@ -293,6 +279,21 @@ class E131Bridge { m_State.IsNetworkDataLoss = false; // Force timeout } +#if defined (E131_HAVE_DMXIN) || defined (NODE_SHOWFILE) + void SetSourceName(const char *pSourceName) { + assert(pSourceName != nullptr); + strncpy(m_SourceName, pSourceName, e131::SOURCE_NAME_LENGTH - 1); + m_SourceName[e131::SOURCE_NAME_LENGTH - 1] = '\0'; + } + const char *GetSourceName() const { + return m_SourceName; + } + + const uint8_t *GetCid() const { + return m_Cid; + } +#endif + void Start(); void Stop(); @@ -339,13 +340,31 @@ class E131Bridge { Process(); -#if defined (LIGHTSET_HAVE_RUN) -# if (ARTNET_VERSION < 4) - m_pLightSet->Run(); -# endif +#if !(ARTNET_VERSION >= 4) + if ((m_nCurrentPacketMillis - m_nPreviousLedpanelMillis) > 200) { + m_nPreviousLedpanelMillis = m_nCurrentPacketMillis; + for (uint32_t nPortIndex = 0; nPortIndex < e131bridge::MAX_PORTS; nPortIndex++) { + hal::panel_led_off(hal::panelled::PORT_A_TX << nPortIndex); +#if defined (E131_HAVE_DMXIN) + hal::panel_led_off(hal::panelled::PORT_A_RX << nPortIndex); +#endif + } + } +#endif +#if defined (DMXCONFIGUDP_H) + m_DmxConfigUdp.Run(); #endif } +#if defined (NODE_SHOWFILE) && defined (CONFIG_SHOWFILE_PROTOCOL_NODE_E131) + void HandleShowFile(const TE131DataPacket *pE131DataPacket) { + m_nCurrentPacketMillis = Hardware::Get()->Millis(); + m_nIpAddressFrom = Network::Get()->GetIp(); + m_pReceiveBuffer = reinterpret_cast(const_cast(pE131DataPacket)); + HandleDmx(); + } +#endif + void Print(); static E131Bridge* Get() { @@ -382,12 +401,7 @@ class E131Bridge { uint32_t m_nCurrentPacketMillis { 0 }; uint32_t m_nPreviousPacketMillis { 0 }; - - TE131DataPacket *m_pE131DataPacket { nullptr }; - TE131DiscoveryPacket *m_pE131DiscoveryPacket { nullptr }; - uint32_t m_DiscoveryIpAddress { 0 }; - uint8_t m_Cid[e131::CID_LENGTH]; - char m_SourceName[e131::SOURCE_NAME_LENGTH]; + uint32_t m_nPreviousLedpanelMillis { 0 }; e131bridge::State m_State; e131bridge::Bridge m_Bridge; @@ -403,6 +417,24 @@ class E131Bridge { // Synchronization handler E131Sync *m_pE131Sync { nullptr }; +#if defined (E131_HAVE_DMXIN) || defined (NODE_SHOWFILE) + char m_SourceName[e131::SOURCE_NAME_LENGTH]; + uint8_t m_Cid[e131::CID_LENGTH]; +#endif + +#if defined (E131_HAVE_DMXIN) + TE131DataPacket m_E131DataPacket; + TE131DiscoveryPacket m_E131DiscoveryPacket; + uint32_t m_DiscoveryIpAddress { 0 }; +#endif + +#if defined (DMXCONFIGUDP_H_) +# if defined (ARTNET_VERSION) +# error +# endif + DmxConfigUdp m_DmxConfigUdp; +#endif + static E131Bridge *s_pThis; }; diff --git a/lib-e131/include/e131bridgeconst.h b/lib-e131/include/e131const.h similarity index 84% rename from lib-e131/include/e131bridgeconst.h rename to lib-e131/include/e131const.h index 79ea3246..a23212e5 100644 --- a/lib-e131/include/e131bridgeconst.h +++ b/lib-e131/include/e131const.h @@ -1,8 +1,8 @@ /** - * @file e131bridgeconst.h + * @file e131const.h * */ -/* Copyright (C) 2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,13 +23,13 @@ * THE SOFTWARE. */ -#ifndef E131BRIDGECONST_H_ -#define E131BRIDGECONST_H_ +#ifndef E131CONST_H_ +#define E131CONST_H_ #include -struct E131BridgeConst { +struct E131Const { static const uint8_t VERSION[]; }; -#endif /* E131BRIDGECONST_H_ */ +#endif /* E131CONST_H_ */ diff --git a/lib-e131/include/e131controller.h b/lib-e131/include/e131controller.h index 13b24f00..ef6f6d3d 100644 --- a/lib-e131/include/e131controller.h +++ b/lib-e131/include/e131controller.h @@ -2,7 +2,7 @@ * @file e131controller.h * */ -/* Copyright (C) 2020-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-e131/include/e131msgconst.h b/lib-e131/include/e131msgconst.h index 3b656c37..c0c4e5e4 100644 --- a/lib-e131/include/e131msgconst.h +++ b/lib-e131/include/e131msgconst.h @@ -2,7 +2,7 @@ * @file e131msgconst.h * */ -/* Copyright (C) 2019-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,7 +27,6 @@ #define E131MSGCONST_H_ struct E131MsgConst { - static const char PARAMS[]; static const char START[]; static const char STARTED[]; }; diff --git a/lib-e131/include/e131packets.h b/lib-e131/include/e131packets.h index 3f0bae68..e13d3091 100644 --- a/lib-e131/include/e131packets.h +++ b/lib-e131/include/e131packets.h @@ -2,7 +2,7 @@ * @file e131packets.h * */ -/* Copyright (C) 2016-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2016-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-e131/include/e131params.h b/lib-e131/include/e131params.h index 24fdfee6..003f62be 100644 --- a/lib-e131/include/e131params.h +++ b/lib-e131/include/e131params.h @@ -2,7 +2,7 @@ * @file e131params.h * */ -/* Copyright (C) 2016-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2016-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,6 +29,7 @@ #include #include "e131bridge.h" +#include "configstore.h" #include "lightset.h" #if !defined(LIGHTSET_PORTS) @@ -112,15 +113,18 @@ struct Mask { class E131ParamsStore { public: - virtual ~E131ParamsStore() {} + static void Update(const struct e131params::Params *pParams) { + ConfigStore::Get()->Update(configstore::Store::NODE, pParams, sizeof(struct e131params::Params)); + } - virtual void Update(const e131params::Params *pParams)=0; - virtual void Copy(e131params::Params *pParams)=0; + static void Copy(struct e131params::Params *pParams) { + ConfigStore::Get()->Copy(configstore::Store::NODE, pParams, sizeof(struct e131params::Params)); + } }; class E131Params { public: - E131Params(E131ParamsStore *pE131ParamsStore); + E131Params(); bool Load(); void Load(const char *pBuffer, uint32_t nLength); @@ -130,9 +134,7 @@ class E131Params { Builder(nullptr, pBuffer, nLength, nSize); } - void Set(uint32_t nPortIndexOffset); - - void Dump(); + void Set(); uint16_t GetUniverse(uint32_t nPortIndex, bool &IsSet) const { if (nPortIndex < e131params::MAX_PORTS) { @@ -162,15 +164,10 @@ class E131Params { } #endif -#if defined (ESP8266) - lightset::OutputType GetOutputType() const { - return static_cast(m_Params.Filler1); - } -#endif - static void staticCallbackFunction(void *p, const char *s); private: + void Dump(); void callbackFunction(const char *s); bool isMaskSet(uint32_t nMask) const { return (m_Params.nSetList & nMask) == nMask; @@ -184,7 +181,6 @@ class E131Params { } private: - E131ParamsStore *m_pE131ParamsStore; e131params::Params m_Params; }; diff --git a/lib-e131/include/e131paramsconst.h b/lib-e131/include/e131paramsconst.h index b2154b14..403e274e 100644 --- a/lib-e131/include/e131paramsconst.h +++ b/lib-e131/include/e131paramsconst.h @@ -2,7 +2,7 @@ * @file e131paramsconst.h * */ -/* Copyright (C) 2019-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-e131/include/e131sync.h b/lib-e131/include/e131sync.h index e7da3b34..6d19c69e 100644 --- a/lib-e131/include/e131sync.h +++ b/lib-e131/include/e131sync.h @@ -3,7 +3,7 @@ * */ -/* Copyright (C) 2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,7 +29,7 @@ class E131Sync { public: - virtual ~E131Sync() {} + virtual ~E131Sync() = default; virtual void Handler()=0; }; diff --git a/lib-e131/src/controller/e131controller.cpp b/lib-e131/src/controller/e131controller.cpp index 0f185ea1..fe0c66ca 100644 --- a/lib-e131/src/controller/e131controller.cpp +++ b/lib-e131/src/controller/e131controller.cpp @@ -2,7 +2,7 @@ * @file e131controller.cpp * */ -/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -362,7 +362,7 @@ uint8_t E131Controller::GetSequenceNumber(uint16_t nUniverse, uint32_t &nMultica } void E131Controller::Print() { - printf("sACN E1.31 Controller\n"); + puts("sACN E1.31 Controller"); printf(" Max Universes : %d\n", static_cast(sizeof(s_SequenceNumbers) / sizeof(s_SequenceNumbers[0]))); if (m_State.SynchronizationPacket.nUniverseNumber != 0) { printf(" Synchronization Universe : %u\n", m_State.SynchronizationPacket.nUniverseNumber); diff --git a/lib-e131/src/node/e131bridgeconst.cpp b/lib-e131/src/e131const.cpp old mode 100644 new mode 100755 similarity index 86% rename from lib-e131/src/node/e131bridgeconst.cpp rename to lib-e131/src/e131const.cpp index eb5ad36e..23696402 --- a/lib-e131/src/node/e131bridgeconst.cpp +++ b/lib-e131/src/e131const.cpp @@ -1,8 +1,8 @@ /** - * @file e131bridgeconst.cpp + * @file e131const.cpp * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -25,6 +25,6 @@ #include -#include "e131bridgeconst.h" +#include "e131const.h" -const uint8_t E131BridgeConst::VERSION[] = { 1, 27 }; +const uint8_t E131Const::VERSION[] = { 1, 27 }; diff --git a/lib-e131/src/node/dmxin/discoverypacket.cpp b/lib-e131/src/node/dmxin/discoverypacket.cpp index ecc78115..95a6fc27 100644 --- a/lib-e131/src/node/dmxin/discoverypacket.cpp +++ b/lib-e131/src/node/dmxin/discoverypacket.cpp @@ -2,7 +2,7 @@ * @file e131bridgediscoverypacket * */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -36,23 +36,23 @@ void E131Bridge::FillDiscoveryPacket() { m_State.DiscoveryPacketLength = static_cast(DISCOVERY_PACKET_SIZE(m_State.nEnabledInputPorts)); - memset(m_pE131DiscoveryPacket, 0, sizeof(struct TE131DiscoveryPacket)); + memset(&m_E131DiscoveryPacket, 0, sizeof(struct TE131DiscoveryPacket)); // Root Layer (See Section 5) - m_pE131DiscoveryPacket->RootLayer.PreAmbleSize = __builtin_bswap16(0x10); - memcpy(m_pE131DiscoveryPacket->RootLayer.ACNPacketIdentifier, E117Const::ACN_PACKET_IDENTIFIER, e117::PACKET_IDENTIFIER_LENGTH); - m_pE131DiscoveryPacket->RootLayer.FlagsLength = __builtin_bswap16(static_cast((0x07 << 12) | (DISCOVERY_ROOT_LAYER_LENGTH(m_State.nEnabledInputPorts)))); - m_pE131DiscoveryPacket->RootLayer.Vector = __builtin_bswap32(e131::vector::root::EXTENDED); - memcpy(m_pE131DiscoveryPacket->RootLayer.Cid, m_Cid, e131::CID_LENGTH); + m_E131DiscoveryPacket.RootLayer.PreAmbleSize = __builtin_bswap16(0x10); + memcpy(m_E131DiscoveryPacket.RootLayer.ACNPacketIdentifier, E117Const::ACN_PACKET_IDENTIFIER, e117::PACKET_IDENTIFIER_LENGTH); + m_E131DiscoveryPacket.RootLayer.FlagsLength = __builtin_bswap16(static_cast((0x07 << 12) | (DISCOVERY_ROOT_LAYER_LENGTH(m_State.nEnabledInputPorts)))); + m_E131DiscoveryPacket.RootLayer.Vector = __builtin_bswap32(e131::vector::root::EXTENDED); + memcpy(m_E131DiscoveryPacket.RootLayer.Cid, m_Cid, e131::CID_LENGTH); // E1.31 Framing Layer (See Section 6) - m_pE131DiscoveryPacket->FrameLayer.FLagsLength = __builtin_bswap16(static_cast((0x07 << 12) | (DISCOVERY_FRAME_LAYER_LENGTH(m_State.nEnabledInputPorts)))); - m_pE131DiscoveryPacket->FrameLayer.Vector = __builtin_bswap32(e131::vector::extended::DISCOVERY); - memcpy(m_pE131DiscoveryPacket->FrameLayer.SourceName, m_SourceName, e131::SOURCE_NAME_LENGTH); + m_E131DiscoveryPacket.FrameLayer.FLagsLength = __builtin_bswap16(static_cast((0x07 << 12) | (DISCOVERY_FRAME_LAYER_LENGTH(m_State.nEnabledInputPorts)))); + m_E131DiscoveryPacket.FrameLayer.Vector = __builtin_bswap32(e131::vector::extended::DISCOVERY); + memcpy(m_E131DiscoveryPacket.FrameLayer.SourceName, m_SourceName, e131::SOURCE_NAME_LENGTH); // Universe Discovery Layer (See Section 8) - m_pE131DiscoveryPacket->UniverseDiscoveryLayer.FlagsLength = __builtin_bswap16(static_cast((0x07 << 12) | DISCOVERY_LAYER_LENGTH(m_State.nEnabledInputPorts))); - m_pE131DiscoveryPacket->UniverseDiscoveryLayer.Vector = __builtin_bswap32(e131::vector::universe::DISCOVERY_UNIVERSE_LIST); + m_E131DiscoveryPacket.UniverseDiscoveryLayer.FlagsLength = __builtin_bswap16(static_cast((0x07 << 12) | DISCOVERY_LAYER_LENGTH(m_State.nEnabledInputPorts))); + m_E131DiscoveryPacket.UniverseDiscoveryLayer.Vector = __builtin_bswap32(e131::vector::universe::DISCOVERY_UNIVERSE_LIST); } void E131Bridge::SendDiscoveryPacket() { @@ -67,11 +67,11 @@ void E131Bridge::SendDiscoveryPacket() { for (uint32_t i = 0; i < e131bridge::MAX_PORTS; i++) { uint16_t nUniverse; if (GetUniverse(i, nUniverse, lightset::PortDir::INPUT)) { - m_pE131DiscoveryPacket->UniverseDiscoveryLayer.ListOfUniverses[nListOfUniverses++] = __builtin_bswap16(nUniverse); + m_E131DiscoveryPacket.UniverseDiscoveryLayer.ListOfUniverses[nListOfUniverses++] = __builtin_bswap16(nUniverse); } } - Network::Get()->SendTo(m_nHandle, m_pE131DiscoveryPacket, m_State.DiscoveryPacketLength, m_DiscoveryIpAddress, e131::UDP_PORT); + Network::Get()->SendTo(m_nHandle, &m_E131DiscoveryPacket, m_State.DiscoveryPacketLength, m_DiscoveryIpAddress, e131::UDP_PORT); } } } diff --git a/lib-e131/src/node/dmxin/handledmxin.cpp b/lib-e131/src/node/dmxin/handledmxin.cpp index bf292b9f..1c304ce5 100644 --- a/lib-e131/src/node/dmxin/handledmxin.cpp +++ b/lib-e131/src/node/dmxin/handledmxin.cpp @@ -2,7 +2,7 @@ * @file e131bridgehandledmxin.cpp * */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -43,50 +43,49 @@ void E131Bridge::FillDataPacket() { // Root Layer (See Section 5) - m_pE131DataPacket->RootLayer.PreAmbleSize = __builtin_bswap16(0x0010); - m_pE131DataPacket->RootLayer.PostAmbleSize = __builtin_bswap16(0x0000); - memcpy(m_pE131DataPacket->RootLayer.ACNPacketIdentifier, E117Const::ACN_PACKET_IDENTIFIER, e117::PACKET_IDENTIFIER_LENGTH); - m_pE131DataPacket->RootLayer.Vector = __builtin_bswap32(e131::vector::root::DATA); - memcpy(m_pE131DataPacket->RootLayer.Cid, m_Cid, e131::CID_LENGTH); + m_E131DataPacket.RootLayer.PreAmbleSize = __builtin_bswap16(0x0010); + m_E131DataPacket.RootLayer.PostAmbleSize = __builtin_bswap16(0x0000); + memcpy(m_E131DataPacket.RootLayer.ACNPacketIdentifier, E117Const::ACN_PACKET_IDENTIFIER, e117::PACKET_IDENTIFIER_LENGTH); + m_E131DataPacket.RootLayer.Vector = __builtin_bswap32(e131::vector::root::DATA); + memcpy(m_E131DataPacket.RootLayer.Cid, m_Cid, e131::CID_LENGTH); // E1.31 Framing Layer (See Section 6) - m_pE131DataPacket->FrameLayer.Vector = __builtin_bswap32(e131::vector::data::PACKET); - memcpy(m_pE131DataPacket->FrameLayer.SourceName, m_SourceName, e131::SOURCE_NAME_LENGTH); - m_pE131DataPacket->FrameLayer.SynchronizationAddress = __builtin_bswap16(0); // Currently not supported - m_pE131DataPacket->FrameLayer.Options = 0; + m_E131DataPacket.FrameLayer.Vector = __builtin_bswap32(e131::vector::data::PACKET); + memcpy(m_E131DataPacket.FrameLayer.SourceName, m_SourceName, e131::SOURCE_NAME_LENGTH); + m_E131DataPacket.FrameLayer.SynchronizationAddress = __builtin_bswap16(0); // Currently not supported + m_E131DataPacket.FrameLayer.Options = 0; // Data Layer - m_pE131DataPacket->DMPLayer.Vector = e131::vector::dmp::SET_PROPERTY; - m_pE131DataPacket->DMPLayer.Type = 0xa1; - m_pE131DataPacket->DMPLayer.FirstAddressProperty = __builtin_bswap16(0x0000); - m_pE131DataPacket->DMPLayer.AddressIncrement = __builtin_bswap16(0x0001); + m_E131DataPacket.DMPLayer.Vector = e131::vector::dmp::SET_PROPERTY; + m_E131DataPacket.DMPLayer.Type = 0xa1; + m_E131DataPacket.DMPLayer.FirstAddressProperty = __builtin_bswap16(0x0000); + m_E131DataPacket.DMPLayer.AddressIncrement = __builtin_bswap16(0x0001); } static uint32_t s_ReceivingMask = 0; void E131Bridge::HandleDmxIn() { for (uint32_t nPortIndex = 0 ; nPortIndex < e131bridge::MAX_PORTS; nPortIndex++) { - if ((m_Bridge.Port[nPortIndex].direction == lightset::PortDir::INPUT) - && (!m_InputPort[nPortIndex].IsDisabled)) { + if ((m_Bridge.Port[nPortIndex].direction == lightset::PortDir::INPUT) && (!m_InputPort[nPortIndex].IsDisabled)) { const auto *const pDmxData = reinterpret_cast(Dmx::Get()->GetDmxChanged(nPortIndex)); if (pDmxData != nullptr) { // Root Layer (See Section 5) auto nLength = (1U + pDmxData->Statistics.nSlotsInPacket); // Add 1 for SC - m_pE131DataPacket->RootLayer.FlagsLength = __builtin_bswap16(static_cast((0x07 << 12) | (DATA_ROOT_LAYER_LENGTH(nLength)))); + m_E131DataPacket.RootLayer.FlagsLength = __builtin_bswap16(static_cast((0x07 << 12) | (DATA_ROOT_LAYER_LENGTH(nLength)))); // E1.31 Framing Layer (See Section 6) - m_pE131DataPacket->FrameLayer.FLagsLength = __builtin_bswap16(static_cast((0x07 << 12) | (DATA_FRAME_LAYER_LENGTH(nLength)))); - m_pE131DataPacket->FrameLayer.Priority = m_InputPort[nPortIndex].nPriority; - m_pE131DataPacket->FrameLayer.SequenceNumber = m_InputPort[nPortIndex].nSequenceNumber++; - m_pE131DataPacket->FrameLayer.Universe = __builtin_bswap16(m_Bridge.Port[nPortIndex].nUniverse); + m_E131DataPacket.FrameLayer.FLagsLength = __builtin_bswap16(static_cast((0x07 << 12) | (DATA_FRAME_LAYER_LENGTH(nLength)))); + m_E131DataPacket.FrameLayer.Priority = m_InputPort[nPortIndex].nPriority; + m_E131DataPacket.FrameLayer.SequenceNumber = m_InputPort[nPortIndex].nSequenceNumber++; + m_E131DataPacket.FrameLayer.Universe = __builtin_bswap16(m_Bridge.Port[nPortIndex].nUniverse); // Data Layer - m_pE131DataPacket->DMPLayer.FlagsLength = __builtin_bswap16(static_cast((0x07 << 12) | (DATA_LAYER_LENGTH(nLength)))); - memcpy(m_pE131DataPacket->DMPLayer.PropertyValues, pDmxData, nLength); - m_pE131DataPacket->DMPLayer.PropertyValueCount = __builtin_bswap16(static_cast(nLength)); + m_E131DataPacket.DMPLayer.FlagsLength = __builtin_bswap16(static_cast((0x07 << 12) | (DATA_LAYER_LENGTH(nLength)))); + memcpy(m_E131DataPacket.DMPLayer.PropertyValues, pDmxData, nLength); + m_E131DataPacket.DMPLayer.PropertyValueCount = __builtin_bswap16(static_cast(nLength)); - Network::Get()->SendTo(m_nHandle, m_pE131DataPacket, static_cast(DATA_PACKET_SIZE(nLength)), m_InputPort[nPortIndex].nMulticastIp, e131::UDP_PORT); + Network::Get()->SendTo(m_nHandle, &m_E131DataPacket, DATA_PACKET_SIZE(nLength), m_InputPort[nPortIndex].nMulticastIp, e131::UDP_PORT); if (m_Bridge.Port[nPortIndex].bLocalMerge) { - m_pReceiveBuffer = reinterpret_cast(m_pE131DataPacket); + m_pReceiveBuffer = reinterpret_cast(&m_E131DataPacket); m_nIpAddressFrom = Network::Get()->GetIp(); HandleDmx(); } @@ -124,21 +123,21 @@ void E131Bridge::HandleDmxIn() { const auto *const pDmxData = reinterpret_cast(Dmx::Get()->GetDmxCurrentData(nPortIndex)); // Root Layer (See Section 5) auto nLength = (1U + pDmxData->Statistics.nSlotsInPacket); // Add 1 for SC - m_pE131DataPacket->RootLayer.FlagsLength = __builtin_bswap16(static_cast((0x07 << 12) | (DATA_ROOT_LAYER_LENGTH(nLength)))); + m_E131DataPacket.RootLayer.FlagsLength = __builtin_bswap16(static_cast((0x07 << 12) | (DATA_ROOT_LAYER_LENGTH(nLength)))); // E1.31 Framing Layer (See Section 6) - m_pE131DataPacket->FrameLayer.FLagsLength = __builtin_bswap16(static_cast((0x07 << 12) | (DATA_FRAME_LAYER_LENGTH(nLength)))); - m_pE131DataPacket->FrameLayer.Priority = m_InputPort[nPortIndex].nPriority; - m_pE131DataPacket->FrameLayer.SequenceNumber = m_InputPort[nPortIndex].nSequenceNumber++; - m_pE131DataPacket->FrameLayer.Universe = __builtin_bswap16(m_Bridge.Port[nPortIndex].nUniverse); + m_E131DataPacket.FrameLayer.FLagsLength = __builtin_bswap16(static_cast((0x07 << 12) | (DATA_FRAME_LAYER_LENGTH(nLength)))); + m_E131DataPacket.FrameLayer.Priority = m_InputPort[nPortIndex].nPriority; + m_E131DataPacket.FrameLayer.SequenceNumber = m_InputPort[nPortIndex].nSequenceNumber++; + m_E131DataPacket.FrameLayer.Universe = __builtin_bswap16(m_Bridge.Port[nPortIndex].nUniverse); // Data Layer - m_pE131DataPacket->DMPLayer.FlagsLength = __builtin_bswap16(static_cast((0x07 << 12) | (DATA_LAYER_LENGTH(nLength)))); - memcpy(m_pE131DataPacket->DMPLayer.PropertyValues, pDmxData, nLength); - m_pE131DataPacket->DMPLayer.PropertyValueCount = __builtin_bswap16(static_cast(nLength)); + m_E131DataPacket.DMPLayer.FlagsLength = __builtin_bswap16(static_cast((0x07 << 12) | (DATA_LAYER_LENGTH(nLength)))); + memcpy(m_E131DataPacket.DMPLayer.PropertyValues, pDmxData, nLength); + m_E131DataPacket.DMPLayer.PropertyValueCount = __builtin_bswap16(static_cast(nLength)); - Network::Get()->SendTo(m_nHandle, m_pE131DataPacket, static_cast(DATA_PACKET_SIZE(nLength)), m_InputPort[nPortIndex].nMulticastIp, e131::UDP_PORT); + Network::Get()->SendTo(m_nHandle, &m_E131DataPacket, DATA_PACKET_SIZE(nLength), m_InputPort[nPortIndex].nMulticastIp, e131::UDP_PORT); if (m_Bridge.Port[nPortIndex].bLocalMerge) { - m_pReceiveBuffer = reinterpret_cast(&m_pE131DataPacket); + m_pReceiveBuffer = reinterpret_cast(&m_E131DataPacket); m_nIpAddressFrom = Network::Get()->GetIp(); HandleDmx(); } diff --git a/lib-e131/src/node/e131bridge.cpp b/lib-e131/src/node/e131bridge.cpp index bb1e06d3..01e97c19 100755 --- a/lib-e131/src/node/e131bridge.cpp +++ b/lib-e131/src/node/e131bridge.cpp @@ -23,6 +23,12 @@ * THE SOFTWARE. */ +#if !defined(__clang__) +# pragma GCC push_options +# pragma GCC optimize ("O2") +# pragma GCC optimize ("no-tree-loop-distribute-patterns") +#endif + #include #include #include @@ -71,7 +77,7 @@ E131Bridge::E131Bridge() { m_InputPort[i].nPriority = 100; } -#if defined (E131_HAVE_DMXIN) +#if defined (E131_HAVE_DMXIN) || defined (NODE_SHOWFILE) char aSourceName[e131::SOURCE_NAME_LENGTH]; uint8_t nLength; snprintf(aSourceName, e131::SOURCE_NAME_LENGTH, "%.48s %s", Network::Get()->GetHostName(), Hardware::Get()->GetBoardName(nLength)); @@ -94,18 +100,10 @@ E131Bridge::~E131Bridge() { void E131Bridge::Start() { #if defined (E131_HAVE_DMXIN) - if (m_pE131DataPacket == nullptr) { - const auto nIpMulticast = network::convert_to_uint(239, 255, 0, 0); - m_DiscoveryIpAddress = nIpMulticast | ((e131::universe::DISCOVERY & static_cast(0xFF)) << 24) | ((e131::universe::DISCOVERY & 0xFF00) << 8); - // TE131DataPacket - m_pE131DataPacket = new TE131DataPacket; - assert(m_pE131DataPacket != nullptr); - FillDataPacket(); - // TE131DiscoveryPacket - m_pE131DiscoveryPacket = new TE131DiscoveryPacket; - assert(m_pE131DiscoveryPacket != nullptr); - FillDiscoveryPacket(); - } + const auto nIpMulticast = network::convert_to_uint(239, 255, 0, 0); + m_DiscoveryIpAddress = nIpMulticast | ((e131::universe::DISCOVERY & static_cast(0xFF)) << 24) | ((e131::universe::DISCOVERY & 0xFF00) << 8); + FillDataPacket(); + FillDiscoveryPacket(); for (uint32_t nPortIndex = 0; nPortIndex < e131bridge::MAX_PORTS; nPortIndex++) { if (m_Bridge.Port[nPortIndex].direction == lightset::PortDir::INPUT) { @@ -580,6 +578,7 @@ void E131Bridge::HandleDmx() { } } else { lightset::Data::Set(m_pLightSet, nPortIndex); + m_OutputPort[nPortIndex].IsDataPending = true; } m_State.nReceivingDmx |= (1U << static_cast(lightset::PortDir::OUTPUT)); diff --git a/lib-e131/src/node/e131bridgehandlesynchronization.cpp b/lib-e131/src/node/e131bridgehandlesynchronization.cpp index c38b404d..5692e280 100755 --- a/lib-e131/src/node/e131bridgehandlesynchronization.cpp +++ b/lib-e131/src/node/e131bridgehandlesynchronization.cpp @@ -2,7 +2,7 @@ * @file e131bridgehandlesynchronization.cpp * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -52,17 +52,18 @@ void E131Bridge::HandleSynchronization() { m_State.SynchronizationTime = m_nCurrentPacketMillis; for (uint32_t nPortIndex = 0; nPortIndex < e131bridge::MAX_PORTS; nPortIndex++) { - if (m_Bridge.Port[nPortIndex].direction == lightset::PortDir::OUTPUT) { + if (m_OutputPort[nPortIndex].IsDataPending) { m_pLightSet->Sync(nPortIndex); } } m_pLightSet->Sync(); - for (uint32_t nPortIndex = 0; nPortIndex < e131bridge::MAX_PORTS; nPortIndex++) { - if (m_Bridge.Port[nPortIndex].direction == lightset::PortDir::OUTPUT) { - if (!m_OutputPort[nPortIndex].IsTransmitting) { - m_OutputPort[nPortIndex].IsTransmitting = true; + for (auto &outputPort : m_OutputPort) { + if (outputPort.IsDataPending) { + outputPort.IsDataPending = false; + if (!outputPort.IsTransmitting) { + outputPort.IsTransmitting = true; m_State.IsChanged = true; } } diff --git a/lib-e131/src/node/e131bridgeprint.cpp b/lib-e131/src/node/e131bridgeprint.cpp index 8450877e..55029594 100644 --- a/lib-e131/src/node/e131bridgeprint.cpp +++ b/lib-e131/src/node/e131bridgeprint.cpp @@ -2,7 +2,7 @@ * @file e131bridgeprint.cpp * */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ #include #include "e131bridge.h" -#include "e131bridgeconst.h" +#include "e131const.h" #include "e131.h" #if defined (E131_HAVE_DMXIN) @@ -46,8 +46,7 @@ void E131Bridge::Print() { uuid_str[UUID_STRING_LENGTH] = '\0'; uuid_unparse(m_Cid, uuid_str); #endif - printf("Bridge\n"); - printf(" Firmware : %d.%d\n", E131BridgeConst::VERSION[0], E131BridgeConst::VERSION[1]); + printf("sACN E1.31 V%d.%d\n", E131Const::VERSION[0], E131Const::VERSION[1]); #if defined (E131_HAVE_DMXIN) printf(" CID : %s\n", uuid_str); #endif @@ -57,7 +56,7 @@ void E131Bridge::Print() { for (uint32_t nPortIndex = 0; nPortIndex < e131bridge::MAX_PORTS; nPortIndex++) { uint16_t nUniverse; if (GetUniverse(nPortIndex, nUniverse, lightset::PortDir::OUTPUT)) { - printf(" Port %-2d %-4u %s\n", nPortIndex, nUniverse, lightset::get_merge_mode(m_OutputPort[nPortIndex].mergeMode, true)); + printf(" Port %-2u %-4u %s\n", static_cast(nPortIndex), static_cast(nUniverse), lightset::get_merge_mode(m_OutputPort[nPortIndex].mergeMode, true)); } } } @@ -69,7 +68,7 @@ void E131Bridge::Print() { for (uint32_t nPortIndex = 0; nPortIndex < e131bridge::MAX_PORTS; nPortIndex++) { uint16_t nUniverse; if (GetUniverse(nPortIndex, nUniverse, lightset::PortDir::INPUT)) { - printf(" Port %-2d %-4u %-3u\n", nPortIndex, nUniverse, GetPriority(nPortIndex)); + printf(" Port %-2u %-4u %-3u\n", static_cast(nPortIndex), static_cast(nUniverse), GetPriority(nPortIndex)); } } } diff --git a/lib-e131/src/node/e131msgconst.cpp b/lib-e131/src/node/e131msgconst.cpp index 9044fdc5..82af7dd6 100644 --- a/lib-e131/src/node/e131msgconst.cpp +++ b/lib-e131/src/node/e131msgconst.cpp @@ -2,7 +2,7 @@ * @file e131mgsconst.cpp * */ -/* Copyright (C) 2019-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -25,6 +25,5 @@ #include "e131msgconst.h" -const char E131MsgConst::PARAMS[] = "Configuring sACN E1.31"; const char E131MsgConst::START[] = "Starting sACN E1.31"; const char E131MsgConst::STARTED[] = "sACN E1.31 started"; diff --git a/lib-e131/src/node/e131params.cpp b/lib-e131/src/node/e131params.cpp index 2084edb8..f06c99cc 100644 --- a/lib-e131/src/node/e131params.cpp +++ b/lib-e131/src/node/e131params.cpp @@ -2,7 +2,7 @@ * @file e131params.cpp * */ -/* Copyright (C) 2016-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2016-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -48,6 +48,12 @@ #include "debug.h" +namespace e131bridge { +namespace configstore { +extern uint32_t DMXPORT_OFFSET; +} // namespace configstore +} // namespace e131bridge + static uint32_t s_nPortsMax; namespace e131params { @@ -62,7 +68,7 @@ static constexpr uint16_t portdir_clear(const uint32_t i) { using namespace e131params; -E131Params::E131Params(E131ParamsStore *pE131ParamsStore):m_pE131ParamsStore(pE131ParamsStore) { +E131Params::E131Params() { DEBUG_ENTRY DEBUG_PRINTF("sizeof(struct Params)=%d", static_cast(sizeof(struct Params))); @@ -92,18 +98,14 @@ bool E131Params::Load() { ReadConfigFile configfile(E131Params::staticCallbackFunction, this); if (configfile.Read(E131ParamsConst::FILE_NAME)) { - if (m_pE131ParamsStore != nullptr) { - m_pE131ParamsStore->Update(&m_Params); - } + E131ParamsStore::Update(&m_Params); } else #endif - if (m_pE131ParamsStore != nullptr) { - m_pE131ParamsStore->Copy(&m_Params); - } else { - DEBUG_EXIT - return false; - } + E131ParamsStore::Copy(&m_Params); +#ifndef NDEBUG + Dump(); +#endif DEBUG_EXIT return true; } @@ -120,9 +122,11 @@ void E131Params::Load(const char* pBuffer, uint32_t nLength) { config.Read(pBuffer, nLength); - assert(m_pE131ParamsStore != nullptr); - m_pE131ParamsStore->Update(&m_Params); + E131ParamsStore::Update(&m_Params); +#ifndef NDEBUG + Dump(); +#endif DEBUG_EXIT } @@ -247,21 +251,13 @@ void E131Params::callbackFunction(const char *pLine) { } } -void E131Params::staticCallbackFunction(void *p, const char *s) { - assert(p != nullptr); - assert(s != nullptr); - - (static_cast(p))->callbackFunction(s); -} - void E131Params::Builder(const struct Params *pParams, char *pBuffer, uint32_t nLength, uint32_t& nSize) { DEBUG_ENTRY if (pParams != nullptr) { memcpy(&m_Params, pParams, sizeof(struct Params)); } else { - assert(m_pE131ParamsStore != nullptr); - m_pE131ParamsStore->Copy(&m_Params); + E131ParamsStore::Copy(&m_Params); } PropertiesBuilder builder(E131ParamsConst::FILE_NAME, pBuffer, nLength); @@ -310,14 +306,14 @@ void E131Params::Builder(const struct Params *pParams, char *pBuffer, uint32_t n DEBUG_EXIT } -void E131Params::Set(uint32_t nPortIndexOffset) { +void E131Params::Set() { DEBUG_ENTRY - if (nPortIndexOffset <= e131bridge::MAX_PORTS) { - s_nPortsMax = std::min(e131params::MAX_PORTS, e131bridge::MAX_PORTS - nPortIndexOffset); + if (e131bridge::configstore::DMXPORT_OFFSET <= e131bridge::MAX_PORTS) { + s_nPortsMax = std::min(e131params::MAX_PORTS, e131bridge::MAX_PORTS - e131bridge::configstore::DMXPORT_OFFSET); } - DEBUG_PRINTF("e131bridge::MAX_PORTS=%u, nPortIndexOffset=%u, s_nPortsMax=%u", e131bridge::MAX_PORTS, nPortIndexOffset, s_nPortsMax); + DEBUG_PRINTF("e131bridge::MAX_PORTS=%u, e131bridge::configstore::DMXPORT_OFFSET=%u, s_nPortsMax=%u", e131bridge::MAX_PORTS, e131bridge::configstore::DMXPORT_OFFSET, s_nPortsMax); if (m_Params.nSetList == 0) { return; @@ -327,7 +323,7 @@ void E131Params::Set(uint32_t nPortIndexOffset) { assert(p != nullptr); for (uint32_t nPortIndex = 0; nPortIndex < s_nPortsMax; nPortIndex++) { - const auto nOffset = nPortIndex + nPortIndexOffset; + const auto nOffset = nPortIndex + e131bridge::configstore::DMXPORT_OFFSET; if (nOffset >= e131bridge::MAX_PORTS) { DEBUG_EXIT @@ -353,3 +349,48 @@ void E131Params::Set(uint32_t nPortIndexOffset) { p->SetDisableMergeTimeout(true); } } + +void E131Params::staticCallbackFunction(void *p, const char *s) { + assert(p != nullptr); + assert(s != nullptr); + + (static_cast(p))->callbackFunction(s); +} + +void E131Params::Dump() { + printf("%s::%s \'%s\':\n", __FILE__, __FUNCTION__, E131ParamsConst::FILE_NAME); + + if (isMaskSet(e131params::Mask::FAILSAFE)) { + printf(" %s=%d [%s]\n", LightSetParamsConst::FAILSAFE, m_Params.nFailSafe, lightset::get_failsafe(static_cast(m_Params.nFailSafe))); + } + + for (uint32_t i = 0; i < e131params::MAX_PORTS; i++) { + if (isMaskSet(e131params::Mask::UNIVERSE_A << i)) { + printf(" %s=%d\n", LightSetParamsConst::UNIVERSE_PORT[i], m_Params.nUniverse[i]); + } + } + + for (uint32_t i = 0; i < e131params::MAX_PORTS; i++) { + printf(" %s=%s\n", LightSetParamsConst::MERGE_MODE_PORT[i], lightset::get_merge_mode(mergemode_get(i))); + } + + for (uint32_t i = 0; i < e131params::MAX_PORTS; i++) { + const auto portDir = static_cast(e131params::portdir_shif_right(m_Params.nDirection, i)); + printf(" %s=%d [%s]\n", LightSetParamsConst::DIRECTION[i], e131params::portdir_shif_right(m_Params.nDirection, i), lightset::get_direction(portDir)); + } + + for (uint32_t i = 0; i < e131params::MAX_PORTS; i++) { + if (isMaskSet(e131params::Mask::PRIORITY_A << i)) { + printf(" %s=%d\n", E131ParamsConst::PRIORITY[i], m_Params.nPriority[i]); + } + } + + for (uint32_t i = 0; i < e131params::MAX_PORTS; i++) { + const auto nOutputStyle = static_cast(isOutputStyleSet(1U << i)); + printf(" %s=%u [%s]\n", LightSetParamsConst::OUTPUT_STYLE[i], static_cast(nOutputStyle), lightset::get_output_style(static_cast(nOutputStyle))); + } + + if (isMaskSet(e131params::Mask::DISABLE_MERGE_TIMEOUT)) { + printf(" %s=1 [Yes]\n", LightSetParamsConst::DISABLE_MERGE_TIMEOUT); + } +} diff --git a/lib-e131/src/node/e131paramsconst.cpp b/lib-e131/src/node/e131paramsconst.cpp index 6654a31f..3b6cd51c 100644 --- a/lib-e131/src/node/e131paramsconst.cpp +++ b/lib-e131/src/node/e131paramsconst.cpp @@ -2,7 +2,7 @@ * @file e131paramsconst.cpp * */ -/* Copyright (C) 2019-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-e131/src/node/e131paramsdump.cpp b/lib-e131/src/node/e131paramsdump.cpp deleted file mode 100644 index 7486385c..00000000 --- a/lib-e131/src/node/e131paramsdump.cpp +++ /dev/null @@ -1,78 +0,0 @@ -/** - * @file e131paramsdump.cpp - * - */ -/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#if !defined(__clang__) // Needed for compiling on MacOS -# pragma GCC push_options -# pragma GCC optimize ("Os") -#endif - -#include -#include - -#include "e131params.h" -#include "e131paramsconst.h" - -#include "lightset.h" -#include "lightsetparamsconst.h" - -void E131Params::Dump() { -#ifndef NDEBUG - printf("%s::%s \'%s\':\n", __FILE__, __FUNCTION__, E131ParamsConst::FILE_NAME); - - if (isMaskSet(e131params::Mask::FAILSAFE)) { - printf(" %s=%d [%s]\n", LightSetParamsConst::FAILSAFE, m_Params.nFailSafe, lightset::get_failsafe(static_cast(m_Params.nFailSafe))); - } - - for (uint32_t i = 0; i < e131params::MAX_PORTS; i++) { - if (isMaskSet(e131params::Mask::UNIVERSE_A << i)) { - printf(" %s=%d\n", LightSetParamsConst::UNIVERSE_PORT[i], m_Params.nUniverse[i]); - } - } - - for (uint32_t i = 0; i < e131params::MAX_PORTS; i++) { - printf(" %s=%s\n", LightSetParamsConst::MERGE_MODE_PORT[i], lightset::get_merge_mode(mergemode_get(i))); - } - - for (uint32_t i = 0; i < e131params::MAX_PORTS; i++) { - const auto portDir = static_cast(e131params::portdir_shif_right(m_Params.nDirection, i)); - printf(" %s=%d [%s]\n", LightSetParamsConst::DIRECTION[i], e131params::portdir_shif_right(m_Params.nDirection, i), lightset::get_direction(portDir)); - } - - for (uint32_t i = 0; i < e131params::MAX_PORTS; i++) { - if (isMaskSet(e131params::Mask::PRIORITY_A << i)) { - printf(" %s=%d\n", E131ParamsConst::PRIORITY[i], m_Params.nPriority[i]); - } - } - - for (uint32_t i = 0; i < e131params::MAX_PORTS; i++) { - const auto nOutputStyle = static_cast(isOutputStyleSet(1U << i)); - printf(" %s=%u [%s]\n", LightSetParamsConst::OUTPUT_STYLE[i], nOutputStyle, lightset::get_output_style(static_cast(nOutputStyle))); - } - - if (isMaskSet(e131params::Mask::DISABLE_MERGE_TIMEOUT)) { - printf(" %s=1 [Yes]\n", LightSetParamsConst::DISABLE_MERGE_TIMEOUT); - } -#endif -} diff --git a/lib-flash/.cproject b/lib-flash/.cproject index deefab79..f3bf1ec5 100755 --- a/lib-flash/.cproject +++ b/lib-flash/.cproject @@ -31,12 +31,10 @@ - diff --git a/lib-flash/include/spi/spi_flash.h b/lib-flash/include/spi/spi_flash.h index 50df49c1..729a61f6 100644 --- a/lib-flash/include/spi/spi_flash.h +++ b/lib-flash/include/spi/spi_flash.h @@ -2,7 +2,7 @@ * @file spi_flash.h * */ -/* Copyright (C) 2018-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-flash/src/spi/gd32/spi_flash.cpp b/lib-flash/src/spi/gd32/spi_flash.cpp index 7b2597ea..a719e284 100644 --- a/lib-flash/src/spi/gd32/spi_flash.cpp +++ b/lib-flash/src/spi/gd32/spi_flash.cpp @@ -2,7 +2,7 @@ * @file spi_flash.cpp * */ -/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,6 +28,7 @@ #include "./../../spi/spi_flash_internal.h" #include "gd32_spi.h" +#include "gd32_gpio.h" #include "gd32.h" #include "debug.h" @@ -41,6 +42,16 @@ int spi_init() { gpio_fsel(SPI_FLASH_CS_GPIOx, SPI_FLASH_CS_GPIO_PINx, GPIO_FSEL_OUTPUT); gpio_bit_set(SPI_FLASH_CS_GPIOx, SPI_FLASH_CS_GPIO_PINx); +#if defined (SPI_FLASH_WP_GPIO_PINx) + gpio_fsel(SPI_GPIOx, SPI_FLASH_WP_GPIO_PINx, GPIO_FSEL_OUTPUT); + gpio_bit_set(SPI_GPIOx, SPI_FLASH_WP_GPIO_PINx); +#endif + +#if defined (SPI_FLASH_HOLD_GPIO_PINx) + gpio_fsel(SPI_GPIOx, SPI_FLASH_HOLD_GPIO_PINx, GPIO_FSEL_OUTPUT); + gpio_bit_set(SPI_GPIOx, SPI_FLASH_HOLD_GPIO_PINx); +#endif + return 0; } diff --git a/lib-flash/src/spi/get_timer.cpp b/lib-flash/src/spi/get_timer.cpp index 91bc169e..3edf77d5 100644 --- a/lib-flash/src/spi/get_timer.cpp +++ b/lib-flash/src/spi/get_timer.cpp @@ -2,7 +2,7 @@ * @file get_timer.cpp * */ -/* Copyright (C) 2018-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-flash/src/spi/gigadevice.cpp b/lib-flash/src/spi/gigadevice.cpp old mode 100644 new mode 100755 index d32ec219..9c72f30a --- a/lib-flash/src/spi/gigadevice.cpp +++ b/lib-flash/src/spi/gigadevice.cpp @@ -12,7 +12,7 @@ /* * Original code : https://github.com/martinezjavier/u-boot/blob/master/drivers/mtd/spi/gigadevice.c */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -50,6 +50,11 @@ static constexpr struct gigadevice_spi_flash_params gigadevice_spi_flash_table[] 64, "GD25LQ", }, + { + 0x4015, + 8, + "GD25Q40", + }, { 0x4017, 128, @@ -68,10 +73,11 @@ int spi_flash_probe_gigadevice(struct spi_flash *flash, uint8_t *idcode) { } if (i == ARRAY_SIZE(gigadevice_spi_flash_table)) { - DEBUG_PRINTF("SF: Unsupported Gigadevice ID %02x%02x", idcode[1], idcode[2]); + DEBUG_PRINTF("SF: Unsupported GigaDevice ID %02x%02x", idcode[1], idcode[2]); return -1; } + flash->name = params->name; flash->page_size = 256; flash->sector_size = flash->page_size * 16; flash->size = flash->sector_size * 16 * params->nr_blocks; diff --git a/lib-flash/src/spi/macronix.cpp b/lib-flash/src/spi/macronix.cpp index 3a2ceb2b..ebff01c6 100644 --- a/lib-flash/src/spi/macronix.cpp +++ b/lib-flash/src/spi/macronix.cpp @@ -19,7 +19,7 @@ /* * Original code : https://github.com/martinezjavier/u-boot/blob/master/drivers/mtd/spi/macronix.c */ -/* Copyright (C) 2018-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-flash/src/spi/spi_flash.cpp b/lib-flash/src/spi/spi_flash.cpp index bcb15794..ab0e11c2 100644 --- a/lib-flash/src/spi/spi_flash.cpp +++ b/lib-flash/src/spi/spi_flash.cpp @@ -5,7 +5,7 @@ /* * Original code : https://github.com/martinezjavier/u-boot/blob/master/drivers/mtd/spi/spi_flash.c */ -/* Copyright (C) 2018-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,6 +33,7 @@ #include #include #include +#include #include "spi/spi_flash.h" @@ -90,6 +91,14 @@ static const struct { }; #define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) +static uint32_t get_timer(uint32_t base) { + if (0 == base) { + return static_cast(time(nullptr)); + } + + return static_cast(time(nullptr)) - base; +} + uint32_t spi_flash_get_size() { return s_flash.size; } @@ -356,7 +365,7 @@ int spi_flash_cmd_write_status(uint8_t sr) { return 0; } -int spi_flash_probe(__attribute__((unused)) unsigned int cs, __attribute__((unused)) unsigned int max_hz, __attribute__((unused)) unsigned int spi_mode) { +int spi_flash_probe([[maybe_unused]] unsigned int cs, [[maybe_unused]] unsigned int max_hz, [[maybe_unused]] unsigned int spi_mode) { int shift; unsigned i; uint8_t idcode[IDCODE_LEN] = {0, }; diff --git a/lib-flash/src/spi/spi_flash_internal.h b/lib-flash/src/spi/spi_flash_internal.h index 6b6af846..019fff1a 100644 --- a/lib-flash/src/spi/spi_flash_internal.h +++ b/lib-flash/src/spi/spi_flash_internal.h @@ -2,7 +2,7 @@ * @file spi_internal.h * */ -/* Copyright (C) 2019-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@g32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -74,18 +74,16 @@ struct spi_flash { #define SPI_XFER_SPEED_HZ 6000000 ///< 6MHz -extern uint32_t get_timer(uint32_t base); //TODO Remove - extern int spi_init(); extern int spi_xfer(uint32_t bitlen, const uint8_t *dout, uint8_t *din, uint32_t flags); -#define CONFIG_SPI_FLASH_MACRONIX -int spi_flash_probe_macronix(struct spi_flash *flash, uint8_t *idcode); +//#define CONFIG_SPI_FLASH_MACRONIX +//int spi_flash_probe_macronix(struct spi_flash *flash, uint8_t *idcode); #define CONFIG_SPI_FLASH_WINBOND extern int spi_flash_probe_winbond(struct spi_flash *spi, uint8_t *idcode); -#define CONFIG_SPI_FLASH_GIGADEVICE -extern int spi_flash_probe_gigadevice(struct spi_flash *spi, uint8_t *idcode); +//#define CONFIG_SPI_FLASH_GIGADEVICE +//extern int spi_flash_probe_gigadevice(struct spi_flash *spi, uint8_t *idcode); #endif /* SPI_FLASH_INTERNAL_H_ */ diff --git a/lib-flash/src/spi/winbond.cpp b/lib-flash/src/spi/winbond.cpp index 249308d4..e821a3c1 100644 --- a/lib-flash/src/spi/winbond.cpp +++ b/lib-flash/src/spi/winbond.cpp @@ -10,7 +10,7 @@ /* * Original code : https://github.com/martinezjavier/u-boot/blob/master/drivers/mtd/spi/winbond.c */ -/* Copyright (C) 2018-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-flashcode/.cproject b/lib-flashcode/.cproject index 4bcd643d..fdc205e6 100755 --- a/lib-flashcode/.cproject +++ b/lib-flashcode/.cproject @@ -31,11 +31,9 @@ - @@ -95,7 +90,6 @@ - diff --git a/lib-flashcode/Makefile.GD32 b/lib-flashcode/Makefile.GD32 index e0ac7451..3808855c 100755 --- a/lib-flashcode/Makefile.GD32 +++ b/lib-flashcode/Makefile.GD32 @@ -4,7 +4,11 @@ ifneq ($(MAKE_FLAGS),) ifeq ($(findstring gd32f4xx,$(FAMILY)), gd32f4xx) EXTRA_SRCDIR=src/gd32/f4xx else - EXTRA_SRCDIR=src/gd32/fmc + ifeq ($(findstring gd32h7xx,$(FAMILY)), gd32h7xx) + EXTRA_SRCDIR=src/gd32/h7xx + else + EXTRA_SRCDIR=src/gd32/fmc + endif endif else EXTRA_SRCDIR=src/gd32/fmc diff --git a/lib-flashcode/include/flashcode.h b/lib-flashcode/include/flashcode.h index 95eacb77..de55e14e 100644 --- a/lib-flashcode/include/flashcode.h +++ b/lib-flashcode/include/flashcode.h @@ -2,7 +2,7 @@ * @file flashcode.h * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-flashcode/src/gd32/f4xx/flashcode.cpp b/lib-flashcode/src/gd32/f4xx/flashcode.cpp deleted file mode 100644 index 3a133f69..00000000 --- a/lib-flashcode/src/gd32/f4xx/flashcode.cpp +++ /dev/null @@ -1,154 +0,0 @@ -/** - * @file flashcode.cpp - * - */ -/* Copyright (C) 2022 by Arjan van Vught mailto:info@gd32-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#include - -#include "flashcode.h" - -#include "gd32.h" -#include "fmc_operation.h" - -#include "debug.h" - -uint32_t FlashCode::GetSize() const { - return FMC_SIZE * 1024U; -} - -uint32_t FlashCode::GetSectorSize() const { - return SIZE_16KB; -} - -bool FlashCode::Read(uint32_t nOffset, uint32_t nLength, uint8_t *pBuffer, flashcode::result& nResult) { - DEBUG_ENTRY - DEBUG_PRINTF("nOffset=%p[%d], nLength=%u[%d], data=%p[%d]", nOffset, (((uint32_t)(nOffset) & 0x3) == 0), nLength, (((uint32_t)(nLength) & 0x3) == 0), data, (((uint32_t)(data) & 0x3) == 0)); - - const uint32_t *src = (uint32_t *)(nOffset + FLASH_BASE); - uint32_t *dst = (uint32_t *)pBuffer; - - while (nLength > 0) { - *dst++ = *src++; - nLength -= 4; - } - - debug_dump((uint8_t *)(nOffset + FLASH_BASE), 64); - debug_dump(pBuffer, 64); - - nResult = flashcode::result::OK; - - DEBUG_EXIT - return 0; -} - -bool FlashCode::Write(uint32_t nOffset, uint32_t nLength, const uint8_t *pBuffer, flashcode::result& nResult) { - DEBUG_ENTRY - DEBUG_PRINTF("nOffset=%p[%d], nLength=%u[%d], data=%p[%d]", nOffset, (((uint32_t)(nOffset) & 0x3) == 0), nLength, (((uint32_t)(nLength) & 0x3) == 0), pBuffer, (((uint32_t)(pBuffer) & 0x3) == 0)); - - nResult = flashcode::result::ERROR; - - fmc_unlock(); - fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_OPERR | FMC_FLAG_WPERR | FMC_FLAG_PGMERR | FMC_FLAG_PGSERR); - - uint32_t address = nOffset + FLASH_BASE; - const uint32_t *data = (uint32_t *)pBuffer; - - while (nLength >= 4) { - - fmc_state_enum state = fmc_word_program(address, *data); - - if (FMC_READY != state) { - DEBUG_PRINTF("state=%d [%p]", state, address); - DEBUG_EXIT - return true; - } - - data++; - address += 4; - nLength -= 4; - } - - if (nLength > 0) { - fmc_state_enum state = fmc_word_program(address, *data); - - if (FMC_READY != state) { - DEBUG_PRINTF("state=%d [%p]", state, address); - DEBUG_EXIT - return true; - } - } - - fmc_lock(); - - debug_dump(pBuffer, 64); - debug_dump((uint8_t *)(nOffset + FLASH_BASE), 64); - - nResult = flashcode::result::OK; - - DEBUG_EXIT - return true; -} - -bool FlashCode::Erase(uint32_t nOffset, uint32_t nLength, flashcode::result& nResult) { - DEBUG_ENTRY - DEBUG_PRINTF("nOffset=%p[%d], nLength=%x[%d]", nOffset, (((uint32_t)(nOffset) & 0x3) == 0), nLength, (((uint32_t)(nLength) & 0x3) == 0)); - - nResult = flashcode::result::ERROR; - - fmc_sector_info_struct sector_info; - uint32_t address = nOffset + FLASH_BASE; - - int size = (int) nLength; - - while (size > 0) { - sector_info = fmc_sector_info_get(address); - - if (FMC_WRONG_SECTOR_NAME == sector_info.sector_name) { - return true; - } - - DEBUG_PRINTF("Address 0x%08X is located in the : SECTOR_NUMBER_%d", address, sector_info.sector_name); - DEBUG_PRINTF("Sector range: 0x%08X to 0x%08X", sector_info.sector_start_addr, sector_info.sector_end_addr); - DEBUG_PRINTF("nSector size: %d KB\n", (sector_info.sector_size/1024)); - - fmc_unlock(); - fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_OPERR | FMC_FLAG_WPERR | FMC_FLAG_PGMERR | FMC_FLAG_PGSERR); - - if (FMC_READY != fmc_sector_erase(sector_info.sector_num)) { - return true; - } - - fmc_lock(); - - size -= sector_info.sector_size; - address += sector_info.sector_size; - } - - - nResult = flashcode::result::OK; - - DEBUG_EXIT - return true; -} diff --git a/lib-flashcode/src/gd32/f4xx/fmc_operation.cpp b/lib-flashcode/src/gd32/f4xx/fmc_operation.cpp deleted file mode 100644 index 32470238..00000000 --- a/lib-flashcode/src/gd32/f4xx/fmc_operation.cpp +++ /dev/null @@ -1,367 +0,0 @@ -/*! - \file fmc_operation.c - \brief flash program, erase - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32.h" -#include "fmc_operation.h" - -/*! - \brief get the sector number, size and range of the given address - \param[in] address: The flash address - \param[out] none - \retval fmc_sector_info_struct: The information of a sector -*/ -fmc_sector_info_struct fmc_sector_info_get(uint32_t addr) -{ - fmc_sector_info_struct sector_info; - uint32_t temp = 0x00000000U; - if((FMC_START_ADDRESS <= addr)&&(FMC_END_ADDRESS >= addr)) { - if ((FMC_BANK1_START_ADDRESS > addr)) { - /* bank0 area */ - temp = (addr - FMC_BANK0_START_ADDRESS) / SIZE_16KB; - if (4U > temp) { - sector_info.sector_name = (uint32_t)temp; - sector_info.sector_num = CTL_SN(temp); - sector_info.sector_size = SIZE_16KB; - sector_info.sector_start_addr = FMC_BANK0_START_ADDRESS + (SIZE_16KB * temp); - sector_info.sector_end_addr = sector_info.sector_start_addr + SIZE_16KB - 1; - } else if (8U > temp) { - sector_info.sector_name = 0x00000004U; - sector_info.sector_num = CTL_SN(4); - sector_info.sector_size = SIZE_64KB; - sector_info.sector_start_addr = 0x08010000U; - sector_info.sector_end_addr = 0x0801FFFFU; - } else { - temp = (addr - FMC_BANK0_START_ADDRESS) / SIZE_128KB; - sector_info.sector_name = (uint32_t)(temp + 4); - sector_info.sector_num = CTL_SN(temp + 4); - sector_info.sector_size = SIZE_128KB; - sector_info.sector_start_addr = FMC_BANK0_START_ADDRESS + (SIZE_128KB * temp); - sector_info.sector_end_addr = sector_info.sector_start_addr + SIZE_128KB - 1; - } - } else { - /* bank1 area */ - temp = (addr - FMC_BANK1_START_ADDRESS) / SIZE_16KB; - if (4U > temp) { - sector_info.sector_name = (uint32_t)(temp + 12); - sector_info.sector_num = CTL_SN(temp + 16); - sector_info.sector_size = SIZE_16KB; - sector_info.sector_start_addr = FMC_BANK0_START_ADDRESS + (SIZE_16KB * temp); - sector_info.sector_end_addr = sector_info.sector_start_addr + SIZE_16KB - 1; - } else if (8U > temp) { - sector_info.sector_name = 0x00000010; - sector_info.sector_num = CTL_SN(20); - sector_info.sector_size = SIZE_64KB; - sector_info.sector_start_addr = 0x08110000U; - sector_info.sector_end_addr = 0x0811FFFFU; - } else if (64U > temp){ - temp = (addr - FMC_BANK1_START_ADDRESS) / SIZE_128KB; - sector_info.sector_name = (uint32_t)(temp + 16); - sector_info.sector_num = CTL_SN(temp + 20); - sector_info.sector_size = SIZE_128KB; - sector_info.sector_start_addr = FMC_BANK1_START_ADDRESS + (SIZE_128KB * temp); - sector_info.sector_end_addr = sector_info.sector_start_addr + SIZE_128KB - 1; - } else { - temp = (addr - FMC_BANK1_START_ADDRESS) / SIZE_256KB; - sector_info.sector_name = (uint32_t)(temp + 20); - sector_info.sector_num = CTL_SN(temp + 8); - sector_info.sector_size = SIZE_256KB; - sector_info.sector_start_addr = FMC_BANK1_START_ADDRESS + (SIZE_256KB * temp); - sector_info.sector_end_addr = sector_info.sector_start_addr + SIZE_256KB - 1; - } - } - } else { - /* invalid address */ - sector_info.sector_name = FMC_WRONG_SECTOR_NAME; - sector_info.sector_num = FMC_WRONG_SECTOR_NUM; - sector_info.sector_size = FMC_INVALID_SIZE; - sector_info.sector_start_addr = FMC_INVALID_ADDR; - sector_info.sector_end_addr = FMC_INVALID_ADDR; - } - return sector_info; -} - -/*! - \brief get the sector number by a given sector name - \param[in] address: a given sector name - \param[out] none - \retval uint32_t: sector number -*/ -uint32_t sector_name_to_number(uint32_t sector_name) -{ - if(11 >= sector_name){ - return CTL_SN(sector_name); - }else if(23 >= sector_name){ - return CTL_SN(sector_name + 4); - }else if(27 >= sector_name){ - return CTL_SN(sector_name - 12); - }else{ - while(1); - } -} - -/*! - \brief erases the sector of a given address - \param[in] address: a given address - \param[out] none - \retval none -*/ -void fmc_erase_sector_by_address(uint32_t address) -{ - fmc_sector_info_struct sector_info; - printf("\r\nFMC erase operation:\n"); - /* get information about the sector in which the specified address is located */ - sector_info = fmc_sector_info_get(address); - if(FMC_WRONG_SECTOR_NAME == sector_info.sector_name){ - printf("\r\nWrong address!\n"); - while(1); - }else{ - printf("\r\nErase start ......\n"); - /* unlock the flash program erase controller */ - fmc_unlock(); - /* clear pending flags */ - fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_OPERR | FMC_FLAG_WPERR | FMC_FLAG_PGMERR | FMC_FLAG_PGSERR); - /* wait the erase operation complete*/ - if(FMC_READY != fmc_sector_erase(sector_info.sector_num)){ - while(1); - } - /* lock the flash program erase controller */ - fmc_lock(); - printf("\r\nAddress 0x%08X is located in the : SECTOR_NUMBER_%d !\n", address, sector_info.sector_name); - printf("\r\nSector range: 0x%08X to 0x%08X\n", sector_info.sector_start_addr, sector_info.sector_end_addr); - printf("\r\nSector size: %d KB\n", (sector_info.sector_size/1024)); - printf("\r\nErase success!\n"); - printf("\r\n"); - } -} - -/*! - \brief write 32 bit length data to a given address - \param[in] address: a given address(0x08000000~0x082FFFFF) - \param[in] length: data length - \param[in] data_32: data pointer - \param[out] none - \retval none -*/ -void fmc_write_32bit_data(uint32_t address, uint16_t length, int32_t* data_32) -{ - fmc_sector_info_struct start_sector_info; - fmc_sector_info_struct end_sector_info; - uint32_t sector_num,i; - - printf("\r\nFMC word programe operation:\n"); - /* unlock the flash program erase controller */ - fmc_unlock(); - /* clear pending flags */ - fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_OPERR | FMC_FLAG_WPERR | FMC_FLAG_PGMERR | FMC_FLAG_PGSERR); - /* get the information of the start and end sectors */ - start_sector_info = fmc_sector_info_get(address); - end_sector_info = fmc_sector_info_get(address + 4*length); - /* erase sector */ - for(i = start_sector_info.sector_name; i <= end_sector_info.sector_name; i++){ - sector_num = sector_name_to_number(i); - if(FMC_READY != fmc_sector_erase(sector_num)){ - while(1); - } - } - - /* write data_32 to the corresponding address */ - for(i=0; i -#include "gd32f4xx.h" - -/* FMC sector information */ -typedef struct -{ - uint32_t sector_name; /*!< the name of the sector */ - uint32_t sector_num; /*!< the number of the sector */ - uint32_t sector_size; /*!< the size of the sector */ - uint32_t sector_start_addr; /*!< the start address of the sector */ - uint32_t sector_end_addr; /*!< the end address of the sector */ -} fmc_sector_info_struct; - -/* sector size */ -#define SIZE_16KB ((uint32_t)0x00004000U) /*!< size of 16KB*/ -#define SIZE_64KB ((uint32_t)0x00010000U) /*!< size of 64KB*/ -#define SIZE_128KB ((uint32_t)0x00020000U) /*!< size of 128KB*/ -#define SIZE_256KB ((uint32_t)0x00040000U) /*!< size of 256KB*/ - -/* FMC BANK address */ -#define FMC_START_ADDRESS FLASH_BASE /*!< FMC start address */ -#define FMC_BANK0_START_ADDRESS FMC_START_ADDRESS /*!< FMC BANK0 start address */ -#define FMC_BANK1_START_ADDRESS ((uint32_t)0x08100000U) /*!< FMC BANK1 start address */ -#define FMC_SIZE (*(uint16_t *)0x1FFF7A22U) /*!< FMC SIZE */ -#define FMC_END_ADDRESS (FLASH_BASE + (FMC_SIZE * 1024) - 1) /*!< FMC end address */ -#define FMC_MAX_END_ADDRESS ((uint32_t)0x08300000U) /*!< FMC maximum end address */ - -/* FMC error message */ -#define FMC_WRONG_SECTOR_NAME ((uint32_t)0xFFFFFFFFU) /*!< wrong sector name*/ -#define FMC_WRONG_SECTOR_NUM ((uint32_t)0xFFFFFFFFU) /*!< wrong sector number*/ -#define FMC_INVALID_SIZE ((uint32_t)0xFFFFFFFFU) /*!< invalid sector size*/ -#define FMC_INVALID_ADDR ((uint32_t)0xFFFFFFFFU) /*!< invalid sector address*/ - -/* get the sector number, size and range of the given address */ -fmc_sector_info_struct fmc_sector_info_get(uint32_t addr); -/* get the sector number by sector name */ -uint32_t sector_name_to_number(uint32_t sector_name); -/* erases the sector of a given sector number */ -void fmc_erase_sector_by_address(uint32_t address); -/* write 32 bit length data to a given address */ -void fmc_write_32bit_data(uint32_t address, uint16_t length, int32_t* data_32); -/* read 32 bit length data from a given address */ -void fmc_read_32bit_data(uint32_t address, uint16_t length, int32_t* data_32); -/* write 16 bit length data to a given address */ -void fmc_write_16bit_data(uint32_t address, uint16_t length, int16_t* data_16); -/* read 16 bit length data from a given address */ -void fmc_read_16bit_data(uint32_t address, uint16_t length, int16_t* data_16); -/* write 8 bit length data to a given address */ -void fmc_write_8bit_data(uint32_t address, uint16_t length, int8_t* data_8); -/* read 8 bit length data from a given address */ -void fmc_read_8bit_data(uint32_t address, uint16_t length, int8_t* data_8); - -#endif/* __FMC_OPERATION_H */ diff --git a/lib-flashcode/src/gd32/flashcode.cpp b/lib-flashcode/src/gd32/flashcode.cpp index 449e416f..f423d045 100644 --- a/lib-flashcode/src/gd32/flashcode.cpp +++ b/lib-flashcode/src/gd32/flashcode.cpp @@ -2,7 +2,7 @@ * @file flashcode.cpp * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -41,7 +41,7 @@ FlashCode::FlashCode() { m_IsDetected = true; - printf("FMC: Detected %s with total %d bytes [%d kB]\n", GetName(), GetSize(), GetSize() / 1024U); + printf("FMC: %s %u [%u]\n", GetName(), static_cast(GetSize()), static_cast(GetSize() / 1024U)); DEBUG_EXIT } diff --git a/lib-flashcode/src/gd32/fmc/flashcode.cpp b/lib-flashcode/src/gd32/fmc/flashcode.cpp index 9338ba59..46c8e3a9 100644 --- a/lib-flashcode/src/gd32/fmc/flashcode.cpp +++ b/lib-flashcode/src/gd32/fmc/flashcode.cpp @@ -2,7 +2,7 @@ * @file flashcode.cpp * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -31,6 +31,16 @@ #include "gd32.h" +/** + * With the latest GD32F firmware, this function is declared as static. + */ +#if defined (GD32F20X) +extern "C" { +fmc_state_enum fmc_bank0_state_get(void); +fmc_state_enum fmc_bank1_state_get(void); +} +#endif + #include "debug.h" namespace flashcode { diff --git a/lib-flashcode/src/gd32/h7xx/flashcode.cpp b/lib-flashcode/src/gd32/h7xx/flashcode.cpp new file mode 100644 index 00000000..47cc26a5 --- /dev/null +++ b/lib-flashcode/src/gd32/h7xx/flashcode.cpp @@ -0,0 +1,217 @@ +/** + * @file flashcode.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include +#include + +#include "flashcode.h" + +#include "gd32.h" + +#include "debug.h" + +namespace flashcode { +/* Backwards compatibility with SPI FLASH */ +static constexpr auto FLASH_SECTOR_SIZE = 4096U; +/* The flash page size is 4KB for bank1 */ +static constexpr auto BANK1_FLASH_PAGE = (4U * 1024U); + +enum class State { + IDLE, + ERASE_BUSY, + ERASE_PROGAM, + WRITE_BUSY, + WRITE_PROGRAM, + ERROR +}; + +static State s_State = State::IDLE; +static uint32_t s_nPage; +static uint32_t s_nLength; +static uint32_t s_nAddress; +static uint32_t *s_pData; +} // namespace flashcode + +using namespace flashcode; + +uint32_t FlashCode::GetSize() const { + const auto FLASH_DENSITY = ((REG32(0x1FF0F7E0) >> 16) & 0xFFFF) * 1024U; + return FLASH_DENSITY; +} + +uint32_t FlashCode::GetSectorSize() const { + return flashcode::FLASH_SECTOR_SIZE; +} + +bool FlashCode::Read(uint32_t nOffset, uint32_t nLength, uint8_t *pBuffer, flashcode::result& nResult) { + DEBUG_ENTRY + DEBUG_PRINTF("offset=%p[%d], len=%u[%d], data=%p[%d]", nOffset, (((uint32_t)(nOffset) & 0x3) == 0), nLength, (((uint32_t)(nLength) & 0x3) == 0), pBuffer, (((uint32_t)(pBuffer) & 0x3) == 0)); + + const auto *pSrc = reinterpret_cast(nOffset + FLASH_BASE); + auto *pDst = reinterpret_cast(pBuffer); + + while (nLength > 0) { + *pDst++ = *pSrc++; + nLength -= 4; + } + + nResult = flashcode::result::OK; + + DEBUG_EXIT + return true; +} + +bool FlashCode::Erase(uint32_t nOffset, uint32_t nLength, flashcode::result& nResult) { + DEBUG_ENTRY + DEBUG_PRINTF("State=%d", static_cast(s_State)); + + nResult = result::OK; + + switch (s_State) { + case State::IDLE: + s_nPage = nOffset + FLASH_BASE; + s_nLength = nLength; + fmc_unlock(); + s_State = State::ERASE_BUSY; + DEBUG_EXIT + return false; + break; + case State::ERASE_BUSY: + if (SET == fmc_flag_get(FMC_FLAG_BUSY)) { + DEBUG_EXIT + return false; + } + + if (s_nLength == 0) { + s_State = State::IDLE; + fmc_lock(); + DEBUG_EXIT + return true; + } + + s_State = State::ERASE_PROGAM; + DEBUG_EXIT + return false; + break; + case State::ERASE_PROGAM: + if (s_nLength > 0) { + DEBUG_PRINTF("s_nPage=%p", s_nPage); + + fmc_sector_erase(s_nPage); + + s_nLength -= BANK1_FLASH_PAGE; + s_nPage += BANK1_FLASH_PAGE; + } + + s_State = State::ERASE_BUSY; + DEBUG_EXIT + return false; + break; + default: + assert(0); + __builtin_unreachable(); + break; + } + + assert(0); + __builtin_unreachable(); + return true; +} + +bool FlashCode::Write(uint32_t nOffset, uint32_t nLength, const uint8_t *pBuffer, flashcode::result& nResult) { + if ((s_State == flashcode::State::WRITE_PROGRAM) || (s_State == flashcode::State::WRITE_BUSY)) { + } else { + DEBUG_ENTRY + } + nResult = result::OK; + + switch (s_State) { + case flashcode::State::IDLE: + DEBUG_PUTS("State::IDLE"); + flashcode::s_nAddress = nOffset + FLASH_BASE; + s_pData = const_cast(reinterpret_cast(pBuffer)); + s_nLength = nLength; + fmc_unlock(); + s_State = State::WRITE_BUSY; + DEBUG_EXIT + return false; + break; + case flashcode::State::WRITE_BUSY: + if (SET == fmc_flag_get(FMC_FLAG_BUSY)) { + DEBUG_EXIT + return false; + } + + if (s_nLength == 0) { + fmc_lock(); + s_State = State::IDLE; + + if( memcmp(reinterpret_cast(nOffset + FLASH_BASE), pBuffer, nLength) == 0) { + DEBUG_PUTS("memcmp OK"); + } else { + DEBUG_PUTS("memcmp failed"); + } + + DEBUG_EXIT + return true; + } + + s_State = flashcode::State::WRITE_PROGRAM; + return false; + break; + case flashcode::State::WRITE_PROGRAM: + if (s_nLength >= 4) { + if (FMC_READY == fmc_ready_wait(0xFF)) { + /* set the PG bit to start program */ + FMC_CTL |= FMC_CTL_PG; + __ISB(); + __DSB(); + REG32(s_nAddress) = *s_pData; + __ISB(); + __DSB(); + /* reset the PG bit */ + FMC_CTL &= ~FMC_CTL_PG; + s_pData++; + s_nAddress += 4; + s_nLength -= 4; + } + } else if (s_nLength > 0) { + DEBUG_PUTS("Error!"); + } + s_State = flashcode::State::WRITE_BUSY; + return false; + break; + default: + assert(0); + __builtin_unreachable(); + break; + } + + assert(0); + __builtin_unreachable(); + return true; +} diff --git a/lib-gd32/.cproject b/lib-gd32/.cproject index bc32b5f4..15476525 100644 --- a/lib-gd32/.cproject +++ b/lib-gd32/.cproject @@ -14,7 +14,7 @@ - + @@ -100,7 +95,6 @@ - diff --git a/lib-gd32/Makefile.GD32 b/lib-gd32/Makefile.GD32 index 3bbe2a4b..a3896d58 100644 --- a/lib-gd32/Makefile.GD32 +++ b/lib-gd32/Makefile.GD32 @@ -1,79 +1,87 @@ +$(info "lib-gd32/Makefile.GD32") $(info $$FAMILY [${FAMILY}]) +$(info $$MAKE_FLAGS [${MAKE_FLAGS}]) -ifeq ($(FAMILY),) - FAMILY=gd32f20x -endif - -$(info $$FAMILY [${FAMILY}]) +DEFINES=NDEBUG -ifeq ($(findstring gd32f10x,$(FAMILY)), gd32f10x) - EXTRA_SRCDIR=gd32f10x/CMSIS/GD/GD32F10x/Source - EXTRA_SRCDIR+=gd32f10x/GD32F10x_standard_peripheral/Source -endif +EXTRA_SRCDIR= -ifeq ($(findstring gd32f20x,$(FAMILY)), gd32f20x) - EXTRA_SRCDIR=gd32f20x/CMSIS/GD/GD32F20x/Source - EXTRA_SRCDIR+=gd32f20x/GD32F20x_standard_peripheral/Source - ifeq ($(findstring ENABLE_USB_HOST,$(MAKE_FLAGS)), ENABLE_USB_HOST) - EXTRA_SRCDIR+=gd32f20x/GD32F20x_usbfs_library/host/core/Source - - EXTRA_C_SOURCE_FILES=gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usb_core.c - EXTRA_C_SOURCE_FILES+=gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usb_host.c - EXTRA_C_SOURCE_FILES+=gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usbh_int.c - - EXTRA_INCLUDES+=gd32f20x/GD32F20x_usbfs_library/driver/Include - EXTRA_INCLUDES+=gd32f20x/GD32F20x_usbfs_library/host/core/Include - EXTRA_INCLUDES+=gd32f20x/GD32F20x_usbfs_library/ustd/common - - ifeq ($(findstring CONFIG_USB_HOST_MSC,$(MAKE_FLAGS)), CONFIG_USB_HOST_MSC) - EXTRA_SRCDIR+=gd32f20x/GD32F20x_usbfs_library/host/class/msc/Source - - EXTRA_INCLUDES+=gd32f20x/GD32F20x_usbfs_library/host/class/msc/Include - EXTRA_INCLUDES+=gd32f20x/GD32F20x_usbfs_library/ustd/class/msc - - EXTRA_INCLUDES+=../lib-hal/ff12c - endif - - endif -endif +ifneq ($(MAKE_FLAGS),) + ifeq ($(findstring CONFIG_HAL_USE_SYSTICK,$(MAKE_FLAGS)), CONFIG_HAL_USE_SYSTICK) + EXTRA_SRCDIR+=src/systick + endif -ifeq ($(findstring gd32f30x,$(FAMILY)), gd32f30x) - EXTRA_SRCDIR=gd32f30x/CMSIS/GD/GD32F30x/Source - EXTRA_SRCDIR+=gd32f30x/GD32F30x_standard_peripheral/Source -endif + ifeq ($(findstring gd32f10x,$(FAMILY)), gd32f10x) + EXTRA_SRCDIR+=gd32f10x/CMSIS/GD/GD32F10x/Source + EXTRA_SRCDIR+=gd32f10x/GD32F10x_standard_peripheral/Source + EXTRA_SRCDIR+=src/f + endif -ifeq ($(findstring gd32f4xx,$(FAMILY)), gd32f4xx) - EXTRA_SRCDIR=gd32f4xx/CMSIS/GD/GD32F4xx/Source - EXTRA_SRCDIR+=gd32f4xx/GD32F4xx_standard_peripheral/Source - ifeq ($(findstring ENABLE_USB_HOST,$(MAKE_FLAGS)), ENABLE_USB_HOST) - EXTRA_SRCDIR+=gd32f4xx/GD32F4xx_usb_library/host/core/Source + ifeq ($(findstring gd32f20x,$(FAMILY)), gd32f20x) + EXTRA_SRCDIR+=gd32f20x/CMSIS/GD/GD32F20x/Source + EXTRA_SRCDIR+=gd32f20x/GD32F20x_standard_peripheral/Source - EXTRA_C_SOURCE_FILES=gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usb_core.c - EXTRA_C_SOURCE_FILES+=gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usb_host.c - EXTRA_C_SOURCE_FILES+=gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usbh_int.c - - EXTRA_INCLUDES+=gd32f4xx/GD32F4xx_usb_library/driver/Include - EXTRA_INCLUDES+=gd32f4xx/GD32F4xx_usb_library/host/core/Include - EXTRA_INCLUDES+=gd32f4xx/GD32F4xx_usb_library/ustd/common - - ifeq ($(findstring CONFIG_USB_HOST_MSC,$(MAKE_FLAGS)), CONFIG_USB_HOST_MSC) - EXTRA_SRCDIR+=gd32f4xx/GD32F4xx_usb_library/host/class/msc/Source - - EXTRA_INCLUDES+=gd32f4xx/GD32F4xx_usb_library/host/class/msc/Include - EXTRA_INCLUDES+=gd32f4xx/GD32F4xx_usb_library/ustd/class/msc - - EXTRA_INCLUDES+=../lib-hal/ff12c - endif - - endif -endif + ifeq ($(findstring ENABLE_USB_HOST,$(MAKE_FLAGS)), ENABLE_USB_HOST) + EXTRA_SRCDIR+=device/usb/f + EXTRA_SRCDIR+=gd32f20x/GD32F20x_usbfs_library/host/core/Source + EXTRA_C_SOURCE_FILES=gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usb_core.c + EXTRA_C_SOURCE_FILES+=gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usb_host.c + EXTRA_C_SOURCE_FILES+=gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usbh_int.c + + ifeq ($(findstring CONFIG_USB_HOST_MSC,$(MAKE_FLAGS)), CONFIG_USB_HOST_MSC) + EXTRA_SRCDIR+=gd32f20x/GD32F20x_usbfs_library/host/class/msc/Source + endif + endif + EXTRA_SRCDIR+=src/f + endif -$(info $$MAKE_FLAGS [${MAKE_FLAGS}]) + ifeq ($(findstring gd32f30x,$(FAMILY)), gd32f30x) + EXTRA_SRCDIR+=gd32f30x/CMSIS/GD/GD32F30x/Source + EXTRA_SRCDIR+=gd32f30x/GD32F30x_standard_peripheral/Source + EXTRA_SRCDIR+=src/f + endif + + ifeq ($(findstring gd32f4xx,$(FAMILY)), gd32f4xx) + EXTRA_SRCDIR+=gd32f4xx/CMSIS/GD/GD32F4xx/Source + EXTRA_SRCDIR+=gd32f4xx/GD32F4xx_standard_peripheral/Source + + ifeq ($(findstring ENABLE_USB_HOST,$(MAKE_FLAGS)), ENABLE_USB_HOST) + EXTRA_SRCDIR+=device/usb/f + EXTRA_SRCDIR+=gd32f4xx/GD32F4xx_usb_library/host/core/Source + EXTRA_C_SOURCE_FILES=gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usb_core.c + EXTRA_C_SOURCE_FILES+=gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usb_host.c + EXTRA_C_SOURCE_FILES+=gd32f4xx/GD32F4xx_usb_library/driver/Source/drv_usbh_int.c + + ifeq ($(findstring CONFIG_USB_HOST_MSC,$(MAKE_FLAGS)), CONFIG_USB_HOST_MSC) + EXTRA_SRCDIR+=gd32f4xx/GD32F4xx_usb_library/host/class/msc/Source + endif + endif + EXTRA_SRCDIR+=src/f + endif + + ifeq ($(findstring gd32h7xx,$(FAMILY)), gd32h7xx) + EXTRA_SRCDIR+=gd32h7xx/CMSIS/GD/GD32H7xx/Source + EXTRA_SRCDIR+=gd32h7xx/GD32H7xx_standard_peripheral/Source + + ifeq ($(findstring ENABLE_USB_HOST,$(MAKE_FLAGS)), ENABLE_USB_HOST) + EXTRA_SRCDIR+=device/usb/h + EXTRA_SRCDIR+=gd32h7xx/GD32H7xx_usbhs_library/host/core/Source + EXTRA_C_SOURCE_FILES=gd32h7xx/GD32H7xx_usbhs_library/driver/Source/drv_usb_core.c + EXTRA_C_SOURCE_FILES+=gd32h7xx/GD32H7xx_usbhs_library/driver/Source/drv_usb_host.c + EXTRA_C_SOURCE_FILES+=gd32h7xx/GD32H7xx_usbhs_library/driver/Source/drv_usbh_int.c + + ifeq ($(findstring CONFIG_USB_HOST_MSC,$(MAKE_FLAGS)), CONFIG_USB_HOST_MSC) + EXTRA_SRCDIR+=gd32h7xx/GD32H7xx_usbhs_library/host/class/msc/Source + endif + endif + EXTRA_SRCDIR+=src/h + endif -ifneq ($(MAKE_FLAGS),) ifeq ($(findstring NO_EMAC,$(MAKE_FLAGS)), NO_EMAC) else - EXTRA_SRCDIR+=device/emac + ifeq ($(findstring CONFIG_ENET_ENABLE_PTP,$(MAKE_FLAGS)), CONFIG_ENET_ENABLE_PTP) + EXTRA_SRCDIR+=src/ptp + endif endif ifeq ($(findstring CONFIG_USE_SOFTUART0,$(MAKE_FLAGS)), CONFIG_USE_SOFTUART0) @@ -85,19 +93,60 @@ ifneq ($(MAKE_FLAGS),) endif endif - ifeq ($(findstring ENABLE_PHY_SWITCH,$(MAKE_FLAGS)), ENABLE_PHY_SWITCH) - EXTRA_SRCDIR+=device/emac/dsa - endif - ifeq ($(findstring ENABLE_USB_HOST,$(MAKE_FLAGS)), ENABLE_USB_HOST) EXTRA_SRCDIR+=device/usb - endif + endif + + ifeq ($(findstring USE_FREE_RTOS,$(MAKE_FLAGS)), USE_FREE_RTOS) + EXTRA_SRCDIR+=FreeRTOS/FreeRTOS-Kernel + EXTRA_SRCDIR+=FreeRTOS/FreeRTOS-Kernel/portable/Common + ifeq ($(findstring ARM_CM3,$(MAKE_FLAGS)), ARM_CM3) +# EXTRA_SRCDIR+=FreeRTOS/FreeRTOS-Kernel/portable/GCC/ARM_CM3 + endif + ifeq ($(findstring ARM_CM3,$(MAKE_FLAGS)), ARM_CM4F) + # EXTRA_SRCDIR+=FreeRTOS/FreeRTOS-Kernel/portable/GCC/ARM_CM4F + endif + ifeq ($(findstring ARM_CM3,$(MAKE_FLAGS)), ARM_CM7) + # EXTRA_SRCDIR+=FreeRTOS/FreeRTOS-Kernel/portable/GCC/ARM_CM7/r0p1 + endif + endif else - EXTRA_SRCDIR+=device/emac device/emac/dsa + ifeq ($(FAMILY),) + ifneq (, $(shell test -d '../lib-gd32/gd32f10x' && echo -n yes)) + FAMILY=gd32f10x + EXTRA_SRCDIR+=src/f + endif + ifneq (, $(shell test -d '../lib-gd32/gd32f20x' && echo -n yes)) + FAMILY=gd32f20x + HAVE_SOFTUART=1 + # EXTRA_SRCDIR+=src/f + endif + ifneq (, $(shell test -d '../lib-gd32/gd32f30x' && echo -n yes)) + FAMILY=gd32f30x +# EXTRA_SRCDIR+=src/f + endif + ifneq (, $(shell test -d '../lib-gd32/gd32f4xx' && echo -n yes)) + FAMILY=gd32f4xx + HAVE_SOFTUART=1 +# EXTRA_SRCDIR+=src/f + endif + ifneq (, $(shell test -d '../lib-gd32/gd32h7xx' && echo -n yes)) + FAMILY=gd32h7xx + HAVE_SOFTUART=1 +# EXTRA_SRCDIR+=src/h + endif + endif + + EXTRA_SRCDIR+=device/emac EXTRA_SRCDIR+=device/usb - EXTRA_SRCDIR+=src/uart0 src/softuart0 + EXTRA_SRCDIR+=src/uart0 + ifdef HAVE_SOFTUART + EXTRA_SRCDIR+=src/softuart0 + endif DEFINES=ENABLE_USB_HOST CONFIG_USB_HOST_MSC endif +$(info $$FAMILY [${FAMILY}]) + include ../firmware-template-gd32/lib/Rules.mk \ No newline at end of file diff --git a/lib-gd32/device/usb/f/usb_conf.h b/lib-gd32/device/usb/f/usb_conf.h new file mode 100644 index 00000000..996d9704 --- /dev/null +++ b/lib-gd32/device/usb/f/usb_conf.h @@ -0,0 +1,101 @@ +/** + * usb_conf.h + * + */ +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef F_USB_CONF_H_ +#define F_USB_CONF_H_ + +#include + +#include "gd32.h" + +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wattributes" + +#if !defined (USE_USB_FS) +# define USE_USB_FS +#endif +#define USB_FS_CORE + +/******************************************************************************* + * FIFO Size Configuration in Host mode + * + * (i) Receive data FIFO size = (Largest Packet Size / 4) + 1 or + * 2x (Largest Packet Size / 4) + 1, If a + * high-bandwidth channel or multiple isochronous + * channels are enabled. + * + * (ii) For the host non periodic Transmit FIFO is the largest maximum packet size + * for all supported non periodic OUT channels. Typically, a space + * corresponding to two Largest Packet Size is recommended. + * + * (iii) The minimum amount of RAM required for Host periodic Transmit FIFO is + * the largest maximum packet size for all supported periodic OUT channels. + * If there is at least one High Bandwidth Isochronous OUT endpoint, + * then the space must be at least two times the maximum packet size for + * that channel. +*******************************************************************************/ + +#define USB_RX_FIFO_FS_SIZE 128 +#define USB_HTX_NPFIFO_FS_SIZE 96 +#define USB_HTX_PFIFO_FS_SIZE 96 + +#define USB_SOF_OUTPUT 0 +#define USB_LOW_POWER 0 + +#if defined (USB_FS_CORE) +# define USBFS_SOF_OUTPUT 0 +# define USBFS_LOW_POWER 0 +#endif + +#define USE_HOST_MODE + +#ifndef USB_FS_CORE + #ifndef USB_HS_CORE + #error "USB_HS_CORE or USB_FS_CORE should be defined" + #endif +#endif + +#ifndef USE_DEVICE_MODE + #ifndef USE_HOST_MODE + #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" + #endif +#endif + +#ifndef USE_USB_HS + #ifndef USE_USB_FS + #error "USE_USB_HS or USE_USB_FS should be defined" + #endif +#endif + +/* __packed keyword used to decrease the data type alignment to 1-byte */ +#if defined ( __GNUC__ ) /* GNU Compiler */ + #ifndef __packed + #define __packed __attribute__ ((__packed__)) + #endif +#elif defined (__TASKING__) /* TASKING Compiler */ + #define __packed __unaligned +#endif /* __GNUC__ */ + +#endif /* F_USB_CONF_H_ */ diff --git a/lib-gd32/device/usb/usb.cpp b/lib-gd32/device/usb/usb.cpp new file mode 100644 index 00000000..5faa51a4 --- /dev/null +++ b/lib-gd32/device/usb/usb.cpp @@ -0,0 +1,35 @@ +/** + * usb.cpp + * + */ +/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "gd32.h" + +extern "C" { +void usb_udelay(uint32_t nMicros) { + udelay(nMicros); +} +void usb_mdelay(uint32_t nMillis) { + udelay(nMillis * 1000U); +} +} diff --git a/lib-gd32/device/usb/usb_conf.h b/lib-gd32/device/usb/usb_conf.h new file mode 100644 index 00000000..0dcf2980 --- /dev/null +++ b/lib-gd32/device/usb/usb_conf.h @@ -0,0 +1,37 @@ +/** + * usb_conf.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef USB_CONF_H_ +#define USB_CONF_H_ + +#include "gd32.h" + +#if defined (GD32H7XX) +# include "h/usb_conf.h" +#else +# include "f/usb_conf.h" +#endif + +#endif /* USB_CONF_H_ */ diff --git a/gd32_emac_e131_dmx_multi/include/display_timeout.h b/lib-gd32/device/usb/usb_vbus.cpp similarity index 72% rename from gd32_emac_e131_dmx_multi/include/display_timeout.h rename to lib-gd32/device/usb/usb_vbus.cpp index a8556629..fc92386e 100644 --- a/gd32_emac_e131_dmx_multi/include/display_timeout.h +++ b/lib-gd32/device/usb/usb_vbus.cpp @@ -1,8 +1,8 @@ /** - * @file display_timeout.h + * usb_vbus.cpp * */ -/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,23 +23,20 @@ * THE SOFTWARE. */ -#ifndef DISPLAY_TIMEOUT_H_ -#define DISPLAY_TIMEOUT_H_ +#include +#include #include "gd32.h" -namespace display { -namespace timeout { - -void gpio_init() { - gpio_fsel(KEY2_GPIOx, KEY2_PINx, GPIO_FSEL_INPUT); +extern "C" { +void usb_vbus_drive (uint8_t state) { + printf("usb_vbus_drive: %u\n", state); +#if defined(USB_HOST_VBUS_GPIOx) + if (0U == state) { + gpio_bit_reset(USB_HOST_VBUS_GPIOx, USB_HOST_VBUS_GPIO_PINx); + } else { + gpio_bit_set(USB_HOST_VBUS_GPIOx, USB_HOST_VBUS_GPIO_PINx); + } +#endif } - -bool gpio_renew() { - return (GPIO_ISTAT(KEY2_GPIOx) & KEY2_PINx) == 0; } - -} // namespace timeout -} // namespace display - -#endif /* DISPLAY_TIMEOUT_H_ */ diff --git a/lib-network/src/emac/gd32/net.c b/lib-gd32/device/usb/usbh_conf.h similarity index 67% rename from lib-network/src/emac/gd32/net.c rename to lib-gd32/device/usb/usbh_conf.h index 5c180de9..8683ce0c 100644 --- a/lib-network/src/emac/gd32/net.c +++ b/lib-gd32/device/usb/usbh_conf.h @@ -1,8 +1,8 @@ /** - * net.c + * usbh_conf.h * */ -/* Copyright (C) 2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,27 +23,22 @@ * THE SOFTWARE. */ +#ifndef USBH_CONF_H_ +#define USBH_CONF_H_ + #include #include "gd32.h" -extern enet_descriptors_struct *dma_current_rxdesc; - -int emac_eth_recv(uint8_t **packet) { - const uint32_t size = enet_rxframe_size_get(); - - if (size > 0) { - *packet = (uint8_t *) (enet_desc_information_get(dma_current_rxdesc, RXDESC_BUFFER_1_ADDR)); - return size; - } +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" - return -1; -} +#define USBH_MAX_EP_NUM 2 +#define USBH_MAX_INTERFACES_NUM 2 +#define USBH_MAX_ALT_SETTING 2 +#define USBH_MAX_SUPPORTED_CLASS 2 -void emac_free_pkt(void) { - ENET_NOCOPY_FRAME_RECEIVE(); -} +#define USBH_DATA_BUF_MAX_LEN 0x200 +#define USBH_CFGSET_MAX_LEN 0x200 -void emac_eth_send(void *packet, int len) { - enet_frame_transmit((uint8_t *) packet, len); -} +#endif /* USBH_CONF_H_ */ diff --git a/lib-gd32/gd32f20x/CMSIS/GD/GD32F20x/Include/gd32f20x.h b/lib-gd32/gd32f20x/CMSIS/GD/GD32F20x/Include/gd32f20x.h index 1df45888..cfc73ab7 100644 --- a/lib-gd32/gd32f20x/CMSIS/GD/GD32F20x/Include/gd32f20x.h +++ b/lib-gd32/gd32f20x/CMSIS/GD/GD32F20x/Include/gd32f20x.h @@ -2,14 +2,11 @@ \file gd32f20x.h \brief general definitions for GD32F20x - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -55,42 +52,37 @@ OF SUCH DAMAGE. #error "Please select first the target gd32f20x device used in your application (in gd32f20x.h file)" #endif /* GD32F20X */ -/* enum definitions */ -typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; -typedef enum {RESET = 0, SET = !RESET} FlagStatus; -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; - /* define value of high speed crystal oscillator (HXTAL) in Hz */ #if !defined HXTAL_VALUE #ifdef GD32F20X_CL #define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */ +#endif /* GD32F20X_CL */ #endif /* HXTAL_VALUE */ -#endif /* high speed crystal oscillator value */ /* define startup timeout value of high speed crystal oscillator (HXTAL) */ #if !defined (HXTAL_STARTUP_TIMEOUT) #define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF) -#endif /* high speed crystal oscillator startup timeout */ +#endif /*HXTAL_STARTUP_TIMEOUT */ /* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ #if !defined (IRC8M_VALUE) #define IRC8M_VALUE ((uint32_t)8000000) -#endif /* internal 8MHz RC oscillator value */ +#endif /* IRC8M_VALUE */ /* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ #if !defined (IRC8M_STARTUP_TIMEOUT) #define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) -#endif /* internal 8MHz RC oscillator startup timeout */ +#endif /* IRC8M_STARTUP_TIMEOUT */ /* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ #if !defined (IRC40K_VALUE) #define IRC40K_VALUE ((uint32_t)40000) -#endif /* internal 40KHz RC oscillator value */ +#endif /* IRC40K_VALUE */ /* define value of low speed crystal oscillator (LXTAL)in Hz */ #if !defined (LXTAL_VALUE) #define LXTAL_VALUE ((uint32_t)32768) -#endif /* low speed crystal oscillator value */ +#endif /* LXTAL_VALUE */ /* GD32F20x firmware library version number V2.0 */ #define __GD32F20x_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ @@ -105,13 +97,13 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; /* configuration of the Cortex-M3 processor and core peripherals */ #define __MPU_PRESENT 0 /*!< GD32 devices does not provide an MPU */ #define __NVIC_PRIO_BITS 4 /*!< GD32F20X uses 4 bits for the Priority levels */ -#define __VENDOR_SYSTICKCONFIG 0 /*!< set to 1 if different systick config is used */ +#define __Vendor_SysTickConfig 0 /*!< set to 1 if different systick config is used */ /* define interrupt number */ typedef enum IRQn { /* Cortex-M3 processor exceptions numbers */ - NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ + NonMaskableInt_IRQn = -14, /*!< 2 non mask-able interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 memory management interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M3 bus fault interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 usage fault interrupt */ @@ -119,7 +111,7 @@ typedef enum IRQn DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 debug monitor interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M3 pend SV interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M3 system tick interrupt */ - /* interruput numbers */ + /* interrupt numbers */ WWDGT_IRQn = 0, /*!< WWDGT interrupt */ LVD_IRQn = 1, /*!< LVD from EXTI line interrupt */ TAMPER_IRQn = 2, /*!< tamper interrupt */ @@ -147,7 +139,7 @@ typedef enum IRQn TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break interrupt and TIMER8 global interrupt */ TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update Interrupt and TIMER9 global interrupt */ TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation interrupt and TIMER10 global interrupt */ - TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */ + TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */ TIMER1_IRQn = 28, /*!< TIMER1 global interrupt */ TIMER2_IRQn = 29, /*!< TIMER2 global interrupt */ TIMER3_IRQn = 30, /*!< TIMER3 global interrupt */ @@ -166,7 +158,7 @@ typedef enum IRQn TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break interrupt and TIMER11 global interrupt */ TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update interrupt and TIMER12 global interrupt */ TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation interrupt and TIMER13 global interrupt */ - TIMER7_Channel_IRQn = 46, /*!< TIMER7 Channel Capture Compare Interrupt */ + TIMER7_Channel_IRQn = 46, /*!< TIMER7 Channel Capture Compare Interrupt */ ADC2_IRQn = 47, /*!< ADC2 global interrupt */ EXMC_IRQn = 48, /*!< EXMC global interrupt */ SDIO_IRQn = 49, /*!< SDIO global interrupt */ @@ -187,19 +179,19 @@ typedef enum IRQn CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ - USBFS_IRQn = 67, /*!< USBFS global interrupt */ - DMA1_Channel5_IRQn = 69, /*!< DMA1 Channel 5 global interrupt */ - DMA1_Channel6_IRQn = 70, /*!< DMA1 Channel 6 global interrupt */ - USART5_IRQn = 71, /*!< USART5 global interrupt */ - I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */ - I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */ - DCI_IRQn = 78, /*!< DCI global interrupt */ - CAU_IRQn = 79, /*!< CAU global interrupt */ - HAU_TRNG_IRQn = 80, /*!< HAU or TRNG global interrupt */ - UART6_IRQn = 82, /*!< UART6 global interrupt */ - UART7_IRQn = 83, /*!< UART7 global interrupt */ - TLI_IRQn = 88, /*!< TLI global interrupt */ - TLI_ER_IRQn = 89 /*!< TLI global error interrupt */ + USBFS_IRQn = 67, /*!< USBFS global interrupt */ + DMA1_Channel5_IRQn = 69, /*!< DMA1 Channel 5 global interrupt */ + DMA1_Channel6_IRQn = 70, /*!< DMA1 Channel 6 global interrupt */ + USART5_IRQn = 71, /*!< USART5 global interrupt */ + I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */ + I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */ + DCI_IRQn = 78, /*!< DCI global interrupt */ + CAU_IRQn = 79, /*!< CAU global interrupt */ + HAU_TRNG_IRQn = 80, /*!< HAU or TRNG global interrupt */ + UART6_IRQn = 82, /*!< UART6 global interrupt */ + UART7_IRQn = 83, /*!< UART7 global interrupt */ + TLI_IRQn = 88, /*!< TLI global interrupt */ + TLI_ER_IRQn = 89 /*!< TLI global error interrupt */ } IRQn_Type; /* includes */ @@ -207,6 +199,12 @@ typedef enum IRQn #include "system_gd32f20x.h" #include +/* enum definitions */ +typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; +// typedef enum {FALSE = 0, TRUE = !FALSE} bool; /** AvV **/ +typedef enum {RESET = 0, SET = !RESET} FlagStatus; +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; + /* bit operations */ #define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) @@ -265,10 +263,10 @@ typedef enum IRQn #define HAU_BASE (AHB2_BUS_BASE + 0x00060400U) /*!< HAU base address */ #define TRNG_BASE (AHB2_BUS_BASE + 0x00060800U) /*!< TRNG base address */ -/* define marco USE_STDPERIPH_DRIVER */ +/* define macro USE_STDPERIPH_DRIVER */ #if !defined USE_STDPERIPH_DRIVER #define USE_STDPERIPH_DRIVER -#endif +#endif /* USE_STDPERIPH_DRIVER */ #ifdef USE_STDPERIPH_DRIVER #include "gd32f20x_libopt.h" #endif /* USE_STDPERIPH_DRIVER */ @@ -276,4 +274,5 @@ typedef enum IRQn #ifdef __cplusplus } #endif -#endif + +#endif /* GD32F20X_H */ diff --git a/lib-gd32/gd32f20x/CMSIS/GD/GD32F20x/Source/system_gd32f20x.c b/lib-gd32/gd32f20x/CMSIS/GD/GD32F20x/Source/system_gd32f20x.c index 37004d45..39beb930 100644 --- a/lib-gd32/gd32f20x/CMSIS/GD/GD32F20x/Source/system_gd32f20x.c +++ b/lib-gd32/gd32f20x/CMSIS/GD/GD32F20x/Source/system_gd32f20x.c @@ -59,6 +59,17 @@ //#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) #define __SYSTEM_CLOCK_120M_PLL_HXTAL (uint32_t)(120000000) +#define RCU_MODIFY(__delay) do{ \ + volatile uint32_t i; \ + if(0 != __delay){ \ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \ + for(i=0; i<__delay; i++){ \ + } \ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV4; \ + for(i=0; i<__delay; i++){ \ + } \ + } \ + }while(0) #define SEL_IRC8M 0x00U #define SEL_HXTAL 0x01U @@ -114,27 +125,33 @@ static void system_clock_120m_hxtal(void); static void system_clock_config(void); /*! - \brief setup the microcontroller system, initialize the system + \brief setup the micro-controller system, initialize the system \param[in] none \param[out] none \retval none */ -void SystemInit (void) +void SystemInit(void) { /* reset the RCC clock configuration to the default reset state */ /* enable IRC8M */ RCU_CTL |= RCU_CTL_IRC8MEN; + while(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ + } + RCU_MODIFY(0x50); + RCU_CFG0 &= ~RCU_CFG0_SCS; + /* reset HXTALEN, CKMEN, PLLEN bits */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */ RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL); /* reset HXTALEN, CKMEN, PLLEN bits */ - RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN ); + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); /* Reset HXTALBPS bit */ RCU_CTL &= ~(RCU_CTL_HXTALBPS); - + /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */ RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4); @@ -147,20 +164,20 @@ void SystemInit (void) /* reset INT register */ RCU_INT = 0x00FF0000U; - + /* reset CFG2 register */ RCU_CFG2 = 0x00000000U; - + /* reset PLLTCTL register */ - RCU_PLLTCTL &= (~RCU_PLLTCTL_PLLTEN); - + RCU_PLLTCTL &= (~RCU_PLLTCTL_PLLTEN); + /* reset PLLTINT register */ RCU_PLLTINT = 0x00400000U; - /* Reset PLLTCFG register */ + /* reset PLLTCFG register */ RCU_PLLTCFG = 0x20003010U; - /* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ + /* configure the system clock source, PLL multiplier, AHB/APBx prescalers and flash settings */ system_clock_config(); } /*! @@ -214,36 +231,35 @@ static void system_clock_8m_irc8m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC8M */ RCU_CTL |= RCU_CTL_IRC8MEN; - + /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do{ + do { timeout++; stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - } - while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - + } while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ - while(1){ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)) { + while(1) { } } - + /* AHB = SYSCLK */ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; /* APB2 = AHB/1 */ RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; /* APB1 = AHB/2 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - + /* select IRC8M as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_IRC8M; - + /* wait until IRC8M is selected as system clock */ - while(0U != (RCU_CFG0 & RCU_SCSS_IRC8M)){ + while(RCU_SCSS_IRC8M != (RCU_CFG0 & RCU_CFG0_SCSS)) { } } @@ -258,21 +274,20 @@ static void system_clock_48m_irc8m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC8M */ RCU_CTL |= RCU_CTL_IRC8MEN; /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do{ + do { timeout++; stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - } - while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + } while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ - while(1){ - } + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)) { + while(1) { + } } /* IRC8M is stable */ @@ -284,14 +299,14 @@ static void system_clock_48m_irc8m(void) RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL ); + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL); RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL12); /* enable PLL */ RCU_CTL |= RCU_CTL_PLLEN; /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) { } /* select PLL as system clock */ @@ -299,7 +314,7 @@ static void system_clock_48m_irc8m(void) RCU_CFG0 |= RCU_CKSYSSRC_PLL; /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + while(RCU_SCSS_PLL != (RCU_CFG0 & RCU_CFG0_SCSS)) { } } @@ -314,19 +329,19 @@ static void system_clock_72m_irc8m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC8M */ RCU_CTL |= RCU_CTL_IRC8MEN; /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do{ + do { timeout++; stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - }while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + } while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ - while(1){ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)) { + while(1) { } } @@ -339,14 +354,14 @@ static void system_clock_72m_irc8m(void) RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL ); + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL); RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18); /* enable PLL */ RCU_CTL |= RCU_CTL_PLLEN; /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) { } /* select PLL as system clock */ @@ -354,7 +369,7 @@ static void system_clock_72m_irc8m(void) RCU_CFG0 |= RCU_CKSYSSRC_PLL; /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + while(RCU_SCSS_PLL != (RCU_CFG0 & RCU_CFG0_SCSS)) { } } @@ -369,19 +384,19 @@ static void system_clock_108m_irc8m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC8M */ RCU_CTL |= RCU_CTL_IRC8MEN; /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do{ + do { timeout++; stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - }while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + } while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ - while(1){ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)) { + while(1) { } } @@ -394,14 +409,14 @@ static void system_clock_108m_irc8m(void) RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL ); + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL); RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL27); /* enable PLL */ RCU_CTL |= RCU_CTL_PLLEN; /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) { } /* select PLL as system clock */ @@ -409,7 +424,7 @@ static void system_clock_108m_irc8m(void) RCU_CFG0 |= RCU_CKSYSSRC_PLL; /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + while(RCU_SCSS_PLL != (RCU_CFG0 & RCU_CFG0_SCSS)) { } } @@ -424,19 +439,19 @@ static void system_clock_120m_irc8m(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable IRC8M */ RCU_CTL |= RCU_CTL_IRC8MEN; /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do{ + do { timeout++; stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - }while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); + } while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ - while(1){ + if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)) { + while(1) { } } @@ -449,14 +464,14 @@ static void system_clock_120m_irc8m(void) RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; /* CK_PLL = (CK_IRC8M/2) * 30 = 120 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL ); + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL); RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL30); - + /* enable PLL */ RCU_CTL |= RCU_CTL_PLLEN; /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) { } /* select PLL as system clock */ @@ -464,7 +479,7 @@ static void system_clock_120m_irc8m(void) RCU_CFG0 |= RCU_CKSYSSRC_PLL; /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + while(RCU_SCSS_PLL != (RCU_CFG0 & RCU_CFG0_SCSS)) { } } @@ -479,41 +494,41 @@ static void system_clock_hxtal(void) { uint32_t timeout = 0U; uint32_t stab_flag = 0U; - + /* enable HXTAL */ RCU_CTL |= RCU_CTL_HXTALEN; - + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ + do { timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - + } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { + while(1) { } } - + /* AHB = SYSCLK */ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; /* APB2 = AHB/1 */ RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; /* APB1 = AHB/2 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - + /* select HXTAL as system clock */ RCU_CFG0 &= ~RCU_CFG0_SCS; RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; - + /* wait until HXTAL is selected as system clock */ - while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ + while(RCU_SCSS_HXTAL != (RCU_CFG0 & RCU_CFG0_SCSS)) { } } #elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) /*! - \brief configure the system clock to 24M by PLL which selects HXTAL(8M) as its clock source + \brief configure the system clock to 24M by PLL which selects HXTAL(25M) as its clock source \param[in] none \param[out] none \retval none @@ -527,14 +542,14 @@ static void system_clock_24m_hxtal(void) RCU_CTL |= RCU_CTL_HXTALEN; /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ + do { timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { + while(1) { } } @@ -546,25 +561,25 @@ static void system_clock_24m_hxtal(void) /* APB1 = AHB/2 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - /* CK_PLL = (CK_PREDIV0) * 6 = 24 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL ); + /* CK_PLL = (CK_PREDIV0) * 6 = 24 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL); RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL6); - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - + /* enable PLL1 */ RCU_CTL |= RCU_CTL_PLL1EN; /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0) { } /* enable PLL */ RCU_CTL |= RCU_CTL_PLLEN; /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) { } /* select PLL as system clock */ @@ -572,14 +587,14 @@ static void system_clock_24m_hxtal(void) RCU_CFG0 |= RCU_CKSYSSRC_PLL; /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + while(RCU_SCSS_PLL != (RCU_CFG0 & RCU_CFG0_SCSS)) { } } #elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) /*! - \brief configure the system clock to 36M by PLL which selects HXTAL(8M) as its clock source + \brief configure the system clock to 36M by PLL which selects HXTAL(25M) as its clock source \param[in] none \param[out] none \retval none @@ -593,14 +608,14 @@ static void system_clock_36m_hxtal(void) RCU_CTL |= RCU_CTL_HXTALEN; /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ + do { timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { + while(1) { } } @@ -612,25 +627,25 @@ static void system_clock_36m_hxtal(void) /* APB1 = AHB/2 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - /* CK_PLL = (CK_PREDIV0) * 9 = 36 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL ); + /* CK_PLL = (CK_PREDIV0) * 9 = 36 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL); RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9); - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ + /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - + /* enable PLL1 */ RCU_CTL |= RCU_CTL_PLL1EN; /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0) { } /* enable PLL */ RCU_CTL |= RCU_CTL_PLLEN; /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) { } /* select PLL as system clock */ @@ -638,14 +653,14 @@ static void system_clock_36m_hxtal(void) RCU_CFG0 |= RCU_CKSYSSRC_PLL; /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + while(RCU_SCSS_PLL != (RCU_CFG0 & RCU_CFG0_SCSS)) { } } #elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) /*! - \brief configure the system clock to 48M by PLL which selects HXTAL(8M) as its clock source + \brief configure the system clock to 48M by PLL which selects HXTAL(25M) as its clock source \param[in] none \param[out] none \retval none @@ -659,14 +674,14 @@ static void system_clock_48m_hxtal(void) RCU_CTL |= RCU_CTL_HXTALEN; /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ + do { timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { + while(1) { } } @@ -678,25 +693,25 @@ static void system_clock_48m_hxtal(void) /* APB1 = AHB/2 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - /* CK_PLL = (CK_PREDIV0) * 6 = 48 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL ); + /* CK_PLL = (CK_PREDIV0) * 6 = 48 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL); RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL6); - - /* CK_PREDIV0 = (CK_HXTAL) / 5 * 8 /5 = 8 MHz */ + + /* CK_PREDIV0 = (CK_HXTAL) / 5 * 8 /5 = 8 MHz */ RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV5); - + /* enable PLL1 */ RCU_CTL |= RCU_CTL_PLL1EN; /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0) { } /* enable PLL */ RCU_CTL |= RCU_CTL_PLLEN; /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) { } /* select PLL as system clock */ @@ -704,13 +719,13 @@ static void system_clock_48m_hxtal(void) RCU_CFG0 |= RCU_CKSYSSRC_PLL; /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + while(RCU_SCSS_PLL != (RCU_CFG0 & RCU_CFG0_SCSS)) { } } #elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) /*! - \brief configure the system clock to 56M by PLL which selects HXTAL(8M) as its clock source + \brief configure the system clock to 56M by PLL which selects HXTAL(25M) as its clock source \param[in] none \param[out] none \retval none @@ -724,14 +739,14 @@ static void system_clock_56m_hxtal(void) RCU_CTL |= RCU_CTL_HXTALEN; /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ + do { timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { + while(1) { } } @@ -743,25 +758,25 @@ static void system_clock_56m_hxtal(void) /* APB1 = AHB/2 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - /* CK_PLL = (CK_PREDIV0) * 7 = 56 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL ); + /* CK_PLL = (CK_PREDIV0) * 7 = 56 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL); RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL7); - - /* CK_PREDIV0 = (CK_HXTAL) / 5 * 8 /5 = 8 MHz */ + + /* CK_PREDIV0 = (CK_HXTAL) / 5 * 8 /5 = 8 MHz */ RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV5); - + /* enable PLL1 */ RCU_CTL |= RCU_CTL_PLL1EN; /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0) { } /* enable PLL */ RCU_CTL |= RCU_CTL_PLLEN; /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) { } /* select PLL as system clock */ @@ -769,13 +784,13 @@ static void system_clock_56m_hxtal(void) RCU_CFG0 |= RCU_CKSYSSRC_PLL; /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + while(RCU_SCSS_PLL != (RCU_CFG0 & RCU_CFG0_SCSS)) { } } #elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) /*! - \brief configure the system clock to 72M by PLL which selects HXTAL(8M) as its clock source + \brief configure the system clock to 72M by PLL which selects HXTAL(25M) as its clock source \param[in] none \param[out] none \retval none @@ -789,14 +804,14 @@ static void system_clock_72m_hxtal(void) RCU_CTL |= RCU_CTL_HXTALEN; /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ + do { timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { + while(1) { } } @@ -808,26 +823,26 @@ static void system_clock_72m_hxtal(void) /* APB1 = AHB/2 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - /* CK_PLL = (CK_PREDIV0) * 9 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL ); + /* CK_PLL = (CK_PREDIV0) * 9 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL); RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9); - - /* CK_PREDIV0 = (CK_HXTAL) / 5 * 8 /5 = 8 MHz */ + + /* CK_PREDIV0 = (CK_HXTAL) / 5 * 8 /5 = 8 MHz */ RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV5); - - + + /* enable PLL1 */ RCU_CTL |= RCU_CTL_PLL1EN; /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0) { } /* enable PLL */ RCU_CTL |= RCU_CTL_PLLEN; /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) { } /* select PLL as system clock */ @@ -835,13 +850,13 @@ static void system_clock_72m_hxtal(void) RCU_CFG0 |= RCU_CKSYSSRC_PLL; /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + while(RCU_SCSS_PLL != (RCU_CFG0 & RCU_CFG0_SCSS)) { } } #elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) /*! - \brief configure the system clock to 96M by PLL which selects HXTAL(8M) as its clock source + \brief configure the system clock to 96M by PLL which selects HXTAL(25M) as its clock source \param[in] none \param[out] none \retval none @@ -855,14 +870,14 @@ static void system_clock_96m_hxtal(void) RCU_CTL |= RCU_CTL_HXTALEN; /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ + do { timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { + while(1) { } } @@ -874,25 +889,25 @@ static void system_clock_96m_hxtal(void) /* APB1 = AHB/2 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - /* CK_PLL = (CK_PREDIV0) * 12 = 96 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL ); + /* CK_PLL = (CK_PREDIV0) * 12 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL); RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL12); - - /* CK_PREDIV0 = (CK_HXTAL) / 5 * 8 /5 = 8 MHz */ + + /* CK_PREDIV0 = (CK_HXTAL) / 5 * 8 /5 = 8 MHz */ RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV5); /* enable PLL1 */ RCU_CTL |= RCU_CTL_PLL1EN; /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0) { } /* enable PLL */ RCU_CTL |= RCU_CTL_PLLEN; /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) { } /* select PLL as system clock */ @@ -900,13 +915,13 @@ static void system_clock_96m_hxtal(void) RCU_CFG0 |= RCU_CKSYSSRC_PLL; /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + while(RCU_SCSS_PLL != (RCU_CFG0 & RCU_CFG0_SCSS)) { } } #elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) /*! - \brief configure the system clock to 108M by PLL which selects HXTAL(8M) as its clock source + \brief configure the system clock to 108M by PLL which selects HXTAL(25M) as its clock source \param[in] none \param[out] none \retval none @@ -920,14 +935,14 @@ static void system_clock_108m_hxtal(void) RCU_CTL |= RCU_CTL_HXTALEN; /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ + do { timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { + while(1) { } } @@ -939,25 +954,25 @@ static void system_clock_108m_hxtal(void) /* APB1 = AHB/2 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - /* CK_PLL = (CK_PREDIV0) * 9 = 108 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL ); + /* CK_PLL = (CK_PREDIV0) * 9 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL); RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9); - - /* CK_PREDIV0 = (CK_HXTAL) / 5 * 12 /5 = 12 MHz */ + + /* CK_PREDIV0 = (CK_HXTAL) / 5 * 12 /5 = 12 MHz */ RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL12 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV5); /* enable PLL1 */ RCU_CTL |= RCU_CTL_PLL1EN; /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0) { } /* enable PLL */ RCU_CTL |= RCU_CTL_PLLEN; /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) { } /* select PLL as system clock */ @@ -965,13 +980,13 @@ static void system_clock_108m_hxtal(void) RCU_CFG0 |= RCU_CKSYSSRC_PLL; /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + while(RCU_SCSS_PLL != (RCU_CFG0 & RCU_CFG0_SCSS)) { } } #elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL) /*! - \brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source + \brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source \param[in] none \param[out] none \retval none @@ -985,14 +1000,14 @@ static void system_clock_120m_hxtal(void) RCU_CTL |= RCU_CTL_HXTALEN; /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ + do { timeout++; stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { + while(1) { } } @@ -1004,25 +1019,25 @@ static void system_clock_120m_hxtal(void) /* APB1 = AHB/2 */ RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - /* CK_PLL = (CK_PREDIV0) * 10 = 120 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL ); + /* CK_PLL = (CK_PREDIV0) * 10 = 120 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLSEL); RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL10); - - /* CK_PREDIV0 = (CK_HXTAL) / 5 * 12 /5 = 12 MHz */ + + /* CK_PREDIV0 = (CK_HXTAL) / 5 * 12 /5 = 12 MHz */ RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL12 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV5); /* enable PLL1 */ RCU_CTL |= RCU_CTL_PLL1EN; /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){ + while((RCU_CTL & RCU_CTL_PLL1STB) == 0U) { } - + /* enable PLL */ RCU_CTL |= RCU_CTL_PLLEN; /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)) { } /* select PLL as system clock */ @@ -1030,26 +1045,28 @@ static void system_clock_120m_hxtal(void) RCU_CFG0 |= RCU_CKSYSSRC_PLL; /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ + while(RCU_SCSS_PLL != (RCU_CFG0 & RCU_CFG0_SCSS)) { } } #endif /* __SYSTEM_CLOCK_IRC8M */ /*! - \brief update the SystemCoreClock with current core clock retrieved from cpu registers + \brief update the SystemCoreClock with current core clock retrieved from CPU registers \param[in] none \param[out] none \retval none */ -void SystemCoreClockUpdate (void) +void SystemCoreClockUpdate(void) { uint32_t sws; - uint32_t pllsel, predv0sel, pllmf,ck_src; + uint32_t pllsel, predv0sel, pllmf, ck_src, idx, clk_exp; uint32_t predv0, predv1, pll1mf; + /* exponent of AHB, APB1 and APB2 clock divider */ + const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; sws = GET_BITS(RCU_CFG0, 2, 3); - switch(sws){ + switch(sws) { /* IRC8M is selected as CK_SYS */ case SEL_IRC8M: SystemCoreClock = IRC8M_VALUE; @@ -1063,46 +1080,46 @@ void SystemCoreClockUpdate (void) /* PLL clock source selection, HXTAL or IRC8M/2 */ pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); - if (RCU_PLLSRC_HXTAL == pllsel) { + if(RCU_PLLSRC_HXTAL == pllsel) { /* PLL clock source is HXTAL */ ck_src = HXTAL_VALUE; predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); /* source clock use PLL1 */ - if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ + if(RCU_PREDV0SRC_CKPLL1 == predv0sel) { predv1 = (uint32_t)((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; - if(17U == pll1mf){ + if(17U == pll1mf) { pll1mf = 20U; } - ck_src = (ck_src/predv1)*pll1mf; + ck_src = (ck_src / predv1) * pll1mf; } predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; ck_src /= predv0; - }else{ + } else { /* PLL clock source is IRC8M/2 */ - ck_src = IRC8M_VALUE/2U; + ck_src = IRC8M_VALUE / 2U; } /* PLL multiplication factor */ pllmf = GET_BITS(RCU_CFG0, 18, 21); - if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ + if((RCU_CFG0 & RCU_CFG0_PLLMF_4)) { pllmf |= 0x10U; } - if(13U == pllmf){ + if(13U == pllmf) { /* PLL source clock multiply by 6.5 */ - SystemCoreClock = ck_src*6U + ck_src/2U; - }else{ - if(pllmf < 15U){ + SystemCoreClock = ck_src * 6U + ck_src / 2U; + } else { + if(pllmf < 15U) { pllmf += 2U; - }else{ + } else { pllmf += 1U; } - SystemCoreClock = ck_src*pllmf; + SystemCoreClock = ck_src * pllmf; } - + break; /* IRC8M is selected as CK_SYS */ default: @@ -1110,4 +1127,8 @@ void SystemCoreClockUpdate (void) break; } + /* calculate AHB clock frequency */ + idx = GET_BITS(RCU_CFG0, 4, 7); + clk_exp = ahb_exp[idx]; + SystemCoreClock = SystemCoreClock >> clk_exp; } diff --git a/lib-gd32/gd32f20x/CMSIS/core_cm3.h b/lib-gd32/gd32f20x/CMSIS/core_cm3.h deleted file mode 100644 index 248d1e4c..00000000 --- a/lib-gd32/gd32f20x/CMSIS/core_cm3.h +++ /dev/null @@ -1,1638 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V3.30 - * @date 17. February 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) /* Cosmic */ - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/lib-gd32/gd32f20x/CMSIS/core_cmFunc.h b/lib-gd32/gd32f20x/CMSIS/core_cmFunc.h deleted file mode 100644 index adb07b5d..00000000 --- a/lib-gd32/gd32f20x/CMSIS/core_cmFunc.h +++ /dev/null @@ -1,616 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.01 - * @date 06. March 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/lib-gd32/gd32f20x/CMSIS/core_cmInstr.h b/lib-gd32/gd32f20x/CMSIS/core_cmInstr.h deleted file mode 100644 index 624c175f..00000000 --- a/lib-gd32/gd32f20x/CMSIS/core_cmInstr.h +++ /dev/null @@ -1,618 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.01 - * @date 06. March 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - uint32_t result; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - - __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); - return(op1); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint8_t result; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint16_t result; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint8_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_adc.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_adc.h index 265cbfa0..fb18a2bc 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_adc.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_adc.h @@ -2,36 +2,33 @@ \file gd32f20x_adc.h \brief definitions for the ADC - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -42,31 +39,31 @@ OF SUCH DAMAGE. /* ADC definitions */ #define ADC0 ADC_BASE -#define ADC1 (ADC_BASE + 0x400U) -#define ADC2 (ADC_BASE + 0x1800U) +#define ADC1 (ADC_BASE + 0x00000400U) +#define ADC2 (ADC_BASE + 0x00001800U) /* registers definitions */ -#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ -#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ -#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ -#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ -#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ -#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ -#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ -#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ -#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ -#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ -#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ -#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */ -#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */ -#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */ -#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ -#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ -#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ -#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ -#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ -#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */ -#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */ +#define ADC_STAT(adcx) REG32((adcx) + 0x00000000U) /*!< ADC status register */ +#define ADC_CTL0(adcx) REG32((adcx) + 0x00000004U) /*!< ADC control register 0 */ +#define ADC_CTL1(adcx) REG32((adcx) + 0x00000008U) /*!< ADC control register 1 */ +#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0000000CU) /*!< ADC sampling time register 0 */ +#define ADC_SAMPT1(adcx) REG32((adcx) + 0x00000010U) /*!< ADC sampling time register 1 */ +#define ADC_IOFF0(adcx) REG32((adcx) + 0x00000014U) /*!< ADC inserted channel data offset register 0 */ +#define ADC_IOFF1(adcx) REG32((adcx) + 0x00000018U) /*!< ADC inserted channel data offset register 1 */ +#define ADC_IOFF2(adcx) REG32((adcx) + 0x0000001CU) /*!< ADC inserted channel data offset register 2 */ +#define ADC_IOFF3(adcx) REG32((adcx) + 0x00000020U) /*!< ADC inserted channel data offset register 3 */ +#define ADC_WDHT(adcx) REG32((adcx) + 0x00000024U) /*!< ADC watchdog high threshold register */ +#define ADC_WDLT(adcx) REG32((adcx) + 0x00000028U) /*!< ADC watchdog low threshold register */ +#define ADC_RSQ0(adcx) REG32((adcx) + 0x0000002CU) /*!< ADC regular sequence register 0 */ +#define ADC_RSQ1(adcx) REG32((adcx) + 0x00000030U) /*!< ADC regular sequence register 1 */ +#define ADC_RSQ2(adcx) REG32((adcx) + 0x00000034U) /*!< ADC regular sequence register 2 */ +#define ADC_ISQ(adcx) REG32((adcx) + 0x00000038U) /*!< ADC inserted sequence register */ +#define ADC_IDATA0(adcx) REG32((adcx) + 0x0000003CU) /*!< ADC inserted data register 0 */ +#define ADC_IDATA1(adcx) REG32((adcx) + 0x00000040U) /*!< ADC inserted data register 1 */ +#define ADC_IDATA2(adcx) REG32((adcx) + 0x00000044U) /*!< ADC inserted data register 2 */ +#define ADC_IDATA3(adcx) REG32((adcx) + 0x00000048U) /*!< ADC inserted data register 3 */ +#define ADC_RDATA(adcx) REG32((adcx) + 0x0000004CU) /*!< ADC regular data register */ +#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x00000080U) /*!< ADC oversampling control register */ /* bits definitions */ /* ADC_STAT */ @@ -96,7 +93,7 @@ OF SUCH DAMAGE. #define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ #define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ -#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ +#define ADC_CTL1_DMA BIT(8) /*!< DMA request enable */ #define ADC_CTL1_DAL BIT(11) /*!< data alignment */ #define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ #define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ @@ -138,15 +135,15 @@ OF SUCH DAMAGE. #define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ #define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ #define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ -#define ADC_OVSAMPCTL_DRES BITS(12,13) /*!< oversampling shift */ +#define ADC_OVSAMPCTL_DRES BITS(12, 13) /*!< ADC resolution */ /* constants definitions */ -/* adc_stat register value */ -#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ -#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion flag */ -#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted channel group conversion flag */ -#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ -#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ +/* ADC flag definitions */ +#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ +#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ +#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted channel group conversion flag */ +#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ +#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ /* adc_ctl0 register value */ #define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ @@ -198,7 +195,7 @@ OF SUCH DAMAGE. #define ADC2_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(5) /*!< TIMER4 CH0 event select */ #define ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6) /*!< TIMER4 CH2 event select */ -/* external trigger mode for inserted channel */ +/* ADC external trigger select for inserted channel */ #define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ /* for ADC0 and ADC1 inserted channel */ #define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ @@ -246,12 +243,14 @@ OF SUCH DAMAGE. #define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ /* adc_ovsampctl register value */ +/* ADC resolution */ #define OVSAMPCTL_DRES(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_OVSAMPCTL_DRES bit field */ #define ADC_RESOLUTION_12B OVSAMPCTL_DRES(0) /*!< 12-bit ADC resolution */ #define ADC_RESOLUTION_10B OVSAMPCTL_DRES(1) /*!< 10-bit ADC resolution */ #define ADC_RESOLUTION_8B OVSAMPCTL_DRES(2) /*!< 8-bit ADC resolution */ #define ADC_RESOLUTION_6B OVSAMPCTL_DRES(3) /*!< 6-bit ADC resolution */ +/* oversampling shift */ #define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ #define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ #define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ @@ -263,6 +262,7 @@ OF SUCH DAMAGE. #define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ #define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ +/* oversampling ratio */ #define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ #define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ #define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ @@ -273,6 +273,7 @@ OF SUCH DAMAGE. #define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ #define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ +/* triggered oversampling */ #define ADC_OVERSAMPLING_ALL_CONVERT 0U /*!< all oversampled conversions for a channel are done consecutively after a trigger */ #define ADC_OVERSAMPLING_ONE_CONVERT 1U /*!< each oversampled conversion for a channel needs a trigger */ @@ -367,7 +368,7 @@ void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, /* enable ADC software trigger */ void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group); -/* get channel data */ +/* ADC data read functions */ /* read ADC regular group data register */ uint16_t adc_regular_data_read(uint32_t adc_periph); /* read ADC inserted group data register */ @@ -375,7 +376,7 @@ uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel); /* read the last ADC0 and ADC1 conversion result data in sync mode */ uint32_t adc_sync_mode_convert_value_read(void); -/* watchdog configure */ +/* ADC analog watchdog functions */ /* configure ADC analog watchdog single channel */ void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel); /* configure ADC analog watchdog group channel */ @@ -385,20 +386,6 @@ void adc_watchdog_disable(uint32_t adc_periph); /* configure ADC analog watchdog threshold */ void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold); -/* interrupt & flag functions */ -/* get the ADC flag bits */ -FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag); -/* clear the ADC flag bits */ -void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag); -/* get the ADC interrupt flag */ -FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt); -/* clear the ADC interrupt flag */ -void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt); -/* enable ADC interrupt */ -void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt); -/* disable ADC interrupt */ -void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt); - /* configure ADC resolution */ void adc_resolution_config(uint32_t adc_periph, uint32_t resolution); /* configure ADC oversample mode */ @@ -408,4 +395,18 @@ void adc_oversample_mode_enable(uint32_t adc_periph); /* disable ADC oversample mode */ void adc_oversample_mode_disable(uint32_t adc_periph); +/* interrupt & flag functions */ +/* get the ADC flag */ +FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag); +/* clear the ADC flag */ +void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag); +/* enable ADC interrupt */ +void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt); +/* disable ADC interrupt */ +void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt); +/* get the ADC interrupt flag */ +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt); +/* clear the ADC interrupt flag */ +void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt); + #endif /* GD32F20X_ADC_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_bkp.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_bkp.h index fe853a8a..2453d790 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_bkp.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_bkp.h @@ -2,36 +2,33 @@ \file gd32f20x_bkp.h \brief definitions for the BKP - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -111,13 +108,13 @@ OF SUCH DAMAGE. #define BKP_TPCS_TER0 BIT(0) /*!< tamper0 event reset */ #define BKP_TPCS_TIR0 BIT(1) /*!< tamper0 interrupt reset */ #define BKP_TPCS_TPIE0 BIT(2) /*!< tamper0 interrupt enable */ -#define BKP_TPCS_TER1 BIT(5) /*!< tamper1 event reset */ -#define BKP_TPCS_TIR1 BIT(6) /*!< tamper1 interrupt reset */ -#define BKP_TPCS_TPIE1 BIT(7) /*!< tamper1 interrupt enable */ +#define BKP_TPCS_TER1 BIT(5) /*!< tamper1/waveform detect event reset */ +#define BKP_TPCS_TIR1 BIT(6) /*!< tamper1/waveform detect interrupt reset */ +#define BKP_TPCS_TPIE1 BIT(7) /*!< tamper1/waveform detect interrupt enable */ #define BKP_TPCS_TEF0 BIT(8) /*!< tamper0 event flag */ #define BKP_TPCS_TIF0 BIT(9) /*!< tamper0 interrupt flag */ -#define BKP_TPCS_TEF1 BIT(14) /*!< tamper1 event flag */ -#define BKP_TPCS_TIF1 BIT(15) /*!< tamper1 interrupt flag */ +#define BKP_TPCS_TEF1 BIT(14) /*!< tamper1/waveform detect event flag */ +#define BKP_TPCS_TIF1 BIT(15) /*!< tamper1/waveform detect interrupt flag */ /* BKP_TPCTL1 */ #define BKP_TPCTL1_TPEN1 BIT(8) /*!< tamper1 detection enable */ @@ -126,16 +123,8 @@ OF SUCH DAMAGE. #define BKP_TPCTL1_TPM1 BIT(15) /*!< the first waveform detection enable */ /* constants definitions */ -/* tamperx definitions */ -typedef enum -{ - TAMPER_0 = 0, /*!< BKP tamper0 */ - TAMPER_1, /*!< BKP tamper1 */ -}bkp_tamper_enum; - /* BKP data register number */ -typedef enum -{ +typedef enum { BKP_DATA_0 = 1, /*!< BKP data register 0 */ BKP_DATA_1, /*!< BKP data register 1 */ BKP_DATA_2, /*!< BKP data register 2 */ @@ -177,8 +166,14 @@ typedef enum BKP_DATA_38, /*!< BKP data register 38 */ BKP_DATA_39, /*!< BKP data register 39 */ BKP_DATA_40, /*!< BKP data register 40 */ - BKP_DATA_41, /*!< BKP data register 41 */ -}bkp_data_register_enum; + BKP_DATA_41 /*!< BKP data register 41 */ +} bkp_data_register_enum; + +/* tamperx definitions */ +typedef enum { + TAMPER_0 = 0, /*!< BKP tamper0 */ + TAMPER_1 /*!< BKP tamper1 */ +} bkp_tamper_enum; /* BKP register */ #define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U) @@ -199,7 +194,7 @@ typedef enum #define RTC_CLOCK_DIV1 ((uint16_t)0x4000U) /*!< RTC clock div 1 */ /* RTC clock calibration direction */ -#define RTC_CLOCK_SLOWED_DOWN ((uint16_t)0x0000U) /*!< RTC clock slow down */ +#define RTC_CLOCK_SLOW_DOWN ((uint16_t)0x0000U) /*!< RTC clock slow down */ #define RTC_CLOCK_SPEED_UP ((uint16_t)0x8000U) /*!< RTC clock speed up */ /* tamper pin active level */ @@ -210,6 +205,10 @@ typedef enum #define BKP_FLAG_TAMPER0 BKP_TPCS_TEF0 /*!< tamper0 event flag */ #define BKP_FLAG_TAMPER1_WAVEDETECT BKP_TPCS_TEF1 /*!< tamper1/waveform detect event flag */ +/* tamper interrupt */ +#define BKP_INT_TAMPER0 BKP_TPCS_TPIE0 /*!< tamper0 interrupt */ +#define BKP_INT_TAMPER1_WAVEDETECT BKP_TPCS_TPIE1 /*!< tamper1/waveform detect interrupt */ + /* tamper interrupt flag */ #define BKP_INT_FLAG_TAMPER0 BKP_TPCS_TIF0 /*!< tamper0 interrupt flag */ #define BKP_INT_FLAG_TAMPER1_WAVEDETECT BKP_TPCS_TIF1 /*!< tamper1/waveform detect interrupt flag */ @@ -253,21 +252,21 @@ void bkp_tamper_detection_enable(bkp_tamper_enum tamperx); void bkp_tamper_detection_disable(bkp_tamper_enum tamperx); /* set tamper pin active level */ void bkp_tamper_active_level_set(bkp_tamper_enum tamperx, uint16_t level); +/* waveform detect configure */ +void bkp_waveform_detect_config(uint16_t waveform_detect_mode, ControlStatus newvalue); /* interrupt & flag functions */ -/* enable tamper pin interrupt */ -void bkp_tamper_interrupt_enable(bkp_tamper_enum tamperx); -/* disable tamper pin interrupt */ -void bkp_tamper_interrupt_disable(bkp_tamper_enum tamperx); -/* waveform detect configure */ -void bkp_waveform_detect_enable(uint16_t waveform_detect_mode, ControlStatus newvalue); -/* get BKP flag state */ +/* get BKP flag */ FlagStatus bkp_flag_get(uint16_t flag); -/* clear BKP flag state */ +/* clear BKP flag */ void bkp_flag_clear(uint16_t flag); -/* get BKP interrupt flag state */ +/* enable tamper interrupt */ +void bkp_tamper_interrupt_enable(uint16_t bkp_interrupt); +/* disable tamper interrupt */ +void bkp_tamper_interrupt_disable(uint16_t bkp_interrupt); +/* get BKP interrupt flag */ FlagStatus bkp_interrupt_flag_get(uint16_t flag); -/* clear BKP interrupt flag state */ +/* clear BKP interrupt flag */ void bkp_interrupt_flag_clear(uint16_t flag); #endif /* GD32F20X_BKP_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_can.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_can.h index 0f25d4a8..c4e089cf 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_can.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_can.h @@ -2,37 +2,33 @@ \file gd32f20x_can.h \brief definitions for the CAN - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x - \version 2019-11-27, V2.1.1, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -42,115 +38,115 @@ OF SUCH DAMAGE. #include "gd32f20x.h" /* CAN definitions */ -#define CAN0 CAN_BASE /*!< CAN0 base address */ -#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ +#define CAN0 CAN_BASE /*!< CAN0 base address */ +#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ /* registers definitions */ -#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */ -#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ -#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/ -#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */ -#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */ -#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */ -#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */ -#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */ -#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */ -#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */ -#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */ -#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */ -#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */ -#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */ -#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */ -#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */ -#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */ -#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */ -#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */ -#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */ -#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */ -#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */ -#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */ -#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */ -#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */ -#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */ -#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */ -#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */ -#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */ -#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */ -#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */ -#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */ -#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */ -#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */ -#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */ -#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */ -#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */ -#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */ -#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */ -#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */ -#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */ -#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */ -#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */ -#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */ -#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */ -#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */ -#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */ -#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */ -#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */ -#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */ -#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */ -#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */ -#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */ -#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */ -#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */ -#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */ -#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */ -#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */ -#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */ -#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */ -#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */ -#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */ -#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */ -#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */ -#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */ -#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */ -#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */ -#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */ -#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */ -#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */ -#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */ -#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */ -#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */ -#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */ -#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */ -#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */ -#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */ -#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */ -#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */ -#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */ -#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */ -#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */ -#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */ -#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */ -#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */ -#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */ -#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */ -#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */ -#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ +#define CAN_CTL(canx) REG32((canx) + 0x00000000U) /*!< CAN control register */ +#define CAN_STAT(canx) REG32((canx) + 0x00000004U) /*!< CAN status register */ +#define CAN_TSTAT(canx) REG32((canx) + 0x00000008U) /*!< CAN transmit status register*/ +#define CAN_RFIFO0(canx) REG32((canx) + 0x0000000CU) /*!< CAN receive FIFO0 register */ +#define CAN_RFIFO1(canx) REG32((canx) + 0x00000010U) /*!< CAN receive FIFO1 register */ +#define CAN_INTEN(canx) REG32((canx) + 0x00000014U) /*!< CAN interrupt enable register */ +#define CAN_ERR(canx) REG32((canx) + 0x00000018U) /*!< CAN error register */ +#define CAN_BT(canx) REG32((canx) + 0x0000001CU) /*!< CAN bit timing register */ +#define CAN_TMI0(canx) REG32((canx) + 0x00000180U) /*!< CAN transmit mailbox0 identifier register */ +#define CAN_TMP0(canx) REG32((canx) + 0x00000184U) /*!< CAN transmit mailbox0 property register */ +#define CAN_TMDATA00(canx) REG32((canx) + 0x00000188U) /*!< CAN transmit mailbox0 data0 register */ +#define CAN_TMDATA10(canx) REG32((canx) + 0x0000018CU) /*!< CAN transmit mailbox0 data1 register */ +#define CAN_TMI1(canx) REG32((canx) + 0x00000190U) /*!< CAN transmit mailbox1 identifier register */ +#define CAN_TMP1(canx) REG32((canx) + 0x00000194U) /*!< CAN transmit mailbox1 property register */ +#define CAN_TMDATA01(canx) REG32((canx) + 0x00000198U) /*!< CAN transmit mailbox1 data0 register */ +#define CAN_TMDATA11(canx) REG32((canx) + 0x0000019CU) /*!< CAN transmit mailbox1 data1 register */ +#define CAN_TMI2(canx) REG32((canx) + 0x000001A0U) /*!< CAN transmit mailbox2 identifier register */ +#define CAN_TMP2(canx) REG32((canx) + 0x000001A4U) /*!< CAN transmit mailbox2 property register */ +#define CAN_TMDATA02(canx) REG32((canx) + 0x000001A8U) /*!< CAN transmit mailbox2 data0 register */ +#define CAN_TMDATA12(canx) REG32((canx) + 0x000001ACU) /*!< CAN transmit mailbox2 data1 register */ +#define CAN_RFIFOMI0(canx) REG32((canx) + 0x000001B0U) /*!< CAN receive FIFO0 mailbox identifier register */ +#define CAN_RFIFOMP0(canx) REG32((canx) + 0x000001B4U) /*!< CAN receive FIFO0 mailbox property register */ +#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x000001B8U) /*!< CAN receive FIFO0 mailbox data0 register */ +#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x000001BCU) /*!< CAN receive FIFO0 mailbox data1 register */ +#define CAN_RFIFOMI1(canx) REG32((canx) + 0x000001C0U) /*!< CAN receive FIFO1 mailbox identifier register */ +#define CAN_RFIFOMP1(canx) REG32((canx) + 0x000001C4U) /*!< CAN receive FIFO1 mailbox property register */ +#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x000001C8U) /*!< CAN receive FIFO1 mailbox data0 register */ +#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x000001CCU) /*!< CAN receive FIFO1 mailbox data1 register */ +#define CAN_FCTL(canx) REG32((canx) + 0x00000200U) /*!< CAN filter control register */ +#define CAN_FMCFG(canx) REG32((canx) + 0x00000204U) /*!< CAN filter mode register */ +#define CAN_FSCFG(canx) REG32((canx) + 0x0000020CU) /*!< CAN filter scale register */ +#define CAN_FAFIFO(canx) REG32((canx) + 0x00000214U) /*!< CAN filter associated FIFO register */ +#define CAN_FW(canx) REG32((canx) + 0x0000021CU) /*!< CAN filter working register */ +#define CAN_F0DATA0(canx) REG32((canx) + 0x00000240U) /*!< CAN filter 0 data 0 register */ +#define CAN_F1DATA0(canx) REG32((canx) + 0x00000248U) /*!< CAN filter 1 data 0 register */ +#define CAN_F2DATA0(canx) REG32((canx) + 0x00000250U) /*!< CAN filter 2 data 0 register */ +#define CAN_F3DATA0(canx) REG32((canx) + 0x00000258U) /*!< CAN filter 3 data 0 register */ +#define CAN_F4DATA0(canx) REG32((canx) + 0x00000260U) /*!< CAN filter 4 data 0 register */ +#define CAN_F5DATA0(canx) REG32((canx) + 0x00000268U) /*!< CAN filter 5 data 0 register */ +#define CAN_F6DATA0(canx) REG32((canx) + 0x00000270U) /*!< CAN filter 6 data 0 register */ +#define CAN_F7DATA0(canx) REG32((canx) + 0x00000278U) /*!< CAN filter 7 data 0 register */ +#define CAN_F8DATA0(canx) REG32((canx) + 0x00000280U) /*!< CAN filter 8 data 0 register */ +#define CAN_F9DATA0(canx) REG32((canx) + 0x00000288U) /*!< CAN filter 9 data 0 register */ +#define CAN_F10DATA0(canx) REG32((canx) + 0x00000290U) /*!< CAN filter 10 data 0 register */ +#define CAN_F11DATA0(canx) REG32((canx) + 0x00000298U) /*!< CAN filter 11 data 0 register */ +#define CAN_F12DATA0(canx) REG32((canx) + 0x000002A0U) /*!< CAN filter 12 data 0 register */ +#define CAN_F13DATA0(canx) REG32((canx) + 0x000002A8U) /*!< CAN filter 13 data 0 register */ +#define CAN_F14DATA0(canx) REG32((canx) + 0x000002B0U) /*!< CAN filter 14 data 0 register */ +#define CAN_F15DATA0(canx) REG32((canx) + 0x000002B8U) /*!< CAN filter 15 data 0 register */ +#define CAN_F16DATA0(canx) REG32((canx) + 0x000002C0U) /*!< CAN filter 16 data 0 register */ +#define CAN_F17DATA0(canx) REG32((canx) + 0x000002C8U) /*!< CAN filter 17 data 0 register */ +#define CAN_F18DATA0(canx) REG32((canx) + 0x000002D0U) /*!< CAN filter 18 data 0 register */ +#define CAN_F19DATA0(canx) REG32((canx) + 0x000002D8U) /*!< CAN filter 19 data 0 register */ +#define CAN_F20DATA0(canx) REG32((canx) + 0x000002E0U) /*!< CAN filter 20 data 0 register */ +#define CAN_F21DATA0(canx) REG32((canx) + 0x000002E8U) /*!< CAN filter 21 data 0 register */ +#define CAN_F22DATA0(canx) REG32((canx) + 0x000002F0U) /*!< CAN filter 22 data 0 register */ +#define CAN_F23DATA0(canx) REG32((canx) + 0x000003F8U) /*!< CAN filter 23 data 0 register */ +#define CAN_F24DATA0(canx) REG32((canx) + 0x00000300U) /*!< CAN filter 24 data 0 register */ +#define CAN_F25DATA0(canx) REG32((canx) + 0x00000308U) /*!< CAN filter 25 data 0 register */ +#define CAN_F26DATA0(canx) REG32((canx) + 0x00000310U) /*!< CAN filter 26 data 0 register */ +#define CAN_F27DATA0(canx) REG32((canx) + 0x00000318U) /*!< CAN filter 27 data 0 register */ +#define CAN_F0DATA1(canx) REG32((canx) + 0x00000244U) /*!< CAN filter 0 data 1 register */ +#define CAN_F1DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 1 data 1 register */ +#define CAN_F2DATA1(canx) REG32((canx) + 0x00000254U) /*!< CAN filter 2 data 1 register */ +#define CAN_F3DATA1(canx) REG32((canx) + 0x0000025CU) /*!< CAN filter 3 data 1 register */ +#define CAN_F4DATA1(canx) REG32((canx) + 0x00000264U) /*!< CAN filter 4 data 1 register */ +#define CAN_F5DATA1(canx) REG32((canx) + 0x0000026CU) /*!< CAN filter 5 data 1 register */ +#define CAN_F6DATA1(canx) REG32((canx) + 0x00000274U) /*!< CAN filter 6 data 1 register */ +#define CAN_F7DATA1(canx) REG32((canx) + 0x0000027CU) /*!< CAN filter 7 data 1 register */ +#define CAN_F8DATA1(canx) REG32((canx) + 0x00000284U) /*!< CAN filter 8 data 1 register */ +#define CAN_F9DATA1(canx) REG32((canx) + 0x0000028CU) /*!< CAN filter 9 data 1 register */ +#define CAN_F10DATA1(canx) REG32((canx) + 0x00000294U) /*!< CAN filter 10 data 1 register */ +#define CAN_F11DATA1(canx) REG32((canx) + 0x0000029CU) /*!< CAN filter 11 data 1 register */ +#define CAN_F12DATA1(canx) REG32((canx) + 0x000002A4U) /*!< CAN filter 12 data 1 register */ +#define CAN_F13DATA1(canx) REG32((canx) + 0x000002ACU) /*!< CAN filter 13 data 1 register */ +#define CAN_F14DATA1(canx) REG32((canx) + 0x000002B4U) /*!< CAN filter 14 data 1 register */ +#define CAN_F15DATA1(canx) REG32((canx) + 0x000002BCU) /*!< CAN filter 15 data 1 register */ +#define CAN_F16DATA1(canx) REG32((canx) + 0x000002C4U) /*!< CAN filter 16 data 1 register */ +#define CAN_F17DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 17 data 1 register */ +#define CAN_F18DATA1(canx) REG32((canx) + 0x000002D4U) /*!< CAN filter 18 data 1 register */ +#define CAN_F19DATA1(canx) REG32((canx) + 0x000002DCU) /*!< CAN filter 19 data 1 register */ +#define CAN_F20DATA1(canx) REG32((canx) + 0x000002E4U) /*!< CAN filter 20 data 1 register */ +#define CAN_F21DATA1(canx) REG32((canx) + 0x000002ECU) /*!< CAN filter 21 data 1 register */ +#define CAN_F22DATA1(canx) REG32((canx) + 0x000002F4U) /*!< CAN filter 22 data 1 register */ +#define CAN_F23DATA1(canx) REG32((canx) + 0x000002FCU) /*!< CAN filter 23 data 1 register */ +#define CAN_F24DATA1(canx) REG32((canx) + 0x00000304U) /*!< CAN filter 24 data 1 register */ +#define CAN_F25DATA1(canx) REG32((canx) + 0x0000030CU) /*!< CAN filter 25 data 1 register */ +#define CAN_F26DATA1(canx) REG32((canx) + 0x00000314U) /*!< CAN filter 26 data 1 register */ +#define CAN_F27DATA1(canx) REG32((canx) + 0x0000031CU) /*!< CAN filter 27 data 1 register */ /* CAN transmit mailbox bank */ -#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ -#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ -#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ -#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ +#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ +#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ +#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ +#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ /* CAN filter bank */ -#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ -#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ +#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ +#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ -/* CAN receive fifo mailbox bank */ -#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ -#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ -#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ -#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ +/* CAN receive FIFO mailbox bank */ +#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ +#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ +#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ +#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ /* bits definitions */ /* CAN_CTL */ @@ -296,10 +292,10 @@ OF SUCH DAMAGE. #define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ /* CAN_FMCFG */ -#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ +#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask */ /* CAN_FSCFG */ -#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/ +#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits */ /* CAN_FAFIFO */ #define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ @@ -329,56 +325,54 @@ OF SUCH DAMAGE. #define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ /* CAN flags */ -typedef enum -{ +typedef enum { /* flags in STAT register */ - CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */ - CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */ - CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */ - CAN_FLAG_TS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< transmitting state */ - CAN_FLAG_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change flag of entering sleep working mode */ - CAN_FLAG_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change flag of wakeup from sleep working mode */ - CAN_FLAG_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error flag */ - CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */ - CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */ + CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */ + CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */ + CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */ + CAN_FLAG_TS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< transmitting state */ + CAN_FLAG_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change flag of entering sleep working mode */ + CAN_FLAG_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change flag of wakeup from sleep working mode */ + CAN_FLAG_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error flag */ + CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */ + CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */ /* flags in TSTAT register */ - CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in Tx FIFO */ - CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in Tx FIFO */ - CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in Tx FIFO */ - CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */ - CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */ - CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */ - CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ - CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ - CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ - CAN_FLAG_MAL2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 18U), /*!< mailbox 2 arbitration lost */ - CAN_FLAG_MAL1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 10U), /*!< mailbox 1 arbitration lost */ - CAN_FLAG_MAL0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 2U), /*!< mailbox 0 arbitration lost */ - CAN_FLAG_MTFNERR2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 17U), /*!< mailbox 2 transmit finished with no error */ - CAN_FLAG_MTFNERR1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 9U), /*!< mailbox 1 transmit finished with no error */ - CAN_FLAG_MTFNERR0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 1U), /*!< mailbox 0 transmit finished with no error */ - CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ - CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ - CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ + CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in TX FIFO */ + CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in TX FIFO */ + CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in TX FIFO */ + CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */ + CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */ + CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */ + CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ + CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ + CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ + CAN_FLAG_MAL2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 18U), /*!< mailbox 2 arbitration lost */ + CAN_FLAG_MAL1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 10U), /*!< mailbox 1 arbitration lost */ + CAN_FLAG_MAL0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 2U), /*!< mailbox 0 arbitration lost */ + CAN_FLAG_MTFNERR2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 17U), /*!< mailbox 2 transmit finished with no error */ + CAN_FLAG_MTFNERR1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 9U), /*!< mailbox 1 transmit finished with no error */ + CAN_FLAG_MTFNERR0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 1U), /*!< mailbox 0 transmit finished with no error */ + CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ + CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ + CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ /* flags in RFIFO0 register */ - CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ - CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ + CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ + CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ /* flags in RFIFO1 register */ - CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ - CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ + CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ + CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ /* flags in ERR register */ - CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ - CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ - CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ -}can_flag_enum; + CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ + CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ + CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ +} can_flag_enum; /* CAN interrupt flags */ -typedef enum -{ +typedef enum { /* interrupt flags in STAT register */ - CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ - CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ - CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ + CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ + CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ + CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ /* interrupt flags in TSTAT register */ CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ @@ -392,42 +386,39 @@ typedef enum CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO1 not empty interrupt flag */ /* interrupt flags in ERR register */ - CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */ - CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */ - CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */ - CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */ -}can_interrupt_flag_enum; + CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */ + CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */ + CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */ + CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */ +} can_interrupt_flag_enum; /* CAN initiliaze parameters structure */ -typedef struct -{ - uint8_t working_mode; /*!< CAN working mode */ +typedef struct { + uint8_t working_mode; /*!< CAN working mode */ uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ uint8_t time_segment_1; /*!< time segment 1 */ uint8_t time_segment_2; /*!< time segment 2 */ ControlStatus time_triggered; /*!< time triggered communication mode */ ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ ControlStatus auto_wake_up; /*!< automatic wake-up mode */ - ControlStatus no_auto_retrans; /*!< automatic retransmission mode disable */ + ControlStatus auto_retrans; /*!< automatic retransmission mode */ ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ ControlStatus trans_fifo_order; /*!< transmit FIFO order */ uint16_t prescaler; /*!< baudrate prescaler */ -}can_parameter_struct; +} can_parameter_struct; /* CAN transmit message structure */ -typedef struct -{ +typedef struct { uint32_t tx_sfid; /*!< standard format frame identifier */ uint32_t tx_efid; /*!< extended format frame identifier */ uint8_t tx_ff; /*!< format of frame, standard or extended format */ uint8_t tx_ft; /*!< type of frame, data or remote */ uint8_t tx_dlen; /*!< data length */ uint8_t tx_data[8]; /*!< transmit data */ -}can_trasnmit_message_struct; +} can_trasnmit_message_struct; /* CAN receive message structure */ -typedef struct -{ +typedef struct { uint32_t rx_sfid; /*!< standard format frame identifier */ uint32_t rx_efid; /*!< extended format frame identifier */ uint8_t rx_ff; /*!< format of frame, standard or extended format */ @@ -438,9 +429,8 @@ typedef struct } can_receive_message_struct; /* CAN filter parameters structure */ -typedef struct -{ - uint16_t filter_list_high; /*!< filter list number high bits*/ +typedef struct { + uint16_t filter_list_high; /*!< filter list number high bits */ uint16_t filter_list_low; /*!< filter list number low bits */ uint16_t filter_mask_high; /*!< filter mask number high bits */ uint16_t filter_mask_low; /*!< filter mask number low bits */ @@ -449,11 +439,10 @@ typedef struct uint16_t filter_mode; /*!< filter mode, list or mask */ uint16_t filter_bits; /*!< filter scale */ ControlStatus filter_enable; /*!< filter work or not */ -}can_filter_parameter_struct; +} can_filter_parameter_struct; /* CAN errors */ -typedef enum -{ +typedef enum { CAN_ERROR_NONE = 0, /*!< no error */ CAN_ERROR_FILL, /*!< fill error */ CAN_ERROR_FORMATE, /*!< format error */ @@ -462,38 +451,36 @@ typedef enum CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ CAN_ERROR_CRC, /*!< CRC error */ CAN_ERROR_SOFTWARECFG, /*!< software configure */ -}can_error_enum; +} can_error_enum; /* transmit states */ -typedef enum -{ - CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */ - CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */ - CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */ - CAN_TRANSMIT_NOMAILBOX = 4, /*!< no empty mailbox to be used for CAN */ -}can_transmit_state_enum; - -typedef enum -{ - CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */ +typedef enum { + CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */ + CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */ + CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */ + CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */ +} can_transmit_state_enum; + +typedef enum { + CAN_INIT_STRUCT = 0, /* CAN initialize parameters struct */ CAN_FILTER_STRUCT, /* CAN filter parameters struct */ CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ -}can_struct_type_enum; +} can_struct_type_enum; -/* CAN baudrate prescaler*/ +/* CAN baudrate prescaler */ #define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) -/* CAN bit segment 1*/ +/* CAN bit segment 1 */ #define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) -/* CAN bit segment 2*/ +/* CAN bit segment 2 */ #define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) -/* CAN resynchronization jump width*/ +/* CAN resynchronization jump width */ #define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) -/* CAN communication mode*/ +/* CAN communication mode */ #define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) /* CAN FDATA high 16 bits */ @@ -502,13 +489,13 @@ typedef enum /* CAN FDATA low 16 bits */ #define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) -/* CAN1 filter start bank_number*/ +/* CAN1 filter start bank_number */ #define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) -/* CAN transmit mailbox extended identifier*/ +/* CAN transmit mailbox extended identifier */ #define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) -/* CAN transmit mailbox standard identifier*/ +/* CAN transmit mailbox standard identifier */ #define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) /* transmit data byte 0 */ @@ -520,76 +507,76 @@ typedef enum /* transmit data byte 2 */ #define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) -/* transmit data byte 3 */ +/* transmit data byte 3 */ #define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) -/* transmit data byte 4 */ +/* transmit data byte 4 */ #define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) -/* transmit data byte 5 */ +/* transmit data byte 5 */ #define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) -/* transmit data byte 6 */ +/* transmit data byte 6 */ #define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) -/* transmit data byte 7 */ +/* transmit data byte 7 */ #define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) -/* receive mailbox extended identifier*/ -#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31) +/* receive mailbox extended identifier */ +#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U) -/* receive mailbox standrad identifier*/ -#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21, 31) +/* receive mailbox standard identifier */ +#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21U, 31U) /* receive data length */ -#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0, 3) +#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0U, 3U) /* the index of the filter by which the frame is passed */ -#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8, 15) +#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8U, 15U) /* receive data byte 0 */ -#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0, 7) +#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0U, 7U) /* receive data byte 1 */ -#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8, 15) +#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8U, 15U) /* receive data byte 2 */ -#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16, 23) +#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16U, 23U) /* receive data byte 3 */ -#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24, 31) +#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24U, 31U) /* receive data byte 4 */ -#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0, 7) +#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0U, 7U) /* receive data byte 5 */ -#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8, 15) +#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8U, 15U) /* receive data byte 6 */ -#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16, 23) +#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16U, 23U) /* receive data byte 7 */ -#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24, 31) +#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24U, 31U) -/* error number */ -#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4, 6) +/* error number */ +#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4U, 6U) -/* transmit error count */ -#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16, 23) +/* transmit error count */ +#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16U, 23U) -/* receive error count */ -#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24, 31) +/* receive error count */ +#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U) /* CAN errors */ #define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) -#define CAN_ERRN_0 ERR_ERRN(0) /*!< no error */ -#define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */ -#define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */ -#define CAN_ERRN_3 ERR_ERRN(3) /*!< ACK error */ -#define CAN_ERRN_4 ERR_ERRN(4) /*!< bit recessive error */ -#define CAN_ERRN_5 ERR_ERRN(5) /*!< bit dominant error */ -#define CAN_ERRN_6 ERR_ERRN(6) /*!< CRC error */ -#define CAN_ERRN_7 ERR_ERRN(7) /*!< software error */ +#define CAN_ERRN_0 ERR_ERRN(0U) /*!< no error */ +#define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */ +#define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */ +#define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */ +#define CAN_ERRN_4 ERR_ERRN(4U) /*!< bit recessive error */ +#define CAN_ERRN_5 ERR_ERRN(5U) /*!< bit dominant error */ +#define CAN_ERRN_6 ERR_ERRN(6U) /*!< CRC error */ +#define CAN_ERRN_7 ERR_ERRN(7U) /*!< software error */ #define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ @@ -643,11 +630,11 @@ typedef enum #define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ #define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ -/* CAN receive fifo */ +/* CAN receive FIFO */ #define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ #define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ -/* frame number of receive fifo */ +/* frame number of receive FIFO */ #define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ #define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ @@ -697,11 +684,11 @@ typedef enum /* deinitialize CAN */ void can_deinit(uint32_t can_periph); /* initialize CAN structure */ -void can_struct_para_init(can_struct_type_enum type, void* p_struct); +void can_struct_para_init(can_struct_type_enum type, void *p_struct); /* initialize CAN */ -ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init); +ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init); /* CAN filter initialization */ -void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init); +void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init); /* function configuration */ /* set can1 filter start bank number */ @@ -718,14 +705,14 @@ void can_time_trigger_mode_disable(uint32_t can_periph); /* transmit functions */ /* transmit CAN message */ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message); +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message); /* get CAN transmit state */ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); /* stop CAN transmission */ void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); /* CAN receive message */ -void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message); -/* CAN release fifo */ +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message); +/* CAN release FIFO */ void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); /* CAN receive message length */ uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); @@ -734,7 +721,7 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); /* CAN wakeup from sleep mode */ ErrStatus can_wakeup(uint32_t can_periph); -/* CAN get error */ +/* CAN get error type */ can_error_enum can_error_get(uint32_t can_periph); /* get CAN receive error number */ uint8_t can_receive_error_number_get(uint32_t can_periph); @@ -742,14 +729,14 @@ uint8_t can_receive_error_number_get(uint32_t can_periph); uint8_t can_transmit_error_number_get(uint32_t can_periph); /* interrupt & flag functions */ -/* CAN interrupt enable */ -void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); -/* CAN interrupt disable */ -void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); /* CAN get flag state */ FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); /* CAN clear flag state */ void can_flag_clear(uint32_t can_periph, can_flag_enum flag); +/* CAN interrupt enable */ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); +/* CAN interrupt disable */ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); /* CAN get interrupt flag state */ FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag); /* CAN clear interrupt flag state */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_cau.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_cau.h index 35946b61..a6776afb 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_cau.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_cau.h @@ -2,36 +2,33 @@ \file gd32f20x_cau.h \brief definitions for the CAU - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -41,29 +38,29 @@ OF SUCH DAMAGE. #include "gd32f20x.h" /* CAU definitions */ -#define CAU CAU_BASE +#define CAU CAU_BASE /*!< CAU base address */ /* registers definitions */ -#define CAU_CTL REG32(CAU + 0x00U) /*!< control register */ -#define CAU_STAT0 REG32(CAU + 0x04U) /*!< status register 0 */ -#define CAU_DI REG32(CAU + 0x08U) /*!< data input register */ -#define CAU_DO REG32(CAU + 0x0CU) /*!< data output register */ -#define CAU_DMAEN REG32(CAU + 0x10U) /*!< DMA enable register */ -#define CAU_INTEN REG32(CAU + 0x14U) /*!< interrupt enable register */ -#define CAU_STAT1 REG32(CAU + 0x18U) /*!< status register 1 */ -#define CAU_INTF REG32(CAU + 0x1CU) /*!< interrupt flag register */ -#define CAU_KEY0H REG32(CAU + 0x20U) /*!< key 0 high register */ -#define CAU_KEY0L REG32(CAU + 0x24U) /*!< key 0 low register */ -#define CAU_KEY1H REG32(CAU + 0x28U) /*!< key 1 high register */ -#define CAU_KEY1L REG32(CAU + 0x2CU) /*!< key 1 low register */ -#define CAU_KEY2H REG32(CAU + 0x30U) /*!< key 2 high register */ -#define CAU_KEY2L REG32(CAU + 0x34U) /*!< key 2 low register */ -#define CAU_KEY3H REG32(CAU + 0x38U) /*!< key 3 high register */ -#define CAU_KEY3L REG32(CAU + 0x3CU) /*!< key 3 low register */ -#define CAU_IV0H REG32(CAU + 0x40U) /*!< initial vector 0 high register */ -#define CAU_IV0L REG32(CAU + 0x44U) /*!< initial vector 0 low register */ -#define CAU_IV1H REG32(CAU + 0x48U) /*!< initial vector 1 high register */ -#define CAU_IV1L REG32(CAU + 0x4CU) /*!< initial vector 1 low register */ +#define CAU_CTL REG32(CAU + 0x00000000U) /*!< control register */ +#define CAU_STAT0 REG32(CAU + 0x00000004U) /*!< status register 0 */ +#define CAU_DI REG32(CAU + 0x00000008U) /*!< data input register */ +#define CAU_DO REG32(CAU + 0x0000000CU) /*!< data output register */ +#define CAU_DMAEN REG32(CAU + 0x00000010U) /*!< DMA enable register */ +#define CAU_INTEN REG32(CAU + 0x00000014U) /*!< interrupt enable register */ +#define CAU_STAT1 REG32(CAU + 0x00000018U) /*!< status register 1 */ +#define CAU_INTF REG32(CAU + 0x0000001CU) /*!< interrupt flag register */ +#define CAU_KEY0H REG32(CAU + 0x00000020U) /*!< key 0 high register */ +#define CAU_KEY0L REG32(CAU + 0x00000024U) /*!< key 0 low register */ +#define CAU_KEY1H REG32(CAU + 0x00000028U) /*!< key 1 high register */ +#define CAU_KEY1L REG32(CAU + 0x0000002CU) /*!< key 1 low register */ +#define CAU_KEY2H REG32(CAU + 0x00000030U) /*!< key 2 high register */ +#define CAU_KEY2L REG32(CAU + 0x00000034U) /*!< key 2 low register */ +#define CAU_KEY3H REG32(CAU + 0x00000038U) /*!< key 3 high register */ +#define CAU_KEY3L REG32(CAU + 0x0000003CU) /*!< key 3 low register */ +#define CAU_IV0H REG32(CAU + 0x00000040U) /*!< initial vector 0 high register */ +#define CAU_IV0L REG32(CAU + 0x00000044U) /*!< initial vector 0 low register */ +#define CAU_IV1H REG32(CAU + 0x00000048U) /*!< initial vector 1 high register */ +#define CAU_IV1L REG32(CAU + 0x0000004CU) /*!< initial vector 1 low register */ /* bits definitions */ /* CAU_CTL */ @@ -117,8 +114,7 @@ OF SUCH DAMAGE. /* constants definitions */ /* structure for keys initialization of the cau */ -typedef struct -{ +typedef struct { uint32_t key_0_high; /*!< key 0 high */ uint32_t key_0_low; /*!< key 0 low */ uint32_t key_1_high; /*!< key 1 high */ @@ -127,28 +123,26 @@ typedef struct uint32_t key_2_low; /*!< key 2 low */ uint32_t key_3_high; /*!< key 3 high */ uint32_t key_3_low; /*!< key 3 low */ -}cau_key_parameter_struct; +} cau_key_parameter_struct; /* structure for vectors initialization of the cau */ -typedef struct -{ +typedef struct { uint32_t iv_0_high; /*!< init vector 0 high */ uint32_t iv_0_low; /*!< init vector 0 low */ uint32_t iv_1_high; /*!< init vector 1 high */ uint32_t iv_1_low; /*!< init vector 1 low */ -}cau_iv_parameter_struct; +} cau_iv_parameter_struct; /* structure for vectors initialization of the cau */ -typedef struct -{ +typedef struct { uint8_t *input; /*!< pointer to the input buffer */ - uint32_t in_length; /*!< length of the input buffer, + uint32_t in_length; /*!< length of the input buffer, must be a multiple of 8(DES and TDES) or 16(AES) */ uint8_t *output; /*!< pointer to the returned buffer */ -}cau_text_struct; +} cau_text_struct; /* cau_ctl register value */ -#define CAU_ENCRYPT ((uint32_t)0x00000000) /*!< encrypt */ +#define CAU_ENCRYPT ((uint32_t)0x00000000U) /*!< encrypt */ #define CAU_DECRYPT CAU_CTL_CAUDIR /*!< decrypt */ #define CTL_ALGM(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) /*!< write value to CAU_CTL_ALGM bit field */ @@ -172,7 +166,7 @@ typedef struct #define CAU_KEYSIZE_192BIT CTL_KEYM(1) /*!< 192 bit key length */ #define CAU_KEYSIZE_256BIT CTL_KEYM(2) /*!< 256 bit key length */ -/* cau_stat0 register value */ +/* cau_stat0 register value */ #define CAU_FLAG_INFIFO_EMPTY CAU_STAT0_IEM /*!< IN FIFO empty */ #define CAU_FLAG_INFIFO_NO_FULL CAU_STAT0_INF /*!< IN FIFO is not full */ #define CAU_FLAG_OUTFIFO_NO_EMPTY CAU_STAT0_ONE /*!< OUT FIFO not empty */ @@ -212,13 +206,13 @@ void cau_init(uint32_t algo_dir, uint32_t algo_mode, uint32_t swapping); /* configure key size if used AES algorithm */ void cau_aes_keysize_config(uint32_t key_size); /* initialize the key parameters */ -void cau_key_init(cau_key_parameter_struct* key_initpara); +void cau_key_init(cau_key_parameter_struct *key_initpara); /* initialize the structure cau_key_initpara */ -void cau_key_parameter_init(cau_key_parameter_struct* key_initpara); +void cau_key_parameter_init(cau_key_parameter_struct *key_initpara); /* initialize the vectors parameters */ -void cau_iv_init(cau_iv_parameter_struct* iv_initpara); +void cau_iv_init(cau_iv_parameter_struct *iv_initpara); /* initialize the vectors parameters */ -void cau_iv_parameter_init(cau_iv_parameter_struct* iv_initpara); +void cau_iv_parameter_init(cau_iv_parameter_struct *iv_initpara); /* flush the IN and OUT FIFOs */ void cau_fifo_flush(void); /* return whether CAU peripheral is enabled or disabled */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_crc.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_crc.h index 4980cd33..721c2306 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_crc.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_crc.h @@ -2,36 +2,33 @@ \file gd32f20x_crc.h \brief definitions for the CRC - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -41,12 +38,12 @@ OF SUCH DAMAGE. #include "gd32f20x.h" /* CRC definitions */ -#define CRC CRC_BASE +#define CRC CRC_BASE /*!< CRC base address */ /* registers definitions */ -#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */ -#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */ -#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */ +#define CRC_DATA REG32(CRC + 0x00000000U) /*!< CRC data register */ +#define CRC_FDATA REG32(CRC + 0x00000004U) /*!< CRC free data register */ +#define CRC_CTL REG32(CRC + 0x00000008U) /*!< CRC control register */ /* bits definitions */ /* CRC_DATA */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_dac.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_dac.h index 0ef9fbfb..c4dd08a6 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_dac.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_dac.h @@ -2,36 +2,33 @@ \file gd32f20x_dac.h \brief definitions for the DAC - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -46,76 +43,76 @@ OF SUCH DAMAGE. #define DAC1 1U /* registers definitions */ -#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ -#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ -#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ -#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ -#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ -#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ -#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ -#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ -#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ -#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ -#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ -#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ -#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ +#define DAC_CTL REG32(DAC + 0x00000000U) /*!< DAC control register */ +#define DAC_SWT REG32(DAC + 0x00000004U) /*!< DAC software trigger register */ +#define DAC0_R12DH REG32(DAC + 0x00000008U) /*!< DAC0 12-bit right-aligned data holding register */ +#define DAC0_L12DH REG32(DAC + 0x0000000CU) /*!< DAC0 12-bit left-aligned data holding register */ +#define DAC0_R8DH REG32(DAC + 0x00000010U) /*!< DAC0 8-bit right-aligned data holding register */ +#define DAC1_R12DH REG32(DAC + 0x00000014U) /*!< DAC1 12-bit right-aligned data holding register */ +#define DAC1_L12DH REG32(DAC + 0x00000018U) /*!< DAC1 12-bit left-aligned data holding register */ +#define DAC1_R8DH REG32(DAC + 0x0000001CU) /*!< DAC1 8-bit right-aligned data holding register */ +#define DACC_R12DH REG32(DAC + 0x00000020U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ +#define DACC_L12DH REG32(DAC + 0x00000024U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ +#define DACC_R8DH REG32(DAC + 0x00000028U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ +#define DAC0_DO REG32(DAC + 0x0000002CU) /*!< DAC0 data output register */ +#define DAC1_DO REG32(DAC + 0x00000030U) /*!< DAC1 data output register */ /* bits definitions */ /* DAC_CTL */ -#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ -#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/off bit */ -#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ -#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ -#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ -#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ -#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ -#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ -#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ -#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ -#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ -#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ +#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ +#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/off bit */ +#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ +#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ +#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ +#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ +#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ +#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ +#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ +#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ +#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ /* DAC_SWT */ -#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ -#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ +#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ +#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ /* DAC0_R12DH */ -#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ +#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ /* DAC0_L12DH */ -#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ +#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ /* DAC0_R8DH */ -#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ +#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ /* DAC1_R12DH */ -#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ +#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ /* DAC1_L12DH */ -#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ +#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ /* DAC1_R8DH */ -#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ +#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ /* DACC_R12DH */ -#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ -#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ +#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ +#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ /* DACC_L12DH */ -#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ -#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ +#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ +#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ /* DACC_R8DH */ -#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ -#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ +#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ +#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ /* DAC0_DO */ -#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ +#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ /* DAC1_DO */ -#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ +#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ /* constants definitions */ /* DAC trigger source */ @@ -195,12 +192,12 @@ void dac_disable(uint32_t dac_periph); /* enable DAC DMA */ void dac_dma_enable(uint32_t dac_periph); /* disable DAC DMA */ -void dac_dma_disable(uint32_t dac_periph); +void dac_dma_disable(uint32_t dac_periph); /* enable DAC output buffer */ void dac_output_buffer_enable(uint32_t dac_periph); /* disable DAC output buffer */ void dac_output_buffer_disable(uint32_t dac_periph); -/* get the last data output value */ +/* get DAC output value */ uint16_t dac_output_value_get(uint32_t dac_periph); /* set DAC data holding register value */ void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); @@ -242,6 +239,6 @@ void dac_concurrent_output_buffer_enable(void); /* disable DAC concurrent buffer function */ void dac_concurrent_output_buffer_disable(void); /* set DAC concurrent mode data holding register value */ -void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); #endif /* GD32F20X_DAC_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_dbg.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_dbg.h index 0029be42..93adde35 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_dbg.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_dbg.h @@ -2,37 +2,33 @@ \file gd32f20x_dbg.h \brief definitions for the DBG - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x - \version 2020-12-14, V2.2.1, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -42,15 +38,15 @@ OF SUCH DAMAGE. #include "gd32f20x.h" /* DBG definitions */ -#define DBG DBG_BASE +#define DBG DBG_BASE /* registers definitions */ -#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ -#define DBG_CTL REG32(DBG + 0x04U) /*!< DBG control register */ +#define DBG_ID REG32(DBG + 0x00000000U) /*!< DBG_ID code register */ +#define DBG_CTL REG32(DBG + 0x00000004U) /*!< DBG control register */ /* bits definitions */ /* DBG_ID */ -#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ +#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ /* DBG_CTL */ #define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ @@ -78,32 +74,33 @@ OF SUCH DAMAGE. #define DBG_CTL_TIMER8_HOLD BIT(28) /*!< hold TIMER8 counter when core is halted */ #define DBG_CTL_TIMER9_HOLD BIT(29) /*!< hold TIMER9 counter when core is halted */ #define DBG_CTL_TIMER10_HOLD BIT(30) /*!< hold TIMER10 counter when core is halted */ +#define DBG_CTL_I2C2_HOLD BIT(31) /*!< hold I2C2 smbus when core is halted */ /* constants definitions */ /* debug hold when core is halted */ -typedef enum -{ - DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */ - DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */ - DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */ - DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */ - DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */ - DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */ - DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */ - DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */ - DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */ - DBG_TIMER7_HOLD = BIT(17), /*!< hold TIMER7 counter when core is halted */ - DBG_TIMER4_HOLD = BIT(18), /*!< hold TIMER4 counter when core is halted */ - DBG_TIMER5_HOLD = BIT(19), /*!< hold TIMER5 counter when core is halted */ - DBG_TIMER6_HOLD = BIT(20), /*!< hold TIMER6 counter when core is halted */ - DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */ - DBG_TIMER11_HOLD = BIT(25), /*!< hold TIMER11 counter when core is halted */ - DBG_TIMER12_HOLD = BIT(26), /*!< hold TIMER12 counter when core is halted */ - DBG_TIMER13_HOLD = BIT(27), /*!< hold TIMER13 counter when core is halted */ - DBG_TIMER8_HOLD = BIT(28), /*!< hold TIMER8 counter when core is halted */ - DBG_TIMER9_HOLD = BIT(29), /*!< hold TIMER9 counter when core is halted */ - DBG_TIMER10_HOLD = BIT(30), /*!< hold TIMER10 counter when core is halted */ -}dbg_periph_enum; +typedef enum { + DBG_FWDGT_HOLD = (int)BIT(8), /*!< debug FWDGT kept when core is halted */ + DBG_WWDGT_HOLD = (int)BIT(9), /*!< debug WWDGT kept when core is halted */ + DBG_TIMER0_HOLD = (int)BIT(10), /*!< hold TIMER0 counter when core is halted */ + DBG_TIMER1_HOLD = (int)BIT(11), /*!< hold TIMER1 counter when core is halted */ + DBG_TIMER2_HOLD = (int)BIT(12), /*!< hold TIMER2 counter when core is halted */ + DBG_TIMER3_HOLD = (int)BIT(13), /*!< hold TIMER3 counter when core is halted */ + DBG_CAN0_HOLD = (int)BIT(14), /*!< debug CAN0 kept when core is halted */ + DBG_I2C0_HOLD = (int)BIT(15), /*!< hold I2C0 smbus when core is halted */ + DBG_I2C1_HOLD = (int)BIT(16), /*!< hold I2C1 smbus when core is halted */ + DBG_TIMER7_HOLD = (int)BIT(17), /*!< hold TIMER7 counter when core is halted */ + DBG_TIMER4_HOLD = (int)BIT(18), /*!< hold TIMER4 counter when core is halted */ + DBG_TIMER5_HOLD = (int)BIT(19), /*!< hold TIMER5 counter when core is halted */ + DBG_TIMER6_HOLD = (int)BIT(20), /*!< hold TIMER6 counter when core is halted */ + DBG_CAN1_HOLD = (int)BIT(21), /*!< debug CAN1 kept when core is halted */ + DBG_TIMER11_HOLD = (int)BIT(25), /*!< hold TIMER11 counter when core is halted */ + DBG_TIMER12_HOLD = (int)BIT(26), /*!< hold TIMER12 counter when core is halted */ + DBG_TIMER13_HOLD = (int)BIT(27), /*!< hold TIMER13 counter when core is halted */ + DBG_TIMER8_HOLD = (int)BIT(28), /*!< hold TIMER8 counter when core is halted */ + DBG_TIMER9_HOLD = (int)BIT(29), /*!< hold TIMER9 counter when core is halted */ + DBG_TIMER10_HOLD = (int)BIT(30), /*!< hold TIMER10 counter when core is halted */ + DBG_I2C2_HOLD = (int)BIT(31), /*!< hold I2C2 smbus when core is halted */ +} dbg_periph_enum; /* DBG low power mode configurations */ #define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */ @@ -111,7 +108,7 @@ typedef enum #define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */ /* DBG_CTL0_TRACE_MODE configurations */ -#define CTL_TRACE_MODE(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U)) +#define CTL_TRACE_MODE(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U)) #define TRACE_MODE_ASYNC CTL_TRACE_MODE(0) /*!< trace pin used for async mode */ #define TRACE_MODE_SYNC_DATASIZE_1 CTL_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */ #define TRACE_MODE_SYNC_DATASIZE_2 CTL_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */ @@ -119,7 +116,7 @@ typedef enum /* function declarations */ /* initialization functions */ -/* read DBG_ID code register */ +/* read DBG_ID register */ uint32_t dbg_id_get(void); /* function configuration */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_dci.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_dci.h index 1e779a2e..8b9d8181 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_dci.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_dci.h @@ -2,36 +2,33 @@ \file gd32f20x_dci.h \brief definitions for the DCI - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -125,15 +122,14 @@ OF SUCH DAMAGE. /* constants definitions */ /* DCI parameter structure definitions */ -typedef struct -{ +typedef struct { uint32_t capture_mode; /*!< DCI capture mode: continuous or snapshot */ uint32_t clock_polarity; /*!< clock polarity selection */ uint32_t hsync_polarity; /*!< horizontal polarity selection */ uint32_t vsync_polarity; /*!< vertical polarity selection */ uint32_t frame_rate; /*!< frame capture rate */ uint32_t interface_format; /*!< digital camera interface format */ -}dci_parameter_struct; +} dci_parameter_struct; #define DCI_CAPTURE_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< continuous capture mode */ #define DCI_CAPTURE_MODE_SNAPSHOT DCI_CTL_SNAP /*!< snapshot capture mode */ @@ -146,13 +142,13 @@ typedef struct #define DCI_VSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */ #define DCI_VSYNC_POLARITY_HIGH DCI_CTL_VPS /*!< high level during blanking period*/ - -#define CTL_FR(regval) (BITS(8,9)&((uint32_t)(regval) << 8U)) + +#define CTL_FR(regval) (BITS(8,9)&((uint32_t)(regval) << 8U)) #define DCI_FRAME_RATE_ALL CTL_FR(0) /*!< capture all frames */ #define DCI_FRAME_RATE_1_2 CTL_FR(1) /*!< capture one in 2 frames */ #define DCI_FRAME_RATE_1_4 CTL_FR(2) /*!< capture one in 4 frames */ -#define CTL_DCIF(regval) (BITS(10,11)&((uint32_t)(regval) << 10U)) +#define CTL_DCIF(regval) (BITS(10,11)&((uint32_t)(regval) << 10U)) #define DCI_INTERFACE_FORMAT_8BITS CTL_DCIF(0) /*!< 8-bit data on every pixel clock */ #define DCI_INTERFACE_FORMAT_10BITS CTL_DCIF(1) /*!< 10-bit data on every pixel clock */ #define DCI_INTERFACE_FORMAT_12BITS CTL_DCIF(2) /*!< 12-bit data on every pixel clock */ @@ -172,7 +168,7 @@ typedef struct #define DCI_INT_FLAG_VSYNC BIT(3) /*!< vsync interrupt flag */ #define DCI_INT_FLAG_EL BIT(4) /*!< end of line interrupt flag */ -/* DCI flag definitions */ +/* DCI flag definitions */ #define DCI_FLAG_HS DCI_STAT0_HS /*!< HS line status */ #define DCI_FLAG_VS DCI_STAT0_VS /*!< VS line status */ #define DCI_FLAG_FV DCI_STAT0_FV /*!< FIFO valid */ @@ -187,7 +183,7 @@ typedef struct /* DCI deinit */ void dci_deinit(void); /* initialize DCI registers */ -void dci_init(dci_parameter_struct* dci_struct); +void dci_init(dci_parameter_struct *dci_struct); /* enable DCI function */ void dci_enable(void); diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_dma.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_dma.h index aefef267..c1ffc259 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_dma.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_dma.h @@ -2,36 +2,33 @@ \file gd32f20x_dma.h \brief definitions for the DMA - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -41,118 +38,115 @@ OF SUCH DAMAGE. #include "gd32f20x.h" /* DMA definitions */ -#define DMA0 (DMA_BASE) /*!< DMA0 base address */ -#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */ +#define DMA0 (DMA_BASE) /*!< DMA0 base address */ +#define DMA1 (DMA_BASE + 0x00000400U) /*!< DMA1 base address */ /* registers definitions */ -#define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */ -#define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */ - -#define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */ -#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */ -#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */ -#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */ - -#define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */ -#define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */ -#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */ -#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */ - -#define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */ -#define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */ -#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */ -#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */ - -#define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */ -#define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */ -#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */ -#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */ - -#define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */ -#define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */ -#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */ -#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */ - -#define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */ -#define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */ -#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */ -#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */ - -#define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */ -#define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */ -#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */ -#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */ - -#define DMA_ACFG REG32((DMA1) + 0x300U) /*!< DMA additional configuration register */ +#define DMA_INTF(dmax) REG32((dmax) + 0x00000000U) /*!< DMA interrupt flag register */ +#define DMA_INTC(dmax) REG32((dmax) + 0x00000004U) /*!< DMA interrupt flag clear register */ + +#define DMA_CH0CTL(dmax) REG32((dmax) + 0x00000008U) /*!< DMA channel 0 control register */ +#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0000000CU) /*!< DMA channel 0 counter register */ +#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x00000010U) /*!< DMA channel 0 peripheral base address register */ +#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x00000014U) /*!< DMA channel 0 memory base address register */ + +#define DMA_CH1CTL(dmax) REG32((dmax) + 0x0000001CU) /*!< DMA channel 1 control register */ +#define DMA_CH1CNT(dmax) REG32((dmax) + 0x00000020U) /*!< DMA channel 1 counter register */ +#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x00000024U) /*!< DMA channel 1 peripheral base address register */ +#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x00000028U) /*!< DMA channel 1 memory base address register */ + +#define DMA_CH2CTL(dmax) REG32((dmax) + 0x00000030U) /*!< DMA channel 2 control register */ +#define DMA_CH2CNT(dmax) REG32((dmax) + 0x00000034U) /*!< DMA channel 2 counter register */ +#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x00000038U) /*!< DMA channel 2 peripheral base address register */ +#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x0000003CU) /*!< DMA channel 2 memory base address register */ + +#define DMA_CH3CTL(dmax) REG32((dmax) + 0x00000044U) /*!< DMA channel 3 control register */ +#define DMA_CH3CNT(dmax) REG32((dmax) + 0x00000048U) /*!< DMA channel 3 counter register */ +#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x0000004CU) /*!< DMA channel 3 peripheral base address register */ +#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x00000050U) /*!< DMA channel 3 memory base address register */ + +#define DMA_CH4CTL(dmax) REG32((dmax) + 0x00000058U) /*!< DMA channel 4 control register */ +#define DMA_CH4CNT(dmax) REG32((dmax) + 0x0000005CU) /*!< DMA channel 4 counter register */ +#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x00000060U) /*!< DMA channel 4 peripheral base address register */ +#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x00000064U) /*!< DMA channel 4 memory base address register */ + +#define DMA_CH5CTL(dmax) REG32((dmax) + 0x0000006CU) /*!< DMA channel 5 control register */ +#define DMA_CH5CNT(dmax) REG32((dmax) + 0x00000070U) /*!< DMA channel 5 counter register */ +#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x00000074U) /*!< DMA channel 5 peripheral base address register */ +#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x00000078U) /*!< DMA channel 5 memory base address register */ + +#define DMA_CH6CTL(dmax) REG32((dmax) + 0x00000080U) /*!< DMA channel 6 control register */ +#define DMA_CH6CNT(dmax) REG32((dmax) + 0x00000084U) /*!< DMA channel 6 counter register */ +#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x00000088U) /*!< DMA channel 6 peripheral base address register */ +#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x0000008CU) /*!< DMA channel 6 memory base address register */ + +#define DMA_ACFG REG32((DMA1) + 0x00000300U) /*!< DMA additional configuration register */ /* bits definitions */ /* DMA_INTF */ -#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ -#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ -#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ -#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ +#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ +#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ +#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ +#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ /* DMA_INTC */ -#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ -#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ -#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ -#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ +#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ +#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ +#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ +#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ /* DMA_CHxCTL, x=0..6 */ -#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */ -#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */ -#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */ -#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */ -#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */ -#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ -#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ -#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ -#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ -#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ -#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ -#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ +#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */ +#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */ +#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */ +#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */ +#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */ +#define DMA_CHXCTL_CMEN BIT(5) /*!< enable circular mode */ +#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ +#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ +#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ +#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ +#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ +#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ /* DMA_CHxCNT, x=0..6 */ -#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ +#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ /* DMA_CHxPADDR, x=0..6 */ -#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ +#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ /* DMA_CHxMADDR, x=0..6 */ -#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ +#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ /* DMA_ACFG */ -#define DMA_ACFG_FD_CH5EN BIT(5) /*!< enable bit for DMA1 channel 5 Full_Data transfer mode */ +#define DMA_ACFG_FD_CH5EN BIT(5) /*!< enable bit for DMA1 channel 5 Full_Data transfer mode */ /* constants definitions */ -/* DMA channel select */ -typedef enum -{ - DMA_CH0 = 0, /*!< DMA channel 0 */ - DMA_CH1, /*!< DMA channel 1 */ - DMA_CH2, /*!< DMA channel 2 */ - DMA_CH3, /*!< DMA channel 3 */ - DMA_CH4, /*!< DMA channel 4 */ - DMA_CH5, /*!< DMA channel 5 */ - DMA_CH6 /*!< DMA channel 6 */ +/* DMA channel selection */ +typedef enum { + DMA_CH0 = 0, /*!< DMA channel 0 */ + DMA_CH1, /*!< DMA channel 1 */ + DMA_CH2, /*!< DMA channel 2 */ + DMA_CH3, /*!< DMA channel 3 */ + DMA_CH4, /*!< DMA channel 4 */ + DMA_CH5, /*!< DMA channel 5 */ + DMA_CH6 /*!< DMA channel 6 */ } dma_channel_enum; -/* DMA initialize struct */ -typedef struct -{ - uint32_t periph_addr; /*!< peripheral base address */ - uint32_t periph_width; /*!< transfer data size of peripheral */ - uint32_t memory_addr; /*!< memory base address */ - uint32_t memory_width; /*!< transfer data size of memory */ - uint32_t number; /*!< channel transfer number */ - uint32_t priority; /*!< channel priority level */ - uint8_t periph_inc; /*!< peripheral increasing mode */ - uint8_t memory_inc; /*!< memory increasing mode */ - uint8_t direction; /*!< channel data transfer direction */ - +/* DMA initialize structure */ +typedef struct { + uint32_t periph_addr; /*!< peripheral base address */ + uint32_t periph_width; /*!< transfer data size of peripheral */ + uint32_t memory_addr; /*!< memory base address */ + uint32_t memory_width; /*!< transfer data size of memory */ + uint32_t number; /*!< channel transfer number */ + uint32_t priority; /*!< channel priority level */ + uint8_t periph_inc; /*!< peripheral increasing mode */ + uint8_t memory_inc; /*!< memory increasing mode */ + uint8_t direction; /*!< channel data transfer direction */ } dma_parameter_struct; -#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */ +#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */ /* DMA_register address */ #define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ @@ -233,10 +227,10 @@ typedef struct /* function declarations */ /* initialization functions */ -/* deinitialize DMA a channel registers */ +/* deinitialize a DMA channel registers */ void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); /* initialize the parameters of DMA structure with the default values */ -void dma_struct_para_init(dma_parameter_struct* init_struct); +void dma_struct_para_init(dma_parameter_struct *init_struct); /* initialize DMA channel */ void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct); /* enable DMA circulation mode */ @@ -278,23 +272,23 @@ void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) /* configure the direction of data transfer on the channel */ void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction); +/* enable the DMA1 channel 5 Full_Data transfer mode */ +void dma_1_channel_5_fulldata_transfer_enable(void); +/* disable the DMA1 channel 5 Full_Data transfer mode */ +void dma_1_channel_5_fulldata_transfer_disable(void); + /* flag and interrupt functions */ /* check DMA flag is set or not */ FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); /* clear the flag of a DMA channel */ void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* check DMA flag and interrupt enable bit is set or not */ -FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* clear the interrupt flag of a DMA channel */ -void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); /* enable DMA interrupt */ void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); /* disable DMA interrupt */ void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); - -/* enable the DMA1 channel 5 Full_Data transfer mode */ -void dma_1_channel_5_fulldata_transfer_enable(void); -/* disable the DMA1 channel 5 Full_Data transfer mode */ -void dma_1_channel_5_fulldata_transfer_disable(void); +/* check DMA flag and interrupt enable bit is set or not */ +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* clear the interrupt flag of a DMA channel */ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); #endif /* GD32F20X_DMA_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_enet.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_enet.h index 689448a1..822ef36e 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_enet.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_enet.h @@ -2,36 +2,33 @@ \file gd32f20x_enet.h \brief definitions for the ENET - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -41,17 +38,17 @@ OF SUCH DAMAGE. #include "gd32f20x.h" #include -#define IF_USE_EXTERNPHY_LIB 0 +#define IF_USE_EXTERNPHY_LIB 0U #if (1 == IF_USE_EXTERNPHY_LIB) #include "phy.h" #endif #ifndef ENET_RXBUF_NUM -#define ENET_RXBUF_NUM 2U /*!< ethernet Rx DMA descriptor number */ +#define ENET_RXBUF_NUM 5U /*!< ethernet Rx DMA descriptor number */ #endif #ifndef ENET_TXBUF_NUM -#define ENET_TXBUF_NUM 1U /*!< ethernet Tx DMA descriptor number */ +#define ENET_TXBUF_NUM 5U /*!< ethernet Tx DMA descriptor number */ #endif #ifndef ENET_RXBUF_SIZE @@ -74,7 +71,7 @@ OF SUCH DAMAGE. #define PHY_ADDRESS ((uint16_t)1U) /*!< phy address determined by the hardware */ -/* PHY read write timeouts */ +/* PHY read write timeouts */ #define PHY_READ_TO ((uint32_t)0x0004FFFFU) /*!< PHY read timeout */ #define PHY_WRITE_TO ((uint32_t)0x0004FFFFU) /*!< PHY write timeout */ @@ -82,35 +79,35 @@ OF SUCH DAMAGE. #define PHY_RESETDELAY ((uint32_t)0x008FFFFFU) /*!< PHY reset delay */ #define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU) /*!< PHY configure delay */ -/* PHY register address */ +/* PHY register address */ #define PHY_REG_BCR 0U /*!< tranceiver basic control register */ #define PHY_REG_BSR 1U /*!< tranceiver basic status register */ /* PHY basic control register */ -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< enable phy loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< configure speed to 100 Mbit/s and the full-duplex mode */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< configure speed to 100 Mbit/s and the half-duplex mode */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< configure speed to 10 Mbit/s and the full-duplex mode */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< configure speed to 10 Mbit/s and the half-duplex mode */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< enable the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< isolate PHY from MII */ +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< enable phy loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< configure speed to 100 Mbit/s and the full-duplex mode */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< configure speed to 100 Mbit/s and the half-duplex mode */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< configure speed to 10 Mbit/s and the full-duplex mode */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< configure speed to 10 Mbit/s and the half-duplex mode */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< enable the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< isolate PHY from MII */ /* PHY basic status register */ -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< auto-negotioation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< jabber condition detected */ +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< auto-negotioation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< jabber condition detected */ -#if(PHY_TYPE == LAN8700) +#if(PHY_TYPE == LAN8700) #define PHY_SR 31U /*!< tranceiver status register */ -#define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< configured information of speed: 10Mbit/s */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< configured information of duplex: full-duplex */ +#define PHY_SPEED_STATUS ((uint16_t)0x0004U) /*!< configured information of speed: 10Mbit/s */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0010U) /*!< configured information of duplex: full-duplex */ #elif(PHY_TYPE == DP83848) #define PHY_SR 16U /*!< tranceiver status register */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< configured information of speed: 10Mbit/s */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< configured information of duplex: full-duplex */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< configured information of speed: 10Mbit/s */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< configured information of duplex: full-duplex */ #elif(PHY_TYPE == RTL8201F) /** AvV **/ # define PHY_SR 0U /*!< tranceiver status register */ # define PHY_SPEED_STATUS ((uint16_t)0x2000) /*!< configured information of speed: 100Mbit/s */ @@ -124,63 +121,63 @@ OF SUCH DAMAGE. #define ENET ENET_BASE /* registers definitions */ -#define ENET_MAC_CFG REG32((ENET) + 0x00U) /*!< ethernet MAC configuration register */ -#define ENET_MAC_FRMF REG32((ENET) + 0x04U) /*!< ethernet MAC frame filter register */ -#define ENET_MAC_HLH REG32((ENET) + 0x08U) /*!< ethernet MAC hash list high register */ -#define ENET_MAC_HLL REG32((ENET) + 0x0CU) /*!< ethernet MAC hash list low register */ -#define ENET_MAC_PHY_CTL REG32((ENET) + 0x10U) /*!< ethernet MAC PHY control register */ -#define ENET_MAC_PHY_DATA REG32((ENET) + 0x14U) /*!< ethernet MAC MII data register */ -#define ENET_MAC_FCTL REG32((ENET) + 0x18U) /*!< ethernet MAC flow control register */ -#define ENET_MAC_FCTH REG32((ENET) + 0x1080U) /*!< ethernet MAC flow control threshold register */ -#define ENET_MAC_VLT REG32((ENET) + 0x1CU) /*!< ethernet MAC VLAN tag register */ -#define ENET_MAC_RWFF REG32((ENET) + 0x28U) /*!< ethernet MAC remote wakeup frame filter register */ -#define ENET_MAC_WUM REG32((ENET) + 0x2CU) /*!< ethernet MAC wakeup management register */ -#define ENET_MAC_INTF REG32((ENET) + 0x38U) /*!< ethernet MAC interrupt flag register */ -#define ENET_MAC_INTMSK REG32((ENET) + 0x3CU) /*!< ethernet MAC interrupt mask register */ -#define ENET_MAC_ADDR0H REG32((ENET) + 0x40U) /*!< ethernet MAC address 0 high register */ -#define ENET_MAC_ADDR0L REG32((ENET) + 0x44U) /*!< ethernet MAC address 0 low register */ -#define ENET_MAC_ADDR1H REG32((ENET) + 0x48U) /*!< ethernet MAC address 1 high register */ -#define ENET_MAC_ADDR1L REG32((ENET) + 0x4CU) /*!< ethernet MAC address 1 low register */ -#define ENET_MAC_ADDT2H REG32((ENET) + 0x50U) /*!< ethernet MAC address 2 high register */ -#define ENET_MAC_ADDR2L REG32((ENET) + 0x54U) /*!< ethernet MAC address 2 low register */ -#define ENET_MAC_ADDR3H REG32((ENET) + 0x58U) /*!< ethernet MAC address 3 high register */ -#define ENET_MAC_ADDR3L REG32((ENET) + 0x5CU) /*!< ethernet MAC address 3 low register */ - -#define ENET_MSC_CTL REG32((ENET) + 0x100U) /*!< ethernet MSC control register */ -#define ENET_MSC_RINTF REG32((ENET) + 0x104U) /*!< ethernet MSC receive interrupt flag register */ -#define ENET_MSC_TINTF REG32((ENET) + 0x108U) /*!< ethernet MSC transmit interrupt flag register */ -#define ENET_MSC_RINTMSK REG32((ENET) + 0x10CU) /*!< ethernet MSC receive interrupt mask register */ -#define ENET_MSC_TINTMSK REG32((ENET) + 0x110U) /*!< ethernet MSC transmit interrupt mask register */ -#define ENET_MSC_SCCNT REG32((ENET) + 0x14CU) /*!< ethernet MSC transmitted good frames after a single collision counter register */ -#define ENET_MSC_MSCCNT REG32((ENET) + 0x150U) /*!< ethernet MSC transmitted good frames after more than a single collision counter register */ -#define ENET_MSC_TGFCNT REG32((ENET) + 0x168U) /*!< ethernet MSC transmitted good frames counter register */ -#define ENET_MSC_RFCECNT REG32((ENET) + 0x194U) /*!< ethernet MSC received frames with CRC error counter register */ -#define ENET_MSC_RFAECNT REG32((ENET) + 0x198U) /*!< ethernet MSC received frames with alignment error counter register */ -#define ENET_MSC_RGUFCNT REG32((ENET) + 0x1C4U) /*!< ethernet MSC received good unicast frames counter register */ - -#define ENET_PTP_TSCTL REG32((ENET) + 0x700U) /*!< ethernet PTP time stamp control register */ -#define ENET_PTP_SSINC REG32((ENET) + 0x704U) /*!< ethernet PTP subsecond increment register */ -#define ENET_PTP_TSH REG32((ENET) + 0x708U) /*!< ethernet PTP time stamp high register */ -#define ENET_PTP_TSL REG32((ENET) + 0x70CU) /*!< ethernet PTP time stamp low register */ -#define ENET_PTP_TSUH REG32((ENET) + 0x710U) /*!< ethernet PTP time stamp update high register */ -#define ENET_PTP_TSUL REG32((ENET) + 0x714U) /*!< ethernet PTP time stamp update low register */ -#define ENET_PTP_TSADDEND REG32((ENET) + 0x718U) /*!< ethernet PTP time stamp addend register */ -#define ENET_PTP_ETH REG32((ENET) + 0x71CU) /*!< ethernet PTP expected time high register */ -#define ENET_PTP_ETL REG32((ENET) + 0x720U) /*!< ethernet PTP expected time low register */ - -#define ENET_DMA_BCTL REG32((ENET) + 0x1000U) /*!< ethernet DMA bus control register */ -#define ENET_DMA_TPEN REG32((ENET) + 0x1004U) /*!< ethernet DMA transmit poll enable register */ -#define ENET_DMA_RPEN REG32((ENET) + 0x1008U) /*!< ethernet DMA receive poll enable register */ -#define ENET_DMA_RDTADDR REG32((ENET) + 0x100CU) /*!< ethernet DMA receive descriptor table address register */ -#define ENET_DMA_TDTADDR REG32((ENET) + 0x1010U) /*!< ethernet DMA transmit descriptor table address register */ -#define ENET_DMA_STAT REG32((ENET) + 0x1014U) /*!< ethernet DMA status register */ -#define ENET_DMA_CTL REG32((ENET) + 0x1018U) /*!< ethernet DMA control register */ -#define ENET_DMA_INTEN REG32((ENET) + 0x101CU) /*!< ethernet DMA interrupt enable register */ -#define ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U) /*!< ethernet DMA missed frame and buffer overflow counter register */ -#define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U) /*!< ethernet DMA current transmit descriptor address register */ -#define ENET_DMA_CRDADDR REG32((ENET) + 0x104CU) /*!< ethernet DMA current receive descriptor address register */ -#define ENET_DMA_CTBADDR REG32((ENET) + 0x1050U) /*!< ethernet DMA current transmit buffer address register */ -#define ENET_DMA_CRBADDR REG32((ENET) + 0x1054U) /*!< ethernet DMA current receive buffer address register */ +#define ENET_MAC_CFG REG32((ENET) + 0x00000000U) /*!< ethernet MAC configuration register */ +#define ENET_MAC_FRMF REG32((ENET) + 0x00000004U) /*!< ethernet MAC frame filter register */ +#define ENET_MAC_HLH REG32((ENET) + 0x00000008U) /*!< ethernet MAC hash list high register */ +#define ENET_MAC_HLL REG32((ENET) + 0x0000000CU) /*!< ethernet MAC hash list low register */ +#define ENET_MAC_PHY_CTL REG32((ENET) + 0x00000010U) /*!< ethernet MAC PHY control register */ +#define ENET_MAC_PHY_DATA REG32((ENET) + 0x00000014U) /*!< ethernet MAC PHY data register */ +#define ENET_MAC_FCTL REG32((ENET) + 0x00000018U) /*!< ethernet MAC flow control register */ +#define ENET_MAC_FCTH REG32((ENET) + 0x00001080U) /*!< ethernet MAC flow control threshold register */ +#define ENET_MAC_VLT REG32((ENET) + 0x0000001CU) /*!< ethernet MAC VLAN tag register */ +#define ENET_MAC_RWFF REG32((ENET) + 0x00000028U) /*!< ethernet MAC remote wakeup frame filter register */ +#define ENET_MAC_WUM REG32((ENET) + 0x0000002CU) /*!< ethernet MAC wakeup management register */ +#define ENET_MAC_INTF REG32((ENET) + 0x00000038U) /*!< ethernet MAC interrupt flag register */ +#define ENET_MAC_INTMSK REG32((ENET) + 0x0000003CU) /*!< ethernet MAC interrupt mask register */ +#define ENET_MAC_ADDR0H REG32((ENET) + 0x00000040U) /*!< ethernet MAC address 0 high register */ +#define ENET_MAC_ADDR0L REG32((ENET) + 0x00000044U) /*!< ethernet MAC address 0 low register */ +#define ENET_MAC_ADDR1H REG32((ENET) + 0x00000048U) /*!< ethernet MAC address 1 high register */ +#define ENET_MAC_ADDR1L REG32((ENET) + 0x0000004CU) /*!< ethernet MAC address 1 low register */ +#define ENET_MAC_ADDT2H REG32((ENET) + 0x00000050U) /*!< ethernet MAC address 2 high register */ +#define ENET_MAC_ADDR2L REG32((ENET) + 0x00000054U) /*!< ethernet MAC address 2 low register */ +#define ENET_MAC_ADDR3H REG32((ENET) + 0x00000058U) /*!< ethernet MAC address 3 high register */ +#define ENET_MAC_ADDR3L REG32((ENET) + 0x0000005CU) /*!< ethernet MAC address 3 low register */ + +#define ENET_MSC_CTL REG32((ENET) + 0x00000100U) /*!< ethernet MSC control register */ +#define ENET_MSC_RINTF REG32((ENET) + 0x00000104U) /*!< ethernet MSC receive interrupt flag register */ +#define ENET_MSC_TINTF REG32((ENET) + 0x00000108U) /*!< ethernet MSC transmit interrupt flag register */ +#define ENET_MSC_RINTMSK REG32((ENET) + 0x0000010CU) /*!< ethernet MSC receive interrupt mask register */ +#define ENET_MSC_TINTMSK REG32((ENET) + 0x00000110U) /*!< ethernet MSC transmit interrupt mask register */ +#define ENET_MSC_SCCNT REG32((ENET) + 0x0000014CU) /*!< ethernet MSC transmitted good frames after a single collision counter register */ +#define ENET_MSC_MSCCNT REG32((ENET) + 0x00000150U) /*!< ethernet MSC transmitted good frames after more than a single collision counter register */ +#define ENET_MSC_TGFCNT REG32((ENET) + 0x00000168U) /*!< ethernet MSC transmitted good frames counter register */ +#define ENET_MSC_RFCECNT REG32((ENET) + 0x00000194U) /*!< ethernet MSC received frames with CRC error counter register */ +#define ENET_MSC_RFAECNT REG32((ENET) + 0x00000198U) /*!< ethernet MSC received frames with alignment error counter register */ +#define ENET_MSC_RGUFCNT REG32((ENET) + 0x000001C4U) /*!< ethernet MSC received good unicast frames counter register */ + +#define ENET_PTP_TSCTL REG32((ENET) + 0x00000700U) /*!< ethernet PTP time stamp control register */ +#define ENET_PTP_SSINC REG32((ENET) + 0x00000704U) /*!< ethernet PTP subsecond increment register */ +#define ENET_PTP_TSH REG32((ENET) + 0x00000708U) /*!< ethernet PTP time stamp high register */ +#define ENET_PTP_TSL REG32((ENET) + 0x0000070CU) /*!< ethernet PTP time stamp low register */ +#define ENET_PTP_TSUH REG32((ENET) + 0x00000710U) /*!< ethernet PTP time stamp update high register */ +#define ENET_PTP_TSUL REG32((ENET) + 0x00000714U) /*!< ethernet PTP time stamp update low register */ +#define ENET_PTP_TSADDEND REG32((ENET) + 0x00000718U) /*!< ethernet PTP time stamp addend register */ +#define ENET_PTP_ETH REG32((ENET) + 0x0000071CU) /*!< ethernet PTP expected time high register */ +#define ENET_PTP_ETL REG32((ENET) + 0x00000720U) /*!< ethernet PTP expected time low register */ + +#define ENET_DMA_BCTL REG32((ENET) + 0x00001000U) /*!< ethernet DMA bus control register */ +#define ENET_DMA_TPEN REG32((ENET) + 0x00001004U) /*!< ethernet DMA transmit poll enable register */ +#define ENET_DMA_RPEN REG32((ENET) + 0x00001008U) /*!< ethernet DMA receive poll enable register */ +#define ENET_DMA_RDTADDR REG32((ENET) + 0x0000100CU) /*!< ethernet DMA receive descriptor table address register */ +#define ENET_DMA_TDTADDR REG32((ENET) + 0x00001010U) /*!< ethernet DMA transmit descriptor table address register */ +#define ENET_DMA_STAT REG32((ENET) + 0x00001014U) /*!< ethernet DMA status register */ +#define ENET_DMA_CTL REG32((ENET) + 0x00001018U) /*!< ethernet DMA control register */ +#define ENET_DMA_INTEN REG32((ENET) + 0x0000101CU) /*!< ethernet DMA interrupt enable register */ +#define ENET_DMA_MFBOCNT REG32((ENET) + 0x00001020U) /*!< ethernet DMA missed frame and buffer overflow counter register */ +#define ENET_DMA_CTDADDR REG32((ENET) + 0x00001048U) /*!< ethernet DMA current transmit descriptor address register */ +#define ENET_DMA_CRDADDR REG32((ENET) + 0x0000104CU) /*!< ethernet DMA current receive descriptor address register */ +#define ENET_DMA_CTBADDR REG32((ENET) + 0x00001050U) /*!< ethernet DMA current transmit buffer address register */ +#define ENET_DMA_CRBADDR REG32((ENET) + 0x00001054U) /*!< ethernet DMA current receive buffer address register */ /* bits definitions */ /* ENET_MAC_CFG */ @@ -196,60 +193,60 @@ OF SUCH DAMAGE. #define ENET_MAC_CFG_ROD BIT(13) /*!< receive own disable */ #define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet speed */ #define ENET_MAC_CFG_CSD BIT(16) /*!< carrier sense disable */ -#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ +#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ #define ENET_MAC_CFG_JBD BIT(22) /*!< jabber disable */ #define ENET_MAC_CFG_WDD BIT(23) /*!< watchdog disable */ /* ENET_MAC_FRMF */ #define ENET_MAC_FRMF_PM BIT(0) /*!< promiscuous mode */ #define ENET_MAC_FRMF_HUF BIT(1) /*!< hash unicast filter */ -#define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */ -#define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ -#define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ -#define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ -#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ -#define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ -#define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ -#define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ -#define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ - +#define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */ +#define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ +#define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ +#define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ +#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ +#define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ +#define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ +#define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ +#define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ + /* ENET_MAC_HLH */ #define ENET_MAC_HLH_HLH BITS(0,31) /*!< hash list high */ - + /* ENET_MAC_HLL */ #define ENET_MAC_HLL_HLL BITS(0,31) /*!< hash list low */ - + /* ENET_MAC_PHY_CTL */ -#define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ -#define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ -#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ -#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ -#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ - +#define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ +#define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ +#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ +#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ +#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ + /* ENET_MAC_PHY_DATA */ #define ENET_MAC_PHY_DATA_PD BITS(0,15) /*!< PHY data */ - + /* ENET_MAC_FCTL */ #define ENET_MAC_FCTL_FLCBBKPA BIT(0) /*!< flow control busy(in full duplex mode)/backpressure activate(in half duplex mode) */ #define ENET_MAC_FCTL_TFCEN BIT(1) /*!< transmit flow control enable */ #define ENET_MAC_FCTL_RFCEN BIT(2) /*!< receive flow control enable */ #define ENET_MAC_FCTL_UPFDT BIT(3) /*!< unicast pause frame detect */ -#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ +#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ #define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-quanta pause */ #define ENET_MAC_FCTL_PTM BITS(16,31) /*!< pause time */ - + /* ENET_MAC_FCTH */ #define ENET_MAC_FCTH_RFA BITS(0,2) /*!< threshold of active flow control */ #define ENET_MAC_FCTH_RFD BITS(4,6) /*!< threshold of deactive flow control */ - + /* ENET_MAC_VLT */ #define ENET_MAC_VLT_VLTI BITS(0,15) /*!< VLAN tag identifier(for receive frames) */ #define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN tag comparison */ - + /* ENET_MAC_RWFF */ #define ENET_MAC_RWFF_DATA BITS(0,31) /*!< wakeup frame filter register data */ - -/* ENET_MAC_WUM */ + +/* ENET_MAC_WUM */ #define ENET_MAC_WUM_PWD BIT(0) /*!< power down */ #define ENET_MAC_WUM_MPEN BIT(1) /*!< magic packet enable */ #define ENET_MAC_WUM_WFEN BIT(2) /*!< wakeup frame enable */ @@ -258,7 +255,7 @@ OF SUCH DAMAGE. #define ENET_MAC_WUM_GU BIT(9) /*!< global unicast */ #define ENET_MAC_WUM_WUFFRPR BIT(31) /*!< wakeup frame filter register pointer reset */ -/* ENET_MAC_INTF */ +/* ENET_MAC_INTF */ #define ENET_MAC_INTF_WUM BIT(3) /*!< WUM status */ #define ENET_MAC_INTF_MSC BIT(4) /*!< MSC status */ #define ENET_MAC_INTF_MSCR BIT(5) /*!< MSC receive status */ @@ -272,28 +269,28 @@ OF SUCH DAMAGE. /* ENET_MAC_ADDR0H */ #define ENET_MAC_ADDR0H_ADDR0H BITS(0,15) /*!< MAC address0 high */ #define ENET_MAC_ADDR0H_MO BIT(31) /*!< always read 1 and must be kept */ - + /* ENET_MAC_ADDR0L */ #define ENET_MAC_ADDR0L_ADDR0L BITS(0,31) /*!< MAC address0 low */ - + /* ENET_MAC_ADDR1H */ #define ENET_MAC_ADDR1H_ADDR1H BITS(0,15) /*!< MAC address1 high */ -#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ +#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ #define ENET_MAC_ADDR1H_SAF BIT(30) /*!< source address filter */ #define ENET_MAC_ADDR1H_AFE BIT(31) /*!< address filter enable */ - + /* ENET_MAC_ADDR1L */ #define ENET_MAC_ADDR1L_ADDR1L BITS(0,31) /*!< MAC address1 low */ - + /* ENET_MAC_ADDR2H */ #define ENET_MAC_ADDR2H_ADDR2H BITS(0,15) /*!< MAC address2 high */ #define ENET_MAC_ADDR2H_MB BITS(24,29) /*!< mask byte */ #define ENET_MAC_ADDR2H_SAF BIT(30) /*!< source address filter */ #define ENET_MAC_ADDR2H_AFE BIT(31) /*!< address filter enable */ - + /* ENET_MAC_ADDR2L */ #define ENET_MAC_ADDR2L_ADDR2L BITS(0,31) /*!< MAC address2 low */ - + /* ENET_MAC_ADDR3H */ #define ENET_MAC_ADDR3H_ADDR3H BITS(0,15) /*!< MAC address3 high */ #define ENET_MAC_ADDR3H_MB BITS(24,29) /*!< mask byte */ @@ -302,7 +299,7 @@ OF SUCH DAMAGE. /* ENET_MAC_ADDR3L */ #define ENET_MAC_ADDR3L_ADDR3L BITS(0,31) /*!< MAC address3 low */ - + /* ENET_MSC_CTL */ #define ENET_MSC_CTL_CTR BIT(0) /*!< counter reset */ #define ENET_MSC_CTL_CTSR BIT(1) /*!< counter stop rollover */ @@ -313,7 +310,7 @@ OF SUCH DAMAGE. #define ENET_MSC_RINTF_RFCE BIT(5) /*!< received frames CRC error */ #define ENET_MSC_RINTF_RFAE BIT(6) /*!< received frames alignment error */ #define ENET_MSC_RINTF_RGUF BIT(17) /*!< receive good unicast frames */ - + /* ENET_MSC_TINTF */ #define ENET_MSC_TINTF_TGFSC BIT(14) /*!< transmitted good frames single collision */ #define ENET_MSC_TINTF_TGFMSC BIT(15) /*!< transmitted good frames more single collision */ @@ -323,30 +320,30 @@ OF SUCH DAMAGE. #define ENET_MSC_RINTMSK_RFCEIM BIT(5) /*!< received frame CRC error interrupt mask */ #define ENET_MSC_RINTMSK_RFAEIM BIT(6) /*!< received frames alignment error interrupt mask */ #define ENET_MSC_RINTMSK_RGUFIM BIT(17) /*!< received good unicast frames interrupt mask */ - + /* ENET_MSC_TINTMSK */ #define ENET_MSC_TINTMSK_TGFSCIM BIT(14) /*!< transmitted good frames single collision interrupt mask */ #define ENET_MSC_TINTMSK_TGFMSCIM BIT(15) /*!< transmitted good frames more single collision interrupt mask */ #define ENET_MSC_TINTMSK_TGFIM BIT(21) /*!< transmitted good frames interrupt mask */ - + /* ENET_MSC_SCCNT */ #define ENET_MSC_SCCNT_SCC BITS(0,31) /*!< transmitted good frames single collision counter */ - + /* ENET_MSC_MSCCNT */ #define ENET_MSC_MSCCNT_MSCC BITS(0,31) /*!< transmitted good frames more one single collision counter */ - + /* ENET_MSC_TGFCNT */ #define ENET_MSC_TGFCNT_TGF BITS(0,31) /*!< transmitted good frames counter */ - + /* ENET_MSC_RFCECNT */ #define ENET_MSC_RFCECNT_RFCER BITS(0,31) /*!< received frames with CRC error counter */ - + /* ENET_MSC_RFAECNT */ #define ENET_MSC_RFAECNT_RFAER BITS(0,31) /*!< received frames alignment error counter */ - + /* ENET_MSC_RGUFCNT */ #define ENET_MSC_RGUFCNT_RGUF BITS(0,31) /*!< received good unicast frames counter */ - + /* ENET_PTP_TSCTL */ #define ENET_PTP_TSCTL_TMSEN BIT(0) /*!< timestamp enable */ #define ENET_PTP_TSCTL_TMSFCU BIT(1) /*!< timestamp fine or coarse update */ @@ -357,30 +354,30 @@ OF SUCH DAMAGE. /* ENET_PTP_SSINC */ #define ENET_PTP_SSINC_STMSSI BITS(0,7) /*!< system time subsecond increment */ - + /* ENET_PTP_TSH */ #define ENET_PTP_TSH_STMS BITS(0,31) /*!< system time second */ - + /* ENET_PTP_TSL */ #define ENET_PTP_TSL_STMSS BITS(0,30) /*!< system time subseconds */ #define ENET_PTP_TSL_STS BIT(31) /*!< system time sign */ - + /* ENET_PTP_TSUH */ #define ENET_PTP_TSUH_TMSUS BITS(0,31) /*!< timestamp update seconds */ - + /* ENET_PTP_TSUL */ #define ENET_PTP_TSUL_TMSUSS BITS(0,30) /*!< timestamp update subseconds */ #define ENET_PTP_TSUL_TMSUPNS BIT(31) /*!< timestamp update positive or negative sign */ /* ENET_PTP_TSADDEND */ #define ENET_PTP_TSADDEND_TMSA BITS(0,31) /*!< timestamp addend */ - + /* ENET_PTP_ETH */ #define ENET_PTP_ETH_ETSH BITS(0,31) /*!< expected time high */ - + /* ENET_PTP_ETL */ #define ENET_PTP_ETL_ETSL BITS(0,31) /*!< expected time low */ - + /* ENET_DMA_BCTL */ #define ENET_DMA_BCTL_SWR BIT(0) /*!< software reset */ #define ENET_DMA_BCTL_DAB BIT(1) /*!< DMA arbitration */ @@ -392,19 +389,19 @@ OF SUCH DAMAGE. #define ENET_DMA_BCTL_UIP BIT(23) /*!< use independent PGBL */ #define ENET_DMA_BCTL_FPBL BIT(24) /*!< four times PGBL mode */ #define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligned */ - + /* ENET_DMA_TPEN */ #define ENET_DMA_TPEN_TPE BITS(0,31) /*!< transmit poll enable */ - + /* ENET_DMA_RPEN */ #define ENET_DMA_RPEN_RPE BITS(0,31) /*!< receive poll enable */ /* ENET_DMA_RDTADDR */ #define ENET_DMA_RDTADDR_SRT BITS(0,31) /*!< start address of receive table */ - + /* ENET_DMA_TDTADDR */ #define ENET_DMA_TDTADDR_STT BITS(0,31) /*!< start address of transmit table */ - + /* ENET_DMA_STAT */ #define ENET_DMA_STAT_TS BIT(0) /*!< transmit status */ #define ENET_DMA_STAT_TPS BIT(1) /*!< transmit process stopped status */ @@ -427,7 +424,7 @@ OF SUCH DAMAGE. #define ENET_DMA_STAT_MSC BIT(27) /*!< MSC status */ #define ENET_DMA_STAT_WUM BIT(28) /*!< WUM status */ #define ENET_DMA_STAT_TST BIT(29) /*!< timestamp trigger status */ - + /* ENET_DMA_CTL */ #define ENET_DMA_CTL_SRE BIT(1) /*!< start/stop receive enable */ #define ENET_DMA_CTL_OSF BIT(2) /*!< operate on second frame */ @@ -441,7 +438,7 @@ OF SUCH DAMAGE. #define ENET_DMA_CTL_DAFRF BIT(24) /*!< disable flushing of received frames */ #define ENET_DMA_CTL_RSFD BIT(25) /*!< receive store-and-forward */ #define ENET_DMA_CTL_DTCERFD BIT(26) /*!< dropping of TCP/IP checksum error frames disable */ - + /* ENET_DMA_INTEN */ #define ENET_DMA_INTEN_TIE BIT(0) /*!< transmit interrupt enable */ #define ENET_DMA_INTEN_TPSIE BIT(1) /*!< transmit process stopped interrupt enable */ @@ -458,7 +455,7 @@ OF SUCH DAMAGE. #define ENET_DMA_INTEN_ERIE BIT(14) /*!< early receive interrupt enable */ #define ENET_DMA_INTEN_AIE BIT(15) /*!< abnormal interrupt summary enable */ #define ENET_DMA_INTEN_NIE BIT(16) /*!< normal interrupt summary enable */ - + /* ENET_DMA_MFBOCNT */ #define ENET_DMA_MFBOCNT_MSFC BITS(0,15) /*!< missed frames by the controller */ #define ENET_DMA_MFBOCNT_OBMFC BIT(16) /*!< overflow bit for missed frame counter */ @@ -470,10 +467,10 @@ OF SUCH DAMAGE. /* ENET_DMA_CRDADDR */ #define ENET_DMA_CRDADDR_RDAP BITS(0,31) /*!< receive descriptor address pointer */ - + /* ENET_DMA_CTBADDR */ #define ENET_DMA_CTBADDR_TBAP BITS(0,31) /*!< transmit buffer address pointer */ - + /* ENET_DMA_CRBADDR */ #define ENET_DMA_CRBADDR_RBAP BITS(0,31) /*!< receive buffer address pointer */ @@ -523,7 +520,7 @@ OF SUCH DAMAGE. #define ENET_RDES0_FRMT BIT(5) /*!< frame type */ #define ENET_RDES0_LCO BIT(6) /*!< late collision */ #define ENET_RDES0_IPHERR BIT(7) /*!< IP frame header error */ -#define ENET_RDES0_LDES BIT(8) /*!< last descriptor */ +#define ENET_RDES0_LDES BIT(8) /*!< last descriptor */ #define ENET_RDES0_FDES BIT(9) /*!< first descriptor */ #define ENET_RDES0_VTAG BIT(10) /*!< VLAN tag */ #define ENET_RDES0_OERR BIT(11) /*!< overflow Error */ @@ -535,7 +532,7 @@ OF SUCH DAMAGE. #define ENET_RDES0_DAFF BIT(30) /*!< destination address filter fail */ #define ENET_RDES0_DAV BIT(31) /*!< descriptor available */ -/* ENET DMA Rx descriptor RDES1 */ +/* ENET DMA Rx descriptor RDES1 */ #define ENET_RDES1_RB1S BITS(0,12) /*!< receive buffer 1 size */ #define ENET_RDES1_RCHM BIT(14) /*!< receive chained mode for second address */ #define ENET_RDES1_RERM BIT(15) /*!< receive end of ring mode*/ @@ -550,52 +547,51 @@ OF SUCH DAMAGE. /* constants definitions */ /* define bit position and its register index offset */ -#define ENET_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph)>>6))) -#define ENET_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define ENET_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6U) | (uint32_t)(bitpos)) +#define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph) >> 6U))) +#define ENET_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) /* ENET clock range judgement */ #define ENET_RANGE(hclk, n, m) (((hclk) >= (n))&&((hclk) < (m))) /* define MAC address configuration and reference address */ -#define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4]) -#define ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0]) -#define ENET_ADDRH_BASE ((ENET) + 0x40U) -#define ENET_ADDRL_BASE ((ENET) + 0x44U) +#define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8U) | (uint32_t)(p)[4]) +#define ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24U) | ((uint32_t)(p)[2] << 16U) | ((uint32_t)(p)[1] << 8U) | (uint32_t)(p)[0]) +#define ENET_ADDRH_BASE ((ENET) + 0x00000040U) +#define ENET_ADDRL_BASE ((ENET) + 0x00000044U) #define ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4U) * 4U)) >> (8U * ((n) % 4U))) & 0xFFU)) /* register offset */ -#define MAC_FCTL_REG_OFFSET 0x0018U /*!< MAC flow control register offset */ -#define MAC_WUM_REG_OFFSET 0x002CU /*!< MAC wakeup management register offset */ -#define MAC_INTF_REG_OFFSET 0x0038U /*!< MAC interrupt flag register offset */ -#define MAC_INTMSK_REG_OFFSET 0x003CU /*!< MAC interrupt mask register offset */ - -#define MSC_RINTF_REG_OFFSET 0x0104U /*!< MSC receive interrupt flag register offset */ -#define MSC_TINTF_REG_OFFSET 0x0108U /*!< MSC transmit interrupt flag register offset */ -#define MSC_RINTMSK_REG_OFFSET 0x010CU /*!< MSC receive interrupt mask register offset */ -#define MSC_TINTMSK_REG_OFFSET 0x0110U /*!< MSC transmit interrupt mask register offset */ -#define MSC_SCCNT_REG_OFFSET 0x014CU /*!< MSC transmitted good frames after a single collision counter register offset */ -#define MSC_MSCCNT_REG_OFFSET 0x0150U /*!< MSC transmitted good frames after more than a single collision counter register offset */ -#define MSC_TGFCNT_REG_OFFSET 0x0168U /*!< MSC transmitted good frames counter register offset */ -#define MSC_RFCECNT_REG_OFFSET 0x0194U /*!< MSC received frames with CRC error counter register offset */ -#define MSC_RFAECNT_REG_OFFSET 0x0198U /*!< MSC received frames with alignment error counter register offset */ -#define MSC_RGUFCNT_REG_OFFSET 0x01C4U /*!< MSC received good unicast frames counter register offset */ - -#define DMA_STAT_REG_OFFSET 0x1014U /*!< DMA status register offset */ -#define DMA_INTEN_REG_OFFSET 0x101CU /*!< DMA interrupt enable register offset */ -#define DMA_TDTADDR_REG_OFFSET 0x1010U /*!< DMA transmit descriptor table address register offset */ -#define DMA_CTDADDR_REG_OFFSET 0x1048U /*!< DMA current transmit descriptor address register */ -#define DMA_CTBADDR_REG_OFFSET 0x1050U /*!< DMA current transmit buffer address register */ -#define DMA_RDTADDR_REG_OFFSET 0x100CU /*!< DMA receive descriptor table address register */ -#define DMA_CRDADDR_REG_OFFSET 0x104CU /*!< DMA current receive descriptor address register */ -#define DMA_CRBADDR_REG_OFFSET 0x1054U /*!< DMA current receive buffer address register */ +#define MAC_FCTL_REG_OFFSET 0x00000018U /*!< MAC flow control register offset */ +#define MAC_WUM_REG_OFFSET 0x0000002CU /*!< MAC wakeup management register offset */ +#define MAC_INTF_REG_OFFSET 0x00000038U /*!< MAC interrupt flag register offset */ +#define MAC_INTMSK_REG_OFFSET 0x0000003CU /*!< MAC interrupt mask register offset */ + +#define MSC_RINTF_REG_OFFSET 0x00000104U /*!< MSC receive interrupt flag register offset */ +#define MSC_TINTF_REG_OFFSET 0x00000108U /*!< MSC transmit interrupt flag register offset */ +#define MSC_RINTMSK_REG_OFFSET 0x0000010CU /*!< MSC receive interrupt mask register offset */ +#define MSC_TINTMSK_REG_OFFSET 0x00000110U /*!< MSC transmit interrupt mask register offset */ +#define MSC_SCCNT_REG_OFFSET 0x0000014CU /*!< MSC transmitted good frames after a single collision counter register offset */ +#define MSC_MSCCNT_REG_OFFSET 0x00000150U /*!< MSC transmitted good frames after more than a single collision counter register offset */ +#define MSC_TGFCNT_REG_OFFSET 0x00000168U /*!< MSC transmitted good frames counter register offset */ +#define MSC_RFCECNT_REG_OFFSET 0x00000194U /*!< MSC received frames with CRC error counter register offset */ +#define MSC_RFAECNT_REG_OFFSET 0x00000198U /*!< MSC received frames with alignment error counter register offset */ +#define MSC_RGUFCNT_REG_OFFSET 0x000001C4U /*!< MSC received good unicast frames counter register offset */ + +#define DMA_STAT_REG_OFFSET 0x00001014U /*!< DMA status register offset */ +#define DMA_INTEN_REG_OFFSET 0x0000101CU /*!< DMA interrupt enable register offset */ +#define DMA_TDTADDR_REG_OFFSET 0x00001010U /*!< DMA transmit descriptor table address register offset */ +#define DMA_CTDADDR_REG_OFFSET 0x00001048U /*!< DMA current transmit descriptor address register */ +#define DMA_CTBADDR_REG_OFFSET 0x00001050U /*!< DMA current transmit buffer address register */ +#define DMA_RDTADDR_REG_OFFSET 0x0000100CU /*!< DMA receive descriptor table address register */ +#define DMA_CRDADDR_REG_OFFSET 0x0000104CU /*!< DMA current receive descriptor address register */ +#define DMA_CRBADDR_REG_OFFSET 0x00001054U /*!< DMA current receive buffer address register */ /* ENET status flag get */ -typedef enum -{ +typedef enum { /* ENET_MAC_WUM register */ ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), /*!< magic packet received flag */ - ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */ + ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */ /* ENET_MAC_FCTL register */ ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U), /*!< flow control status flag */ /* ENET_MAC_INTF register */ @@ -608,7 +604,7 @@ typedef enum ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ - /* ENET_MSC_TINTF register */ + /* ENET_MSC_TINTF register */ ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ @@ -633,12 +629,11 @@ typedef enum ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U), /*!< error during data buffer/descriptor access flag */ ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ - ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ -}enet_flag_enum; + ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U) /*!< timestamp trigger status flag */ +} enet_flag_enum; /* ENET status flag clear */ -typedef enum -{ +typedef enum { /* ENET_DMA_STAT register */ ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ @@ -654,24 +649,23 @@ typedef enum ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ -}enet_flag_clear_enum; + ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U) /*!< normal interrupt summary flag */ +} enet_flag_clear_enum; /* ENET interrupt enable/disable */ -typedef enum -{ +typedef enum { /* ENET_MAC_INTMSK register */ ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), /*!< WUM interrupt mask */ ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), /*!< timestamp trigger interrupt mask */ - /* ENET_MSC_RINTMSK register */ + /* ENET_MSC_RINTMSK register */ ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U), /*!< received frame CRC error interrupt mask */ ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U), /*!< received frames alignment error interrupt mask */ ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U), /*!< received good unicast frames interrupt mask */ - /* ENET_MSC_TINTMSK register */ + /* ENET_MSC_TINTMSK register */ ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U), /*!< transmitted good frames single collision interrupt mask */ ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U), /*!< transmitted good frames more single collision interrupt mask */ ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U), /*!< transmitted good frames interrupt mask */ - /* ENET_DMA_INTEN register */ + /* ENET_DMA_INTEN register */ ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U), /*!< transmit interrupt enable */ ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U), /*!< transmit process stopped interrupt enable */ ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U), /*!< transmit buffer unavailable interrupt enable */ @@ -686,12 +680,11 @@ typedef enum ENET_DMA_INT_FBEIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 13U), /*!< fatal bus error interrupt enable */ ENET_DMA_INT_ERIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 14U), /*!< early receive interrupt enable */ ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U), /*!< abnormal interrupt summary enable */ - ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U), /*!< normal interrupt summary enable */ -}enet_int_enum; - + ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U) /*!< normal interrupt summary enable */ +} enet_int_enum; + /* ENET interrupt flag get */ -typedef enum -{ +typedef enum { /* ENET_MAC_INTF register */ ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ @@ -724,12 +717,11 @@ typedef enum ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ - ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ -}enet_int_flag_enum; + ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U) /*!< timestamp trigger status flag */ +} enet_int_flag_enum; /* ENET interrupt flag clear */ -typedef enum -{ +typedef enum { /* ENET_DMA_STAT register */ ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ @@ -745,34 +737,31 @@ typedef enum ENET_DMA_INT_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ ENET_DMA_INT_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ ENET_DMA_INT_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ -}enet_int_flag_clear_enum; + ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U) /*!< normal interrupt summary flag */ +} enet_int_flag_clear_enum; /* current RX/TX descriptor/buffer/descriptor table address get */ -typedef enum -{ +typedef enum { ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET, /*!< RX descriptor table */ ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET, /*!< current RX descriptor */ ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET, /*!< current RX buffer */ ENET_TX_DESC_TABLE = DMA_TDTADDR_REG_OFFSET, /*!< TX descriptor table */ ENET_TX_CURRENT_DESC = DMA_CTDADDR_REG_OFFSET, /*!< current TX descriptor */ ENET_TX_CURRENT_BUFFER = DMA_CTBADDR_REG_OFFSET /*!< current TX buffer */ -}enet_desc_reg_enum; +} enet_desc_reg_enum; /* MAC statistics counter get */ -typedef enum -{ +typedef enum { ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET, /*!< MSC transmitted good frames after a single collision counter */ ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET, /*!< MSC transmitted good frames after more than a single collision counter */ ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET, /*!< MSC transmitted good frames counter */ ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET, /*!< MSC received frames with CRC error counter */ ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET, /*!< MSC received frames with alignment error counter */ ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET /*!< MSC received good unicast frames counter */ -}enet_msc_counter_enum; +} enet_msc_counter_enum; /* function option, used for ENET initialization */ -typedef enum -{ +typedef enum { FORWARD_OPTION = BIT(0), /*!< configure the frame forward related parameters */ DMABUS_OPTION = BIT(1), /*!< configure the DMA bus mode related parameters */ DMA_MAXBURST_OPTION = BIT(2), /*!< configure the DMA max burst related parameters */ @@ -786,152 +775,140 @@ typedef enum FILTER_OPTION = BIT(10), /*!< configure the frame filter control related parameters */ HALFDUPLEX_OPTION = BIT(11), /*!< configure the halfduplex related parameters */ TIMER_OPTION = BIT(12), /*!< configure the frame timer related parameters */ - INTERFRAMEGAP_OPTION = BIT(13), /*!< configure the inter frame gap related parameters */ -}enet_option_enum; + INTERFRAMEGAP_OPTION = BIT(13) /*!< configure the inter frame gap related parameters */ +} enet_option_enum; /* phy mode and mac loopback configurations */ -typedef enum -{ +typedef enum { ENET_AUTO_NEGOTIATION = 0x01U, /*!< PHY auto negotiation */ ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */ - ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD , /*!< 100Mbit/s, half-duplex */ + ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD, /*!< 100Mbit/s, half-duplex */ ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM, /*!< 10Mbit/s, full-duplex */ ENET_10M_HALFDUPLEX = (uint32_t)0x00000000U, /*!< 10Mbit/s, half-duplex */ ENET_LOOPBACKMODE = (ENET_MAC_CFG_LBM | ENET_MAC_CFG_DPM) /*!< MAC in loopback mode at the MII */ -}enet_mediamode_enum; +} enet_mediamode_enum; /* IP frame checksum function */ -typedef enum -{ +typedef enum { ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U, /*!< disable IP frame checksum function */ ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO, /*!< enable IP frame checksum function */ - ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO|ENET_DMA_CTL_DTCERFD) /*!< enable IP frame checksum function, and the received frame + ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO | ENET_DMA_CTL_DTCERFD) /*!< enable IP frame checksum function, and the received frame with only payload error but no other errors will not be dropped */ -}enet_chksumconf_enum; +} enet_chksumconf_enum; /* received frame filter function */ -typedef enum -{ +typedef enum { ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM, /*!< promiscuous mode enabled */ ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR, /*!< all received frame are forwarded to application */ - ENET_CUSTOM = BIT(4), + ENET_CUSTOM = BIT(4), /** AvV **/ ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U, /*!< the address filters pass all received broadcast frames */ ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ -}enet_frmrecept_enum; +} enet_frmrecept_enum; /* register group value get */ -typedef enum -{ - ALL_MAC_REG = 0, /*!< MAC register group */ - ALL_MSC_REG = 22, /*!< MSC register group */ - ALL_PTP_REG = 33, /*!< PTP register group */ - ALL_DMA_REG = 44, /*!< DMA register group */ -}enet_registers_type_enum; +typedef enum { + ALL_MAC_REG = 0U, /*!< MAC register group */ + ALL_MSC_REG = 22U, /*!< MSC register group */ + ALL_PTP_REG = 33U, /*!< PTP register group */ + ALL_DMA_REG = 44U /*!< DMA register group */ +} enet_registers_type_enum; /* dma direction select */ -typedef enum -{ +typedef enum { ENET_DMA_TX = ENET_DMA_STAT_TP, /*!< DMA transmit direction */ ENET_DMA_RX = ENET_DMA_STAT_RP /*!< DMA receive direction */ -}enet_dmadirection_enum; +} enet_dmadirection_enum; /* PHY operation direction select */ -typedef enum -{ - ENET_PHY_READ = (uint32_t)0x00000000, /*!< read PHY */ +typedef enum { + ENET_PHY_READ = (uint32_t)0x00000000U, /*!< read PHY */ ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW /*!< write PHY */ -}enet_phydirection_enum; +} enet_phydirection_enum; /* register operation direction select */ -typedef enum -{ +typedef enum { ENET_REG_READ, /*!< read register */ ENET_REG_WRITE /*!< write register */ -}enet_regdirection_enum; +} enet_regdirection_enum; -/* ENET MAC addresses */ -typedef enum -{ - ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), /*!< MAC address0 */ - ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008), /*!< MAC address1 */ - ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010), /*!< MAC address2 */ - ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018) /*!< MAC address3 */ -}enet_macaddress_enum; +/* ENET MAC addresses */ +typedef enum { + ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000U), /*!< MAC address0 */ + ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008U), /*!< MAC address1 */ + ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010U), /*!< MAC address2 */ + ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018U) /*!< MAC address3 */ +} enet_macaddress_enum; /* descriptor information */ -typedef enum -{ +typedef enum { TXDESC_COLLISION_COUNT, /*!< the number of collisions occurred before the frame was transmitted */ TXDESC_BUFFER_1_ADDR, /*!< transmit frame buffer 1 address */ RXDESC_FRAME_LENGTH, /*!< the byte length of the received frame that was transferred to the buffer */ RXDESC_BUFFER_1_SIZE, /*!< receive buffer 1 size */ RXDESC_BUFFER_2_SIZE, /*!< receive buffer 2 size */ RXDESC_BUFFER_1_ADDR /*!< receive frame buffer 1 address */ -}enet_descstate_enum; +} enet_descstate_enum; /* structure for initialization of the ENET */ -typedef struct -{ +typedef struct { uint32_t option_enable; /*!< select which function to configure */ - uint32_t forward_frame; /*!< frame forward related parameters */ + uint32_t forward_frame; /*!< frame forward related parameters */ uint32_t dmabus_mode; /*!< DMA bus mode related parameters */ uint32_t dma_maxburst; /*!< DMA max burst related parameters */ uint32_t dma_arbitration; /*!< DMA Tx and Rx arbitration related parameters */ uint32_t store_forward_mode; /*!< store forward mode related parameters */ uint32_t dma_function; /*!< DMA control related parameters */ - uint32_t vlan_config; /*!< VLAN tag related parameters */ + uint32_t vlan_config; /*!< VLAN tag related parameters */ uint32_t flow_control; /*!< flow control related parameters */ uint32_t hashtable_high; /*!< hash list high 32-bit related parameters */ uint32_t hashtable_low; /*!< hash list low 32-bit related parameters */ uint32_t framesfilter_mode; /*!< frame filter control related parameters */ - uint32_t halfduplex_param; /*!< halfduplex related parameters */ + uint32_t halfduplex_param; /*!< halfduplex related parameters */ uint32_t timer_config; /*!< frame timer related parameters */ uint32_t interframegap; /*!< inter frame gap related parameters */ -}enet_initpara_struct; +} enet_initpara_struct; -/* structure for ENET DMA descriptors */ -typedef struct -{ +/* structure for ENET DMA descriptors */ +typedef struct { uint32_t status; /*!< status */ uint32_t control_buffer_size; /*!< control and buffer1, buffer2 lengths */ uint32_t buffer1_addr; /*!< buffer1 address pointer/timestamp low */ uint32_t buffer2_next_desc_addr; /*!< buffer2 or next descriptor address pointer/timestamp high */ } enet_descriptors_struct; -/* structure of PTP system time */ -typedef struct -{ +/* structure of PTP system time */ +typedef struct { uint32_t second; /*!< second of system time */ uint32_t nanosecond; /*!< nanosecond of system time */ uint32_t sign; /*!< sign of system time */ -}enet_ptp_systime_struct; +} enet_ptp_systime_struct; /* mac_cfg register value */ -#define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5)) /*!< write value to ENET_MAC_CFG_BOL bit field */ +#define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5U)) /*!< write value to ENET_MAC_CFG_BOL bit field */ #define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0) /*!< min (n, 10) */ #define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1) /*!< min (n, 8) */ #define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2) /*!< min (n, 4) */ -#define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ +#define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ -#define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */ -#define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ +#define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17U)) /*!< write value to ENET_MAC_CFG_IGBS bit field */ +#define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ #define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1) /*!< minimum 88 bit times */ #define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2) /*!< minimum 80 bit times */ #define ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3) /*!< minimum 72 bit times */ -#define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4) /*!< minimum 64 bit times */ +#define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4) /*!< minimum 64 bit times */ #define ENET_INTERFRAMEGAP_56BIT MAC_CFG_IGBS(5) /*!< minimum 56 bit times */ #define ENET_INTERFRAMEGAP_48BIT MAC_CFG_IGBS(6) /*!< minimum 48 bit times */ -#define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7) /*!< minimum 40 bit times */ +#define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7) /*!< minimum 40 bit times */ #define ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U) /*!< the MAC allows no more than 2048 bytes of the frame being received */ #define ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD /*!< the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16384 bytes */ - + #define ENET_JABBER_ENABLE ((uint32_t)0x00000000U) /*!< the maximum transmission byte is 2048 */ #define ENET_JABBER_DISABLE ENET_MAC_CFG_JBD /*!< the maximum transmission byte can be 16384 */ #define ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U) /*!< the MAC transmitter generates carrier sense error and aborts the transmission */ #define ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD /*!< the MAC transmitter ignores the MII CRS signal during frame transmission in half-duplex mode */ - + #define ENET_SPEEDMODE_10M ((uint32_t)0x00000000U) /*!< 10 Mbit/s */ #define ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD /*!< 100 Mbit/s */ @@ -958,15 +935,15 @@ typedef struct #define ENET_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000U) /*!< the deferral check function is disabled */ /* mac_frmf register value */ -#define MAC_FRMF_PCFRM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_FRMF_PCFRM bit field */ +#define MAC_FRMF_PCFRM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U)) /*!< write value to ENET_MAC_FRMF_PCFRM bit field */ #define ENET_PCFRM_PREVENT_ALL MAC_FRMF_PCFRM(0) /*!< MAC prevents all control frames from reaching the application */ #define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1) /*!< MAC only forwards all other control frames except pause control frame */ #define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2) /*!< MAC forwards all control frames to application even if they fail the address filter */ #define ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3) /*!< MAC forwards control frames that only pass the address filter */ - + #define ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR /*!< all received frame are forwarded to application */ #define ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U) /*!< only the frame passed the filter can be forwarded to application */ - + #define ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT /*!< filter source address */ #define ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT) /*!< inverse source address filtering result */ #define ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< source address function in filter disable */ @@ -975,14 +952,14 @@ typedef struct #define ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U) /*!< the address filters pass all received broadcast frames */ #define ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ - + #define ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result */ #define ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U) /*!< not inverse DA filtering result */ #define ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result function */ #define ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM /*!< promiscuous mode enabled */ #define ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U) /*!< promiscuous mode disabled */ - + #define ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT) /*!< pass multicast frames that match either the perfect or the hash filtering */ #define ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF /*!< pass multicast frames that match the hash filtering */ #define ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass multicast frames that match the perfect filtering */ @@ -997,25 +974,25 @@ typedef struct #define ENET_UNICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HUF /*!< HASH unicast filter function */ /* mac_phy_ctl register value */ -#define MAC_PHY_CTL_CLR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_MAC_PHY_CTL_CLR bit field */ +#define MAC_PHY_CTL_CLR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2U)) /*!< write value to ENET_MAC_PHY_CTL_CLR bit field */ #define ENET_MDC_HCLK_DIV42 MAC_PHY_CTL_CLR(0) /*!< HCLK:60-100 MHz; MDC clock= HCLK/42 */ #define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-120 MHz; MDC clock= HCLK/62 */ #define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */ #define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */ -#define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */ +#define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6U)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */ -#define MAC_PHY_CTL_PA(regval) (BITS(11,15) & ((uint32_t)(regval) << 11)) /*!< write value to ENET_MAC_PHY_CTL_PA bit field */ +#define MAC_PHY_CTL_PA(regval) (BITS(11,15) & ((uint32_t)(regval) << 11U)) /*!< write value to ENET_MAC_PHY_CTL_PA bit field */ /* mac_phy_data register value */ -#define MAC_PHY_DATA_PD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_PHY_DATA_PD bit field */ +#define MAC_PHY_DATA_PD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to ENET_MAC_PHY_DATA_PD bit field */ /* mac_fctl register value */ -#define MAC_FCTL_PLTS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< write value to ENET_MAC_FCTL_PLTS bit field */ +#define MAC_FCTL_PLTS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4U)) /*!< write value to ENET_MAC_FCTL_PLTS bit field */ #define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0) /*!< pause time minus 4 slot times */ #define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1) /*!< pause time minus 28 slot times */ #define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2) /*!< pause time minus 144 slot times */ -#define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */ +#define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */ #define ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U) /*!< enable the automatic zero-quanta generation function */ #define ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP /*!< disable the automatic zero-quanta generation function */ @@ -1023,7 +1000,7 @@ typedef struct #define ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT /*!< besides the unique multicast address, MAC also use the MAC0 address to detect pause frame */ #define ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U) /*!< only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected */ - + #define ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN /*!< enable decoding function for the received pause frame and process it */ #define ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< decode function for pause frame is disabled */ #define ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN /*!< decoding function for the received pause frame and process it */ @@ -1035,28 +1012,28 @@ typedef struct #define ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA /*!< enable the back pressure operation in the MAC */ #define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U) /*!< disable the back pressure operation in the MAC */ #define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA /*!< the back pressure operation in the MAC */ - -#define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */ + +#define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16U)) /*!< write value to ENET_MAC_FCTL_PTM bit field */ /* mac_vlt register value */ -#define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */ - +#define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to ENET_MAC_VLT_VLTI bit field */ + #define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC /*!< only low 12 bits of the VLAN tag are used for comparison */ #define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) /*!< all 16 bits of the VLAN tag are used for comparison */ -/* mac_wum register value */ +/* mac_wum register value */ #define ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR /*!< wakeup frame filter register poniter reset */ #define ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR /*!< wakeup frame received */ #define ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR /*!< magic packet received */ -#define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */ -#define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */ -#define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */ +#define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */ +#define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */ +#define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */ #define ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU /*!< any received unicast frame passed filter is considered to be a wakeup frame */ /* mac_addr0h register value */ -#define MAC_ADDR0H_ADDR0H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDR0H_ADDR0H bit field */ +#define MAC_ADDR0H_ADDR0H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to ENET_MAC_ADDR0H_ADDR0H bit field */ /* mac_addrxh register value, x = 1,2,3 */ -#define MAC_ADDR123H_ADDR123H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDRxH_ADDRxH(x=1,2,3) bit field */ +#define MAC_ADDR123H_ADDR123H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to ENET_MAC_ADDRxH_ADDRxH(x=1,2,3) bit field */ #define ENET_ADDRESS_MASK_BYTE0 BIT(24) /*!< low register bits [7:0] */ #define ENET_ADDRESS_MASK_BYTE1 BIT(25) /*!< low register bits [15:8] */ @@ -1066,10 +1043,10 @@ typedef struct #define ENET_ADDRESS_MASK_BYTE5 BIT(29) /*!< high register bits [15:8] */ #define ENET_ADDRESS_FILTER_SA BIT(30) /*!< use MAC address[47:0] is to compare with the SA fields of the received frame */ -#define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000) /*!< use MAC address[47:0] is to compare with the DA fields of the received frame */ - +#define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000U) /*!< use MAC address[47:0] is to compare with the DA fields of the received frame */ + /* mac_fcth register value */ -#define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0))<<8) /*!< write value to ENET_MAC_FCTH_RFA bit field */ +#define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0U)) << 8U) /*!< write value to ENET_MAC_FCTH_RFA bit field */ #define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0) /*!< threshold level is 256 bytes */ #define ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1) /*!< threshold level is 512 bytes */ #define ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2) /*!< threshold level is 768 bytes */ @@ -1078,7 +1055,7 @@ typedef struct #define ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5) /*!< threshold level is 1536 bytes */ #define ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6) /*!< threshold level is 1792 bytes */ -#define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4))<<8) /*!< write value to ENET_MAC_FCTH_RFD bit field */ +#define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4U)) << 8U) /*!< write value to ENET_MAC_FCTH_RFD bit field */ #define ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0) /*!< threshold level is 256 bytes */ #define ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1) /*!< threshold level is 512 bytes */ #define ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2) /*!< threshold level is 768 bytes */ @@ -1097,100 +1074,100 @@ typedef struct #define ENET_PTP_TIMESTAMP_INT ENET_PTP_TSCTL_TMSITEN /*!< timestamp interrupt trigger enable */ /* ptp_ssinc register value */ -#define PTP_SSINC_STMSSI(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_SSINC_STMSSI bit field */ +#define PTP_SSINC_STMSSI(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U)) /*!< write value to ENET_PTP_SSINC_STMSSI bit field */ /* ptp_tsl register value */ -#define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30) /*!< get value of ENET_PTP_TSL_STMSS bit field */ - -#define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000) /*!< time value is positive */ -#define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS /*!< time value is negative */ +#define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval), 0U, 30U) /*!< get value of ENET_PTP_TSL_STMSS bit field */ -#define GET_PTP_TSL_STS(regval) (((regval) & BIT(31)) >> (31U)) /*!< get value of ENET_PTP_TSL_STS bit field */ +#define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000U) /*!< time value is positive */ +#define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS /*!< time value is negative */ + +#define GET_PTP_TSL_STS(regval) (((regval) & BIT(31)) >> (31U)) /*!< get value of ENET_PTP_TSL_STS bit field */ /* ptp_tsul register value */ -#define PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_TSUL_TMSUSS bit field */ +#define PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0U)) /*!< write value to ENET_PTP_TSUL_TMSUSS bit field */ -#define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000) /*!< timestamp update value is added to system time */ -#define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS /*!< timestamp update value is subtracted from system time */ +#define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000U) /*!< timestamp update value is added to system time */ +#define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS /*!< timestamp update value is subtracted from system time */ /* dma_bctl register value */ -#define DMA_BCTL_DPSL(regval) (BITS(2,6) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_DMA_BCTL_DPSL bit field */ -#define GET_DMA_BCTL_DPSL(regval) GET_BITS((regval),2,6) /*!< get value of ENET_DMA_BCTL_DPSL bit field */ - -#define DMA_BCTL_PGBL(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) /*!< write value to ENET_DMA_BCTL_PGBL bit field */ -#define ENET_PGBL_1BEAT DMA_BCTL_PGBL(1) /*!< maximum number of beats is 1 */ -#define ENET_PGBL_2BEAT DMA_BCTL_PGBL(2) /*!< maximum number of beats is 2 */ -#define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4) /*!< maximum number of beats is 4 */ -#define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8) /*!< maximum number of beats is 8 */ -#define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16) /*!< maximum number of beats is 16 */ -#define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */ -#define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 4 */ -#define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 8 */ -#define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 16 */ -#define ENET_PGBL_4xPGBL_32BEAT (DMA_BCTL_PGBL(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 32 */ -#define ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 64 */ -#define ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 128 */ - -#define DMA_BCTL_RTPR(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_BCTL_RTPR bit field */ -#define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0) /*!< receive and transmit priority ratio is 1:1*/ -#define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1) /*!< receive and transmit priority ratio is 2:1*/ -#define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2) /*!< receive and transmit priority ratio is 3:1 */ -#define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */ -#define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB /*!< RxDMA has higher priority than TxDMA */ - -#define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB /*!< AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers */ -#define ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB can use SINGLE/INCR burst transfer operations */ - -#define DMA_BCTL_RXDP(regval) (BITS(17,22) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_DMA_BCTL_RXDP bit field */ -#define ENET_RXDP_1BEAT DMA_BCTL_RXDP(1) /*!< maximum number of beats 1 */ -#define ENET_RXDP_2BEAT DMA_BCTL_RXDP(2) /*!< maximum number of beats 2 */ -#define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4) /*!< maximum number of beats 4 */ -#define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8) /*!< maximum number of beats 8 */ -#define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16) /*!< maximum number of beats 16 */ -#define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */ -#define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 4 */ -#define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 8 */ -#define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 16 */ -#define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 32 */ -#define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 64 */ -#define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */ - -#define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP /*!< RxDMA uses the RXDP[5:0], while TxDMA uses the PGBL[5:0] */ -#define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000) /*!< RxDMA/TxDMA uses PGBL[5:0] */ - -#define ENET_ADDRESS_ALIGN_ENABLE ENET_DMA_BCTL_AA /*!< enabled address-aligned */ -#define ENET_ADDRESS_ALIGN_DISABLE ((uint32_t)0x00000000) /*!< disable address-aligned */ +#define DMA_BCTL_DPSL(regval) (BITS(2,6) & ((uint32_t)(regval) << 2U)) /*!< write value to ENET_DMA_BCTL_DPSL bit field */ +#define GET_DMA_BCTL_DPSL(regval) GET_BITS((regval), 2U, 6U) /*!< get value of ENET_DMA_BCTL_DPSL bit field */ + +#define DMA_BCTL_PGBL(regval) (BITS(8,13) & ((uint32_t)(regval) << 8U)) /*!< write value to ENET_DMA_BCTL_PGBL bit field */ +#define ENET_PGBL_1BEAT DMA_BCTL_PGBL(1) /*!< maximum number of beats is 1 */ +#define ENET_PGBL_2BEAT DMA_BCTL_PGBL(2) /*!< maximum number of beats is 2 */ +#define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4) /*!< maximum number of beats is 4 */ +#define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8) /*!< maximum number of beats is 8 */ +#define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16) /*!< maximum number of beats is 16 */ +#define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */ +#define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 4 */ +#define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 8 */ +#define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 16 */ +#define ENET_PGBL_4xPGBL_32BEAT (DMA_BCTL_PGBL(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 32 */ +#define ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 64 */ +#define ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 128 */ + +#define DMA_BCTL_RTPR(regval) (BITS(14,15) & ((uint32_t)(regval) << 14U)) /*!< write value to ENET_DMA_BCTL_RTPR bit field */ +#define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0) /*!< receive and transmit priority ratio is 1:1*/ +#define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1) /*!< receive and transmit priority ratio is 2:1*/ +#define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2) /*!< receive and transmit priority ratio is 3:1 */ +#define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */ +#define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB /*!< RxDMA has higher priority than TxDMA */ + +#define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB /*!< AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers */ +#define ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000U) /*!< AHB can use SINGLE/INCR burst transfer operations */ + +#define DMA_BCTL_RXDP(regval) (BITS(17,22) & ((uint32_t)(regval) << 17U)) /*!< write value to ENET_DMA_BCTL_RXDP bit field */ +#define ENET_RXDP_1BEAT DMA_BCTL_RXDP(1) /*!< maximum number of beats 1 */ +#define ENET_RXDP_2BEAT DMA_BCTL_RXDP(2) /*!< maximum number of beats 2 */ +#define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4) /*!< maximum number of beats 4 */ +#define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8) /*!< maximum number of beats 8 */ +#define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16) /*!< maximum number of beats 16 */ +#define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */ +#define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 4 */ +#define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 8 */ +#define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 16 */ +#define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 32 */ +#define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 64 */ +#define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */ + +#define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP /*!< RxDMA uses the RXDP[5:0], while TxDMA uses the PGBL[5:0] */ +#define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000U) /*!< RxDMA/TxDMA uses PGBL[5:0] */ + +#define ENET_ADDRESS_ALIGN_ENABLE ENET_DMA_BCTL_AA /*!< enabled address-aligned */ +#define ENET_ADDRESS_ALIGN_DISABLE ((uint32_t)0x00000000U) /*!< disable address-aligned */ /* dma_stat register value */ -#define GET_DMA_STAT_RP(regval) GET_BITS((uint32_t)(regval),17,19) /*!< get value of ENET_DMA_STAT_RP bit field */ -#define ENET_RX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop rx command issued */ +#define GET_DMA_STAT_RP(regval) GET_BITS((uint32_t)(regval), 17U, 19U) /*!< get value of ENET_DMA_STAT_RP bit field */ +#define ENET_RX_STATE_STOPPED ((uint32_t)0x00000000U) /*!< reset or stop rx command issued */ #define ENET_RX_STATE_FETCHING BIT(17) /*!< fetching the Rx descriptor */ #define ENET_RX_STATE_WAITING (BIT(17)|BIT(18)) /*!< waiting for receive packet */ #define ENET_RX_STATE_SUSPENDED BIT(19) /*!< Rx descriptor unavailable */ #define ENET_RX_STATE_CLOSING (BIT(17)|BIT(19)) /*!< closing receive descriptor */ #define ENET_RX_STATE_QUEUING ENET_DMA_STAT_RP /*!< transferring the receive packet data from recevie buffer to host memory */ -#define GET_DMA_STAT_TP(regval) GET_BITS((uint32_t)(regval),20,22) /*!< get value of ENET_DMA_STAT_TP bit field */ -#define ENET_TX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop Tx Command issued */ +#define GET_DMA_STAT_TP(regval) GET_BITS((uint32_t)(regval), 20U, 22U) /*!< get value of ENET_DMA_STAT_TP bit field */ +#define ENET_TX_STATE_STOPPED ((uint32_t)0x00000000U) /*!< reset or stop Tx Command issued */ #define ENET_TX_STATE_FETCHING BIT(20) /*!< fetching the Tx descriptor */ #define ENET_TX_STATE_WAITING BIT(21) /*!< waiting for status */ #define ENET_TX_STATE_READING (BIT(20)|BIT(21)) /*!< reading the data from host memory buffer and queuing it to transmit buffer */ #define ENET_TX_STATE_SUSPENDED (BIT(21)|BIT(22)) /*!< Tx descriptor unavailabe or transmit buffer underflow */ #define ENET_TX_STATE_CLOSING ENET_DMA_STAT_TP /*!< closing Tx descriptor */ -#define GET_DMA_STAT_EB(regval) GET_BITS((uint32_t)(regval),23,25) /*!< get value of ENET_DMA_STAT_EB bit field */ +#define GET_DMA_STAT_EB(regval) GET_BITS((uint32_t)(regval), 23U, 25U) /*!< get value of ENET_DMA_STAT_EB bit field */ #define ENET_ERROR_TXDATA_TRANSFER BIT(23) /*!< error during data transfer by TxDMA or RxDMA */ #define ENET_ERROR_READ_TRANSFER BIT(24) /*!< error during write transfer or read transfer */ #define ENET_ERROR_DESC_ACCESS BIT(25) /*!< error during descriptor or buffer access */ /* dma_ctl register value */ -#define DMA_CTL_RTHC(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) /*!< write value to ENET_DMA_CTL_RTHC bit field */ +#define DMA_CTL_RTHC(regval) (BITS(3,4) & ((uint32_t)(regval) << 3U)) /*!< write value to ENET_DMA_CTL_RTHC bit field */ #define ENET_RX_THRESHOLD_64BYTES DMA_CTL_RTHC(0) /*!< threshold level is 64 Bytes */ #define ENET_RX_THRESHOLD_32BYTES DMA_CTL_RTHC(1) /*!< threshold level is 32 Bytes */ #define ENET_RX_THRESHOLD_96BYTES DMA_CTL_RTHC(2) /*!< threshold level is 96 Bytes */ #define ENET_RX_THRESHOLD_128BYTES DMA_CTL_RTHC(3) /*!< threshold level is 128 Bytes */ -#define DMA_CTL_TTHC(regval) (BITS(14,16) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_CTL_TTHC bit field */ +#define DMA_CTL_TTHC(regval) (BITS(14,16) & ((uint32_t)(regval) << 14U)) /*!< write value to ENET_DMA_CTL_TTHC bit field */ #define ENET_TX_THRESHOLD_64BYTES DMA_CTL_TTHC(0) /*!< threshold level is 64 Bytes */ #define ENET_TX_THRESHOLD_128BYTES DMA_CTL_TTHC(1) /*!< threshold level is 128 Bytes */ #define ENET_TX_THRESHOLD_192BYTES DMA_CTL_TTHC(2) /*!< threshold level is 192 Bytes */ @@ -1201,68 +1178,68 @@ typedef struct #define ENET_TX_THRESHOLD_16BYTES DMA_CTL_TTHC(7) /*!< threshold level is 16 Bytes */ #define ENET_TCPIP_CKSUMERROR_ACCEPT ENET_DMA_CTL_DTCERFD /*!< Rx frame with only payload error but no other errors will not be dropped */ -#define ENET_TCPIP_CKSUMERROR_DROP ((uint32_t)0x00000000) /*!< all error frames will be dropped when FERF = 0 */ +#define ENET_TCPIP_CKSUMERROR_DROP ((uint32_t)0x00000000U) /*!< all error frames will be dropped when FERF = 0 */ #define ENET_RX_MODE_STOREFORWARD ENET_DMA_CTL_RSFD /*!< RxFIFO operates in store-and-forward mode */ -#define ENET_RX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< RxFIFO operates in cut-through mode */ +#define ENET_RX_MODE_CUTTHROUGH ((uint32_t)0x00000000U) /*!< RxFIFO operates in cut-through mode */ -#define ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000) /*!< RxDMA flushes all frames */ +#define ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000U) /*!< RxDMA flushes all frames */ #define ENET_FLUSH_RXFRAME_DISABLE ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush any frames */ #define ENET_NO_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush frames function */ #define ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD /*!< TxFIFO operates in store-and-forward mode */ -#define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< TxFIFO operates in cut-through mode */ +#define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000U) /*!< TxFIFO operates in cut-through mode */ -#define ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF<<2) /*!< all frame received with error except runt error are forwarded to memory */ +#define ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF << 2U) /*!< all frame received with error except runt error are forwarded to memory */ #define ENET_FORWARD_ERRFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drop error frame */ -#define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF<<2) /*!< the function that all frame received with error except runt error are forwarded to memory */ +#define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF << 2U) /*!< the function that all frame received with error except runt error are forwarded to memory */ -#define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF<<2) /*!< forward undersized good frames */ -#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drops all frames whose length is less than 64 bytes */ -#define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF<<2) /*!< the function that forwarding undersized good frames */ +#define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF << 2U) /*!< forward undersized good frames */ +#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000U) /*!< RxFIFO drops all frames whose length is less than 64 bytes */ +#define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF << 2U) /*!< the function that forwarding undersized good frames */ -#define ENET_SECONDFRAME_OPT_ENABLE ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame mode enable*/ -#define ENET_SECONDFRAME_OPT_DISABLE ((uint32_t)0x00000000) /*!< TxDMA controller operate on second frame mode disable */ -#define ENET_SECONDFRAME_OPT ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame function */ +#define ENET_SECONDFRAME_OPT_ENABLE ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame mode enable*/ +#define ENET_SECONDFRAME_OPT_DISABLE ((uint32_t)0x00000000U) /*!< TxDMA controller operate on second frame mode disable */ +#define ENET_SECONDFRAME_OPT ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame function */ /* dma_mfbocnt register value */ -#define GET_DMA_MFBOCNT_MSFC(regval) GET_BITS((regval),0,15) /*!< get value of ENET_DMA_MFBOCNT_MSFC bit field */ +#define GET_DMA_MFBOCNT_MSFC(regval) GET_BITS((regval), 0U, 15U) /*!< get value of ENET_DMA_MFBOCNT_MSFC bit field */ -#define GET_DMA_MFBOCNT_MSFA(regval) GET_BITS((regval),17,27) /*!< get value of ENET_DMA_MFBOCNT_MSFA bit field */ +#define GET_DMA_MFBOCNT_MSFA(regval) GET_BITS((regval), 17U, 27U) /*!< get value of ENET_DMA_MFBOCNT_MSFA bit field */ /* dma tx descriptor tdes0 register value */ -#define TDES0_CONT(regval) (BITS(3,6) & ((uint32_t)(regval) << 3)) /*!< write value to ENET DMA TDES0 CONT bit field */ -#define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6) /*!< get value of ENET DMA TDES0 CONT bit field */ +#define TDES0_CONT(regval) (BITS(3,6) & ((uint32_t)(regval) << 3U)) /*!< write value to ENET DMA TDES0 CONT bit field */ +#define GET_TDES0_COCNT(regval) GET_BITS((regval), 3U, 6U) /*!< get value of ENET DMA TDES0 CONT bit field */ -#define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */ -#define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ -#define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ -#define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ -#define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ +#define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22U)) /*!< write value to ENET DMA TDES0 CM bit field */ +#define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ +#define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ +#define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ +#define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ /* dma tx descriptor tdes1 register value */ -#define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */ +#define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0U)) /*!< write value to ENET DMA TDES1 TB1S bit field */ -#define TDES1_TB2S(regval) (BITS(16,28) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA TDES1 TB2S bit field */ +#define TDES1_TB2S(regval) (BITS(16,28) & ((uint32_t)(regval) << 16U)) /*!< write value to ENET DMA TDES1 TB2S bit field */ /* dma rx descriptor rdes0 register value */ -#define RDES0_FRML(regval) (BITS(16,29) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA RDES0 FRML bit field */ -#define GET_RDES0_FRML(regval) GET_BITS((regval),16,29) /*!< get value of ENET DMA RDES0 FRML bit field */ +#define RDES0_FRML(regval) (BITS(16,29) & ((uint32_t)(regval) << 16U)) /*!< write value to ENET DMA RDES0 FRML bit field */ +#define GET_RDES0_FRML(regval) GET_BITS((regval), 16U, 29U) /*!< get value of ENET DMA RDES0 FRML bit field */ /* dma rx descriptor rdes1 register value */ -#define ENET_RECEIVE_COMPLETE_INT_ENABLE ((uint32_t)0x00000000U) /*!< RS bit immediately set after Rx completed */ -#define ENET_RECEIVE_COMPLETE_INT_DISABLE ENET_RDES1_DINTC /*!< RS bit not immediately set after Rx completed */ +#define ENET_RECEIVE_COMPLETE_INT_ENABLE ((uint32_t)0x00000000U) /*!< RS bit immediately set after Rx completed */ +#define ENET_RECEIVE_COMPLETE_INT_DISABLE ENET_RDES1_DINTC /*!< RS bit not immediately set after Rx completed */ -#define GET_RDES1_RB1S(regval) GET_BITS((regval),0,12) /*!< get value of ENET DMA RDES1 RB1S bit field */ +#define GET_RDES1_RB1S(regval) GET_BITS((regval), 0U, 12U) /*!< get value of ENET DMA RDES1 RB1S bit field */ -#define GET_RDES1_RB2S(regval) GET_BITS((regval),16,28) /*!< get value of ENET DMA RDES1 RB2S bit field */ +#define GET_RDES1_RB2S(regval) GET_BITS((regval), 16U, 28U) /*!< get value of ENET DMA RDES1 RB2S bit field */ /* dma rx descriptor rdes4 register value */ -#define RDES4_IPPLDT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA RDES4 IPPLDT bit field */ -#define GET_RDES4_IPPLDT(regval) GET_BITS((regval),0,2) /*!< get value of ENET DMA RDES4 IPPLDT bit field */ +#define RDES4_IPPLDT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U)) /*!< write value to ENET DMA RDES4 IPPLDT bit field */ +#define GET_RDES4_IPPLDT(regval) GET_BITS((regval),0,2) /*!< get value of ENET DMA RDES4 IPPLDT bit field */ -#define RDES4_PTPMT(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to ENET DMA RDES4 PTPMT bit field */ -#define GET_RDES4_PTPMT(regval) GET_BITS((regval),8,11) /*!< get value of ENET DMA RDES4 PTPMT bit field */ +#define RDES4_PTPMT(regval) (BITS(8,11) & ((uint32_t)(regval) << 8U)) /*!< write value to ENET DMA RDES4 PTPMT bit field */ +#define GET_RDES4_PTPMT(regval) GET_BITS((regval),8,11) /*!< get value of ENET DMA RDES4 PTPMT bit field */ /* ENET register mask value */ #define MAC_CFG_MASK ((uint32_t)0xFD30810FU) /*!< ENET_MAC_CFG register mask */ @@ -1270,23 +1247,23 @@ typedef struct #define DMA_CTL_MASK ((uint32_t)0xF8DE3F23U) /*!< ENET_DMA_CTL register mask */ #define DMA_BCTL_MASK ((uint32_t)0xF800007DU) /*!< ENET_DMA_BCTL register mask */ -#define ETH_DMATXDESC_SIZE 0x10U /*!< TxDMA descriptor size */ -#define ETH_DMARXDESC_SIZE 0x10U /*!< RxDMA descriptor size */ +#define ETH_DMATXDESC_SIZE 0x00000010U /*!< TxDMA descriptor size */ +#define ETH_DMARXDESC_SIZE 0x00000010U /*!< RxDMA descriptor size */ -typedef enum{ +typedef enum { ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI, /*!< timestamp initialize */ - ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */ + ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */ ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU, /*!< addend register update */ - ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU| BIT(31)), /*!< the system timestamp uses the fine method for updating */ + ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU | BIT(31)), /*!< the system timestamp uses the fine method for updating */ ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU, /*!< the system timestamp uses the coarse method for updating */ -}enet_ptp_function_enum; +} enet_ptp_function_enum; /* ENET remote wake-up frame register length */ #define ETH_WAKEUP_REGISTER_LENGTH 8U /*!< remote wake-up frame register length */ -/* ENET frame size */ -#define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */ +/* ENET frame size */ +#define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */ /* ENET delay timeout */ #define ENET_DELAY_TO ((uint32_t)0x0004FFFFU) /*!< ENET delay timeout */ @@ -1319,27 +1296,14 @@ ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length); /* configure the transmit IP frame checksum offload calculation and insertion */ void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum); /* ENET Tx and Rx function enable (include MAC and DMA module) */ -void enet_enable(void); +void enet_enable(void); /* ENET Tx and Rx function disable (include MAC and DMA module) */ void enet_disable(void); /* configure MAC address */ void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]); -/* get MAC address */ +/* get MAC address */ void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]); -/* get the ENET MAC/MSC/PTP/DMA status flag */ -FlagStatus enet_flag_get(enet_flag_enum enet_flag); -/* clear the ENET DMA status flag */ -void enet_flag_clear(enet_flag_clear_enum enet_flag); -/* enable ENET MAC/MSC/DMA interrupt */ -void enet_interrupt_enable(enet_int_enum enet_int); -/* disable ENET MAC/MSC/DMA interrupt */ -void enet_interrupt_disable(enet_int_enum enet_int); -/* get ENET MAC/MSC/DMA interrupt flag */ -FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag); -/* clear ENET DMA interrupt flag */ -void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear); - /* MAC function */ /* ENET Tx function enable (include MAC and DMA module) */ void enet_tx_enable(void); @@ -1392,7 +1356,7 @@ void enet_flowcontrol_feature_disable(uint32_t feature); /* DMA function */ /* get the dma transmit/receive process state */ -uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction); +uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction); /* poll the dma transmission/reception enable */ void enet_dmaprocess_resume(enet_dmadirection_enum direction); /* check and recover the Rx process */ @@ -1412,7 +1376,7 @@ FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) /* set the bit flag of ENET dma tx descriptor */ void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag); /* clear the bit flag of ENET dma tx descriptor */ -void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag); +void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag); /* when receiving the completed, set RS bit in ENET_DMA_STAT register will set */ void enet_desc_receive_complete_bit_enable(enet_descriptors_struct *desc); /* when receiving the completed, set RS bit in ENET_DMA_STAT register will not set */ @@ -1450,11 +1414,11 @@ void enet_wum_feature_disable(uint32_t feature); /* MSC function */ /* reset the MAC statistics counters */ void enet_msc_counters_reset(void); -/* enable the MAC statistics counter features */ +/* enable the MAC statistics counter features */ void enet_msc_feature_enable(uint32_t feature); -/* disable the MAC statistics counter features */ +/* disable the MAC statistics counter features */ void enet_msc_feature_disable(uint32_t feature); -/* get MAC statistics counter */ +/* get MAC statistics counter */ uint32_t enet_msc_counters_get(enet_msc_counter_enum counter); /* PTP function */ @@ -1485,7 +1449,7 @@ void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg); /* update system time in coarse method */ void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct); /* set system time in fine method */ -void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct); +void enet_ptp_finecorrection_settime(enet_ptp_systime_struct *systime_struct); /* get the ptp flag status */ FlagStatus enet_ptp_flag_get(uint32_t flag); @@ -1496,7 +1460,7 @@ void enet_initpara_reset(void); static void enet_default_init(void); #ifdef USE_DELAY /* user can provide more timing precise _ENET_DELAY_ function */ -#define _ENET_DELAY_ delay_ms +#define _ENET_DELAY_ delay_ms #else /* insert a delay time */ static void enet_delay(uint32_t ncount); @@ -1504,4 +1468,17 @@ static void enet_delay(uint32_t ncount); #define _ENET_DELAY_ enet_delay #endif +/* get the ENET MAC/MSC/PTP/DMA status flag */ +FlagStatus enet_flag_get(enet_flag_enum enet_flag); +/* clear the ENET DMA status flag */ +void enet_flag_clear(enet_flag_clear_enum enet_flag); +/* enable ENET MAC/MSC/DMA interrupt */ +void enet_interrupt_enable(enet_int_enum enet_int); +/* disable ENET MAC/MSC/DMA interrupt */ +void enet_interrupt_disable(enet_int_enum enet_int); +/* get ENET MAC/MSC/DMA interrupt flag */ +FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag); +/* clear ENET DMA interrupt flag */ +void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear); + #endif /* GD32F20X_ENET_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_exmc.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_exmc.h index 691e8351..0f05d115 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_exmc.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_exmc.h @@ -2,36 +2,33 @@ \file gd32f20x_exmc.h \brief definitions for the EXMC - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -42,66 +39,66 @@ OF SUCH DAMAGE. /* EXMC definitions */ #define EXMC (EXMC_BASE) /*!< EXMC register base address */ -#define EXMC_NOR_PSRAM (EXMC_BASE - 0x40000000) /*!< EXMC NOR/PSRAM base address */ -#define EXMC_NAND (EXMC_BASE - 0x30000000) /*!< EXMC NAND base address */ -#define EXMC_PCCARD (EXMC_BASE - 0x10000000) /*!< EXMC PC card base address */ -#define EXMC_SDRAM (EXMC_BASE + 0x20000000) /*!< EXMC SDRAM base address */ +#define EXMC_NOR_PSRAM (EXMC_BASE - 0x40000000U) /*!< EXMC NOR/PSRAM base address */ +#define EXMC_NAND (EXMC_BASE - 0x30000000U) /*!< EXMC NAND base address */ +#define EXMC_PCCARD (EXMC_BASE - 0x10000000U) /*!< EXMC PC card base address */ +#define EXMC_SDRAM (EXMC_BASE + 0x20000000U) /*!< EXMC SDRAM base address */ /* registers definitions */ /* NOR/PSRAM */ -#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register */ -#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register */ -#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register */ +#define EXMC_SNCTL0 REG32(EXMC + 0x00000000U) /*!< EXMC SRAM/NOR flash control register */ +#define EXMC_SNTCFG0 REG32(EXMC + 0x00000004U) /*!< EXMC SRAM/NOR flash timing configuration register */ +#define EXMC_SNWTCFG0 REG32(EXMC + 0x00000104U) /*!< EXMC SRAM/NOR flash write timing configuration register */ -#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register */ -#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register */ -#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register */ +#define EXMC_SNCTL1 REG32(EXMC + 0x00000008U) /*!< EXMC SRAM/NOR flash control register */ +#define EXMC_SNTCFG1 REG32(EXMC + 0x0000000CU) /*!< EXMC SRAM/NOR flash timing configuration register */ +#define EXMC_SNWTCFG1 REG32(EXMC + 0x0000010CU) /*!< EXMC SRAM/NOR flash write timing configuration register */ -#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register */ -#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register */ -#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register */ +#define EXMC_SNCTL2 REG32(EXMC + 0x00000010U) /*!< EXMC SRAM/NOR flash control register */ +#define EXMC_SNTCFG2 REG32(EXMC + 0x00000014U) /*!< EXMC SRAM/NOR flash timing configuration register */ +#define EXMC_SNWTCFG2 REG32(EXMC + 0x00000114U) /*!< EXMC SRAM/NOR flash write timing configuration register */ -#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register */ -#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register */ -#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register */ +#define EXMC_SNCTL3 REG32(EXMC + 0x00000018U) /*!< EXMC SRAM/NOR flash control register */ +#define EXMC_SNTCFG3 REG32(EXMC + 0x0000001CU) /*!< EXMC SRAM/NOR flash timing configuration register */ +#define EXMC_SNWTCFG3 REG32(EXMC + 0x0000011CU) /*!< EXMC SRAM/NOR flash write timing configuration register */ /* NAND/PC card */ -#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register */ -#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register */ -#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register */ -#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register */ -#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register */ - -#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register */ -#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register */ -#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register */ -#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register */ -#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register */ - -#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register */ -#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register */ -#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register */ -#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register */ -#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register */ +#define EXMC_NPCTL1 REG32(EXMC + 0x00000060U) /*!< EXMC NAND/PC card control register */ +#define EXMC_NPINTEN1 REG32(EXMC + 0x00000064U) /*!< EXMC NAND/PC card interrupt enable register */ +#define EXMC_NPCTCFG1 REG32(EXMC + 0x00000068U) /*!< EXMC NAND/PC card common space timing configuration register */ +#define EXMC_NPATCFG1 REG32(EXMC + 0x0000006CU) /*!< EXMC NAND/PC card attribute space timing configuration register */ +#define EXMC_NECC1 REG32(EXMC + 0x00000074U) /*!< EXMC NAND ECC register */ + +#define EXMC_NPCTL2 REG32(EXMC + 0x00000080U) /*!< EXMC NAND/PC card control register */ +#define EXMC_NPINTEN2 REG32(EXMC + 0x00000084U) /*!< EXMC NAND/PC card interrupt enable register */ +#define EXMC_NPCTCFG2 REG32(EXMC + 0x00000088U) /*!< EXMC NAND/PC card common space timing configuration register */ +#define EXMC_NPATCFG2 REG32(EXMC + 0x0000008CU) /*!< EXMC NAND/PC card attribute space timing configuration register */ +#define EXMC_NECC2 REG32(EXMC + 0x00000094U) /*!< EXMC NAND ECC register */ + +#define EXMC_NPCTL3 REG32(EXMC + 0x000000A0U) /*!< EXMC NAND/PC card control register */ +#define EXMC_NPINTEN3 REG32(EXMC + 0x000000A4U) /*!< EXMC NAND/PC card interrupt enable register */ +#define EXMC_NPCTCFG3 REG32(EXMC + 0x000000A8U) /*!< EXMC NAND/PC card common space timing configuration register */ +#define EXMC_NPATCFG3 REG32(EXMC + 0x000000ACU) /*!< EXMC NAND/PC card attribute space timing configuration register */ +#define EXMC_PIOTCFG3 REG32(EXMC + 0x000000B0U) /*!< EXMC PC card I/O space timing configuration register */ /* SDRAM */ -#define EXMC_SDCTL0 REG32(EXMC + 0x140U) /*!< EXMC SDRAM control register */ -#define EXMC_SDTCFG0 REG32(EXMC + 0x148U) /*!< EXMC SDRAM timing configuration register register */ +#define EXMC_SDCTL0 REG32(EXMC + 0x000000140U) /*!< EXMC SDRAM control register */ +#define EXMC_SDTCFG0 REG32(EXMC + 0x000000148U) /*!< EXMC SDRAM timing configuration register register */ -#define EXMC_SDCTL1 REG32(EXMC + 0x144U) /*!< EXMC SDRAM control register */ -#define EXMC_SDTCFG1 REG32(EXMC + 0x14CU) /*!< EXMC SDRAM timing configuration register register */ +#define EXMC_SDCTL1 REG32(EXMC + 0x00000144U) /*!< EXMC SDRAM control register */ +#define EXMC_SDTCFG1 REG32(EXMC + 0x0000014CU) /*!< EXMC SDRAM timing configuration register register */ -#define EXMC_SDCMD REG32(EXMC + 0x150U) /*!< EXMC SDRAM command register */ -#define EXMC_SDARI REG32(EXMC + 0x154U) /*!< EXMC SDRAM auto-refresh interval register */ -#define EXMC_SDSTAT REG32(EXMC + 0x158U) /*!< EXMC SDRAM status register */ -#define EXMC_SDRSCTL REG32(EXMC + 0x180U) /*!< EXMC SDRAM read sample control register */ +#define EXMC_SDCMD REG32(EXMC + 0x00000150U) /*!< EXMC SDRAM command register */ +#define EXMC_SDARI REG32(EXMC + 0x00000154U) /*!< EXMC SDRAM auto-refresh interval register */ +#define EXMC_SDSTAT REG32(EXMC + 0x00000158U) /*!< EXMC SDRAM status register */ +#define EXMC_SDRSCTL REG32(EXMC + 0x00000180U) /*!< EXMC SDRAM read sample control register */ /* SQPI PSRAM */ -#define EXMC_SINIT REG32(EXMC + 0x310U) /*!< EXMC SPI initialization register */ -#define EXMC_SRCMD REG32(EXMC + 0x320U) /*!< EXMC SPI read command register */ -#define EXMC_SWCMD REG32(EXMC + 0x330U) /*!< EXMC SPI write command register */ -#define EXMC_SIDL REG32(EXMC + 0x340U) /*!< EXMC SPI ID low register */ -#define EXMC_SIDH REG32(EXMC + 0x350U) /*!< EXMC SPI ID high register */ +#define EXMC_SINIT REG32(EXMC + 0x00000310U) /*!< EXMC SPI initialization register */ +#define EXMC_SRCMD REG32(EXMC + 0x00000320U) /*!< EXMC SPI read command register */ +#define EXMC_SWCMD REG32(EXMC + 0x00000330U) /*!< EXMC SPI write command register */ +#define EXMC_SIDL REG32(EXMC + 0x00000340U) /*!< EXMC SPI ID low register */ +#define EXMC_SIDH REG32(EXMC + 0x00000350U) /*!< EXMC SPI ID high register */ /* bits definitions */ /* NOR/PSRAM */ @@ -250,234 +247,227 @@ OF SUCH DAMAGE. /* constants definitions */ /* EXMC NOR/SRAM timing initialize structure */ -typedef struct -{ +typedef struct { uint32_t asyn_access_mode; /*!< asynchronous access mode */ - + uint32_t syn_data_latency; /*!< configure the data latency */ - /*!< the range is EXMC_DATALAT_2_CLK to EXMC_DATALAT_17_CLK */ - + /*!< the range is EXMC_DATALAT_2_CLK to EXMC_DATALAT_17_CLK */ + uint32_t syn_clk_division; /*!< configure the clock divide ratio */ - /*!< the range is EXMC_SYN_CLOCK_RATIO_2_CLK to EXMC_SYN_CLOCK_RATIO_16_CLK */ - + /*!< the range is EXMC_SYN_CLOCK_RATIO_2_CLK to EXMC_SYN_CLOCK_RATIO_16_CLK */ + uint32_t bus_latency; /*!< configure the bus latency */ - /*!< the range is 1 to 16 HCLK */ - + /*!< the range is 1 to 16 HCLK */ + uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ - /*!< the range is 2 to 256 HCLK */ - + /*!< the range is 2 to 256 HCLK */ + uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */ - /*!< the range is 2 to 16 HCLK */ - + /*!< the range is 2 to 16 HCLK */ + uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ - /*!< the range is 1 to 16 HCLK */ -}exmc_norsram_timing_parameter_struct; + /*!< the range is 1 to 16 HCLK */ +} exmc_norsram_timing_parameter_struct; /* EXMC NOR/SRAM initialize structure */ -typedef struct -{ +typedef struct { uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ - /*!< norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0..3 */ - + /*!< norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0..3 */ + uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */ - /*!< write_mode: EXMC_ASYN_WRITE or EXMC_SYN_WRITE */ - + /*!< write_mode: EXMC_ASYN_WRITE or EXMC_SYN_WRITE */ + uint32_t extended_mode; /*!< enable or disable the extended mode */ - /*!< extended_mode: ENABLE or DISABLE */ - + /*!< extended_mode: ENABLE or DISABLE */ + uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */ - /*!< asyn_wait: ENABLE or DISABLE */ - + /*!< asyn_wait: ENABLE or DISABLE */ + uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */ - /*!< nwait_signal: ENABLE or DISABLE */ - + /*!< nwait_signal: ENABLE or DISABLE */ + uint32_t memory_write; /*!< enable or disable the write operation */ - /*!< memory_write: ENABLE or DISABLE */ - + /*!< memory_write: ENABLE or DISABLE */ + uint32_t nwait_config; /*!< NWAIT signal configuration */ - /*!< nwait_config: EXMC_NWAIT_CONFIG_BEFORE or EXMC_NWAIT_CONFIG_DURING */ - + /*!< nwait_config: EXMC_NWAIT_CONFIG_BEFORE or EXMC_NWAIT_CONFIG_DURING */ + uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */ - /*!< wrap_burst_mode: ENABLE or DISABLE */ - + /*!< wrap_burst_mode: ENABLE or DISABLE */ + uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */ - /*!< nwait_polarity: EXMC_NWAIT_POLARITY_LOW or EXMC_NWAIT_POLARITY_HIGH */ - + /*!< nwait_polarity: EXMC_NWAIT_POLARITY_LOW or EXMC_NWAIT_POLARITY_HIGH */ + uint32_t burst_mode; /*!< enable or disable the burst mode */ - /*!< burst_mode: ENABLE or DISABLE */ - + /*!< burst_mode: ENABLE or DISABLE */ + uint32_t databus_width; /*!< specifies the databus width of external memory */ - /*!< databus_width: EXMC_NOR_DATABUS_WIDTH_8B or EXMC_NOR_DATABUS_WIDTH_16B */ - + /*!< databus_width: EXMC_NOR_DATABUS_WIDTH_8B or EXMC_NOR_DATABUS_WIDTH_16B */ + uint32_t memory_type; /*!< specifies the type of external memory */ - /*!< memory_type: EXMC_MEMORY_TYPE_SRAM / EXMC_MEMORY_TYPE_PSRAM / EXMC_MEMORY_TYPE_NOR */ - + /*!< memory_type: EXMC_MEMORY_TYPE_SRAM / EXMC_MEMORY_TYPE_PSRAM / EXMC_MEMORY_TYPE_NOR */ + uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ - /*!< address_data_mux: ENABLE or DISABLE */ - - exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extendedmode is not used or the timing + /*!< address_data_mux: ENABLE or DISABLE */ + + exmc_norsram_timing_parameter_struct + *read_write_timing; /*!< timing parameters for read and write if the extendedmode is not used or the timing parameters for read if the extendedmode is used. */ - - exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extendedmode is used. */ -}exmc_norsram_parameter_struct; + + exmc_norsram_timing_parameter_struct *write_timing; /*!< timing parameters for write when the extendedmode is used. */ +} exmc_norsram_parameter_struct; /* EXMC NAND/PC card timing initialize struct */ -typedef struct -{ - uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */ - /*!< the range is 1 to 256 HCLK */ - +typedef struct { + uint32_t databus_hiztime; /*!< configure the databus HiZ time for write operation */ + /*!< the range is 1 to 256 HCLK */ + uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */ - /*!< the range is 1 to 255 HCLK */ - + /*!< the range is 1 to 255 HCLK */ + uint32_t waittime; /*!< configure the minimum wait time */ - /*!< the range is 2 to 256 HCLK (+NWAIT active cycles) */ - + /*!< the range is 2 to 256 HCLK (+NWAIT active cycles) */ + uint32_t setuptime; /*!< configure the address setup time */ - /*!< the range is 1 to 256 HCLK */ -}exmc_nand_pccard_timing_parameter_struct; + /*!< the range is 1 to 256 HCLK */ +} exmc_nand_pccard_timing_parameter_struct; /* EXMC NAND initialize structure */ -typedef struct -{ +typedef struct { uint32_t nand_bank; /*!< select the bank of NAND */ - /*!< nand_bank: EXMC_BANK1_NAND or EXMC_BANK2_NAND */ - + /*!< nand_bank: EXMC_BANK1_NAND or EXMC_BANK2_NAND */ + uint32_t ecc_size; /*!< the page size for the ECC calculation */ - /*!< ecc_size: EXMC_ECC_SIZE_xBYTES,x=256,512,1024,2048,4096 */ - - uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ - /*!< atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 */ - + /*!< ecc_size: EXMC_ECC_SIZE_xBYTES,x=256,512,1024,2048,4096 */ + + uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ + /*!< atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 */ + uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ - /*!< ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 */ - + /*!< ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 */ + uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */ - /*!< ecc_logic: ENABLE or DISABLE */ - + /*!< ecc_logic: ENABLE or DISABLE */ + uint32_t databus_width; /*!< the NAND flash databus width */ - /*!< databus_width: EXMC_NAND_DATABUS_WIDTH_8B or EXMC_NAND_DATABUS_WIDTH_16B */ - - uint32_t wait_feature; /*!< enables or disables the wait feature */ - /*!< wait_feature: ENABLE or DISABLE */ - - exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash Common Space */ - - exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash Attribute Space */ -}exmc_nand_parameter_struct; + /*!< databus_width: EXMC_NAND_DATABUS_WIDTH_8B or EXMC_NAND_DATABUS_WIDTH_16B */ + + uint32_t wait_feature; /*!< enable or disable the wait feature */ + /*!< wait_feature: ENABLE or DISABLE */ + + exmc_nand_pccard_timing_parameter_struct *common_space_timing; /*!< the timing parameters for NAND flash common space */ + + exmc_nand_pccard_timing_parameter_struct *attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ +} exmc_nand_parameter_struct; /* EXMC PC card initialize structure */ -typedef struct -{ +typedef struct { uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ - /*!< atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 */ - + /*!< atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 */ + uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ - /*!< ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 */ - - uint32_t wait_feature; /*!< enables or disables the Wait feature */ - /*!< wait_feature: ENABLE or DISABLE */ - - exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash Common Space */ - - exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash Attribute Space */ - - exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for NAND flash IO Space */ -}exmc_pccard_parameter_struct; + /*!< ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 */ + + uint32_t wait_feature; /*!< enable or disable the wait feature */ + /*!< wait_feature: ENABLE or DISABLE */ + + exmc_nand_pccard_timing_parameter_struct *common_space_timing; /*!< the timing parameters for NAND flash common space */ + + exmc_nand_pccard_timing_parameter_struct *attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ + + exmc_nand_pccard_timing_parameter_struct *io_space_timing; /*!< the timing parameters for NAND flash IO Space */ +} exmc_pccard_parameter_struct; /* EXMC SDRAM timing initialize structure */ -typedef struct -{ +typedef struct { uint32_t row_to_column_delay; /*!< configure the row to column delay */ - /*!< the range is 1 to 16 cycles */ - + /*!< the range is 1 to 16 cycles */ + uint32_t row_precharge_delay; /*!< configure the row precharge delay */ - /*!< the range is 1 to 16 cycles */ - + /*!< the range is 1 to 16 cycles */ + uint32_t write_recovery_delay; /*!< configure the write recovery delay */ - /*!< the range is 1 to 16 cycles */ - - uint32_t auto_refresh_delay; /*!< configure the auto refresh delay */ - /*!< the range is 1 to 16 cycles */ - + /*!< the range is 1 to 16 cycles */ + + uint32_t auto_refresh_delay; /*!< configure the auto refresh delay */ + /*!< the range is 1 to 16 cycles */ + uint32_t row_address_select_delay; /*!< configure the row address select delay */ - /*!< the range is 1 to 16 cycles */ - + /*!< the range is 1 to 16 cycles */ + uint32_t exit_selfrefresh_delay; /*!< configure the exit self-refresh delay */ - /*!< the range is 1 to 16 cycles */ - + /*!< the range is 1 to 16 cycles */ + uint32_t load_mode_register_delay; /*!< configure the load mode register delay */ - /*!< the range is 1 to 16 cycles */ -}exmc_sdram_timing_parameter_struct; + /*!< the range is 1 to 16 cycles */ +} exmc_sdram_timing_parameter_struct; /* EXMC SDRAM initialize structure */ -typedef struct -{ +typedef struct { uint32_t sdram_device; /*!< device of SDRAM */ - /*!< sdram_device: EXMC_SDRAM_DEVICE0 or EXMC_SDRAM_DEVICE1 */ - + /*!< sdram_device: EXMC_SDRAM_DEVICE0 or EXMC_SDRAM_DEVICE1 */ + uint32_t pipeline_read_delay; /*!< the delay for reading data after CAS latency in HCLK clock cycles */ - /*!< pipeline_read_delay: EXMC_PIPELINE_DELAY_x_HCLK, x=0..2 */ - - uint32_t brust_read_switch; /*!< enable or disable the burst read */ - /*!< brust_read_switch: ENABLE or DISABLE */ - + /*!< pipeline_read_delay: EXMC_PIPELINE_DELAY_x_HCLK, x=0..2 */ + + uint32_t burst_read_switch; /*!< enable or disable the burst read */ + /*!< burst_read_switch: ENABLE or DISABLE */ + uint32_t sdclock_config; /*!< the SDCLK memory clock for both SDRAM banks */ - /*!< sdclock_config: EXMC_SDCLK_DISABLE,EXMC_SDCLK_PERIODS_2_HCLK,EXMC_SDCLK_PERIODS_3_HCLK */ - + /*!< sdclock_config: EXMC_SDCLK_DISABLE,EXMC_SDCLK_PERIODS_2_HCLK,EXMC_SDCLK_PERIODS_3_HCLK */ + uint32_t write_protection; /*!< enable or disable SDRAM bank write protection function */ - /*!< write_protection: ENABLE or DISABLE */ - + /*!< write_protection: ENABLE or DISABLE */ + uint32_t cas_latency; /*!< configure the SDRAM CAS latency */ - /*!< cas_latency: EXMC_CAS_LATENCY_x_SDCLK, x=1..3 */ - + /*!< cas_latency: EXMC_CAS_LATENCY_x_SDCLK, x=1..3 */ + uint32_t internal_bank_number; /*!< the number internal banks */ - /*!< internal_bank_number: EXMC_SDRAM_2_INTER_BANK or EXMC_SDRAM_4_INTER_BANK */ - + /*!< internal_bank_number: EXMC_SDRAM_2_INTER_BANK or EXMC_SDRAM_4_INTER_BANK */ + uint32_t data_width; /*!< the databus width of SDRAM memory */ - /*!< data_width: EXMC_SDRAM_DATABUS_WIDTH_8B,EXMC_SDRAM_DATABUS_WIDTH_16B,EXMC_SDRAM_DATABUS_WIDTH_32B */ - + /*!< data_width: EXMC_SDRAM_DATABUS_WIDTH_8B,EXMC_SDRAM_DATABUS_WIDTH_16B,EXMC_SDRAM_DATABUS_WIDTH_32B */ + uint32_t row_address_width; /*!< the bit width of a row address */ - /*!< row_address_width: EXMC_SDRAM_ROW_ADDRESS_x, x=11..13 */ - + /*!< row_address_width: EXMC_SDRAM_ROW_ADDRESS_x, x=11..13 */ + uint32_t column_address_width; /*!< the bit width of a column address */ - /*!< column_address_width: EXMC_SDRAM_COW_ADDRESS_x, x=8..11 */ - - exmc_sdram_timing_parameter_struct* timing; /*!< the timing parameters for write and read SDRAM */ -}exmc_sdram_parameter_struct; + /*!< column_address_width: EXMC_SDRAM_COW_ADDRESS_x, x=8..11 */ + + exmc_sdram_timing_parameter_struct *timing; /*!< the timing parameters for write and read SDRAM */ +} exmc_sdram_parameter_struct; /* EXMC SDRAM command initialize structure */ -typedef struct -{ +typedef struct { uint32_t mode_register_content; /*!< the SDRAM mode register content */ - /*!< mode_register_content: */ - + /*!< mode_register_content: */ + uint32_t auto_refresh_number; /*!< the number of successive auto-refresh cycles will be send when CMD = 011 */ - /*!< auto_refresh_number: EXMC_SDRAM_AUTO_REFLESH_x_SDCLK, x=1..15 */ - + /*!< auto_refresh_number: EXMC_SDRAM_AUTO_REFLESH_x_SDCLK, x=1..15 */ + uint32_t bank_select; /*!< the bank which command will be sent to */ - /*!< bank_select: EXMC_SDRAM_DEVICE0_SELECT, EXMC_SDRAM_DEVICE1_SELECT, EXMC_SDRAM_DEVICE0_1_SELECT */ - + /*!< bank_select: EXMC_SDRAM_DEVICE0_SELECT, EXMC_SDRAM_DEVICE1_SELECT, EXMC_SDRAM_DEVICE0_1_SELECT */ + uint32_t command; /*!< the commands that will be sent to SDRAM */ - /*!< command: EXMC_SDRAM_NORMAL_OPERATION, EXMC_SDRAM_CLOCK_ENABLE, EXMC_SDRAM_PRECHARGE_ALL, - EXMC_SDRAM_AUTO_REFRESH, EXMC_SDRAM_LOAD_MODE_REGISTER, EXMC_SDRAM_SELF_REFRESH, - EXMC_SDRAM_POWERDOWN_ENTRY */ -}exmc_sdram_command_parameter_struct; + /*!< command: EXMC_SDRAM_NORMAL_OPERATION, EXMC_SDRAM_CLOCK_ENABLE, EXMC_SDRAM_PRECHARGE_ALL, + EXMC_SDRAM_AUTO_REFRESH, EXMC_SDRAM_LOAD_MODE_REGISTER, EXMC_SDRAM_SELF_REFRESH, + EXMC_SDRAM_POWERDOWN_ENTRY */ +} exmc_sdram_command_parameter_struct; /* EXMC SQPISRAM initialize structure */ -typedef struct{ +typedef struct { uint32_t sample_polarity; /*!< read data sample polarity */ - /*!< sample_polarity: EXMC_SDRAM_SAMPLE_RISING_EDGE,EXMC_SDRAM_SAMPLE_FALLING_EDGE */ - + /*!< sample_polarity: EXMC_SDRAM_SAMPLE_RISING_EDGE,EXMC_SDRAM_SAMPLE_FALLING_EDGE */ + uint32_t id_length; /*!< SPI PSRAM ID length */ - /*!< id_length: EXMC_SQPIPSRAM_ID_LENGTH_xB,x=8,16,32,64 */ - + /*!< id_length: EXMC_SQPIPSRAM_ID_LENGTH_xB,x=8,16,32,64 */ + uint32_t address_bits; /*!< bit number of SPI PSRAM address phase */ - /*!< address_bits: EXMC_SQPIPSRAM_ADDR_LENGTH_xB,x=1..26 */ - + /*!< address_bits: EXMC_SQPIPSRAM_ADDR_LENGTH_xB,x=1..26 */ + uint32_t command_bits; /*!< bit number of SPI PSRAM command phase */ - /*!< command_bits: EXMC_SQPIPSRAM_COMMAND_LENGTH_xB,x=4,8,16 */ -}exmc_sqpipsram_parameter_struct; + /*!< command_bits: EXMC_SQPIPSRAM_COMMAND_LENGTH_xB,x=4,8,16 */ +} exmc_sqpipsram_parameter_struct; /* EXMC NOR/SRAM bank region definition */ #define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ @@ -548,21 +538,23 @@ typedef struct{ /* synchronous clock divide ratio */ #define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) -#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ +#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ +#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = HCLK/2 */ +#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = HCLK/3 */ +#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = HCLK/4 */ +#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = HCLK/5 */ +#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = HCLK/6 */ +#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = HCLK/7 */ +#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = HCLK/8 */ +#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = HCLK/9 */ +#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = HCLK/10 */ +#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = HCLK/11 */ +#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = HCLK/12 */ +#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = HCLK/13 */ +#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = HCLK/14 */ +#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = HCLK/15 */ +#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = HCLK/16 */ + /* EXMC NOR/SRAM write mode */ #define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */ #define EXMC_SYN_WRITE EXMC_SNCTL_SYNCWR /*!< synchronous write mode */ @@ -578,50 +570,50 @@ typedef struct{ /* NAND/PC card */ /* ECC size */ #define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) -#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* 256 bytes */ -#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* 512 bytes */ -#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* 1024 bytes */ -#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* 2048 bytes */ -#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* 4096 bytes */ -#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* 8192 bytes */ +#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /*!< ECC size is 256 bytes */ +#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /*!< ECC size is 512 bytes */ +#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /*!< ECC size is 1024 bytes */ +#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /*!< ECC size is 2048 bytes */ +#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /*!< ECC size is 4096 bytes */ +#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /*!< ECC size is 8192 bytes */ /* ALE to RE delay */ #define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13)) -#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */ -#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */ -#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */ -#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */ -#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */ -#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */ -#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */ -#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */ -#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */ -#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */ -#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */ -#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */ -#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */ -#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */ -#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */ -#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */ +#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /*!< ALE to RE delay = 1*HCLK */ +#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /*!< ALE to RE delay = 2*HCLK */ +#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /*!< ALE to RE delay = 3*HCLK */ +#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /*!< ALE to RE delay = 4*HCLK */ +#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /*!< ALE to RE delay = 5*HCLK */ +#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /*!< ALE to RE delay = 6*HCLK */ +#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /*!< ALE to RE delay = 7*HCLK */ +#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /*!< ALE to RE delay = 8*HCLK */ +#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /*!< ALE to RE delay = 9*HCLK */ +#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /*!< ALE to RE delay = 10*HCLK */ +#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /*!< ALE to RE delay = 11*HCLK */ +#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /*!< ALE to RE delay = 12*HCLK */ +#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /*!< ALE to RE delay = 13*HCLK */ +#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /*!< ALE to RE delay = 14*HCLK */ +#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /*!< ALE to RE delay = 15*HCLK */ +#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /*!< ALE to RE delay = 16*HCLK */ /* CLE to RE delay */ #define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9)) -#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */ -#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */ -#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */ -#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */ -#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */ -#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */ -#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */ -#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */ -#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */ -#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */ -#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */ -#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */ -#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */ -#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */ -#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */ -#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */ +#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /*!< CLE to RE delay = 1*HCLK */ +#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /*!< CLE to RE delay = 2*HCLK */ +#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /*!< CLE to RE delay = 3*HCLK */ +#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /*!< CLE to RE delay = 4*HCLK */ +#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /*!< CLE to RE delay = 5*HCLK */ +#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /*!< CLE to RE delay = 6*HCLK */ +#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /*!< CLE to RE delay = 7*HCLK */ +#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /*!< CLE to RE delay = 8*HCLK */ +#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /*!< CLE to RE delay = 9*HCLK */ +#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /*!< CLE to RE delay = 10*HCLK */ +#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /*!< CLE to RE delay = 11*HCLK */ +#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /*!< CLE to RE delay = 12*HCLK */ +#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /*!< CLE to RE delay = 13*HCLK */ +#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /*!< CLE to RE delay = 14*HCLK */ +#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /*!< CLE to RE delay = 15*HCLK */ +#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /*!< CLE to RE delay = 16*HCLK */ /* NAND bank memory data bus width */ #define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) @@ -713,7 +705,7 @@ typedef struct{ #define EXMC_SDRAM_14_DELAY_CELL SDRSCTL_SDSC(14) /*!< select the clock after 14 delay cell */ #define EXMC_SDRAM_15_DELAY_CELL SDRSCTL_SDSC(15) /*!< select the clock after 15 delay cell */ - /* EXMC SDRAM internal banks */ +/* EXMC SDRAM internal banks */ #define EXMC_SDRAM_2_INTER_BANK ((uint32_t)0x00000000U) /*!< 2 internal banks */ #define EXMC_SDRAM_4_INTER_BANK EXMC_SDCTL_NBK /*!< 4 internal banks */ @@ -821,57 +813,62 @@ typedef struct{ #define EXMC_SDRAM_INT_FLAG_REFRESH EXMC_SDARI_REIE /*!< interrupt refresh error enable */ /* function declarations */ -/* function configuration */ +/* NOR/SRAM */ /* deinitialize EXMC NOR/SRAM region */ void exmc_norsram_deinit(uint32_t exmc_norsram_region); -/* exmc_norsram_parameter_struct parameter initialize */ -void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); +/* initialize exmc_norsram_parameter_struct with the default values */ +void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct); /* initialize EXMC NOR/SRAM region */ -void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); -/* EXMC NOR/SRAM bank enable */ +void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct); +/* enable EXMC NOR/SRAM bank region */ void exmc_norsram_enable(uint32_t exmc_norsram_region); -/* EXMC NOR/SRAM bank disable */ +/* disable EXMC NOR/SRAM bank region */ void exmc_norsram_disable(uint32_t exmc_norsram_region); +/* NAND */ /* deinitialize EXMC NAND bank */ void exmc_nand_deinit(uint32_t exmc_nand_bank); -/* exmc_nand_init_struct parameter initialize */ -void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct); +/* initialize exmc_nand_parameter_struct with the default values */ +void exmc_nand_struct_para_init(exmc_nand_parameter_struct *exmc_nand_init_struct); /* initialize EXMC NAND bank */ -void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct); -/* EXMC NAND bank enable */ +void exmc_nand_init(exmc_nand_parameter_struct *exmc_nand_init_struct); +/* enable EXMC NAND bank */ void exmc_nand_enable(uint32_t exmc_nand_bank); -/* EXMC NAND bank disable */ +/* disable EXMC NAND bank */ void exmc_nand_disable(uint32_t exmc_nand_bank); /* enable or disable the EXMC NAND ECC function */ void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue); /* get the EXMC ECC value */ uint32_t exmc_ecc_get(uint32_t exmc_nand_bank); +/* PC card */ /* deinitialize EXMC PC card bank */ void exmc_pccard_deinit(void); +/* initialize exmc_pccard_parameter_struct with the default values */ +void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct); /* initialize EXMC PC card bank */ -void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); -/* exmc_pccard_parameter_struct parameter initialize */ -void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); -/* EXMC PC card bank enable */ +void exmc_pccard_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct); +/* enable EXMC PC card bank */ void exmc_pccard_enable(void); -/* EXMC PC card bank disable */ +/* disable EXMC PC card bank */ void exmc_pccard_disable(void); +/* SDRAM */ /* deinitialize EXMC SDRAM device */ void exmc_sdram_deinit(uint32_t exmc_sdram_device); +/* initialize exmc_sdram_init_struct with the default values */ +void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct *exmc_sdram_init_struct); /* initialize EXMC SDRAM device */ -void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); -/* exmc_sdram_parameter_struct parameter initialize */ -void exmc_sdram_parameter_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); +void exmc_sdram_init(exmc_sdram_parameter_struct *exmc_sdram_init_struct); +/* initialize exmc_sdram_command_parameter_struct with the default values */ +void exmc_sdram_struct_command_para_init(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct); /* configure the SDRAM memory command */ -void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_command_init_struct); +void exmc_sdram_command_config(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct); /* set auto-refresh interval */ void exmc_sdram_refresh_count_set(uint32_t exmc_count); /* set the number of successive auto-refresh command */ void exmc_sdram_autorefresh_number_set(uint32_t exmc_number); -/* config the write protection function */ +/* configure the write protection function */ void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue); /* get the status of SDRAM device0 or device1 */ uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device); @@ -882,12 +879,13 @@ void exmc_sdram_readsample_enable(void); /* disable read sample */ void exmc_sdram_readsample_disable(void); +/* SQPIPSARM */ /* deinitialize EXMC SQPIPSRAM */ void exmc_sqpipsram_deinit(void); +/* initialize exmc_sqpipsram_init_struct with the default values */ +void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct *exmc_sqpipsram_init_struct); /* initialize EXMC SQPIPSRAM */ -void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct); -/* exmc_sqpipsram_parameter_struct parameter initialize */ -void exmc_sqpipsram_parameter_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct); +void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct *exmc_sqpipsram_init_struct); /* set the read command */ void exmc_sqpipsram_read_command_set(uint32_t read_command_mode, uint32_t read_wait_cycle, uint32_t read_command_code); /* set the write command */ @@ -904,17 +902,17 @@ uint32_t exmc_sqpipsram_high_id_get(void); FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag); /* interrupt & flag functions */ -/* check EXMC flag is set or not */ +/* get EXMC flag status */ FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag); -/* clear EXMC flag */ +/* clear EXMC flag status */ void exmc_flag_clear(uint32_t bank, uint32_t flag); -/* check EXMC flag is set or not */ -FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt_source); -/* clear EXMC flag */ -void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt_source); /* enable EXMC interrupt */ -void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt_source); +void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt); /* disable EXMC interrupt */ -void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt_source); +void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt); +/* get EXMC interrupt flag */ +FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt); +/* clear EXMC interrupt flag */ +void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt); #endif /* GD32F20X_EXMC_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_exti.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_exti.h index 34ff3974..79c4f43b 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_exti.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_exti.h @@ -2,36 +2,33 @@ \file gd32f20x_exti.h \brief definitions for the EXTI - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -44,12 +41,12 @@ OF SUCH DAMAGE. #define EXTI EXTI_BASE /* registers definitions */ -#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */ -#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */ -#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */ -#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */ -#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */ -#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */ +#define EXTI_INTEN REG32(EXTI + 0x00000000U) /*!< interrupt enable register */ +#define EXTI_EVEN REG32(EXTI + 0x00000004U) /*!< event enable register */ +#define EXTI_RTEN REG32(EXTI + 0x00000008U) /*!< rising edge trigger enable register */ +#define EXTI_FTEN REG32(EXTI + 0x0000000CU) /*!< falling edge trigger enable register */ +#define EXTI_SWIEV REG32(EXTI + 0x00000010U) /*!< software interrupt event register */ +#define EXTI_PD REG32(EXTI + 0x00000014U) /*!< pending register */ /* bits definitions */ /* EXTI_INTEN */ @@ -163,31 +160,30 @@ OF SUCH DAMAGE. #define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */ /* EXTI_PD */ -#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ -#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ -#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ -#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ -#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ -#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ -#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ -#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ -#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ -#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ -#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ -#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ -#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ -#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ -#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ -#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ -#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ -#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ -#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ -#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ +#define EXTI_PD_PD0 BIT(0) /*!< interrupt pending status from line 0 */ +#define EXTI_PD_PD1 BIT(1) /*!< interrupt pending status from line 1 */ +#define EXTI_PD_PD2 BIT(2) /*!< interrupt pending status from line 2 */ +#define EXTI_PD_PD3 BIT(3) /*!< interrupt pending status from line 3 */ +#define EXTI_PD_PD4 BIT(4) /*!< interrupt pending status from line 4 */ +#define EXTI_PD_PD5 BIT(5) /*!< interrupt pending status from line 5 */ +#define EXTI_PD_PD6 BIT(6) /*!< interrupt pending status from line 6 */ +#define EXTI_PD_PD7 BIT(7) /*!< interrupt pending status from line 7 */ +#define EXTI_PD_PD8 BIT(8) /*!< interrupt pending status from line 8 */ +#define EXTI_PD_PD9 BIT(9) /*!< interrupt pending status from line 9 */ +#define EXTI_PD_PD10 BIT(10) /*!< interrupt pending status from line 10 */ +#define EXTI_PD_PD11 BIT(11) /*!< interrupt pending status from line 11 */ +#define EXTI_PD_PD12 BIT(12) /*!< interrupt pending status from line 12 */ +#define EXTI_PD_PD13 BIT(13) /*!< interrupt pending status from line 13 */ +#define EXTI_PD_PD14 BIT(14) /*!< interrupt pending status from line 14 */ +#define EXTI_PD_PD15 BIT(15) /*!< interrupt pending status from line 15 */ +#define EXTI_PD_PD16 BIT(16) /*!< interrupt pending status from line 16 */ +#define EXTI_PD_PD17 BIT(17) /*!< interrupt pending status from line 17 */ +#define EXTI_PD_PD18 BIT(18) /*!< interrupt pending status from line 18 */ +#define EXTI_PD_PD19 BIT(19) /*!< interrupt pending status from line 19 */ /* constants definitions */ /* EXTI line number */ -typedef enum -{ +typedef enum { EXTI_0 = BIT(0), /*!< EXTI line 0 */ EXTI_1 = BIT(1), /*!< EXTI line 1 */ EXTI_2 = BIT(2), /*!< EXTI line 2 */ @@ -207,52 +203,50 @@ typedef enum EXTI_16 = BIT(16), /*!< EXTI line 16 */ EXTI_17 = BIT(17), /*!< EXTI line 17 */ EXTI_18 = BIT(18), /*!< EXTI line 18 */ - EXTI_19 = BIT(19), /*!< EXTI line 19 */ -}exti_line_enum; + EXTI_19 = BIT(19) /*!< EXTI line 19 */ +} exti_line_enum; /* external interrupt and event */ -typedef enum -{ +typedef enum { EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ EXTI_EVENT /*!< EXTI event mode */ -}exti_mode_enum; +} exti_mode_enum; -/* interrupt trigger mode */ -typedef enum -{ +/* interrupt and event trigger mode */ +typedef enum { EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ - EXTI_TRIG_BOTH /*!< EXTI rising and falling edge trigger */ -}exti_trig_type_enum; + EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */ + EXTI_TRIG_NONE /*!< without rising edge or falling edge trigger */ +} exti_trig_type_enum; /* function declarations */ /* initialization, EXTI lines configuration functions */ /* deinitialize the EXTI */ void exti_deinit(void); -/* enable the configuration of EXTI initialize */ +/* initialize the EXTI line x */ void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); /* enable the interrupts from EXTI line x */ void exti_interrupt_enable(exti_line_enum linex); -/* enable the events from EXTI line x */ -void exti_event_enable(exti_line_enum linex); /* disable the interrupts from EXTI line x */ void exti_interrupt_disable(exti_line_enum linex); +/* enable the events from EXTI line x */ +void exti_event_enable(exti_line_enum linex); /* disable the events from EXTI line x */ void exti_event_disable(exti_line_enum linex); +/* enable the software interrupt event from EXTI line x */ +void exti_software_interrupt_enable(exti_line_enum linex); +/* disable the software interrupt event from EXTI line x */ +void exti_software_interrupt_disable(exti_line_enum linex); /* interrupt & flag functions */ -/* get EXTI lines pending flag */ +/* get EXTI line x interrupt pending flag */ FlagStatus exti_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ +/* clear EXTI line x interrupt pending flag */ void exti_flag_clear(exti_line_enum linex); -/* get EXTI lines flag when the interrupt flag is set */ +/* get EXTI line x interrupt pending flag */ FlagStatus exti_interrupt_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ +/* clear EXTI line x interrupt pending flag */ void exti_interrupt_flag_clear(exti_line_enum linex); -/* enable the EXTI software interrupt event */ -void exti_software_interrupt_enable(exti_line_enum linex); -/* disable the EXTI software interrupt event */ -void exti_software_interrupt_disable(exti_line_enum linex); #endif /* GD32F20X_EXTI_H */ - diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_fmc.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_fmc.h index f070ffe1..585ed656 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_fmc.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_fmc.h @@ -2,36 +2,33 @@ \file gd32f20x_fmc.h \brief definitions for the FMC - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -45,27 +42,27 @@ OF SUCH DAMAGE. #define OB OB_BASE /*!< option bytes base address */ /* registers definitions */ -#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ -#define FMC_KEY0 REG32((FMC) + 0x04U) /*!< FMC unlock key register 0 */ -#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */ -#define FMC_STAT0 REG32((FMC) + 0x0CU) /*!< FMC status register 0 */ -#define FMC_CTL0 REG32((FMC) + 0x10U) /*!< FMC control register 0 */ -#define FMC_ADDR0 REG32((FMC) + 0x14U) /*!< FMC address register 0 */ -#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */ -#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */ -#define FMC_KEY1 REG32((FMC) + 0x44U) /*!< FMC unlock key register 1 */ -#define FMC_STAT1 REG32((FMC) + 0x4CU) /*!< FMC status register 1 */ -#define FMC_CTL1 REG32((FMC) + 0x50U) /*!< FMC control register 1 */ -#define FMC_ADDR1 REG32((FMC) + 0x54U) /*!< FMC address register 1 */ -#define FMC_WSEN REG32((FMC) + 0xFCU) /*!< FMC wait state enable register */ -#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ - -#define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */ -#define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/ -#define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */ -#define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */ -#define OB_WP2 REG16((OB) + 0x0CU) /*!< option byte write protection 2 */ -#define OB_WP3 REG16((OB) + 0x0EU) /*!< option byte write protection 3 */ +#define FMC_WS REG32((FMC) + 0x00000000U) /*!< FMC wait state register */ +#define FMC_KEY0 REG32((FMC) + 0x00000004U) /*!< FMC unlock key register 0 */ +#define FMC_OBKEY REG32((FMC) + 0x00000008U) /*!< FMC option bytes unlock key register */ +#define FMC_STAT0 REG32((FMC) + 0x0000000CU) /*!< FMC status register 0 */ +#define FMC_CTL0 REG32((FMC) + 0x00000010U) /*!< FMC control register 0 */ +#define FMC_ADDR0 REG32((FMC) + 0x00000014U) /*!< FMC address register 0 */ +#define FMC_OBSTAT REG32((FMC) + 0x0000001CU) /*!< FMC option bytes status register */ +#define FMC_WP REG32((FMC) + 0x00000020U) /*!< FMC erase/program protection register */ +#define FMC_KEY1 REG32((FMC) + 0x00000044U) /*!< FMC unlock key register 1 */ +#define FMC_STAT1 REG32((FMC) + 0x0000004CU) /*!< FMC status register 1 */ +#define FMC_CTL1 REG32((FMC) + 0x00000050U) /*!< FMC control register 1 */ +#define FMC_ADDR1 REG32((FMC) + 0x00000054U) /*!< FMC address register 1 */ +#define FMC_WSEN REG32((FMC) + 0x000000FCU) /*!< FMC wait state enable register */ +#define FMC_PID REG32((FMC) + 0x00000100U) /*!< FMC product ID register */ + +#define OB_SPC REG16((OB) + 0x0000U) /*!< option byte security protection value */ +#define OB_USER REG16((OB) + 0x0002U) /*!< option byte user value*/ +#define OB_WP0 REG16((OB) + 0x0008U) /*!< option byte write protection 0 */ +#define OB_WP1 REG16((OB) + 0x000AU) /*!< option byte write protection 1 */ +#define OB_WP2 REG16((OB) + 0x000CU) /*!< option byte write protection 2 */ +#define OB_WP3 REG16((OB) + 0x000EU) /*!< option byte write protection 3 */ /* bits definitions */ /* FMC_WS */ @@ -96,7 +93,7 @@ OF SUCH DAMAGE. #define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ /* FMC_ADDR0 */ -#define FMC_ADDR0_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ +#define FMC_ADDR0_ADDR BITS(0,31) /*!< flash erase/program command address bits */ /* FMC_OBSTAT */ #define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ @@ -126,7 +123,7 @@ OF SUCH DAMAGE. #define FMC_CTL1_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ /* FMC_ADDR1 */ -#define FMC_ADDR1_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ +#define FMC_ADDR1_ADDR BITS(0,31) /*!< flash erase/program command address bits */ /* FMC_WSEN */ #define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ @@ -146,34 +143,31 @@ OF SUCH DAMAGE. #define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12) /* configuration register */ -#define FMC_STAT0_REG_OFFSET 0x0CU /*!< status register 0 offset */ -#define FMC_CTL0_REG_OFFSET 0x10U /*!< control register 0 offset */ -#define FMC_STAT1_REG_OFFSET 0x4CU /*!< status register 1 offset */ -#define FMC_CTL1_REG_OFFSET 0x50U /*!< control register 1 offset */ -#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */ +#define FMC_STAT0_REG_OFFSET ((uint32_t)0x0000000CU) /*!< status register 0 offset */ +#define FMC_CTL0_REG_OFFSET ((uint32_t)0x00000010U) /*!< control register 0 offset */ +#define FMC_STAT1_REG_OFFSET ((uint32_t)0x0000004CU) /*!< status register 1 offset */ +#define FMC_CTL1_REG_OFFSET ((uint32_t)0x00000050U) /*!< control register 1 offset */ +#define FMC_OBSTAT_REG_OFFSET ((uint32_t)0x0000001CU) /*!< option byte status register offset */ /* fmc state */ -typedef enum -{ - FMC_READY, /*!< the operation has been completed */ - FMC_BUSY, /*!< the operation is in progress */ - FMC_PGERR, /*!< program error */ - FMC_WPERR, /*!< erase/program protection error */ - FMC_TOERR, /*!< timeout error */ -}fmc_state_enum; - -/* FMC interrupt enable */ -typedef enum -{ - FMC_INT_BANK0_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */ - FMC_INT_BANK0_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */ - FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), /*!< enable FMC bank1 end of program interrupt */ - FMC_INT_BANK1_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U), /*!< enable FMC bank1 error interrupt */ -}fmc_int_enum; +typedef enum { + FMC_READY = 0, /*!< the operation has been completed */ + FMC_BUSY, /*!< the operation is in progress */ + FMC_PGERR, /*!< program error */ + FMC_WPERR, /*!< erase/program protection error */ + FMC_TOERR /*!< timeout error */ +} fmc_state_enum; + +/* FMC interrupt */ +typedef enum { + FMC_INT_BANK0_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< FMC bank0 end of program interrupt */ + FMC_INT_BANK0_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< FMC bank0 error interrupt */ + FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), /*!< FMC bank1 end of program interrupt */ + FMC_INT_BANK1_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U) /*!< FMC bank1 error interrupt */ +} fmc_interrupt_enum; /* FMC flags */ -typedef enum -{ +typedef enum { FMC_FLAG_BANK0_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC bank0 busy flag */ FMC_FLAG_BANK0_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC bank0 operation error flag bit */ FMC_FLAG_BANK0_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC bank0 erase/program protection error flag bit */ @@ -182,114 +176,114 @@ typedef enum FMC_FLAG_BANK1_BUSY = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 0U), /*!< FMC bank1 busy flag */ FMC_FLAG_BANK1_PGERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U), /*!< FMC bank1 operation error flag bit */ FMC_FLAG_BANK1_WPERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U), /*!< FMC bank1 erase/program protection error flag bit */ - FMC_FLAG_BANK1_END = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U), /*!< FMC bank1 end of operation flag bit */ -}fmc_flag_enum; + FMC_FLAG_BANK1_END = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U) /*!< FMC bank1 end of operation flag bit */ +} fmc_flag_enum; /* FMC interrupt flags */ -typedef enum -{ +typedef enum { FMC_INT_FLAG_BANK0_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC bank0 operation error interrupt flag bit */ FMC_INT_FLAG_BANK0_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC bank0 erase/program protection error interrupt flag bit */ FMC_INT_FLAG_BANK0_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC bank0 end of operation interrupt flag bit */ FMC_INT_FLAG_BANK1_PGERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 2U, 10U), /*!< FMC bank1 operation error interrupt flag bit */ FMC_INT_FLAG_BANK1_WPERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 4U, 10U), /*!< FMC bank1 erase/program protection error interrupt flag bit */ - FMC_INT_FLAG_BANK1_END = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U), /*!< FMC bank1 end of operation interrupt flag bit */ -}fmc_interrupt_flag_enum; + FMC_INT_FLAG_BANK1_END = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U) /*!< FMC bank1 end of operation interrupt flag bit */ +} fmc_interrupt_flag_enum; /* unlock key */ -#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ -#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ +#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ +#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ /* FMC wait state counter */ #define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) -#define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */ -#define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ -#define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ +#define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */ +#define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ +#define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ -/* option bytes software/hardware free watch dog timer */ -#define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */ -#define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */ +/* option bytes software/hardware free watch dog timer */ +#define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */ +#define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */ /* option bytes reset or not entering deep sleep mode */ -#define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */ -#define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */ +#define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */ +#define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */ /* option bytes reset or not entering standby mode */ -#define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */ -#define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */ +#define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */ +#define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */ /* option bytes boot bank value */ -#define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */ -#define OB_BOOT_B1 ((uint8_t)0x00U) /*!< boot from bank1 */ +#define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */ +#define OB_BOOT_B1 ((uint8_t)0x00U) /*!< boot from bank1 */ -#define OB_USER_MASK ((uint8_t)0xF0U) /*!< MASK value */ +#define OB_USER_MASK ((uint8_t)0xF0U) /*!< mask value */ /* read protect configure */ -#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */ -#define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */ +#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */ +#define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */ /* OB_SPC */ -#define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */ -#define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */ +#define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */ +#define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */ /* OB_USER */ -#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */ -#define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */ +#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */ +#define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */ /* OB_WP0 */ -#define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */ +#define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */ /* OB_WP1 */ -#define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */ +#define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */ /* OB_WP2 */ -#define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */ +#define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */ /* OB_WP3 */ -#define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */ +#define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */ /* option bytes write protection */ -#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */ -#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */ -#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */ -#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */ -#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */ -#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */ -#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */ -#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */ -#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */ -#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ -#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ -#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ -#define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */ -#define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */ -#define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */ -#define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */ -#define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */ -#define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */ -#define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */ -#define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */ -#define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */ -#define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */ -#define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */ -#define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */ -#define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */ -#define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */ -#define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */ -#define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */ -#define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */ -#define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */ -#define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */ -#define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */ -#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */ +#define OB_WP_NONE ((uint32_t)0x00000000U) /*!< disable all erase/program protection */ +#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */ +#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */ +#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */ +#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */ +#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */ +#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */ +#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */ +#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */ +#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */ +#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ +#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ +#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ +#define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */ +#define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */ +#define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */ +#define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */ +#define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */ +#define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */ +#define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */ +#define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */ +#define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */ +#define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */ +#define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */ +#define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */ +#define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */ +#define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */ +#define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */ +#define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */ +#define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */ +#define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */ +#define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */ +#define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */ +#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */ /* FMC timeout */ -#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */ +#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */ /* FMC BANK address */ -#define FMC_BANK0_END_ADDRESS ((uint32_t)0x0807FFFFU) /*!< FMC bank0 end address */ -#define FMC_BANK0_SIZE ((uint32_t)0x00000200U) /*!< FMC bank0 size */ -#define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */ +#define FMC_BANK0_END_ADDRESS ((uint32_t)0x0807FFFFU) /*!< FMC bank0 end address */ +#define FMC_BANK0_SIZE ((uint32_t)0x00000200U) /*!< FMC bank0 size */ +#define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */ /* function declarations */ /* FMC main memory programming functions */ @@ -307,17 +301,17 @@ void fmc_lock(void); void fmc_bank0_lock(void); /* lock the bank1 FMC operation */ void fmc_bank1_lock(void); -/* FMC erase page */ +/* erase page */ fmc_state_enum fmc_page_erase(uint32_t page_address); -/* FMC erase whole chip */ +/* erase whole chip */ fmc_state_enum fmc_mass_erase(void); -/* FMC erase whole bank0 */ +/* erase whole bank0 */ fmc_state_enum fmc_bank0_erase(void); -/* FMC erase whole bank1 */ +/* erase whole bank1 */ fmc_state_enum fmc_bank1_erase(void); -/* FMC program a word at the corresponding address */ +/* program a word at the corresponding address */ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); -/* FMC program a half word at the corresponding address */ +/* program a half word at the corresponding address */ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); /* FMC option bytes programming functions */ @@ -327,17 +321,17 @@ void ob_unlock(void); void ob_lock(void); /* erase the option byte */ fmc_state_enum ob_erase(void); -/* enable write protect */ +/* enable write protection */ fmc_state_enum ob_write_protection_enable(uint32_t ob_wp); /* configure the option byte security protection */ fmc_state_enum ob_security_protection_config(uint8_t ob_spc); -/* write the FMC option byte */ +/* program option bytes user */ fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot); /* program option bytes data */ fmc_state_enum ob_data_program(uint32_t address, uint8_t data); -/* get the FMC option byte user */ +/* get the FMC option bytes user */ uint8_t ob_user_get(void); -/* get OB_DATA in register FMC_OBSTAT */ +/* get the FMC option bytes data */ uint16_t ob_data_get(void); /* get the FMC option byte write protection */ uint32_t ob_write_protection_get(void); @@ -345,25 +339,17 @@ uint32_t ob_write_protection_get(void); FlagStatus ob_spc_get(void); /* FMC interrupts and flags management functions */ -/* enable FMC interrupt */ -void fmc_interrupt_enable(uint32_t interrupt); -/* disable FMC interrupt */ -void fmc_interrupt_disable(uint32_t interrupt); /* check flag is set or not */ FlagStatus fmc_flag_get(uint32_t flag); /* clear the FMC flag */ void fmc_flag_clear(uint32_t flag); +/* enable FMC interrupt */ +void fmc_interrupt_enable(fmc_interrupt_enum interrupt); +/* disable FMC interrupt */ +void fmc_interrupt_disable(fmc_interrupt_enum interrupt); /* get FMC interrupt flag state */ -FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag); +FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum int_flag); /* clear FMC interrupt flag state */ -void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag); -/* return the FMC bank0 state */ -fmc_state_enum fmc_bank0_state_get(void); -/* return the FMC bank1 state */ -fmc_state_enum fmc_bank1_state_get(void); -/* check FMC bank0 ready or not */ -fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout); -/* check FMC bank1 ready or not */ -fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout); +void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum int_flag); #endif /* GD32F20X_FMC_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_fwdgt.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_fwdgt.h index 1cc6c00f..b5f4b1e6 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_fwdgt.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_fwdgt.h @@ -2,36 +2,33 @@ \file gd32f20x_fwdgt.h \brief definitions for the FWDGT - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -88,12 +85,10 @@ OF SUCH DAMAGE. #define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ #define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ -#ifdef __cplusplus - extern "C" { -#endif +/* write value to FWDGT_RLD_RLD bit field */ +#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /* function declarations */ -/* function configuration */ /* enable write access to FWDGT_PSC and FWDGT_RLD */ void fwdgt_write_enable(void); /* disable write access to FWDGT_PSC and FWDGT_RLD */ @@ -101,16 +96,16 @@ void fwdgt_write_disable(void); /* start the free watchdog timer counter */ void fwdgt_enable(void); +/* configure the free watchdog timer counter prescaler value */ +ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value); +/* configure the free watchdog timer counter reload value */ +ErrStatus fwdgt_reload_value_config(uint16_t reload_value); /* reload the counter of FWDGT */ void fwdgt_counter_reload(void); /* configure counter reload value, and prescaler divider value */ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); -/* interrupt & flag functions */ /* get flag state of FWDGT */ FlagStatus fwdgt_flag_get(uint16_t flag); -#ifdef __cplusplus -} -#endif #endif /* GD32F20X_FWDGT_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_gpio.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_gpio.h index dc249900..5b6f8f05 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_gpio.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_gpio.h @@ -2,36 +2,33 @@ \file gd32f20x_gpio.h \brief definitions for the GPIO - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -41,45 +38,45 @@ OF SUCH DAMAGE. #include "gd32f20x.h" /* GPIOx(x=A,B,C,D,E,F,G,H,I) definitions */ -#define GPIOA (GPIO_BASE + 0x00000000U) -#define GPIOB (GPIO_BASE + 0x00000400U) -#define GPIOC (GPIO_BASE + 0x00000800U) -#define GPIOD (GPIO_BASE + 0x00000C00U) -#define GPIOE (GPIO_BASE + 0x00001000U) -#define GPIOF (GPIO_BASE + 0x00001400U) -#define GPIOG (GPIO_BASE + 0x00001800U) -#define GPIOH (GPIO_BASE + 0x00006C00U) -#define GPIOI (GPIO_BASE + 0x00007000U) +#define GPIOA (GPIO_BASE + 0x00000000U) /*!< GPIOA bsae address */ +#define GPIOB (GPIO_BASE + 0x00000400U) /*!< GPIOB bsae address */ +#define GPIOC (GPIO_BASE + 0x00000800U) /*!< GPIOC bsae address */ +#define GPIOD (GPIO_BASE + 0x00000C00U) /*!< GPIOD bsae address */ +#define GPIOE (GPIO_BASE + 0x00001000U) /*!< GPIOE bsae address */ +#define GPIOF (GPIO_BASE + 0x00001400U) /*!< GPIOF bsae address */ +#define GPIOG (GPIO_BASE + 0x00001800U) /*!< GPIOG bsae address */ +#define GPIOH (GPIO_BASE + 0x00006C00U) /*!< GPIOH bsae address */ +#define GPIOI (GPIO_BASE + 0x00007000U) /*!< GPIOI bsae address */ /* AFIO definitions */ -#define AFIO AFIO_BASE +#define AFIO AFIO_BASE /*!< AFIO bsae address */ /* registers definitions */ /* GPIO registers definitions */ -#define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register 0 */ -#define GPIO_CTL1(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port control register 1 */ -#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port input status register */ -#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port output control register */ -#define GPIO_BOP(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port bit operation register */ -#define GPIO_BC(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO bit clear register */ -#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port configuration lock register */ +#define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00000000U) /*!< GPIO port control register 0 */ +#define GPIO_CTL1(gpiox) REG32((gpiox) + 0x00000004U) /*!< GPIO port control register 1 */ +#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x00000008U) /*!< GPIO port input status register */ +#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0000000CU) /*!< GPIO port output control register */ +#define GPIO_BOP(gpiox) REG32((gpiox) + 0x00000010U) /*!< GPIO port bit operation register */ +#define GPIO_BC(gpiox) REG32((gpiox) + 0x00000014U) /*!< GPIO bit clear register */ +#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x00000018U) /*!< GPIO port configuration lock register */ /* AFIO registers definitions */ -#define AFIO_EC REG32(AFIO + 0x00U) /*!< AFIO event control register */ -#define AFIO_PCF0 REG32(AFIO + 0x04U) /*!< AFIO port configuration register 0 */ -#define AFIO_EXTISS0 REG32(AFIO + 0x08U) /*!< AFIO port EXTI sources selection register 0 */ -#define AFIO_EXTISS1 REG32(AFIO + 0x0CU) /*!< AFIO port EXTI sources selection register 1 */ -#define AFIO_EXTISS2 REG32(AFIO + 0x10U) /*!< AFIO port EXTI sources selection register 2 */ -#define AFIO_EXTISS3 REG32(AFIO + 0x14U) /*!< AFIO port EXTI sources selection register 3 */ -#define AFIO_PCF1 REG32(AFIO + 0x1CU) /*!< AFIO port configuration register 1 */ -#define AFIO_PCF2 REG32(AFIO + 0x3CU) /*!< AFIO port configuration register 2 */ -#define AFIO_PCF3 REG32(AFIO + 0x40U) /*!< AFIO port configuration register 3 */ -#define AFIO_PCF4 REG32(AFIO + 0x44U) /*!< AFIO port configuration register 4 */ -#define AFIO_PCF5 REG32(AFIO + 0x48U) /*!< AFIO port configuration register 5 */ +#define AFIO_EC REG32(AFIO + 0x00000000U) /*!< AFIO event control register */ +#define AFIO_PCF0 REG32(AFIO + 0x00000004U) /*!< AFIO port configuration register 0 */ +#define AFIO_EXTISS0 REG32(AFIO + 0x00000008U) /*!< AFIO port EXTI sources selection register 0 */ +#define AFIO_EXTISS1 REG32(AFIO + 0x0000000CU) /*!< AFIO port EXTI sources selection register 1 */ +#define AFIO_EXTISS2 REG32(AFIO + 0x00000010U) /*!< AFIO port EXTI sources selection register 2 */ +#define AFIO_EXTISS3 REG32(AFIO + 0x00000014U) /*!< AFIO port EXTI sources selection register 3 */ +#define AFIO_PCF1 REG32(AFIO + 0x0000001CU) /*!< AFIO port configuration register 1 */ +#define AFIO_PCF2 REG32(AFIO + 0x0000003CU) /*!< AFIO port configuration register 2 */ +#define AFIO_PCF3 REG32(AFIO + 0x00000040U) /*!< AFIO port configuration register 3 */ +#define AFIO_PCF4 REG32(AFIO + 0x00000044U) /*!< AFIO port configuration register 4 */ +#define AFIO_PCF5 REG32(AFIO + 0x00000048U) /*!< AFIO port configuration register 5 */ /* bits definitions */ /* GPIO_CTL0 */ -#define GPIO_CTL0_MD0 BITS(0,1) /*!< port 0 mode bits */ +#define GPIO_CTL0_MD0 BITS(0,1) /*!< port 0 mode bits */ #define GPIO_CTL0_CTL0 BITS(2,3) /*!< pin 0 configuration bits */ #define GPIO_CTL0_MD1 BITS(4,5) /*!< port 1 mode bits */ #define GPIO_CTL0_CTL1 BITS(6,7) /*!< pin 1 configuration bits */ @@ -97,7 +94,7 @@ OF SUCH DAMAGE. #define GPIO_CTL0_CTL7 BITS(30,31) /*!< pin 7 configuration bits */ /* GPIO_CTL1 */ -#define GPIO_CTL1_MD8 BITS(0,1) /*!< port 8 mode bits */ +#define GPIO_CTL1_MD8 BITS(0,1) /*!< port 8 mode bits */ #define GPIO_CTL1_CTL8 BITS(2,3) /*!< pin 8 configuration bits */ #define GPIO_CTL1_MD9 BITS(4,5) /*!< port 9 mode bits */ #define GPIO_CTL1_CTL9 BITS(6,7) /*!< pin 9 configuration bits */ @@ -636,7 +633,7 @@ typedef FlagStatus bit_status; #define GPIO_PCF5_SPI1_NSCK_REMAP0 ((uint32_t)0x00000400U) /*!< SPI1 NSS/SCK remapping 0 */ #define GPIO_PCF5_SPI1_NSCK_REMAP1 ((uint32_t)0x00000600U) /*!< SPI1 NSS/SCK remapping 1 */ #define GPIO_PCF5_SPI1_IO_REMAP0 ((uint32_t)0x00000800U) /*!< SPI1 MISO/MOSI remapping 0 */ -#define GPIO_PCF5_SPI1_IO_REMAP1 ((uint32_t)0x00001800U) /*!< SPI1 MISO/MOSI remapping 1 */ +#define GPIO_PCF5_SPI1_IO_REMAP1 ((uint32_t)0x00001000U) /*!< SPI1 MISO/MOSI remapping 1 */ #define GPIO_PCF5_UART3_REMAP ((uint32_t)0x00002000U) /*!< UART3 remapping */ #define GPIO_PCF5_TIMER11_REMAP ((uint32_t)0x00004000U) /*!< TIMER11 remapping */ #define GPIO_PCF5_CAN0_ADD_REMAP ((uint32_t)0x00008000U) /*!< CAN0 addition remapping */ @@ -677,9 +674,9 @@ void gpio_afio_deinit(void); void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin); /* function configuration */ -/* set GPIO pin bit */ +/* set GPIO pin */ void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); -/* reset GPIO pin bit */ +/* reset GPIO pin */ void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); /* write data to the specified GPIO pin */ void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); @@ -696,10 +693,13 @@ FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); uint16_t gpio_output_port_get(uint32_t gpio_periph); /* configure GPIO pin remap */ -void gpio_pin_remap_config(uint32_t gpio_remap, ControlStatus newvalue); +void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue); /* configure GPIO pin remap1 */ void gpio_pin_remap1_config(uint8_t remap_reg, uint32_t remap, ControlStatus newvalue); +/* select ethernet MII or RMII PHY */ +void gpio_ethernet_phy_select(uint32_t enet_sel); + /* select GPIO pin exti sources */ void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin); /* configure GPIO pin event output */ @@ -712,7 +712,4 @@ void gpio_event_output_disable(void); /* lock GPIO pin bit */ void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); -/* select ethernet MII or RMII PHY */ -void gpio_ethernet_phy_select(uint32_t enet_sel); - #endif /* GD32F20X_GPIO_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_hau.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_hau.h index 043342c1..2d7e9c2d 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_hau.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_hau.h @@ -2,36 +2,33 @@ \file gd32f20x_hau.h \brief definitions for the HAU - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -41,22 +38,22 @@ OF SUCH DAMAGE. #include "gd32f20x.h" /* HAU definitions */ -#define HAU HAU_BASE +#define HAU HAU_BASE /*!< HAU base address */ /* registers definitions */ -#define HAU_CTL REG32(HAU + 0x00U) /*!< control register */ -#define HAU_DI REG32(HAU + 0x04U) /*!< data input register */ -#define HAU_CFG REG32(HAU + 0x08U) /*!< configuration register */ -#define HAU_DO0 REG32(HAU + 0x0CU) /*!< data output register 0 */ -#define HAU_DO1 REG32(HAU + 0x10U) /*!< data output register 1 */ -#define HAU_DO2 REG32(HAU + 0x14U) /*!< data output register 2 */ -#define HAU_DO3 REG32(HAU + 0x18U) /*!< data output register 3 */ -#define HAU_DO4 REG32(HAU + 0x1CU) /*!< data output register 4 */ -#define HAU_DO5 REG32(HAU + 0x324U) /*!< data output register 5 */ -#define HAU_DO6 REG32(HAU + 0x328U) /*!< data output register 6 */ -#define HAU_DO7 REG32(HAU + 0x32CU) /*!< data output register 7 */ -#define HAU_INTEN REG32(HAU + 0x20U) /*!< interrupt enable register */ -#define HAU_STAT REG32(HAU + 0x24U) /*!< status and interrupt flag register */ +#define HAU_CTL REG32(HAU + 0x00000000U) /*!< control register */ +#define HAU_DI REG32(HAU + 0x00000004U) /*!< data input register */ +#define HAU_CFG REG32(HAU + 0x00000008U) /*!< configuration register */ +#define HAU_DO0 REG32(HAU + 0x0000000CU) /*!< data output register 0 */ +#define HAU_DO1 REG32(HAU + 0x00000010U) /*!< data output register 1 */ +#define HAU_DO2 REG32(HAU + 0x00000014U) /*!< data output register 2 */ +#define HAU_DO3 REG32(HAU + 0x00000018U) /*!< data output register 3 */ +#define HAU_DO4 REG32(HAU + 0x0000001CU) /*!< data output register 4 */ +#define HAU_DO5 REG32(HAU + 0x00000324U) /*!< data output register 5 */ +#define HAU_DO6 REG32(HAU + 0x00000328U) /*!< data output register 6 */ +#define HAU_DO7 REG32(HAU + 0x0000032CU) /*!< data output register 7 */ +#define HAU_INTEN REG32(HAU + 0x00000020U) /*!< interrupt enable register */ +#define HAU_STAT REG32(HAU + 0x00000024U) /*!< status and interrupt flag register */ /* bits definitions */ /* HAU_CTL */ @@ -92,28 +89,26 @@ OF SUCH DAMAGE. #define HAU_STAT_BUSY BIT(3) /*!< busy bit */ /* constants definitions */ -/* structure for initialization of the hau */ -typedef struct -{ +/* structure for initialization of the hau */ +typedef struct { uint32_t algo; /*!< algorithm selection */ uint32_t mode; /*!< HAU mode selection */ uint32_t datatype; /*!< data type mode */ uint32_t keytype; /*!< key length mode */ -}hau_init_parameter_struct; +} hau_init_parameter_struct; /* structure for message digest result of the hau */ -typedef struct -{ +typedef struct { uint32_t out[8]; /* message digest result 0-7 */ -}hau_digest_parameter_struct; +} hau_digest_parameter_struct; -/* hau_ctl register value */ +/* hau_ctl register value */ #define HAU_ALGO_SHA1 ((uint32_t)0x00000000U) /*!< HAU function is SHA1 */ #define HAU_ALGO_SHA224 HAU_CTL_ALGM_1 /*!< HAU function is SHA224 */ #define HAU_ALGO_SHA256 (HAU_CTL_ALGM_1 | HAU_CTL_ALGM_0) /*!< HAU function is SHA256 */ #define HAU_ALGO_MD5 HAU_CTL_ALGM_0 /*!< HAU function is MD5 */ -#define HAU_MODE_HASH ((uint32_t)0x00000000U) /*!< HAU mode is HASH */ +#define HAU_MODE_HASH ((uint32_t)0x00000000U) /*!< HAU mode is HASH */ #define HAU_MODE_HMAC HAU_CTL_HMS /*!< HAU mode is HMAC */ #define CTL_DATAM_1(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< write value to HAU_CTL_DATAM bit field */ @@ -141,7 +136,7 @@ typedef struct #define HAU_FLAG_CALCULATION_COMPLETE HAU_STAT_CINT /*!< digest calculation is completed */ #define HAU_FLAG_DMA HAU_STAT_DMAS /*!< DMA is enabled (DMAE =1) or a transfer is processing */ #define HAU_FLAG_BUSY HAU_STAT_BUSY /*!< data block is in process */ -#define HAU_FLAG_INFIFO_NO_EMPTY HAU_CTL_DINE /*!< the input FIFO is not empty */ +#define HAU_FLAG_INFIFO_NO_EMPTY HAU_CTL_DINE /*!< the input FIFO is not empty */ #define HAU_INT_FLAG_DATA_INPUT HAU_STAT_DINT /*!< there is enough space (16 bytes) in the input FIFO */ #define HAU_INT_FLAG_CALCULATION_COMPLETE HAU_STAT_CINT /*!< digest calculation is completed */ @@ -151,9 +146,9 @@ typedef struct /* reset the HAU peripheral */ void hau_deinit(void); /* initialize the HAU peripheral parameters */ -void hau_init(hau_init_parameter_struct* initpara); +void hau_init(hau_init_parameter_struct *initpara); /* initialize the structure hau_initpara */ -void hau_init_parameter_init(hau_init_parameter_struct* initpara); +void hau_init_struct_para_init(hau_init_parameter_struct *initpara); /* reset the HAU processor core */ void hau_reset(void); /* configure the number of valid bits in last word of the message */ @@ -163,7 +158,7 @@ void hau_data_write(uint32_t data); /* return the number of words already written into the IN FIFO */ uint32_t hau_infifo_words_num_get(void); /* read the message digest result */ -void hau_digest_read(hau_digest_parameter_struct* digestpara); +void hau_digest_read(hau_digest_parameter_struct *digestpara); /* enable digest calculation */ void hau_digest_calculation_enable(void); /* configure single or multiple DMA is used, and digest calculation at the end of a DMA transfer or not */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_i2c.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_i2c.h index 414e089d..f9404c2d 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_i2c.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_i2c.h @@ -2,37 +2,33 @@ \file gd32f20x_i2c.h \brief definitions for the I2C - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x - \version 2019-04-16, V2.1.1, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -42,228 +38,221 @@ OF SUCH DAMAGE. #include "gd32f20x.h" /* I2Cx(x=0,1,2) definitions */ -#define I2C0 I2C_BASE /*!< I2C0 base address */ -#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ -#define I2C2 (I2C_BASE + 0x00006C00U) /*!< I2C2 base address */ +#define I2C0 I2C_BASE /*!< I2C0 base address */ +#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ +#define I2C2 (I2C_BASE + 0x00006C00U) /*!< I2C2 base address */ /* registers definitions */ -#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ -#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ -#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/ -#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */ -#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */ -#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */ -#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */ -#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */ -#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ +#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */ +#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */ +#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0 */ +#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register 1 */ +#define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */ +#define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */ +#define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */ +#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */ +#define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */ /* bits definitions */ /* I2Cx_CTL0 */ -#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ -#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ -#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ -#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ -#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ -#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ -#define I2C_CTL0_DISSTRC BIT(7) /*!< clock stretching disable (slave mode) */ -#define I2C_CTL0_START BIT(8) /*!< start generation */ -#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ -#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ -#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ -#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ -#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ -#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ +#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ +#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ +#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ +#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ +#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ +#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ +#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ +#define I2C_CTL0_START BIT(8) /*!< start generation */ +#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ +#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ +#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ +#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ +#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ +#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ /* I2Cx_CTL1 */ -#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ -#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ -#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ -#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ -#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ -#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ +#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ +#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ +#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ +#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ +#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ +#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ /* I2Cx_SADDR0 */ -#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ -#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ +#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ +#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ /* I2Cx_SADDR1 */ -#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ -#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ +#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ +#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ /* I2Cx_DATA */ -#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ +#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ /* I2Cx_STAT0 */ -#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ -#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ -#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ -#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ -#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ -#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ -#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ -#define I2C_STAT0_BERR BIT(8) /*!< bus error */ -#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ -#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ -#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ -#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ -#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ -#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ +#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ +#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ +#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ +#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ +#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ +#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ +#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ +#define I2C_STAT0_BERR BIT(8) /*!< bus error */ +#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ +#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ +#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ +#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ +#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ +#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ /* I2Cx_STAT1 */ -#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ -#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ -#define I2C_STAT1_TRS BIT(2) /*!< transmitter/receiver */ -#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ -#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ -#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ -#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ -#define I2C_STAT1_ECV BITS(8,15) /*!< packet error checking register */ +#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ +#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ +#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ +#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ +#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ +#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ +#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ +#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ /* I2Cx_CKCFG */ -#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ -#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ -#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ +#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ +#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ +#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ /* I2Cx_RT */ -#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ +#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ /* constants definitions */ /* define the I2C bit position and its register index offset */ #define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) -#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) +#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) #define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ - | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) #define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) -#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) +#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) /* register offset */ -#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */ -#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */ -#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */ -#define I2C_SAMCS_REG_OFFSET 0x80U /*!< SAMCS register offset */ +#define I2C_CTL1_REG_OFFSET ((uint32_t)0x00000004U) /*!< CTL1 register offset */ +#define I2C_STAT0_REG_OFFSET ((uint32_t)0x00000014U) /*!< STAT0 register offset */ +#define I2C_STAT1_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT1 register offset */ +#define I2C_SAMCS_REG_OFFSET ((uint32_t)0x00000080U) /*!< SAMCS register offset */ /* I2C flags */ -typedef enum -{ +typedef enum { /* flags in STAT0 register */ - I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ - I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ - I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ - I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ - I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ - I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */ - I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ - I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ - I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ - I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ - I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ - I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ - I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ - I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ + I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ + I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ + I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ + I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ + I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not empty during receiving */ + I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ + I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ + I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ + I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ + I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ + I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ + I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ + I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ /* flags in STAT1 register */ - I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ - I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ - I2C_FLAG_TRS = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ - I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ - I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ - I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ - I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U) /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ -}i2c_flag_enum; + I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ + I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ + I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ + I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ + I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ + I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ + I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U) /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ +} i2c_flag_enum; /* I2C interrupt flags */ -typedef enum -{ +typedef enum { /* interrupt flags in CTL1 register */ I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ - I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes interrupt flag */ I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ - I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ + I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ - I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ -}i2c_interrupt_flag_enum; + I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status interrupt flag */ +} i2c_interrupt_flag_enum; -/* I2C interrupt enable or disable */ -typedef enum -{ +/* I2C interrupt */ +typedef enum { /* interrupt in CTL1 register */ - I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ - I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ - I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ -}i2c_interrupt_enum; + I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt */ + I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt */ + I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt */ +} i2c_interrupt_enum; /* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ -#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ +#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ +#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ /* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ -#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ +#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ +#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ /* I2C transfer direction */ -#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ -#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ +#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ +#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ /* whether or not to send an ACK */ -#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ -#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ +#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ +#define I2C_ACK_ENABLE I2C_CTL0_ACKEN /*!< ACK will be sent */ /* I2C POAP position*/ -#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ -#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ - -/* I2C dual-address mode switch */ -#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */ -#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */ +#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ +#define I2C_ACKPOS_NEXT I2C_CTL0_POAP /*!< ACKEN bit decides whether or not to send ACK for the next byte */ /* whether or not to stretch SCL low */ -#define I2C_SCLSTRETCH_DISABLE ((uint32_t)0x00000000U) /*!< SCL stretching is disabled */ -#define I2C_SCLSTRETCH_ENABLE I2C_CTL0_DISSTRC /*!< SCL stretching is enabled */ +#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< enable SCL stretching */ +#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< disable SCL stretching */ /* whether or not to response to a general call */ -#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ -#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ +#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ +#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ /* software reset I2C */ -#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ -#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ +#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ +#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ /* I2C DMA mode configure */ /* DMA mode switch */ -#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ -#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ +#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< disable DMA mode */ +#define I2C_DMA_ON I2C_CTL1_DMAON /*!< enable DMA mode */ /* flag indicating DMA last transfer */ -#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ -#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ +#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ +#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ /* I2C PEC configure */ /* PEC enable */ -#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ -#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ +#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ +#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ /* PEC transfer */ -#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ -#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ +#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ +#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC value */ /* I2C SMBus configure */ /* issue or not alert through SMBA pin */ -#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ -#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ +#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ +#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ /* ARP protocol in SMBus switch */ -#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP is enabled */ -#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP is disabled */ +#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< disable ARP */ +#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< enable ARP */ /* transmit I2C data */ #define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) @@ -272,12 +261,12 @@ typedef enum #define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) /* I2C duty cycle in fast mode */ -#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< T_low/T_high = 2 in fast mode */ +#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< T_low/T_high = 16/9 in fast mode */ /* address mode for the I2C slave */ -#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ -#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ +#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address format is 7 bits */ +#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address format is 10 bits */ /* function declarations */ /* initialization functions */ @@ -287,7 +276,9 @@ void i2c_deinit(uint32_t i2c_periph); void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); /* configure I2C address */ void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); -/* SMBus type selection */ + +/* application function declarations */ +/* select SMBus type */ void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); /* whether or not to send an ACK */ void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); @@ -299,8 +290,6 @@ void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandire void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr); /* disable dual-address mode */ void i2c_dualaddr_disable(uint32_t i2c_periph); - -/* function configuration */ /* enable I2C */ void i2c_enable(uint32_t i2c_periph); /* disable I2C */ @@ -313,40 +302,39 @@ void i2c_stop_on_bus(uint32_t i2c_periph); void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); /* I2C receive data function */ uint8_t i2c_data_receive(uint32_t i2c_periph); -/* enable I2C DMA mode */ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); +/* configure I2C DMA mode */ +void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate); /* configure whether next DMA EOT is DMA last transfer or not */ void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); /* whether to stretch SCL low when data is not ready in slave mode */ void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); /* whether or not to response to a general call */ void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); -/* software reset I2C */ +/* configure software reset of I2C */ void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); - -/* I2C PEC calculation on or off */ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); -/* I2C whether to transfer PEC value */ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); -/* packet error checking value */ +/* configure I2C PEC calculation */ +void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate); +/* configure whether to transfer PEC value */ +void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara); +/* get packet error checking value */ uint8_t i2c_pec_value_get(uint32_t i2c_periph); -/* I2C issue alert through SMBA pin */ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); -/* I2C ARP protocol in SMBus switch */ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); +/* configure I2C alert through SMBA pin */ +void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara); +/* configure I2C ARP protocol in SMBus */ +void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate); /* interrupt & flag functions */ -/* check I2C flag is set or not */ +/* get I2C flag status */ FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); -/* clear I2C flag */ +/* clear I2C flag status */ void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); /* enable I2C interrupt */ void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); /* disable I2C interrupt */ void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); -/* check I2C interrupt flag */ +/* get I2C interrupt flag status */ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); -/* clear I2C interrupt flag */ +/* clear I2C interrupt flag status */ void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); #endif /* GD32F20X_I2C_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_misc.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_misc.h index 93bdc821..640da184 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_misc.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_misc.h @@ -2,36 +2,33 @@ \file gd32f20x_misc.h \brief definitions for the MISC - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -42,26 +39,26 @@ OF SUCH DAMAGE. /* constants definitions */ /* set the RAM and FLASH base address */ -#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ -#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ +#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000U) /*!< RAM base address */ +#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000U) /*!< Flash base address */ /* set the NVIC vector table offset mask */ -#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) /*!< NVIC vector table offset mask */ +#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80U) /*!< NVIC vector table offset mask */ /* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */ -#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) /*!< NVIC VECTKEY mask */ +#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000U) /*!< NVIC VECTKEY mask */ /* priority group - define the pre-emption priority and the subpriority */ -#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ -#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ -#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ -#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ -#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ +#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x00000700U) /*!< 0 bits for pre-emption priority, 4 bits for subpriority */ +#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x00000600U) /*!< 1 bits for pre-emption priority, 3 bits for subpriority */ +#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x00000500U) /*!< 2 bits for pre-emption priority, 2 bits for subpriority */ +#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x00000400U) /*!< 3 bits for pre-emption priority, 1 bits for subpriority */ +#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x00000300U) /*!< 4 bits for pre-emption priority, 0 bits for subpriority */ -/* choose the method to enter or exit the lowpower mode */ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ +/* choose the method to enter or exit the low power mode */ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02U) /*!< choose the system whether enter low power mode by exiting from ISR */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04U) /*!< choose the system enter the DEEPSLEEP mode or SLEEP mode */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10U) /*!< choose the interrupt source that can wake up the low power mode */ #define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT /*!< low power mode by exiting from ISR */ #define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP /*!< DEEPSLEEP mode or SLEEP mode */ @@ -72,25 +69,20 @@ OF SUCH DAMAGE. #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ /* function declarations */ -/* function configuration */ /* set the priority group */ void nvic_priority_group_set(uint32_t nvic_prigroup); -/* enable NVIC request */ +/* enable NVIC interrupt request */ void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority); -/* disable NVIC request */ +/* disable NVIC interrupt request */ void nvic_irq_disable(uint8_t nvic_irq); - /* set the NVIC vector table base address */ void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset); - /* set the state of the low power mode */ void system_lowpower_set(uint8_t lowpower_mode); /* reset the state of the low power mode */ void system_lowpower_reset(uint8_t lowpower_mode); - /* set the systick clock source */ void systick_clksource_set(uint32_t systick_clksource); #endif /* GD32F20X_MISC_H */ - diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_pmu.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_pmu.h index 56487285..839bc672 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_pmu.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_pmu.h @@ -2,36 +2,33 @@ \file gd32f20x_pmu.h \brief definitions for the PMU - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -64,6 +61,10 @@ OF SUCH DAMAGE. #define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ /* constants definitions */ +/* PMU ldo definitions */ +#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ +#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ + /* PMU low voltage detector threshold definitions */ #define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval) << 5)) #define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */ @@ -80,10 +81,6 @@ OF SUCH DAMAGE. #define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ #define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ -/* PMU ldo definitions */ -#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ -#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ - /* PMU flag reset definitions */ #define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ #define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ @@ -93,22 +90,22 @@ OF SUCH DAMAGE. #define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ /* function declarations */ -/* initialization functions */ /* reset PMU registers */ void pmu_deinit(void); +/* LVD functions */ /* select low voltage detector threshold */ void pmu_lvd_select(uint32_t lvdt_n); /* disable PMU lvd */ void pmu_lvd_disable(void); /* set PMU mode */ -/* PMU work at sleep mode */ +/* PMU work in sleep mode */ void pmu_to_sleepmode(uint8_t sleepmodecmd); -/* PMU work at deepsleep mode */ +/* PMU work in deepsleep mode */ void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); -/* PMU work at standby mode */ -void pmu_to_standbymode(uint8_t standbymodecmd); +/* PMU work in standby mode */ +void pmu_to_standbymode(void); /* enable PMU wakeup pin */ void pmu_wakeup_pin_enable(void); /* disable PMU wakeup pin */ @@ -124,6 +121,6 @@ void pmu_backup_write_disable(void); /* get flag state */ FlagStatus pmu_flag_get(uint32_t flag); /* clear flag bit */ -void pmu_flag_clear(uint32_t flag_reset); +void pmu_flag_clear(uint32_t flag); #endif /* GD32F20X_PMU_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_rcu.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_rcu.h index 4ac9bfa5..4b94875c 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_rcu.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_rcu.h @@ -2,36 +2,33 @@ \file gd32f20x_rcu.h \brief definitions for the RCU - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -359,8 +356,7 @@ OF SUCH DAMAGE. #define PLLTCFG_REG_OFFSET 0x98U /*!< PLLT configuration register offset */ /* peripheral clock enable */ -typedef enum -{ +typedef enum { /* AHB peripherals */ RCU_DMA0 = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 0U), /*!< DMA0 clock */ RCU_DMA1 = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 1U), /*!< DMA1 clock */ @@ -371,12 +367,12 @@ typedef enum RCU_ENET = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 14U), /*!< ENET clock */ RCU_ENETTX = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 15U), /*!< ENETTX clock */ RCU_ENETRX = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 16U), /*!< ENETRX clock */ - + RCU_DCI = RCU_REGIDX_BIT(AHB2EN_REG_OFFSET, 0U), /*!< DCI clock */ RCU_CAU = RCU_REGIDX_BIT(AHB2EN_REG_OFFSET, 4U), /*!< CAU clock */ RCU_HAU = RCU_REGIDX_BIT(AHB2EN_REG_OFFSET, 5U), /*!< HAU clock */ RCU_TRNG = RCU_REGIDX_BIT(AHB2EN_REG_OFFSET, 6U), /*!< TRNG clock */ - + /* APB1 peripherals */ RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ @@ -401,13 +397,13 @@ typedef enum RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */ RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ - + RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ - + RCU_I2C2 = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 23U), /*!< I2C2 clock */ RCU_UART6 = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 30U), /*!< UART6 clock */ RCU_UART7 = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 31U), /*!< UART7 clock */ - + /* APB2 peripherals */ RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */ RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */ @@ -427,34 +423,32 @@ typedef enum RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 19U), /*!< TIMER8 clock */ RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< TIMER9 clock */ RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< TIMER10 clock */ - + RCU_USART5 = RCU_REGIDX_BIT(ADD_APB2EN_REG_OFFSET, 24U), /*!< USART5 clock */ RCU_TLI = RCU_REGIDX_BIT(ADD_APB2EN_REG_OFFSET, 26U), /*!< TLI clock */ RCU_GPIOH = RCU_REGIDX_BIT(ADD_APB2EN_REG_OFFSET, 30U), /*!< GPIOH clock */ RCU_GPIOI = RCU_REGIDX_BIT(ADD_APB2EN_REG_OFFSET, 31U), /*!< GPIOI clock */ -}rcu_periph_enum; +} rcu_periph_enum; /* peripheral clock enable when sleep mode*/ -typedef enum -{ +typedef enum { /* AHB peripherals */ RCU_SRAM_SLP = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 2U), /*!< SRAM clock */ RCU_FMC_SLP = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 4U), /*!< FMC clock */ -}rcu_periph_sleep_enum; +} rcu_periph_sleep_enum; /* peripherals reset */ -typedef enum -{ +typedef enum { /* AHB peripherals */ RCU_USBFSRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 12U), /*!< USBFS clock reset */ RCU_ENETRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 14U), /*!< ENET clock reset */ - + RCU_DCIRST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 0U), /*!< DCI clock reset */ RCU_CAURST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 4U), /*!< CAU clock reset */ RCU_HAURST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 5U), /*!< HAU clock reset */ RCU_TRNGRST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 6U), /*!< TRNG clock reset */ - + /* APB1 peripherals */ RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ @@ -479,7 +473,7 @@ typedef enum RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */ RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ - + RCU_I2C2RST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 23U), /*!< I2C2 clock reset */ RCU_UART6RST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 30U), /*!< UART6 clock reset */ RCU_UART7RST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 31U), /*!< UART7 clock reset */ @@ -509,11 +503,10 @@ typedef enum RCU_GPIOHRST = RCU_REGIDX_BIT(ADD_APB2RST_REG_OFFSET, 30U), /*!< GPIOH clock reset */ RCU_GPIOIRST = RCU_REGIDX_BIT(ADD_APB2RST_REG_OFFSET, 31U), /*!< GPIOI clock reset */ -}rcu_periph_reset_enum; +} rcu_periph_reset_enum; /* clock stabilization and peripheral reset flags */ -typedef enum -{ +typedef enum { /* clock stabilization flags */ RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */ RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ @@ -522,7 +515,7 @@ typedef enum RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */ RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ - + RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */ RCU_FLAG_PLLTSTB = RCU_REGIDX_BIT(PLLTCTL_REG_OFFSET, 29U), /*!< PLLT stabilization flags */ @@ -534,11 +527,10 @@ typedef enum RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */ -}rcu_flag_enum; +} rcu_flag_enum; /* clock stabilization and ckm interrupt flags */ -typedef enum -{ +typedef enum { RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */ RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ @@ -548,11 +540,10 @@ typedef enum RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */ RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ RCU_INT_FLAG_PLLTSTB = RCU_REGIDX_BIT(PLLTINT_REG_OFFSET, 6U), /*!< PLLT stabilization interrupt flag */ -}rcu_int_flag_enum; +} rcu_int_flag_enum; /* clock stabilization and stuck interrupt flags clear */ -typedef enum -{ +typedef enum { RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */ RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */ @@ -562,11 +553,10 @@ typedef enum RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */ RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ RCU_INT_FLAG_PLLTSTB_CLR = RCU_REGIDX_BIT(PLLTINT_REG_OFFSET, 22U), /*!< PLLT stabilization interrupt clear */ -}rcu_int_flag_clear_enum; +} rcu_int_flag_clear_enum; /* clock stabilization interrupt enable or disable */ -typedef enum -{ +typedef enum { RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */ RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */ @@ -575,33 +565,31 @@ typedef enum RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */ RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */ RCU_INT_PLLTSTB = RCU_REGIDX_BIT(PLLTINT_REG_OFFSET, 14U), /*!< PLLT stabilization interrupt */ -}rcu_int_enum; +} rcu_int_enum; /* oscillator types */ -typedef enum -{ +typedef enum { RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */ RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */ RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */ - + RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */ RCU_PLLT_CK = RCU_REGIDX_BIT(PLLTCTL_REG_OFFSET, 28U), /*!< PLLT */ -}rcu_osci_type_enum; +} rcu_osci_type_enum; /* rcu clock frequency */ -typedef enum -{ +typedef enum { CK_SYS = 0, /*!< system clock */ CK_AHB, /*!< AHB clock */ CK_APB1, /*!< APB1 clock */ CK_APB2, /*!< APB2 clock */ -}rcu_clock_freq_enum; +} rcu_clock_freq_enum; /* RCU_CFG0 register bit define */ /* system clock source selection */ @@ -975,10 +963,6 @@ typedef enum #define RCU_PLLTSRC_IRC8M ((uint32_t)0x00000000U) /*!< IRC8M selected as source clock of PLLT */ #define RCU_PLLTSRC_HXTAL RCU_PLLTCFG_PLLTSEL /*!< HXTAL selected as source clock of PLLT */ -#ifdef __cplusplus - extern "C" { -#endif - /* function declarations */ /* initialization, peripheral clock enable/disable functions */ /* deinitialize the RCU */ @@ -1018,7 +1002,7 @@ void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div); void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div); /* configure the PLL clock source selection and PLL multiply factor */ -void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); +void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); /* configure the PREDV0 division factor and clock source */ void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div); @@ -1048,19 +1032,6 @@ ErrStatus rcu_pllt_vco_config(uint32_t pllt_psc, uint32_t pllt_mul, uint32_t ppl /* configure the TLI prescaler factor */ void rcu_tli_clock_config(uint32_t tli_psc); -/* get the clock stabilization and periphral reset flags */ -FlagStatus rcu_flag_get(rcu_flag_enum flag); -/* clear the reset flag */ -void rcu_all_reset_flag_clear(void); -/* get the clock stabilization interrupt and ckm flags */ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); -/* clear the interrupt flags */ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); -/* enable the stabilization interrupt */ -void rcu_interrupt_enable(rcu_int_enum stab_int); -/* disable the stabilization interrupt */ -void rcu_interrupt_disable(rcu_int_enum stab_int); - /* configure the LXTAL drive capability */ void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); /* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ @@ -1077,17 +1048,24 @@ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); void rcu_hxtal_clock_monitor_enable(void); /* disable the HXTAL clock monitor */ void rcu_hxtal_clock_monitor_disable(void); - /* set the IRC8M adjust value */ void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval); - /* set the deep sleep mode voltage */ void rcu_deepsleep_voltage_set(uint32_t dsvol); - /* get the system clock, bus and peripheral clock frequency */ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); -#ifdef __cplusplus -} -#endif +/* get the clock stabilization and peripheral reset flags */ +FlagStatus rcu_flag_get(rcu_flag_enum flag); +/* clear the reset flag */ +void rcu_all_reset_flag_clear(void); +/* enable the stabilization interrupt */ +void rcu_interrupt_enable(rcu_int_enum stab_int); +/* disable the stabilization interrupt */ +void rcu_interrupt_disable(rcu_int_enum stab_int); +/* get the clock stabilization interrupt and ckm flags */ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); +/* clear the interrupt flags */ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); + #endif /* GD32F20X_RCU_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_rtc.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_rtc.h index 3f7bab19..6d45c3de 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_rtc.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_rtc.h @@ -2,36 +2,33 @@ \file gd32f20x_rtc.h \brief definitions for the RTC - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -41,19 +38,19 @@ OF SUCH DAMAGE. #include "gd32f20x.h" /* RTC definitions */ -#define RTC RTC_BASE +#define RTC RTC_BASE /*!< RTC base address */ /* registers definitions */ -#define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */ -#define RTC_CTL REG32(RTC + 0x04U) /*!< control register */ -#define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */ -#define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */ -#define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */ -#define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */ -#define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */ -#define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */ -#define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */ -#define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */ +#define RTC_INTEN REG32(RTC + 0x00000000U) /*!< interrupt enable register */ +#define RTC_CTL REG32(RTC + 0x00000004U) /*!< control register */ +#define RTC_PSCH REG32(RTC + 0x00000008U) /*!< prescaler high register */ +#define RTC_PSCL REG32(RTC + 0x0000000CU) /*!< prescaler low register */ +#define RTC_DIVH REG32(RTC + 0x00000010U) /*!< divider high register */ +#define RTC_DIVL REG32(RTC + 0x00000014U) /*!< divider low register */ +#define RTC_CNTH REG32(RTC + 0x00000018U) /*!< counter high register */ +#define RTC_CNTL REG32(RTC + 0x0000001CU) /*!< counter low register */ +#define RTC_ALRMH REG32(RTC + 0x00000020U) /*!< alarm high register */ +#define RTC_ALRML REG32(RTC + 0x00000024U) /*!< alarm low register */ /* bits definitions */ /* RTC_INTEN */ @@ -69,28 +66,20 @@ OF SUCH DAMAGE. #define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */ #define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ -/* RTC_PSCH */ +/* RTC_PSC */ #define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */ - -/* RTC_PSCL */ #define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */ -/* RTC_DIVH */ +/* RTC_DIV */ #define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */ - -/* RTC_DIVL */ #define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */ -/* RTC_CNTH */ +/* RTC_CNT */ #define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */ - -/* RTC_CNTL */ #define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */ -/* RTC_ALRMH */ +/* RTC_ALRM */ #define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */ - -/* RTC_ALRML */ #define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */ /* constants definitions */ @@ -99,11 +88,6 @@ OF SUCH DAMAGE. #define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */ #define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */ -/* RTC interrupt flag definitions */ -#define RTC_INT_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ -#define RTC_INT_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ -#define RTC_INT_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ - /* RTC flag definitions */ #define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ #define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ @@ -112,40 +96,36 @@ OF SUCH DAMAGE. #define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */ /* function declarations */ -/* initialization functions */ /* enter RTC configuration mode */ void rtc_configuration_mode_enter(void); /* exit RTC configuration mode */ void rtc_configuration_mode_exit(void); -/* set RTC counter value */ -void rtc_counter_set(uint32_t cnt); -/* set RTC prescaler value */ -void rtc_prescaler_set(uint32_t psc); /* operation functions */ /* wait RTC last write operation finished flag set */ void rtc_lwoff_wait(void); /* wait RTC registers synchronized flag set */ void rtc_register_sync_wait(void); -/* set RTC alarm value */ -void rtc_alarm_config(uint32_t alarm); + /* get RTC counter value */ uint32_t rtc_counter_get(void); +/* set RTC counter value */ +void rtc_counter_set(uint32_t cnt); +/* set RTC prescaler value */ +void rtc_prescaler_set(uint32_t psc); +/* set RTC alarm value */ +void rtc_alarm_config(uint32_t alarm); /* get RTC divider value */ uint32_t rtc_divider_get(void); +/* enable RTC interrupt */ +void rtc_interrupt_enable(uint32_t interrupt); +/* disable RTC interrupt */ +void rtc_interrupt_disable(uint32_t interrupt); /* flag & interrupt functions */ /* get RTC flag status */ FlagStatus rtc_flag_get(uint32_t flag); /* clear RTC flag status */ void rtc_flag_clear(uint32_t flag); -/* get RTC interrupt flag status */ -FlagStatus rtc_interrupt_flag_get(uint32_t flag); -/* clear RTC interrupt flag status */ -void rtc_interrupt_flag_clear(uint32_t flag); -/* enable RTC interrupt */ -void rtc_interrupt_enable(uint32_t interrupt); -/* disable RTC interrupt */ -void rtc_interrupt_disable(uint32_t interrupt); #endif /* GD32F20X_RTC_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_sdio.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_sdio.h index d33510b6..6e85d251 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_sdio.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_sdio.h @@ -2,36 +2,33 @@ \file gd32f20x_sdio.h \brief definitions for the SDIO - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_spi.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_spi.h index bf27bfe2..80d03c7a 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_spi.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_spi.h @@ -2,36 +2,33 @@ \file gd32f20x_spi.h \brief definitions for the SPI - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -45,17 +42,17 @@ OF SUCH DAMAGE. #define SPI1 SPI_BASE #define SPI2 (SPI_BASE + 0x00000400U) -/* SPI registers definitions */ -#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ -#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ -#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ -#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ -#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ -#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ -#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ -#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ -#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ -#define SPI_QCTL(spix) REG32((spix) + 0x80U) /*!< SPI quad mode control register(only SPI0) */ +/* registers definitions */ +#define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control register 0 */ +#define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control register 1*/ +#define SPI_STAT(spix) REG32((spix) + 0x00000008U) /*!< SPI status register */ +#define SPI_DATA(spix) REG32((spix) + 0x0000000CU) /*!< SPI data register */ +#define SPI_CRCPOLY(spix) REG32((spix) + 0x00000010U) /*!< SPI CRC polynomial register */ +#define SPI_RCRC(spix) REG32((spix) + 0x00000014U) /*!< SPI receive CRC register */ +#define SPI_TCRC(spix) REG32((spix) + 0x00000018U) /*!< SPI transmit CRC register */ +#define SPI_I2SCTL(spix) REG32((spix) + 0x0000001CU) /*!< SPI I2S control register */ +#define SPI_I2SPSC(spix) REG32((spix) + 0x00000020U) /*!< SPI I2S clock prescaler register */ +#define SPI_QCTL(spix) REG32((spix) + 0x00000080U) /*!< SPI quad mode control register(only available in SPI0) */ /* bits definitions */ /* SPI_CTL0 */ @@ -75,8 +72,8 @@ OF SUCH DAMAGE. #define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ /* SPI_CTL1 */ -#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ -#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ +#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer DMA enable */ +#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer DMA enable */ #define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ #define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ #define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ @@ -119,15 +116,14 @@ OF SUCH DAMAGE. #define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ #define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ -/* SPI_QCTL(only for SPI0) */ +/* SPI_QCTL(only available in SPI0) */ #define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */ #define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */ #define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */ /* constants definitions */ /* SPI and I2S parameter struct definitions */ -typedef struct -{ +typedef struct { uint32_t device_mode; /*!< SPI master or slave */ uint32_t trans_mode; /*!< SPI transfer type */ uint32_t frame_size; /*!< SPI frame size */ @@ -135,7 +131,7 @@ typedef struct uint32_t endian; /*!< SPI big endian or little endian */ uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ uint32_t prescale; /*!< SPI prescaler factor */ -}spi_parameter_struct; +} spi_parameter_struct; /* SPI mode definitions */ #define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ @@ -143,7 +139,7 @@ typedef struct /* SPI bidirectional transfer direction */ #define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ -#define SPI_BIDIRECTIONAL_RECEIVE ~SPI_CTL0_BDOEN /*!< SPI work in receive-only mode */ +#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ /* SPI transmit type */ #define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ @@ -169,16 +165,16 @@ typedef struct #define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ #define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ -/* SPI clock prescale factor */ +/* SPI clock prescaler factor */ #define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ -#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ -#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ -#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ -#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ -#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ -#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ -#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ +#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescaler factor is 2 */ +#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescaler factor is 4 */ +#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescaler factor is 8 */ +#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescaler factor is 16 */ +#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescaler factor is 32 */ +#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescaler factor is 64 */ +#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescaler factor is 128 */ +#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescaler factor is 256 */ /* I2S audio sample rate */ #define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ @@ -221,7 +217,7 @@ typedef struct #define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ #define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ -/* SPI DMA constants definitions */ +/* SPI DMA constants definitions */ #define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ #define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ @@ -230,9 +226,9 @@ typedef struct #define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ /* SPI/I2S interrupt enable/disable constants definitions */ -#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ -#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ -#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ +#define SPI_I2S_INT_TBE SPI_CTL1_TBEIE /*!< transmit buffer empty interrupt */ +#define SPI_I2S_INT_RBNE SPI_CTL1_RBNEIE /*!< receive buffer not empty interrupt */ +#define SPI_I2S_INT_ERR SPI_CTL1_ERRIE /*!< error interrupt */ /* SPI/I2S interrupt flag constants definitions */ #define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ @@ -242,7 +238,7 @@ typedef struct #define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ #define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ -/* SPI/I2S flag definitions */ +/* SPI/I2S flag definitions */ #define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ #define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ #define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ @@ -257,18 +253,19 @@ typedef struct #define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ /* function declarations */ -/* SPI/I2S deinitialization and initialization functions */ +/* SPI deinitialization and initialization functions */ /* reset SPI and I2S */ void spi_i2s_deinit(uint32_t spi_periph); /* initialize the parameters of SPI structure with the default values */ -void spi_struct_para_init(spi_parameter_struct* spi_struct); -/* initialize SPI parameter */ -void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct); +void spi_struct_para_init(spi_parameter_struct *spi_struct); +/* initialize SPI parameters */ +void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct); /* enable SPI */ void spi_enable(uint32_t spi_periph); /* disable SPI */ void spi_disable(uint32_t spi_periph); +/* I2S initialization functions */ /* initialize I2S parameter */ void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl); /* configure I2S prescaler */ @@ -288,21 +285,21 @@ void spi_nss_internal_high(uint32_t spi_periph); /* SPI NSS pin low level in software mode */ void spi_nss_internal_low(uint32_t spi_periph); -/* DMA communication */ +/* DMA functions */ /* enable SPI DMA */ void spi_dma_enable(uint32_t spi_periph, uint8_t dma); /* disable SPI DMA */ void spi_dma_disable(uint32_t spi_periph, uint8_t dma); -/* normal mode communication */ -/* configure SPI/I2S data frame format */ +/* communication functions */ +/* configure SPI data frame format */ void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); +/* configure SPI bidirectional transfer direction */ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); /* SPI transmit data */ void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); /* SPI receive data */ uint16_t spi_i2s_data_receive(uint32_t spi_periph); -/* configure SPI bidirectional transfer direction */ -void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); /* SPI CRC functions */ /* set SPI CRC polynomial */ @@ -317,30 +314,31 @@ void spi_crc_off(uint32_t spi_periph); void spi_crc_next(uint32_t spi_periph); /* get SPI CRC send value or receive value */ uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc); +/* clear SPI CRC error flag status */ +void spi_crc_error_clear(uint32_t spi_periph); + +/* quad wire SPI functions */ +/* enable quad wire SPI */ +void spi_quad_enable(uint32_t spi_periph); +/* disable quad wire SPI */ +void spi_quad_disable(uint32_t spi_periph); +/* enable quad wire SPI write */ +void spi_quad_write_enable(uint32_t spi_periph); +/* enable quad wire SPI read */ +void spi_quad_read_enable(uint32_t spi_periph); +/* enable SPI_IO2 and SPI_IO3 pin output */ +void spi_quad_io23_output_enable(uint32_t spi_periph); +/* disable SPI_IO2 and SPI_IO3 pin output */ +void spi_quad_io23_output_disable(uint32_t spi_periph); /* flag and interrupt functions */ +/* get SPI and I2S flag status */ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); /* enable SPI and I2S interrupt */ void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); /* disable SPI and I2S interrupt */ void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); /* get SPI and I2S interrupt status */ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); -/* get SPI and I2S flag status */ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); -/* clear SPI CRC error flag status */ -void spi_crc_error_clear(uint32_t spi_periph); - -/* enable quad wire SPI */ -void qspi_enable(uint32_t spi_periph); -/* disable quad wire SPI */ -void qspi_disable(uint32_t spi_periph); -/* enable quad wire SPI write */ -void qspi_write_enable(uint32_t spi_periph); -/* enable quad wire SPI read */ -void qspi_read_enable(uint32_t spi_periph); -/* enable quad wire SPI_IO2 and SPI_IO3 pin output */ -void qspi_io23_output_enable(uint32_t spi_periph); -/* disable quad wire SPI_IO2 and SPI_IO3 pin output */ -void qspi_io23_output_disable(uint32_t spi_periph); #endif /* GD32F20X_SPI_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_timer.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_timer.h index d83f771c..a04b85ae 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_timer.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_timer.h @@ -2,36 +2,33 @@ \file gd32f20x_timer.h \brief definitions for the TIMER - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -74,7 +71,7 @@ OF SUCH DAMAGE. #define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ #define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ #define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ -#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER channel complementary protection register */ +#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER complementary channel protection register */ #define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ #define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ @@ -111,7 +108,7 @@ OF SUCH DAMAGE. #define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ #define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ #define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ - + /* TIMER_DMAINTEN */ #define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ #define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ @@ -122,10 +119,10 @@ OF SUCH DAMAGE. #define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ #define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ #define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ -#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 capture/compare DMA request enable */ -#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 capture/compare DMA request enable */ -#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 capture/compare DMA request enable */ -#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 capture/compare DMA request enable */ +#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 DMA request enable */ +#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 DMA request enable */ +#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 DMA request enable */ +#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 DMA request enable */ #define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ #define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ @@ -248,19 +245,17 @@ OF SUCH DAMAGE. /* constants definitions */ /* TIMER init parameter structure definitions */ -typedef struct -{ +typedef struct { uint16_t prescaler; /*!< prescaler value */ uint16_t alignedmode; /*!< aligned mode */ uint16_t counterdirection; /*!< counter direction */ uint32_t period; /*!< period value */ uint16_t clockdivision; /*!< clock division value */ uint8_t repetitioncounter; /*!< the counter repetition value */ -}timer_parameter_struct; +} timer_parameter_struct; /* break parameter structure definitions*/ -typedef struct -{ +typedef struct { uint16_t runoffstate; /*!< run mode off-state */ uint16_t ideloffstate; /*!< idle mode off-state */ uint16_t deadtime; /*!< dead time */ @@ -268,27 +263,25 @@ typedef struct uint16_t outputautostate; /*!< output automatic enable */ uint16_t protectmode; /*!< complementary register protect control */ uint16_t breakstate; /*!< break enable */ -}timer_break_parameter_struct; +} timer_break_parameter_struct; /* channel output parameter structure definitions */ -typedef struct -{ +typedef struct { uint16_t outputstate; /*!< channel output state */ uint16_t outputnstate; /*!< channel complementary output state */ uint16_t ocpolarity; /*!< channel output polarity */ uint16_t ocnpolarity; /*!< channel complementary output polarity */ uint16_t ocidlestate; /*!< idle state of channel output */ uint16_t ocnidlestate; /*!< idle state of channel complementary output */ -}timer_oc_parameter_struct; +} timer_oc_parameter_struct; /* channel input parameter structure definitions */ -typedef struct -{ +typedef struct { uint16_t icpolarity; /*!< channel input polarity */ uint16_t icselection; /*!< channel input mode selection */ uint16_t icprescaler; /*!< channel input capture prescaler */ uint16_t icfilter; /*!< channel input capture filter control */ -}timer_ic_parameter_struct; +} timer_ic_parameter_struct; /* TIMER interrupt enable or disable */ #define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ @@ -296,20 +289,10 @@ typedef struct #define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ #define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ #define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ -#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ +#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt */ #define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ #define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ -/* TIMER interrupt flag */ -#define TIMER_INT_FLAG_UP TIMER_INT_UP /*!< update interrupt */ -#define TIMER_INT_FLAG_CH0 TIMER_INT_CH0 /*!< channel 0 interrupt */ -#define TIMER_INT_FLAG_CH1 TIMER_INT_CH1 /*!< channel 1 interrupt */ -#define TIMER_INT_FLAG_CH2 TIMER_INT_CH2 /*!< channel 2 interrupt */ -#define TIMER_INT_FLAG_CH3 TIMER_INT_CH3 /*!< channel 3 interrupt */ -#define TIMER_INT_FLAG_CMT TIMER_INT_CMT /*!< channel commutation interrupt flag */ -#define TIMER_INT_FLAG_TRG TIMER_INT_TRG /*!< trigger interrupt */ -#define TIMER_INT_FLAG_BRK TIMER_INT_BRK - /* TIMER flag */ #define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ #define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ @@ -324,6 +307,16 @@ typedef struct #define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ #define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ +/* TIMER interrupt flag */ +#define TIMER_INT_FLAG_UP TIMER_INTF_UPIF /*!< update interrupt flag */ +#define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 interrupt flag */ +#define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 interrupt flag */ +#define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 interrupt flag */ +#define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 interrupt flag */ +#define TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation interrupt flag */ +#define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */ +#define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF /*!< break interrupt */ + /* TIMER DMA source enable */ #define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ #define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ @@ -333,12 +326,12 @@ typedef struct #define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ #define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ -/* channel DMA request source selection */ -#define TIMER_DMAREQUEST_UPDATEEVENT TIMER_CTL1_DMAS /*!< DMA request of channel n is sent when update event occurs */ -#define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel n is sent when channel n event occurs */ +/* channel DMA request source selection */ +#define TIMER_DMAREQUEST_UPDATEEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel y is sent when update event occurs */ +#define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000001U) /*!< DMA request of channel y is sent when channel y event occurs */ /* DMA access base address */ -#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) +#define DMACFG_DMATA(regval) (BITS(0,4) & ((uint32_t)(regval) << 0U)) #define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ #define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ #define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ @@ -361,7 +354,7 @@ typedef struct #define TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19) /*!< DMA transfer address is TIMER_DMATB */ /* DMA access burst length */ -#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) +#define DMACFG_DMATC(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) #define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ #define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ #define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ @@ -392,39 +385,39 @@ typedef struct #define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ /* center-aligned mode selection */ -#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) +#define CTL0_CAM(regval) ((uint16_t)(BITS(5,6) & ((uint32_t)(regval) << 5U))) #define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ #define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ #define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ #define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ /* TIMER prescaler reload mode */ -#define TIMER_PSC_RELOAD_NOW TIMER_SWEVG_UPG /*!< the prescaler is loaded right now */ -#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000000U) /*!< the prescaler is loaded at the next update event */ +#define TIMER_PSC_RELOAD_NOW ((uint32_t)0x00000000U) /*!< the prescaler is loaded right now */ +#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000001U) /*!< the prescaler is loaded at the next update event */ /* count direction */ #define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ #define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ /* specify division ratio between TIMER clock and dead-time and sampling clock */ -#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8,9) & ((uint32_t)(regval) << 8U))) #define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ #define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ #define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ /* single pulse mode */ -#define TIMER_SP_MODE_SINGLE TIMER_CTL0_SPM /*!< single pulse mode */ -#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000000U) /*!< repetitive pulse mode */ +#define TIMER_SP_MODE_SINGLE ((uint32_t)0x00000000U) /*!< single pulse mode */ +#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000001U) /*!< repetitive pulse mode */ /* update source */ -#define TIMER_UPDATE_SRC_REGULAR TIMER_CTL0_UPS /*!< update generate only by counter overflow/underflow */ -#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000000U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ +#define TIMER_UPDATE_SRC_REGULAR ((uint32_t)0x00000000U) /*!< update generate only by counter overflow/underflow */ +#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000001U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ /* run mode off-state configure */ #define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ #define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are disabled */ -/* idle mode off-state configure */ +/* idle mode off-state configure */ #define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ #define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals(CHx_O/CHx_ON) are disabled */ @@ -437,7 +430,7 @@ typedef struct #define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ /* complementary register protect control */ -#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define CCHP_PROT(regval) ((uint16_t)(BITS(8,9) & ((uint32_t)(regval) << 8U))) #define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ #define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ #define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ @@ -469,19 +462,19 @@ typedef struct #define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ #define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ -/* idle state of channel output */ +/* idle state of channel output */ #define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ #define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ -/* idle state of channel complementary output */ +/* idle state of channel complementary output */ #define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ #define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ /* channel output compare mode */ -#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< frozen mode */ -#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< set the channel output */ -#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< clear the channel output */ -#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle on match */ +#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ +#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ +#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ +#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ #define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ #define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ #define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ @@ -499,16 +492,16 @@ typedef struct #define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ #define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ -/* channel control shadow register update control */ -#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers update by when CMTG bit is set */ -#define TIMER_UPDATECTL_CCUTRI TIMER_CTL1_CCUC /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ +/* channel control shadow register update control */ +#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers are updated when CMTG bit is set */ +#define TIMER_UPDATECTL_CCUTRI ((uint32_t)0x00000001U) /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ /* channel input capture polarity */ #define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ #define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ #define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ -/* timer input capture selection */ +/* TIMER input capture selection */ #define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */ #define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */ #define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */ @@ -520,7 +513,7 @@ typedef struct #define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ /* trigger selection */ -#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define SMCFG_TRGSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4U)) #define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ #define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ #define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ @@ -528,10 +521,10 @@ typedef struct #define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ #define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ #define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ -#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ +#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< filtered external trigger input */ /* master mode control */ -#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define CTL1_MMC(regval) (BITS(4,6) & ((uint32_t)(regval) << 4U)) #define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ #define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ #define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ @@ -542,22 +535,22 @@ typedef struct #define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ /* slave mode control */ -#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) +#define SMCFG_SMC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U)) #define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ -#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ -#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ -#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ +#define TIMER_QUAD_DECODER_MODE0 SMCFG_SMC(1) /*!< quadrature decoder mode 0 */ +#define TIMER_QUAD_DECODER_MODE1 SMCFG_SMC(2) /*!< quadrature decoder mode 1 */ +#define TIMER_QUAD_DECODER_MODE2 SMCFG_SMC(3) /*!< quadrature decoder mode 2 */ #define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ #define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ #define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ #define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ -/* master slave mode selection */ -#define TIMER_MASTER_SLAVE_MODE_ENABLE TIMER_SMCFG_MSM /*!< master slave mode enable */ -#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ +/* master slave mode selection */ +#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint32_t)0x00000000U) /*!< master slave mode enable */ +#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000001U) /*!< master slave mode disable */ /* external trigger prescaler */ -#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) +#define SMCFG_ETPSC(regval) (BITS(12,13) & ((uint32_t)(regval) << 12U)) #define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ #define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ #define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ @@ -567,22 +560,18 @@ typedef struct #define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ #define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ -/* channel 0 trigger input selection */ -#define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall sensor mode enable */ -#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode disable */ - -/* TIMERx(x=0..4,7..13) write CHxVAL register selection */ -#define TIMER_CHVSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< write CHxVAL register selection enable */ -#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ +/* channel 0 trigger input selection */ +#define TIMER_HALLINTERFACE_ENABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode enable */ +#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000001U) /*!< TIMER hall sensor mode disable */ /* function declarations */ /* TIMER timebase */ /* deinit a TIMER */ void timer_deinit(uint32_t timer_periph); /* initialize TIMER init parameter structure */ -void timer_struct_para_init(timer_parameter_struct* initpara); +void timer_struct_para_init(timer_parameter_struct *initpara); /* initialize TIMER counter */ -void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); +void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara); /* enable a TIMER */ void timer_enable(uint32_t timer_periph); /* disable a TIMER */ @@ -604,7 +593,7 @@ void timer_counter_down_direction(uint32_t timer_periph); /* configure TIMER prescaler */ void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload); /* configure TIMER repetition register value */ -void timer_repetition_value_config(uint32_t timer_periph, uint8_t repetition); +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); /* configure TIMER autoreload register value */ void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload); /* configure TIMER counter register value */ @@ -618,7 +607,7 @@ void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); /* configure TIMER update source */ void timer_update_source_config(uint32_t timer_periph, uint32_t update); -/* timer DMA and event */ +/* TIMER DMA and event */ /* enable the TIMER DMA */ void timer_dma_enable(uint32_t timer_periph, uint16_t dma); /* disable the TIMER DMA */ @@ -632,9 +621,9 @@ void timer_event_software_generate(uint32_t timer_periph, uint16_t event); /* TIMER channel complementary protection */ /* initialize TIMER break parameter struct */ -void timer_break_struct_para_init(timer_break_parameter_struct* breakpara); +void timer_break_struct_para_init(timer_break_parameter_struct *breakpara); /* configure TIMER break function */ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara); /* enable TIMER break function */ void timer_break_enable(uint32_t timer_periph); /* disable TIMER break function */ @@ -652,13 +641,13 @@ void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t /* TIMER channel output */ /* initialize TIMER channel output parameter struct */ -void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara); +void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara); /* configure TIMER channel output function */ -void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara); +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara); /* configure TIMER channel output compare mode */ void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode); /* configure TIMER channel output pulse value */ -void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint16_t pulse); +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); /* configure TIMER channel output shadow function */ void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); /* configure TIMER channel output fast function */ @@ -676,15 +665,15 @@ void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint /* TIMER channel input */ /* initialize TIMER channel input parameter structure */ -void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara); +void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara); /* configure TIMER input capture parameter */ -void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara); /* configure TIMER channel input capture prescaler value */ void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); /* read TIMER channel capture compare register value */ uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); /* configure TIMER input pwm capture function */ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm); /* configure TIMER hall sensor mode */ void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); @@ -698,7 +687,7 @@ void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode); /* configure TIMER master slave mode */ void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); /* configure TIMER external trigger input */ -void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint8_t extfilter); +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); /* configure TIMER quadrature decoder mode */ void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); /* configure TIMER internal clock mode */ @@ -706,26 +695,26 @@ void timer_internal_clock_config(uint32_t timer_periph); /* configure TIMER the internal trigger as external clock input */ void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); /* configure TIMER the external trigger as external clock input */ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint8_t extfilter); +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter); /* configure TIMER the external clock mode 0 */ -void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint8_t extfilter); +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); /* configure TIMER the external clock mode 1 */ -void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint8_t extfilter); +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); /* disable TIMER the external clock mode 1 */ void timer_external_clock_mode1_disable(uint32_t timer_periph); /* TIMER interrupt and flag */ +/* get TIMER flags */ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); +/* clear TIMER flags */ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag); /* enable the TIMER interrupt */ void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); /* disable the TIMER interrupt */ void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); -/* get TIMER interrupt flag */ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); -/* clear TIMER interrupt flag */ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); -/* get TIMER flag */ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); -/* clear TIMER flag */ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag); +/* get TIMER interrupt flags */ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t int_flag); +/* clear TIMER interrupt flags */ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t int_flag); #endif /* GD32F20X_TIMER_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_tli.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_tli.h index 55bfc902..00efc28e 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_tli.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_tli.h @@ -2,36 +2,33 @@ \file gd32f20x_tli.h \brief definitions for the TLI - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -193,12 +190,11 @@ OF SUCH DAMAGE. /* constants definitions */ /* TLI parameter structure definitions */ -typedef struct -{ - uint32_t synpsz_vpsz; /*!< size of the vertical synchronous pulse */ - uint32_t synpsz_hpsz; /*!< size of the horizontal synchronous pulse */ - uint32_t backpsz_vbpsz; /*!< size of the vertical back porch plus synchronous pulse */ - uint32_t backpsz_hbpsz; /*!< size of the horizontal back porch plus synchronous pulse */ +typedef struct { + uint16_t synpsz_vpsz; /*!< size of the vertical synchronous pulse */ + uint16_t synpsz_hpsz; /*!< size of the horizontal synchronous pulse */ + uint16_t backpsz_vbpsz; /*!< size of the vertical back porch plus synchronous pulse */ + uint16_t backpsz_hbpsz; /*!< size of the horizontal back porch plus synchronous pulse */ uint32_t activesz_vasz; /*!< size of the vertical active area width plus back porch and synchronous pulse */ uint32_t activesz_hasz; /*!< size of the horizontal active area width plus back porch and synchronous pulse */ uint32_t totalsz_vtsz; /*!< vertical total size of the display */ @@ -210,49 +206,46 @@ typedef struct uint32_t signalpolarity_vs; /*!< vertical pulse polarity selection */ uint32_t signalpolarity_de; /*!< data enable polarity selection */ uint32_t signalpolarity_pixelck; /*!< pixel clock polarity selection */ -}tli_parameter_struct; +} tli_parameter_struct; /* TLI layer parameter structure definitions */ -typedef struct -{ - uint32_t layer_window_rightpos; /*!< window right position */ - uint32_t layer_window_leftpos; /*!< window left position */ - uint32_t layer_window_bottompos; /*!< window bottom position */ - uint32_t layer_window_toppos; /*!< window top position */ +typedef struct { + uint16_t layer_window_rightpos; /*!< window right position */ + uint16_t layer_window_leftpos; /*!< window left position */ + uint16_t layer_window_bottompos; /*!< window bottom position */ + uint16_t layer_window_toppos; /*!< window top position */ uint32_t layer_ppf; /*!< packeted pixel format */ - uint32_t layer_sa; /*!< specified alpha */ - uint32_t layer_default_alpha; /*!< the default color alpha */ - uint32_t layer_default_red; /*!< the default color red */ - uint32_t layer_default_green; /*!< the default color green */ - uint32_t layer_default_blue; /*!< the default color blue */ + uint8_t layer_sa; /*!< specified alpha */ + uint8_t layer_default_alpha; /*!< the default color alpha */ + uint8_t layer_default_red; /*!< the default color red */ + uint8_t layer_default_green; /*!< the default color green */ + uint8_t layer_default_blue; /*!< the default color blue */ uint32_t layer_acf1; /*!< alpha calculation factor 1 of blending method */ uint32_t layer_acf2; /*!< alpha calculation factor 2 of blending method */ uint32_t layer_frame_bufaddr; /*!< frame buffer base address */ - uint32_t layer_frame_buf_stride_offset; /*!< frame buffer stride offset */ - uint32_t layer_frame_line_length; /*!< frame line length */ - uint32_t layer_frame_total_line_number; /*!< frame total line number */ -}tli_layer_parameter_struct; + uint16_t layer_frame_buf_stride_offset; /*!< frame buffer stride offset */ + uint16_t layer_frame_line_length; /*!< frame line length */ + uint16_t layer_frame_total_line_number; /*!< frame total line number */ +} tli_layer_parameter_struct; /* TLI layer LUT parameter structure definitions */ -typedef struct -{ +typedef struct { uint32_t layer_table_addr; /*!< look up table write address */ - uint32_t layer_lut_channel_red; /*!< red channel of a LUT entry */ - uint32_t layer_lut_channel_green; /*!< green channel of a LUT entry */ - uint32_t layer_lut_channel_blue; /*!< blue channel of a LUT entry */ -}tli_layer_lut_parameter_struct; + uint8_t layer_lut_channel_red; /*!< red channel of a LUT entry */ + uint8_t layer_lut_channel_green; /*!< green channel of a LUT entry */ + uint8_t layer_lut_channel_blue; /*!< blue channel of a LUT entry */ +} tli_layer_lut_parameter_struct; /* packeted pixel format */ -typedef enum -{ - LAYER_PPF_ARGB8888, /*!< layerx packeted pixel format ARGB8888 */ - LAYER_PPF_RGB888, /*!< layerx packeted pixel format RGB888 */ - LAYER_PPF_RGB565, /*!< layerx packeted pixel format RGB565 */ - LAYER_PPF_ARGB1555, /*!< layerx packeted pixel format ARGB1555 */ - LAYER_PPF_ARGB4444, /*!< layerx packeted pixel format ARGB4444 */ - LAYER_PPF_L8, /*!< layerx packeted pixel format L8 */ - LAYER_PPF_AL44, /*!< layerx packeted pixel format AL44 */ - LAYER_PPF_AL88 /*!< layerx packeted pixel format AL88 */ +typedef enum { + LAYER_PPF_ARGB8888 = 0U, /*!< layerx packeted pixel format ARGB8888 */ + LAYER_PPF_RGB888, /*!< layerx packeted pixel format RGB888 */ + LAYER_PPF_RGB565, /*!< layerx packeted pixel format RGB565 */ + LAYER_PPF_ARGB1555, /*!< layerx packeted pixel format ARGB1555 */ + LAYER_PPF_ARGB4444, /*!< layerx packeted pixel format ARGB4444 */ + LAYER_PPF_L8, /*!< layerx packeted pixel format L8 */ + LAYER_PPF_AL44, /*!< layerx packeted pixel format AL44 */ + LAYER_PPF_AL88 /*!< layerx packeted pixel format AL88 */ } tli_layer_ppf_enum; /* TLI flags and states */ @@ -288,10 +281,12 @@ typedef enum /* horizontal pulse polarity selection */ #define TLI_HSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< horizontal synchronous pulse active low */ #define TLI_HSYN_ACTLIVE_HIGHT TLI_CTL_HPPS /*!< horizontal synchronous pulse active high */ +#define TLI_HSYN_ACTLIVE_HIGH TLI_HSYN_ACTLIVE_HIGHT /*!< horizontal synchronous pulse active high */ /* vertical pulse polarity selection */ #define TLI_VSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< vertical synchronous pulse active low */ #define TLI_VSYN_ACTLIVE_HIGHT TLI_CTL_VPPS /*!< vertical synchronous pulse active high */ +#define TLI_VSYN_ACTLIVE_HIGH TLI_VSYN_ACTLIVE_HIGHT /*!< vertical synchronous pulse active high */ /* pixel clock polarity selection */ #define TLI_PIXEL_CLOCK_TLI ((uint32_t)0x00000000U) /*!< pixel clock is TLI clock */ @@ -300,69 +295,79 @@ typedef enum /* data enable polarity selection */ #define TLI_DE_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< data enable active low */ #define TLI_DE_ACTLIVE_HIGHT TLI_CTL_DEPS /*!< data enable active high */ +#define TLI_DE_ACTLIVE_HIGH TLI_DE_ACTLIVE_HIGHT /*!< data enable active high */ /* alpha calculation factor 1 of blending method */ -#define LxBLEND_ACF1(regval) (BITS(8,10) & ((regval)<<8)) +#define LxBLEND_ACF1(regval) (BITS(8,10) & ((uint32_t)(regval)<<8)) #define LAYER_ACF1_SA LxBLEND_ACF1(4) /*!< normalization specified alpha */ #define LAYER_ACF1_PASA LxBLEND_ACF1(6) /*!< normalization pixel alpha * normalization specified alpha */ /* alpha calculation factor 2 of blending method */ -#define LxBLEND_ACF2(regval) (BITS(0,2) & ((regval))) +#define LxBLEND_ACF2(regval) (BITS(0,2) & ((uint32_t)(regval))) #define LAYER_ACF2_SA LxBLEND_ACF2(5) /*!< normalization specified alpha */ #define LAYER_ACF2_PASA LxBLEND_ACF2(7) /*!< normalization pixel alpha * normalization specified alpha */ /* function declarations */ /* initialization functions */ -/* deinitialize TLI */ +/* deinitialize TLI registers */ void tli_deinit(void); -/* initialize TLI */ +/* initialize the parameters of TLI parameter structure with the default values, it is suggested + that call this function after a tli_parameter_struct structure is defined */ +void tli_struct_para_init(tli_parameter_struct *tli_struct); +/* initialize TLI display timing parameters */ void tli_init(tli_parameter_struct *tli_struct); /* configure TLI dither function */ -void tli_dither_config(uint8_t ditherstat); +void tli_dither_config(uint8_t dither_stat); /* enable TLI */ void tli_enable(void); /* disable TLI */ void tli_disable(void); /* configure TLI reload mode */ -void tli_reload_config(uint8_t reloadmode); - -/* set line mark value */ -void tli_line_mark_set(uint32_t linenum); -/* get current displayed position */ -uint32_t tli_current_pos_get(void); - -/* function configuration */ -/* TLI layer enable */ +void tli_reload_config(uint8_t reload_mod); + +/* TLI layer configuration functions */ +/* initialize the parameters of TLI layer structure with the default values, it is suggested + that call this function after a tli_layer_parameter_struct structure is defined */ +void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct); +/* initialize TLI layer */ +void tli_layer_init(uint32_t layerx, tli_layer_parameter_struct *layer_struct); +/* reconfigure window position */ +void tli_layer_window_offset_modify(uint32_t layerx, uint16_t offset_x, uint16_t offset_y); +/* initialize the parameters of TLI layer LUT structure with the default values, it is suggested + that call this function after a tli_layer_lut_parameter_struct structure is defined */ +void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct); +/* initialize TLI layer LUT */ +void tli_lut_init(uint32_t layerx, tli_layer_lut_parameter_struct *lut_struct); +/* initialize TLI layer color key */ +void tli_color_key_init(uint32_t layerx, uint8_t redkey, uint8_t greenkey, uint8_t bluekey); +/* enable TLI layer */ void tli_layer_enable(uint32_t layerx); -/* TLI layer disable */ +/* disable TLI layer */ void tli_layer_disable(uint32_t layerx); -/* TLI layer color keying enable */ +/* enable TLI layer color keying */ void tli_color_key_enable(uint32_t layerx); -/* TLI layer color keying disable */ +/* disable TLI layer color keying */ void tli_color_key_disable(uint32_t layerx); -/* TLI layer LUT enable */ +/* enable TLI layer LUT */ void tli_lut_enable(uint32_t layerx); -/* TLI layer LUT disable */ +/* disable TLI layer LUT */ void tli_lut_disable(uint32_t layerx); -/* TLI layer initialize */ -void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct); -/* TLI layer initialize */ -void tli_layer_window_offset_modify(uint32_t layerx,uint32_t offset_x,uint32_t offset_y); -/* TLI layer LUT initialize */ -void tli_lut_init(uint32_t layerx,tli_layer_lut_parameter_struct *lut_struct); -/* TLI layer key initialize */ -void tli_ckey_init(uint32_t layerx,uint32_t redkey,uint32_t greenkey,uint32_t bluekey); - -/* interrupt & flag functions */ -/* get TLI flag or state */ -FlagStatus tli_flag_get(uint32_t flag); + +/* set line mark value */ +void tli_line_mark_set(uint16_t line_num); +/* get current displayed position */ +uint32_t tli_current_pos_get(void); + +/* flag and interrupt functions */ /* enable TLI interrupt */ -void tli_interrupt_enable(uint32_t interrupt); +void tli_interrupt_enable(uint32_t int_flag); /* disable TLI interrupt */ -void tli_interrupt_disable(uint32_t interrupt); +void tli_interrupt_disable(uint32_t int_flag); /* get TLI interrupt flag */ FlagStatus tli_interrupt_flag_get(uint32_t int_flag); /* clear TLI interrupt flag */ void tli_interrupt_flag_clear(uint32_t int_flag); +/* get TLI flag or state in TLI_INTF register or TLI_STAT register */ +FlagStatus tli_flag_get(uint32_t flag); #endif /* GD32F20X_TLI_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_trng.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_trng.h index da2edeb0..3db15e46 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_trng.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_trng.h @@ -2,36 +2,33 @@ \file gd32f20x_trng.h \brief definitions for the TRNG - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -41,17 +38,17 @@ OF SUCH DAMAGE. #include "gd32f20x.h" /* TRNG definitions */ -#define TRNG TRNG_BASE +#define TRNG TRNG_BASE /*!< TRNG base address */ /* registers definitions */ -#define TRNG_CTL REG32(TRNG + 0x00U) /*!< control register */ -#define TRNG_STAT REG32(TRNG + 0x04U) /*!< status register */ -#define TRNG_DATA REG32(TRNG + 0x08U) /*!< data register */ +#define TRNG_CTL REG32(TRNG + 0x00000000U) /*!< control register */ +#define TRNG_STAT REG32(TRNG + 0x00000004U) /*!< status register */ +#define TRNG_DATA REG32(TRNG + 0x00000008U) /*!< data register */ /* bits definitions */ /* TRNG_CTL */ #define TRNG_CTL_TRNGEN BIT(2) /*!< TRNG enable bit */ -#define TRNG_CTL_IE BIT(3) /*!< interrupt enable bit */ +#define TRNG_CTL_TRNGIE BIT(3) /*!< interrupt enable bit */ /* TRNG_STAT */ #define TRNG_STAT_DRDY BIT(0) /*!< random data ready status bit */ @@ -60,46 +57,41 @@ OF SUCH DAMAGE. #define TRNG_STAT_CEIF BIT(5) /*!< clock error interrupt flag */ #define TRNG_STAT_SEIF BIT(6) /*!< seed error interrupt flag */ -/* TRNG_DATA */ -#define TRNG_DATA_TRNDATA BITS(0,31) /*!< 32-Bit Random data */ - /* constants definitions */ /* trng status flag */ -typedef enum -{ +typedef enum { TRNG_FLAG_DRDY = TRNG_STAT_DRDY, /*!< random Data ready status */ TRNG_FLAG_CECS = TRNG_STAT_CECS, /*!< clock error current status */ TRNG_FLAG_SECS = TRNG_STAT_SECS /*!< seed error current status */ -}trng_flag_enum; +} trng_flag_enum; /* trng inerrupt flag */ -typedef enum -{ - TRNG_INT_FLAG_CE = TRNG_STAT_CEIF, /*!< clock error interrupt flag */ - TRNG_INT_FLAG_SE = TRNG_STAT_SEIF /*!< seed error interrupt flag */ -}trng_int_flag_enum; +typedef enum { + TRNG_INT_FLAG_CE = TRNG_STAT_CEIF, /*!< clock error interrupt flag */ + TRNG_INT_FLAG_SE = TRNG_STAT_SEIF /*!< seed error interrupt flag */ +} trng_int_flag_enum; /* function declarations */ /* initialization functions */ -/* deinitialize the TRNG */ +/* reset TRNG */ void trng_deinit(void); -/* enable the TRNG interface */ +/* enable TRNG */ void trng_enable(void); -/* disable the TRNG interface */ +/* disable TRNG */ void trng_disable(void); /* get the true random data */ uint32_t trng_get_true_random_data(void); /* interrupt & flag functions */ -/* get the trng status flags */ +/* get TRNG status flags */ FlagStatus trng_flag_get(trng_flag_enum flag); -/* the trng interrupt enable */ +/* enable TRNG interrupt */ void trng_interrupt_enable(void); -/* the trng interrupt disable */ +/* disable TRNG interrupt */ void trng_interrupt_disable(void); -/* get the trng interrupt flags */ +/* get TRNG interrupt flag status */ FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag); -/* clear the trng interrupt flags */ +/* clear TRNG interrupt flag status */ void trng_interrupt_flag_clear(trng_int_flag_enum int_flag); #endif /* GD32F20X_TRNG_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_usart.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_usart.h index 01c43fc6..114eb53a 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_usart.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_usart.h @@ -2,36 +2,33 @@ \file gd32f20x_usart.h \brief definitions for the USART - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -42,108 +39,108 @@ OF SUCH DAMAGE. /* USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) definitions */ #define USART1 USART_BASE /*!< USART1 base address */ -#define USART2 (USART_BASE+0x00000400U) /*!< USART2 base address */ -#define UART3 (USART_BASE+0x00000800U) /*!< UART3 base address */ -#define UART4 (USART_BASE+0x00000C00U) /*!< UART4 base address */ -#define UART6 (USART_BASE+0x00003400U) /*!< UART6 base address */ -#define UART7 (USART_BASE+0x00003800U) /*!< UART7 base address */ -#define USART0 (USART_BASE+0x0000F400U) /*!< USART0 base address */ -#define USART5 (USART_BASE+0x00012C00U) /*!< USART5 base address */ +#define USART2 (USART_BASE + 0x00000400U) /*!< USART2 base address */ +#define UART3 (USART_BASE + 0x00000800U) /*!< UART3 base address */ +#define UART4 (USART_BASE + 0x00000C00U) /*!< UART4 base address */ +#define UART6 (USART_BASE + 0x00003400U) /*!< UART6 base address */ +#define UART7 (USART_BASE + 0x00003800U) /*!< UART7 base address */ +#define USART0 (USART_BASE + 0x0000F400U) /*!< USART0 base address */ +#define USART5 (USART_BASE + 0x00012C00U) /*!< USART5 base address */ /* registers definitions */ -#define USART_STAT0(usartx) REG32((usartx) + 0x00U) /*!< USART status register 0 */ -#define USART_DATA(usartx) REG32((usartx) + 0x04U) /*!< USART data register */ -#define USART_BAUD(usartx) REG32((usartx) + 0x08U) /*!< USART baud rate register */ -#define USART_CTL0(usartx) REG32((usartx) + 0x0CU) /*!< USART control register 0 */ -#define USART_CTL1(usartx) REG32((usartx) + 0x10U) /*!< USART control register 1 */ -#define USART_CTL2(usartx) REG32((usartx) + 0x14U) /*!< USART control register 2 */ -#define USART_GP(usartx) REG32((usartx) + 0x18U) /*!< USART guard time and prescaler register */ -#define USART_CTL3(usartx) REG32((usartx) + 0x80U) /*!< USART control register 3 */ -#define USART_RT(usartx) REG32((usartx) + 0x84U) /*!< USART receiver timeout register */ -#define USART_STAT1(usartx) REG32((usartx) + 0x88U) /*!< USART status register 1 */ +#define USART_STAT0(usartx) REG32((usartx) + 0x00000000U) /*!< USART status register 0 */ +#define USART_DATA(usartx) REG32((usartx) + 0x00000004U) /*!< USART data register */ +#define USART_BAUD(usartx) REG32((usartx) + 0x00000008U) /*!< USART baud rate register */ +#define USART_CTL0(usartx) REG32((usartx) + 0x0000000CU) /*!< USART control register 0 */ +#define USART_CTL1(usartx) REG32((usartx) + 0x00000010U) /*!< USART control register 1 */ +#define USART_CTL2(usartx) REG32((usartx) + 0x00000014U) /*!< USART control register 2 */ +#define USART_GP(usartx) REG32((usartx) + 0x00000018U) /*!< USART guard time and prescaler register */ +#define USART_CTL3(usartx) REG32((usartx) + 0x00000080U) /*!< USART control register 3 */ +#define USART_RT(usartx) REG32((usartx) + 0x00000084U) /*!< USART receiver timeout register */ +#define USART_STAT1(usartx) REG32((usartx) + 0x00000088U) /*!< USART status register 1 */ /* bits definitions */ /* USARTx_STAT0 */ -#define USART_STAT0_PERR BIT(0) /*!< parity error flag */ -#define USART_STAT0_FERR BIT(1) /*!< frame error flag */ -#define USART_STAT0_NERR BIT(2) /*!< noise error flag */ -#define USART_STAT0_ORERR BIT(3) /*!< overrun error */ -#define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */ -#define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */ -#define USART_STAT0_TC BIT(6) /*!< transmission complete */ -#define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */ -#define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */ -#define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ +#define USART_STAT0_PERR BIT(0) /*!< parity error flag */ +#define USART_STAT0_FERR BIT(1) /*!< frame error flag */ +#define USART_STAT0_NERR BIT(2) /*!< noise error flag */ +#define USART_STAT0_ORERR BIT(3) /*!< overrun error */ +#define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */ +#define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */ +#define USART_STAT0_TC BIT(6) /*!< transmission complete */ +#define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */ +#define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */ +#define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ /* USARTx_DATA */ -#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ +#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ /* USARTx_BAUD */ -#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ -#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ +#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ +#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ /* USARTx_CTL0 */ -#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ -#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ -#define USART_CTL0_REN BIT(2) /*!< receiver enable */ -#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ -#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ -#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ -#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ -#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ -#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ -#define USART_CTL0_PM BIT(9) /*!< parity mode */ -#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ -#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ -#define USART_CTL0_WL BIT(12) /*!< word length */ -#define USART_CTL0_UEN BIT(13) /*!< USART enable */ +#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ +#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ +#define USART_CTL0_REN BIT(2) /*!< enable receiver */ +#define USART_CTL0_TEN BIT(3) /*!< enable transmitter */ +#define USART_CTL0_IDLEIE BIT(4) /*!< enable idle line detected interrupt */ +#define USART_CTL0_RBNEIE BIT(5) /*!< enable read data buffer not empty interrupt and overrun error interrupt */ +#define USART_CTL0_TCIE BIT(6) /*!< enable transmission complete interrupt */ +#define USART_CTL0_TBEIE BIT(7) /*!< enable transmitter buffer empty interrupt */ +#define USART_CTL0_PERRIE BIT(8) /*!< enable parity error interrupt */ +#define USART_CTL0_PM BIT(9) /*!< parity mode */ +#define USART_CTL0_PCEN BIT(10) /*!< enable parity check function */ +#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ +#define USART_CTL0_WL BIT(12) /*!< word length */ +#define USART_CTL0_UEN BIT(13) /*!< enable USART */ /* USARTx_CTL1 */ -#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ -#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ -#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ -#define USART_CTL1_CLEN BIT(8) /*!< CK length */ -#define USART_CTL1_CPH BIT(9) /*!< CK phase */ -#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ -#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ -#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ -#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ +#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ +#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ +#define USART_CTL1_LBDIE BIT(6) /*!< eanble LIN break detected interrupt */ +#define USART_CTL1_CLEN BIT(8) /*!< CK length */ +#define USART_CTL1_CPH BIT(9) /*!< CK phase */ +#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ +#define USART_CTL1_CKEN BIT(11) /*!< enable CK pin */ +#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ +#define USART_CTL1_LMEN BIT(14) /*!< enable LIN mode */ /* USARTx_CTL2 */ -#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ -#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ -#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ -#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ -#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ -#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ -#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ -#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ -#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ -#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ -#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ +#define USART_CTL2_ERRIE BIT(0) /*!< enable error interrupt */ +#define USART_CTL2_IREN BIT(1) /*!< enable IrDA mode */ +#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ +#define USART_CTL2_HDEN BIT(3) /*!< enable half-duplex */ +#define USART_CTL2_NKEN BIT(4) /*!< mode NACK enable in smartcard */ +#define USART_CTL2_SCEN BIT(5) /*!< senable martcard mode */ +#define USART_CTL2_DENR BIT(6) /*!< enable DMA request for reception */ +#define USART_CTL2_DENT BIT(7) /*!< enable DMA request for transmission */ +#define USART_CTL2_RTSEN BIT(8) /*!< enable RTS */ +#define USART_CTL2_CTSEN BIT(9) /*!< enable CTS */ +#define USART_CTL2_CTSIE BIT(10) /*!< enable CTS interrupt */ /* USARTx_GP */ -#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ -#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ - +#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ +#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ + /* USARTx_CTL3 */ -#define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ -#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ -#define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ -#define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ -#define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ -#define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */ -#define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */ -#define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ +#define USART_CTL3_RTEN BIT(0) /*!< enable receiver timeout */ +#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ +#define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ +#define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ +#define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ +#define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */ +#define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */ +#define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ /* USARTx_RT */ -#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ -#define USART_RT_BL BITS(24,31) /*!< block length */ +#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ +#define USART_RT_BL BITS(24,31) /*!< block length */ /* USARTx_STAT1 */ -#define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ -#define USART_STAT1_EBF BIT(12) /*!< end of block flag */ -#define USART_STAT1_BSY BIT(16) /*!< busy flag */ +#define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ +#define USART_STAT1_EBF BIT(12) /*!< end of block flag */ +#define USART_STAT1_BSY BIT(16) /*!< busy flag */ /* constants definitions */ /* define the USART bit position and its register index offset */ @@ -156,36 +153,34 @@ OF SUCH DAMAGE. #define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) /* register offset */ -#define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ -#define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ -#define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ -#define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ -#define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ -#define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */ +#define USART_STAT0_REG_OFFSET ((uint32_t)0x00000000U) /*!< STAT0 register offset */ +#define USART_STAT1_REG_OFFSET ((uint32_t)0x00000088U) /*!< STAT1 register offset */ +#define USART_CTL0_REG_OFFSET ((uint32_t)0x0000000CU) /*!< CTL0 register offset */ +#define USART_CTL1_REG_OFFSET ((uint32_t)0x00000010U) /*!< CTL1 register offset */ +#define USART_CTL2_REG_OFFSET ((uint32_t)0x00000014U) /*!< CTL2 register offset */ +#define USART_CTL3_REG_OFFSET ((uint32_t)0x00000080U) /*!< CTL3 register offset */ /* USART flags */ -typedef enum -{ +typedef enum { /* flags in STAT0 register */ - USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */ - USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */ - USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 7U), /*!< transmit data buffer empty */ - USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete */ - USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty */ - USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ - USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 3U), /*!< overrun error */ - USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 2U), /*!< noise error flag */ - USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 1U), /*!< frame error flag */ - USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 0U), /*!< parity error flag */ + USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */ + USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */ + USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 7U), /*!< transmit data buffer empty */ + USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete */ + USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty */ + USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ + USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 3U), /*!< overrun error */ + USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 2U), /*!< noise error flag */ + USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 1U), /*!< frame error flag */ + USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 0U), /*!< parity error flag */ /* flags in STAT1 register */ - USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U), /*!< busy flag */ - USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U), /*!< end of block flag */ - USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */ -}usart_flag_enum; + USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U), /*!< busy flag */ + USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U), /*!< end of block flag */ + USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U) /*!< receiver timeout flag */ +} usart_flag_enum; /* USART interrupt flags */ -typedef enum -{ +typedef enum { /* interrupt flags in CTL0 register */ USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ @@ -202,12 +197,11 @@ typedef enum USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ /* interrupt flags in CTL3 register */ USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */ - USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */ -}usart_interrupt_flag_enum; + USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U) /*!< interrupt enable bit of receive timeout event and flag */ +} usart_interrupt_flag_enum; /* USART interrupt enable or disable */ -typedef enum -{ +typedef enum { /* interrupt in CTL0 register */ USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ @@ -221,123 +215,115 @@ typedef enum USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ /* interrupt in CTL3 register */ USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< end of block interrupt */ - USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< receive timeout interrupt */ -}usart_interrupt_enum; + USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U) /*!< receive timeout interrupt */ +} usart_interrupt_enum; -/* USART invert configure */ -typedef enum -{ +/* configure USART invert */ +typedef enum { /* data bit level inversion */ - USART_DINV_ENABLE, /*!< data bit level inversion */ - USART_DINV_DISABLE, /*!< data bit level not inversion */ + USART_DINV_ENABLE, /*!< data bit level inversion */ + USART_DINV_DISABLE, /*!< data bit level not inversion */ /* TX pin level inversion */ - USART_TXPIN_ENABLE, /*!< TX pin level inversion */ - USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ + USART_TXPIN_ENABLE, /*!< TX pin level inversion */ + USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ /* RX pin level inversion */ - USART_RXPIN_ENABLE, /*!< RX pin level inversion */ - USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ -}usart_invert_enum; + USART_RXPIN_ENABLE, /*!< RX pin level inversion */ + USART_RXPIN_DISABLE /*!< RX pin level not inversion */ +} usart_invert_enum; -/* USART receiver configure */ +/* configure USART receiver */ #define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ -#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ +#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ +#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ -/* USART transmitter configure */ +/* configure USART transmitter */ #define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) -#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ -#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ +#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ +#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ /* USART parity bits definitions */ #define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) -#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ -#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ -#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ +#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ +#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ +#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ /* USART wakeup method in mute mode */ #define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) -#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ -#define USART_WM_ADDR CTL0_WM(1) /*!< address match */ +#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ +#define USART_WM_ADDR CTL0_WM(1) /*!< address match */ /* USART word length definitions */ #define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) -#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ -#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ +#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ +#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ /* USART stop bits definitions */ #define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) -#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ -#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ -#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ -#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ +#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ +#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ +#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ +#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ /* USART LIN break frame length */ #define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) -#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ -#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ +#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ +#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ /* USART CK length */ #define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ -#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ +#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ +#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ /* USART clock phase */ #define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ -#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ +#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ +#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ /* USART clock polarity */ #define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) -#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ -#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ - -/* USART DMA request for receive configure */ -#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) -#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ -#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ - -/* USART DMA request for transmission configure */ -#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) -#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ -#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ - -/* USART RTS configure */ +#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ +#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ + +/* configure USART DMA */ +#define CLT2_RECEIVE_DMAEN(regval) (BIT(6) & ((uint32_t)(regval) << 6)) +#define CTL2_TRANSMIT_DMAEN(regval) (BIT(7) & ((uint32_t)(regval) << 7)) +#define USART_RECEIVE_DMA_ENABLE CLT2_RECEIVE_DMAEN(1) /* enable DMA request for reception */ +#define USART_RECEIVE_DMA_DISABLE CLT2_RECEIVE_DMAEN(0) /* disable DMA request for reception */ +#define USART_TRANSMIT_DMA_ENABLE CTL2_TRANSMIT_DMAEN(1) /* enable DMA request for transmission */ +#define USART_TRANSMIT_DMA_DISABLE CTL2_TRANSMIT_DMAEN(0) /* disable DMA request for transmission */ + +/* configure USART RTS */ #define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ -#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ +#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< enable RTS */ +#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< disable RTS */ -/* USART CTS configure */ +/* configure USART CTS */ #define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ -#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ +#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< enable CTS */ +#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< disable CTS */ -/* USART IrDA low-power enable */ +/* enable USART IrDA low-power */ #define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ -#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ +#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ +#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ /* USART data is transmitted/received with the LSB/MSB first */ #define CTL3_MSBF(regval) (BIT(11) & ((uint32_t)(regval) << 11)) -#define USART_MSBF_LSB CTL3_MSBF(0) /*!< LSB first */ -#define USART_MSBF_MSB CTL3_MSBF(1) /*!< MSB first */ - - +#define USART_MSBF_LSB CTL3_MSBF(0) /*!< LSB first */ +#define USART_MSBF_MSB CTL3_MSBF(1) /*!< MSB first */ /* function declarations */ /* initialization functions */ -/* reset USART */ +/* reset USART/UART */ void usart_deinit(uint32_t usart_periph); /* configure USART baud rate value */ void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); -/* configure USART parity function */ +/* configure USART parity */ void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); /* configure USART word length */ void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); /* configure USART stop bit length */ void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); - -/* function configuration */ -/* USART normal mode communication */ /* enable USART */ void usart_enable(uint32_t usart_periph); /* disable USART */ @@ -346,9 +332,11 @@ void usart_disable(uint32_t usart_periph); void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); /* configure USART receiver */ void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); + +/* USART normal mode communication */ /* data is transmitted/received with the LSB/MSB first */ void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); -/* configure USART inverted */ +/* configure USART inversion */ void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara); /* enable receiver timeout */ void usart_receiver_timeout_enable(uint32_t usart_periph); @@ -362,7 +350,7 @@ void usart_data_transmit(uint32_t usart_periph, uint16_t data); uint16_t usart_data_receive(uint32_t usart_periph); /* multi-processor communication */ -/* configure address of the USART */ +/* configure the address of the USART in wake up by address match mode */ void usart_address_config(uint32_t usart_periph, uint8_t addr); /* enable mute mode */ void usart_mute_mode_enable(uint32_t usart_periph); @@ -372,44 +360,44 @@ void usart_mute_mode_disable(uint32_t usart_periph); void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); /* LIN mode communication */ -/* LIN mode enable */ +/* enable LIN mode */ void usart_lin_mode_enable(uint32_t usart_periph); -/* LIN mode disable */ +/* disable LIN mode */ void usart_lin_mode_disable(uint32_t usart_periph); -/* LIN break detection length */ +/* configure lin break frame length */ void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); /* send break frame */ void usart_send_break(uint32_t usart_periph); /* half-duplex communication */ -/* half-duplex enable */ +/* enable half-duplex mode */ void usart_halfduplex_enable(uint32_t usart_periph); -/* half-duplex disable */ +/* disable half-duplex mode */ void usart_halfduplex_disable(uint32_t usart_periph); /* synchronous communication */ -/* clock enable */ +/* enable CK pin in synchronous mode */ void usart_synchronous_clock_enable(uint32_t usart_periph); -/* clock disable */ +/* disable CK pin in synchronous mode */ void usart_synchronous_clock_disable(uint32_t usart_periph); -/* configure usart synchronous mode parameters */ +/* configure USART synchronous mode parameters */ void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); /* smartcard communication */ -/* guard time value configure in smartcard mode */ -void usart_guard_time_config(uint32_t usart_periph,uint32_t guat); -/* smartcard mode enable */ +/* configure guard time value in smartcard mode */ +void usart_guard_time_config(uint32_t usart_periph, uint8_t guat); +/* enable smartcard mode */ void usart_smartcard_mode_enable(uint32_t usart_periph); -/* smartcard mode disable */ +/* disable smartcard mode */ void usart_smartcard_mode_disable(uint32_t usart_periph); -/* NACK enable in smartcard mode */ +/* enable NACK in smartcard mode */ void usart_smartcard_mode_nack_enable(uint32_t usart_periph); -/* NACK disable in smartcard mode */ +/* disable NACK in smartcard mode */ void usart_smartcard_mode_nack_disable(uint32_t usart_periph); -/* smartcard auto-retry number configure */ -void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); -/* block length configure */ -void usart_block_length_config(uint32_t usart_periph, uint32_t bl); +/* configure smartcard auto-retry number */ +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint8_t scrtnum); +/* configure block length */ +void usart_block_length_config(uint32_t usart_periph, uint8_t bl); /* IrDA communication */ /* enable IrDA mode */ @@ -427,23 +415,24 @@ void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); /* configure hardware flow control CTS */ void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); -/* configure USART DMA for reception */ -void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); -/* configure USART DMA for transmission */ -void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); +/* DMA communication */ +/* configure USART DMA reception */ +void usart_dma_receive_config(uint32_t usart_periph, uint8_t dmaconfig); +/* configure USART DMA transmission */ +void usart_dma_transmit_config(uint32_t usart_periph, uint8_t dmaconfig); -/* interrupt & flag functions */ +/* flag & interrupt functions */ /* get flag in STAT0/STAT1 register */ FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); /* clear flag in STAT0/STAT1 register */ void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); /* enable USART interrupt */ -void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag); +void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt); /* disable USART interrupt */ -void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag); +void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt); /* get USART interrupt and flag status */ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag); -/* clear interrupt flag in STAT0/STAT1 register */ -void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag); +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); +/* clear USART interrupt flag in STAT0/STAT1 register */ +void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); -#endif /* GD32F20X_USART_H */ +#endif /* GD32F20X_USART_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_wwdgt.h b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_wwdgt.h index 84b2dd26..d483ffc5 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_wwdgt.h +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Include/gd32f20x_wwdgt.h @@ -1,37 +1,34 @@ /*! \file gd32f20x_wwdgt.h - \brief definitions for the WWDGT + \brief definitions for the WWDGT - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -68,24 +65,30 @@ OF SUCH DAMAGE. #define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ #define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ +/* write value to WWDGT_CTL_CNT bit field */ +#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) +/* write value to WWDGT_CFG_WIN bit field */ +#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) + /* function declarations */ /* initialization functions */ /* reset the window watchdog timer configuration */ void wwdgt_deinit(void); /* start the window watchdog timer counter */ void wwdgt_enable(void); - /* configure the window watchdog timer counter value */ void wwdgt_counter_update(uint16_t counter_value); /* configure counter value, window value, and prescaler divider value */ void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); /* interrupt & flag functions */ -/* enable early wakeup interrupt of WWDGT */ -void wwdgt_interrupt_enable(void); -/* check early wakeup interrupt state of WWDGT */ +/* get early wakeup interrupt flag of WWDGT */ +FlagStatus wwdgt_interrupt_flag_get(void); +/* get early wakeup flag of WWDGT */ FlagStatus wwdgt_flag_get(void); /* clear early wakeup interrupt state of WWDGT */ void wwdgt_flag_clear(void); +/* enable early wakeup interrupt of WWDGT */ +void wwdgt_interrupt_enable(void); #endif /* GD32F20X_WWDGT_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_adc.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_adc.c index 3e563616..5b6b2093 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_adc.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_adc.c @@ -2,36 +2,33 @@ \file gd32f20x_adc.c \brief ADC driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -60,14 +57,14 @@ OF SUCH DAMAGE. #define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) /*! - \brief reset ADC + \brief reset ADC \param[in] adc_periph: ADCx, x=0,1,2 \param[out] none \retval none */ void adc_deinit(uint32_t adc_periph) { - switch(adc_periph){ + switch(adc_periph) { case ADC0: /* reset ADC0 */ rcu_periph_reset_enable(RCU_ADC0RST); @@ -125,33 +122,33 @@ void adc_mode_config(uint32_t mode) */ void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus new_value) { - if(new_value){ - if(0U != (function & ADC_SCAN_MODE)){ + if(new_value) { + if(0U != (function & ADC_SCAN_MODE)) { /* enable ADC scan mode */ ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; } - if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)) { /* enable ADC inserted channel group convert automatically */ ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; } - if(0U != (function & ADC_CONTINUOUS_MODE)){ + if(0U != (function & ADC_CONTINUOUS_MODE)) { /* enable ADC continuous mode */ ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; - } - }else{ - if(0U != (function & ADC_SCAN_MODE)){ + } + } else { + if(0U != (function & ADC_SCAN_MODE)) { /* disable scan mode */ ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; } - if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ + if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)) { /* disable ADC inserted channel group convert automatically */ ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; } - if(0U != (function & ADC_CONTINUOUS_MODE)){ + if(0U != (function & ADC_CONTINUOUS_MODE)) { /* disable ADC continuous mode */ ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; } @@ -159,7 +156,7 @@ void adc_special_function_config(uint32_t adc_periph, uint32_t function, Control } /*! - \brief configure ADC data alignment + \brief configure ADC data alignment \param[in] adc_periph: ADCx, x=0,1,2 \param[in] data_alignment: data alignment select only one parameter can be selected which is shown as below: @@ -170,10 +167,10 @@ void adc_special_function_config(uint32_t adc_periph, uint32_t function, Control */ void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment) { - if(ADC_DATAALIGN_RIGHT != data_alignment){ + if(ADC_DATAALIGN_RIGHT != data_alignment) { /* MSB alignment */ ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; - }else{ + } else { /* LSB alignment */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); } @@ -187,7 +184,7 @@ void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment) */ void adc_enable(uint32_t adc_periph) { - if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){ + if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)) { /* enable ADC */ ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; } @@ -216,12 +213,12 @@ void adc_calibration_enable(uint32_t adc_periph) /* reset the selected ADC calibration registers */ ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; /* check the RSTCLB bit state */ - while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ + while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)) { } /* enable ADC calibration process */ ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; /* check the CLB bit state */ - while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){ + while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)) { } } @@ -250,7 +247,7 @@ void adc_tempsensor_vrefint_disable(void) } /*! - \brief enable DMA request + \brief enable DMA request \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected \param[out] none @@ -263,7 +260,7 @@ void adc_dma_mode_enable(uint32_t adc_periph) } /*! - \brief disable DMA request + \brief disable DMA request \param[in] adc_periph: ADCx, x=0,1,2 \param[out] none \retval none @@ -275,7 +272,7 @@ void adc_dma_mode_disable(uint32_t adc_periph) } /*! - \brief configure ADC discontinuous mode + \brief configure ADC discontinuous mode \param[in] adc_periph: ADCx, x=0,1,2 \param[in] adc_channel_group: select the channel group only one parameter can be selected which is shown as below: @@ -291,7 +288,7 @@ void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_grou { /* disable discontinuous mode of regular & inserted channel */ ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); - switch(adc_channel_group){ + switch(adc_channel_group) { case ADC_REGULAR_CHANNEL: /* configure the number of conversions in discontinuous mode */ ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); @@ -304,7 +301,7 @@ void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_grou ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; break; case ADC_CHANNEL_DISCON_DISABLE: - /* disable discontinuous mode of regular & inserted channel */ + /* disable discontinuous mode of regular & inserted channel */ default: break; } @@ -325,7 +322,7 @@ void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_grou */ void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length) { - switch(adc_channel_group){ + switch(adc_channel_group) { case ADC_REGULAR_CHANNEL: /* configure the length of regular channel group */ ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); @@ -348,7 +345,7 @@ void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, u \param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15 \param[in] adc_channel: the selected ADC channel only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx + \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx \param[in] sample_time: the sample time value only one parameter can be selected which is shown as below: \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles @@ -364,56 +361,56 @@ void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, u */ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) { - uint32_t rsq,sampt; - + uint32_t rsq, sampt; + /* configure ADC regular sequence */ - if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){ + if(rank < ADC_REGULAR_CHANNEL_RANK_SIX) { /* the regular group sequence rank is smaller than six */ rsq = ADC_RSQ2(adc_periph); rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH * rank))); /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH * rank)); ADC_RSQ2(adc_periph) = rsq; - }else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE){ + } else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE) { /* the regular group sequence rank is smaller than twelve */ rsq = ADC_RSQ1(adc_periph); rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_SIX)))); /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_SIX))); ADC_RSQ1(adc_periph) = rsq; - }else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN){ + } else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN) { /* the regular group sequence rank is smaller than sixteen */ rsq = ADC_RSQ0(adc_periph); rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_TWELVE)))); /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH * (rank - ADC_REGULAR_CHANNEL_RANK_TWELVE))); ADC_RSQ0(adc_periph) = rsq; - }else{ + } else { /* illegal parameters */ } - + /* configure ADC sampling time */ - if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ + if(adc_channel < ADC_CHANNEL_SAMPLE_TEN) { /* the regular group sequence rank is smaller than ten */ sampt = ADC_SAMPT1(adc_periph); sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel))); /* channel sample time set*/ sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel)); ADC_SAMPT1(adc_periph) = sampt; - }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){ + } else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN) { /* the regular group sequence rank is smaller than eighteen */ sampt = ADC_SAMPT0(adc_periph); sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); /* channel sample time set*/ sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))); ADC_SAMPT0(adc_periph) = sampt; - }else{ - /* illegal parameters */ + } else { + /* illegal parameters */ } } /*! - \brief configure ADC inserted channel + \brief configure ADC inserted channel \param[in] adc_periph: ADCx,x=0,1,2 only one among these parameters can be selected \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 @@ -436,7 +433,7 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) { uint8_t inserted_length; - uint32_t isq,sampt; + uint32_t isq, sampt; /* get inserted channel group length */ inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U); /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */ @@ -445,28 +442,28 @@ void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_ isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH - (inserted_length - rank) * ADC_INSERTED_CHANNEL_RANK_LENGTH)); ADC_ISQ(adc_periph) = isq; - /* ADC sampling time config */ - if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ + /* ADC sampling time config */ + if(adc_channel < ADC_CHANNEL_SAMPLE_TEN) { /* the inserted group sequence rank is smaller than ten */ sampt = ADC_SAMPT1(adc_periph); sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel))); /* channel sample time set*/ sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel); ADC_SAMPT1(adc_periph) = sampt; - }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){ + } else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN) { /* the inserted group sequence rank is smaller than eighteen */ sampt = ADC_SAMPT0(adc_periph); sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); /* channel sample time set*/ sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))); ADC_SAMPT0(adc_periph) = sampt; - }else{ + } else { /* illegal parameters */ } } /*! - \brief configure ADC inserted channel offset + \brief configure ADC inserted channel offset \param[in] adc_periph: ADCx,x=0,1,2 only one among these parameters can be selected \param[in] inserted_channel: insert channel select @@ -486,8 +483,8 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_ch inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U); num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel)); - - if(num <= ADC_OFFSET_LENGTH){ + + if(num <= ADC_OFFSET_LENGTH) { /* calculate the offset of the register */ num = num * ADC_OFFSET_SHIFT_LENGTH; /* configure the offset of the selected channels */ @@ -496,7 +493,7 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_ch } /*! - \brief configure ADC external trigger source + \brief configure ADC external trigger source \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected \param[in] adc_channel_group: select the channel group @@ -518,7 +515,7 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_ch \arg ADC2_EXTTRIG_REGULAR_T1_CH2: TIMER1 CH2 event select \arg ADC2_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select \arg ADC2_EXTTRIG_REGULAR_T7_CH0: TIMER7 CH0 event select - \arg ADC2_EXTTRIG_REGULAR_T7_TRGO: TIMER7 TRGO event select + \arg ADC2_EXTTRIG_REGULAR_T7_TRGO: TIMER7 TRGO event select \arg ADC2_EXTTRIG_REGULAR_T4_CH0: TIMER4 CH0 event select \arg ADC2_EXTTRIG_REGULAR_T4_CH2: TIMER4 CH2 event select \arg ADC0_1_2_EXTTRIG_REGULAR_NONE: software trigger @@ -543,8 +540,8 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_ch \retval none */ void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source) -{ - switch(adc_channel_group){ +{ + switch(adc_channel_group) { case ADC_REGULAR_CHANNEL: /* configure ADC regular group external trigger source */ ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); @@ -561,7 +558,7 @@ void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel } /*! - \brief configure ADC external trigger + \brief configure ADC external trigger \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected \param[in] adc_channel_group: select the channel group @@ -574,23 +571,23 @@ void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel */ void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue) { - if(newvalue){ - if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + if(newvalue) { + if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)) { /* external trigger enable for regular channel */ ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC; } - if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)) { /* external trigger enable for inserted channel */ ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC; } - }else{ - if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + } else { + if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)) { /* external trigger disable for regular channel */ ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC; } - if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)) { /* external trigger disable for inserted channel */ ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC; } @@ -598,7 +595,7 @@ void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, } /*! - \brief enable ADC software trigger + \brief enable ADC software trigger \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected \param[in] adc_channel_group: select the channel group @@ -610,19 +607,19 @@ void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, */ void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group) { - if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)) { /* enable regular group channel software trigger */ ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST; } - if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)) { /* enable inserted channel group software trigger */ ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST; } } /*! - \brief read ADC regular group data register + \brief read ADC regular group data register \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected \param[in] none @@ -635,7 +632,7 @@ uint16_t adc_regular_data_read(uint32_t adc_periph) } /*! - \brief read ADC inserted group data register + \brief read ADC inserted group data register \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected \param[in] inserted_channel: inserted channel select @@ -651,7 +648,7 @@ uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel) { uint32_t idata; /* read the data of the selected channel */ - switch(inserted_channel){ + switch(inserted_channel) { case ADC_INSERTED_CHANNEL_0: /* read the data of channel 0 */ idata = ADC_IDATA0(adc_periph); @@ -688,7 +685,7 @@ uint32_t adc_sync_mode_convert_value_read(void) } /*! - \brief configure ADC analog watchdog single channel + \brief configure ADC analog watchdog single channel \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected \param[in] adc_channel: the selected ADC channel @@ -706,11 +703,11 @@ void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel } /*! - \brief configure ADC analog watchdog group channel + \brief configure ADC analog watchdog group channel \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected \param[in] adc_channel_group: the channel group use analog watchdog - only one parameter can be selected which is shown as below: + only one parameter can be selected which is shown as below: \arg ADC_REGULAR_CHANNEL: regular channel group \arg ADC_INSERTED_CHANNEL: inserted channel group \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group @@ -721,7 +718,7 @@ void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_ { ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); /* select the group */ - switch(adc_channel_group){ + switch(adc_channel_group) { case ADC_REGULAR_CHANNEL: /* regular channel analog watchdog enable */ ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; @@ -740,7 +737,7 @@ void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_ } /*! - \brief disable ADC analog watchdog + \brief disable ADC analog watchdog \param[in] adc_periph: ADCx,x=0,1,2 only one among these parameters can be selected \param[out] none @@ -752,7 +749,7 @@ void adc_watchdog_disable(uint32_t adc_periph) } /*! - \brief configure ADC analog watchdog threshold + \brief configure ADC analog watchdog threshold \param[in] adc_periph: ADCx,x=0,1,2 only one among these parameters can be selected \param[in] low_threshold: analog watchdog low threshold,0..4095 @@ -766,6 +763,95 @@ void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold); } +/*! + \brief configure ADC resolution + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[in] resolution: ADC resolution + only one among these parameters can be selected + \arg ADC_RESOLUTION_12B: 12-bit ADC resolution + \arg ADC_RESOLUTION_10B: 10-bit ADC resolution + \arg ADC_RESOLUTION_8B: 8-bit ADC resolution + \arg ADC_RESOLUTION_6B: 6-bit ADC resolution + \param[out] none + \retval none +*/ +void adc_resolution_config(uint32_t adc_periph, uint32_t resolution) +{ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_DRES); + ADC_OVSAMPCTL(adc_periph) |= (uint32_t)resolution; +} + +/*! + \brief configure ADC oversample mode + \param[in] adc_periph: ADCx, x=0,1,2 + only one among these parameters can be selected + \param[in] mode: ADC oversampling mode + only oneparameter can be selected + \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger + \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger + \param[in] shift: ADC oversampling shift + only oneparameter can be selected + \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift + \param[in] ratio: ADC oversampling ratio + only oneparameter can be selected + \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 + \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 + \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 + \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 + \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 + \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 + \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 + \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 + \param[out] none + \retval none +*/ +void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio) +{ + /* configure ADC oversampling mode */ + if(ADC_OVERSAMPLING_ONE_CONVERT == mode) { + ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS; + } else { + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); + } + + /* configure the shift and ratio */ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS)); + ADC_OVSAMPCTL(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio); +} + +/*! + \brief enable ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[out] none + \retval none +*/ +void adc_oversample_mode_enable(uint32_t adc_periph) +{ + ADC_OVSAMPCTL(adc_periph) |= ADC_OVSAMPCTL_OVSEN; +} + +/*! + \brief disable ADC oversample mode + \param[in] adc_periph: ADCx,x=0,1,2 + only one among these parameters can be selected + \param[out] none + \retval none +*/ +void adc_oversample_mode_disable(uint32_t adc_periph) +{ + ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN); +} + /*! \brief get the ADC flag bits \param[in] adc_periph: ADCx, x=0,1,2 @@ -783,7 +869,7 @@ void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag) { FlagStatus reval = RESET; - if(ADC_STAT(adc_periph) & adc_flag){ + if(ADC_STAT(adc_periph) & adc_flag) { reval = SET; } return reval; @@ -809,70 +895,7 @@ void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag) } /*! - \brief get the ADC interrupt flag - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] adc_interrupt: the adc interrupt bits - only one parameter can be selected which is shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt) -{ - FlagStatus interrupt_flag = RESET; - uint32_t state; - /* check the interrupt bits */ - switch(adc_interrupt){ - case ADC_INT_FLAG_WDE: - /* get the ADC analog watchdog interrupt bits */ - state = ADC_STAT(adc_periph) & ADC_STAT_WDE; - if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){ - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_EOC: - /* get the ADC end of group conversion interrupt bits */ - state = ADC_STAT(adc_periph) & ADC_STAT_EOC; - if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){ - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_EOIC: - /* get the ADC end of inserted group conversion interrupt bits */ - state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; - if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){ - interrupt_flag = SET; - } - break; - default: - break; - } - - return interrupt_flag; -} - -/*! - \brief clear the ADC interrupt flag - \param[in] adc_periph: ADCx, x=0,1,2 - only one among these parameters can be selected - \param[in] adc_interrupt: the adc status flag - one or more parameters can be selected which are shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt - \param[out] none - \retval none -*/ -void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt) -{ - ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); -} - -/*! - \brief enable ADC interrupt + \brief enable ADC interrupt \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected \param[in] adc_interrupt: the adc interrupt @@ -886,21 +909,21 @@ void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt) void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) { /* enable ADC analog watchdog interrupt */ - if(0U != (adc_interrupt & ADC_INT_WDE)){ + if(0U != (adc_interrupt & ADC_INT_WDE)) { ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; - } + } /* enable ADC end of group conversion interrupt */ - if(0U != (adc_interrupt & ADC_INT_EOC)){ + if(0U != (adc_interrupt & ADC_INT_EOC)) { ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; - } + } /* enable ADC end of inserted group conversion interrupt */ - if(0U != (adc_interrupt & ADC_INT_EOIC)){ + if(0U != (adc_interrupt & ADC_INT_EOIC)) { ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; } } /*! - \brief disable ADC interrupt + \brief disable ADC interrupt \param[in] adc_periph: ADCx,x=0,1,2 only one among these parameters can be selected \param[in] adc_interrupt: the adc interrupt flag @@ -912,108 +935,81 @@ void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) \retval none */ void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) -{ +{ /* disable ADC analog watchdog interrupt */ - if(0U != (adc_interrupt & ADC_INT_WDE)){ + if(0U != (adc_interrupt & ADC_INT_WDE)) { ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE; - } + } /* disable ADC end of group conversion interrupt */ - if(0U != (adc_interrupt & ADC_INT_EOC)){ + if(0U != (adc_interrupt & ADC_INT_EOC)) { ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE; - } + } /* disable ADC end of inserted group conversion interrupt */ - if(0U != (adc_interrupt & ADC_INT_EOIC)){ + if(0U != (adc_interrupt & ADC_INT_EOIC)) { ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE; } } - - /*! - \brief configure ADC resolution + \brief get the ADC interrupt flag \param[in] adc_periph: ADCx,x=0,1,2 only one among these parameters can be selected - \param[in] resolution: ADC resolution - only one among these parameters can be selected - \arg ADC_RESOLUTION_12B: 12-bit ADC resolution - \arg ADC_RESOLUTION_10B: 10-bit ADC resolution - \arg ADC_RESOLUTION_8B: 8-bit ADC resolution - \arg ADC_RESOLUTION_6B: 6-bit ADC resolution - \param[out] none - \retval none -*/ -void adc_resolution_config(uint32_t adc_periph, uint32_t resolution) -{ - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_DRES); - ADC_OVSAMPCTL(adc_periph) |= (uint32_t)resolution; -} - -/*! - \brief configure ADC oversample mode - \param[in] adc_periph: ADCx, x=0,1,2 - only one among these parameters can be selected - \param[in] mode: ADC oversampling mode - only oneparameter can be selected - \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger - \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger - \param[in] shift: ADC oversampling shift - only oneparameter can be selected - \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift - \param[in] ratio: ADC oversampling ratio - only oneparameter can be selected - \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 - \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 - \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 - \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 - \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 - \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 - \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 - \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 + \param[in] adc_interrupt: the adc interrupt bits + only one parameter can be selected which is shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt \param[out] none - \retval none + \retval FlagStatus: SET or RESET */ -void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio) +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt) { - /* configure ADC oversampling mode */ - if(ADC_OVERSAMPLING_ONE_CONVERT == mode){ - ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS; - }else{ - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); + FlagStatus interrupt_flag = RESET; + uint32_t state; + /* check the interrupt bits */ + switch(adc_interrupt) { + case ADC_INT_FLAG_WDE: + /* get the ADC analog watchdog interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_WDE; + if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state) { + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOC: + /* get the ADC end of group conversion interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_EOC; + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state) { + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOIC: + /* get the ADC end of inserted group conversion interrupt bits */ + state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; + if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state) { + interrupt_flag = SET; + } + break; + default: + break; } - - /* configure the shift and ratio */ - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS)); - ADC_OVSAMPCTL(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio); -} -/*! - \brief enable ADC oversample mode - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[out] none - \retval none -*/ -void adc_oversample_mode_enable(uint32_t adc_periph) -{ - ADC_OVSAMPCTL(adc_periph) |= ADC_OVSAMPCTL_OVSEN; + return interrupt_flag; } /*! - \brief disable ADC oversample mode - \param[in] adc_periph: ADCx,x=0,1,2 + \brief clear the ADC interrupt flag + \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected + \param[in] adc_interrupt: the adc status flag + one or more parameters can be selected which are shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt \param[out] none \retval none */ -void adc_oversample_mode_disable(uint32_t adc_periph) +void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt) { - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN); + ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); } + diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_bkp.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_bkp.c index c6081cc5..687d4464 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_bkp.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_bkp.c @@ -2,43 +2,41 @@ \file gd32f20x_bkp.c \brief BKP driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f20x_bkp.h" -#define TAMPER0_FLAG_SHIFT ((uint8_t)8U) -#define TAMPER1_FLAG_SHIFT ((uint8_t)9U) +#define TAMPER0_FLAG_SHIFT ((uint8_t)0x08U) +#define TAMPER1_FLAG_SHIFT ((uint8_t)0x09U) +#define TAMPER1_PIN_SHIFT ((uint8_t)0x08U) /*! \brief reset BKP registers @@ -64,11 +62,11 @@ void bkp_deinit(void) */ void bkp_data_write(bkp_data_register_enum register_number, uint16_t data) { - if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ + if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)) { BKP_DATA10_41(register_number - 1U) = data; - }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ + } else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)) { BKP_DATA0_9(register_number - 1U) = data; - }else{ + } else { /* illegal parameters */ } } @@ -84,13 +82,13 @@ void bkp_data_write(bkp_data_register_enum register_number, uint16_t data) uint16_t bkp_data_read(bkp_data_register_enum register_number) { uint16_t data = 0U; - + /* get the data from the BKP data register */ - if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ + if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)) { data = BKP_DATA10_41(register_number - 1U); - }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ + } else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)) { data = BKP_DATA0_9(register_number - 1U); - }else{ + } else { /* illegal parameters */ } return data; @@ -152,7 +150,7 @@ void bkp_rtc_signal_output_disable(void) void bkp_rtc_output_select(uint16_t outputsel) { uint16_t ctl = 0U; - + ctl = BKP_OCTL; ctl &= (uint16_t)~BKP_OCTL_ROSEL; ctl |= outputsel; @@ -160,8 +158,9 @@ void bkp_rtc_output_select(uint16_t outputsel) } /*! - \brief select RTC clock output + \brief RTC clock output selection \param[in] clocksel: RTC clock output selection + only one parameter can be selected which is shown as below: \arg RTC_CLOCK_DIV64: RTC clock div 64 \arg RTC_CLOCK_DIV1: RTC clock \param[out] none @@ -170,7 +169,7 @@ void bkp_rtc_output_select(uint16_t outputsel) void bkp_rtc_clock_output_select(uint16_t clocksel) { uint16_t ctl = 0U; - + ctl = BKP_OCTL; ctl &= (uint16_t)~BKP_OCTL_CCOSEL; ctl |= clocksel; @@ -180,7 +179,8 @@ void bkp_rtc_clock_output_select(uint16_t clocksel) /*! \brief RTC clock calibration direction \param[in] direction: RTC clock calibration direction - \arg RTC_CLOCK_SLOWED_DOWN: RTC clock slow down + only one parameter can be selected which is shown as below: + \arg RTC_CLOCK_SLOW_DOWN: RTC clock slow down \arg RTC_CLOCK_SPEED_UP: RTC clock speed up \param[out] none \retval none @@ -188,7 +188,7 @@ void bkp_rtc_clock_output_select(uint16_t clocksel) void bkp_rtc_clock_calibration_direction(uint16_t direction) { uint16_t ctl = 0U; - + ctl = BKP_OCTL; ctl &= (uint16_t)~BKP_OCTL_CALDIR; ctl |= direction; @@ -196,7 +196,7 @@ void bkp_rtc_clock_calibration_direction(uint16_t direction) } /*! - \brief set RTC clock calibration value + \brief set RTC clock calibration value \param[in] value: RTC clock calibration value \arg 0x00 - 0x7F \param[out] none @@ -205,7 +205,7 @@ void bkp_rtc_clock_calibration_direction(uint16_t direction) void bkp_rtc_calibration_value_set(uint8_t value) { uint16_t ctl; - + /* configure BKP_OCTL_RCCV with value */ ctl = BKP_OCTL; ctl &= (uint16_t)OCTL_RCCV(0); @@ -214,8 +214,9 @@ void bkp_rtc_calibration_value_set(uint8_t value) } /*! - \brief enable tamper detection - \param[in] tamperx + \brief enable tamper pin detection + \param[in] tamperx: BKP tamperx + only one parameter can be selected which is shown as below: \arg TAMPER_0: BKP tamper0 \arg TAMPER_1: BKP tamper1 \param[out] none @@ -223,16 +224,17 @@ void bkp_rtc_calibration_value_set(uint8_t value) */ void bkp_tamper_detection_enable(bkp_tamper_enum tamperx) { - if(TAMPER_0 == tamperx){ + if(TAMPER_0 == tamperx) { BKP_TPCTL0 |= (uint16_t)BKP_TPCTL0_TPEN0; - }else{ + } else { BKP_TPCTL1 |= (uint16_t)BKP_TPCTL1_TPEN1; } } /*! - \brief disable tamper detection - \param[in] tamperx + \brief disable tamper pin detection + \param[in] tamperx: BKP tamperx + only one parameter can be selected which is shown as below: \arg TAMPER_0: BKP tamper0 \arg TAMPER_1: BKP tamper1 \param[out] none @@ -240,19 +242,21 @@ void bkp_tamper_detection_enable(bkp_tamper_enum tamperx) */ void bkp_tamper_detection_disable(bkp_tamper_enum tamperx) { - if(TAMPER_0 == tamperx){ + if(TAMPER_0 == tamperx) { BKP_TPCTL0 &= (uint16_t)~BKP_TPCTL0_TPEN0; - }else{ + } else { BKP_TPCTL1 &= (uint16_t)~BKP_TPCTL1_TPEN1; } } /*! \brief set tamper pin active level - \param[in] tamperx + \param[in] tamperx: BKP tamperx + only one parameter can be selected which is shown as below: \arg TAMPER_0: BKP tamper0 \arg TAMPER_1: BKP tamper1 - \param[in] level: tamper active level + \param[in] level: tamper pin active level + only one parameter can be selected which is shown as below: \arg TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high \arg TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low \param[out] none @@ -262,69 +266,36 @@ void bkp_tamper_active_level_set(bkp_tamper_enum tamperx, uint16_t level) { uint16_t ctl = 0U; - if(TAMPER_0 == tamperx){ + if(TAMPER_0 == tamperx) { ctl = BKP_TPCTL0; ctl &= (uint16_t)~BKP_TPCTL0_TPAL0; ctl |= level; BKP_TPCTL0 = ctl; - }else{ + } else { ctl = BKP_TPCTL1; ctl &= (uint16_t)~BKP_TPCTL1_TPAL1; - ctl |= level; + ctl |= (uint16_t)(level << TAMPER1_PIN_SHIFT); BKP_TPCTL1 = ctl; } } -/*! - \brief enable tamper interrupt - \param[in] tamperx - \arg TAMPER_0: BKP tamper0 - \arg TAMPER_1: BKP tamper1 - \param[out] none - \retval none -*/ -void bkp_tamper_interrupt_enable(bkp_tamper_enum tamperx) -{ - if(TAMPER_0 == tamperx){ - BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE0; - }else{ - BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE1; - } -} - -/*! - \brief disable tamper interrupt - \param[in] tamperx - \arg TAMPER_0: BKP tamper0 - \arg TAMPER_1: BKP tamper1 - \param[out] none - \retval none -*/ -void bkp_tamper_interrupt_disable(bkp_tamper_enum tamperx) -{ - if(TAMPER_0 == tamperx){ - BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE0; - }else{ - BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE1; - } -} - /*! \brief waveform detect configure - \param[in] waveform_detect_mode + \param[in] waveform_detect_mode: + only one parameter can be selected which is shown as below: \arg BKP_WAVEFORM_DETECT_1: the first waveform detection \arg BKP_WAVEFORM_DETECT_2: the second waveform detection \param[in] newvalue: ENABLE or DISABLE \param[out] none - \retval FlagStatus: SET or RESET + \retval none */ -void bkp_waveform_detect_enable(uint16_t waveform_detect_mode, ControlStatus newvalue) +void bkp_waveform_detect_config(uint16_t waveform_detect_mode, ControlStatus newvalue) { uint16_t tpctl0 = 0U, tpctl1 = 0U, octl = 0U; - + tpctl0 = BKP_TPCTL0; tpctl1 = BKP_TPCTL1; - + /* disable tamper0 and tamper1 */ tpctl0 &= (uint16_t)~BKP_TPCTL0_TPEN0; tpctl1 &= (uint16_t)~BKP_TPCTL1_TPEN1; @@ -339,54 +310,99 @@ void bkp_waveform_detect_enable(uint16_t waveform_detect_mode, ControlStatus new BKP_TPCTL1 = tpctl1; BKP_OCTL = octl; - if(DISABLE != newvalue){ + if(DISABLE != newvalue) { /* enable the waveform detection function */ BKP_TPCTL1 |= waveform_detect_mode; - }else{ + } else { /* disable the waveform detection function */ BKP_TPCTL1 &= (uint16_t)(~waveform_detect_mode); } } /*! - \brief get bkp flag state - \param[in] flag + \brief get BKP flag + \param[in] flag: + only one parameter can be selected which is shown as below: \arg BKP_FLAG_TAMPER0: tamper0 event flag - \arg BKP_FLAG_TAMPER1_WAVEDETECT: tamper1/wavedetect event flag + \arg BKP_FLAG_TAMPER1_WAVEDETECT: tamper1/waveform detect event flag \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus bkp_flag_get(uint16_t flag) { - if(RESET != (BKP_TPCS & flag)){ + if(RESET != (BKP_TPCS & flag)) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear bkp flag state - \param[in] flag + \brief clear BKP flag + \param[in] flag: + only one parameter can be selected which is shown as below: \arg BKP_FLAG_TAMPER0: tamper0 event flag - \arg BKP_FLAG_TAMPER1_WAVEDETECT: tamper1/wavedetect event flag + \arg BKP_FLAG_TAMPER1_WAVEDETECT: tamper1/waveform detect event flag \param[out] none \retval none */ void bkp_flag_clear(uint16_t flag) { - if(BKP_FLAG_TAMPER0 == flag){ + if(BKP_FLAG_TAMPER0 == flag) { BKP_TPCS |= (uint16_t)(flag >> TAMPER0_FLAG_SHIFT); - }else if(BKP_FLAG_TAMPER1_WAVEDETECT == flag){ + } else if(BKP_FLAG_TAMPER1_WAVEDETECT == flag) { BKP_TPCS |= (uint16_t)(flag >> TAMPER1_FLAG_SHIFT); - }else{ + } else { /* illegal parameters */ } } /*! - \brief get bkp interrupt flag state - \param[in] flag + \brief enable tamper interrupt + \param[in] bkp_interrupt: the BKP interrupt + only one parameter can be selected which is shown as below: + \arg BKP_INT_TAMPER0: BKP tamper0 interrupt + \arg BKP_INT_TAMPER1_WAVEDETECT: BKP tamper1/waveform detect interrupt + \param[out] none + \retval none +*/ +void bkp_tamper_interrupt_enable(uint16_t bkp_interrupt) +{ + /* enable BKP tamper0 interrupt */ + if(0U != (bkp_interrupt & BKP_TPCS_TPIE0)) { + BKP_TPCS |= (uint16_t) BKP_TPCS_TPIE0; + } + /* enable BKP tamper1/waveform detect interrupt */ + if(0U != (bkp_interrupt & BKP_TPCS_TPIE1)) { + BKP_TPCS |= (uint16_t) BKP_TPCS_TPIE1; + } +} + +/*! + \brief disable tamper interrupt + \param[in] bkp_interrupt: the BKP interrupt + only one parameter can be selected which is shown as below: + \arg BKP_INT_TAMPER0: BKP tamper0 interrupt + \arg BKP_INT_TAMPER1_WAVEDETECT: BKP tamper1/waveform detect interrupt + \param[out] none + \retval none +*/ +void bkp_tamper_interrupt_disable(uint16_t bkp_interrupt) +{ + /* disable BKP tamper0 interrupt */ + if(0U != (bkp_interrupt & BKP_TPCS_TPIE0)) { + BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE0; + } + /* disable BKP tamper1/waveform detect interrupt */ + if(0U != (bkp_interrupt & BKP_TPCS_TPIE1)) { + BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE1; + } +} + +/*! + \brief get BKP interrupt flag + \param[in] flag: + only one parameter can be selected which is shown as below: \arg BKP_INT_FLAG_TAMPER0: tamper0 interrupt flag \arg BKP_INT_FLAG_TAMPER1_WAVEDETECT: tamper1/waveform detect interrupt flag \param[out] none @@ -394,16 +410,17 @@ void bkp_flag_clear(uint16_t flag) */ FlagStatus bkp_interrupt_flag_get(uint16_t flag) { - if(RESET != (BKP_TPCS & flag)){ + if(RESET != (BKP_TPCS & flag)) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear bkp interrupt flag state - \param[in] flag + \brief clear BKP interrupt flag + \param[in] flag: + only one parameter can be selected which is shown as below: \arg BKP_INT_FLAG_TAMPER0: tamper0 interrupt flag \arg BKP_INT_FLAG_TAMPER1_WAVEDETECT: tamper1/waveform detect interrupt flag \param[out] none @@ -411,11 +428,11 @@ FlagStatus bkp_interrupt_flag_get(uint16_t flag) */ void bkp_interrupt_flag_clear(uint16_t flag) { - if(BKP_INT_FLAG_TAMPER0 == flag){ + if(BKP_INT_FLAG_TAMPER0 == flag) { BKP_TPCS |= (uint16_t)(flag >> TAMPER0_FLAG_SHIFT); - }else if(BKP_INT_FLAG_TAMPER1_WAVEDETECT == flag){ + } else if(BKP_INT_FLAG_TAMPER1_WAVEDETECT == flag) { BKP_TPCS |= (uint16_t)(flag >> TAMPER1_FLAG_SHIFT); - }else{ + } else { /* illegal parameters */ } } diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_can.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_can.c index b1a3abee..c3fa0079 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_can.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_can.c @@ -2,61 +2,56 @@ \file gd32f20x_can.c \brief CAN driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2019-11-27, V2.1.1, firmware for GD32F20x - \version 2020-07-14, V2.1.2, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f20x_can.h" #define CAN_ERROR_HANDLE(s) do{}while(1) - -#define RFO1_CLEAR_VAL ((uint32_t)0x00000000U) /*!< RFO1 clear value */ -#define RFF1_CLEAR_VAL ((uint32_t)0x00000018U) /*!< RFF1 clear value */ + +#define RFO1_CLEAR_VAL ((uint32_t)0x00000000U) /*!< RFO1 clear value */ +#define RFF1_CLEAR_VAL ((uint32_t)0x00000018U) /*!< RFF1 clear value */ /*! - \brief deinitialize CAN + \brief deinitialize CAN \param[in] can_periph - \arg CANx(x=0,1) + \arg CANx(x=0,1) \param[out] none \retval none */ void can_deinit(uint32_t can_periph) { - if(CAN0 == can_periph){ + if(CAN0 == can_periph) { rcu_periph_reset_enable(RCU_CAN0RST); rcu_periph_reset_disable(RCU_CAN0RST); - }else{ + } else { rcu_periph_reset_enable(RCU_CAN1RST); rcu_periph_reset_disable(RCU_CAN1RST); } @@ -64,7 +59,7 @@ void can_deinit(uint32_t can_periph) /*! \brief initialize CAN parameter struct with a default value - \param[in] type: the type of CAN parameter struct + \param[in] type: the type of CAN parameter struct only one parameter can be selected which is shown as below: \arg CAN_INIT_STRUCT: the CAN initial struct \arg CAN_FILTER_STRUCT: the CAN filter struct @@ -77,67 +72,71 @@ void can_deinit(uint32_t can_periph) void can_struct_para_init(can_struct_type_enum type, void* p_struct) { uint8_t i; - + + if(NULL == p_struct){ + CAN_ERROR_HANDLE("struct parameter can not be NULL \r\n"); + } + /* get type of the struct */ - switch(type){ - /* used for can_init() */ - case CAN_INIT_STRUCT: - ((can_parameter_struct*)p_struct)->auto_bus_off_recovery = DISABLE; - ((can_parameter_struct*)p_struct)->no_auto_retrans = DISABLE; - ((can_parameter_struct*)p_struct)->auto_wake_up = DISABLE; - ((can_parameter_struct*)p_struct)->prescaler = 0x03FFU; - ((can_parameter_struct*)p_struct)->rec_fifo_overwrite = DISABLE; - ((can_parameter_struct*)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; - ((can_parameter_struct*)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; - ((can_parameter_struct*)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; - ((can_parameter_struct*)p_struct)->time_triggered = DISABLE; - ((can_parameter_struct*)p_struct)->trans_fifo_order = DISABLE; - ((can_parameter_struct*)p_struct)->working_mode = CAN_NORMAL_MODE; - - break; - /* used for can_filter_init() */ - case CAN_FILTER_STRUCT: - ((can_filter_parameter_struct*)p_struct)->filter_bits = CAN_FILTERBITS_32BIT; - ((can_filter_parameter_struct*)p_struct)->filter_enable = DISABLE; - ((can_filter_parameter_struct*)p_struct)->filter_fifo_number = CAN_FIFO0; - ((can_filter_parameter_struct*)p_struct)->filter_list_high = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_list_low = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mask_high = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mask_low = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mode = CAN_FILTERMODE_MASK; - ((can_filter_parameter_struct*)p_struct)->filter_number = 0U; - - break; - /* used for can_message_transmit() */ - case CAN_TX_MESSAGE_STRUCT: - for(i = 0U; i < 8U; i++){ - ((can_trasnmit_message_struct*)p_struct)->tx_data[i] = 0U; - } - - ((can_trasnmit_message_struct*)p_struct)->tx_dlen = 0u; - ((can_trasnmit_message_struct*)p_struct)->tx_efid = 0U; - ((can_trasnmit_message_struct*)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; - ((can_trasnmit_message_struct*)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; - ((can_trasnmit_message_struct*)p_struct)->tx_sfid = 0U; - - break; - /* used for can_message_receive() */ - case CAN_RX_MESSAGE_STRUCT: - for(i = 0U; i < 8U; i++){ - ((can_receive_message_struct*)p_struct)->rx_data[i] = 0U; - } - - ((can_receive_message_struct*)p_struct)->rx_dlen = 0U; - ((can_receive_message_struct*)p_struct)->rx_efid = 0U; - ((can_receive_message_struct*)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD; - ((can_receive_message_struct*)p_struct)->rx_fi = 0U; - ((can_receive_message_struct*)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA; - ((can_receive_message_struct*)p_struct)->rx_sfid = 0U; - - break; - - default: - CAN_ERROR_HANDLE("parameter is invalid \r\n"); + switch(type) { + /* used for can_init() */ + case CAN_INIT_STRUCT: + ((can_parameter_struct *)p_struct)->auto_bus_off_recovery = DISABLE; + ((can_parameter_struct *)p_struct)->auto_retrans = DISABLE; + ((can_parameter_struct *)p_struct)->auto_wake_up = DISABLE; + ((can_parameter_struct *)p_struct)->prescaler = 0x03FFU; + ((can_parameter_struct *)p_struct)->rec_fifo_overwrite = DISABLE; + ((can_parameter_struct *)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; + ((can_parameter_struct *)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; + ((can_parameter_struct *)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; + ((can_parameter_struct *)p_struct)->time_triggered = DISABLE; + ((can_parameter_struct *)p_struct)->trans_fifo_order = DISABLE; + ((can_parameter_struct *)p_struct)->working_mode = CAN_NORMAL_MODE; + + break; + /* used for can_filter_init() */ + case CAN_FILTER_STRUCT: + ((can_filter_parameter_struct *)p_struct)->filter_bits = CAN_FILTERBITS_32BIT; + ((can_filter_parameter_struct *)p_struct)->filter_enable = DISABLE; + ((can_filter_parameter_struct *)p_struct)->filter_fifo_number = CAN_FIFO0; + ((can_filter_parameter_struct *)p_struct)->filter_list_high = 0x0000U; + ((can_filter_parameter_struct *)p_struct)->filter_list_low = 0x0000U; + ((can_filter_parameter_struct *)p_struct)->filter_mask_high = 0x0000U; + ((can_filter_parameter_struct *)p_struct)->filter_mask_low = 0x0000U; + ((can_filter_parameter_struct *)p_struct)->filter_mode = CAN_FILTERMODE_MASK; + ((can_filter_parameter_struct *)p_struct)->filter_number = 0U; + + break; + /* used for can_message_transmit() */ + case CAN_TX_MESSAGE_STRUCT: + for(i = 0U; i < 8U; i++) { + ((can_trasnmit_message_struct *)p_struct)->tx_data[i] = 0U; + } + + ((can_trasnmit_message_struct *)p_struct)->tx_dlen = 0u; + ((can_trasnmit_message_struct *)p_struct)->tx_efid = 0U; + ((can_trasnmit_message_struct *)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_trasnmit_message_struct *)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; + ((can_trasnmit_message_struct *)p_struct)->tx_sfid = 0U; + + break; + /* used for can_message_receive() */ + case CAN_RX_MESSAGE_STRUCT: + for(i = 0U; i < 8U; i++) { + ((can_receive_message_struct *)p_struct)->rx_data[i] = 0U; + } + + ((can_receive_message_struct *)p_struct)->rx_dlen = 0U; + ((can_receive_message_struct *)p_struct)->rx_efid = 0U; + ((can_receive_message_struct *)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_receive_message_struct *)p_struct)->rx_fi = 0U; + ((can_receive_message_struct *)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA; + ((can_receive_message_struct *)p_struct)->rx_sfid = 0U; + + break; + + default: + CAN_ERROR_HANDLE("parameter is invalid \r\n"); } } @@ -153,7 +152,7 @@ void can_struct_para_init(can_struct_type_enum type, void* p_struct) \arg time_triggered: ENABLE or DISABLE \arg auto_bus_off_recovery: ENABLE or DISABLE \arg auto_wake_up: ENABLE or DISABLE - \arg no_auto_retrans: ENABLE or DISABLE + \arg auto_retrans: ENABLE or DISABLE \arg rec_fifo_overwrite: ENABLE or DISABLE \arg trans_fifo_order: ENABLE or DISABLE \arg prescaler: 0x0001 - 0x0400 @@ -164,158 +163,159 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init { uint32_t timeout = CAN_TIMEOUT; ErrStatus flag = ERROR; - + /* disable sleep mode */ CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; /* enable initialize mode */ CAN_CTL(can_periph) |= CAN_CTL_IWMOD; /* wait ACK */ - while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { timeout--; } /* check initialize working success */ - if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ + if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) { flag = ERROR; - }else{ + } else { /* set the bit timing register */ CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \ BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \ BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \ BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \ BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U))); + /* time trigger communication mode */ - if(ENABLE == can_parameter_init->time_triggered){ + if(ENABLE == can_parameter_init->time_triggered) { CAN_CTL(can_periph) |= CAN_CTL_TTC; - }else{ + } else { CAN_CTL(can_periph) &= ~CAN_CTL_TTC; } - /* automatic bus-off managment */ - if(ENABLE == can_parameter_init->auto_bus_off_recovery){ + /* automatic bus-off management */ + if(ENABLE == can_parameter_init->auto_bus_off_recovery) { CAN_CTL(can_periph) |= CAN_CTL_ABOR; - }else{ + } else { CAN_CTL(can_periph) &= ~CAN_CTL_ABOR; } /* automatic wakeup mode */ - if(ENABLE == can_parameter_init->auto_wake_up){ + if(ENABLE == can_parameter_init->auto_wake_up) { CAN_CTL(can_periph) |= CAN_CTL_AWU; - }else{ + } else { CAN_CTL(can_periph) &= ~CAN_CTL_AWU; } - /* automatic retransmission mode disable*/ - if(ENABLE == can_parameter_init->no_auto_retrans){ - CAN_CTL(can_periph) |= CAN_CTL_ARD; - }else{ + /* automatic retransmission mode disable */ + if(ENABLE == can_parameter_init->auto_retrans) { CAN_CTL(can_periph) &= ~CAN_CTL_ARD; + } else { + CAN_CTL(can_periph) |= CAN_CTL_ARD; } - /* receive fifo overwrite mode */ - if(ENABLE == can_parameter_init->rec_fifo_overwrite){ - CAN_CTL(can_periph) |= CAN_CTL_RFOD; - }else{ + /* receive fifo overwrite mode */ + if(ENABLE == can_parameter_init->rec_fifo_overwrite) { CAN_CTL(can_periph) &= ~CAN_CTL_RFOD; - } + } else { + CAN_CTL(can_periph) |= CAN_CTL_RFOD; + } /* transmit fifo order */ - if(ENABLE == can_parameter_init->trans_fifo_order){ + if(ENABLE == can_parameter_init->trans_fifo_order) { CAN_CTL(can_periph) |= CAN_CTL_TFO; - }else{ + } else { CAN_CTL(can_periph) &= ~CAN_CTL_TFO; - } + } /* disable initialize mode */ CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; timeout = CAN_TIMEOUT; /* wait the ACK */ - while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ + while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { timeout--; } /* check exit initialize mode */ - if(0U != timeout){ + if(0U != timeout) { flag = SUCCESS; } - } + } return flag; } /*! - \brief initialize CAN filter + \brief initialize CAN filter \param[in] can_filter_parameter_init: struct for CAN filter initialization \arg filter_list_high: 0x0000 - 0xFFFF \arg filter_list_low: 0x0000 - 0xFFFF \arg filter_mask_high: 0x0000 - 0xFFFF \arg filter_mask_low: 0x0000 - 0xFFFF - \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 + \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 \arg filter_number: 0 - 27 \arg filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST - \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT + \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT \arg filter_enable: ENABLE or DISABLE \param[out] none \retval none */ -void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) +void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init) { uint32_t val = 0U; - + val = ((uint32_t)1) << (can_filter_parameter_init->filter_number); /* filter lock disable */ CAN_FCTL(CAN0) |= CAN_FCTL_FLD; /* disable filter */ CAN_FW(CAN0) &= ~(uint32_t)val; - + /* filter 16 bits */ - if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){ + if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits) { /* set filter 16 bits */ CAN_FSCFG(CAN0) &= ~(uint32_t)val; /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */ CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \ - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \ + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */ CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \ - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS); + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \ + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS); } /* filter 32 bits */ - if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits){ + if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits) { /* set filter 32 bits */ CAN_FSCFG(CAN0) |= (uint32_t)val; /* 32 bits list or first 32 bits list */ CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); + FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | + FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); /* 32 bits mask or second 32 bits list */ CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | - FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); + FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | + FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); } - + /* filter mode */ - if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){ + if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode) { /* mask mode */ CAN_FMCFG(CAN0) &= ~(uint32_t)val; - }else{ + } else { /* list mode */ CAN_FMCFG(CAN0) |= (uint32_t)val; } - + /* filter FIFO */ - if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){ + if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)) { /* FIFO0 */ CAN_FAFIFO(CAN0) &= ~(uint32_t)val; - }else{ + } else { /* FIFO1 */ CAN_FAFIFO(CAN0) |= (uint32_t)val; } - + /* filter working */ - if(ENABLE == can_filter_parameter_init->filter_enable){ - + if(ENABLE == can_filter_parameter_init->filter_enable) { + CAN_FW(CAN0) |= (uint32_t)val; } - + /* filter lock enable */ CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; } /*! - \brief set CAN1 fliter start bank number + \brief set CAN1 filter start bank number \param[in] start_bank: CAN1 start bank number only one parameter can be selected which is shown as below: \arg (1..27) @@ -329,14 +329,14 @@ void can1_filter_start_bank(uint8_t start_bank) /* set CAN1 filter start number */ CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F; CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank); - /* filter lock enaable */ + /* filter lock enable */ CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; } /*! \brief enable CAN debug freeze \param[in] can_periph - \arg CANx(x=0,1) + \arg CANx(x=0,1) \param[out] none \retval none */ @@ -345,9 +345,9 @@ void can_debug_freeze_enable(uint32_t can_periph) /* set DFZ bit */ CAN_CTL(can_periph) |= CAN_CTL_DFZ; - if(CAN0 == can_periph){ + if(CAN0 == can_periph) { dbg_periph_enable(DBG_CAN0_HOLD); - }else{ + } else { dbg_periph_enable(DBG_CAN1_HOLD); } } @@ -364,9 +364,9 @@ void can_debug_freeze_disable(uint32_t can_periph) /* set DFZ bit */ CAN_CTL(can_periph) &= ~CAN_CTL_DFZ; - if(CAN0 == can_periph){ + if(CAN0 == can_periph) { dbg_periph_disable(DBG_CAN0_HOLD); - }else{ + } else { dbg_periph_disable(DBG_CAN1_HOLD); } } @@ -381,11 +381,11 @@ void can_debug_freeze_disable(uint32_t can_periph) void can_time_trigger_mode_enable(uint32_t can_periph) { uint8_t mailbox_number; - - /* enable the tcc mode */ + + /* enable the TTC mode */ CAN_CTL(can_periph) |= CAN_CTL_TTC; /* enable time stamp */ - for(mailbox_number=0U; mailbox_number<3U; mailbox_number++){ + for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) { CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN; } } @@ -399,20 +399,20 @@ void can_time_trigger_mode_enable(uint32_t can_periph) */ void can_time_trigger_mode_disable(uint32_t can_periph) { - uint8_t mailbox_number; - - /* disable the TCC mode */ + uint8_t mailbox_number; + + /* disable the TTC mode */ CAN_CTL(can_periph) &= ~CAN_CTL_TTC; /* reset TSEN bits */ - for(mailbox_number=0U; mailbox_number<3U; mailbox_number++){ + for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) { CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN; } } /*! - \brief transmit CAN message + \brief transmit CAN message \param[in] can_periph - \arg CANx(x=0,1) + \arg CANx(x=0,1) \param[in] transmit_message: struct for CAN transmit message \arg tx_sfid: 0x00000000 - 0x000007FF \arg tx_efid: 0x00000000 - 0x1FFFFFFF @@ -423,48 +423,48 @@ void can_time_trigger_mode_disable(uint32_t can_periph) \param[out] none \retval mailbox_number */ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message) +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message) { uint8_t mailbox_number = CAN_MAILBOX0; /* select one empty mailbox */ - if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)){ + if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)) { mailbox_number = CAN_MAILBOX0; - }else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)){ + } else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)) { mailbox_number = CAN_MAILBOX1; - }else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)){ + } else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)) { mailbox_number = CAN_MAILBOX2; - }else{ + } else { mailbox_number = CAN_NOMAILBOX; } /* return no mailbox empty */ - if(CAN_NOMAILBOX == mailbox_number){ + if(CAN_NOMAILBOX == mailbox_number) { return CAN_NOMAILBOX; } - + CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; - if(CAN_FF_STANDARD == transmit_message->tx_ff){ + if(CAN_FF_STANDARD == transmit_message->tx_ff) { /* set transmit mailbox standard identifier */ CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \ - transmit_message->tx_ft); - }else{ + transmit_message->tx_ft); + } else { /* set transmit mailbox extended identifier */ CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \ - transmit_message->tx_ff | \ - transmit_message->tx_ft); + transmit_message->tx_ff | \ + transmit_message->tx_ft); } /* set the data length */ - CAN_TMP(can_periph, mailbox_number) &= ((uint32_t)~CAN_TMP_DLENC); + CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_DLENC; CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen; /* set the data */ CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \ - TMDATA0_DB2(transmit_message->tx_data[2]) | \ - TMDATA0_DB1(transmit_message->tx_data[1]) | \ - TMDATA0_DB0(transmit_message->tx_data[0]); + TMDATA0_DB2(transmit_message->tx_data[2]) | \ + TMDATA0_DB1(transmit_message->tx_data[1]) | \ + TMDATA0_DB0(transmit_message->tx_data[0]); CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \ - TMDATA1_DB6(transmit_message->tx_data[6]) | \ - TMDATA1_DB5(transmit_message->tx_data[5]) | \ - TMDATA1_DB4(transmit_message->tx_data[4]); + TMDATA1_DB6(transmit_message->tx_data[6]) | \ + TMDATA1_DB5(transmit_message->tx_data[5]) | \ + TMDATA1_DB4(transmit_message->tx_data[4]); /* enable transmission */ CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN; @@ -472,7 +472,7 @@ uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* t } /*! - \brief get CAN transmit state + \brief get CAN transmit state \param[in] can_periph \arg CANx(x=0,1) \param[in] mailbox_number @@ -485,9 +485,9 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox { can_transmit_state_enum state = CAN_TRANSMIT_FAILED; uint32_t val = 0U; - - /* check selected mailbox state */ - switch(mailbox_number){ + + /* check selected mailbox state */ + switch(mailbox_number) { /* mailbox0 */ case CAN_MAILBOX0: val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0); @@ -504,26 +504,26 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox val = CAN_TRANSMIT_FAILED; break; } - - switch(val){ - /* transmit pending */ - case (CAN_STATE_PENDING): + + switch(val) { + /* transmit pending */ + case(CAN_STATE_PENDING): state = CAN_TRANSMIT_PENDING; break; - /* mailbox0 transmit succeeded */ - case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): + /* mailbox0 transmit succeeded */ + case(CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): state = CAN_TRANSMIT_OK; break; - /* mailbox1 transmit succeeded */ - case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): + /* mailbox1 transmit succeeded */ + case(CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): state = CAN_TRANSMIT_OK; break; - /* mailbox2 transmit succeeded */ - case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): + /* mailbox2 transmit succeeded */ + case(CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): state = CAN_TRANSMIT_OK; break; - /* transmit failed */ - default: + /* transmit failed */ + default: state = CAN_TRANSMIT_FAILED; break; } @@ -542,19 +542,19 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox */ void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) { - if(CAN_MAILBOX0 == mailbox_number){ + if(CAN_MAILBOX0 == mailbox_number) { CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; - while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)){ + while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)) { } - }else if(CAN_MAILBOX1 == mailbox_number){ + } else if(CAN_MAILBOX1 == mailbox_number) { CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; - while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)){ + while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)) { } - }else if(CAN_MAILBOX2 == mailbox_number){ + } else if(CAN_MAILBOX2 == mailbox_number) { CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; - while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)){ + while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)) { } - }else{ + } else { /* illegal parameters */ } } @@ -562,7 +562,7 @@ void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) /*! \brief CAN receive message \param[in] can_periph - \arg CANx(x=0,1) + \arg CANx(x=0,1) \param[in] fifo_number \arg CAN_FIFOx(x=0,1) \param[out] receive_message: struct for CAN receive message @@ -575,24 +575,24 @@ void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) \arg rx_fi: 0 - 27 \retval none */ -void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message) +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message) { /* get the frame format */ receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number)); - if(CAN_FF_STANDARD == receive_message->rx_ff){ + if(CAN_FF_STANDARD == receive_message->rx_ff) { /* get standard identifier */ - receive_message -> rx_sfid = (uint32_t)(GET_RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); - }else{ + receive_message->rx_sfid = (uint32_t)(GET_RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); + } else { /* get extended identifier */ - receive_message -> rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); + receive_message->rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); } /* get frame type */ - receive_message -> rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); - /* get recevie data length */ - receive_message -> rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); + receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); /* filtering index */ - receive_message -> rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); + receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); + /* get receive data length */ + receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); /* receive data */ receive_message -> rx_data[0] = (uint8_t)(GET_RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number))); @@ -605,15 +605,15 @@ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_m receive_message -> rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); /* release FIFO */ - if(CAN_FIFO0 == fifo_number){ + if(CAN_FIFO0 == fifo_number) { CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; - }else{ + } else { CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; } } /*! - \brief release FIFO0 + \brief release FIFO \param[in] can_periph \arg CANx(x=0,1) \param[in] fifo_number @@ -624,11 +624,11 @@ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_m */ void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) { - if(CAN_FIFO0 == fifo_number){ + if(CAN_FIFO0 == fifo_number) { CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; - }else if(CAN_FIFO1 == fifo_number){ + } else if(CAN_FIFO1 == fifo_number) { CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; - }else{ + } else { /* illegal parameters */ CAN_ERROR_HANDLE("CAN FIFO NUM is invalid \r\n"); } @@ -640,21 +640,21 @@ void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) \arg CANx(x=0,1) \param[in] fifo_number only one parameter can be selected which is shown as below: - \arg CAN_FIFOx(x=0,1) + \arg CAN_FIFOx(x=0,1) \param[out] none \retval message length */ uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) { uint8_t val = 0U; - - if(CAN_FIFO0 == fifo_number){ + + if(CAN_FIFO0 == fifo_number) { /* FIFO0 */ val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK); - }else if(CAN_FIFO1 == fifo_number){ + } else if(CAN_FIFO1 == fifo_number) { /* FIFO1 */ val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK); - }else{ + } else { /* illegal parameters */ } return val; @@ -663,7 +663,7 @@ uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) /*! \brief set CAN working mode \param[in] can_periph - \arg CANx(x=0,1) + \arg CANx(x=0,1) \param[in] can_working_mode only one parameter can be selected which is shown as below: \arg CAN_MODE_INITIALIZE @@ -676,49 +676,49 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) { ErrStatus flag = ERROR; /* timeout for IWS or also for SLPWS bits */ - uint32_t timeout = CAN_TIMEOUT; - - if(CAN_MODE_INITIALIZE == working_mode){ + uint32_t timeout = CAN_TIMEOUT; + + if(CAN_MODE_INITIALIZE == working_mode) { /* disable sleep mode */ CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); /* set initialize mode */ CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; /* wait the acknowledge */ - while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ + while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { timeout--; } - if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ + if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) { flag = ERROR; - }else{ + } else { flag = SUCCESS; } - }else if(CAN_MODE_NORMAL == working_mode){ + } else if(CAN_MODE_NORMAL == working_mode) { /* enter normal mode */ CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); /* wait the acknowledge */ - while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){ + while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)) { timeout--; } - if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){ + if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) { flag = ERROR; - }else{ + } else { flag = SUCCESS; } - }else if(CAN_MODE_SLEEP == working_mode){ + } else if(CAN_MODE_SLEEP == working_mode) { /* disable initialize mode */ CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD); /* set sleep mode */ CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD; /* wait the acknowledge */ - while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){ + while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)) { timeout--; } - if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ + if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) { flag = ERROR; - }else{ + } else { flag = SUCCESS; } - }else{ + } else { flag = ERROR; } return flag; @@ -727,7 +727,7 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) /*! \brief wake up CAN \param[in] can_periph - \arg CANx(x=0,1) + \arg CANx(x=0,1) \param[out] none \retval ErrStatus: SUCCESS or ERROR */ @@ -735,17 +735,17 @@ ErrStatus can_wakeup(uint32_t can_periph) { ErrStatus flag = ERROR; uint32_t timeout = CAN_TIMEOUT; - + /* wakeup */ CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; - - while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){ + + while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)) { timeout--; } /* check state */ - if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ + if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) { flag = ERROR; - }else{ + } else { flag = SUCCESS; } return flag; @@ -770,7 +770,7 @@ can_error_enum can_error_get(uint32_t can_periph) { can_error_enum error; error = CAN_ERROR_NONE; - + /* get error type */ error = (can_error_enum)(GET_ERR_ERRN(CAN_ERR(can_periph))); return error; @@ -779,14 +779,14 @@ can_error_enum can_error_get(uint32_t can_periph) /*! \brief get CAN receive error number \param[in] can_periph - \arg CANx(x=0,1) + \arg CANx(x=0,1) \param[out] none \retval error number */ uint8_t can_receive_error_number_get(uint32_t can_periph) { uint8_t val; - + /* get error count */ val = (uint8_t)(GET_ERR_RECNT(CAN_ERR(can_periph))); return val; @@ -795,74 +795,18 @@ uint8_t can_receive_error_number_get(uint32_t can_periph) /*! \brief get CAN transmit error number \param[in] can_periph - \arg CANx(x=0,1) + \arg CANx(x=0,1) \param[out] none \retval error number */ uint8_t can_transmit_error_number_get(uint32_t can_periph) { uint8_t val; - + val = (uint8_t)(GET_ERR_TECNT(CAN_ERR(can_periph))); return val; } -/*! - \brief enable CAN interrupt - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] interrupt - one or more parameters can be selected which are shown as below: - \arg CAN_INT_TME: transmit mailbox empty interrupt enable - \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable - \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable - \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable - \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable - \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable - \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable - \arg CAN_INT_WERR: warning error interrupt enable - \arg CAN_INT_PERR: passive error interrupt enable - \arg CAN_INT_BO: bus-off interrupt enable - \arg CAN_INT_ERRN: error number interrupt enable - \arg CAN_INT_ERR: error interrupt enable - \arg CAN_INT_WAKEUP: wakeup interrupt enable - \arg CAN_INT_SLPW: sleep working interrupt enable - \param[out] none - \retval none -*/ -void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) -{ - CAN_INTEN(can_periph) |= interrupt; -} - -/*! - \brief disable CAN interrupt - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] interrupt - one or more parameters can be selected which are shown as below: - \arg CAN_INT_TME: transmit mailbox empty interrupt enable - \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable - \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable - \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable - \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable - \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable - \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable - \arg CAN_INT_WERR: warning error interrupt enable - \arg CAN_INT_PERR: passive error interrupt enable - \arg CAN_INT_BO: bus-off interrupt enable - \arg CAN_INT_ERRN: error number interrupt enable - \arg CAN_INT_ERR: error interrupt enable - \arg CAN_INT_WAKEUP: wakeup interrupt enable - \arg CAN_INT_SLPW: sleep working interrupt enable - \param[out] none - \retval none -*/ -void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) -{ - CAN_INTEN(can_periph) &= ~interrupt; -} - /*! \brief get CAN flag state \param[in] can_periph @@ -878,9 +822,9 @@ void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) \arg CAN_FLAG_ERRIF: error flag \arg CAN_FLAG_SLPWS: sleep working state \arg CAN_FLAG_IWS: initial working state - \arg CAN_FLAG_TMLS2: transmit mailbox 2 last sending in Tx FIFO - \arg CAN_FLAG_TMLS1: transmit mailbox 1 last sending in Tx FIFO - \arg CAN_FLAG_TMLS0: transmit mailbox 0 last sending in Tx FIFO + \arg CAN_FLAG_TMLS2: transmit mailbox 2 last sending in TX FIFO + \arg CAN_FLAG_TMLS1: transmit mailbox 1 last sending in TX FIFO + \arg CAN_FLAG_TMLS0: transmit mailbox 0 last sending in TX FIFO \arg CAN_FLAG_TME2: transmit mailbox 2 empty \arg CAN_FLAG_TME1: transmit mailbox 1 empty \arg CAN_FLAG_TME0: transmit mailbox 0 empty @@ -907,11 +851,11 @@ void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) \retval FlagStatus: SET or RESET */ FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) -{ +{ /* get flag and interrupt enable state */ - if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){ + if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))) { return SET; - }else{ + } else { return RESET; } } @@ -946,15 +890,71 @@ FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) */ void can_flag_clear(uint32_t can_periph, can_flag_enum flag) { - if (flag == CAN_FLAG_RFO1){ + if(flag == CAN_FLAG_RFO1) { CAN_REG_VAL(can_periph, flag) = RFO1_CLEAR_VAL; - } else if (flag == CAN_FLAG_RFF1){ + } else if(flag == CAN_FLAG_RFF1) { CAN_REG_VAL(can_periph, flag) = RFF1_CLEAR_VAL; } else { CAN_REG_VAL(can_periph, flag) = BIT(CAN_BIT_POS(flag)); } } +/*! + \brief enable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] interrupt + one or more parameters can be selected which are shown as below: + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WAKEUP: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable + \param[out] none + \retval none +*/ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) +{ + CAN_INTEN(can_periph) |= interrupt; +} + +/*! + \brief disable CAN interrupt + \param[in] can_periph + \arg CANx(x=0,1) + \param[in] interrupt + one or more parameters can be selected which are shown as below: + \arg CAN_INT_TME: transmit mailbox empty interrupt enable + \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable + \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable + \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable + \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable + \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable + \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable + \arg CAN_INT_WERR: warning error interrupt enable + \arg CAN_INT_PERR: passive error interrupt enable + \arg CAN_INT_BO: bus-off interrupt enable + \arg CAN_INT_ERRN: error number interrupt enable + \arg CAN_INT_ERR: error interrupt enable + \arg CAN_INT_WAKEUP: wakeup interrupt enable + \arg CAN_INT_SLPW: sleep working interrupt enable + \param[out] none + \retval none +*/ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) +{ + CAN_INTEN(can_periph) &= ~interrupt; +} + /*! \brief get CAN interrupt flag state \param[in] can_periph @@ -984,22 +984,22 @@ FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum f { uint32_t ret1 = RESET; uint32_t ret2 = RESET; - - /* get the staus of interrupt flag */ - if (flag == CAN_INT_FLAG_RFL0) { + + /* get the status of interrupt flag */ + if(flag == CAN_INT_FLAG_RFL0) { ret1 = can_receive_message_length_get(can_periph, CAN_FIFO0); - } else if (flag == CAN_INT_FLAG_RFL1) { + } else if(flag == CAN_INT_FLAG_RFL1) { ret1 = can_receive_message_length_get(can_periph, CAN_FIFO1); - } else if (flag == CAN_INT_FLAG_ERRN) { + } else if(flag == CAN_INT_FLAG_ERRN) { ret1 = can_error_get(can_periph); } else { ret1 = CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag)); } - /* get the staus of interrupt enale bit */ + /* get the status of interrupt enable bit */ ret2 = CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag)); - if(ret1 && ret2){ + if(ret1 && ret2) { return SET; - }else{ + } else { return RESET; } } @@ -1025,9 +1025,9 @@ FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum f */ void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag) { - if (flag == CAN_INT_FLAG_RFO1){ + if(flag == CAN_INT_FLAG_RFO1) { CAN_REG_VALS(can_periph, flag) = RFO1_CLEAR_VAL; - } else if (flag == CAN_INT_FLAG_RFF1){ + } else if(flag == CAN_INT_FLAG_RFF1) { CAN_REG_VALS(can_periph, flag) = RFF1_CLEAR_VAL; } else { CAN_REG_VALS(can_periph, flag) = BIT(CAN_BIT_POS0(flag)); diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_cau.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_cau.c index d0fd887a..2b4ee8f5 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_cau.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_cau.c @@ -2,36 +2,33 @@ \file gd32f20x_cau.c \brief CAU driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -42,7 +39,7 @@ OF SUCH DAMAGE. /*! \brief reset the CAU peripheral - \param[in] none + \param[in] none \param[out] none \retval none */ @@ -63,8 +60,8 @@ void cau_deinit(void) void cau_enable(void) { /* enable the CAU processor */ - CAU_CTL |= CAU_CTL_CAUEN; -} + CAU_CTL |= CAU_CTL_CAUEN; +} /*! \brief disable the CAU peripheral @@ -82,7 +79,7 @@ void cau_disable(void) \brief enable the CAU DMA interface \param[in] dma_req: specify the CAU DMA transfer request to be enabled one or more parameters can be selected which are shown as below - \arg CAU_DMA_INFIFO: DMA for incoming(Rx) data transfer + \arg CAU_DMA_INFIFO: DMA for incoming(Rx) data transfer \arg CAU_DMA_OUTFIFO: DMA for outgoing(Tx) data transfer \param[out] none \retval none @@ -97,7 +94,7 @@ void cau_dma_enable(uint32_t dma_req) \brief disable the CAU DMA interface \param[in] dma_req: specify the CAU DMA transfer request to be disabled one or more parameters can be selected which are shown as below - \arg CAU_DMA_INFIFO: DMA for incoming(Rx) data transfer + \arg CAU_DMA_INFIFO: DMA for incoming(Rx) data transfer \arg CAU_DMA_OUTFIFO: DMA for outgoing(Tx) data transfer \param[out] none \retval none @@ -123,27 +120,27 @@ void cau_dma_disable(uint32_t dma_req) \arg CAU_MODE_AES_ECB: AES-ECB (AES Electronic codebook) \arg CAU_MODE_AES_CBC: AES-CBC (AES Cipher block chaining) \arg CAU_MODE_AES_CTR: AES-CTR (AES counter mode) - \arg CAU_MODE_AES_KEY: AES decryption key preparation mode + \arg CAU_MODE_AES_KEY: AES decryption key preparation mode \param[in] swapping: data swapping selection only one parameter can be selected which is shown as below \arg CAU_SWAPPING_32BIT: no swapping \arg CAU_SWAPPING_16BIT: half-word swapping \arg CAU_SWAPPING_8BIT: bytes swapping - \arg CAU_SWAPPING_1BIT: bit swapping + \arg CAU_SWAPPING_1BIT: bit swapping \param[out] none \retval none */ void cau_init(uint32_t algo_dir, uint32_t algo_mode, uint32_t swapping) -{ - /* select algorithm mode */ +{ + /* select algorithm mode */ CAU_CTL &= ~CAU_CTL_ALGM; CAU_CTL |= algo_mode; - - /* select data swapping */ + + /* select data swapping */ CAU_CTL &= ~CAU_CTL_DATAM; CAU_CTL |= swapping; - /* select algorithm direction */ + /* select algorithm direction */ CAU_CTL &= ~CAU_CTL_CAUDIR; CAU_CTL |= algo_dir; } @@ -153,16 +150,16 @@ void cau_init(uint32_t algo_dir, uint32_t algo_mode, uint32_t swapping) \param[in] key_size: key length selection when aes mode only one parameter can be selected which is shown as below \arg CAU_KEYSIZE_128BIT: 128 bit key length - \arg CAU_KEYSIZE_192BIT: 192 bit key length - \arg CAU_KEYSIZE_256BIT: 256 bit key length + \arg CAU_KEYSIZE_192BIT: 192 bit key length + \arg CAU_KEYSIZE_256BIT: 256 bit key length \param[out] none \retval none */ void cau_aes_keysize_config(uint32_t key_size) { CAU_CTL &= ~CAU_CTL_KEYM; - CAU_CTL |= key_size; -} + CAU_CTL |= key_size; +} /*! \brief initialize the key parameters @@ -178,7 +175,7 @@ void cau_aes_keysize_config(uint32_t key_size) \param[out] none \retval none */ -void cau_key_init(cau_key_parameter_struct* key_initpara) +void cau_key_init(cau_key_parameter_struct *key_initpara) { CAU_KEY0H = key_initpara->key_0_high; CAU_KEY0L = key_initpara->key_0_low; @@ -204,7 +201,7 @@ void cau_key_init(cau_key_parameter_struct* key_initpara) \param[out] none \retval none */ -void cau_key_parameter_init(cau_key_parameter_struct* key_initpara) +void cau_key_parameter_init(cau_key_parameter_struct *key_initpara) { key_initpara->key_0_high = 0U; key_initpara->key_0_low = 0U; @@ -226,7 +223,7 @@ void cau_key_parameter_init(cau_key_parameter_struct* key_initpara) \param[out] none \retval none */ -void cau_iv_init(cau_iv_parameter_struct* iv_initpara) +void cau_iv_init(cau_iv_parameter_struct *iv_initpara) { CAU_IV0H = iv_initpara->iv_0_high; CAU_IV0L = iv_initpara->iv_0_low; @@ -244,7 +241,7 @@ void cau_iv_init(cau_iv_parameter_struct* iv_initpara) \param[out] none \retval none */ -void cau_iv_parameter_init(cau_iv_parameter_struct* iv_initpara) +void cau_iv_parameter_init(cau_iv_parameter_struct *iv_initpara) { iv_initpara->iv_0_high = 0U; iv_initpara->iv_0_low = 0U; @@ -273,7 +270,7 @@ void cau_fifo_flush(void) ControlStatus cau_enable_state_get(void) { ControlStatus ret = DISABLE; - if(RESET != (CAU_CTL & CAU_CTL_CAUEN)){ + if(RESET != (CAU_CTL & CAU_CTL_CAUEN)) { ret = ENABLE; } return ret; @@ -305,13 +302,13 @@ uint32_t cau_data_read(void) \brief get the CAU flag status \param[in] flag: CAU flag status only one parameter can be selected which is shown as below - \arg CAU_FLAG_INFIFO_EMPTY: input FIFO empty + \arg CAU_FLAG_INFIFO_EMPTY: input FIFO empty \arg CAU_FLAG_INFIFO_NO_FULL: input FIFO is not full - \arg CAU_FLAG_OUTFIFO_NO_EMPTY: output FIFO not empty + \arg CAU_FLAG_OUTFIFO_NO_EMPTY: output FIFO not empty \arg CAU_FLAG_OUTFIFO_FULL: output FIFO is full - \arg CAU_FLAG_BUSY: the CAU core is busy + \arg CAU_FLAG_BUSY: the CAU core is busy \arg CAU_FLAG_INFIFO: input FIFO flag status - \arg CAU_FLAG_OUTFIFO: output FIFO flag status + \arg CAU_FLAG_OUTFIFO: output FIFO flag status \param[out] none \retval FlagStatus: SET or RESET */ @@ -321,18 +318,18 @@ FlagStatus cau_flag_get(uint32_t flag) FlagStatus ret_flag = RESET; /* check if the flag is in CAU_STAT1 register */ - if(RESET != (flag & FLAG_MASK)){ + if(RESET != (flag & FLAG_MASK)) { reg = CAU_STAT1; - }else{ + } else { /* the flag is in CAU_STAT0 register */ reg = CAU_STAT0; } /* check the status of the specified CAU flag */ - if(RESET != (reg & flag)){ + if(RESET != (reg & flag)) { ret_flag = SET; } - + return ret_flag; } @@ -340,7 +337,7 @@ FlagStatus cau_flag_get(uint32_t flag) \brief enable the CAU interrupts \param[in] interrupt: specify the CAU interrupt source to be enabled one or more parameters can be selected which are shown as below - \arg CAU_INT_INFIFO: input FIFO interrupt + \arg CAU_INT_INFIFO: input FIFO interrupt \arg CAU_INT_OUTFIFO: output FIFO interrupt \param[out] none \retval none @@ -355,7 +352,7 @@ void cau_interrupt_enable(uint32_t interrupt) \brief disable the CAU interrupts \param[in] interrupt: specify the CAU interrupt source to be disabled one or more parameters can be selected which are shown as below - \arg CAU_INT_INFIFO: input FIFO interrupt + \arg CAU_INT_INFIFO: input FIFO interrupt \arg CAU_INT_OUTFIFO: output FIFO interrupt \param[out] none \retval none @@ -370,7 +367,7 @@ void cau_interrupt_disable(uint32_t interrupt) \brief get the interrupt flag \param[in] int_flag: CAU interrupt flag only one parameter can be selected which is shown as below - \arg CAU_INT_FLAG_INFIFO: input FIFO interrupt + \arg CAU_INT_FLAG_INFIFO: input FIFO interrupt \arg CAU_INT_FLAG_OUTFIFO: output FIFO interrupt \param[out] none \retval FlagStatus: SET or RESET @@ -378,11 +375,11 @@ void cau_interrupt_disable(uint32_t interrupt) FlagStatus cau_interrupt_flag_get(uint32_t int_flag) { FlagStatus flag = RESET; - + /* check the status of the specified CAU interrupt */ - if(RESET != (CAU_INTF & int_flag)){ + if(RESET != (CAU_INTF & int_flag)) { flag = SET; } - + return flag; } diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_cau_aes.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_cau_aes.c index e9980134..f70d7adf 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_cau_aes.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_cau_aes.c @@ -2,36 +2,33 @@ \file gd32f20x_cau_aes.c \brief CAU_AES driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -40,7 +37,7 @@ OF SUCH DAMAGE. #define AESBSY_TIMEOUT ((uint32_t)0x00010000U) /* AES key structure parameter config */ -static void cau_aes_key_config(uint8_t *key, uint16_t keysize, cau_key_parameter_struct* cau_key_initpara); +static void cau_aes_key_config(uint8_t *key, uint16_t keysize, cau_key_parameter_struct *cau_key_initpara); /* AES calculate process */ static ErrStatus cau_aes_calculate(uint8_t *input, uint32_t in_length, uint8_t *output); @@ -52,7 +49,7 @@ static ErrStatus cau_aes_calculate(uint8_t *input, uint32_t in_length, uint8_t * \arg CAU_DECRYPT: decrypt \param[in] key: key used for AES algorithm \param[in] keysize: length of the key, must be a 128, 192 or 256 - \param[in] text: pointer to the text information struct + \param[in] text: pointer to the text information struct input: pointer to the input buffer in_length: length of the input buffer, must be a multiple of 16 output: pointer to the returned buffer @@ -71,32 +68,32 @@ ErrStatus cau_aes_ecb(uint32_t algo_dir, uint8_t *key, uint16_t keysize, cau_tex /* AES key structure parameter config */ cau_aes_key_config(key, keysize, &key_initpara); /* key initialization */ - cau_key_init(&key_initpara); + cau_key_init(&key_initpara); /* AES decryption */ - if(CAU_DECRYPT == algo_dir){ + if(CAU_DECRYPT == algo_dir) { /* flush the IN and OUT FIFOs */ cau_fifo_flush(); /* initialize the CAU peripheral */ - cau_init(CAU_DECRYPT, CAU_MODE_AES_KEY, CAU_SWAPPING_32BIT); + cau_init(CAU_DECRYPT, CAU_MODE_AES_KEY, CAU_SWAPPING_32BIT); /* enable the CAU peripheral */ cau_enable(); /* wait until the busy flag is RESET */ - do{ + do { busystatus = cau_flag_get(CAU_FLAG_BUSY); counter++; - }while((AESBSY_TIMEOUT != counter) && (RESET != busystatus)); + } while((AESBSY_TIMEOUT != counter) && (RESET != busystatus)); - if(RESET != busystatus){ + if(RESET != busystatus) { return ERROR; } } - + /* initialize the CAU peripheral */ cau_init(algo_dir, CAU_MODE_AES_ECB, CAU_SWAPPING_8BIT); - + /* flush the IN and OUT FIFOs */ cau_fifo_flush(); @@ -118,14 +115,14 @@ ErrStatus cau_aes_ecb(uint32_t algo_dir, uint8_t *key, uint16_t keysize, cau_tex \arg CAU_DECRYPT: decrypt \param[in] key: key used for AES algorithm \param[in] keysize: length of the key, must be a 128, 192 or 256 - \param[in] iv: initialization vectors used for TDES algorithm - \param[in] text: pointer to the text information struct + \param[in] iv: initialization vectors used for TDES algorithm + \param[in] text: pointer to the text information struct input: pointer to the input buffer in_length: length of the input buffer, must be a multiple of 16 output: pointer to the returned buffer \param[out] none \retval ErrStatus: SUCCESS or ERROR -*/ +*/ ErrStatus cau_aes_cbc(uint32_t algo_dir, uint8_t *key, uint16_t keysize, uint8_t iv[16], cau_text_struct *text) { ErrStatus ret = ERROR; @@ -133,7 +130,7 @@ ErrStatus cau_aes_cbc(uint32_t algo_dir, uint8_t *key, uint16_t keysize, uint8_t cau_iv_parameter_struct iv_initpara; __IO uint32_t counter = 0U; uint32_t busystatus = 0U; - + uint32_t ivaddr = (uint32_t)iv; /* key structure initialization */ @@ -141,41 +138,41 @@ ErrStatus cau_aes_cbc(uint32_t algo_dir, uint8_t *key, uint16_t keysize, uint8_t /* AES key structure parameter config */ cau_aes_key_config(key, keysize, &key_initpara); /* key initialization */ - cau_key_init(&key_initpara); + cau_key_init(&key_initpara); /* AES decryption */ - if(CAU_DECRYPT == algo_dir){ + if(CAU_DECRYPT == algo_dir) { /* flush the IN and OUT FIFOs */ cau_fifo_flush(); /* initialize the CAU peripheral */ - cau_init(CAU_DECRYPT, CAU_MODE_AES_KEY, CAU_SWAPPING_32BIT); + cau_init(CAU_DECRYPT, CAU_MODE_AES_KEY, CAU_SWAPPING_32BIT); /* enable the CAU peripheral */ cau_enable(); /* wait until the busy flag is RESET */ - do{ + do { busystatus = cau_flag_get(CAU_FLAG_BUSY); counter++; - }while((AESBSY_TIMEOUT != counter) && (RESET != busystatus)); + } while((AESBSY_TIMEOUT != counter) && (RESET != busystatus)); - if(RESET != busystatus){ + if(RESET != busystatus) { return ERROR; } } - + /* initialize the CAU peripheral */ cau_init(algo_dir, CAU_MODE_AES_CBC, CAU_SWAPPING_8BIT); - + /* vectors initialization */ - iv_initpara.iv_0_high = __REV(*(uint32_t*)(ivaddr)); + iv_initpara.iv_0_high = __REV(*(uint32_t *)(ivaddr)); ivaddr += 4U; - iv_initpara.iv_0_low = __REV(*(uint32_t*)(ivaddr)); + iv_initpara.iv_0_low = __REV(*(uint32_t *)(ivaddr)); ivaddr += 4U; - iv_initpara.iv_1_high = __REV(*(uint32_t*)(ivaddr)); + iv_initpara.iv_1_high = __REV(*(uint32_t *)(ivaddr)); ivaddr += 4U; - iv_initpara.iv_1_low = __REV(*(uint32_t*)(ivaddr)); - cau_iv_init(&iv_initpara); + iv_initpara.iv_1_low = __REV(*(uint32_t *)(ivaddr)); + cau_iv_init(&iv_initpara); /* flush the IN and OUT FIFOs */ cau_fifo_flush(); @@ -198,40 +195,40 @@ ErrStatus cau_aes_cbc(uint32_t algo_dir, uint8_t *key, uint16_t keysize, uint8_t \arg CAU_DECRYPT: decrypt \param[in] key: key used for AES algorithm \param[in] keysize: length of the key, must be a 128, 192 or 256 - \param[in] iv: initialization vectors used for TDES algorithm - \param[in] text: pointer to the text information struct + \param[in] iv: initialization vectors used for TDES algorithm + \param[in] text: pointer to the text information struct input: pointer to the input buffer in_length: length of the input buffer, must be a multiple of 16 output: pointer to the returned buffer \param[out] none \retval ErrStatus: SUCCESS or ERROR -*/ +*/ ErrStatus cau_aes_ctr(uint32_t algo_dir, uint8_t *key, uint16_t keysize, uint8_t iv[16], cau_text_struct *text) { ErrStatus ret = ERROR; cau_key_parameter_struct key_initpara; cau_iv_parameter_struct iv_initpara; - + uint32_t ivaddr = (uint32_t)iv; /* key structure initialization */ cau_key_parameter_init(&key_initpara); /* initialize the CAU peripheral */ - cau_init(algo_dir, CAU_MODE_AES_CTR, CAU_SWAPPING_8BIT); - + cau_init(algo_dir, CAU_MODE_AES_CTR, CAU_SWAPPING_8BIT); + /* AES key structure parameter config */ cau_aes_key_config(key, keysize, &key_initpara); /* key initialization */ cau_key_init(&key_initpara); - + /* vectors initialization */ - iv_initpara.iv_0_high = __REV(*(uint32_t*)(ivaddr)); + iv_initpara.iv_0_high = __REV(*(uint32_t *)(ivaddr)); ivaddr += 4U; - iv_initpara.iv_0_low = __REV(*(uint32_t*)(ivaddr)); + iv_initpara.iv_0_low = __REV(*(uint32_t *)(ivaddr)); ivaddr += 4U; - iv_initpara.iv_1_high = __REV(*(uint32_t*)(ivaddr)); + iv_initpara.iv_1_high = __REV(*(uint32_t *)(ivaddr)); ivaddr += 4U; - iv_initpara.iv_1_low = __REV(*(uint32_t*)(ivaddr)); + iv_initpara.iv_1_low = __REV(*(uint32_t *)(ivaddr)); cau_iv_init(&iv_initpara); /* flush the IN and OUT FIFOs */ @@ -250,7 +247,7 @@ ErrStatus cau_aes_ctr(uint32_t algo_dir, uint8_t *key, uint16_t keysize, uint8_t /*! \brief AES key structure parameter config \param[in] key: key used for AES algorithm - \param[in] keysize: length of the key, must be a 128, 192 or 256 + \param[in] keysize: length of the key, must be a 128, 192 or 256 \param[out] cau_key_initpara: key init parameter struct key_0_high: key 0 high key_0_low: key 0 low @@ -262,52 +259,52 @@ ErrStatus cau_aes_ctr(uint32_t algo_dir, uint8_t *key, uint16_t keysize, uint8_t key_3_low: key 3 low \retval none */ -static void cau_aes_key_config(uint8_t *key, uint16_t keysize, cau_key_parameter_struct* cau_key_initpara) +static void cau_aes_key_config(uint8_t *key, uint16_t keysize, cau_key_parameter_struct *cau_key_initpara) { uint32_t keyaddr = (uint32_t)key; - - switch(keysize){ - case 128: + + switch(keysize) { + case 128: cau_aes_keysize_config(CAU_KEYSIZE_128BIT); - cau_key_initpara->key_2_high = __REV(*(uint32_t*)(keyaddr)); + cau_key_initpara->key_2_high = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - cau_key_initpara->key_2_low = __REV(*(uint32_t*)(keyaddr)); + cau_key_initpara->key_2_low = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - cau_key_initpara->key_3_high = __REV(*(uint32_t*)(keyaddr)); + cau_key_initpara->key_3_high = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - cau_key_initpara->key_3_low = __REV(*(uint32_t*)(keyaddr)); + cau_key_initpara->key_3_low = __REV(*(uint32_t *)(keyaddr)); break; case 192: cau_aes_keysize_config(CAU_KEYSIZE_192BIT); - cau_key_initpara->key_1_high = __REV(*(uint32_t*)(keyaddr)); + cau_key_initpara->key_1_high = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - cau_key_initpara->key_1_low = __REV(*(uint32_t*)(keyaddr)); + cau_key_initpara->key_1_low = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - cau_key_initpara->key_2_high = __REV(*(uint32_t*)(keyaddr)); + cau_key_initpara->key_2_high = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - cau_key_initpara->key_2_low = __REV(*(uint32_t*)(keyaddr)); + cau_key_initpara->key_2_low = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - cau_key_initpara->key_3_high = __REV(*(uint32_t*)(keyaddr)); + cau_key_initpara->key_3_high = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - cau_key_initpara->key_3_low = __REV(*(uint32_t*)(keyaddr)); + cau_key_initpara->key_3_low = __REV(*(uint32_t *)(keyaddr)); break; case 256: cau_aes_keysize_config(CAU_KEYSIZE_256BIT); - cau_key_initpara->key_0_high = __REV(*(uint32_t*)(keyaddr)); + cau_key_initpara->key_0_high = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - cau_key_initpara->key_0_low = __REV(*(uint32_t*)(keyaddr)); + cau_key_initpara->key_0_low = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - cau_key_initpara->key_1_high = __REV(*(uint32_t*)(keyaddr)); + cau_key_initpara->key_1_high = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - cau_key_initpara->key_1_low = __REV(*(uint32_t*)(keyaddr)); + cau_key_initpara->key_1_low = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - cau_key_initpara->key_2_high = __REV(*(uint32_t*)(keyaddr)); + cau_key_initpara->key_2_high = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - cau_key_initpara->key_2_low = __REV(*(uint32_t*)(keyaddr)); + cau_key_initpara->key_2_low = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - cau_key_initpara->key_3_high = __REV(*(uint32_t*)(keyaddr)); + cau_key_initpara->key_3_high = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - cau_key_initpara->key_3_low = __REV(*(uint32_t*)(keyaddr)); + cau_key_initpara->key_3_low = __REV(*(uint32_t *)(keyaddr)); break; default: break; @@ -316,9 +313,9 @@ static void cau_aes_key_config(uint8_t *key, uint16_t keysize, cau_key_parameter /*! \brief AES calculate process - \param[in] input: pointer to the input buffer - \param[in] in_length: length of the input buffer, must be a multiple of 16 - \param[in] output: pointer to the returned buffer + \param[in] input: pointer to the input buffer + \param[in] in_length: length of the input buffer, must be a multiple of 16 + \param[in] output: pointer to the returned buffer \param[out] none \retval ErrStatus: SUCCESS or ERROR */ @@ -328,45 +325,45 @@ static ErrStatus cau_aes_calculate(uint8_t *input, uint32_t in_length, uint8_t * uint32_t outputaddr = (uint32_t)output; uint32_t i = 0U; __IO uint32_t counter = 0U; - uint32_t busystatus = 0U; - - /* the clock is not enabled or there is no embeded CAU peripheral */ - if(DISABLE == cau_enable_state_get()){ + uint32_t busystatus = 0U; + + /* the clock is not enabled or there is no embeded CAU peripheral */ + if(DISABLE == cau_enable_state_get()) { return ERROR; } - for(i = 0U; i < in_length; i += 16U){ + for(i = 0U; i < in_length; i += 16U) { /* write data to the IN FIFO */ - cau_data_write(*(uint32_t*)(inputaddr)); + cau_data_write(*(uint32_t *)(inputaddr)); + inputaddr += 4U; + cau_data_write(*(uint32_t *)(inputaddr)); inputaddr += 4U; - cau_data_write(*(uint32_t*)(inputaddr)); + cau_data_write(*(uint32_t *)(inputaddr)); inputaddr += 4U; - cau_data_write(*(uint32_t*)(inputaddr)); + cau_data_write(*(uint32_t *)(inputaddr)); inputaddr += 4U; - cau_data_write(*(uint32_t*)(inputaddr)); - inputaddr += 4U; /* wait until the complete message has been processed */ counter = 0U; - do{ + do { busystatus = cau_flag_get(CAU_FLAG_BUSY); counter++; - }while((AESBSY_TIMEOUT != counter) && (RESET != busystatus)); + } while((AESBSY_TIMEOUT != counter) && (RESET != busystatus)); - if(RESET != busystatus){ + if(RESET != busystatus) { return ERROR; - }else{ + } else { /* read the output block from the output FIFO */ - *(uint32_t*)(outputaddr) = cau_data_read(); + *(uint32_t *)(outputaddr) = cau_data_read(); outputaddr += 4U; - *(uint32_t*)(outputaddr) = cau_data_read(); + *(uint32_t *)(outputaddr) = cau_data_read(); outputaddr += 4U; - *(uint32_t*)(outputaddr) = cau_data_read(); + *(uint32_t *)(outputaddr) = cau_data_read(); + outputaddr += 4U; + *(uint32_t *)(outputaddr) = cau_data_read(); outputaddr += 4U; - *(uint32_t*)(outputaddr) = cau_data_read(); - outputaddr += 4U; } } - + return SUCCESS; } diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_cau_des.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_cau_des.c index 3bcc3981..82c646cd 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_cau_des.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_cau_des.c @@ -2,36 +2,33 @@ \file gd32f20x_cau_des.c \brief CAU_DES driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -48,14 +45,14 @@ static ErrStatus cau_des_calculate(uint8_t *input, uint32_t in_length, uint8_t * only one parameter can be selected which is shown as below \arg CAU_ENCRYPT: encrypt \arg CAU_DECRYPT: decrypt - \param[in] key: key used for DES algorithm - \param[in] text: pointer to the text information struct + \param[in] key: key used for DES algorithm + \param[in] text: pointer to the text information struct input: pointer to the input buffer in_length: length of the input buffer, must be a multiple of 8 output: pointer to the returned buffer \param[out] none \retval ErrStatus: SUCCESS or ERROR -*/ +*/ ErrStatus cau_des_ecb(uint32_t algo_dir, uint8_t key[24], cau_text_struct *text) { ErrStatus ret = ERROR; @@ -66,12 +63,12 @@ ErrStatus cau_des_ecb(uint32_t algo_dir, uint8_t key[24], cau_text_struct *text) /* key structure initialization */ cau_key_parameter_init(&key_initpara); /* initialize the CAU peripheral */ - cau_init(algo_dir, CAU_MODE_DES_ECB, CAU_SWAPPING_8BIT); - - /* key initialisation */ - key_initpara.key_1_high = __REV(*(uint32_t*)(keyaddr)); + cau_init(algo_dir, CAU_MODE_DES_ECB, CAU_SWAPPING_8BIT); + + /* key initialization */ + key_initpara.key_1_high = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - key_initpara.key_1_low= __REV(*(uint32_t*)(keyaddr)); + key_initpara.key_1_low = __REV(*(uint32_t *)(keyaddr)); cau_key_init(& key_initpara); /* flush the IN and OUT FIFOs */ @@ -84,7 +81,7 @@ ErrStatus cau_des_ecb(uint32_t algo_dir, uint8_t key[24], cau_text_struct *text) /* disable the CAU peripheral */ cau_disable(); - return ret; + return ret; } /*! @@ -94,11 +91,11 @@ ErrStatus cau_des_ecb(uint32_t algo_dir, uint8_t key[24], cau_text_struct *text) \arg CAU_ENCRYPT: encrypt \arg CAU_DECRYPT: decrypt \param[in] key: key used for DES algorithm - \param[in] iv: initialization vectors used for TDES algorithm - \param[in] text: pointer to the text information struct + \param[in] iv: initialization vectors used for TDES algorithm + \param[in] text: pointer to the text information struct input: pointer to the input buffer in_length: length of the input buffer, must be a multiple of 8 - output: pointer to the returned buffer + output: pointer to the returned buffer \param[out] none \retval ErrStatus: SUCCESS or ERROR */ @@ -115,17 +112,17 @@ ErrStatus cau_des_cbc(uint32_t algo_dir, uint8_t key[24], uint8_t iv[8], cau_tex cau_key_parameter_init(&key_initpara); /* initialize the CAU peripheral */ cau_init(algo_dir, CAU_MODE_DES_CBC, CAU_SWAPPING_8BIT); - - /* key initialisation */ - key_initpara.key_1_high = __REV(*(uint32_t*)(keyaddr)); + + /* key initialization */ + key_initpara.key_1_high = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - key_initpara.key_1_low= __REV(*(uint32_t*)(keyaddr)); + key_initpara.key_1_low = __REV(*(uint32_t *)(keyaddr)); cau_key_init(&key_initpara); /* vectors initialization */ - iv_initpara.iv_0_high = __REV(*(uint32_t*)(ivaddr)); + iv_initpara.iv_0_high = __REV(*(uint32_t *)(ivaddr)); ivaddr += 4U; - iv_initpara.iv_0_low= __REV(*(uint32_t*)(ivaddr)); + iv_initpara.iv_0_low = __REV(*(uint32_t *)(ivaddr)); cau_iv_init(&iv_initpara); /* flush the IN and OUT FIFOs */ @@ -138,14 +135,14 @@ ErrStatus cau_des_cbc(uint32_t algo_dir, uint8_t key[24], uint8_t iv[8], cau_tex /* disable the CAU peripheral */ cau_disable(); - return ret; + return ret; } /*! \brief DES calculate process - \param[in] input: pointer to the input buffer - \param[in] in_length: length of the input buffer, must be a multiple of 8 - \param[in] output: pointer to the returned buffer + \param[in] input: pointer to the input buffer + \param[in] in_length: length of the input buffer, must be a multiple of 8 + \param[in] output: pointer to the returned buffer \param[out] none \retval ErrStatus: SUCCESS or ERROR */ @@ -155,37 +152,37 @@ static ErrStatus cau_des_calculate(uint8_t *input, uint32_t in_length, uint8_t * uint32_t outputaddr = (uint32_t)output; uint32_t i = 0U; __IO uint32_t counter = 0U; - uint32_t busystatus = 0U; - - /* the clock is not enabled or there is no embeded CAU peripheral */ - if(DISABLE == cau_enable_state_get()){ + uint32_t busystatus = 0U; + + /* the clock is not enabled or there is no embeded CAU peripheral */ + if(DISABLE == cau_enable_state_get()) { return ERROR; } - for(i = 0U; i < in_length; i += 8U){ + for(i = 0U; i < in_length; i += 8U) { /* write data to the IN FIFO */ - cau_data_write(*(uint32_t*)(inputaddr)); + cau_data_write(*(uint32_t *)(inputaddr)); inputaddr += 4U; - cau_data_write(*(uint32_t*)(inputaddr)); + cau_data_write(*(uint32_t *)(inputaddr)); inputaddr += 4U; /* wait until the complete message has been processed */ counter = 0U; - do{ + do { busystatus = cau_flag_get(CAU_FLAG_BUSY); counter++; - }while((DESBUSY_TIMEOUT != counter) && (RESET != busystatus)); + } while((DESBUSY_TIMEOUT != counter) && (RESET != busystatus)); - if(RESET != busystatus){ + if(RESET != busystatus) { return ERROR; - }else{ + } else { /* read the output block from the output FIFO */ - *(uint32_t*)(outputaddr) = cau_data_read(); + *(uint32_t *)(outputaddr) = cau_data_read(); outputaddr += 4U; - *(uint32_t*)(outputaddr) = cau_data_read(); + *(uint32_t *)(outputaddr) = cau_data_read(); outputaddr += 4U; } } - + return SUCCESS; } diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_cau_tdes.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_cau_tdes.c index aa698226..b555c931 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_cau_tdes.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_cau_tdes.c @@ -2,36 +2,33 @@ \file gd32f20x_cau_tdes.c \brief CAU_TDES driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -48,14 +45,14 @@ static ErrStatus cau_tdes_calculate(uint8_t *input, uint32_t in_length, uint8_t only one parameter can be selected which is shown as below \arg CAU_ENCRYPT: encrypt \arg CAU_DECRYPT: decrypt - \param[in] key: key used for TDES algorithm - \param[in] text: pointer to the text information struct + \param[in] key: key used for TDES algorithm + \param[in] text: pointer to the text information struct input: pointer to the input buffer in_length: length of the input buffer, must be a multiple of 8 output: pointer to the returned buffer \param[out] none \retval ErrStatus: SUCCESS or ERROR -*/ +*/ ErrStatus cau_tdes_ecb(uint32_t algo_dir, uint8_t key[24], cau_text_struct *text) { ErrStatus ret = ERROR; @@ -69,17 +66,17 @@ ErrStatus cau_tdes_ecb(uint32_t algo_dir, uint8_t key[24], cau_text_struct *text cau_init(algo_dir, CAU_MODE_TDES_ECB, CAU_SWAPPING_8BIT); /* key initialization */ - key_initpara.key_1_high = __REV(*(uint32_t*)(keyaddr)); + key_initpara.key_1_high = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - key_initpara.key_1_low= __REV(*(uint32_t*)(keyaddr)); + key_initpara.key_1_low = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - key_initpara.key_2_high = __REV(*(uint32_t*)(keyaddr)); + key_initpara.key_2_high = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - key_initpara.key_2_low= __REV(*(uint32_t*)(keyaddr)); + key_initpara.key_2_low = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - key_initpara.key_3_high = __REV(*(uint32_t*)(keyaddr)); + key_initpara.key_3_high = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - key_initpara.key_3_low= __REV(*(uint32_t*)(keyaddr)); + key_initpara.key_3_low = __REV(*(uint32_t *)(keyaddr)); cau_key_init(&key_initpara); /* flush the IN and OUT FIFOs */ @@ -92,7 +89,7 @@ ErrStatus cau_tdes_ecb(uint32_t algo_dir, uint8_t key[24], cau_text_struct *text /* disable the CAU peripheral */ cau_disable(); - return ret; + return ret; } /*! @@ -102,20 +99,20 @@ ErrStatus cau_tdes_ecb(uint32_t algo_dir, uint8_t key[24], cau_text_struct *text \arg CAU_ENCRYPT: encrypt \arg CAU_DECRYPT: decrypt \param[in] key: key used for TDES algorithm - \param[in] iv: initialization vectors used for TDES algorithm - \param[in] text: pointer to the text information struct + \param[in] iv: initialization vectors used for TDES algorithm + \param[in] text: pointer to the text information struct input: pointer to the input buffer in_length: length of the input buffer, must be a multiple of 8 output: pointer to the returned buffer \param[out] none \retval ErrStatus: SUCCESS or ERROR -*/ +*/ ErrStatus cau_tdes_cbc(uint32_t algo_dir, uint8_t key[24], uint8_t iv[8], cau_text_struct *text) { ErrStatus ret = ERROR; cau_key_parameter_struct key_initpara; cau_iv_parameter_struct iv_initpara; - + uint32_t keyaddr = (uint32_t)key; uint32_t ivaddr = (uint32_t)iv; @@ -123,25 +120,25 @@ ErrStatus cau_tdes_cbc(uint32_t algo_dir, uint8_t key[24], uint8_t iv[8], cau_te cau_key_parameter_init(&key_initpara); /* initialize the CAU peripheral */ cau_init(algo_dir, CAU_MODE_TDES_CBC, CAU_SWAPPING_8BIT); - + /* key initialization */ - key_initpara.key_1_high = __REV(*(uint32_t*)(keyaddr)); + key_initpara.key_1_high = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - key_initpara.key_1_low= __REV(*(uint32_t*)(keyaddr)); + key_initpara.key_1_low = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - key_initpara.key_2_high = __REV(*(uint32_t*)(keyaddr)); + key_initpara.key_2_high = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - key_initpara.key_2_low= __REV(*(uint32_t*)(keyaddr)); + key_initpara.key_2_low = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - key_initpara.key_3_high = __REV(*(uint32_t*)(keyaddr)); + key_initpara.key_3_high = __REV(*(uint32_t *)(keyaddr)); keyaddr += 4U; - key_initpara.key_3_low= __REV(*(uint32_t*)(keyaddr)); + key_initpara.key_3_low = __REV(*(uint32_t *)(keyaddr)); cau_key_init(&key_initpara); /* vectors initialization */ - iv_initpara.iv_0_high = __REV(*(uint32_t*)(ivaddr)); + iv_initpara.iv_0_high = __REV(*(uint32_t *)(ivaddr)); ivaddr += 4U; - iv_initpara.iv_0_low= __REV(*(uint32_t*)(ivaddr)); + iv_initpara.iv_0_low = __REV(*(uint32_t *)(ivaddr)); cau_iv_init(&iv_initpara); /* flush the IN and OUT FIFOs */ @@ -154,14 +151,14 @@ ErrStatus cau_tdes_cbc(uint32_t algo_dir, uint8_t key[24], uint8_t iv[8], cau_te /* disable the CAU peripheral */ cau_disable(); - return ret; + return ret; } /*! \brief TDES calculate process - \param[in] input: pointer to the input buffer - \param[in] in_length: length of the input buffer, must be a multiple of 8 - \param[in] output: pointer to the returned buffer + \param[in] input: pointer to the input buffer + \param[in] in_length: length of the input buffer, must be a multiple of 8 + \param[in] output: pointer to the returned buffer \param[out] none \retval ErrStatus: SUCCESS or ERROR */ @@ -171,37 +168,37 @@ static ErrStatus cau_tdes_calculate(uint8_t *input, uint32_t in_length, uint8_t uint32_t outputaddr = (uint32_t)output; uint32_t i = 0U; __IO uint32_t counter = 0U; - uint32_t busystatus = 0U; - - /* the clock is not enabled or there is no embeded CAU peripheral */ - if(DISABLE == cau_enable_state_get()){ + uint32_t busystatus = 0U; + + /* the clock is not enabled or there is no embedded CAU peripheral */ + if(DISABLE == cau_enable_state_get()) { return ERROR; } - for(i = 0U; i < in_length; i += 8U){ + for(i = 0U; i < in_length; i += 8U) { /* write data to the IN FIFO */ - cau_data_write(*(uint32_t*)(inputaddr)); + cau_data_write(*(uint32_t *)(inputaddr)); inputaddr += 4U; - cau_data_write(*(uint32_t*)(inputaddr)); + cau_data_write(*(uint32_t *)(inputaddr)); inputaddr += 4U; /* wait until the complete message has been processed */ counter = 0U; - do{ + do { busystatus = cau_flag_get(CAU_FLAG_BUSY); counter++; - }while((TDESBSY_TIMEOUT != counter) && (RESET != busystatus)); + } while((TDESBSY_TIMEOUT != counter) && (RESET != busystatus)); - if(RESET != busystatus){ + if(RESET != busystatus) { return ERROR; - }else{ + } else { /* read the output block from the output FIFO */ - *(uint32_t*)(outputaddr) = cau_data_read(); + *(uint32_t *)(outputaddr) = cau_data_read(); outputaddr += 4U; - *(uint32_t*)(outputaddr) = cau_data_read(); + *(uint32_t *)(outputaddr) = cau_data_read(); outputaddr += 4U; } } - + return SUCCESS; } diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_crc.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_crc.c index 418b6814..a8ca8fa5 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_crc.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_crc.c @@ -2,36 +2,33 @@ \file gd32f20x_crc.c \brief CRC driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -54,7 +51,7 @@ void crc_deinit(void) } /*! - \brief reset data register to the value of initializaiton data register + \brief reset data register to the value of initialization data register \param[in] none \param[out] none \retval none @@ -65,7 +62,7 @@ void crc_data_register_reset(void) } /*! - \brief read the value of the data register + \brief read the value of the data register \param[in] none \param[out] none \retval 32-bit value of the data register @@ -123,7 +120,7 @@ uint32_t crc_single_data_calculate(uint32_t sdata) uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) { uint32_t index; - for(index = 0U; index < size; index++){ + for(index = 0U; index < size; index++) { CRC_DATA = array[index]; } return (CRC_DATA); diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_dac.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_dac.c index 1677143f..a638fe96 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_dac.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_dac.c @@ -2,36 +2,33 @@ \file gd32f20x_dac.c \brief DAC driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -63,12 +60,12 @@ void dac_deinit(void) */ void dac_enable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL |= DAC_CTL_DEN0; - }else{ + } else { DAC_CTL |= DAC_CTL_DEN1; } -} +} /*! \brief disable DAC @@ -79,9 +76,9 @@ void dac_enable(uint32_t dac_periph) */ void dac_disable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL &= ~DAC_CTL_DEN0; - }else{ + } else { DAC_CTL &= ~DAC_CTL_DEN1; } } @@ -95,9 +92,9 @@ void dac_disable(uint32_t dac_periph) */ void dac_dma_enable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL |= DAC_CTL_DDMAEN0; - }else{ + } else { DAC_CTL |= DAC_CTL_DDMAEN1; } } @@ -111,9 +108,9 @@ void dac_dma_enable(uint32_t dac_periph) */ void dac_dma_disable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL &= ~DAC_CTL_DDMAEN0; - }else{ + } else { DAC_CTL &= ~DAC_CTL_DDMAEN1; } } @@ -127,9 +124,9 @@ void dac_dma_disable(uint32_t dac_periph) */ void dac_output_buffer_enable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL &= ~DAC_CTL_DBOFF0; - }else{ + } else { DAC_CTL &= ~DAC_CTL_DBOFF1; } } @@ -143,9 +140,9 @@ void dac_output_buffer_enable(uint32_t dac_periph) */ void dac_output_buffer_disable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL |= DAC_CTL_DBOFF0; - }else{ + } else { DAC_CTL |= DAC_CTL_DBOFF1; } } @@ -160,10 +157,10 @@ void dac_output_buffer_disable(uint32_t dac_periph) uint16_t dac_output_value_get(uint32_t dac_periph) { uint16_t data = 0U; - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* store the DAC0 output value */ data = (uint16_t)DAC0_DO; - }else{ + } else { /* store the DAC1 output value */ data = (uint16_t)DAC1_DO; } @@ -185,8 +182,8 @@ uint16_t dac_output_value_get(uint32_t dac_periph) */ void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) { - if(DAC0 == dac_periph){ - switch(dac_align){ + if(DAC0 == dac_periph) { + switch(dac_align) { /* data right 12b alignment */ case DAC_ALIGN_12B_R: DAC0_R12DH = data; @@ -202,8 +199,8 @@ void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) default: break; } - }else{ - switch(dac_align){ + } else { + switch(dac_align) { /* data right 12b alignment */ case DAC_ALIGN_12B_R: DAC1_R12DH = data; @@ -231,9 +228,9 @@ void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) */ void dac_trigger_enable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL |= DAC_CTL_DTEN0; - }else{ + } else { DAC_CTL |= DAC_CTL_DTEN1; } } @@ -247,9 +244,9 @@ void dac_trigger_enable(uint32_t dac_periph) */ void dac_trigger_disable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_CTL &= ~DAC_CTL_DTEN0; - }else{ + } else { DAC_CTL &= ~DAC_CTL_DTEN1; } } @@ -273,11 +270,11 @@ void dac_trigger_disable(uint32_t dac_periph) */ void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* configure DAC0 trigger source */ DAC_CTL &= ~DAC_CTL_DTSEL0; DAC_CTL |= triggersource; - }else{ + } else { /* configure DAC1 trigger source */ DAC_CTL &= ~DAC_CTL_DTSEL1; DAC_CTL |= (triggersource << DAC1_REG_OFFSET); @@ -292,9 +289,9 @@ void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource) */ void dac_software_trigger_enable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_SWT |= DAC_SWT_SWTR0; - }else{ + } else { DAC_SWT |= DAC_SWT_SWTR1; } } @@ -308,9 +305,9 @@ void dac_software_trigger_enable(uint32_t dac_periph) */ void dac_software_trigger_disable(uint32_t dac_periph) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { DAC_SWT &= ~DAC_SWT_SWTR0; - }else{ + } else { DAC_SWT &= ~DAC_SWT_SWTR1; } } @@ -329,11 +326,11 @@ void dac_software_trigger_disable(uint32_t dac_periph) */ void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* configure DAC0 wave mode */ DAC_CTL &= ~DAC_CTL_DWM0; DAC_CTL |= wave_mode; - }else{ + } else { /* configure DAC1 wave mode */ DAC_CTL &= ~DAC_CTL_DWM1; DAC_CTL |= (wave_mode << DAC1_REG_OFFSET); @@ -363,11 +360,11 @@ void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) */ void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* configure DAC0 wave bit width */ DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL |= bit_width; - }else{ + } else { /* configure DAC1 wave bit width */ DAC_CTL &= ~DAC_CTL_DWBW1; DAC_CTL |= (bit_width << DAC1_REG_OFFSET); @@ -397,11 +394,11 @@ void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) */ void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* configure DAC0 LFSR noise mode */ DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL |= unmask_bits; - }else{ + } else { /* configure DAC1 LFSR noise mode */ DAC_CTL &= ~DAC_CTL_DWBW1; DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET); @@ -431,11 +428,11 @@ void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) */ void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) { - if(DAC0 == dac_periph){ + if(DAC0 == dac_periph) { /* configure DAC0 triangle noise mode */ DAC_CTL &= ~DAC_CTL_DWBW0; DAC_CTL |= amplitude; - }else{ + } else { /* configure DAC1 triangle noise mode */ DAC_CTL &= ~DAC_CTL_DWBW1; DAC_CTL |= (amplitude << DAC1_REG_OFFSET); @@ -478,7 +475,7 @@ void dac_concurrent_software_trigger_enable(void) { uint32_t swt = 0U; swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; - DAC_SWT |= (swt); + DAC_SWT |= (swt); } /*! @@ -535,7 +532,7 @@ void dac_concurrent_output_buffer_disable(void) void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) { uint32_t data = 0U; - switch(dac_align){ + switch(dac_align) { /* data right 12b alignment */ case DAC_ALIGN_12B_R: data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_dbg.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_dbg.c index bbd6c9f0..8bde336c 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_dbg.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_dbg.c @@ -2,36 +2,33 @@ \file gd32f20x_dbg.c \brief DBG driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -67,9 +64,9 @@ void dbg_low_power_enable(uint32_t dbg_low_power) \brief disable low power behavior when the mcu is in debug mode \param[in] dbg_low_power: one or more parameters can be selected which are shown as below: - \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode - \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode - \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode + \arg DBG_LOW_POWER_SLEEP: do not keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: do not keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: do not keep debugger connection during standby mode \param[out] none \retval none */ @@ -82,11 +79,11 @@ void dbg_low_power_disable(uint32_t dbg_low_power) \brief enable peripheral behavior when the mcu is in debug mode \param[in] dbg_periph: refer to dbg_periph_enum one or more parameters can be selected which are shown as below: - \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted - \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted - \arg DBG_CANx_HOLD (x=0,1): hold CANx counter when core is halted - \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted - \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): hold TIMERx counter when core is halted + \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted + \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted + \arg DBG_CANx_HOLD(x=0,1): hold CANx counter when core is halted + \arg DBG_I2Cx_HOLD(x=0,1,2): hold I2Cx smbus when core is halted + \arg DBG_TIMERx_HOLD(x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): hold TIMERx counter when core is halted \param[out] none \retval none */ @@ -99,11 +96,11 @@ void dbg_periph_enable(dbg_periph_enum dbg_periph) \brief disable peripheral behavior when the mcu is in debug mode \param[in] dbg_periph: refer to dbg_periph_enum one or more parameters can be selected which are shown as below: - \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted - \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted - \arg DBG_CANx_HOLD (x=0,1): hold CANx counter when core is halted - \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted - \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): hold TIMERx counter when core is halted + \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted + \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted + \arg DBG_CANx_HOLD(x=0,1): hold CANx counter when core is halted + \arg DBG_I2Cx_HOLD(x=0,1,2): hold I2Cx smbus when core is halted + \arg DBG_TIMERx_HOLD(x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): hold TIMERx counter when core is halted \param[out] none \retval none */ @@ -135,10 +132,10 @@ void dbg_trace_pin_disable(void) } /*! - \brief trace pin mode selection + \brief trace pin mode selection \param[in] trace_mode: only one parameter can be selected which is shown as below: - \arg TRACE_MODE_ASYNC: trace pin used for async mode + \arg TRACE_MODE_ASYNC: trace pin used for async mode \arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1 \arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2 \arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4 diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_dci.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_dci.c index 33ef579d..dbfa925f 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_dci.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_dci.c @@ -2,36 +2,33 @@ \file gd32f20x_dci.c \brief DCI driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -63,7 +60,7 @@ void dci_deinit(void) \param[out] none \retval none */ -void dci_init(dci_parameter_struct* dci_struct) +void dci_init(dci_parameter_struct *dci_struct) { uint32_t reg = 0U; /* disable capture function and DCI */ @@ -80,18 +77,18 @@ void dci_init(dci_parameter_struct* dci_struct) } /*! - \brief enable DCI function + \brief enable DCI function \param[in] none \param[out] none \retval none */ void dci_enable(void) { - DCI_CTL |= DCI_CTL_DCIEN; + DCI_CTL |= DCI_CTL_DCIEN; } /*! - \brief disable DCI function + \brief disable DCI function \param[in] none \param[out] none \retval none @@ -102,7 +99,7 @@ void dci_disable(void) } /*! - \brief enable DCI capture + \brief enable DCI capture \param[in] none \param[out] none \retval none @@ -113,7 +110,7 @@ void dci_capture_enable(void) } /*! - \brief disable DCI capture + \brief disable DCI capture \param[in] none \param[out] none \retval none @@ -124,7 +121,7 @@ void dci_capture_disable(void) } /*! - \brief enable DCI jpeg mode + \brief enable DCI jpeg mode \param[in] none \param[out] none \retval none @@ -135,7 +132,7 @@ void dci_jpeg_enable(void) } /*! - \brief disable DCI jpeg mode + \brief disable DCI jpeg mode \param[in] none \param[out] none \retval none @@ -168,7 +165,7 @@ void dci_crop_window_disable(void) } /*! - \brief configure DCI cropping window + \brief configure DCI cropping window \param[in] start_x: window horizontal start position \param[in] start_y: window vertical start position \param[in] size_width: window horizontal size @@ -178,8 +175,8 @@ void dci_crop_window_disable(void) */ void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height) { - DCI_CWSPOS = ((uint32_t)start_x | ((uint32_t)start_y<<16)); - DCI_CWSZ = ((uint32_t)size_width | ((uint32_t)size_height<<16)); + DCI_CWSPOS = ((uint32_t)start_x | ((uint32_t)start_y << 16)); + DCI_CWSZ = ((uint32_t)size_width | ((uint32_t)size_height << 16)); } /*! @@ -214,7 +211,7 @@ void dci_embedded_sync_disable(void) */ void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end) { - DCI_SC = ((uint32_t)frame_start | ((uint32_t)line_start<<8) | ((uint32_t)line_end<<16) | ((uint32_t)frame_end<<24)); + DCI_SC = ((uint32_t)frame_start | ((uint32_t)line_start << 8) | ((uint32_t)line_end << 16) | ((uint32_t)frame_end << 24)); } /*! @@ -228,14 +225,14 @@ void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line */ void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end) { - DCI_SCUMSK = ((uint32_t)frame_start | ((uint32_t)line_start<<8) | ((uint32_t)line_end<<16) | ((uint32_t)frame_end<<24)); + DCI_SCUMSK = ((uint32_t)frame_start | ((uint32_t)line_start << 8) | ((uint32_t)line_end << 16) | ((uint32_t)frame_end << 24)); } /*! \brief read DCI data register \param[in] none \param[out] none - \retval data + \retval data of DCI data register */ uint32_t dci_data_read(void) { @@ -259,18 +256,18 @@ uint32_t dci_data_read(void) FlagStatus dci_flag_get(uint32_t flag) { uint32_t stat = 0U; - - if(flag >> 31){ + + if(flag >> 31) { /* get flag status from DCI_STAT1 register */ stat = DCI_STAT1; - }else{ + } else { /* get flag status from DCI_STAT0 register */ stat = DCI_STAT0; } - - if(flag & stat){ + + if(flag & stat) { return SET; - }else{ + } else { return RESET; } } @@ -280,7 +277,7 @@ FlagStatus dci_flag_get(uint32_t flag) \param[in] interrupt: \arg DCI_INT_EF: end of frame interrupt \arg DCI_INT_OVR: FIFO overrun interrupt - \arg DCI_INT_ESE: embedded synchronous error interrupt + \arg DCI_INT_ESE: embedded synchronous error interrupt \arg DCI_INT_VSYNC: vsync interrupt \arg DCI_INT_EL: end of line interrupt \param[out] none @@ -296,7 +293,7 @@ void dci_interrupt_enable(uint32_t interrupt) \param[in] interrupt: \arg DCI_INT_EF: end of frame interrupt \arg DCI_INT_OVR: FIFO overrun interrupt - \arg DCI_INT_ESE: embedded synchronous error interrupt + \arg DCI_INT_ESE: embedded synchronous error interrupt \arg DCI_INT_VSYNC: vsync interrupt \arg DCI_INT_EL: end of line interrupt \param[out] none @@ -312,7 +309,7 @@ void dci_interrupt_disable(uint32_t interrupt) \param[in] int_flag: \arg DCI_INT_FLAG_EF: end of frame interrupt flag \arg DCI_INT_FLAG_OVR: FIFO overrun interrupt flag - \arg DCI_INT_FLAG_ESE: embedded synchronous error interrupt flag + \arg DCI_INT_FLAG_ESE: embedded synchronous error interrupt flag \arg DCI_INT_FLAG_VSYNC: vsync interrupt flag \arg DCI_INT_FLAG_EL: end of line interrupt flag \param[out] none @@ -320,9 +317,9 @@ void dci_interrupt_disable(uint32_t interrupt) */ FlagStatus dci_interrupt_flag_get(uint32_t int_flag) { - if(RESET == (DCI_INTF & int_flag)){ + if(RESET == (DCI_INTF & int_flag)) { return RESET; - }else{ + } else { return SET; } } @@ -332,7 +329,7 @@ FlagStatus dci_interrupt_flag_get(uint32_t int_flag) \param[in] int_flag: \arg DCI_INT_EF: end of frame interrupt \arg DCI_INT_OVR: FIFO overrun interrupt - \arg DCI_INT_ESE: embedded synchronous error interrupt + \arg DCI_INT_ESE: embedded synchronous error interrupt \arg DCI_INT_VSYNC: vsync interrupt \arg DCI_INT_EL: end of line interrupt \param[out] none diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_dma.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_dma.c index 7a0650e7..f41c1308 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_dma.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_dma.c @@ -2,46 +2,42 @@ \file gd32f20x_dma.c \brief DMA driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f20x_dma.h" -#include "gd32f20x_rcu.h" #define DMA_WRONG_HANDLE while(1){} /*! - \brief deinitialize DMA a channel registers + \brief deinitialize a DMA channel registers \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel is deinitialized @@ -60,23 +56,23 @@ void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE; DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); - - if((DMA1 == dma_periph) && (DMA_CH5 == channelx)){ + + if((DMA1 == dma_periph) && (DMA_CH5 == channelx)) { DMA_ACFG = DMA_ACFG_RESET_VALUE; } } /*! \brief initialize the parameters of DMA struct with the default values - \param[in] init_struct: the initialization data needed to initialize DMA channel - \param[out] none + \param[in] none + \param[out] init_struct: the initialization data needed to initialize DMA channel \retval none */ -void dma_struct_para_init(dma_parameter_struct* init_struct) +void dma_struct_para_init(dma_parameter_struct *init_struct) { /* set the DMA struct with the default values */ init_struct->periph_addr = 0U; - init_struct->periph_width = 0U; + init_struct->periph_width = 0U; init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE; init_struct->memory_addr = 0U; init_struct->memory_width = 0U; @@ -96,12 +92,12 @@ void dma_struct_para_init(dma_parameter_struct* init_struct) \param[in] init_struct: the data needed to initialize DMA channel periph_addr: peripheral base address periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT - periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE + periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE memory_addr: memory base address memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL - number: the number of remaining data to be transferred by the DMA + number: the number of remaining data to be transferred by the DMA, 0 - 0xFFFF priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH \param[out] none \retval none @@ -112,13 +108,13 @@ void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_stru /* configure peripheral base address */ DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr; - + /* configure memory base address */ DMA_CHMADDR(dma_periph, channelx) = init_struct->memory_addr; - + /* configure the number of remaining data to be transferred */ DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); - + /* configure peripheral transfer width,memory transfer width, */ ctl = DMA_CHCTL(dma_periph, channelx); ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); @@ -126,36 +122,36 @@ void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_stru DMA_CHCTL(dma_periph, channelx) = ctl; /* configure peripheral increasing mode */ - if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){ + if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) { DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; - }else{ + } else { DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; } /* configure memory increasing mode */ - if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){ + if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) { DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; - }else{ + } else { DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; } - + /* configure the direction of data transfer */ - if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction){ + if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction) { DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; - }else{ + } else { DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; - } + } } /*! - \brief enable DMA circulation mode + \brief enable DMA circulation mode \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) \param[out] none - \retval none + \retval none */ void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) { @@ -163,14 +159,14 @@ void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) } /*! - \brief disable DMA circulation mode + \brief disable DMA circulation mode \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) \param[out] none - \retval none + \retval none */ void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) { @@ -181,7 +177,7 @@ void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) \brief enable memory to memory mode \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) \param[out] none @@ -208,14 +204,14 @@ void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx } /*! - \brief enable DMA channel + \brief enable DMA channel \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) \param[out] none - \retval none + \retval none */ void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) { @@ -223,14 +219,14 @@ void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) } /*! - \brief disable DMA channel + \brief disable DMA channel \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) \param[out] none - \retval none + \retval none */ void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) { @@ -238,15 +234,15 @@ void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) } /*! - \brief set DMA peripheral base address + \brief set DMA peripheral base address \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set peripheral base address + \param[in] channelx: specify which DMA channel to set peripheral base address only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) \param[in] address: peripheral base address \param[out] none - \retval none + \retval none */ void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) { @@ -254,15 +250,15 @@ void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, u } /*! - \brief set DMA memory base address + \brief set DMA memory base address \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set memory base address + \param[in] channelx: specify which DMA channel to set memory base address only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) \param[in] address: memory base address \param[out] none - \retval none + \retval none */ void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) { @@ -270,16 +266,16 @@ void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, u } /*! - \brief set the number of remaining data to be transferred by the DMA + \brief set the number of remaining data to be transferred by the DMA \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set number + \param[in] channelx: specify which DMA channel to set number only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) \param[in] number: the number of remaining data to be transferred by the DMA \arg 0x0000-0xFFFF \param[out] none - \retval none + \retval none */ void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) { @@ -287,14 +283,14 @@ void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, } /*! - \brief get the number of remaining data to be transferred by the DMA + \brief get the number of remaining data to be transferred by the DMA \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set number + \param[in] channelx: specify which DMA channel to set number only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) \param[out] none - \retval uint32_t: the number of remaining data to be transferred by the DMA + \retval uint32_t: the number of remaining data to be transferred by the DMA */ uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) { @@ -302,10 +298,10 @@ uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) } /*! - \brief configure priority level of DMA channel + \brief configure priority level of DMA channel \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) \param[in] priority: priority Level of this channel @@ -315,7 +311,7 @@ uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) \arg DMA_PRIORITY_HIGH: high priority \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority \param[out] none - \retval none + \retval none */ void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) { @@ -323,17 +319,17 @@ void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_ /* acquire DMA_CHxCTL register */ ctl = DMA_CHCTL(dma_periph, channelx); - /* assign regiser */ + /* assign register */ ctl &= ~DMA_CHXCTL_PRIO; ctl |= priority; DMA_CHCTL(dma_periph, channelx) = ctl; } /*! - \brief configure transfer data size of memory + \brief configure transfer data size of memory \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) \param[in] mwidth: transfer data width of memory @@ -357,10 +353,10 @@ void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uin } /*! - \brief configure transfer data size of peripheral + \brief configure transfer data size of peripheral \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) \param[in] pwidth: transfer data width of peripheral @@ -377,17 +373,17 @@ void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uin /* acquire DMA_CHxCTL register */ ctl = DMA_CHCTL(dma_periph, channelx); - /* assign regiser */ + /* assign register */ ctl &= ~DMA_CHXCTL_PWIDTH; ctl |= pwidth; DMA_CHCTL(dma_periph, channelx) = ctl; } /*! - \brief enable next address increasement algorithm of memory + \brief enable next address increasement algorithm of memory \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) \param[out] none @@ -399,10 +395,10 @@ void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) } /*! - \brief disable next address increasement algorithm of memory + \brief disable next address increasement algorithm of memory \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) \param[out] none @@ -417,7 +413,7 @@ void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) \brief enable next address increasement algorithm of peripheral \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) \param[out] none @@ -429,10 +425,10 @@ void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) } /*! - \brief disable next address increasement algorithm of peripheral + \brief disable next address increasement algorithm of peripheral \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) \param[out] none @@ -444,10 +440,10 @@ void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) } /*! - \brief configure the direction of data transfer on the channel + \brief configure the direction of data transfer on the channel \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) \param[in] direction: specify the direction of data transfer @@ -459,15 +455,37 @@ void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) */ void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction) { - if(DMA_PERIPHERAL_TO_MEMORY == direction){ + if(DMA_PERIPHERAL_TO_MEMORY == direction) { DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; - }else{ + } else { DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; } } /*! - \brief check DMA flag is set or not + \brief enable the DMA1 channel 5 Full_Data transfer mode + \param[in] none + \param[out] none + \retval none +*/ +void dma_1_channel_5_fulldata_transfer_enable(void) +{ + DMA_ACFG |= DMA_ACFG_FD_CH5EN; +} + +/*! + \brief disable the DMA1 channel 5 Full_Data transfer mode + \param[in] none + \param[out] none + \retval none +*/ +void dma_1_channel_5_fulldata_transfer_disable(void) +{ + DMA_ACFG &= ~DMA_ACFG_FD_CH5EN; +} + +/*! + \brief check DMA flag is set or not \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) \param[in] channelx: specify which DMA channel to get flag @@ -487,12 +505,12 @@ FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t FlagStatus reval; /* check whether the flag is set or not */ - if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))){ + if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))) { reval = SET; - }else{ + } else { reval = RESET; } - + return reval; } @@ -517,93 +535,15 @@ void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t fla DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); } -/*! - \brief check DMA flag and interrupt enable bit is set or not - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to get flag - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_INT_FLAG_G: global interrupt flag of channel - \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_ERR: error interrupt flag of channel - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - uint32_t interrupt_enable = 0U, interrupt_flag = 0U; - uint32_t gif_check = 0x0FU, gif_enable = 0x0EU; - - switch(flag){ - case DMA_INT_FLAG_FTF: - /* check whether the full transfer finish interrupt flag is set and enabled */ - interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); - interrupt_flag = interrupt_flag >> ((channelx) * 4U); - interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; - break; - case DMA_INT_FLAG_HTF: - /* check whether the half transfer finish interrupt flag is set and enabled */ - interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); - interrupt_flag = interrupt_flag >> ((channelx) * 4U); - interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; - break; - case DMA_INT_FLAG_ERR: - /* check whether the error interrupt flag is set and enabled */ - interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); - interrupt_flag = interrupt_flag >> ((channelx) * 4U); - interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE; - break; - case DMA_INT_FLAG_G: - interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(gif_check, channelx); - interrupt_flag = interrupt_flag >> ((channelx) * 4U); - interrupt_enable = DMA_CHCTL(dma_periph, channelx) & gif_enable; - break; - default: - DMA_WRONG_HANDLE - } - - /* when the interrupt flag is set and enabled, return SET */ - if(interrupt_flag && interrupt_enable){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear DMA a channel flag - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to clear flag - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_INT_FLAG_G: global interrupt flag of channel - \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_ERR: error interrupt flag of channel - \param[out] none - \retval none -*/ -void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); -} - /*! \brief enable DMA interrupt \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) \param[in] source: specify which interrupt to enbale - one or more parameters can be selected which are shown as below + one or more parameters can be selected which are shown as below: \arg DMA_INT_FTF: channel full transfer finish interrupt \arg DMA_INT_HTF: channel half transfer finish interrupt \arg DMA_INT_ERR: channel error interrupt @@ -619,11 +559,11 @@ void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32 \brief disable DMA interrupt \param[in] dma_periph: DMAx(x=0,1) \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel + \param[in] channelx: specify which DMA channel only one parameter can be selected which is shown as below: \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) - \param[in] source: specify which interrupt to disbale - one or more parameters can be selected which are shown as below + \param[in] source: specify which interrupt to disable + one or more parameters can be selected which are shown as below: \arg DMA_INT_FTF: channel full transfer finish interrupt \arg DMA_INT_HTF: channel half transfer finish interrupt \arg DMA_INT_ERR: channel error interrupt @@ -636,23 +576,79 @@ void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint3 } /*! - \brief enable the DMA1 channel 5 Full_Data transfer mode - \param[in] none + \brief check DMA flag and interrupt enable bit is set or not + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to get flag + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_G: global interrupt flag of channel + \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_ERR: error interrupt flag of channel \param[out] none - \retval none + \retval FlagStatus: SET or RESET */ -void dma_1_channel_5_fulldata_transfer_enable(void) +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) { - DMA_ACFG |= DMA_ACFG_FD_CH5EN; + uint32_t interrupt_enable = 0U, interrupt_flag = 0U; + uint32_t gif_check = 0x0FU, gif_enable = 0x0EU; + + switch(flag) { + case DMA_INT_FLAG_FTF: + /* check whether the full transfer finish interrupt flag is set and enabled */ + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_flag = interrupt_flag >> ((channelx) * 4U); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; + break; + case DMA_INT_FLAG_HTF: + /* check whether the half transfer finish interrupt flag is set and enabled */ + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_flag = interrupt_flag >> ((channelx) * 4U); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; + break; + case DMA_INT_FLAG_ERR: + /* check whether the error interrupt flag is set and enabled */ + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_flag = interrupt_flag >> ((channelx) * 4U); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE; + break; + case DMA_INT_FLAG_G: + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(gif_check, channelx); + interrupt_flag = interrupt_flag >> ((channelx) * 4U); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & gif_enable; + break; + default: + DMA_WRONG_HANDLE + } + + /* when the interrupt flag is set and enabled, return SET */ + if(interrupt_flag && interrupt_enable) { + return SET; + } else { + return RESET; + } } /*! - \brief disable the DMA1 channel 5 Full_Data transfer mode - \param[in] none + \brief clear DMA a channel flag + \param[in] dma_periph: DMAx(x=0,1) + \arg DMAx(x=0,1) + \param[in] channelx: specify which DMA channel to clear flag + only one parameter can be selected which is shown as below: + \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..6) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_G: global interrupt flag of channel + \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel + \arg DMA_INT_FLAG_ERR: error interrupt flag of channel \param[out] none \retval none */ -void dma_1_channel_5_fulldata_transfer_disable(void) +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) { - DMA_ACFG &= ~DMA_ACFG_FD_CH5EN; + DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); } diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_enet.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_enet.c index 7748d7d9..ce05fc8f 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_enet.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_enet.c @@ -2,36 +2,33 @@ \file gd32f20x_enet.c \brief ENET driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -40,13 +37,13 @@ OF SUCH DAMAGE. #ifdef GD32F20X_CL #if defined (__CC_ARM) /*!< ARM compiler */ -__align(4) +__align(4) enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ -__align(4) +__align(4) enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ -__align(4) +__align(4) uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ -__align(4) +__align(4) uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ #elif defined ( __ICCARM__ ) /*!< IAR compiler */ @@ -60,10 +57,10 @@ uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive bu uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ #elif defined (__GNUC__) /* GNU Compiler */ -enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM] __attribute__ ((aligned (4))); /*!< ENET RxDMA descriptor */ -enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM] __attribute__ ((aligned (4))); /*!< ENET TxDMA descriptor */ -uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE] __attribute__ ((aligned (4))); /*!< ENET receive buffer */ -uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE] __attribute__ ((aligned (4))); /*!< ENET transmit buffer */ +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM] __attribute__((aligned(4))); /*!< ENET RxDMA descriptor */ +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM] __attribute__((aligned(4))); /*!< ENET TxDMA descriptor */ +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE] __attribute__((aligned(4))); /*!< ENET receive buffer */ +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE] __attribute__((aligned(4))); /*!< ENET transmit buffer */ #endif /* __CC_ARM */ @@ -76,21 +73,22 @@ enet_descriptors_struct *dma_current_ptp_txdesc = NULL; enet_descriptors_struct *dma_current_ptp_rxdesc = NULL; /* init structure parameters for ENET initialization */ -static enet_initpara_struct enet_initpara ={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; +static enet_initpara_struct enet_initpara = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static uint32_t enet_unknow_err = 0U; /* array of register offset for debug information get */ static const uint16_t enet_reg_tab[] = { -0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x1080, 0x001C, 0x0028, 0x002C, -0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C, - -0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, - -0x0700, 0x0704,0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, - -0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1048, 0x104C, -0x1050, 0x1054}; + 0x0000U, 0x0004U, 0x0008U, 0x000CU, 0x0010U, 0x0014U, 0x0018U, 0x1080U, 0x001CU, 0x0028U, 0x002CU, + + 0x0038U, 0x003CU, 0x0040U, 0x0044U, 0x0048U, 0x004CU, 0x0050U, 0x0054U, 0x0058U, 0x005CU, 0x0100U, + + 0x0104U, 0x0108U, 0x010CU, 0x0110U, 0x014CU, 0x0150U, 0x0168U, 0x0194U, 0x0198U, 0x01C4U, 0x0700U, + + 0x0704U, 0x0708U, 0x070CU, 0x0710U, 0x0714U, 0x0718U, 0x071CU, 0x0720U, 0x1000U, 0x1004U, 0x1008U, + + 0x100CU, 0x1010U, 0x1014U, 0x1018U, 0x101CU, 0x1020U, 0x1048U, 0x104CU, 0x1050U, 0x1054U +}; /*! @@ -108,16 +106,16 @@ void enet_deinit(void) /*! \brief configure the parameters which are usually less cared for initialization - note -- this function must be called before enet_init(), otherwise + note -- this function must be called before enet_init(), otherwise configuration will be no effect - \param[in] option: different function option, which is related to several parameters, + \param[in] option: different function option, which is related to several parameters, only one parameter can be selected which is shown as below, refer to enet_option_enum \arg FORWARD_OPTION: choose to configure the frame forward related parameters \arg DMABUS_OPTION: choose to configure the DMA bus mode related parameters \arg DMA_MAXBURST_OPTION: choose to configure the DMA max burst related parameters \arg DMA_ARBITRATION_OPTION: choose to configure the DMA arbitration related parameters \arg STORE_OPTION: choose to configure the store forward mode related parameters - \arg DMA_OPTION: choose to configure the DMA descriptor related parameters + \arg DMA_OPTION: choose to configure the DMA descriptor related parameters \arg VLAN_OPTION: choose to configure vlan related parameters \arg FLOWCTL_OPTION: choose to configure flow control related parameters \arg HASHH_OPTION: choose to configure hash high @@ -126,7 +124,7 @@ void enet_deinit(void) \arg HALFDUPLEX_OPTION: choose to configure halfduplex mode related parameters \arg TIMER_OPTION: choose to configure time counter related parameters \arg INTERFRAMEGAP_OPTION: choose to configure the inter frame gap related parameters - \param[in] para: the related parameters according to the option + \param[in] para: the related parameters according to the option all the related parameters should be configured which are shown as below FORWARD_OPTION related parameters: - ENET_AUTO_PADCRC_DROP_ENABLE/ ENET_AUTO_PADCRC_DROP_DISABLE ; @@ -169,7 +167,7 @@ void enet_deinit(void) FLOWCTL_OPTION related parameters: - MAC_FCTL_PTM(regval) ; - ENET_ZERO_QUANTA_PAUSE_ENABLE/ ENET_ZERO_QUANTA_PAUSE_DISABLE ; - - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ + - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ; - ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ; - ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ; @@ -187,7 +185,15 @@ void enet_deinit(void) - ENET_UNICAST_FILTER_EITHER/ ENET_UNICAST_FILTER_HASH/ ENET_UNICAST_FILTER_PERFECT ; - ENET_PCFRM_PREVENT_ALL/ ENET_PCFRM_PREVENT_PAUSEFRAME/ - ENET_PCFRM_FORWARD_ALL/ ENET_PCFRM_FORWARD_FILTERED . + ENET_PCFRM_FORWARD_ALL/ ENET_PCFRM_FORWARD_FILTERED ; + - ENET_ACTIVE_THRESHOLD_256BYTES/ ENET_ACTIVE_THRESHOLD_512BYTES ; + - ENET_ACTIVE_THRESHOLD_768BYTES/ ENET_ACTIVE_THRESHOLD_1024BYTES ; + - ENET_ACTIVE_THRESHOLD_1280BYTES/ ENET_ACTIVE_THRESHOLD_1536BYTES ; + - ENET_ACTIVE_THRESHOLD_1792BYTES ; + - ENET_DEACTIVE_THRESHOLD_256BYTES/ ENET_DEACTIVE_THRESHOLD_512BYTES ; + - ENET_DEACTIVE_THRESHOLD_768BYTES/ ENET_DEACTIVE_THRESHOLD_1024BYTES ; + - ENET_DEACTIVE_THRESHOLD_1280BYTES/ ENET_DEACTIVE_THRESHOLD_1536BYTES ; + - ENET_DEACTIVE_THRESHOLD_1792BYTES . HALFDUPLEX_OPTION related parameters: - ENET_CARRIERSENSE_ENABLE/ ENET_CARRIERSENSE_DISABLE ; - ENET_RECEIVEOWN_ENABLE/ ENET_RECEIVEOWN_DISABLE ; @@ -203,12 +209,12 @@ void enet_deinit(void) ENET_INTERFRAMEGAP_80BIT/ ENET_INTERFRAMEGAP_72BIT/ ENET_INTERFRAMEGAP_64BIT/ ENET_INTERFRAMEGAP_56BIT/ ENET_INTERFRAMEGAP_48BIT/ ENET_INTERFRAMEGAP_40BIT . - \param[out] none + \param[out] none \retval none */ void enet_initpara_config(enet_option_enum option, uint32_t para) { - switch(option){ + switch(option) { case FORWARD_OPTION: /* choose to configure forward_frame, and save the configuration parameters */ enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION; @@ -272,7 +278,7 @@ void enet_initpara_config(enet_option_enum option, uint32_t para) case TIMER_OPTION: /* choose to configure timer_config, and save the configuration parameters */ enet_initpara.option_enable |= (uint32_t)TIMER_OPTION; - enet_initpara.timer_config = para; + enet_initpara.timer_config = para; break; case INTERFRAMEGAP_OPTION: /* choose to configure interframegap, and save the configuration parameters */ @@ -280,15 +286,15 @@ void enet_initpara_config(enet_option_enum option, uint32_t para) enet_initpara.interframegap = para; break; default: - break; - } -} + break; + } +} /*! - \brief initialize ENET peripheral with generally concerned parameters and the less cared + \brief initialize ENET peripheral with generally concerned parameters and the less cared parameters \param[in] mediamode: PHY mode and mac loopback configurations, only one parameter can be selected - which is shown as below, refer to enet_mediamode_enum + which is shown as below, refer to enet_mediamode_enum \arg ENET_AUTO_NEGOTIATION: PHY auto negotiation \arg ENET_100M_FULLDUPLEX: 100Mbit/s, full-duplex \arg ENET_100M_HALFDUPLEX: 100Mbit/s, half-duplex @@ -296,135 +302,136 @@ void enet_initpara_config(enet_option_enum option, uint32_t para) \arg ENET_10M_HALFDUPLEX: 10Mbit/s, half-duplex \arg ENET_LOOPBACKMODE: MAC in loopback mode at the MII \param[in] checksum: IP frame checksum offload function, only one parameter can be selected - which is shown as below, refer to enet_mediamode_enum + which is shown as below, refer to enet_mediamode_enum \arg ENET_NO_AUTOCHECKSUM: disable IP frame checksum function \arg ENET_AUTOCHECKSUM_DROP_FAILFRAMES: enable IP frame checksum function \arg ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES: enable IP frame checksum function, and the received frame with only payload error but no other errors will not be dropped \param[in] recept: frame filter function, only one parameter can be selected - which is shown as below, refer to enet_frmrecept_enum + which is shown as below, refer to enet_frmrecept_enum \arg ENET_PROMISCUOUS_MODE: promiscuous mode enabled \arg ENET_RECEIVEALL: all received frame are forwarded to application \arg ENET_BROADCAST_FRAMES_PASS: the address filters pass all received broadcast frames \arg ENET_BROADCAST_FRAMES_DROP: the address filters filter all incoming broadcast frames - \param[out] none + \param[out] none \retval ErrStatus: ERROR or SUCCESS */ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept) { - uint32_t reg_value=0U, reg_temp = 0U, temp = 0U; + uint32_t reg_value = 0U, reg_temp = 0U, temp = 0U; uint32_t media_temp = 0U; uint32_t timeout = 0U; uint16_t phy_value = 0U; - ErrStatus phy_state= ERROR, enet_state = ERROR; + ErrStatus phy_state = ERROR, enet_state = ERROR; /* PHY interface configuration, configure SMI clock and reset PHY chip */ -// if(ERROR == enet_phy_config()){ -// _ENET_DELAY_(PHY_RESETDELAY); -// if(ERROR == enet_phy_config()){ -// return enet_state; -// } -// } +/** AvV **/ +// if(ERROR == enet_phy_config()) { +// _ENET_DELAY_(PHY_RESETDELAY); +// if(ERROR == enet_phy_config()) { +// return enet_state; +// } +// } +/** AvV **/ /* initialize ENET peripheral with generally concerned parameters */ enet_default_init(); /* 1st, configure mediamode */ media_temp = (uint32_t)mediamode; /* if is PHY auto negotiation */ - if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp){ + if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp) { /* wait for PHY_LINKED_STATUS bit be set */ - do{ + do { enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); - phy_value &= PHY_LINKED_STATUS; + phy_value &= PHY_LINKED_STATUS; timeout++; - }while((RESET == phy_value) && (timeout < PHY_READ_TO)); + } while((RESET == phy_value) && (timeout < PHY_READ_TO)); /* return ERROR due to timeout */ - if(PHY_READ_TO == timeout){ + if(PHY_READ_TO == timeout) { return enet_state; } - /* reset timeout counter */ timeout = 0U; /* enable auto-negotiation */ phy_value = PHY_AUTONEGOTIATION; phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); - if(!phy_state){ + if(!phy_state) { /* return ERROR due to write timeout */ return enet_state; } /* wait for the PHY_AUTONEGO_COMPLETE bit be set */ - do{ + do { enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); phy_value &= PHY_AUTONEGO_COMPLETE; timeout++; - }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); + } while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); /* return ERROR due to timeout */ - if(PHY_READ_TO == timeout){ + if(PHY_READ_TO == timeout) { return enet_state; } - /* reset timeout counter */ timeout = 0U; /* read the result of the auto-negotiation */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); /* configure the duplex mode of MAC following the auto-negotiation result */ - if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)){ + if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)) { media_temp = ENET_MODE_FULLDUPLEX; - }else{ + } else { media_temp = ENET_MODE_HALFDUPLEX; } - /* configure the communication speed of MAC following the auto-negotiation result */ #if(PHY_TYPE == RTL8201F) /** AvV **/ if ((uint16_t) RESET == (phy_value & PHY_SPEED_STATUS)) { #else if ((uint16_t) RESET != (phy_value & PHY_SPEED_STATUS)) { #endif - media_temp |= ENET_SPEEDMODE_10M; - } else { - media_temp |= ENET_SPEEDMODE_100M; - } - }else{ -// phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3); -// phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1); -// phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); -// if(!phy_state){ -// /* return ERROR due to write timeout */ -// return enet_state; -// } -// /* PHY configuration need some time */ -// _ENET_DELAY_(PHY_CONFIGDELAY); + media_temp |= ENET_SPEEDMODE_10M; + } else { + media_temp |= ENET_SPEEDMODE_100M; + } + } else { +/** AvV **/ +// phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3U); +// phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1U); +// phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); +// if(!phy_state) { +// /* return ERROR due to write timeout */ +// return enet_state; +// } +// /* PHY configuration need some time */ +// _ENET_DELAY_(PHY_CONFIGDELAY); +/** AvV **/ } /* after configuring the PHY, use mediamode to configure registers */ reg_value = ENET_MAC_CFG; /* configure ENET_MAC_CFG register */ - reg_value &= (~(ENET_MAC_CFG_SPD |ENET_MAC_CFG_DPM |ENET_MAC_CFG_LBM)); + reg_value &= (~(ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM | ENET_MAC_CFG_LBM)); reg_value |= media_temp; ENET_MAC_CFG = reg_value; - - + + /* 2st, configure checksum */ - if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)){ + if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)) { ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE; - + reg_value = ENET_DMA_CTL; /* configure ENET_DMA_CTL register */ reg_value &= ~ENET_DMA_CTL_DTCERFD; reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD); ENET_DMA_CTL = reg_value; } - - /* 3rd, configure recept */ + + /* 3rd, configure receipt */ ENET_MAC_FRMF |= (uint32_t)recept; - + /* 4th, configure different function options */ /* configure forward_frame related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)) { reg_temp = enet_initpara.forward_frame; - + reg_value = ENET_MAC_CFG; temp = reg_temp; /* configure ENET_MAC_CFG register */ @@ -432,76 +439,76 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum temp &= ENET_MAC_CFG_APCD; reg_value |= temp; ENET_MAC_CFG = reg_value; - + reg_value = ENET_DMA_CTL; temp = reg_temp; /* configure ENET_DMA_CTL register */ - reg_value &= (~(ENET_DMA_CTL_FERF |ENET_DMA_CTL_FUF)); - temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)<<2); + reg_value &= (~(ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)); + temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF) << 2); reg_value |= (temp >> 2); ENET_DMA_CTL = reg_value; } /* configure dmabus_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)) { temp = enet_initpara.dmabus_mode; - + reg_value = ENET_DMA_BCTL; /* configure ENET_DMA_BCTL register */ reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \ - |ENET_DMA_BCTL_FPBL); + | ENET_DMA_BCTL_FPBL); reg_value |= temp; ENET_DMA_BCTL = reg_value; } /* configure dma_maxburst related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)) { temp = enet_initpara.dma_maxburst; - + reg_value = ENET_DMA_BCTL; /* configure ENET_DMA_BCTL register */ - reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); + reg_value &= ~(ENET_DMA_BCTL_RXDP | ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); reg_value |= temp; ENET_DMA_BCTL = reg_value; } /* configure dma_arbitration related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)) { temp = enet_initpara.dma_arbitration; - + reg_value = ENET_DMA_BCTL; /* configure ENET_DMA_BCTL register */ reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB); reg_value |= temp; ENET_DMA_BCTL = reg_value; } - + /* configure store_forward_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)) { temp = enet_initpara.store_forward_mode; - + reg_value = ENET_DMA_CTL; /* configure ENET_DMA_CTL register */ - reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD| ENET_DMA_CTL_RTHC| ENET_DMA_CTL_TTHC); + reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD | ENET_DMA_CTL_RTHC | ENET_DMA_CTL_TTHC); reg_value |= temp; ENET_DMA_CTL = reg_value; } /* configure dma_function related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)) { reg_temp = enet_initpara.dma_function; - + reg_value = ENET_DMA_CTL; /* configure ENET_DMA_CTL register */ - reg_value &= (~(ENET_DMA_CTL_DAFRF |ENET_DMA_CTL_OSF)); + reg_value &= (~(ENET_DMA_CTL_DAFRF | ENET_DMA_CTL_OSF)); reg_value |= reg_temp; ENET_DMA_CTL = reg_value; } /* configure vlan_config related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)) { reg_temp = enet_initpara.vlan_config; - + reg_value = ENET_MAC_VLT; /* configure ENET_MAC_VLT register */ reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC); @@ -510,84 +517,84 @@ ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum } /* configure flow_control related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)) { reg_temp = enet_initpara.flow_control; - + reg_value = ENET_MAC_FCTL; temp = reg_temp; /* configure ENET_MAC_FCTL register */ - reg_value &= ~(ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ - | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); - temp &= (ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ - | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); + reg_value &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_DZQP | ENET_MAC_FCTL_PLTS \ + | ENET_MAC_FCTL_UPFDT | ENET_MAC_FCTL_RFCEN | ENET_MAC_FCTL_TFCEN); + temp &= (ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_DZQP | ENET_MAC_FCTL_PLTS \ + | ENET_MAC_FCTL_UPFDT | ENET_MAC_FCTL_RFCEN | ENET_MAC_FCTL_TFCEN); reg_value |= temp; ENET_MAC_FCTL = reg_value; - + reg_value = ENET_MAC_FCTH; temp = reg_temp; /* configure ENET_MAC_FCTH register */ - reg_value &= ~(ENET_MAC_FCTH_RFA |ENET_MAC_FCTH_RFD); - temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD )<<8); - reg_value |= (temp >> 8); + reg_value &= ~(ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD); + temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD) << 8U); + reg_value |= (temp >> 8U); ENET_MAC_FCTH = reg_value; - } - + } + /* configure hashtable_high related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)) { ENET_MAC_HLH = enet_initpara.hashtable_high; - } + } /* configure hashtable_low related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)) { ENET_MAC_HLL = enet_initpara.hashtable_low; - } + } /* configure framesfilter_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)) { reg_temp = enet_initpara.framesfilter_mode; - + reg_value = ENET_MAC_FRMF; /* configure ENET_MAC_FRMF register */ reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \ - | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \ - | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM); + | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \ + | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM); reg_value |= reg_temp; ENET_MAC_FRMF = reg_value; - } + } /* configure halfduplex_param related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)) { reg_temp = enet_initpara.halfduplex_param; - + reg_value = ENET_MAC_CFG; /* configure ENET_MAC_CFG register */ reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \ - | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC); + | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC); reg_value |= reg_temp; ENET_MAC_CFG = reg_value; - } + } /* configure timer_config related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)) { reg_temp = enet_initpara.timer_config; - + reg_value = ENET_MAC_CFG; /* configure ENET_MAC_CFG register */ reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD); reg_value |= reg_temp; ENET_MAC_CFG = reg_value; - } - + } + /* configure interframegap related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){ + if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)) { reg_temp = enet_initpara.interframegap; - + reg_value = ENET_MAC_CFG; /* configure ENET_MAC_CFG register */ reg_value &= ~ENET_MAC_CFG_IGBS; reg_value |= reg_temp; ENET_MAC_CFG = reg_value; - } + } enet_state = SUCCESS; return enet_state; @@ -604,21 +611,21 @@ ErrStatus enet_software_reset(void) uint32_t timeout = 0U; ErrStatus enet_state = ERROR; uint32_t dma_flag; - + /* reset all core internal registers located in CLK_TX and CLK_RX */ ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR; - + /* wait for reset operation complete */ - do{ + do { dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR); timeout++; - }while((RESET != dma_flag) && (ENET_DELAY_TO != timeout)); + } while((RESET != dma_flag) && (ENET_DELAY_TO != timeout)); - /* reset operation complete */ - if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)){ + /* reset operation complete */ + if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)) { enet_state = SUCCESS; } - + return enet_state; } @@ -632,19 +639,19 @@ uint32_t enet_rxframe_size_get(void) { uint32_t size = 0U; uint32_t status; - + /* get rdes0 information of current RxDMA descriptor */ status = dma_current_rxdesc->status; - - /* if the desciptor is owned by DMA */ - if((uint32_t)RESET != (status & ENET_RDES0_DAV)){ + + /* if the descriptor is owned by DMA */ + if((uint32_t)RESET != (status & ENET_RDES0_DAV)) { return 0U; } - + /* if has any error, or the frame uses two or more descriptors */ if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) || - (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) || - (((uint32_t)RESET) == (status & ENET_RDES0_FDES))){ + (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) || + (((uint32_t)RESET) == (status & ENET_RDES0_FDES))) { /* drop current receive frame */ enet_rxframe_drop(); @@ -653,30 +660,30 @@ uint32_t enet_rxframe_size_get(void) /* if is an ethernet-type frame, and IP frame payload error occurred */ if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) && - (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))){ - /* drop current receive frame */ - enet_rxframe_drop(); + (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))) { + /* drop current receive frame */ + enet_rxframe_drop(); return 1U; - } + } - /* if CPU owns current descriptor, no error occured, the frame uses only one descriptor */ + /* if CPU owns current descriptor, no error occurred, the frame uses only one descriptor */ if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) && - (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) && - (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) && - (((uint32_t)RESET) != (status & ENET_RDES0_FDES))){ + (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (status & ENET_RDES0_FDES))) { /* get the size of the received data including CRC */ size = GET_RDES0_FRML(status); - /* substract the CRC size */ + /* substract the CRC size */ size = size - 4U; - }else{ + } else { enet_unknow_err++; enet_rxframe_drop(); - return 1U; + return 1U; } - - /* return packet size */ + + /* return packet size */ return size; } @@ -694,62 +701,62 @@ void enet_descriptors_chain_init(enet_dmadirection_enum direction) uint32_t num = 0U, count = 0U, maxsize = 0U; uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc, *desc_tab; - uint8_t *buf; + uint8_t *buf; /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; maxsize = ENET_TXBUF_SIZE; - + /* select chain mode */ desc_status = ENET_TDES0_TCHM; - + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; maxsize = ENET_RXBUF_SIZE; - + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* select receive chained mode and set buffer1 size */ desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; + dma_current_rxdesc = desc_tab; } dma_current_ptp_rxdesc = NULL; dma_current_ptp_txdesc = NULL; - - /* configure each descriptor */ - for(num=0U; num < count; num++){ + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; + desc->status = desc_status; desc->control_buffer_size = desc_bufsize; desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + /* if is not the last descriptor */ - if(num < (count - 1U)){ + if(num < (count - 1U)) { /* configure the next descriptor address */ desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t) desc_tab; + } else { + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t) desc_tab; } - } + } } /*! @@ -767,64 +774,64 @@ void enet_descriptors_ring_init(enet_dmadirection_enum direction) uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc; enet_descriptors_struct *desc_tab; - uint8_t *buf; - + uint8_t *buf; + /* configure descriptor skip length */ ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - + /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - + maxsize = ENET_TXBUF_SIZE; + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - + maxsize = ENET_RXBUF_SIZE; + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* set buffer1 size */ desc_bufsize = ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ + + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; + dma_current_rxdesc = desc_tab; } dma_current_ptp_rxdesc = NULL; dma_current_ptp_txdesc = NULL; - - /* configure each descriptor */ - for(num=0U; num < count; num++){ + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ + if(num == (count - 1U)) { + if(ENET_DMA_TX == direction) { + /* configure transmit end of ring mode */ desc->status |= ENET_TDES0_TERM; - }else{ + } else { /* configure receive end of ring mode */ desc->control_buffer_size |= ENET_RDES1_RERM; } } - } + } } /*! @@ -837,64 +844,64 @@ void enet_descriptors_ring_init(enet_dmadirection_enum direction) ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) { uint32_t offset = 0U, size = 0U; - + /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ - return ERROR; + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { + return ERROR; } - + /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ + if(NULL != buffer) { /* if no error occurs, and the frame uses only one descriptor */ - if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ + if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))) { /* get the frame length except CRC */ size = GET_RDES0_FRML(dma_current_rxdesc->status); size = size - 4U; - + /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ + if(size > bufsize) { return ERROR; } - + /* copy data from Rx buffer to application buffer */ - for(offset = 0U; offsetbuffer1_addr) + offset)); + for(offset = 0U; offset < size; offset++) { + (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_rxdesc->buffer1_addr) + offset)); } - - }else{ + + } else { /* return ERROR */ return ERROR; } } /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - + dma_current_rxdesc->status = ENET_RDES0_DAV; + /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ + if((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { /* clear RBU flag */ ENET_DMA_STAT = ENET_DMA_STAT_RBU; /* resume DMA reception by writing to the RPEN register*/ ENET_DMA_RPEN = 0U; } - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + + /* update the current RxDMA descriptor pointer to the next descriptor in RxDMA descriptor table */ /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - }else{ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_rxdesc->buffer2_next_desc_addr); + } else { /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - }else{ + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + } else { /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); } } - + return SUCCESS; } @@ -910,55 +917,55 @@ ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) { uint32_t offset = 0U; uint32_t dma_tbu_flag, dma_tu_flag; - + /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) { return ERROR; } - + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ + if(length > ENET_MAX_FRAME_SIZE) { return ERROR; - } - + } + /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ + if(NULL != buffer) { /* copy frame data from application buffer to Tx buffer */ - for(offset = 0U; offset < length; offset++){ - (*(__IO uint8_t *) (uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + for(offset = 0U; offset < length; offset++) { + (*(__IO uint8_t *)(uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); } } - + /* set the frame length */ dma_current_txdesc->control_buffer_size = length; - /* set the segment of frame, frame is transmitted in one descriptor */ + /* set the segment of frame, frame is transmitted in one descriptor */ dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; /* enable the DMA transmission */ dma_current_txdesc->status |= ENET_TDES0_DAV; - + /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - - if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ + + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)) { /* clear TBU and TU flag */ ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); /* resume DMA transmission by writing to the TPEN register*/ ENET_DMA_TPEN = 0U; } - - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ + + /* update the current TxDMA descriptor pointer to the next descriptor in TxDMA descriptor table*/ /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); - }else{ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)) { + dma_current_txdesc = (enet_descriptors_struct *)(dma_current_txdesc->buffer2_next_desc_addr); + } else { /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)) { /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); - }else{ + dma_current_txdesc = (enet_descriptors_struct *)(ENET_DMA_TDTADDR); + } else { /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + dma_current_txdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); } } @@ -1008,18 +1015,18 @@ void enet_disable(void) } /*! - \brief configure MAC address - \param[in] mac_addr: select which MAC address will be set, - only one parameter can be selected which is shown as below + \brief configure MAC address + \param[in] mac_addr: select which MAC address will be set, + only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS0: set MAC address 0 filter \arg ENET_MAC_ADDRESS1: set MAC address 1 filter \arg ENET_MAC_ADDRESS2: set MAC address 2 filter \arg ENET_MAC_ADDRESS3: set MAC address 3 filter \param[in] paddr: the buffer pointer which stores the MAC address - (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) \param[out] none \retval none -*/ +*/ void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) { REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr); @@ -1027,7 +1034,7 @@ void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) } /*! - \brief get MAC address + \brief get MAC address \param[in] mac_addr: select which MAC address will be get, only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS0: get MAC address 0 filter @@ -1035,9 +1042,9 @@ void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) \arg ENET_MAC_ADDRESS2: get MAC address 2 filter \arg ENET_MAC_ADDRESS3: get MAC address 3 filter \param[out] paddr: the buffer pointer which is stored the MAC address - (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) \retval none -*/ +*/ void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) { paddr[0] = ENET_GET_MACADDR(mac_addr, 0U); @@ -1049,277 +1056,41 @@ void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) } /*! - \brief get the ENET MAC/MSC/PTP/DMA status flag - \param[in] enet_flag: ENET status flag, refer to enet_flag_enum, - only one parameter can be selected which is shown as below - \arg ENET_MAC_FLAG_MPKR: magic packet received flag - \arg ENET_MAC_FLAG_WUFR: wakeup frame received flag - \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag - \arg ENET_MAC_FLAG_WUM: WUM status flag - \arg ENET_MAC_FLAG_MSC: MSC status flag - \arg ENET_MAC_FLAG_MSCR: MSC receive status flag - \arg ENET_MAC_FLAG_MSCT: MSC transmit status flag - \arg ENET_MAC_FLAG_TMST: time stamp trigger status flag - \arg ENET_PTP_FLAG_TSSCO: timestamp second counter overflow flag - \arg ENET_PTP_FLAG_TTM: target time match flag - \arg ENET_MSC_FLAG_RFCE: received frames CRC error flag - \arg ENET_MSC_FLAG_RFAE: received frames alignment error flag - \arg ENET_MSC_FLAG_RGUF: received good unicast frames flag - \arg ENET_MSC_FLAG_TGFSC: transmitted good frames single collision flag - \arg ENET_MSC_FLAG_TGFMSC: transmitted good frames more single collision flag - \arg ENET_MSC_FLAG_TGF: transmitted good frames flag - \arg ENET_DMA_FLAG_TS: transmit status flag - \arg ENET_DMA_FLAG_TPS: transmit process stopped status flag - \arg ENET_DMA_FLAG_TBU: transmit buffer unavailable status flag - \arg ENET_DMA_FLAG_TJT: transmit jabber timeout status flag - \arg ENET_DMA_FLAG_RO: receive overflow status flag - \arg ENET_DMA_FLAG_TU: transmit underflow status flag - \arg ENET_DMA_FLAG_RS: receive status flag - \arg ENET_DMA_FLAG_RBU: receive buffer unavailable status flag - \arg ENET_DMA_FLAG_RPS: receive process stopped status flag - \arg ENET_DMA_FLAG_RWT: receive watchdog timeout status flag - \arg ENET_DMA_FLAG_ET: early transmit status flag - \arg ENET_DMA_FLAG_FBE: fatal bus error status flag - \arg ENET_DMA_FLAG_ER: early receive status flag - \arg ENET_DMA_FLAG_AI: abnormal interrupt summary flag - \arg ENET_DMA_FLAG_NI: normal interrupt summary flag - \arg ENET_DMA_FLAG_EB_DMA_ERROR: DMA error flag - \arg ENET_DMA_FLAG_EB_TRANSFER_ERROR: transfer error flag - \arg ENET_DMA_FLAG_EB_ACCESS_ERROR: access error flag - \arg ENET_DMA_FLAG_MSC: MSC status flag - \arg ENET_DMA_FLAG_WUM: WUM status flag - \arg ENET_DMA_FLAG_TST: timestamp trigger status flag + \brief ENET Tx function enable (include MAC and DMA module) + \param[in] none \param[out] none - \retval FlagStatus: SET or RESET + \retval none */ -FlagStatus enet_flag_get(enet_flag_enum enet_flag) +void enet_tx_enable(void) { - if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))){ - return SET; - }else{ - return RESET; - } + ENET_MAC_CFG |= ENET_MAC_CFG_TEN; + enet_txfifo_flush(); + ENET_DMA_CTL |= ENET_DMA_CTL_STE; } /*! - \brief clear the ENET DMA status flag - \param[in] enet_flag: ENET DMA flag clear, refer to enet_flag_clear_enum - only one parameter can be selected which is shown as below - \arg ENET_DMA_FLAG_TS_CLR: transmit status flag clear - \arg ENET_DMA_FLAG_TPS_CLR: transmit process stopped status flag clear - \arg ENET_DMA_FLAG_TBU_CLR: transmit buffer unavailable status flag clear - \arg ENET_DMA_FLAG_TJT_CLR: transmit jabber timeout status flag clear - \arg ENET_DMA_FLAG_RO_CLR: receive overflow status flag clear - \arg ENET_DMA_FLAG_TU_CLR: transmit underflow status flag clear - \arg ENET_DMA_FLAG_RS_CLR: receive status flag clear - \arg ENET_DMA_FLAG_RBU_CLR: receive buffer unavailable status flag clear - \arg ENET_DMA_FLAG_RPS_CLR: receive process stopped status flag clear - \arg ENET_DMA_FLAG_RWT_CLR: receive watchdog timeout status flag clear - \arg ENET_DMA_FLAG_ET_CLR: early transmit status flag clear - \arg ENET_DMA_FLAG_FBE_CLR: fatal bus error status flag clear - \arg ENET_DMA_FLAG_ER_CLR: early receive status flag clear - \arg ENET_DMA_FLAG_AI_CLR: abnormal interrupt summary flag clear - \arg ENET_DMA_FLAG_NI_CLR: normal interrupt summary flag clear + \brief ENET Tx function disable (include MAC and DMA module) + \param[in] none \param[out] none \retval none */ -void enet_flag_clear(enet_flag_clear_enum enet_flag) +void enet_tx_disable(void) { - /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ - ENET_REG_VAL(enet_flag) = BIT(ENET_BIT_POS(enet_flag)); + ENET_DMA_CTL &= ~ENET_DMA_CTL_STE; + enet_txfifo_flush(); + ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN; } /*! - \brief enable ENET MAC/MSC/DMA interrupt - \param[in] enet_int: ENET interrupt, - only one parameter can be selected which is shown as below - \arg ENET_MAC_INT_WUMIM: WUM interrupt mask - \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask - \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask - \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask - \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask - \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask - \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask - \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask - \arg ENET_DMA_INT_TIE: transmit interrupt enable - \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable - \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable - \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable - \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable - \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable - \arg ENET_DMA_INT_RIE: receive interrupt enable - \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable - \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable - \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable - \arg ENET_DMA_INT_ETIE: early transmit interrupt enable - \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable - \arg ENET_DMA_INT_ERIE: early receive interrupt enable - \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable - \arg ENET_DMA_INT_NIE: normal interrupt summary enable + \brief ENET Rx function enable (include MAC and DMA module) + \param[in] none \param[out] none \retval none */ -void enet_interrupt_enable(enet_int_enum enet_int) +void enet_rx_enable(void) { - if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ - /* ENET_DMA_INTEN register interrupt */ - ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); - }else{ - /* other INTMSK register interrupt */ - ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); - } -} - -/*! - \brief disable ENET MAC/MSC/DMA interrupt - \param[in] enet_int: ENET interrupt, - only one parameter can be selected which is shown as below - \arg ENET_MAC_INT_WUMIM: WUM interrupt mask - \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask - \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask - \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask - \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask - \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask - \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask - \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask - \arg ENET_DMA_INT_TIE: transmit interrupt enable - \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable - \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable - \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable - \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable - \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable - \arg ENET_DMA_INT_RIE: receive interrupt enable - \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable - \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable - \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable - \arg ENET_DMA_INT_ETIE: early transmit interrupt enable - \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable - \arg ENET_DMA_INT_ERIE: early receive interrupt enable - \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable - \arg ENET_DMA_INT_NIE: normal interrupt summary enable - \param[out] none - \retval none -*/ -void enet_interrupt_disable(enet_int_enum enet_int) -{ - if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ - /* ENET_DMA_INTEN register interrupt */ - ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); - }else{ - /* other INTMSK register interrupt */ - ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); - } -} - -/*! - \brief get ENET MAC/MSC/DMA interrupt flag - \param[in] int_flag: ENET interrupt flag, - only one parameter can be selected which is shown as below - \arg ENET_MAC_INT_FLAG_WUM: WUM status flag - \arg ENET_MAC_INT_FLAG_MSC: MSC status flag - \arg ENET_MAC_INT_FLAG_MSCR: MSC receive status flag - \arg ENET_MAC_INT_FLAG_MSCT: MSC transmit status flag - \arg ENET_MAC_INT_FLAG_TMST: time stamp trigger status flag - \arg ENET_MSC_INT_FLAG_RFCE: received frames CRC error flag - \arg ENET_MSC_INT_FLAG_RFAE: received frames alignment error flag - \arg ENET_MSC_INT_FLAG_RGUF: received good unicast frames flag - \arg ENET_MSC_INT_FLAG_TGFSC: transmitted good frames single collision flag - \arg ENET_MSC_INT_FLAG_TGFMSC: transmitted good frames more single collision flag - \arg ENET_MSC_INT_FLAG_TGF: transmitted good frames flag - \arg ENET_DMA_INT_FLAG_TS: transmit status flag - \arg ENET_DMA_INT_FLAG_TPS: transmit process stopped status flag - \arg ENET_DMA_INT_FLAG_TBU: transmit buffer unavailable status flag - \arg ENET_DMA_INT_FLAG_TJT: transmit jabber timeout status flag - \arg ENET_DMA_INT_FLAG_RO: receive overflow status flag - \arg ENET_DMA_INT_FLAG_TU: transmit underflow status flag - \arg ENET_DMA_INT_FLAG_RS: receive status flag - \arg ENET_DMA_INT_FLAG_RBU: receive buffer unavailable status flag - \arg ENET_DMA_INT_FLAG_RPS: receive process stopped status flag - \arg ENET_DMA_INT_FLAG_RWT: receive watchdog timeout status flag - \arg ENET_DMA_INT_FLAG_ET: early transmit status flag - \arg ENET_DMA_INT_FLAG_FBE: fatal bus error status flag - \arg ENET_DMA_INT_FLAG_ER: early receive status flag - \arg ENET_DMA_INT_FLAG_AI: abnormal interrupt summary flag - \arg ENET_DMA_INT_FLAG_NI: normal interrupt summary flag - \arg ENET_DMA_INT_FLAG_MSC: MSC status flag - \arg ENET_DMA_INT_FLAG_WUM: WUM status flag - \arg ENET_DMA_INT_FLAG_TST: timestamp trigger status flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag) -{ - if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear ENET DMA interrupt flag - \param[in] int_flag_clear: clear ENET interrupt flag, - only one parameter can be selected which is shown as below - \arg ENET_DMA_INT_FLAG_TS_CLR: transmit status flag - \arg ENET_DMA_INT_FLAG_TPS_CLR: transmit process stopped status flag - \arg ENET_DMA_INT_FLAG_TBU_CLR: transmit buffer unavailable status flag - \arg ENET_DMA_INT_FLAG_TJT_CLR: transmit jabber timeout status flag - \arg ENET_DMA_INT_FLAG_RO_CLR: receive overflow status flag - \arg ENET_DMA_INT_FLAG_TU_CLR: transmit underflow status flag - \arg ENET_DMA_INT_FLAG_RS_CLR: receive status flag - \arg ENET_DMA_INT_FLAG_RBU_CLR: receive buffer unavailable status flag - \arg ENET_DMA_INT_FLAG_RPS_CLR: receive process stopped status flag - \arg ENET_DMA_INT_FLAG_RWT_CLR: receive watchdog timeout status flag - \arg ENET_DMA_INT_FLAG_ET_CLR: early transmit status flag - \arg ENET_DMA_INT_FLAG_FBE_CLR: fatal bus error status flag - \arg ENET_DMA_INT_FLAG_ER_CLR: early receive status flag - \arg ENET_DMA_INT_FLAG_AI_CLR: abnormal interrupt summary flag - \arg ENET_DMA_INT_FLAG_NI_CLR: normal interrupt summary flag - \param[out] none - \retval none -*/ -void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear) -{ - /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ - ENET_REG_VAL(int_flag_clear) = BIT(ENET_BIT_POS(int_flag_clear)); -} - -/*! - \brief ENET Tx function enable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_tx_enable(void) -{ - ENET_MAC_CFG |= ENET_MAC_CFG_TEN; - enet_txfifo_flush(); - ENET_DMA_CTL |= ENET_DMA_CTL_STE; -} - -/*! - \brief ENET Tx function disable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_tx_disable(void) -{ - ENET_DMA_CTL &= ~ENET_DMA_CTL_STE; - enet_txfifo_flush(); - ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN; -} - -/*! - \brief ENET Rx function enable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_rx_enable(void) -{ - ENET_MAC_CFG |= ENET_MAC_CFG_REN; - ENET_DMA_CTL |= ENET_DMA_CTL_SRE; + ENET_MAC_CFG |= ENET_MAC_CFG_REN; + ENET_DMA_CTL |= ENET_DMA_CTL_SRE; } /*! @@ -1335,10 +1106,10 @@ void enet_rx_disable(void) } /*! - \brief put registers value into the application buffer + \brief put registers value into the application buffer \param[in] type: register type which will be get, refer to enet_registers_type_enum, only one parameter can be selected which is shown as below - \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH + \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH \arg ALL_MSC_REG: get the registers within the offset scope between ENET_MSC_CTL and ENET_MSC_RGUFCNT \arg ALL_PTP_REG: get the registers within the offset scope between ENET_PTP_TSCTL and ENET_PTP_PPSCTL \arg ALL_DMA_REG: get the registers within the offset scope between ENET_DMA_BCTL and ENET_DMA_CRBADDR @@ -1349,26 +1120,26 @@ void enet_rx_disable(void) void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num) { uint32_t offset = 0U, max = 0U, limit = 0U; - + offset = (uint32_t)type; max = (uint32_t)type + num; - limit = sizeof(enet_reg_tab)/sizeof(uint16_t); - + limit = sizeof(enet_reg_tab) / sizeof(uint16_t); + /* prevent element in this array is out of range */ - if(max > limit){ + if(max > limit) { max = limit; } - - for(; offset < max; offset++){ + + for(; offset < max; offset++) { /* get value of the corresponding register */ - *preg = REG32((ENET) + enet_reg_tab[offset]); + *preg = REG32((ENET) + enet_reg_tab[offset]); preg++; } -} +} /*! - \brief enable the MAC address filter - \param[in] mac_addr: select which MAC address will be enable + \brief enable the MAC address filter + \param[in] mac_addr: select which MAC address will be enable \arg ENET_MAC_ADDRESS1: enable MAC address 1 filter \arg ENET_MAC_ADDRESS2: enable MAC address 2 filter \arg ENET_MAC_ADDRESS3: enable MAC address 3 filter @@ -1381,7 +1152,7 @@ void enet_address_filter_enable(enet_macaddress_enum mac_addr) } /*! - \brief disable the MAC address filter + \brief disable the MAC address filter \param[in] mac_addr: select which MAC address will be disable, only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS1: disable MAC address 1 filter @@ -1396,7 +1167,7 @@ void enet_address_filter_disable(enet_macaddress_enum mac_addr) } /*! - \brief configure the MAC address filter + \brief configure the MAC address filter \param[in] mac_addr: select which MAC address will be configured, only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS1: configure MAC address 1 filter @@ -1405,7 +1176,7 @@ void enet_address_filter_disable(enet_macaddress_enum mac_addr) \param[in] addr_mask: select which MAC address bytes will be mask, one or more parameters can be selected which are shown as below \arg ENET_ADDRESS_MASK_BYTE0: mask ENET_MAC_ADDR1L[7:0] bits - \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits + \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits \arg ENET_ADDRESS_MASK_BYTE2: mask ENET_MAC_ADDR1L[23:16] bits \arg ENET_ADDRESS_MASK_BYTE3: mask ENET_MAC_ADDR1L [31:24] bits \arg ENET_ADDRESS_MASK_BYTE4: mask ENET_MAC_ADDR1H [7:0] bits @@ -1420,7 +1191,7 @@ void enet_address_filter_disable(enet_macaddress_enum mac_addr) void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type) { uint32_t reg; - + /* get the address filter register value which is to be configured */ reg = REG32(ENET_ADDRH_BASE + mac_addr); @@ -1435,53 +1206,53 @@ void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mas \param[in] none \param[out] none \retval ErrStatus: SUCCESS or ERROR -*/ +*/ ErrStatus enet_phy_config(void) { uint32_t ahbclk; uint32_t reg; uint16_t phy_value; ErrStatus enet_state = ERROR; - + /* clear the previous MDC clock */ reg = ENET_MAC_PHY_CTL; reg &= ~ENET_MAC_PHY_CTL_CLR; /* get the HCLK frequency */ ahbclk = rcu_clock_freq_get(CK_AHB); - + /* configure MDC clock according to HCLK frequency range */ - if(ENET_RANGE(ahbclk, 20000000U, 35000000U)){ + if(ENET_RANGE(ahbclk, 20000000U, 35000000U)) { reg |= ENET_MDC_HCLK_DIV16; - }else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)){ + } else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)) { reg |= ENET_MDC_HCLK_DIV26; - }else if(ENET_RANGE(ahbclk, 60000000U, 100000000U)){ + } else if(ENET_RANGE(ahbclk, 60000000U, 100000000U)) { reg |= ENET_MDC_HCLK_DIV42; - }else if((ENET_RANGE(ahbclk, 100000000U, 120000000U))||(120000000U == ahbclk)){ - reg |= ENET_MDC_HCLK_DIV62; - }else{ + } else if((ENET_RANGE(ahbclk, 100000000U, 120000000U)) || (120000000U == ahbclk)) { + reg |= ENET_MDC_HCLK_DIV62; + } else { return enet_state; } ENET_MAC_PHY_CTL = reg; /* reset PHY */ phy_value = PHY_RESET; - if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ + if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))) { return enet_state; } - /* PHY reset need some time */ + /* PHY reset need some time */ _ENET_DELAY_(ENET_DELAY_TO); - + /* check whether PHY reset is complete */ - if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ + if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))) { return enet_state; } /* PHY reset complete */ - if(RESET == (phy_value & PHY_RESET)){ + if(RESET == (phy_value & PHY_RESET)) { enet_state = SUCCESS; } - + return enet_state; } @@ -1492,7 +1263,7 @@ ErrStatus enet_phy_config(void) \arg ENET_PHY_READ: read data from phy register \param[in] phy_address: 0x0 - 0x1F \param[in] phy_reg: 0x0 - 0x1F - \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction + \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction \param[out] pvalue: the value will be read from the PHY register in ENET_PHY_READ direction \retval ErrStatus: SUCCESS or ERROR */ @@ -1502,34 +1273,33 @@ ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_add uint32_t timeout = 0U; ErrStatus enet_state = ERROR; - /* configure ENET_MAC_PHY_CTL with write/read operation */ + /* configure ENET_MAC_PHY_CTL with write/read operation */ reg = ENET_MAC_PHY_CTL; reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA); - reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); + reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); /* if do the write operation, write value to the register */ - if(ENET_PHY_WRITE == direction){ - ENET_MAC_PHY_DATA = *pvalue; + if(ENET_PHY_WRITE == direction) { + ENET_MAC_PHY_DATA = *pvalue; } - + /* do PHY write/read operation, and wait the operation complete */ ENET_MAC_PHY_CTL = reg; - do{ + do { phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB); timeout++; - } - while((RESET != phy_flag) && (ENET_DELAY_TO != timeout)); + } while((RESET != phy_flag) && (ENET_DELAY_TO != timeout)); - /* write/read operation complete */ - if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)){ + /* write/read operation complete */ + if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)) { enet_state = SUCCESS; } - /* if do the read operation, get value from the register */ - if(ENET_PHY_READ == direction){ - *pvalue = (uint16_t)ENET_MAC_PHY_DATA; + /* if do the read operation, get value from the register */ + if(ENET_PHY_READ == direction) { + *pvalue = (uint16_t)ENET_MAC_PHY_DATA; } - + return enet_state; } @@ -1545,7 +1315,7 @@ ErrStatus enet_phyloopback_enable(void) ErrStatus phy_state = ERROR; /* get the PHY configuration to update it */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); /* enable the PHY loopback mode */ temp_phy |= PHY_LOOPBACK; @@ -1568,7 +1338,7 @@ ErrStatus enet_phyloopback_disable(void) ErrStatus phy_state = ERROR; /* get the PHY configuration to update it */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); /* disable the PHY loopback mode */ temp_phy &= (uint16_t)~PHY_LOOPBACK; @@ -1592,10 +1362,10 @@ ErrStatus enet_phyloopback_disable(void) void enet_forward_feature_enable(uint32_t feature) { uint32_t mask; - + mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); ENET_MAC_CFG |= mask; - + mask = (feature & (~(ENET_AUTO_PADCRC_DROP))); ENET_DMA_CTL |= (mask >> 2); } @@ -1604,24 +1374,24 @@ void enet_forward_feature_enable(uint32_t feature) \brief disable ENET forward feature \param[in] feature: the feature of ENET forward mode, one or more parameters can be selected which are shown as below - \arg ENET_AUTO_PADCRC_DROP: the automatic zero-quanta generation function - \arg ENET_FORWARD_ERRFRAMES: decoding function for the received pause frame and process it - \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: back pressure operation in the MAC(only use in half-dulex mode) + \arg ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames + \arg ENET_FORWARD_ERRFRAMES: the function that all frame received with error except runt error are forwarded to memory + \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: the function that forwarding undersized good frames \param[out] none \retval none */ void enet_forward_feature_disable(uint32_t feature) { uint32_t mask; - + mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); ENET_MAC_CFG &= ~mask; - + mask = (feature & (~(ENET_AUTO_PADCRC_DROP))); - ENET_DMA_CTL &= ~(mask >> 2); + ENET_DMA_CTL &= ~(mask >> 2U); } - -/*! + +/*! \brief enable ENET fliter feature \param[in] feature: the feature of ENET fliter mode, one or more parameters can be selected which are shown as below @@ -1666,18 +1436,18 @@ void enet_fliter_feature_disable(uint32_t feature) \param[out] none \retval ErrStatus: ERROR or SUCCESS */ -ErrStatus enet_pauseframe_generate(void) -{ - ErrStatus enet_state =ERROR; +ErrStatus enet_pauseframe_generate(void) +{ + ErrStatus enet_state = ERROR; uint32_t temp = 0U; /* in full-duplex mode, must make sure this bit is 0 before writing register */ temp = ENET_MAC_FCTL & ENET_MAC_FCTL_FLCBBKPA; - if(RESET == temp){ + if(RESET == temp) { ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA; enet_state = SUCCESS; } - return enet_state; + return enet_state; } /*! @@ -1686,7 +1456,7 @@ ErrStatus enet_pauseframe_generate(void) only one parameter can be selected which is shown as below \arg ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT: besides the unique multicast address, MAC can also use the MAC0 address to detecting pause frame - \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified + \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected \param[out] none \retval none @@ -1719,7 +1489,7 @@ void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) /*! \brief configure the threshold of the flow control(deactive and active threshold) \param[in] deactive: the threshold of the deactive flow control, this value - should always be less than active flow control value, only one + should always be less than active flow control value, only one parameter can be selected which is shown as below \arg ENET_DEACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes \arg ENET_DEACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes @@ -1742,7 +1512,7 @@ void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) */ void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active) { - ENET_MAC_FCTH = ((deactive | active) >> 8); + ENET_MAC_FCTH = ((deactive | active) >> 8U); } /*! @@ -1758,7 +1528,7 @@ void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active) */ void enet_flowcontrol_feature_enable(uint32_t feature) { - if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ + if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)) { ENET_MAC_FCTL &= ~ENET_ZERO_QUANTA_PAUSE; } feature &= ~ENET_ZERO_QUANTA_PAUSE; @@ -1778,7 +1548,7 @@ void enet_flowcontrol_feature_enable(uint32_t feature) */ void enet_flowcontrol_feature_disable(uint32_t feature) { - if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ + if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)) { ENET_MAC_FCTL |= ENET_ZERO_QUANTA_PAUSE; } feature &= ~ENET_ZERO_QUANTA_PAUSE; @@ -1787,7 +1557,7 @@ void enet_flowcontrol_feature_disable(uint32_t feature) /*! \brief get the dma transmit/receive process state - \param[in] direction: choose the direction of dma process which users want to check, + \param[in] direction: choose the direction of dma process which users want to check, refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below \arg ENET_DMA_TX: dma transmit process \arg ENET_DMA_RX: dma receive process @@ -1806,9 +1576,9 @@ uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction) } /*! - \brief poll the DMA transmission/reception enable by writing any value to the + \brief poll the DMA transmission/reception enable by writing any value to the ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception - \param[in] direction: choose the direction of DMA process which users want to resume, + \param[in] direction: choose the direction of DMA process which users want to resume, refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA transmit process \arg ENET_DMA_RX: DMA receive process @@ -1817,15 +1587,15 @@ uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction) */ void enet_dmaprocess_resume(enet_dmadirection_enum direction) { - if(ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { ENET_DMA_TPEN = 0U; - }else{ + } else { ENET_DMA_RPEN = 0U; } } /*! - \brief check and recover the Rx process + \brief check and recover the Rx process \param[in] none \param[out] none \retval none @@ -1834,15 +1604,15 @@ void enet_rxprocess_check_recovery(void) { uint32_t status; - /* get DAV information of current RxDMA descriptor */ + /* get DAV information of current RxDMA descriptor */ status = dma_current_rxdesc->status; status &= ENET_RDES0_DAV; - - /* if current descriptor is owned by DMA, but the descriptor address mismatches with + + /* if current descriptor is owned by DMA, but the descriptor address mismatches with receive descriptor address pointer updated by RxDMA controller */ if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) && - (ENET_RDES0_DAV == status)){ - dma_current_rxdesc = (enet_descriptors_struct*)ENET_DMA_CRDADDR; + (ENET_RDES0_DAV == status)) { + dma_current_rxdesc = (enet_descriptors_struct *)ENET_DMA_CRDADDR; } } @@ -1857,19 +1627,19 @@ ErrStatus enet_txfifo_flush(void) uint32_t flush_state; uint32_t timeout = 0U; ErrStatus enet_state = ERROR; - + /* set the FTF bit for flushing transmit FIFO */ - ENET_DMA_CTL |= ENET_DMA_CTL_FTF; + ENET_DMA_CTL |= ENET_DMA_CTL_FTF; /* wait until the flush operation completes */ - do{ - flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; + do { + flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; timeout++; - }while((RESET != flush_state) && (timeout < ENET_DELAY_TO)); + } while((RESET != flush_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ - if(RESET == flush_state){ + if(RESET == flush_state) { enet_state = SUCCESS; } - + return enet_state; } @@ -1885,14 +1655,14 @@ ErrStatus enet_txfifo_flush(void) \arg ENET_TX_CURRENT_DESC: the start descriptor address of the current transmit descriptor read by the TxDMA controller \arg ENET_TX_CURRENT_BUFFER: the current transmit buffer address being read by the TxDMA controller - \param[out] none + \param[out] none \retval address value */ uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get) { uint32_t reval = 0U; - reval = REG32((ENET) +(uint32_t)addr_get); + reval = REG32((ENET) + (uint32_t)addr_get); return reval; } @@ -1914,30 +1684,30 @@ uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate { uint32_t reval = 0xFFFFFFFFU; - switch(info_get){ + switch(info_get) { case RXDESC_BUFFER_1_SIZE: reval = GET_RDES1_RB1S(desc->control_buffer_size); break; case RXDESC_BUFFER_2_SIZE: reval = GET_RDES1_RB2S(desc->control_buffer_size); - break; - case RXDESC_FRAME_LENGTH: + break; + case RXDESC_FRAME_LENGTH: reval = GET_RDES0_FRML(desc->status); - if(reval > 4U){ + if(reval > 4U) { reval = reval - 4U; - }else{ + } else { reval = 0U; } break; - case RXDESC_BUFFER_1_ADDR: - reval = desc->buffer1_addr; + case RXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; break; - case TXDESC_BUFFER_1_ADDR: - reval = desc->buffer1_addr; + case TXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; break; - case TXDESC_COLLISION_COUNT: + case TXDESC_COLLISION_COUNT: reval = GET_TDES0_COCNT(desc->status); - break; + break; default: break; } @@ -1954,7 +1724,7 @@ uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) { uint32_t temp_counter = 0U; - + temp_counter = ENET_DMA_MFBOCNT; *rxfifo_drop = GET_DMA_MFBOCNT_MSFA(temp_counter); *rxdma_drop = GET_DMA_MFBOCNT_MSFC(temp_counter); @@ -1965,7 +1735,7 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) \param[in] desc: the descriptor pointer which users want to get flag \param[in] desc_flag: the bit flag of ENET DMA descriptor, only one parameter can be selected which is shown as below - \arg ENET_TDES0_DB: deferred + \arg ENET_TDES0_DB: deferred \arg ENET_TDES0_UFE: underflow error \arg ENET_TDES0_EXD: excessive deferral \arg ENET_TDES0_VFRM: VLAN frame @@ -1978,18 +1748,18 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) \arg ENET_TDES0_JT: jabber timeout \arg ENET_TDES0_ES: error summary \arg ENET_TDES0_IPHE: IP header error - \arg ENET_TDES0_TTMSS: transmit timestamp status + \arg ENET_TDES0_TTMSS: transmit timestamp status \arg ENET_TDES0_TCHM: the second address chained mode \arg ENET_TDES0_TERM: transmit end of ring mode \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DPAD: disable adding pad \arg ENET_TDES0_DCRC: disable CRC \arg ENET_TDES0_FSG: first segment \arg ENET_TDES0_LSG: last segment \arg ENET_TDES0_INTC: interrupt on completion \arg ENET_TDES0_DAV: DAV bit - - \arg ENET_RDES0_PCERR: payload checksum error + + \arg ENET_RDES0_PCERR: payload checksum error \arg ENET_RDES0_CERR: CRC error \arg ENET_RDES0_DBERR: dribble bit error \arg ENET_RDES0_RERR: receive error @@ -2000,11 +1770,11 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) \arg ENET_RDES0_LDES: last descriptor \arg ENET_RDES0_FDES: first descriptor \arg ENET_RDES0_VTAG: VLAN tag - \arg ENET_RDES0_OERR: overflow error + \arg ENET_RDES0_OERR: overflow error \arg ENET_RDES0_LERR: length error \arg ENET_RDES0_SAFF: SA filter fail \arg ENET_RDES0_DERR: descriptor error - \arg ENET_RDES0_ERRS: error summary + \arg ENET_RDES0_ERRS: error summary \arg ENET_RDES0_DAFF: destination address filter fail \arg ENET_RDES0_DAV: descriptor available \param[out] none @@ -2013,8 +1783,8 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) { FlagStatus enet_flag = RESET; - - if ((uint32_t)RESET != (desc->status & desc_flag)){ + + if((uint32_t)RESET != (desc->status & desc_flag)) { enet_flag = SET; } @@ -2031,13 +1801,13 @@ FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) \arg ENET_TDES0_TCHM: the second address chained mode \arg ENET_TDES0_TERM: transmit end of ring mode \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DPAD: disable adding pad \arg ENET_TDES0_DCRC: disable CRC \arg ENET_TDES0_FSG: first segment \arg ENET_TDES0_LSG: last segment \arg ENET_TDES0_INTC: interrupt on completion \arg ENET_TDES0_DAV: DAV bit - \arg ENET_RDES0_DAV: descriptor available + \arg ENET_RDES0_DAV: descriptor available \param[out] none \retval none */ @@ -2056,13 +1826,13 @@ void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag) \arg ENET_TDES0_TCHM: the second address chained mode \arg ENET_TDES0_TERM: transmit end of ring mode \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DPAD: disable adding pad \arg ENET_TDES0_DCRC: disable CRC \arg ENET_TDES0_FSG: first segment \arg ENET_TDES0_LSG: last segment \arg ENET_TDES0_INTC: interrupt on completion \arg ENET_TDES0_DAV: DAV bit - \arg ENET_RDES0_DAV: descriptor available + \arg ENET_RDES0_DAV: descriptor available \param[out] none \retval none */ @@ -2072,7 +1842,7 @@ void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag) } /*! - \brief when receiving completed, set RS bit in ENET_DMA_STAT register will set + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will set \param[in] desc: the descriptor pointer which users want to configure \param[out] none \retval none @@ -2083,7 +1853,7 @@ void enet_desc_receive_complete_bit_enable(enet_descriptors_struct *desc) } /*! - \brief when receiving completed, set RS bit in ENET_DMA_STAT register will not set + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will not set \param[in] desc: the descriptor pointer which users want to configure \param[out] none \retval none @@ -2102,36 +1872,36 @@ void enet_desc_receive_complete_bit_disable(enet_descriptors_struct *desc) void enet_rxframe_drop(void) { /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - + dma_current_rxdesc->status = ENET_RDES0_DAV; + /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - if(NULL != dma_current_ptp_rxdesc){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + if(NULL != dma_current_ptp_rxdesc) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->buffer2_next_desc_addr); /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_rxdesc->status){ + if(0U != dma_current_ptp_rxdesc->status) { /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ - /* ponter to the next ptp descriptor */ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { + /* pointer to the next ptp descriptor */ dma_current_ptp_rxdesc++; } - }else{ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); + } else { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_rxdesc->buffer2_next_desc_addr); } - - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - if(NULL != dma_current_ptp_rxdesc){ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + if(NULL != dma_current_ptp_rxdesc) { + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); } - }else{ + } else { /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - if(NULL != dma_current_ptp_rxdesc){ + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + if(NULL != dma_current_ptp_rxdesc) { dma_current_ptp_rxdesc++; } } @@ -2149,7 +1919,7 @@ void enet_rxframe_drop(void) */ void enet_dma_feature_enable(uint32_t feature) { - ENET_DMA_CTL |= feature; + ENET_DMA_CTL |= feature; } /*! @@ -2182,67 +1952,67 @@ void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, en uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc, *desc_tab; uint8_t *buf; - + /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - + maxsize = ENET_TXBUF_SIZE; + /* select chain mode, and enable transmit timestamp function */ desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; - + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; dma_current_ptp_txdesc = desc_ptptab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - + maxsize = ENET_RXBUF_SIZE; + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* select receive chained mode and set buffer1 size */ desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; dma_current_rxdesc = desc_tab; - dma_current_ptp_rxdesc = desc_ptptab; + dma_current_ptp_rxdesc = desc_ptptab; } - - /* configure each descriptor */ - for(num = 0U; num < count; num++){ + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; + desc->status = desc_status; desc->control_buffer_size = desc_bufsize; desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + /* if is not the last descriptor */ - if(num < (count - 1U)){ + if(num < (count - 1U)) { /* configure the next descriptor address */ desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t)desc_tab; + } else { + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t)desc_tab; } /* set desc_ptptab equal to desc_tab */ (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; - } - /* when it is the last ptp descriptor, preserve the first descriptor + } + /* when it is the last ptp descriptor, preserve the first descriptor address of desc_ptptab in ptp descriptor status */ - (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; + (&desc_ptptab[num - 1U])->status = (uint32_t)desc_ptptab; } /*! @@ -2265,57 +2035,57 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene /* configure descriptor skip length */ ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - + /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - + maxsize = ENET_TXBUF_SIZE; + /* select ring mode, and enable transmit timestamp function */ desc_status = ENET_TDES0_TTSEN; - + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; dma_current_ptp_txdesc = desc_ptptab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - + maxsize = ENET_RXBUF_SIZE; + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* select receive ring mode and set buffer1 size */ desc_bufsize = (uint32_t)ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; dma_current_rxdesc = desc_tab; - dma_current_ptp_rxdesc = desc_ptptab; + dma_current_ptp_rxdesc = desc_ptptab; } - - /* configure each descriptor */ - for(num = 0U; num < count; num++){ + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; + desc->status = desc_status; desc->control_buffer_size = desc_bufsize; desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ + if(num == (count - 1U)) { + if(ENET_DMA_TX == direction) { + /* configure transmit end of ring mode */ desc->status |= ENET_TDES0_TERM; - }else{ + } else { /* configure receive end of ring mode */ desc->control_buffer_size |= ENET_RDES1_RERM; } @@ -2323,14 +2093,14 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene /* set desc_ptptab equal to desc_tab */ (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; - } - /* when it is the last ptp descriptor, preserve the first descriptor + } + /* when it is the last ptp descriptor, preserve the first descriptor address of desc_ptptab in ptp descriptor status */ - (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; + (&desc_ptptab[num - 1U])->status = (uint32_t)desc_ptptab; } /*! - \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode + \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode \param[in] bufsize: the size of buffer which is the parameter in function \param[out] timestamp: pointer to the table which stores the timestamp high and low \param[out] buffer: pointer to the application buffer @@ -2340,33 +2110,33 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) { uint32_t offset = 0U, size = 0U; - + /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { return ERROR; } - + /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ + if(NULL != buffer) { /* if no error occurs, and the frame uses only one descriptor */ if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ - + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))) { + /* get the frame length except CRC */ size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; - + /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ + if(size > bufsize) { return ERROR; } /* copy data from Rx buffer to application buffer */ - for(offset = 0U; offset < size; offset++){ + for(offset = 0U; offset < size; offset++) { (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset)); } - - }else{ + + } else { return ERROR; } } @@ -2376,42 +2146,42 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ; dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr; - + /* enable reception, descriptor is owned by DMA */ dma_current_rxdesc->status = ENET_RDES0_DAV; - + /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ + if((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { /* clear RBU flag */ ENET_DMA_STAT = ENET_DMA_STAT_RBU; /* resume DMA reception by writing to the RPEN register*/ ENET_DMA_RPEN = 0U; } - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ + + /* update the current RxDMA descriptor pointer to the next descriptor in RxDMA descriptor table */ /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->buffer2_next_desc_addr); /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_rxdesc->status){ + if(0U != dma_current_ptp_rxdesc->status) { /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { /* ponter to the next ptp descriptor */ dma_current_ptp_rxdesc++; } - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table, use the same table with RxDMA descriptor */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); dma_current_ptp_rxdesc ++; } } @@ -2420,7 +2190,7 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u } /*! - \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode + \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode \param[in] buffer: pointer on the application buffer note -- if the input is NULL, user should copy data in application by himself \param[in] length: the length of frame data to be transmitted @@ -2431,23 +2201,23 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) { uint32_t offset = 0U, timeout = 0U; - uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; - + uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; + /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) { return ERROR; } /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ + if(length > ENET_MAX_FRAME_SIZE) { return ERROR; } - + /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ + if(NULL != buffer) { /* copy frame data from application buffer to Tx buffer */ - for(offset = 0U; offset < length; offset++){ - (*(__IO uint8_t *) (uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + for(offset = 0U; offset < length; offset++) { + (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); } } /* set the frame length */ @@ -2456,31 +2226,31 @@ ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, u dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; /* enable the DMA transmission */ dma_current_txdesc->status |= ENET_TDES0_DAV; - + /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - - if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ + + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)) { /* clear TBU and TU flag */ ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); /* resume DMA transmission by writing to the TPEN register*/ ENET_DMA_TPEN = 0U; } - + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ - if(NULL != timestamp){ + if(NULL != timestamp) { /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ - do{ + do { tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); timeout++; - }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); - + } while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ + if(ENET_DELAY_TO == timeout) { return ERROR; - } - + } + /* clear the ENET_TDES0_TTMSS flag */ dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; /* get the timestamp value of the transmit frame */ @@ -2490,37 +2260,37 @@ ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, u dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ; dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr; - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */ + /* update the current TxDMA descriptor pointer to the next descriptor in TxDMA descriptor table */ /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->buffer2_next_desc_addr); + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)) { + dma_current_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->buffer2_next_desc_addr); /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_txdesc->status){ + if(0U != dma_current_ptp_txdesc->status) { /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); - }else{ - /* ponter to the next ptp descriptor */ + dma_current_ptp_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->status); + } else { + /* pointer to the next ptp descriptor */ dma_current_ptp_txdesc++; } - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)) { /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); + dma_current_txdesc = (enet_descriptors_struct *)(ENET_DMA_TDTADDR); /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table, use the same table with TxDMA descriptor */ - dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); - }else{ + dma_current_ptp_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->status); + } else { /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - dma_current_ptp_txdesc ++; + dma_current_txdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_ptp_txdesc ++; } } return SUCCESS; } /*! - \brief wakeup frame filter register pointer reset + \brief wakeup frame filter register pointer reset \param[in] none \param[out] none \retval none @@ -2531,7 +2301,7 @@ void enet_wum_filter_register_pointer_reset(void) } /*! - \brief set the remote wakeup frame registers + \brief set the remote wakeup frame registers \param[in] pdata: pointer to buffer data which is written to remote wakeup frame registers (8 words total) \param[out] none \retval none @@ -2539,15 +2309,15 @@ void enet_wum_filter_register_pointer_reset(void) void enet_wum_filter_config(uint32_t pdata[]) { uint32_t num = 0U; - + /* configure ENET_MAC_RWFF register */ - for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++){ + for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++) { ENET_MAC_RWFF = pdata[num]; } } /*! - \brief enable wakeup management features + \brief enable wakeup management features \param[in] feature: one or more parameters can be selected which are shown as below \arg ENET_WUM_POWER_DOWN: power down mode \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception @@ -2562,7 +2332,7 @@ void enet_wum_feature_enable(uint32_t feature) } /*! - \brief disable wakeup management features + \brief disable wakeup management features \param[in] feature: one or more parameters can be selected which are shown as below \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception @@ -2576,8 +2346,8 @@ void enet_wum_feature_disable(uint32_t feature) } /*! - \brief reset the MAC statistics counters - \param[in] none + \brief reset the MAC statistics counters + \param[in] none \param[out] none \retval none */ @@ -2603,7 +2373,7 @@ void enet_msc_feature_enable(uint32_t feature) /*! \brief disable the MAC statistics counter features - \param[in] feature: one or more parameters can be selected which are shown as below + \param[in] feature: one or more parameters can be selected which are shown as below \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover \arg ENET_MSC_RESET_ON_READ: reset on read \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze @@ -2612,11 +2382,11 @@ void enet_msc_feature_enable(uint32_t feature) */ void enet_msc_feature_disable(uint32_t feature) { - ENET_MSC_CTL &= (~feature); + ENET_MSC_CTL &= (~feature); } /*! - \brief get MAC statistics counter + \brief get MAC statistics counter \param[in] counter: MSC counters which is selected, refer to enet_msc_counter_enum, only one parameter can be selected which is shown as below \arg ENET_MSC_TX_SCCNT: MSC transmitted good frames after a single collision counter @@ -2631,14 +2401,14 @@ void enet_msc_feature_disable(uint32_t feature) uint32_t enet_msc_counters_get(enet_msc_counter_enum counter) { uint32_t reval; - + reval = REG32((ENET + (uint32_t)counter)); - + return reval; } /*! - \brief change subsecond to nanosecond + \brief change subsecond to nanosecond \param[in] subsecond: subsecond value \param[out] none \retval the nanosecond value @@ -2646,12 +2416,12 @@ uint32_t enet_msc_counters_get(enet_msc_counter_enum counter) uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond) { uint64_t val = subsecond * 1000000000Ull; - val >>= 31; + val >>= 31U; return (uint32_t)val; } /*! - \brief change nanosecond to subsecond + \brief change nanosecond to subsecond \param[in] nanosecond: nanosecond value \param[out] none \retval the subsecond value @@ -2709,54 +2479,54 @@ ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) uint32_t timeout = 0U; ErrStatus enet_state = SUCCESS; - switch(func){ - case ENET_PTP_ADDEND_UPDATE: + switch(func) { + case ENET_PTP_ADDEND_UPDATE: /* this bit must be read as zero before application set it */ - do{ - temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; + do { + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + } while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ + if(ENET_DELAY_TO == timeout) { enet_state = ERROR; - }else{ + } else { ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU; - } + } break; case ENET_PTP_SYSTIME_UPDATE: /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */ - do{ - temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); + do { + temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + } while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ + if(ENET_DELAY_TO == timeout) { enet_state = ERROR; - }else{ + } else { ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU; - } - break; + } + break; case ENET_PTP_SYSTIME_INIT: /* this bit must be read as zero before application set it */ - do{ - temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; + do { + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + } while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ + if(ENET_DELAY_TO == timeout) { enet_state = ERROR; - }else{ + } else { ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI; - } - break; + } + break; default: - temp_config = (uint32_t)func & (~BIT(31)); - if(RESET != ((uint32_t)func & BIT(31))){ - ENET_PTP_TSCTL |= temp_config; - }else{ - ENET_PTP_TSCTL &= ~temp_config; + temp_config = (uint32_t)func & (~BIT(31)); + if(RESET != ((uint32_t)func & BIT(31))) { + ENET_PTP_TSCTL |= temp_config; + } else { + ENET_PTP_TSCTL &= ~temp_config; } - break; + break; } return enet_state; @@ -2764,7 +2534,7 @@ ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) /*! \brief configure system time subsecond increment value - \param[in] subsecond: the value will be added to the subsecond value of system time, + \param[in] subsecond: the value will be added to the subsecond value of system time, this value must be between 0 and 0xFF \param[out] none \retval none @@ -2792,7 +2562,7 @@ void enet_ptp_timestamp_addend_config(uint32_t add) \arg ENET_PTP_ADD_TO_TIME: timestamp update value is added to system time \arg ENET_PTP_SUBSTRACT_FROM_TIME: timestamp update value is subtracted from system time \param[in] second: initializing or adding/subtracting to second of the system time - \param[in] subsecond: the current subsecond of the system time + \param[in] subsecond: the current subsecond of the system time with 0.46 ns accuracy if required accuracy is 20 ns \param[out] none \retval none @@ -2800,7 +2570,7 @@ void enet_ptp_timestamp_addend_config(uint32_t add) void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond) { ENET_PTP_TSUH = second; - ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond); + ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond); } /*! @@ -2819,7 +2589,7 @@ void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond) /*! \brief get the current system time \param[in] none - \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains + \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains parameters of PTP system time members of the structure and the member values are shown as below: second: 0x0 - 0xFFFF FFFF @@ -2831,11 +2601,11 @@ void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct) { uint32_t temp_sec = 0U, temp_subs = 0U; - /* get the value of sysytem time registers */ - temp_sec = (uint32_t)ENET_PTP_TSH; + /* get the value of system time registers */ + temp_sec = (uint32_t)ENET_PTP_TSH; temp_subs = (uint32_t)ENET_PTP_TSL; - - /* get sysytem time and construct the enet_ptp_systime_struct structure */ + + /* get system time and construct the enet_ptp_systime_struct structure */ systime_struct->second = temp_sec; systime_struct->nanosecond = GET_PTP_TSL_STMSS(temp_subs); systime_struct->nanosecond = enet_ptp_subsecond_2_nanosecond(systime_struct->nanosecond); @@ -2865,12 +2635,12 @@ void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subse /* configure system time subsecond increment based on the PTP clock frequency */ enet_ptp_subsecond_increment_config(accuracy_cfg); - if(ENET_PTP_FINEMODE == updatemethod){ + if(ENET_PTP_FINEMODE == updatemethod) { /* fine correction method: configure the timestamp addend, then update */ enet_ptp_timestamp_addend_config(carry_cfg); enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); /* wait until update is completed */ - while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_ADDEND_UPDATE)){ + while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_ADDEND_UPDATE)) { } } @@ -2897,7 +2667,7 @@ void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg) /*! \brief update system time in coarse method - \param[in] systime_struct: pointer to a enet_ptp_systime_struct structure which contains + \param[in] systime_struct: pointer to a enet_ptp_systime_struct structure which contains parameters of PTP system time members of the structure and the member values are shown as below: second: 0x0 - 0xFFFF FFFF @@ -2912,7 +2682,7 @@ void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_s uint32_t carry_cfg; subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond); - + /* save the carry_cfg value */ carry_cfg = ENET_PTP_TSADDEND_TMSA; @@ -2921,9 +2691,9 @@ void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_s enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_UPDATE); /* wait until the update is completed */ - while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_UPDATE)){ + while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_UPDATE)) { } - + /* write back the carry_cfg value, then update */ enet_ptp_timestamp_addend_config(carry_cfg); enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); @@ -2931,7 +2701,7 @@ void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_s /*! \brief set system time in fine method - \param[in] systime_struct: pointer to a enet_ptp_systime_struct structure which contains + \param[in] systime_struct: pointer to a enet_ptp_systime_struct structure which contains parameters of PTP system time members of the structure and the member values are shown as below: second: 0x0 - 0xFFFF FFFF @@ -2940,7 +2710,7 @@ void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_s \param[out] none \retval none */ -void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct) +void enet_ptp_finecorrection_settime(enet_ptp_systime_struct *systime_struct) { uint32_t subsecond_val; @@ -2949,15 +2719,15 @@ void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct) /* initialize the system time */ enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val); enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT); - + /* wait until the system time initialzation finished */ - while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_INIT)){ + while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_INIT)) { } } /*! \brief get the ptp flag status - \param[in] flag: ptp flag status to be checked + \param[in] flag: ptp flag status to be checked \arg ENET_PTP_ADDEND_UPDATE: addend register update \arg ENET_PTP_SYSTIME_UPDATE: timestamp update \arg ENET_PTP_SYSTIME_INIT: timestamp initialize @@ -2968,10 +2738,10 @@ FlagStatus enet_ptp_flag_get(uint32_t flag) { FlagStatus bitstatus = RESET; - if ((uint32_t)RESET != (ENET_PTP_TSCTL & flag)){ + if((uint32_t)RESET != (ENET_PTP_TSCTL & flag)) { bitstatus = SET; } - + return bitstatus; } @@ -2989,7 +2759,7 @@ void enet_initpara_reset(void) enet_initpara.dma_maxburst = 0U; enet_initpara.dma_arbitration = 0U; enet_initpara.store_forward_mode = 0U; - enet_initpara.dma_function = 0U; + enet_initpara.dma_function = 0U; enet_initpara.vlan_config = 0U; enet_initpara.flow_control = 0U; enet_initpara.hashtable_high = 0U; @@ -2998,10 +2768,10 @@ void enet_initpara_reset(void) enet_initpara.halfduplex_param = 0U; enet_initpara.timer_config = 0U; enet_initpara.interframegap = 0U; -} +} /*! - \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() + \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() \param[in] none \param[out] none \retval none @@ -3015,56 +2785,53 @@ static void enet_default_init(void) reg_value = ENET_MAC_CFG; reg_value &= MAC_CFG_MASK; reg_value |= ENET_WATCHDOG_ENABLE | ENET_JABBER_ENABLE | ENET_INTERFRAMEGAP_96BIT \ - | ENET_SPEEDMODE_10M |ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \ - | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \ - | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \ - | ENET_DEFERRALCHECK_DISABLE \ - | ENET_AUTO_PADCRC_DROP_DISABLE \ - | ENET_CHECKSUMOFFLOAD_DISABLE; + | ENET_SPEEDMODE_10M | ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \ + | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \ + | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \ + | ENET_DEFERRALCHECK_DISABLE \ + | ENET_AUTO_PADCRC_DROP_DISABLE \ + | ENET_CHECKSUMOFFLOAD_DISABLE; ENET_MAC_CFG = reg_value; - + /* configure ENET_MAC_FRMF register */ - ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE |ENET_DEST_FILTER_INVERSE_DISABLE \ - |ENET_MULTICAST_FILTER_PERFECT |ENET_UNICAST_FILTER_PERFECT \ - |ENET_PCFRM_PREVENT_ALL |ENET_BROADCASTFRAMES_ENABLE \ - |ENET_PROMISCUOUS_DISABLE |ENET_RX_FILTER_ENABLE; + ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE | ENET_DEST_FILTER_INVERSE_DISABLE \ + | ENET_MULTICAST_FILTER_PERFECT | ENET_UNICAST_FILTER_PERFECT \ + | ENET_PCFRM_PREVENT_ALL | ENET_BROADCASTFRAMES_ENABLE \ + | ENET_PROMISCUOUS_DISABLE | ENET_RX_FILTER_ENABLE; /* configure ENET_MAC_HLH, ENET_MAC_HLL register */ ENET_MAC_HLH = 0x0U; - + ENET_MAC_HLL = 0x0U; /* configure ENET_MAC_FCTL, ENET_MAC_FCTH register */ reg_value = ENET_MAC_FCTL; reg_value &= MAC_FCTL_MASK; - reg_value |= MAC_FCTL_PTM(0) |ENET_ZERO_QUANTA_PAUSE_DISABLE \ - |ENET_PAUSETIME_MINUS4 |ENET_UNIQUE_PAUSEDETECT \ - |ENET_RX_FLOWCONTROL_DISABLE |ENET_TX_FLOWCONTROL_DISABLE; - ENET_MAC_FCTL = reg_value; - - ENET_MAC_FCTH = ENET_DEACTIVE_THRESHOLD_512BYTES |ENET_ACTIVE_THRESHOLD_1536BYTES; - + reg_value |= MAC_FCTL_PTM(0) | ENET_ZERO_QUANTA_PAUSE_DISABLE \ + | ENET_PAUSETIME_MINUS4 | ENET_UNIQUE_PAUSEDETECT \ + | ENET_RX_FLOWCONTROL_DISABLE | ENET_TX_FLOWCONTROL_DISABLE; + ENET_MAC_FCTL = reg_value; + /* configure ENET_MAC_VLT register */ - ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT |MAC_VLT_VLTI(0); - + ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT | MAC_VLT_VLTI(0); + /* DMA */ /* configure ENET_DMA_CTL register */ reg_value = ENET_DMA_CTL; reg_value &= DMA_CTL_MASK; - reg_value |= ENET_TCPIP_CKSUMERROR_DROP |ENET_RX_MODE_STOREFORWARD \ - |ENET_FLUSH_RXFRAME_ENABLE |ENET_TX_MODE_STOREFORWARD \ - |ENET_TX_THRESHOLD_64BYTES |ENET_RX_THRESHOLD_64BYTES \ - |ENET_FORWARD_ERRFRAMES_DISABLE |ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE \ - |ENET_SECONDFRAME_OPT_DISABLE; - ENET_DMA_CTL = reg_value; + reg_value |= ENET_TCPIP_CKSUMERROR_DROP | ENET_RX_MODE_STOREFORWARD \ + | ENET_FLUSH_RXFRAME_ENABLE | ENET_TX_MODE_STOREFORWARD \ + | ENET_TX_THRESHOLD_64BYTES | ENET_RX_THRESHOLD_64BYTES \ + | ENET_SECONDFRAME_OPT_DISABLE; + ENET_DMA_CTL = reg_value; /* configure ENET_DMA_BCTL register */ reg_value = ENET_DMA_BCTL; reg_value &= DMA_BCTL_MASK; - reg_value = ENET_ADDRESS_ALIGN_ENABLE |ENET_ARBITRATION_RXTX_2_1 \ - |ENET_RXDP_32BEAT |ENET_PGBL_32BEAT |ENET_RXTX_DIFFERENT_PGBL \ - |ENET_FIXED_BURST_ENABLE; - ENET_DMA_BCTL = reg_value; + reg_value = ENET_ADDRESS_ALIGN_ENABLE | ENET_ARBITRATION_RXTX_2_1 \ + | ENET_RXDP_32BEAT | ENET_PGBL_32BEAT | ENET_RXTX_DIFFERENT_PGBL \ + | ENET_FIXED_BURST_ENABLE; + ENET_DMA_BCTL = reg_value; } #ifndef USE_DELAY @@ -3076,11 +2843,247 @@ static void enet_default_init(void) */ static void enet_delay(uint32_t ncount) { - __IO uint32_t delay_time = 0U; - - for(delay_time = ncount; delay_time != 0U; delay_time--){ + __IO uint32_t delay_time = 0U; + + for(delay_time = ncount; delay_time != 0U; delay_time--) { } } #endif /* USE_DELAY */ +/*! + \brief get the ENET MAC/MSC/PTP/DMA status flag + \param[in] enet_flag: ENET status flag, refer to enet_flag_enum, + only one parameter can be selected which is shown as below + \arg ENET_MAC_FLAG_MPKR: magic packet received flag + \arg ENET_MAC_FLAG_WUFR: wakeup frame received flag + \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag + \arg ENET_MAC_FLAG_WUM: WUM status flag + \arg ENET_MAC_FLAG_MSC: MSC status flag + \arg ENET_MAC_FLAG_MSCR: MSC receive status flag + \arg ENET_MAC_FLAG_MSCT: MSC transmit status flag + \arg ENET_MAC_FLAG_TMST: time stamp trigger status flag + \arg ENET_PTP_FLAG_TSSCO: timestamp second counter overflow flag + \arg ENET_PTP_FLAG_TTM: target time match flag + \arg ENET_MSC_FLAG_RFCE: received frames CRC error flag + \arg ENET_MSC_FLAG_RFAE: received frames alignment error flag + \arg ENET_MSC_FLAG_RGUF: received good unicast frames flag + \arg ENET_MSC_FLAG_TGFSC: transmitted good frames single collision flag + \arg ENET_MSC_FLAG_TGFMSC: transmitted good frames more single collision flag + \arg ENET_MSC_FLAG_TGF: transmitted good frames flag + \arg ENET_DMA_FLAG_TS: transmit status flag + \arg ENET_DMA_FLAG_TPS: transmit process stopped status flag + \arg ENET_DMA_FLAG_TBU: transmit buffer unavailable status flag + \arg ENET_DMA_FLAG_TJT: transmit jabber timeout status flag + \arg ENET_DMA_FLAG_RO: receive overflow status flag + \arg ENET_DMA_FLAG_TU: transmit underflow status flag + \arg ENET_DMA_FLAG_RS: receive status flag + \arg ENET_DMA_FLAG_RBU: receive buffer unavailable status flag + \arg ENET_DMA_FLAG_RPS: receive process stopped status flag + \arg ENET_DMA_FLAG_RWT: receive watchdog timeout status flag + \arg ENET_DMA_FLAG_ET: early transmit status flag + \arg ENET_DMA_FLAG_FBE: fatal bus error status flag + \arg ENET_DMA_FLAG_ER: early receive status flag + \arg ENET_DMA_FLAG_AI: abnormal interrupt summary flag + \arg ENET_DMA_FLAG_NI: normal interrupt summary flag + \arg ENET_DMA_FLAG_EB_DMA_ERROR: DMA error flag + \arg ENET_DMA_FLAG_EB_TRANSFER_ERROR: transfer error flag + \arg ENET_DMA_FLAG_EB_ACCESS_ERROR: access error flag + \arg ENET_DMA_FLAG_MSC: MSC status flag + \arg ENET_DMA_FLAG_WUM: WUM status flag + \arg ENET_DMA_FLAG_TST: timestamp trigger status flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_flag_get(enet_flag_enum enet_flag) +{ + if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear the ENET DMA status flag + \param[in] enet_flag: ENET DMA flag clear, refer to enet_flag_clear_enum + only one parameter can be selected which is shown as below + \arg ENET_DMA_FLAG_TS_CLR: transmit status flag clear + \arg ENET_DMA_FLAG_TPS_CLR: transmit process stopped status flag clear + \arg ENET_DMA_FLAG_TBU_CLR: transmit buffer unavailable status flag clear + \arg ENET_DMA_FLAG_TJT_CLR: transmit jabber timeout status flag clear + \arg ENET_DMA_FLAG_RO_CLR: receive overflow status flag clear + \arg ENET_DMA_FLAG_TU_CLR: transmit underflow status flag clear + \arg ENET_DMA_FLAG_RS_CLR: receive status flag clear + \arg ENET_DMA_FLAG_RBU_CLR: receive buffer unavailable status flag clear + \arg ENET_DMA_FLAG_RPS_CLR: receive process stopped status flag clear + \arg ENET_DMA_FLAG_RWT_CLR: receive watchdog timeout status flag clear + \arg ENET_DMA_FLAG_ET_CLR: early transmit status flag clear + \arg ENET_DMA_FLAG_FBE_CLR: fatal bus error status flag clear + \arg ENET_DMA_FLAG_ER_CLR: early receive status flag clear + \arg ENET_DMA_FLAG_AI_CLR: abnormal interrupt summary flag clear + \arg ENET_DMA_FLAG_NI_CLR: normal interrupt summary flag clear + \param[out] none + \retval none +*/ +void enet_flag_clear(enet_flag_clear_enum enet_flag) +{ + /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ + ENET_REG_VAL(enet_flag) = BIT(ENET_BIT_POS(enet_flag)); +} + +/*! + \brief enable ENET MAC/MSC/DMA interrupt + \param[in] enet_int: ENET interrupt, + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_WUMIM: WUM interrupt mask + \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask + \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask + \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask + \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask + \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask + \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask + \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask + \arg ENET_DMA_INT_TIE: transmit interrupt enable + \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable + \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable + \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable + \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable + \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable + \arg ENET_DMA_INT_RIE: receive interrupt enable + \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable + \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable + \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable + \arg ENET_DMA_INT_ETIE: early transmit interrupt enable + \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable + \arg ENET_DMA_INT_ERIE: early receive interrupt enable + \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable + \arg ENET_DMA_INT_NIE: normal interrupt summary enable + \param[out] none + \retval none +*/ +void enet_interrupt_enable(enet_int_enum enet_int) +{ + if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6U)) { + /* ENET_DMA_INTEN register interrupt */ + ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); + } else { + /* other INTMSK register interrupt */ + ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); + } +} + +/*! + \brief disable ENET MAC/MSC/DMA interrupt + \param[in] enet_int: ENET interrupt, + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_WUMIM: WUM interrupt mask + \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask + \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask + \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask + \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask + \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask + \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask + \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask + \arg ENET_DMA_INT_TIE: transmit interrupt enable + \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable + \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable + \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable + \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable + \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable + \arg ENET_DMA_INT_RIE: receive interrupt enable + \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable + \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable + \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable + \arg ENET_DMA_INT_ETIE: early transmit interrupt enable + \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable + \arg ENET_DMA_INT_ERIE: early receive interrupt enable + \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable + \arg ENET_DMA_INT_NIE: normal interrupt summary enable + \param[out] none + \retval none +*/ +void enet_interrupt_disable(enet_int_enum enet_int) +{ + if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6U)) { + /* ENET_DMA_INTEN register interrupt */ + ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); + } else { + /* other INTMSK register interrupt */ + ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); + } +} + +/*! + \brief get ENET MAC/MSC/DMA interrupt flag + \param[in] int_flag: ENET interrupt flag, + only one parameter can be selected which is shown as below + \arg ENET_MAC_INT_FLAG_WUM: WUM status flag + \arg ENET_MAC_INT_FLAG_MSC: MSC status flag + \arg ENET_MAC_INT_FLAG_MSCR: MSC receive status flag + \arg ENET_MAC_INT_FLAG_MSCT: MSC transmit status flag + \arg ENET_MAC_INT_FLAG_TMST: time stamp trigger status flag + \arg ENET_MSC_INT_FLAG_RFCE: received frames CRC error flag + \arg ENET_MSC_INT_FLAG_RFAE: received frames alignment error flag + \arg ENET_MSC_INT_FLAG_RGUF: received good unicast frames flag + \arg ENET_MSC_INT_FLAG_TGFSC: transmitted good frames single collision flag + \arg ENET_MSC_INT_FLAG_TGFMSC: transmitted good frames more single collision flag + \arg ENET_MSC_INT_FLAG_TGF: transmitted good frames flag + \arg ENET_DMA_INT_FLAG_TS: transmit status flag + \arg ENET_DMA_INT_FLAG_TPS: transmit process stopped status flag + \arg ENET_DMA_INT_FLAG_TBU: transmit buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_TJT: transmit jabber timeout status flag + \arg ENET_DMA_INT_FLAG_RO: receive overflow status flag + \arg ENET_DMA_INT_FLAG_TU: transmit underflow status flag + \arg ENET_DMA_INT_FLAG_RS: receive status flag + \arg ENET_DMA_INT_FLAG_RBU: receive buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_RPS: receive process stopped status flag + \arg ENET_DMA_INT_FLAG_RWT: receive watchdog timeout status flag + \arg ENET_DMA_INT_FLAG_ET: early transmit status flag + \arg ENET_DMA_INT_FLAG_FBE: fatal bus error status flag + \arg ENET_DMA_INT_FLAG_ER: early receive status flag + \arg ENET_DMA_INT_FLAG_AI: abnormal interrupt summary flag + \arg ENET_DMA_INT_FLAG_NI: normal interrupt summary flag + \arg ENET_DMA_INT_FLAG_MSC: MSC status flag + \arg ENET_DMA_INT_FLAG_WUM: WUM status flag + \arg ENET_DMA_INT_FLAG_TST: timestamp trigger status flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag) +{ + if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear ENET DMA interrupt flag + \param[in] int_flag_clear: clear ENET interrupt flag, + only one parameter can be selected which is shown as below + \arg ENET_DMA_INT_FLAG_TS_CLR: transmit status flag + \arg ENET_DMA_INT_FLAG_TPS_CLR: transmit process stopped status flag + \arg ENET_DMA_INT_FLAG_TBU_CLR: transmit buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_TJT_CLR: transmit jabber timeout status flag + \arg ENET_DMA_INT_FLAG_RO_CLR: receive overflow status flag + \arg ENET_DMA_INT_FLAG_TU_CLR: transmit underflow status flag + \arg ENET_DMA_INT_FLAG_RS_CLR: receive status flag + \arg ENET_DMA_INT_FLAG_RBU_CLR: receive buffer unavailable status flag + \arg ENET_DMA_INT_FLAG_RPS_CLR: receive process stopped status flag + \arg ENET_DMA_INT_FLAG_RWT_CLR: receive watchdog timeout status flag + \arg ENET_DMA_INT_FLAG_ET_CLR: early transmit status flag + \arg ENET_DMA_INT_FLAG_FBE_CLR: fatal bus error status flag + \arg ENET_DMA_INT_FLAG_ER_CLR: early receive status flag + \arg ENET_DMA_INT_FLAG_AI_CLR: abnormal interrupt summary flag + \arg ENET_DMA_INT_FLAG_NI_CLR: normal interrupt summary flag + \param[out] none + \retval none +*/ +void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear) +{ + /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ + ENET_REG_VAL(int_flag_clear) = BIT(ENET_BIT_POS(int_flag_clear)); +} + #endif /* GD32F20X_CL */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_exmc.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_exmc.c index ce34be58..7634a973 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_exmc.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_exmc.c @@ -2,36 +2,33 @@ \file gd32f20x_exmc.c \brief EXMC driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -127,6 +124,7 @@ OF SUCH DAMAGE. /*! \brief deinitialize EXMC NOR/SRAM region \param[in] exmc_norsram_region: select the region of bank0 + only one parameter can be selected which is shown as below: \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) \param[out] none \retval none @@ -140,14 +138,14 @@ void exmc_norsram_deinit(uint32_t exmc_norsram_region) } /*! - \brief initialize the struct exmc_norsram_parameter_struct + \brief initialize exmc_norsram_parameter_struct with the default values \param[in] none \param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer \retval none */ -void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) +void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) { - /* configure the structure with default value */ + /* configure the structure with default values */ exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0; exmc_norsram_init_struct->address_data_mux = ENABLE; exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM; @@ -162,7 +160,7 @@ void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_i exmc_norsram_init_struct->asyn_wait = DISABLE; exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE; - /* read/write timing configure */ + /* configure read/write timing */ exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; @@ -171,7 +169,7 @@ void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_i exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; - /* write timing configure, when extended mode is used */ + /* configure write timing, when extended mode is used */ exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; @@ -184,7 +182,7 @@ void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_i \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0..3 write_mode: EXMC_ASYN_WRITE or EXMC_SYN_WRITE - extended_mode: ENABLE or DISABLE + extended_mode: ENABLE or DISABLE asyn_wait: ENABLE or DISABLE nwait_signal: ENABLE or DISABLE memory_write: ENABLE or DISABLE @@ -198,68 +196,70 @@ void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_i read_write_timing: struct exmc_norsram_timing_parameter_struct set the time asyn_access_mode: EXMC_ACCESS_MODE_A, EXMC_ACCESS_MODE_B, EXMC_ACCESS_MODE_C, EXMC_ACCESS_MODE_D syn_data_latency: EXMC_DATALAT_x_CLK, x=2..17 - syn_clk_division: EXMC_SYN_CLOCK_RATIO_x_CLK, x=2..16 - bus_latency: 0x01U~0x10U + syn_clk_division: EXMC_SYN_CLOCK_RATIO_DISABLE, EXMC_SYN_CLOCK_RATIO_x_CLK, x=2..16 + bus_latency: 0x01U~0x10U asyn_data_setuptime: 0x02U~0x100U asyn_address_holdtime: 0x02U~0x10U asyn_address_setuptime: 0x01U~0x10U write_timing: struct exmc_norsram_timing_parameter_struct set the time asyn_access_mode: EXMC_ACCESS_MODE_A, EXMC_ACCESS_MODE_B, EXMC_ACCESS_MODE_C, EXMC_ACCESS_MODE_D syn_data_latency: EXMC_DATALAT_x_CLK, x=2..17 - syn_clk_division: EXMC_SYN_CLOCK_RATIO_x_CLK, x=2..16 - bus_latency: 0x01U~0x10U + syn_clk_division: EXMC_SYN_CLOCK_RATIO_DISABLE, EXMC_SYN_CLOCK_RATIO_x_CLK, x=2..16 + bus_latency: 0x01U~0x10U asyn_data_setuptime: 0x02U~0x100U asyn_address_holdtime: 0x02U~0x10U asyn_address_setuptime: 0x01U~0x10U \param[out] none \retval none */ -void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) +void exmc_norsram_init(exmc_norsram_parameter_struct *exmc_norsram_init_struct) { uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U, snwtcfg = 0x00000000U; - + /* get the register value */ snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); /* clear relative bits */ - snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | - EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WREN | - EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_SYNCWR | - EXMC_SNCTL_NRMUX )); + snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | + EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WREN | + EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_SYNCWR | + EXMC_SNCTL_NRMUX)); + /* configure control bits */ snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | - exmc_norsram_init_struct->memory_type | - exmc_norsram_init_struct->databus_width | - (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | - exmc_norsram_init_struct->nwait_polarity | - (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | - exmc_norsram_init_struct->nwait_config | - (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | - (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | - (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | - (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | - exmc_norsram_init_struct->write_mode; - + exmc_norsram_init_struct->memory_type | + exmc_norsram_init_struct->databus_width | + (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | + exmc_norsram_init_struct->nwait_polarity | + (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | + exmc_norsram_init_struct->nwait_config | + (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | + (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | + (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | + (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | + exmc_norsram_init_struct->write_mode; + + /* configure timing */ sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U) & EXMC_SNTCFG_ASET) | - (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U) << SNTCFG_AHLD_OFFSET) & EXMC_SNTCFG_AHLD) | - (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U) << SNTCFG_DSET_OFFSET) & EXMC_SNTCFG_DSET) | - (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U) << SNTCFG_BUSLAT_OFFSET) & EXMC_SNTCFG_BUSLAT) | - exmc_norsram_init_struct->read_write_timing->syn_clk_division | - exmc_norsram_init_struct->read_write_timing->syn_data_latency | - exmc_norsram_init_struct->read_write_timing->asyn_access_mode; - - /* nor flash access enable */ - if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){ + (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U) << SNTCFG_AHLD_OFFSET) & EXMC_SNTCFG_AHLD) | + (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U) << SNTCFG_DSET_OFFSET) & EXMC_SNTCFG_DSET) | + (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U) << SNTCFG_BUSLAT_OFFSET) & EXMC_SNTCFG_BUSLAT) | + exmc_norsram_init_struct->read_write_timing->syn_clk_division | + exmc_norsram_init_struct->read_write_timing->syn_data_latency | + exmc_norsram_init_struct->read_write_timing->asyn_access_mode; + + /* enable nor flash access */ + if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type) { snctl |= (uint32_t)EXMC_SNCTL_NREN; } - /* extended mode configure */ - if(ENABLE == exmc_norsram_init_struct->extended_mode){ + /* configure extended mode */ + if(ENABLE == exmc_norsram_init_struct->extended_mode) { snwtcfg = (uint32_t)(((exmc_norsram_init_struct->write_timing->asyn_address_setuptime - 1U) & EXMC_SNWTCFG_WASET) | - (((exmc_norsram_init_struct->write_timing->asyn_address_holdtime - 1U) << SNTCFG_AHLD_OFFSET ) & EXMC_SNWTCFG_WAHLD)| + (((exmc_norsram_init_struct->write_timing->asyn_address_holdtime - 1U) << SNTCFG_AHLD_OFFSET) & EXMC_SNWTCFG_WAHLD) | (((exmc_norsram_init_struct->write_timing->asyn_data_setuptime - 1U) << SNTCFG_DSET_OFFSET) & EXMC_SNWTCFG_WDSET) | - exmc_norsram_init_struct->write_timing->asyn_access_mode); - }else{ + exmc_norsram_init_struct->write_timing->asyn_access_mode); + } else { snwtcfg = BANK0_SNWTCFG_RESET; } @@ -271,7 +271,8 @@ void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) /*! \brief enable EXMC NOR/PSRAM bank region - \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM bank + \param[in] exmc_norsram_region: specify the region of NOR/PSRAM bank + only one parameter can be selected which is shown as below: \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) \param[out] none \retval none @@ -283,7 +284,8 @@ void exmc_norsram_enable(uint32_t exmc_norsram_region) /*! \brief disable EXMC NOR/PSRAM bank region - \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM Bank + \param[in] exmc_norsram_region: specify the region of NOR/PSRAM Bank + only one parameter can be selected which is shown as below: \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) \param[out] none \retval none @@ -296,7 +298,8 @@ void exmc_norsram_disable(uint32_t exmc_norsram_region) /*! \brief deinitialize EXMC NAND bank \param[in] exmc_nand_bank: select the bank of NAND - \arg EXMC_BANKx_NAND(x=1..2) + only one parameter can be selected which is shown as below: + \arg EXMC_BANKx_NAND(x=1, 2) \param[out] none \retval none */ @@ -310,14 +313,14 @@ void exmc_nand_deinit(uint32_t exmc_nand_bank) } /*! - \brief initialize the struct exmc_nand_init_struct + \brief initialize exmc_nand_parameter_struct with the default values \param[in] none - \param[out] the initialized struct exmc_nand_init_struct pointer + \param[out] the initialized struct exmc_nand_parameter_struct pointer \retval none */ -void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct) +void exmc_nand_struct_para_init(exmc_nand_parameter_struct *exmc_nand_init_struct) { - /* configure the structure with default value */ + /* configure the structure with default values */ exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND; exmc_nand_init_struct->wait_feature = DISABLE; exmc_nand_init_struct->databus_width = EXMC_NAND_DATABUS_WIDTH_8B; @@ -358,29 +361,29 @@ void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struc \param[out] none \retval none */ -void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct) +void exmc_nand_init(exmc_nand_parameter_struct *exmc_nand_init_struct) { uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U; - - npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET)| - EXMC_NPCTL_NDTP | - exmc_nand_init_struct->databus_width | - (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET)| - exmc_nand_init_struct->ecc_size | - exmc_nand_init_struct->ctr_latency | - exmc_nand_init_struct->atr_latency; - - npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) | - (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | - ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | - (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); - - npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | - (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | - ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) | - (((exmc_nand_init_struct->attribute_space_timing->databus_hiztime - 1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ ); - - /* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */ + + npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | + EXMC_NPCTL_NDTP | + exmc_nand_init_struct->databus_width | + (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET) | + exmc_nand_init_struct->ecc_size | + exmc_nand_init_struct->ctr_latency | + exmc_nand_init_struct->atr_latency; + + npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET) | + (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT) | + ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD) | + (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ); + + npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET) | + (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT) | + ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD) | + (((exmc_nand_init_struct->attribute_space_timing->databus_hiztime - 1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ); + + /* initialize EXMC_BANK1_NAND or EXMC_BANK2_NAND */ EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl; EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg; EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg; @@ -388,7 +391,8 @@ void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct) /*! \brief enable NAND bank - \param[in] exmc_nand_bank: specifie the NAND bank + \param[in] exmc_nand_bank: specify the NAND bank + only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1,2) \param[out] none \retval none @@ -400,7 +404,8 @@ void exmc_nand_enable(uint32_t exmc_nand_bank) /*! \brief disable NAND bank - \param[in] exmc_nand_bank: specifie the NAND bank + \param[in] exmc_nand_bank: specify the NAND bank + only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1,2) \param[out] none \retval none @@ -412,7 +417,8 @@ void exmc_nand_disable(uint32_t exmc_nand_bank) /*! \brief enable or disable the EXMC NAND ECC function - \param[in] exmc_nand_bank: specifie the NAND bank + \param[in] exmc_nand_bank: specify the NAND bank + only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1,2) \param[in] newvalue: ENABLE or DISABLE \param[out] none @@ -420,10 +426,10 @@ void exmc_nand_disable(uint32_t exmc_nand_bank) */ void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue) { - if (ENABLE == newvalue){ + if(ENABLE == newvalue) { /* enable the selected NAND bank ECC function */ EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_ECCEN; - }else{ + } else { /* disable the selected NAND bank ECC function */ EXMC_NPCTL(exmc_nand_bank) &= ~EXMC_NPCTL_ECCEN; } @@ -431,7 +437,8 @@ void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue) /*! \brief get the EXMC ECC value - \param[in] exmc_nand_bank: specifie the NAND bank + \param[in] exmc_nand_bank: specify the NAND bank + only one parameter can be selected which is shown as below: \arg EXMC_BANKx_NAND(x=1,2) \param[out] none \retval the error correction code(ECC) value @@ -457,6 +464,32 @@ void exmc_pccard_deinit(void) EXMC_PIOTCFG3 = BANK3_PIOTCFG3_RESET; } +/*! + \brief initialize exmc_pccard_parameter_struct with the default values + \param[in] none + \param[out] the initialized struct exmc_pccard_parameter_struct pointer + \retval none +*/ +void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct) +{ + /* configure the structure with default value */ + exmc_pccard_init_struct->wait_feature = DISABLE; + exmc_pccard_init_struct->ctr_latency = 0x0U; + exmc_pccard_init_struct->atr_latency = 0x0U; + exmc_pccard_init_struct->common_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->common_space_timing->databus_hiztime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->setuptime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->waittime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->holdtime = 0xFCU; + exmc_pccard_init_struct->io_space_timing->databus_hiztime = 0xFCU; +} + /*! \brief initialize EXMC PC card bank \param[in] exmc_pccard_parameter_struct: configure the EXMC NAND parameter @@ -481,61 +514,35 @@ void exmc_pccard_deinit(void) \param[out] none \retval none */ -void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) +void exmc_pccard_init(exmc_pccard_parameter_struct *exmc_pccard_init_struct) { /* configure the EXMC bank3 PC card control register */ EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | - EXMC_NAND_DATABUS_WIDTH_16B | - exmc_pccard_init_struct->ctr_latency | - exmc_pccard_init_struct->atr_latency ; - + EXMC_NAND_DATABUS_WIDTH_16B | + exmc_pccard_init_struct->ctr_latency | + exmc_pccard_init_struct->atr_latency ; + /* configure the EXMC bank3 PC card common space timing configuration register */ - EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) | - (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | - ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | - (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); + EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET) | + (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT) | + ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD) | + (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ); /* configure the EXMC bank3 PC card attribute space timing configuration register */ - EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | - (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | - ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) | - (((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime - 1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ); + EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET) | + (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT) | + ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD) | + (((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime - 1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ); /* configure the EXMC bank3 PC card io space timing configuration register */ - EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET ) | - (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT ) | - ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD ) | - ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ ); + EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET) | + (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT) | + ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD) | + ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ); } /*! - \brief initialize the struct exmc_pccard_parameter_struct - \param[in] none - \param[out] the initialized struct exmc_pccard_parameter_struct pointer - \retval none -*/ -void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) -{ - /* configure the structure with default value */ - exmc_pccard_init_struct->wait_feature = DISABLE; - exmc_pccard_init_struct->ctr_latency = 0x0U; - exmc_pccard_init_struct->atr_latency = 0x0U; - exmc_pccard_init_struct->common_space_timing->setuptime = 0xFCU; - exmc_pccard_init_struct->common_space_timing->waittime = 0xFCU; - exmc_pccard_init_struct->common_space_timing->holdtime = 0xFCU; - exmc_pccard_init_struct->common_space_timing->databus_hiztime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->setuptime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->waittime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->holdtime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->setuptime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->waittime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->holdtime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->databus_hiztime = 0xFCU; -} - -/*! - \brief enable PC Card Bank + \brief enable PC card bank \param[in] none \param[out] none \retval none @@ -546,19 +553,21 @@ void exmc_pccard_enable(void) } /*! - \brief disable PC Card Bank + \brief disable PC card bank \param[in] none \param[out] none \retval none */ void exmc_pccard_disable(void) { - EXMC_NPCTL3 &= ~EXMC_NPCTL_NDBKEN; + EXMC_NPCTL3 &= ~EXMC_NPCTL_NDBKEN; } /*! \brief deinitialize EXMC SDRAM device - \param[in] exmc_sdram_device: + \param[in] exmc_sdram_device: select the SDRAM device + only one parameter can be selected which is shown as below: + \arg EXMC_SDRAM_DEVICEx(x=0, 1) \param[out] none \retval none */ @@ -572,6 +581,35 @@ void exmc_sdram_deinit(uint32_t exmc_sdram_device) EXMC_SDRSCTL = SDRAM_DEVICE_SDRSCTL_RESET; } +/*! + \brief initialize exmc_sdram_init_struct with the default values + \param[in] none + \param[out] the initialized struct exmc_sdram_parameter_struct pointer + \retval none +*/ +void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct *exmc_sdram_init_struct) +{ + /* configure the structure with default value */ + exmc_sdram_init_struct->sdram_device = EXMC_SDRAM_DEVICE0; + exmc_sdram_init_struct->column_address_width = EXMC_SDRAM_COW_ADDRESS_8; + exmc_sdram_init_struct->row_address_width = EXMC_SDRAM_ROW_ADDRESS_11; + exmc_sdram_init_struct->data_width = EXMC_SDRAM_DATABUS_WIDTH_16B; + exmc_sdram_init_struct->internal_bank_number = EXMC_SDRAM_4_INTER_BANK; + exmc_sdram_init_struct->cas_latency = EXMC_CAS_LATENCY_1_SDCLK; + exmc_sdram_init_struct->write_protection = ENABLE; + exmc_sdram_init_struct->sdclock_config = EXMC_SDCLK_DISABLE; + exmc_sdram_init_struct->burst_read_switch = DISABLE; + exmc_sdram_init_struct->pipeline_read_delay = EXMC_PIPELINE_DELAY_0_HCLK; + + exmc_sdram_init_struct->timing->load_mode_register_delay = 16U; + exmc_sdram_init_struct->timing->exit_selfrefresh_delay = 16U; + exmc_sdram_init_struct->timing->row_address_select_delay = 16U; + exmc_sdram_init_struct->timing->auto_refresh_delay = 16U; + exmc_sdram_init_struct->timing->write_recovery_delay = 16U; + exmc_sdram_init_struct->timing->row_precharge_delay = 16U; + exmc_sdram_init_struct->timing->row_to_column_delay = 16U; +} + /*! \brief initialize EXMC SDRAM device \param[in] exmc_sdram_parameter_struct: configure the EXMC SDRAM parameter @@ -596,62 +634,62 @@ void exmc_sdram_deinit(uint32_t exmc_sdram_device) \param[out] none \retval none */ -void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) +void exmc_sdram_init(exmc_sdram_parameter_struct *exmc_sdram_init_struct) { uint32_t sdctl0, sdctl1, sdtcfg0, sdtcfg1; - /* configuration EXMC_SDCTL0 or EXMC_SDCTL1 */ - if(EXMC_SDRAM_DEVICE0 == exmc_sdram_init_struct->sdram_device){ - /* configuration EXMC_SDCTL0 */ - EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = (uint32_t)exmc_sdram_init_struct->column_address_width | - exmc_sdram_init_struct->row_address_width | - exmc_sdram_init_struct->data_width | - exmc_sdram_init_struct->internal_bank_number | - exmc_sdram_init_struct->cas_latency | - (exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET)| - exmc_sdram_init_struct->sdclock_config | - (exmc_sdram_init_struct->brust_read_switch << SDCTL_BRSTRD_OFFSET)| - exmc_sdram_init_struct->pipeline_read_delay; + /* configure EXMC_SDCTL0 or EXMC_SDCTL1 */ + if(EXMC_SDRAM_DEVICE0 == exmc_sdram_init_struct->sdram_device) { + /* configure EXMC_SDCTL0 */ + EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = (uint32_t)(exmc_sdram_init_struct->column_address_width | + exmc_sdram_init_struct->row_address_width | + exmc_sdram_init_struct->data_width | + exmc_sdram_init_struct->internal_bank_number | + exmc_sdram_init_struct->cas_latency | + (exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET) | + exmc_sdram_init_struct->sdclock_config | + (exmc_sdram_init_struct->burst_read_switch << SDCTL_BRSTRD_OFFSET) | + exmc_sdram_init_struct->pipeline_read_delay); - /* configuration EXMC_SDTCFG0 */ - EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay)-1U) | - (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay)-1U) << SDTCFG_XSRD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_address_select_delay)-1U) << SDTCFG_RASD_OFFSET) | - (((exmc_sdram_init_struct->timing->auto_refresh_delay)-1U) << SDTCFG_ARFD_OFFSET) | - (((exmc_sdram_init_struct->timing->write_recovery_delay)-1U) << SDTCFG_WRD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_precharge_delay)-1U) << SDTCFG_RPD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_to_column_delay)-1U) << SDTCFG_RCD_OFFSET); - }else{ - /* configuration EXMC_SDCTL0 and EXMC_SDCTL1 */ + /* configure EXMC_SDTCFG0 */ + EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay) - 1U) | + (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay) - 1U) << SDTCFG_XSRD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_address_select_delay) - 1U) << SDTCFG_RASD_OFFSET) | + (((exmc_sdram_init_struct->timing->auto_refresh_delay) - 1U) << SDTCFG_ARFD_OFFSET) | + (((exmc_sdram_init_struct->timing->write_recovery_delay) - 1U) << SDTCFG_WRD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_precharge_delay) - 1U) << SDTCFG_RPD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_to_column_delay) - 1U) << SDTCFG_RCD_OFFSET); + } else { + /* configure EXMC_SDCTL0 and EXMC_SDCTL1 */ /* some bits in the EXMC_SDCTL1 register are reserved */ - sdctl0 = EXMC_SDCTL(EXMC_SDRAM_DEVICE0) & (~( EXMC_SDCTL_PIPED | EXMC_SDCTL_BRSTRD | EXMC_SDCTL_SDCLK )); - - sdctl0 |= (uint32_t)exmc_sdram_init_struct->sdclock_config | - exmc_sdram_init_struct->brust_read_switch | - exmc_sdram_init_struct->pipeline_read_delay; + sdctl0 = EXMC_SDCTL(EXMC_SDRAM_DEVICE0) & (~(EXMC_SDCTL_PIPED | EXMC_SDCTL_BRSTRD | EXMC_SDCTL_SDCLK)); + + sdctl0 |= (uint32_t)(exmc_sdram_init_struct->sdclock_config | + (exmc_sdram_init_struct->burst_read_switch << SDCTL_BRSTRD_OFFSET) | + exmc_sdram_init_struct->pipeline_read_delay); - sdctl1 = (uint32_t)exmc_sdram_init_struct->column_address_width | - exmc_sdram_init_struct->row_address_width | - exmc_sdram_init_struct->data_width | - exmc_sdram_init_struct->internal_bank_number | - exmc_sdram_init_struct->cas_latency | - exmc_sdram_init_struct->write_protection ; + sdctl1 = (uint32_t)(exmc_sdram_init_struct->column_address_width | + exmc_sdram_init_struct->row_address_width | + exmc_sdram_init_struct->data_width | + exmc_sdram_init_struct->internal_bank_number | + exmc_sdram_init_struct->cas_latency | + (exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET)); EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = sdctl0; EXMC_SDCTL(EXMC_SDRAM_DEVICE1) = sdctl1; - + /* configuration EXMC_SDTCFG0 and EXMC_SDTCFG1 */ /* some bits in the EXMC_SDTCFG1 register are reserved */ sdtcfg0 = EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) & (~(EXMC_SDTCFG_RPD | EXMC_SDTCFG_WRD | EXMC_SDTCFG_ARFD)); - sdtcfg0 |= (uint32_t)(((exmc_sdram_init_struct->timing->auto_refresh_delay)-1U) << SDTCFG_ARFD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_precharge_delay)-1U) << SDTCFG_RPD_OFFSET) | - (((exmc_sdram_init_struct->timing->write_recovery_delay)-1U) << SDTCFG_WRD_OFFSET); + sdtcfg0 |= (uint32_t)(((exmc_sdram_init_struct->timing->auto_refresh_delay) - 1U) << SDTCFG_ARFD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_precharge_delay) - 1U) << SDTCFG_RPD_OFFSET) | + (((exmc_sdram_init_struct->timing->write_recovery_delay) - 1U) << SDTCFG_WRD_OFFSET); - sdtcfg1 = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay)-1U) | - (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay)-1U) << SDTCFG_XSRD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_address_select_delay)-1U) << SDTCFG_RASD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_to_column_delay)-1U) << SDTCFG_RCD_OFFSET); + sdtcfg1 = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay) - 1U) | + (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay) - 1U) << SDTCFG_XSRD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_address_select_delay) - 1U) << SDTCFG_RASD_OFFSET) | + (((exmc_sdram_init_struct->timing->row_to_column_delay) - 1U) << SDTCFG_RCD_OFFSET); EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = sdtcfg0; EXMC_SDTCFG(EXMC_SDRAM_DEVICE1) = sdtcfg1; @@ -659,88 +697,74 @@ void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) } /*! - \brief initialize the struct exmc_sdram_parameter_struct + \brief initialize exmc_sdram_struct_command_para_init with the default values \param[in] none - \param[out] the initialized struct exmc_sdram_parameter_struct pointer + \param[out] the initialized struct exmc_sdram_struct_command_para_init pointer \retval none */ -void exmc_sdram_parameter_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) +void exmc_sdram_struct_command_para_init(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct) { /* configure the structure with default value */ - exmc_sdram_init_struct->sdram_device = EXMC_SDRAM_DEVICE0; - exmc_sdram_init_struct->column_address_width = EXMC_SDRAM_COW_ADDRESS_8; - exmc_sdram_init_struct->row_address_width = EXMC_SDRAM_ROW_ADDRESS_11; - exmc_sdram_init_struct->data_width = EXMC_SDRAM_DATABUS_WIDTH_16B; - exmc_sdram_init_struct->internal_bank_number = EXMC_SDRAM_4_INTER_BANK; - exmc_sdram_init_struct->cas_latency = EXMC_CAS_LATENCY_1_SDCLK; - exmc_sdram_init_struct->write_protection = ENABLE; - exmc_sdram_init_struct->sdclock_config = EXMC_SDCLK_DISABLE; - exmc_sdram_init_struct->brust_read_switch = DISABLE; - exmc_sdram_init_struct->pipeline_read_delay = EXMC_PIPELINE_DELAY_0_HCLK; - - exmc_sdram_init_struct->timing->load_mode_register_delay = 16U; - exmc_sdram_init_struct->timing->exit_selfrefresh_delay = 16U; - exmc_sdram_init_struct->timing->row_address_select_delay = 16U; - exmc_sdram_init_struct->timing->auto_refresh_delay = 16U; - exmc_sdram_init_struct->timing->write_recovery_delay = 16U; - exmc_sdram_init_struct->timing->row_precharge_delay = 16U; - exmc_sdram_init_struct->timing->row_to_column_delay = 16U; + exmc_sdram_command_init_struct->mode_register_content = 0U; + exmc_sdram_command_init_struct->auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK; + exmc_sdram_command_init_struct->bank_select = EXMC_SDRAM_DEVICE0_SELECT; + exmc_sdram_command_init_struct->command = EXMC_SDRAM_NORMAL_OPERATION; } /*! \brief configure the SDRAM memory command - \param[in] exmc_sdram_command_init_struct: initialize EXMC SDRAM command + \param[in] exmc_sdram_command_init_struct: initialize EXMC SDRAM command mode_register_content: auto_refresh_number: EXMC_SDRAM_AUTO_REFLESH_x_SDCLK, x=1..15 - bank_select: EXMC_SDRAM_DEVICE0_SELECT, EXMC_SDRAM_DEVICE1_SELECT, EXMC_SDRAM_DEVICE0_1_SELECT - command: EXMC_SDRAM_NORMAL_OPERATION, EXMC_SDRAM_CLOCK_ENABLE, EXMC_SDRAM_PRECHARGE_ALL, - EXMC_SDRAM_AUTO_REFRESH, EXMC_SDRAM_LOAD_MODE_REGISTER, EXMC_SDRAM_SELF_REFRESH, - EXMC_SDRAM_POWERDOWN_ENTRY + bank_select: EXMC_SDRAM_DEVICE0_SELECT, EXMC_SDRAM_DEVICE1_SELECT, EXMC_SDRAM_DEVICE0_1_SELECT + command: EXMC_SDRAM_NORMAL_OPERATION, EXMC_SDRAM_CLOCK_ENABLE, EXMC_SDRAM_PRECHARGE_ALL, + EXMC_SDRAM_AUTO_REFRESH, EXMC_SDRAM_LOAD_MODE_REGISTER, EXMC_SDRAM_SELF_REFRESH, + EXMC_SDRAM_POWERDOWN_ENTRY \param[out] none \retval none */ -void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_command_init_struct) +void exmc_sdram_command_config(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct) { /* configure command register */ EXMC_SDCMD = (uint32_t)((exmc_sdram_command_init_struct->command) | - (exmc_sdram_command_init_struct->bank_select) | - ((exmc_sdram_command_init_struct->auto_refresh_number)) | - ((exmc_sdram_command_init_struct->mode_register_content)<bank_select) | + ((exmc_sdram_command_init_struct->auto_refresh_number)) | + ((exmc_sdram_command_init_struct->mode_register_content) << SDCMD_MRC_OFFSET)); } /*! \brief set auto-refresh interval - \param[in] exmc_count: the number SDRAM clock cycles unit between two successive auto-refresh commands - \arg (SDRAM refresh period / number of rows) - 20 + \param[in] exmc_count: the number SDRAM clock cycles unit between two successive auto-refresh commands, 0x0000~0x1FFF \param[out] none \retval none */ void exmc_sdram_refresh_count_set(uint32_t exmc_count) { uint32_t sdari; - + sdari = EXMC_SDARI & (~EXMC_SDARI_ARINTV); EXMC_SDARI = sdari | (uint32_t)((exmc_count << SDARI_ARINTV_OFFSET) & EXMC_SDARI_ARINTV); } /*! \brief set the number of successive auto-refresh command - \param[in] exmc_number: how many successive Auto-refresh cycles will be send when CMD = Auto-refresh command - \arg EXMC_SDRAM_AUTO_REFLESH_x_SDCLK, x=1..15 + \param[in] exmc_number: the number of successive auto-refresh cycles will be send, 1~15 + \arg EXMC_SDRAM_AUTO_REFLESH_x_SDCLK(x=1..15) \param[out] none \retval none */ void exmc_sdram_autorefresh_number_set(uint32_t exmc_number) { uint32_t sdcmd; - + sdcmd = EXMC_SDCMD & (~EXMC_SDCMD_NARF); EXMC_SDCMD = sdcmd | (uint32_t)((exmc_number << SDCMD_NARF_OFFSET) & EXMC_SDCMD_NARF) ; } /*! - \brief config the write protection function - \param[in] exmc_sdram_device: specifie the SDRAM device + \brief configure the write protection function + \param[in] exmc_sdram_device: specify the SDRAM device + only one parameter can be selected which is shown as below: \arg EXMC_SDRAM_DEVICEx(x=0,1) \param[in] newvalue: ENABLE or DISABLE \param[out] none @@ -748,9 +772,9 @@ void exmc_sdram_autorefresh_number_set(uint32_t exmc_number) */ void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue) { - if (ENABLE == newvalue){ + if(ENABLE == newvalue) { EXMC_SDCTL(exmc_sdram_device) |= (uint32_t)EXMC_SDCTL_WPEN; - }else{ + } else { EXMC_SDCTL(exmc_sdram_device) &= ~((uint32_t)EXMC_SDCTL_WPEN); } @@ -758,7 +782,8 @@ void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatu /*! \brief get the status of SDRAM device0 or device1 - \param[in] exmc_sdram_device: specifie the SDRAM device + \param[in] exmc_sdram_device: specify the SDRAM device + only one parameter can be selected which is shown as below: \arg EXMC_SDRAM_DEVICEx(x=0,1) \param[out] none \retval the status of SDRAM device @@ -770,9 +795,9 @@ uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device) { uint32_t sdstat = 0U; - if(EXMC_SDRAM_DEVICE0 == exmc_sdram_device){ + if(EXMC_SDRAM_DEVICE0 == exmc_sdram_device) { sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA0) >> SDSTAT_STA0_OFFSET); - }else{ + } else { sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA1) >> SDSTAT_STA1_OFFSET); } @@ -782,8 +807,10 @@ uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device) /*! \brief configure the delayed sample clock of read data \param[in] delay_cell: SDRAM the delayed sample clock of read data + only one parameter can be selected which is shown as below: \arg EXMC_SDRAM_x_DELAY_CELL(x=0..15) \param[in] extra_hclk: sample cycle of read data + only one parameter can be selected which is shown as below: \arg EXMC_SDRAM_READSAMPLE_x_EXTRAHCLK(x=0,1) \param[out] none \retval none @@ -791,10 +818,10 @@ uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device) void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk) { uint32_t sdrsctl = 0U; - + sdrsctl = EXMC_SDRSCTL & (~(EXMC_SDRSCTL_SDSC | EXMC_SDRSCTL_SSCR)); sdrsctl |= (uint32_t)(delay_cell & EXMC_SDRSCTL_SDSC) | - ((extra_hclk << SDRSCTL_SSCR_OFFSET) & EXMC_SDRSCTL_SSCR); + ((extra_hclk << SDRSCTL_SSCR_OFFSET) & EXMC_SDRSCTL_SSCR); EXMC_SDRSCTL = sdrsctl; } @@ -822,7 +849,7 @@ void exmc_sdram_readsample_disable(void) /*! - \brief deinitialize exmc SQPIPSRAM + \brief deinitialize EXMC SQPIPSRAM \param[in] none \param[out] none \retval none @@ -837,6 +864,21 @@ void exmc_sqpipsram_deinit(void) EXMC_SIDH = BANK0_SQPI_SIDH_RESET; } +/*! + \brief initialize exmc_sqpipsram_init_struct with the default values + \param[in] the structure exmc_sqpipsram_parameter_struct pointer + \param[out] none + \retval none +*/ +void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct *exmc_sqpipsram_init_struct) +{ + /* configure the structure with default value */ + exmc_sqpipsram_init_struct->sample_polarity = EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE; + exmc_sqpipsram_init_struct->id_length = EXMC_SQPIPSRAM_ID_LENGTH_64B; + exmc_sqpipsram_init_struct->address_bits = EXMC_SQPIPSRAM_ADDR_LENGTH_24B; + exmc_sqpipsram_init_struct->command_bits = EXMC_SQPIPSRAM_COMMAND_LENGTH_8B; +} + /*! \brief initialize EXMC SQPIPSRAM \param[in] exmc_sqpipsram_parameter_struct: configure the EXMC SQPIPSRAM parameter @@ -847,33 +889,19 @@ void exmc_sqpipsram_deinit(void) \param[out] none \retval none */ -void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct) +void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct *exmc_sqpipsram_init_struct) { /* initialize SQPI controller */ EXMC_SINIT = (uint32_t)exmc_sqpipsram_init_struct->sample_polarity | - exmc_sqpipsram_init_struct->id_length | - exmc_sqpipsram_init_struct->address_bits | - exmc_sqpipsram_init_struct->command_bits; -} - -/*! - \brief initialize the struct exmc_sqpipsram_parameter_struct - \param[in] the struct exmc_sqpipsram_parameter_struct pointer - \param[out] none - \retval none -*/ -void exmc_sqpipsram_parameter_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct) -{ - /* configure the structure with default value */ - exmc_sqpipsram_init_struct->sample_polarity = EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE; - exmc_sqpipsram_init_struct->id_length = EXMC_SQPIPSRAM_ID_LENGTH_64B; - exmc_sqpipsram_init_struct->address_bits = EXMC_SQPIPSRAM_ADDR_LENGTH_24B; - exmc_sqpipsram_init_struct->command_bits = EXMC_SQPIPSRAM_COMMAND_LENGTH_8B; + exmc_sqpipsram_init_struct->id_length | + exmc_sqpipsram_init_struct->address_bits | + exmc_sqpipsram_init_struct->command_bits; } /*! \brief set the read command \param[in] read_command_mode: configure SPI PSRAM read command mode + only one parameter can be selected which is shown as below: \arg EXMC_SQPIPSRAM_READ_MODE_DISABLE: not SPI mode \arg EXMC_SQPIPSRAM_READ_MODE_SPI: SPI mode \arg EXMC_SQPIPSRAM_READ_MODE_SQPI: SQPI mode @@ -886,16 +914,17 @@ void exmc_sqpipsram_parameter_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsr void exmc_sqpipsram_read_command_set(uint32_t read_command_mode, uint32_t read_wait_cycle, uint32_t read_command_code) { uint32_t srcmd; - + srcmd = (uint32_t) read_command_mode | - ((read_wait_cycle << SRCMD_RWAITCYCLE_OFFSET) & EXMC_SRCMD_RWAITCYCLE) | - ((read_command_code & EXMC_SRCMD_RCMD)); + ((read_wait_cycle << SRCMD_RWAITCYCLE_OFFSET) & EXMC_SRCMD_RWAITCYCLE) | + ((read_command_code & EXMC_SRCMD_RCMD)); EXMC_SRCMD = srcmd; } /*! \brief set the write command \param[in] write_command_mode: configure SPI PSRAM write command mode + only one parameter can be selected which is shown as below: \arg EXMC_SQPIPSRAM_WRITE_MODE_DISABLE: not SPI mode \arg EXMC_SQPIPSRAM_WRITE_MODE_SPI: SPI mode \arg EXMC_SQPIPSRAM_WRITE_MODE_SQPI: SQPI mode @@ -908,10 +937,10 @@ void exmc_sqpipsram_read_command_set(uint32_t read_command_mode, uint32_t read_w void exmc_sqpipsram_write_command_set(uint32_t write_command_mode, uint32_t write_wait_cycle, uint32_t write_command_code) { uint32_t swcmd; - + swcmd = (uint32_t) write_command_mode | - ((write_wait_cycle << SWCMD_WWAITCYCLE_OFFSET) & EXMC_SWCMD_WWAITCYCLE) | - ((write_command_code & EXMC_SWCMD_WCMD)); + ((write_wait_cycle << SWCMD_WWAITCYCLE_OFFSET) & EXMC_SWCMD_WWAITCYCLE) | + ((write_command_code & EXMC_SWCMD_WCMD)); EXMC_SWCMD = swcmd; } @@ -962,6 +991,7 @@ uint32_t exmc_sqpipsram_high_id_get(void) /*! \brief get the bit value of EXMC send write command bit or read ID command \param[in] send_command_flag: the send command flag + only one parameter can be selected which is shown as below: \arg EXMC_SEND_COMMAND_FLAG_RDID: EXMC_SRCMD_RDID flag bit \arg EXMC_SEND_COMMAND_FLAG_SC: EXMC_SWCMD_SC flag bit \param[out] none @@ -970,32 +1000,34 @@ uint32_t exmc_sqpipsram_high_id_get(void) FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag) { uint32_t flag = 0x00000000U; - - if(EXMC_SEND_COMMAND_FLAG_RDID == send_command_flag){ + + if(EXMC_SEND_COMMAND_FLAG_RDID == send_command_flag) { flag = EXMC_SRCMD; - }else if(EXMC_SEND_COMMAND_FLAG_SC == send_command_flag){ + } else if(EXMC_SEND_COMMAND_FLAG_SC == send_command_flag) { flag = EXMC_SWCMD; - }else{ + } else { } - - if (flag & send_command_flag){ + + if(flag & send_command_flag) { /* flag is set */ return SET; - }else{ + } else { /* flag is reset */ return RESET; } } /*! - \brief check EXMC flag is set or not - \param[in] bank: specifies the NAND bank , PC card bank or SDRAM device + \brief get EXMC flag status + \param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device + only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 \arg EXMC_BANK3_PCCARD: the PC Card bank \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] flag: specify get which flag + \param[in] flag: EXMC status and flag + only one parameter can be selected which is shown as below: \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status @@ -1009,32 +1041,34 @@ FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag) { uint32_t status = 0x00000000U; - if((EXMC_BANK1_NAND == bank) || (EXMC_BANK2_NAND == bank) || (EXMC_BANK3_PCCARD == bank)){ + if((EXMC_BANK1_NAND == bank) || (EXMC_BANK2_NAND == bank) || (EXMC_BANK3_PCCARD == bank)) { /* NAND bank1,bank2 or PC card bank3 */ status = EXMC_NPINTEN(bank); - }else{ - /* SDRAM device0 or device1 */ + } else { + /* SDRAM device0 or device1 */ status = EXMC_SDSTAT; } - - if((status & flag) != (uint32_t)flag){ + + if((status & flag) != (uint32_t)flag) { /* flag is reset */ return RESET; - }else{ + } else { /* flag is set */ return SET; } } /*! - \brief clear EXMC flag - \param[in] bank: specifie the NAND bank , PCCARD bank or SDRAM device + \brief clear EXMC flag status + \param[in] exmc_bank: specify the NAND bank , PCCARD bank or SDRAM device + only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 \arg EXMC_BANK3_PCCARD: the PC card bank \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] flag: specify get which flag + \param[in] flag: EXMC status and flag + only one parameter can be selected which is shown as below: \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status @@ -1046,133 +1080,140 @@ FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag) */ void exmc_flag_clear(uint32_t bank, uint32_t flag) { - if((EXMC_BANK1_NAND == bank) || (EXMC_BANK2_NAND == bank) || (EXMC_BANK3_PCCARD == bank)){ + if((EXMC_BANK1_NAND == bank) || (EXMC_BANK2_NAND == bank) || (EXMC_BANK3_PCCARD == bank)) { /* NAND bank1,bank2 or PC card bank3 */ EXMC_NPINTEN(bank) &= ~flag; - }else{ + } else { /* SDRAM device0 or device1 */ EXMC_SDSTAT &= ~flag; - } + } } /*! - \brief check EXMC interrupt flag is set or not - \param[in] bank: specifies the NAND bank , PC card bank or SDRAM device + \brief enable EXMC interrupt + \param[in] bank: specify the NAND bank,PC card bank or SDRAM device + only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 \arg EXMC_BANK3_PCCARD: the PC card bank \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] interrupt_source: specify get which interrupt flag - \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: interrupt source of falling edge - \arg EXMC_SDRAM_INT_FLAG_REFRESH: interrupt source of refresh error + \param[in] interrupt: specify get which interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge + \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level + \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge + \arg EXMC_SDRAM_INT_REFRESH: interrupt source of refresh error \param[out] none - \retval FlagStatus: SET or RESET + \retval none */ -FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt_source) +void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt) { - uint32_t status = 0x00000000U, interrupt_enable = 0x00000000U, interrupt_state = 0x00000000U; - - if((EXMC_BANK1_NAND == bank) || (EXMC_BANK2_NAND == bank) || (EXMC_BANK3_PCCARD == bank)){ + if((EXMC_BANK1_NAND == bank) || (EXMC_BANK2_NAND == bank) || (EXMC_BANK3_PCCARD == bank)) { /* NAND bank1,bank2 or PC card bank3 */ - status = EXMC_NPINTEN(bank); - interrupt_state = (status & (interrupt_source >> INTEN_INTS_OFFSET)); - }else{ - /* SDRAM device0 or device1 */ - status = EXMC_SDARI; - interrupt_state = (EXMC_SDSTAT & EXMC_SDSDAT_REIF); - } - - interrupt_enable = (status & interrupt_source); - - if ((interrupt_enable) && (interrupt_state)){ - /* interrupt flag is set */ - return SET; - }else{ - /* interrupt flag is reset */ - return RESET; + EXMC_NPINTEN(bank) |= interrupt; + } else { + /* SDRAM device0 or device1 */ + EXMC_SDARI |= EXMC_SDARI_REIE; } } /*! - \brief clear EXMC interrupt flag - \param[in] bank: specifies the NAND bank , PC card bank or SDRAM device + \brief disable EXMC interrupt + \param[in] bank: specify the NAND bank , PC card bank or SDRAM device + only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 \arg EXMC_BANK3_PCCARD: the PC card bank \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] interrupt_source: specify get which interrupt flag - \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: interrupt source of falling edge - \arg EXMC_SDRAM_INT_FLAG_REFRESH: interrupt source of refresh error + \param[in] interrupt: specify get which interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge + \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level + \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge + \arg EXMC_SDRAM_INT_REFRESH: interrupt source of refresh error \param[out] none \retval none */ -void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt_source) +void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt) { - if((EXMC_BANK1_NAND == bank) || (EXMC_BANK2_NAND == bank) || (EXMC_BANK3_PCCARD == bank)){ + if((EXMC_BANK1_NAND == bank) || (EXMC_BANK2_NAND == bank) || (EXMC_BANK3_PCCARD == bank)) { /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(bank) &= ~(interrupt_source >> INTEN_INTS_OFFSET); - }else{ + EXMC_NPINTEN(bank) &= ~interrupt; + } else { /* SDRAM device0 or device1 */ - EXMC_SDARI |= EXMC_SDARI_REC; + EXMC_SDARI &= ~EXMC_SDARI_REIE; } } /*! - \brief enable EXMC interrupt - \param[in] bank: specifies the NAND bank,PC card bank or SDRAM device + \brief get EXMC interrupt flag + \param[in] bank: specify the NAND bank , PC card bank or SDRAM device + only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 \arg EXMC_BANK3_PCCARD: the PC card bank \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] interrupt_source: specify get which interrupt flag - \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge - \arg EXMC_SDRAM_INT_REFRESH: interrupt source of refresh error + \param[in] interrupt: EXMC interrupt flag + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: interrupt source of rising edge + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: interrupt source of high-level + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: interrupt source of falling edge + \arg EXMC_SDRAM_INT_FLAG_REFRESH: interrupt source of refresh error \param[out] none - \retval none + \retval FlagStatus: SET or RESET */ -void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt_source) +FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt) { - if((EXMC_BANK1_NAND == bank) || (EXMC_BANK2_NAND == bank) || (EXMC_BANK3_PCCARD == bank)){ + uint32_t status = 0x00000000U, interrupt_enable = 0x00000000U, interrupt_state = 0x00000000U; + + if((EXMC_BANK1_NAND == bank) || (EXMC_BANK2_NAND == bank) || (EXMC_BANK3_PCCARD == bank)) { /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(bank) |= interrupt_source; - }else{ + status = EXMC_NPINTEN(bank); + interrupt_state = (status & (interrupt >> INTEN_INTS_OFFSET)); + } else { /* SDRAM device0 or device1 */ - EXMC_SDARI |= EXMC_SDARI_REIE; + status = EXMC_SDARI; + interrupt_state = (EXMC_SDSTAT & EXMC_SDSDAT_REIF); + } + + interrupt_enable = (status & interrupt); + + if((interrupt_enable) && (interrupt_state)) { + /* interrupt flag is set */ + return SET; + } else { + /* interrupt flag is reset */ + return RESET; } } /*! - \brief disable EXMC interrupt - \param[in] bank: specifies the NAND bank , PC card bank or SDRAM device + \brief clear EXMC interrupt flag + \param[in] bank: specify the NAND bank , PC card bank or SDRAM device + only one parameter can be selected which is shown as below: \arg EXMC_BANK1_NAND: the NAND bank1 \arg EXMC_BANK2_NAND: the NAND bank2 \arg EXMC_BANK3_PCCARD: the PC card bank \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] interrupt_source: specify get which interrupt flag - \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge - \arg EXMC_SDRAM_INT_REFRESH: interrupt source of refresh error + \param[in] interrupt: specify get which interrupt flag + only one parameter can be selected which is shown as below: + \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: interrupt source of rising edge + \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: interrupt source of high-level + \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: interrupt source of falling edge + \arg EXMC_SDRAM_INT_FLAG_REFRESH: interrupt source of refresh error \param[out] none \retval none */ -void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt_source) +void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt) { - if((EXMC_BANK1_NAND == bank) || (EXMC_BANK2_NAND == bank) || (EXMC_BANK3_PCCARD == bank)){ + if((EXMC_BANK1_NAND == bank) || (EXMC_BANK2_NAND == bank) || (EXMC_BANK3_PCCARD == bank)) { /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(bank) &= ~interrupt_source; - }else{ + EXMC_NPINTEN(bank) &= ~(interrupt >> INTEN_INTS_OFFSET); + } else { /* SDRAM device0 or device1 */ - EXMC_SDARI &= ~EXMC_SDARI_REIE; + EXMC_SDARI |= EXMC_SDARI_REC; } } diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_exti.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_exti.c index ffa56cc5..70246c2e 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_exti.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_exti.c @@ -2,36 +2,33 @@ \file gd32f20x_exti.c \brief EXTI driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -56,7 +53,7 @@ void exti_deinit(void) } /*! - \brief initialize the EXTI + \brief initialize the EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..19): EXTI line x @@ -67,8 +64,9 @@ void exti_deinit(void) \param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum only one parameter can be selected which is shown as below: \arg EXTI_TRIG_RISING: rising edge trigger - \arg EXTI_TRIG_FALLING: falling edge trigger - \arg EXTI_TRIG_BOTH: rising edge and falling edge trigger + \arg EXTI_TRIG_FALLING: falling trigger + \arg EXTI_TRIG_BOTH: rising and falling trigger + \arg EXTI_TRIG_NONE: without rising edge or falling edge trigger \param[out] none \retval none */ @@ -79,9 +77,9 @@ void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum tr EXTI_EVEN &= ~(uint32_t)linex; EXTI_RTEN &= ~(uint32_t)linex; EXTI_FTEN &= ~(uint32_t)linex; - + /* set the EXTI mode and enable the interrupts or events from EXTI line x */ - switch(mode){ + switch(mode) { case EXTI_INTERRUPT: EXTI_INTEN |= (uint32_t)linex; break; @@ -91,9 +89,9 @@ void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum tr default: break; } - + /* set the EXTI trigger type */ - switch(trig_type){ + switch(trig_type) { case EXTI_TRIG_RISING: EXTI_RTEN |= (uint32_t)linex; EXTI_FTEN &= ~(uint32_t)linex; @@ -106,6 +104,7 @@ void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum tr EXTI_RTEN |= (uint32_t)linex; EXTI_FTEN |= (uint32_t)linex; break; + case EXTI_TRIG_NONE: default: break; } @@ -125,29 +124,29 @@ void exti_interrupt_enable(exti_line_enum linex) } /*! - \brief enable the events from EXTI line x + \brief disable the interrupts from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..19): EXTI line x \param[out] none \retval none */ -void exti_event_enable(exti_line_enum linex) +void exti_interrupt_disable(exti_line_enum linex) { - EXTI_EVEN |= (uint32_t)linex; + EXTI_INTEN &= ~(uint32_t)linex; } /*! - \brief disable the interrupt from EXTI line x + \brief enable the events from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..19): EXTI line x \param[out] none \retval none */ -void exti_interrupt_disable(exti_line_enum linex) +void exti_event_enable(exti_line_enum linex) { - EXTI_INTEN &= ~(uint32_t)linex; + EXTI_EVEN |= (uint32_t)linex; } /*! @@ -164,92 +163,87 @@ void exti_event_disable(exti_line_enum linex) } /*! - \brief get EXTI lines flag + \brief enable the software interrupt event from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..19): EXTI line x \param[out] none - \retval FlagStatus: status of flag (RESET or SET) + \retval none */ -FlagStatus exti_flag_get(exti_line_enum linex) +void exti_software_interrupt_enable(exti_line_enum linex) { - if(RESET != (EXTI_PD & (uint32_t)linex)){ - return SET; - }else{ - return RESET; - } + EXTI_SWIEV |= (uint32_t)linex; } /*! - \brief clear EXTI lines pending flag + \brief disable the software interrupt event from EXTI line x \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..19): EXTI line x \param[out] none \retval none */ -void exti_flag_clear(exti_line_enum linex) +void exti_software_interrupt_disable(exti_line_enum linex) { - EXTI_PD = (uint32_t)linex; + EXTI_SWIEV &= ~(uint32_t)linex; } /*! - \brief get EXTI lines flag when the interrupt flag is set + \brief get EXTI line x interrupt pending flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..19): EXTI line x \param[out] none \retval FlagStatus: status of flag (RESET or SET) */ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex) +FlagStatus exti_flag_get(exti_line_enum linex) { - uint32_t flag_left, flag_right; - - flag_left = EXTI_PD & (uint32_t)linex; - flag_right = EXTI_INTEN & (uint32_t)linex; - - if((RESET != flag_left) && (RESET != flag_right)){ + if(RESET != (EXTI_PD & (uint32_t)linex)) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear EXTI lines pending flag + \brief clear EXTI line x interrupt pending flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..19): EXTI line x \param[out] none \retval none */ -void exti_interrupt_flag_clear(exti_line_enum linex) +void exti_flag_clear(exti_line_enum linex) { EXTI_PD = (uint32_t)linex; } /*! - \brief enable EXTI software interrupt event + \brief get EXTI line x interrupt pending flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..19): EXTI line x \param[out] none - \retval none + \retval FlagStatus: status of flag (RESET or SET) */ -void exti_software_interrupt_enable(exti_line_enum linex) +FlagStatus exti_interrupt_flag_get(exti_line_enum linex) { - EXTI_SWIEV |= (uint32_t)linex; + if(RESET != (EXTI_PD & (uint32_t)linex)) { + return SET; + } else { + return RESET; + } } /*! - \brief disable EXTI software interrupt event + \brief clear EXTI line x interrupt pending flag \param[in] linex: EXTI line number, refer to exti_line_enum only one parameter can be selected which is shown as below: \arg EXTI_x (x=0..19): EXTI line x \param[out] none \retval none */ -void exti_software_interrupt_disable(exti_line_enum linex) +void exti_interrupt_flag_clear(exti_line_enum linex) { - EXTI_SWIEV &= ~(uint32_t)linex; + EXTI_PD = (uint32_t)linex; } diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_fmc.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_fmc.c index f10bf34c..aee94fae 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_fmc.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_fmc.c @@ -2,44 +2,51 @@ \file gd32f20x_fmc.c \brief FMC driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f20x_fmc.h" +/* return the FMC bank0 state */ +fmc_state_enum fmc_bank0_state_get(void); /** AvV **/ +/* return the FMC bank1 state */ +fmc_state_enum fmc_bank1_state_get(void); /** AvV **/ +/* check FMC bank0 ready or not */ +static fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout); +/* check FMC bank1 ready or not */ +static fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout); + /*! \brief set the wait state counter value - \param[in] wscnt£ºwait state counter value + \param[in] wscnt��wait state counter value + only one parameter can be selected which is shown as below: \arg WS_WSCNT_0: FMC 0 wait state \arg WS_WSCNT_1: FMC 1 wait state \arg WS_WSCNT_2: FMC 2 wait state @@ -49,7 +56,7 @@ OF SUCH DAMAGE. void fmc_wscnt_set(uint32_t wscnt) { uint32_t reg; - + reg = FMC_WS; /* set the wait state counter value */ reg &= ~FMC_WS_WSCNT; @@ -64,14 +71,14 @@ void fmc_wscnt_set(uint32_t wscnt) */ void fmc_unlock(void) { - if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){ + if((RESET != (FMC_CTL0 & FMC_CTL0_LK))) { /* write the FMC unlock key */ FMC_KEY0 = UNLOCK_KEY0; FMC_KEY0 = UNLOCK_KEY1; } - if(FMC_BANK0_SIZE < FMC_SIZE){ + if(FMC_BANK0_SIZE < FMC_SIZE) { /* write the FMC unlock key */ - if(RESET != (FMC_CTL1 & FMC_CTL1_LK)){ + if(RESET != (FMC_CTL1 & FMC_CTL1_LK)) { FMC_KEY1 = UNLOCK_KEY0; FMC_KEY1 = UNLOCK_KEY1; } @@ -79,7 +86,7 @@ void fmc_unlock(void) } /*! - \brief unlock the FMC bank0 operation + \brief unlock the FMC bank0 operation this function can be used for all GD32F20x devices. for GD32F20x with flash more than 512KB, this function unlocks bank0. for GD32F20x with flash no more than 512KB and it is equivalent to fmc_unlock function. @@ -89,7 +96,7 @@ void fmc_unlock(void) */ void fmc_bank0_unlock(void) { - if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){ + if((RESET != (FMC_CTL0 & FMC_CTL0_LK))) { /* write the FMC unlock key */ FMC_KEY0 = UNLOCK_KEY0; FMC_KEY0 = UNLOCK_KEY1; @@ -97,7 +104,7 @@ void fmc_bank0_unlock(void) } /*! - \brief unlock the FMC bank1 operation + \brief unlock the FMC bank1 operation this function can be used for GD32F20x with flash more than 512KB. \param[in] none \param[out] none @@ -105,7 +112,7 @@ void fmc_bank0_unlock(void) */ void fmc_bank1_unlock(void) { - if((RESET != (FMC_CTL1 & FMC_CTL1_LK))){ + if((RESET != (FMC_CTL1 & FMC_CTL1_LK))) { /* write the FMC unlock key */ FMC_KEY1 = UNLOCK_KEY0; FMC_KEY1 = UNLOCK_KEY1; @@ -122,8 +129,8 @@ void fmc_lock(void) { /* set the LK bit */ FMC_CTL0 |= FMC_CTL0_LK; - - if(FMC_BANK0_SIZE < FMC_SIZE){ + + if(FMC_BANK0_SIZE < FMC_SIZE) { /* set the LK bit */ FMC_CTL1 |= FMC_CTL1_LK; } @@ -167,11 +174,11 @@ fmc_state_enum fmc_page_erase(uint32_t page_address) { fmc_state_enum fmc_state; /* flash size is greater than 512k */ - if(FMC_BANK0_SIZE < FMC_SIZE){ - if(FMC_BANK0_END_ADDRESS > page_address){ + if(FMC_BANK0_SIZE < FMC_SIZE) { + if(FMC_BANK0_END_ADDRESS > page_address) { fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); /* if the last operation is completed, start page erase */ - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { FMC_CTL0 |= FMC_CTL0_PER; FMC_ADDR0 = page_address; FMC_CTL0 |= FMC_CTL0_START; @@ -180,14 +187,14 @@ fmc_state_enum fmc_page_erase(uint32_t page_address) /* reset the PER bit */ FMC_CTL0 &= ~FMC_CTL0_PER; } - }else{ + } else { /* wait for the FMC ready */ fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); /* if the last operation is completed, start page erase */ - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { FMC_CTL1 |= FMC_CTL1_PER; FMC_ADDR1 = page_address; - if(FMC_OBSTAT & FMC_OBSTAT_SPC){ + if(FMC_OBSTAT & FMC_OBSTAT_SPC) { FMC_ADDR0 = page_address; } FMC_CTL1 |= FMC_CTL1_START; @@ -197,10 +204,10 @@ fmc_state_enum fmc_page_erase(uint32_t page_address) FMC_CTL1 &= ~FMC_CTL1_PER; } } - }else{ + } else { fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); /* if the last operation is completed, start page erase */ - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { FMC_CTL0 |= FMC_CTL0_PER; FMC_ADDR0 = page_address; FMC_CTL0 |= FMC_CTL0_START; @@ -224,10 +231,10 @@ fmc_state_enum fmc_mass_erase(void) { fmc_state_enum fmc_state; /* flash size is greater than 512k */ - if(FMC_BANK0_SIZE < FMC_SIZE){ + if(FMC_BANK0_SIZE < FMC_SIZE) { /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { /* start whole chip erase */ FMC_CTL0 |= FMC_CTL0_MER; FMC_CTL0 |= FMC_CTL0_START; @@ -237,7 +244,7 @@ fmc_state_enum fmc_mass_erase(void) FMC_CTL0 &= ~FMC_CTL0_MER; } fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { /* start whole chip erase */ FMC_CTL1 |= FMC_CTL1_MER; FMC_CTL1 |= FMC_CTL1_START; @@ -246,20 +253,20 @@ fmc_state_enum fmc_mass_erase(void) /* reset the MER bit */ FMC_CTL1 &= ~FMC_CTL1_MER; } - }else{ + } else { fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ + + if(FMC_READY == fmc_state) { /* start whole chip erase */ FMC_CTL0 |= FMC_CTL0_MER; - FMC_CTL0 |= FMC_CTL0_START; + FMC_CTL0 |= FMC_CTL0_START; /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); /* reset the MER bit */ FMC_CTL0 &= ~FMC_CTL0_MER; } } - /* return the FMC state */ + /* return the FMC state */ return fmc_state; } @@ -275,7 +282,7 @@ fmc_state_enum fmc_bank0_erase(void) /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { /* start FMC bank0 erase */ FMC_CTL0 |= FMC_CTL0_MER; FMC_CTL0 |= FMC_CTL0_START; @@ -284,7 +291,7 @@ fmc_state_enum fmc_bank0_erase(void) /* reset the MER bit */ FMC_CTL0 &= ~FMC_CTL0_MER; } - /* return the fmc state */ + /* return the FMC state */ return fmc_state; } @@ -299,8 +306,8 @@ fmc_state_enum fmc_bank1_erase(void) fmc_state_enum fmc_state = FMC_READY; /* wait for the FMC ready */ fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ + + if(FMC_READY == fmc_state) { /* start FMC bank1 erase */ FMC_CTL1 |= FMC_CTL1_MER; FMC_CTL1 |= FMC_CTL1_START; @@ -309,7 +316,7 @@ fmc_state_enum fmc_bank1_erase(void) /* reset the MER bit */ FMC_CTL1 &= ~FMC_CTL1_MER; } - /* return the fmc state */ + /* return the FMC state */ return fmc_state; } @@ -324,11 +331,11 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) { fmc_state_enum fmc_state = FMC_READY; /* flash size is greater than 512k */ - if(FMC_BANK0_SIZE < FMC_SIZE){ - if(FMC_BANK0_END_ADDRESS > address){ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ + if(FMC_BANK0_SIZE < FMC_SIZE) { + if(FMC_BANK0_END_ADDRESS > address) { + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { /* set the PG bit to start program */ FMC_CTL0 |= FMC_CTL0_PG; REG32(address) = data; @@ -337,10 +344,10 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) /* reset the PG bit */ FMC_CTL0 &= ~FMC_CTL0_PG; } - }else{ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ + } else { + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { /* set the PG bit to start program */ FMC_CTL1 |= FMC_CTL1_PG; REG32(address) = data; @@ -350,10 +357,10 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) FMC_CTL1 &= ~FMC_CTL1_PG; } } - }else{ + } else { fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ + + if(FMC_READY == fmc_state) { /* set the PG bit to start program */ FMC_CTL0 |= FMC_CTL0_PG; REG32(address) = data; @@ -361,7 +368,7 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); /* reset the PG bit */ FMC_CTL0 &= ~FMC_CTL0_PG; - } + } } /* return the FMC state */ return fmc_state; @@ -378,11 +385,11 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) { fmc_state_enum fmc_state = FMC_READY; /* flash size is greater than 512k */ - if(FMC_BANK0_SIZE < FMC_SIZE){ - if(FMC_BANK0_END_ADDRESS > address){ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ + if(FMC_BANK0_SIZE < FMC_SIZE) { + if(FMC_BANK0_END_ADDRESS > address) { + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { /* set the PG bit to start program */ FMC_CTL0 |= FMC_CTL0_PG; REG16(address) = data; @@ -391,10 +398,10 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) /* reset the PG bit */ FMC_CTL0 &= ~FMC_CTL0_PG; } - }else{ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ + } else { + fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { /* set the PG bit to start program */ FMC_CTL1 |= FMC_CTL1_PG; REG16(address) = data; @@ -404,10 +411,10 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) FMC_CTL1 &= ~FMC_CTL1_PG; } } - }else{ + } else { fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ + + if(FMC_READY == fmc_state) { /* set the PG bit to start program */ FMC_CTL0 |= FMC_CTL0_PG; REG16(address) = data; @@ -415,7 +422,7 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); /* reset the PG bit */ FMC_CTL0 &= ~FMC_CTL0_PG; - } + } } /* return the FMC state */ return fmc_state; @@ -429,14 +436,14 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) */ void ob_unlock(void) { - if(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){ + if(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)) { /* write the FMC key */ FMC_OBKEY = UNLOCK_KEY0; FMC_OBKEY = UNLOCK_KEY1; } /* wait until OBWEN bit is set by hardware */ - while(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){ + while(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)) { } } @@ -466,11 +473,11 @@ fmc_state_enum ob_erase(void) fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); /* check the option byte security protection value */ - if(RESET != ob_spc_get()){ - temp_spc = FMC_USPC; + if(RESET != ob_spc_get()) { + temp_spc = FMC_USPC; } - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { /* start erase the option byte */ FMC_CTL0 |= FMC_CTL0_OBER; @@ -478,22 +485,22 @@ fmc_state_enum ob_erase(void) /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ + + if(FMC_READY == fmc_state) { /* reset the OBER bit */ FMC_CTL0 &= ~FMC_CTL0_OBER; /* set the OBPG bit */ FMC_CTL0 |= FMC_CTL0_OBPG; /* no security protection */ - OB_SPC = (uint16_t)temp_spc; + OB_SPC = (uint16_t)temp_spc; /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_TOERR != fmc_state){ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + if(FMC_TOERR != fmc_state) { /* reset the OBPG bit */ FMC_CTL0 &= ~FMC_CTL0_OBPG; } - }else{ - if(FMC_TOERR != fmc_state){ + } else { + if(FMC_TOERR != fmc_state) { /* reset the OBPG bit */ FMC_CTL0 &= ~FMC_CTL0_OBPG; } @@ -505,10 +512,11 @@ fmc_state_enum ob_erase(void) /*! \brief enable write protection - \param[in] ob_wp: specify sector to be write protected, set the bit to 1 if - you want to protect the corresponding pages. meanwhile, sector - macro could used to set specific sector write protected. + \param[in] ob_wp: specify sector to be write protected, set the bit to 1 if + you want to protect the corresponding pages. meanwhile, sector + macro could used to set specific sector write protected. one or more parameters can be selected which are shown as below: + OB_WP_NONE: disable all erase/program protection \arg OB_WPx(x = 0..31): write protect specify sector \arg OB_WP_ALL: write protect all sector \param[out] none @@ -526,40 +534,40 @@ fmc_state_enum ob_write_protection_enable(uint32_t ob_wp) temp_wp2 = (uint16_t)((ob_wp & OB_WP2_WP2) >> 16U); temp_wp3 = (uint16_t)((ob_wp & OB_WP3_WP3) >> 24U); - if(FMC_READY == fmc_state){ - + if(FMC_READY == fmc_state) { + /* set the OBPG bit*/ FMC_CTL0 |= FMC_CTL0_OBPG; - if(0xFFU != temp_wp0){ + if(0xFFU != temp_wp0) { OB_WP0 = temp_wp0; - + /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); } - if((FMC_READY == fmc_state) && (0xFFU != temp_wp1)){ + if((FMC_READY == fmc_state) && (0xFFU != temp_wp1)) { OB_WP1 = temp_wp1; - + /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); } - if((FMC_READY == fmc_state) && (0xFFU != temp_wp2)){ + if((FMC_READY == fmc_state) && (0xFFU != temp_wp2)) { OB_WP2 = temp_wp2; - + /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); } - if((FMC_READY == fmc_state) && (0xFFU != temp_wp3)){ + if((FMC_READY == fmc_state) && (0xFFU != temp_wp3)) { OB_WP3 = temp_wp3; - + /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); } - if(FMC_TOERR != fmc_state){ + if(FMC_TOERR != fmc_state) { /* reset the OBPG bit */ FMC_CTL0 &= ~FMC_CTL0_OBPG; } - } + } /* return the FMC state */ return fmc_state; } @@ -577,31 +585,31 @@ fmc_state_enum ob_security_protection_config(uint8_t ob_spc) { fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { FMC_CTL0 |= FMC_CTL0_OBER; FMC_CTL0 |= FMC_CTL0_START; - + /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ + + if(FMC_READY == fmc_state) { /* reset the OBER bit */ FMC_CTL0 &= ~FMC_CTL0_OBER; - + /* start the option byte program */ FMC_CTL0 |= FMC_CTL0_OBPG; - + OB_SPC = (uint16_t)ob_spc; /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ + fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state) { /* reset the OBPG bit */ FMC_CTL0 &= ~FMC_CTL0_OBPG; } - }else{ - if(FMC_TOERR != fmc_state){ + } else { + if(FMC_TOERR != fmc_state) { /* reset the OBER bit */ FMC_CTL0 &= ~FMC_CTL0_OBER; } @@ -612,17 +620,21 @@ fmc_state_enum ob_security_protection_config(uint8_t ob_spc) } /*! - \brief program the FMC user option byte + \brief program option bytes user \param[in] ob_fwdgt: option byte watchdog value + only one parameter can be selected which is shown as below: \arg OB_FWDGT_SW: software free watchdog \arg OB_FWDGT_HW: hardware free watchdog \param[in] ob_deepsleep: option byte deepsleep reset value + only one parameter can be selected which is shown as below: \arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode - \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode + \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode \param[in] ob_stdby:option byte standby reset value + only one parameter can be selected which is shown as below: \arg OB_STDBY_NRST: no reset when entering standby mode \arg OB_STDBY_RST: generate a reset instead of entering standby mode \param[in] ob_boot: specifies the option byte boot bank value + only one parameter can be selected which is shown as below: \arg OB_BOOT_B0: boot from bank0 \arg OB_BOOT_B1: boot from bank1 or bank0 if bank1 is void \param[out] none @@ -635,18 +647,18 @@ fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_ /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ + + if(FMC_READY == fmc_state) { /* set the OBPG bit*/ - FMC_CTL0 |= FMC_CTL0_OBPG; + FMC_CTL0 |= FMC_CTL0_OBPG; temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK); OB_USER = (uint16_t)temp; - + /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_TOERR != fmc_state){ + if(FMC_TOERR != fmc_state) { /* reset the OBPG bit */ FMC_CTL0 &= ~FMC_CTL0_OBPG; } @@ -666,15 +678,15 @@ fmc_state_enum ob_data_program(uint32_t address, uint8_t data) { fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + if(FMC_READY == fmc_state) { /* set the OBPG bit */ - FMC_CTL0 |= FMC_CTL0_OBPG; + FMC_CTL0 |= FMC_CTL0_OBPG; REG16(address) = data; - + /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ + + if(FMC_TOERR != fmc_state) { /* reset the OBPG bit */ FMC_CTL0 &= ~FMC_CTL0_OBPG; } @@ -684,7 +696,7 @@ fmc_state_enum ob_data_program(uint32_t address, uint8_t data) } /*! - \brief get the FMC user option byte + \brief get the FMC option bytes user \param[in] none \param[out] none \retval the FMC user option byte values @@ -696,7 +708,7 @@ uint8_t ob_user_get(void) } /*! - \brief get OB_DATA in register FMC_OBSTAT + \brief get the FMC option bytes data \param[in] none \param[out] none \retval ob_data @@ -728,46 +740,14 @@ FlagStatus ob_spc_get(void) { FlagStatus spc_state = RESET; - if(RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)){ + if(RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)) { spc_state = SET; - }else{ + } else { spc_state = RESET; } return spc_state; } -/*! - \brief enable FMC interrupt - \param[in] interrupt: the FMC interrupt source - only one parameter can be selected which is shown as below: - \arg FMC_INT_BANK0_END: enable FMC end of program interrupt - \arg FMC_INT_BANK0_ERR: enable FMC error interrupt - \arg FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt - \arg FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_enable(uint32_t interrupt) -{ - FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt)); -} - -/*! - \brief disable FMC interrupt - \param[in] interrupt: the FMC interrupt source - only one parameter can be selected which is shown as below: - \arg FMC_INT_BANK0_END: enable FMC end of program interrupt - \arg FMC_INT_BANK0_ERR: enable FMC error interrupt - \arg FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt - \arg FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_disable(uint32_t interrupt) -{ - FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt)); -} - /*! \brief check flag is set or not \param[in] flag: check FMC flag @@ -786,9 +766,9 @@ void fmc_interrupt_disable(uint32_t interrupt) */ FlagStatus fmc_flag_get(uint32_t flag) { - if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))){ + if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))) { return SET; - }else{ + } else { return RESET; } } @@ -811,9 +791,41 @@ void fmc_flag_clear(uint32_t flag) FMC_REG_VAL(flag) |= BIT(FMC_BIT_POS(flag)); } +/*! + \brief enable FMC interrupt + \param[in] interrupt: the FMC interrupt source + only one parameter can be selected which is shown as below: + \arg FMC_INT_BANK0_END: FMC bank0 end of program interrupt + \arg FMC_INT_BANK0_ERR: FMC bank0 error interrupt + \arg FMC_INT_BANK1_END: FMC bank1 end of program interrupt + \arg FMC_INT_BANK1_ERR: FMC bank1 error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_enable(fmc_interrupt_enum interrupt) +{ + FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt)); +} + +/*! + \brief disable FMC interrupt + \param[in] interrupt: the FMC interrupt source + only one parameter can be selected which is shown as below: + \arg FMC_INT_BANK0_END: FMC bank0 end of program interrupt + \arg FMC_INT_BANK0_ERR: FMC bank0 error interrupt + \arg FMC_INT_BANK1_END: FMC bank1 end of program interrupt + \arg FMC_INT_BANK1_ERR: FMC bank1 error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_disable(fmc_interrupt_enum interrupt) +{ + FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt)); +} + /*! \brief get FMC interrupt flag state - \param[in] flag: FMC interrupt flags, refer to fmc_interrupt_flag_enum + \param[in] int_flag: FMC interrupt flags, refer to fmc_interrupt_flag_enum only one parameter can be selected which is shown as below: \arg FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit \arg FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit @@ -824,33 +836,33 @@ void fmc_flag_clear(uint32_t flag) \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag) -{ - FlagStatus ret1 = RESET; - FlagStatus ret2 = RESET; - - if(FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){ - /* get the staus of interrupt flag */ - ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); - /* get the staus of interrupt enale bit */ - ret2 = (FlagStatus)(FMC_CTL0 & BIT(FMC_BIT_POS1(flag))); - }else{ - /* get the staus of interrupt flag */ - ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); - /* get the staus of interrupt enale bit */ - ret2 = (FlagStatus)(FMC_CTL1 & BIT(FMC_BIT_POS1(flag))); +FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum int_flag) +{ + uint32_t ret1 = RESET; + uint32_t ret2 = RESET; + + if(FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(int_flag)) { + /* get the status of interrupt flag */ + ret1 = (uint32_t)(FMC_REG_VALS(int_flag) & BIT(FMC_BIT_POS0(int_flag))); + /* get the status of interrupt enable bit */ + ret2 = (uint32_t)(FMC_CTL0 & BIT(FMC_BIT_POS1(int_flag))); + } else { + /* get the status of interrupt flag */ + ret1 = (uint32_t)(FMC_REG_VALS(int_flag) & BIT(FMC_BIT_POS0(int_flag))); + /* get the status of interrupt enable bit */ + ret2 = (uint32_t)(FMC_CTL1 & BIT(FMC_BIT_POS1(int_flag))); } - if(ret1 && ret2){ + if(ret1 && ret2) { return SET; - }else{ + } else { return RESET; } } /*! \brief clear FMC interrupt flag state - \param[in] flag: FMC interrupt flags, refer to can_interrupt_flag_enum + \param[in] int_flag: FMC interrupt flags, refer to can_interrupt_flag_enum only one parameter can be selected which is shown as below: \arg FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit \arg FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit @@ -861,9 +873,9 @@ FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag) \param[out] none \retval none */ -void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag) +void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum int_flag) { - FMC_REG_VALS(flag) |= BIT(FMC_BIT_POS0(flag)); + FMC_REG_VALS(int_flag) |= BIT(FMC_BIT_POS0(int_flag)); } /*! @@ -872,18 +884,18 @@ void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag) \param[out] none \retval state of FMC, refer to fmc_state_enum */ -fmc_state_enum fmc_bank0_state_get(void) +fmc_state_enum fmc_bank0_state_get(void) /** AvV **/ { fmc_state_enum fmc_state = FMC_READY; - - if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)){ + + if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)) { fmc_state = FMC_BUSY; - }else{ - if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)){ + } else { + if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)) { fmc_state = FMC_WPERR; - }else{ - if((uint32_t)0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))){ - fmc_state = FMC_PGERR; + } else { + if((uint32_t)0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))) { + fmc_state = FMC_PGERR; } } } @@ -897,18 +909,18 @@ fmc_state_enum fmc_bank0_state_get(void) \param[out] none \retval state of FMC, refer to fmc_state_enum */ -fmc_state_enum fmc_bank1_state_get(void) +fmc_state_enum fmc_bank1_state_get(void) /** AvV **/ { fmc_state_enum fmc_state = FMC_READY; - if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_BUSY)){ + if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_BUSY)) { fmc_state = FMC_BUSY; - }else{ - if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_WPERR)){ + } else { + if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_WPERR)) { fmc_state = FMC_WPERR; - }else{ - if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_PGERR)){ - fmc_state = FMC_PGERR; + } else { + if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_PGERR)) { + fmc_state = FMC_PGERR; } } } @@ -923,18 +935,18 @@ fmc_state_enum fmc_bank1_state_get(void) \param[out] none \retval state of FMC, refer to fmc_state_enum */ -fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout) +static fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout) { fmc_state_enum fmc_state = FMC_BUSY; - + /* wait for FMC ready */ - do{ + do { /* get FMC state */ fmc_state = fmc_bank0_state_get(); timeout--; - }while((FMC_BUSY == fmc_state) && (0x00U != timeout)); - - if(FMC_BUSY == fmc_state){ + } while((FMC_BUSY == fmc_state) && (0x00U != timeout)); + + if(FMC_BUSY == fmc_state) { fmc_state = FMC_TOERR; } /* return the FMC state */ @@ -947,18 +959,18 @@ fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout) \param[out] none \retval state of FMC, refer to fmc_state_enum */ -fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout) +static fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout) { fmc_state_enum fmc_state = FMC_BUSY; - + /* wait for FMC ready */ - do{ + do { /* get FMC state */ fmc_state = fmc_bank1_state_get(); timeout--; - }while((FMC_BUSY == fmc_state) && (0x00U != timeout)); - - if(FMC_BUSY == fmc_state){ + } while((FMC_BUSY == fmc_state) && (0x00U != timeout)); + + if(FMC_BUSY == fmc_state) { fmc_state = FMC_TOERR; } /* return the FMC state */ diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_fwdgt.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_fwdgt.c index 0afbec24..1c7fdd36 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_fwdgt.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_fwdgt.c @@ -2,46 +2,38 @@ \file gd32f20x_fwdgt.c \brief FWDGT driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f20x_fwdgt.h" -/* write value to FWDGT_CTL_CMD bit field */ -#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) -/* write value to FWDGT_RLD_RLD bit field */ -#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) - /*! \brief enable write access to FWDGT_PSC and FWDGT_RLD \param[in] none @@ -75,6 +67,71 @@ void fwdgt_enable(void) FWDGT_CTL = FWDGT_KEY_ENABLE; } +/*! + \brief configure the free watchdog timer counter prescaler value + \param[in] prescaler_value: specify prescaler value + only one parameter can be selected which is shown as below: + \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 + \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 + \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 + \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 + \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 + \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 + \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value) +{ + uint32_t timeout = FWDGT_PSC_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_PSC */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the PUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_PUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if ((uint32_t)RESET != flag_status){ + return ERROR; + } + + /* configure FWDGT */ + FWDGT_PSC = (uint32_t)prescaler_value; + + return SUCCESS; +} + +/*! + \brief configure the free watchdog timer counter reload value + \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_reload_value_config(uint16_t reload_value) +{ + uint32_t timeout = FWDGT_RLD_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_RLD */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the RUD flag to be reset */ + do{ + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if ((uint32_t)RESET != flag_status){ + return ERROR; + } + + FWDGT_RLD = RLD_RLD(reload_value); + + return SUCCESS; +} + /*! \brief reload the counter of FWDGT \param[in] none @@ -105,16 +162,16 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) { uint32_t timeout = FWDGT_PSC_TIMEOUT; uint32_t flag_status = RESET; - + /* enable write access to FWDGT_PSC,and FWDGT_RLD */ FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - + /* wait until the PUD flag to be reset */ - do{ - flag_status = FWDGT_STAT & FWDGT_STAT_PUD; - }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if ((uint32_t)RESET != flag_status){ + do { + flag_status = FWDGT_STAT & FWDGT_STAT_PUD; + } while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if((uint32_t)RESET != flag_status) { return ERROR; } @@ -123,16 +180,16 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) timeout = FWDGT_RLD_TIMEOUT; /* wait until the RUD flag to be reset */ - do{ - flag_status = FWDGT_STAT & FWDGT_STAT_RUD; - }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if ((uint32_t)RESET != flag_status){ + do { + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + } while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if((uint32_t)RESET != flag_status) { return ERROR; } - + FWDGT_RLD = RLD_RLD(reload_value); - + /* reload the counter */ FWDGT_CTL = FWDGT_KEY_RELOAD; @@ -141,7 +198,7 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) /*! \brief get flag state of FWDGT - \param[in] flag: flag to get + \param[in] flag: flag to get only one parameter can be selected which is shown as below: \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going @@ -150,9 +207,9 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) */ FlagStatus fwdgt_flag_get(uint16_t flag) { - if(FWDGT_STAT & flag){ + if(FWDGT_STAT & flag) { return SET; } - + return RESET; } diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_gpio.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_gpio.c index 0acf1093..4fd2c55a 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_gpio.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_gpio.c @@ -2,46 +2,43 @@ \file gd32f20x_gpio.c \brief GPIO driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f20x_gpio.h" -#define AFIO_EXTI_SOURCE_MASK ((uint8_t)0x03U) /*!< AFIO exti source selection mask*/ +#define AFIO_EXTI_SOURCE_MASK ((uint8_t)0x03U) /*!< AFIO exti source selection mask*/ #define AFIO_EXTI_SOURCE_FIELDS ((uint8_t)0x04U) /*!< select AFIO exti source registers */ #define LSB_16BIT_MASK ((uint16_t)0xFFFFU) /*!< LSB 16-bit mask */ #define PCF_POSITION_MASK ((uint32_t)0x000F0000U) /*!< AFIO_PCF register position mask */ -#define PCF_SWJCFG_MASK ((uint32_t)0xF0FFFFFFU) /*!< AFIO_PCF register SWJCFG mask */ +#define PCF_SWJCFG_MASK ((uint32_t)0xF8FFFFFFU) /*!< AFIO_PCF register SWJCFG mask */ #define PCF_LOCATION1_MASK ((uint32_t)0x00200000U) /*!< AFIO_PCF register location1 mask */ #define PCF_LOCATION2_MASK ((uint32_t)0x00100000U) /*!< AFIO_PCF register location2 mask */ #define AFIO_PCF1_FIELDS ((uint32_t)0x80000000U) /*!< select AFIO_PCF1 register */ @@ -55,7 +52,7 @@ OF SUCH DAMAGE. */ void gpio_deinit(uint32_t gpio_periph) { - switch(gpio_periph){ + switch(gpio_periph) { case GPIOA: /* reset GPIOA */ rcu_periph_reset_enable(RCU_GPIOARST); @@ -120,7 +117,7 @@ void gpio_afio_deinit(void) /*! \brief GPIO parameter initialization - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) \param[in] mode: gpio pin mode only one parameter can be selected which is shown as below: \arg GPIO_MODE_AIN: analog input mode @@ -139,7 +136,6 @@ void gpio_afio_deinit(void) \param[in] pin: GPIO pin one or more parameters can be selected which are shown as below: \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none \retval none */ @@ -151,30 +147,29 @@ void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin /* GPIO mode configuration */ temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU)); - + /* GPIO speed configuration */ - if(((uint32_t)0x00U) != ((uint32_t)mode & ((uint32_t)0x10U))){ - /* output mode max speed:10MHz,2MHz,50MHz */ + if(((uint32_t)0x00U) != ((uint32_t)mode & ((uint32_t)0x10U))) { + /* output mode max speed: 10MHz, 2MHz, 50MHz */ temp_mode |= (uint32_t)speed; } /* configure the eight low port pins with GPIO_CTL0 */ - for(i = 0U;i < 8U;i++){ - if((1U << i) & pin){ + for(i = 0U; i < 8U; i++) { + if((1U << i) & pin) { reg = GPIO_CTL0(gpio_periph); - /* clear the specified pin mode bits */ reg &= ~GPIO_MODE_MASK(i); /* set the specified pin mode bits */ reg |= GPIO_MODE_SET(i, temp_mode); - + /* set IPD or IPU */ - if(GPIO_MODE_IPD == mode){ + if(GPIO_MODE_IPD == mode) { /* reset the corresponding OCTL bit */ GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin); - }else{ + } else { /* set the corresponding OCTL bit */ - if(GPIO_MODE_IPU == mode){ + if(GPIO_MODE_IPU == mode) { GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin); } } @@ -183,22 +178,21 @@ void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin } } /* configure the eight high port pins with GPIO_CTL1 */ - for(i = 8U;i < 16U;i++){ - if((1U << i) & pin){ + for(i = 8U; i < 16U; i++) { + if((1U << i) & pin) { reg = GPIO_CTL1(gpio_periph); - /* clear the specified pin mode bits */ reg &= ~GPIO_MODE_MASK(i - 8U); /* set the specified pin mode bits */ reg |= GPIO_MODE_SET(i - 8U, temp_mode); - + /* set IPD or IPU */ - if(GPIO_MODE_IPD == mode){ + if(GPIO_MODE_IPD == mode) { /* reset the corresponding OCTL bit */ GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin); - }else{ + } else { /* set the corresponding OCTL bit */ - if(GPIO_MODE_IPU == mode){ + if(GPIO_MODE_IPU == mode) { GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin); } } @@ -210,35 +204,35 @@ void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin /*! \brief set GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) \param[in] pin: GPIO pin one or more parameters can be selected which are shown as below: \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval none */ -void gpio_bit_set(uint32_t gpio_periph,uint32_t pin) +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) { GPIO_BOP(gpio_periph) = (uint32_t)pin; } /*! \brief reset GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) \param[in] pin: GPIO pin one or more parameters can be selected which are shown as below: \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL \param[out] none \retval none */ -void gpio_bit_reset(uint32_t gpio_periph,uint32_t pin) +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) { GPIO_BC(gpio_periph) = (uint32_t)pin; } /*! \brief write data to the specified GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) \param[in] pin: GPIO pin one or more parameters can be selected which are shown as below: \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL @@ -248,23 +242,23 @@ void gpio_bit_reset(uint32_t gpio_periph,uint32_t pin) \param[out] none \retval none */ -void gpio_bit_write(uint32_t gpio_periph,uint32_t pin,bit_status bit_value) +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) { - if(RESET != bit_value){ + if(RESET != bit_value) { GPIO_BOP(gpio_periph) = (uint32_t)pin; - }else{ + } else { GPIO_BC(gpio_periph) = (uint32_t)pin; } } /*! \brief write data to the specified GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) + \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G,H,I) \param[in] data: specify the value to be written to the port output data register \param[out] none \retval none */ -void gpio_port_write(uint32_t gpio_periph,uint16_t data) +void gpio_port_write(uint32_t gpio_periph, uint16_t data) { GPIO_OCTL(gpio_periph) = (uint32_t)data; } @@ -278,11 +272,11 @@ void gpio_port_write(uint32_t gpio_periph,uint16_t data) \param[out] none \retval input status of gpio pin: SET or RESET */ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin) +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) { - if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ - return SET; - }else{ + if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph) & (pin))) { + return SET; + } else { return RESET; } } @@ -307,11 +301,11 @@ uint16_t gpio_input_port_get(uint32_t gpio_periph) \param[out] none \retval output status of gpio pin: SET or RESET */ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph,uint32_t pin) +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) { - if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){ + if((uint32_t)RESET != (GPIO_OCTL(gpio_periph) & (pin))) { return SET; - }else{ + } else { return RESET; } } @@ -329,14 +323,15 @@ uint16_t gpio_output_port_get(uint32_t gpio_periph) /*! \brief configure GPIO pin remap - \param[in] gpio_remap: select the pin to remap + \param[in] remap: select the pin to remap + only one parameter can be selected which are shown as below: \arg GPIO_SPI0_REMAP: SPI0 remapping \arg GPIO_I2C0_REMAP: I2C0 remapping \arg GPIO_USART0_REMAP: USART0 remapping \arg GPIO_USART1_REMAP: USART1 remapping \arg GPIO_USART2_PARTIAL_REMAP: USART2 partial remapping \arg GPIO_USART2_FULL_REMAP: USART2 full remapping - \arg GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping + \arg GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping \arg GPIO_TIMER0_FULL_REMAP: TIMER0 full remapping \arg GPIO_TIMER1_PARTIAL_REMAP0: TIMER1 partial remapping \arg GPIO_TIMER1_PARTIAL_REMAP1: TIMER1 partial remapping @@ -354,12 +349,12 @@ uint16_t gpio_output_port_get(uint32_t gpio_periph) \arg GPIO_ADC1_ETRGREG_REMAP: ADC1 external trigger regular conversion remapping \arg GPIO_ENET_REMAP: ENET remapping \arg GPIO_CAN1_REMAP: CAN1 remapping - \arg GPIO_SWJ_NONJTRST_REMAP: full SWJ(JTAG-DP + SW-DP),but without NJTRST + \arg GPIO_SWJ_NONJTRST_REMAP: full SWJ(JTAG-DP + SW-DP), but without NJTRST \arg GPIO_SWJ_SWDPENABLE_REMAP: JTAG-DP disabled and SW-DP enabled \arg GPIO_SWJ_DISABLE_REMAP: JTAG-DP disabled and SW-DP disabled \arg GPIO_SPI2_REMAP: SPI2 remapping \arg GPIO_TIMER1ITI1_REMAP: TIMER1 internal trigger 1 remapping - \arg GPIO_PTP_PPS_REMAP: ethernet PTP PPS remapping + \arg GPIO_PTP_PPS_REMAP: ethernet PTP PPS remapping \arg GPIO_TIMER8_REMAP: TIMER8 remapping \arg GPIO_TIMER9_REMAP: TIMER9 remapping \arg GPIO_TIMER10_REMAP: TIMER10 remapping @@ -370,51 +365,51 @@ uint16_t gpio_output_port_get(uint32_t gpio_periph) \param[out] none \retval none */ -void gpio_pin_remap_config(uint32_t gpio_remap, ControlStatus newvalue) +void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue) { uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U; - if(AFIO_PCF1_FIELDS == (gpio_remap & AFIO_PCF1_FIELDS)){ + if(AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)) { /* get AFIO_PCF1 regiter value */ temp_reg = AFIO_PCF1; - }else{ + } else { /* get AFIO_PCF0 regiter value */ temp_reg = AFIO_PCF0; } - temp_mask = (gpio_remap & PCF_POSITION_MASK) >> 0x10U; - remap1 = gpio_remap & LSB_16BIT_MASK; + temp_mask = (remap & PCF_POSITION_MASK) >> 0x10U; + remap1 = remap & LSB_16BIT_MASK; /* judge pin remap type */ - if((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) == (gpio_remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))){ + if((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) == (remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))) { temp_reg &= PCF_SWJCFG_MASK; AFIO_PCF0 &= PCF_SWJCFG_MASK; - }else if(PCF_LOCATION2_MASK == (gpio_remap & PCF_LOCATION2_MASK)){ + } else if(PCF_LOCATION2_MASK == (remap & PCF_LOCATION2_MASK)) { remap2 = ((uint32_t)0x03U) << temp_mask; temp_reg &= ~remap2; temp_reg |= ~PCF_SWJCFG_MASK; - }else{ - temp_reg &= ~(remap1 << ((gpio_remap >> 0x15U)*0x10U)); + } else { + temp_reg &= ~(remap1 << ((remap >> 0x15U) * 0x10U)); temp_reg |= ~PCF_SWJCFG_MASK; } - + /* set pin remap value */ - if(DISABLE != newvalue){ - temp_reg |= (remap1 << ((gpio_remap >> 0x15U)*0x10U)); + if(DISABLE != newvalue) { + temp_reg |= (remap1 << ((remap >> 0x15U) * 0x10U)); } - - if(AFIO_PCF1_FIELDS == (gpio_remap & AFIO_PCF1_FIELDS)){ - /* set AFIO_PCF1 regiter value */ + + if(AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)) { + /* set AFIO_PCF1 register value */ AFIO_PCF1 = temp_reg; - }else{ - /* set AFIO_PCF0 regiter value */ + } else { + /* set AFIO_PCF0 register value */ AFIO_PCF0 = temp_reg; } } /*! \brief configure GPIO pin remap1 - \param[in] remap_reg: + \param[in] remap_reg: \arg GPIO_PCF2: AFIO port configuration register 2 \arg GPIO_PCF3: AFIO port configuration register 3 \arg GPIO_PCF4: AFIO port configuration register 4 @@ -437,109 +432,109 @@ void gpio_pin_remap_config(uint32_t gpio_remap, ControlStatus newvalue) \arg GPIO_PCF2_DCI_D5_PD3_REMAP: DCI D5 remapped to PD3 \arg GPIO_PCF2_DCI_D5_PI4_REMAP: DCI D5 remapped to PI4 \arg GPIO_PCF2_DCI_D6_PE5_REMAP: DCI D6 remapped to PE5 - \arg GPIO_PCF2_DCI_D6_PI6_REMAP: DCI D6 remapped to PI6 - \arg GPIO_PCF2_DCI_D7_PE6_REMAP: DCI D7 remapped to PE6 - \arg GPIO_PCF2_DCI_D7_PI7_REMAP: DCI D7 remapped to PI7 - \arg GPIO_PCF2_DCI_D8_PH6_REMAP: DCI D8 remapped to PH6 - \arg GPIO_PCF2_DCI_D8_PI1_REMAP: DCI D8 remapped to PI1 - \arg GPIO_PCF2_DCI_D9_PH7_REMAP: DCI D9 remapped to PH7 - \arg GPIO_PCF2_DCI_D9_PI2_REMAP: DCI D9 remapped to PI2 - \arg GPIO_PCF2_DCI_D10_PD6_REMAP: DCI D10 remapped to PD6 - \arg GPIO_PCF2_DCI_D10_PI3_REMAP: DCI D10 remapped to PI3 - \arg GPIO_PCF2_DCI_D11_PF10_REMAP: DCI D11 remapped to PF10 - \arg GPIO_PCF2_DCI_D11_PH15_REMAP: DCI D11 remapped to PH15 - \arg GPIO_PCF2_DCI_D12_PG6_REMAP: DCI D12 remapped to PG6 - \arg GPIO_PCF2_DCI_D13_PG15_REMAP: DCI D12 remapped to PG15 - \arg GPIO_PCF2_DCI_D13_PI0_REMAP: DCI D13 remapped to PI0 - \arg GPIO_PCF2_DCI_HSYNC_PH8_REMAP: DCI HSYNC to PH8 - \arg GPIO_PCF2_PH01_REMAP: PH0/PH1 remapping - \arg GPIO_PCF3_TLI_B5_PA3_REMAP: TLI B5 remapped to PA3 - \arg GPIO_PCF3_TLI_VSYNC_PA4_REMAP: TLI VSYNC remapped to PA4 - \arg GPIO_PCF3_TLI_G2_PA6_REMAP: TLI G2 remapped to PA6 - \arg GPIO_PCF3_TLI_R6_PA8_REMAP: TLI R6 remapped to PA8 - \arg GPIO_PCF3_TLI_R4_PA11_REMAP: TLI R4 remapped to PA11 - \arg GPIO_PCF3_TLI_R5_PA12_REMAP: TLI R5 remapped to PA12 - \arg GPIO_PCF3_TLI_R3_PB0_REMAP: TLI R3 remapped to PB0 - \arg GPIO_PCF3_TLI_R6_PB1_REMAP: TLI R6 remapped to PB1 - \arg GPIO_PCF3_TLI_B6_PB8_REMAP: TLI B6 remapped to PB8 - \arg GPIO_PCF3_TLI_B7_PB9_REMAP: TLI B7 remapped to PB9 - \arg GPIO_PCF3_TLI_G4_PB10_REMAP: TLI G4 remapped to PB10 - \arg GPIO_PCF3_TLI_G5_PB11_REMAP: TLI G5 remapped to PB11 - \arg GPIO_PCF3_TLI_HSYNC_PC6_REMAP: TLI HSYNC remapped to PC6 - \arg GPIO_PCF3_TLI_G6_PC7_REMAP: TLI G6 remapped to PC7 - \arg GPIO_PCF3_TLI_R2_PC10_REMAP: TLI R2 remapped to PC10 - \arg GPIO_PCF3_TLI_G7_PD3_REMAP: TLI G7 remapped to PD3 - \arg GPIO_PCF3_TLI_B2_PD6_REMAP: TLI B2 remapped to PD6 - \arg GPIO_PCF3_TLI_B3_PD10_REMAP: TLI B3 remapped to PD10 - \arg GPIO_PCF3_TLI_B0_PE4_REMAP: TLI B0 remapped to PE4 - \arg GPIO_PCF3_TLI_G0_PE5_REMAP: TLI G0 remapped to PE5 - \arg GPIO_PCF3_TLI_G1_PE6_REMAP: TLI G1 remapped to PE6 - \arg GPIO_PCF3_TLI_G3_PE11_REMAP: TLI G3 remapped to PE11 - \arg GPIO_PCF3_TLI_B4_PE12_REMAP: TLI B4 remapped to PE12 - \arg GPIO_PCF3_TLI_DE_PE13_REMAP: TLI DE remapped to PE13 - \arg GPIO_PCF3_TLI_CLK_PE14_REMAP: TLI CLK remapped to PE14 - \arg GPIO_PCF3_TLI_R7_PE15_REMAP: TLI R7 remapped to PE15 - \arg GPIO_PCF3_TLI_DE_PF10_REMAP: TLI DE remapped to PF10 - \arg GPIO_PCF3_TLI_R7_PG6_REMAP: TLI R7 remapped to PG6 - \arg GPIO_PCF3_TLI_CLK_PG7_REMAP: TLI CLK remapped to PG7 - \arg GPIO_PCF3_TLI_G3_PG10_REMAP: TLI G3 remapped to PG10 - \arg GPIO_PCF3_TLI_B2_PG10_REMAP: TLI B2 remapped to PG10 - \arg GPIO_PCF3_TLI_B3_PG11_REMAP: TLI B3 remapped to PG11 - \arg GPIO_PCF4_TLI_B4_PG12_REMAP: B4 remapped to PG12 - \arg GPIO_PCF4_TLI_B1_PG12_REMAP: B1 remapped to PG12 - \arg GPIO_PCF4_TLI_R0_PH2_REMAP2: R0 remapped to PH2 - \arg GPIO_PCF4_TLI_R1_PH3_REMAP: TLI R1 remapped to PH3 - \arg GPIO_PCF4_TLI_R2_PH8_REMAP: TLI R2 remapped to PH8 - \arg GPIO_PCF4_TLI_R3_PH9_REMAP: TLI R3 remapped to PH9 - \arg GPIO_PCF4_TLI_R4_PH10_REMAP: TLI R4 remapped to PH10 - \arg GPIO_PCF4_TLI_R5_PH11_REMAP: TLI R5 remapped to PH11 - \arg GPIO_PCF4_TLI_R6_PH12_REMAP: TLI R6 remapped to PH12 - \arg GPIO_PCF4_TLI_G2_PH13_REMAP: TLI G2 remapped to PH13 - \arg GPIO_PCF4_TLI_G3_PH14_REMAP: TLI G3 remapped to PH14 - \arg GPIO_PCF4_TLI_G4_PH15_REMAP: TLI G4 remapped to PH15 - \arg GPIO_PCF4_TLI_G5_PI0_REMAP: TLI G5 remapped to PI0 - \arg GPIO_PCF4_TLI_G6_PI1_REMAP: TLI G6 remapped to PI1 - \arg GPIO_PCF4_TLI_G7_PI2_REMAP: TLI G7 remapped to PI2 - \arg GPIO_PCF4_TLI_B4_PI4_REMAP: TLI B4 remapped to PI4 - \arg GPIO_PCF4_TLI_B5_PI5_REMAP: TLI B5 remapped to PI5 - \arg GPIO_PCF4_TLI_B6_PI6_REMAP: TLI B6 remapped to PI6 - \arg GPIO_PCF4_TLI_B7_PI7_REMAP: TLI B7 remapped to PI7 - \arg GPIO_PCF4_TLI_VSYNC_PI9_REMAP: TLI VSYNC remapped to PI9 - \arg GPIO_PCF4_TLI_HSYNC_PI10_REMAP: TLI HSYNC remapped to PI10 - \arg GPIO_PCF4_TLI_R0_PH4_REMAP: TLI R0 remapped to PH4 - \arg GPIO_PCF4_TLI_R1_PI3_REMAP: TLI R1 remapped to PI3 - \arg GPIO_PCF4_SPI1_SCK_PD3_REMAP: SPI1 SCK remapped to PD3 - \arg GPIO_PCF4_SPI2_MOSI_PD6_REMAP: SPI2 MOSI remapped to PD6 - \arg GPIO_PCF5_I2C2_REMAP0: I2C2 remapping 0 - \arg GPIO_PCF5_I2C2_REMAP1: I2C2 remapping 1 - \arg GPIO_PCF5_TIMER1_CH0_REMAP: TIMER1 CH0 remapped to PA5 - \arg GPIO_PCF5_TIMER4_REMAP: TIMER4 CH0 remapping - \arg GPIO_PCF5_TIMER7_CHON_REMAP0: TIMER7 CHON remapping 0 - \arg GPIO_PCF5_TIMER7_CHON_REMAP1: TIMER7 CHON remapping 1 - \arg GPIO_PCF5_TIMER7_CH_REMAP: TIMER7 CH remapping - \arg GPIO_PCF5_I2C1_REMAP0: I2C1 remapping 0 - \arg GPIO_PCF5_I2C1_REMAP1: I2C1 remapping 1 - \arg GPIO_PCF5_SPI1_NSCK_REMAP0: SPI1 NSS/SCK remapping 0 - \arg GPIO_PCF5_SPI1_NSCK_REMAP1: SPI1 NSS/SCK remapping 1 - \arg GPIO_PCF5_SPI1_IO_REMAP0: SPI1 MISO/MOSI remapping 0 - \arg GPIO_PCF5_SPI1_IO_REMAP1: SPI1 MISO/MOSI remapping 1 - \arg GPIO_PCF5_UART3_REMAP: UART3 remapping - \arg GPIO_PCF5_TIMER11_REMAP: TIMER11 remapping - \arg GPIO_PCF5_CAN0_ADD_REMAP: CAN0 addition remapping - \arg GPIO_PCF5_ENET_TXD3_REMAP: ETH_TXD3 remapped to PE2 - \arg GPIO_PCF5_PPS_HI_REMAP: ETH_PPS_OUT remapped to PG8 - \arg GPIO_PCF5_ENET_TXD01_REMAP: ETH_TX_EN/ETH_TXD0/ETH_TXD1 remapping - \arg GPIO_PCF5_ENET_CRSCOL_REMAP: ETH_MII_CRS/ETH_MII_COL remapping - \arg GPIO_PCF5_ENET_RX_HI_REMAP: ETH_RXD2/ETH_RXD3/ETH_RX_ER remapping - \arg GPIO_PCF5_UART6_REMAP: UART6 remapping - \arg GPIO_PCF5_USART5_CK_PG7_REMAP: USART5 CK remapped to PG7 - \arg GPIO_PCF5_USART5_RTS_PG12_REMAP: USART5 RTS remapped to PG12 - \arg GPIO_PCF5_USART5_CTS_PG13_REMAP: USART5 CTS remapped to PG13 - \arg GPIO_PCF5_USART5_TX_PG14_REMAP: USART5 TX remapped to PG14 - \arg GPIO_PCF5_USART5_RX_PG9_REMAP: USART5 RX remapped to PG9 - \arg GPIO_PCF5_EXMC_SDNWE_PC0_REMAP: EXMC SDNWE remapped to PC0 - \arg GPIO_PCF5_EXMC_SDCKE0_PC3_REMAP: EXMC SDCKE0 remapped to PC3 - \arg GPIO_PCF5_EXMC_SDCKE1_PB5_REMAP: EXMC SDCKE1 remapped to PB5 + \arg GPIO_PCF2_DCI_D6_PI6_REMAP: DCI D6 remapped to PI6 + \arg GPIO_PCF2_DCI_D7_PE6_REMAP: DCI D7 remapped to PE6 + \arg GPIO_PCF2_DCI_D7_PI7_REMAP: DCI D7 remapped to PI7 + \arg GPIO_PCF2_DCI_D8_PH6_REMAP: DCI D8 remapped to PH6 + \arg GPIO_PCF2_DCI_D8_PI1_REMAP: DCI D8 remapped to PI1 + \arg GPIO_PCF2_DCI_D9_PH7_REMAP: DCI D9 remapped to PH7 + \arg GPIO_PCF2_DCI_D9_PI2_REMAP: DCI D9 remapped to PI2 + \arg GPIO_PCF2_DCI_D10_PD6_REMAP: DCI D10 remapped to PD6 + \arg GPIO_PCF2_DCI_D10_PI3_REMAP: DCI D10 remapped to PI3 + \arg GPIO_PCF2_DCI_D11_PF10_REMAP: DCI D11 remapped to PF10 + \arg GPIO_PCF2_DCI_D11_PH15_REMAP: DCI D11 remapped to PH15 + \arg GPIO_PCF2_DCI_D12_PG6_REMAP: DCI D12 remapped to PG6 + \arg GPIO_PCF2_DCI_D13_PG15_REMAP: DCI D12 remapped to PG15 + \arg GPIO_PCF2_DCI_D13_PI0_REMAP: DCI D13 remapped to PI0 + \arg GPIO_PCF2_DCI_HSYNC_PH8_REMAP: DCI HSYNC to PH8 + \arg GPIO_PCF2_PH01_REMAP: PH0/PH1 remapping + \arg GPIO_PCF3_TLI_B5_PA3_REMAP: TLI B5 remapped to PA3 + \arg GPIO_PCF3_TLI_VSYNC_PA4_REMAP: TLI VSYNC remapped to PA4 + \arg GPIO_PCF3_TLI_G2_PA6_REMAP: TLI G2 remapped to PA6 + \arg GPIO_PCF3_TLI_R6_PA8_REMAP: TLI R6 remapped to PA8 + \arg GPIO_PCF3_TLI_R4_PA11_REMAP: TLI R4 remapped to PA11 + \arg GPIO_PCF3_TLI_R5_PA12_REMAP: TLI R5 remapped to PA12 + \arg GPIO_PCF3_TLI_R3_PB0_REMAP: TLI R3 remapped to PB0 + \arg GPIO_PCF3_TLI_R6_PB1_REMAP: TLI R6 remapped to PB1 + \arg GPIO_PCF3_TLI_B6_PB8_REMAP: TLI B6 remapped to PB8 + \arg GPIO_PCF3_TLI_B7_PB9_REMAP: TLI B7 remapped to PB9 + \arg GPIO_PCF3_TLI_G4_PB10_REMAP: TLI G4 remapped to PB10 + \arg GPIO_PCF3_TLI_G5_PB11_REMAP: TLI G5 remapped to PB11 + \arg GPIO_PCF3_TLI_HSYNC_PC6_REMAP: TLI HSYNC remapped to PC6 + \arg GPIO_PCF3_TLI_G6_PC7_REMAP: TLI G6 remapped to PC7 + \arg GPIO_PCF3_TLI_R2_PC10_REMAP: TLI R2 remapped to PC10 + \arg GPIO_PCF3_TLI_G7_PD3_REMAP: TLI G7 remapped to PD3 + \arg GPIO_PCF3_TLI_B2_PD6_REMAP: TLI B2 remapped to PD6 + \arg GPIO_PCF3_TLI_B3_PD10_REMAP: TLI B3 remapped to PD10 + \arg GPIO_PCF3_TLI_B0_PE4_REMAP: TLI B0 remapped to PE4 + \arg GPIO_PCF3_TLI_G0_PE5_REMAP: TLI G0 remapped to PE5 + \arg GPIO_PCF3_TLI_G1_PE6_REMAP: TLI G1 remapped to PE6 + \arg GPIO_PCF3_TLI_G3_PE11_REMAP: TLI G3 remapped to PE11 + \arg GPIO_PCF3_TLI_B4_PE12_REMAP: TLI B4 remapped to PE12 + \arg GPIO_PCF3_TLI_DE_PE13_REMAP: TLI DE remapped to PE13 + \arg GPIO_PCF3_TLI_CLK_PE14_REMAP: TLI CLK remapped to PE14 + \arg GPIO_PCF3_TLI_R7_PE15_REMAP: TLI R7 remapped to PE15 + \arg GPIO_PCF3_TLI_DE_PF10_REMAP: TLI DE remapped to PF10 + \arg GPIO_PCF3_TLI_R7_PG6_REMAP: TLI R7 remapped to PG6 + \arg GPIO_PCF3_TLI_CLK_PG7_REMAP: TLI CLK remapped to PG7 + \arg GPIO_PCF3_TLI_G3_PG10_REMAP: TLI G3 remapped to PG10 + \arg GPIO_PCF3_TLI_B2_PG10_REMAP: TLI B2 remapped to PG10 + \arg GPIO_PCF3_TLI_B3_PG11_REMAP: TLI B3 remapped to PG11 + \arg GPIO_PCF4_TLI_B4_PG12_REMAP: B4 remapped to PG12 + \arg GPIO_PCF4_TLI_B1_PG12_REMAP: B1 remapped to PG12 + \arg GPIO_PCF4_TLI_R0_PH2_REMAP2: R0 remapped to PH2 + \arg GPIO_PCF4_TLI_R1_PH3_REMAP: TLI R1 remapped to PH3 + \arg GPIO_PCF4_TLI_R2_PH8_REMAP: TLI R2 remapped to PH8 + \arg GPIO_PCF4_TLI_R3_PH9_REMAP: TLI R3 remapped to PH9 + \arg GPIO_PCF4_TLI_R4_PH10_REMAP: TLI R4 remapped to PH10 + \arg GPIO_PCF4_TLI_R5_PH11_REMAP: TLI R5 remapped to PH11 + \arg GPIO_PCF4_TLI_R6_PH12_REMAP: TLI R6 remapped to PH12 + \arg GPIO_PCF4_TLI_G2_PH13_REMAP: TLI G2 remapped to PH13 + \arg GPIO_PCF4_TLI_G3_PH14_REMAP: TLI G3 remapped to PH14 + \arg GPIO_PCF4_TLI_G4_PH15_REMAP: TLI G4 remapped to PH15 + \arg GPIO_PCF4_TLI_G5_PI0_REMAP: TLI G5 remapped to PI0 + \arg GPIO_PCF4_TLI_G6_PI1_REMAP: TLI G6 remapped to PI1 + \arg GPIO_PCF4_TLI_G7_PI2_REMAP: TLI G7 remapped to PI2 + \arg GPIO_PCF4_TLI_B4_PI4_REMAP: TLI B4 remapped to PI4 + \arg GPIO_PCF4_TLI_B5_PI5_REMAP: TLI B5 remapped to PI5 + \arg GPIO_PCF4_TLI_B6_PI6_REMAP: TLI B6 remapped to PI6 + \arg GPIO_PCF4_TLI_B7_PI7_REMAP: TLI B7 remapped to PI7 + \arg GPIO_PCF4_TLI_VSYNC_PI9_REMAP: TLI VSYNC remapped to PI9 + \arg GPIO_PCF4_TLI_HSYNC_PI10_REMAP: TLI HSYNC remapped to PI10 + \arg GPIO_PCF4_TLI_R0_PH4_REMAP: TLI R0 remapped to PH4 + \arg GPIO_PCF4_TLI_R1_PI3_REMAP: TLI R1 remapped to PI3 + \arg GPIO_PCF4_SPI1_SCK_PD3_REMAP: SPI1 SCK remapped to PD3 + \arg GPIO_PCF4_SPI2_MOSI_PD6_REMAP: SPI2 MOSI remapped to PD6 + \arg GPIO_PCF5_I2C2_REMAP0: I2C2 remapping 0 + \arg GPIO_PCF5_I2C2_REMAP1: I2C2 remapping 1 + \arg GPIO_PCF5_TIMER1_CH0_REMAP: TIMER1 CH0 remapped to PA5 + \arg GPIO_PCF5_TIMER4_REMAP: TIMER4 CH0 remapping + \arg GPIO_PCF5_TIMER7_CHON_REMAP0: TIMER7 CHON remapping 0 + \arg GPIO_PCF5_TIMER7_CHON_REMAP1: TIMER7 CHON remapping 1 + \arg GPIO_PCF5_TIMER7_CH_REMAP: TIMER7 CH remapping + \arg GPIO_PCF5_I2C1_REMAP0: I2C1 remapping 0 + \arg GPIO_PCF5_I2C1_REMAP1: I2C1 remapping 1 + \arg GPIO_PCF5_SPI1_NSCK_REMAP0: SPI1 NSS/SCK remapping 0 + \arg GPIO_PCF5_SPI1_NSCK_REMAP1: SPI1 NSS/SCK remapping 1 + \arg GPIO_PCF5_SPI1_IO_REMAP0: SPI1 MISO/MOSI remapping 0 + \arg GPIO_PCF5_SPI1_IO_REMAP1: SPI1 MISO/MOSI remapping 1 + \arg GPIO_PCF5_UART3_REMAP: UART3 remapping + \arg GPIO_PCF5_TIMER11_REMAP: TIMER11 remapping + \arg GPIO_PCF5_CAN0_ADD_REMAP: CAN0 addition remapping + \arg GPIO_PCF5_ENET_TXD3_REMAP: ETH_TXD3 remapped to PE2 + \arg GPIO_PCF5_PPS_HI_REMAP: ETH_PPS_OUT remapped to PG8 + \arg GPIO_PCF5_ENET_TXD01_REMAP: ETH_TX_EN/ETH_TXD0/ETH_TXD1 remapping + \arg GPIO_PCF5_ENET_CRSCOL_REMAP: ETH_MII_CRS/ETH_MII_COL remapping + \arg GPIO_PCF5_ENET_RX_HI_REMAP: ETH_RXD2/ETH_RXD3/ETH_RX_ER remapping + \arg GPIO_PCF5_UART6_REMAP: UART6 remapping + \arg GPIO_PCF5_USART5_CK_PG7_REMAP: USART5 CK remapped to PG7 + \arg GPIO_PCF5_USART5_RTS_PG12_REMAP: USART5 RTS remapped to PG12 + \arg GPIO_PCF5_USART5_CTS_PG13_REMAP: USART5 CTS remapped to PG13 + \arg GPIO_PCF5_USART5_TX_PG14_REMAP: USART5 TX remapped to PG14 + \arg GPIO_PCF5_USART5_RX_PG9_REMAP: USART5 RX remapped to PG9 + \arg GPIO_PCF5_EXMC_SDNWE_PC0_REMAP: EXMC SDNWE remapped to PC0 + \arg GPIO_PCF5_EXMC_SDCKE0_PC3_REMAP: EXMC SDCKE0 remapped to PC3 + \arg GPIO_PCF5_EXMC_SDCKE1_PB5_REMAP: EXMC SDCKE1 remapped to PB5 \arg GPIO_PCF5_EXMC_SDNE0_PC2_REMAP: EXMC SDNE0 remapped to PC2 \arg GPIO_PCF5_EXMC_SDNE1_PB6_REMAP: EXMC SDNE1 remapped to PB6 \param[in] newvalue: ENABLE or DISABLE @@ -550,63 +545,83 @@ void gpio_pin_remap1_config(uint8_t remap_reg, uint32_t remap, ControlStatus new { uint32_t reg = 0U; - if(DISABLE != newvalue){ + if(DISABLE != newvalue) { /* AFIO port configuration register selection */ - if(GPIO_PCF2 == remap_reg){ + if(GPIO_PCF2 == remap_reg) { reg = AFIO_PCF2; reg |= remap; AFIO_PCF2 = reg; - }else if(GPIO_PCF3 == remap_reg){ + } else if(GPIO_PCF3 == remap_reg) { reg = AFIO_PCF3; reg |= remap; AFIO_PCF3 = reg; - }else if(GPIO_PCF4 == remap_reg){ + } else if(GPIO_PCF4 == remap_reg) { reg = AFIO_PCF4; reg |= remap; AFIO_PCF4 = reg; - }else if(GPIO_PCF5 == remap_reg){ + } else if(GPIO_PCF5 == remap_reg) { reg = AFIO_PCF5; reg |= remap; AFIO_PCF5 = reg; - }else{ + } else { /* illegal parameters */ } - }else{ - if(GPIO_PCF2 == remap_reg){ + } else { + if(GPIO_PCF2 == remap_reg) { reg = AFIO_PCF2; reg &= ~remap; AFIO_PCF2 = reg; - }else if(GPIO_PCF3 == remap_reg){ + } else if(GPIO_PCF3 == remap_reg) { reg = AFIO_PCF3; reg &= ~remap; AFIO_PCF3 = reg; - }else if(GPIO_PCF4 == remap_reg){ + } else if(GPIO_PCF4 == remap_reg) { reg = AFIO_PCF4; reg &= ~remap; AFIO_PCF4 = reg; - }else if(GPIO_PCF5 == remap_reg){ + } else if(GPIO_PCF5 == remap_reg) { reg = AFIO_PCF5; reg &= ~remap; AFIO_PCF5 = reg; - }else{ + } else { /* illegal parameters */ } } } +/*! + \brief select ethernet MII or RMII PHY + \param[in] enet_sel: ethernet MII or RMII PHY selection + \arg GPIO_ENET_PHY_MII: configure ethernet MAC for connection with an MII PHY + \arg GPIO_ENET_PHY_RMII: configure ethernet MAC for connection with an RMII PHY + \param[out] none + \retval none +*/ +void gpio_ethernet_phy_select(uint32_t enet_sel) +{ + /* clear AFIO_PCF0_ENET_PHY_SEL bit */ + AFIO_PCF0 &= (uint32_t)(~AFIO_PCF0_ENET_PHY_SEL); + + /* select MII or RMII PHY */ + AFIO_PCF0 |= (uint32_t)enet_sel; +} + /*! \brief select GPIO pin exti sources \param[in] output_port: gpio event output port + only one parameter can be selected which are shown as below: \arg GPIO_PORT_SOURCE_GPIOA: output port source A \arg GPIO_PORT_SOURCE_GPIOB: output port source B \arg GPIO_PORT_SOURCE_GPIOC: output port source C \arg GPIO_PORT_SOURCE_GPIOD: output port source D - \arg GPIO_PORT_SOURCE_GPIOE: output port source E + \arg GPIO_PORT_SOURCE_GPIOE: output port source E \arg GPIO_PORT_SOURCE_GPIOF: output port source F \arg GPIO_PORT_SOURCE_GPIOG: output port source G \arg GPIO_PORT_SOURCE_GPIOH: output port source H \arg GPIO_PORT_SOURCE_GPIOI: output port source I - \param[in] output_pin: GPIO_PIN_SOURCE_x(x=0..15) + \param[in] output_pin: GPIO output pin source + only one parameter can be selected which are shown as below: + \arg GPIO_PIN_SOURCE_x(x=0..15) \param[out] none \retval none */ @@ -616,19 +631,19 @@ void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin) source = ((uint32_t)0x0FU) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)); /* select EXTI sources */ - if(GPIO_PIN_SOURCE_4 > output_pin){ + if(GPIO_PIN_SOURCE_4 > output_pin) { /* select EXTI0/EXTI1/EXTI2/EXTI3 */ AFIO_EXTISS0 &= ~source; AFIO_EXTISS0 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); - }else if(GPIO_PIN_SOURCE_8 > output_pin){ + } else if(GPIO_PIN_SOURCE_8 > output_pin) { /* select EXTI4/EXTI5/EXTI6/EXTI7 */ AFIO_EXTISS1 &= ~source; AFIO_EXTISS1 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); - }else if(GPIO_PIN_SOURCE_12 > output_pin){ + } else if(GPIO_PIN_SOURCE_12 > output_pin) { /* select EXTI8/EXTI9/EXTI10/EXTI11 */ AFIO_EXTISS2 &= ~source; AFIO_EXTISS2 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); - }else{ + } else { /* select EXTI12/EXTI13/EXTI14/EXTI15 */ AFIO_EXTISS3 &= ~source; AFIO_EXTISS3 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); @@ -644,7 +659,7 @@ void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin) \arg GPIO_EVENT_PORT_GPIOC: event output port C \arg GPIO_EVENT_PORT_GPIOD: event output port D \arg GPIO_EVENT_PORT_GPIOE: event output port E - \param[in] output_pin: + \param[in] output_pin: GPIO event output pin only one parameter can be selected which are shown as below: \arg GPIO_EVENT_PIN_x(x=0..15) \param[out] none @@ -654,13 +669,13 @@ void gpio_event_output_config(uint8_t output_port, uint8_t output_pin) { uint32_t reg = 0U; reg = AFIO_EC; - + /* clear AFIO_EC_PORT and AFIO_EC_PIN bits */ - reg &= (uint32_t)(~(AFIO_EC_PORT|AFIO_EC_PIN)); - + reg &= (uint32_t)(~(AFIO_EC_PORT | AFIO_EC_PIN)); + reg |= (uint32_t)((uint32_t)output_port << GPIO_OUTPUT_PORT_OFFSET); reg |= (uint32_t)output_pin; - + AFIO_EC = reg; } @@ -695,7 +710,7 @@ void gpio_event_output_disable(void) \param[out] none \retval none */ -void gpio_pin_lock(uint32_t gpio_periph,uint32_t pin) +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) { uint32_t lock = 0x00010000U; lock |= pin; @@ -707,20 +722,3 @@ void gpio_pin_lock(uint32_t gpio_periph,uint32_t pin) lock = GPIO_LOCK(gpio_periph); lock = GPIO_LOCK(gpio_periph); } - -/*! - \brief select ethernet MII or RMII PHY - \param[in] enet_sel: ethernet MII or RMII PHY selection - \arg GPIO_ENET_PHY_MII: configure ethernet MAC for connection with an MII PHY - \arg GPIO_ENET_PHY_RMII: configure ethernet MAC for connection with an RMII PHY - \param[out] none - \retval none -*/ -void gpio_ethernet_phy_select(uint32_t enet_sel) -{ - /* clear AFIO_PCF0_ENET_PHY_SEL bit */ - AFIO_PCF0 &= (uint32_t)(~AFIO_PCF0_ENET_PHY_SEL); - - /* select MII or RMII PHY */ - AFIO_PCF0 |= (uint32_t)enet_sel; -} diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_hau.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_hau.c index 6b2482fb..5cc79f0c 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_hau.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_hau.c @@ -1,37 +1,34 @@ /*! - \file gd32f20x_cau.c - \brief CAU driver + \file gd32f20x_hau.c + \brief HAU driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -40,7 +37,7 @@ OF SUCH DAMAGE. /*! \brief reset the HAU peripheral - \param[in] none + \param[in] none \param[out] none \retval none */ @@ -63,20 +60,20 @@ void hau_deinit(void) \param[out] none \retval none */ -void hau_init(hau_init_parameter_struct* initpara) +void hau_init(hau_init_parameter_struct *initpara) { /* configure the algorithm, mode and the data type */ HAU_CTL &= ~(HAU_CTL_ALGM_0 | HAU_CTL_ALGM_1 | HAU_CTL_DATAM | HAU_CTL_HMS); HAU_CTL |= (initpara->algo | initpara->datatype | initpara->mode); - - /* when mode is HMAC, set the key */ - if(HAU_MODE_HMAC == initpara->mode){ + + /* when mode is HMAC, set the key */ + if(HAU_MODE_HMAC == initpara->mode) { HAU_CTL &= ~HAU_CTL_KLM; HAU_CTL |= initpara->keytype; } /* start the digest of a new message */ - HAU_CTL |= HAU_CTL_START; + HAU_CTL |= HAU_CTL_START; } /*! @@ -90,7 +87,7 @@ void hau_init(hau_init_parameter_struct* initpara) \param[out] none \retval none */ -void hau_init_parameter_init(hau_init_parameter_struct* initpara) +void hau_init_struct_para_init(hau_init_parameter_struct *initpara) { initpara->algo = HAU_ALGO_SHA1; initpara->mode = HAU_MODE_HASH; @@ -100,7 +97,7 @@ void hau_init_parameter_init(hau_init_parameter_struct* initpara) /*! \brief reset the HAU processor core - \param[in] none + \param[in] none \param[out] none \retval none */ @@ -123,7 +120,7 @@ void hau_reset(void) \retval none */ void hau_last_word_validbits_num_config(uint32_t valid_num) -{ +{ HAU_CFG &= ~(HAU_CFG_VBL); HAU_CFG |= CFG_VBL(valid_num); } @@ -146,8 +143,8 @@ void hau_data_write(uint32_t data) \retval number of words in the input FIFO */ uint32_t hau_infifo_words_num_get(void) -{ - uint32_t ret = 0U; +{ + uint32_t ret = 0U; ret = GET_CTL_NWIF(HAU_CTL); return ret; } @@ -159,7 +156,7 @@ uint32_t hau_infifo_words_num_get(void) out[7:0]: message digest result 0-7 \retval none */ -void hau_digest_read(hau_digest_parameter_struct* digestpara) +void hau_digest_read(hau_digest_parameter_struct *digestpara) { digestpara->out[0] = HAU_DO0; digestpara->out[1] = HAU_DO1; @@ -172,7 +169,7 @@ void hau_digest_read(hau_digest_parameter_struct* digestpara) } /*! - \brief enable digest calculation + \brief enable digest calculation \param[in] none \param[out] none \retval none @@ -183,7 +180,7 @@ void hau_digest_calculation_enable(void) } /*! - \brief configure single or multiple DMA is used, and digest calculation at the end of a DMA transfer or not + \brief configure single or multiple DMA is used, and digest calculation at the end of a DMA transfer or not \param[in] multi_single only one parameter can be selected which is shown as below \arg SINGLE_DMA_AUTO_DIGEST: message padding and message digest calculation at the end of a DMA transfer @@ -196,9 +193,9 @@ void hau_multiple_single_dma_config(uint32_t multi_single) HAU_CTL &= ~HAU_CTL_MDS; HAU_CTL |= multi_single; } - + /*! - \brief enable the HAU DMA interface + \brief enable the HAU DMA interface \param[in] none \param[out] none \retval none @@ -209,7 +206,7 @@ void hau_dma_enable(void) } /*! - \brief disable the HAU DMA interface + \brief disable the HAU DMA interface \param[in] none \param[out] none \retval none @@ -223,7 +220,7 @@ void hau_dma_disable(void) \brief get the HAU flag status \param[in] flag: HAU flag status only one parameter can be selected which is shown as below - \arg HAU_FLAG_DATA_INPUT: there is enough space (16 bytes) in the input FIFO + \arg HAU_FLAG_DATA_INPUT: there is enough space (16 bytes) in the input FIFO \arg HAU_FLAG_CALCULATION_COMPLETE: digest calculation is completed \arg HAU_FLAG_DMA: DMA is enabled (DMAE =1) or a transfer is processing \arg HAU_FLAG_BUSY: data block is in process @@ -237,13 +234,13 @@ FlagStatus hau_flag_get(uint32_t flag) FlagStatus ret_flag = RESET; /* check if the flag is in HAU_CTL register */ - if(RESET != (flag & HAU_FLAG_INFIFO_NO_EMPTY)){ + if(RESET != (flag & HAU_FLAG_INFIFO_NO_EMPTY)) { ret = HAU_CTL; - }else{ + } else { ret = HAU_STAT; } - if (RESET != (ret & flag)){ + if(RESET != (ret & flag)) { ret_flag = SET; } @@ -254,7 +251,7 @@ FlagStatus hau_flag_get(uint32_t flag) \brief clear the HAU flag status \param[in] flag: HAU flag status one or more parameters can be selected which are shown as below - \arg HAU_FLAG_DATA_INPUT: there is enough space (16 bytes) in the input FIFO + \arg HAU_FLAG_DATA_INPUT: there is enough space (16 bytes) in the input FIFO \arg HAU_FLAG_CALCULATION_COMPLETE: digest calculation is completed \param[out] none \retval none @@ -268,7 +265,7 @@ void hau_flag_clear(uint32_t flag) \brief enable the HAU interrupts \param[in] interrupt: specify the HAU interrupt source to be enabled one or more parameters can be selected which are shown as below - \arg HAU_INT_DATA_INPUT: a new block can be entered into the IN buffer + \arg HAU_INT_DATA_INPUT: a new block can be entered into the IN buffer \arg HAU_INT_CALCULATION_COMPLETE: calculation complete \param[out] none \retval none @@ -282,7 +279,7 @@ void hau_interrupt_enable(uint32_t interrupt) \brief disable the HAU interrupts \param[in] interrupt: specify the HAU interrupt source to be disabled one or more parameters can be selected which are shown as below - \arg HAU_INT_DATA_INPUT: a new block can be entered into the IN buffer + \arg HAU_INT_DATA_INPUT: a new block can be entered into the IN buffer \arg HAU_INT_CALCULATION_COMPLETE: calculation complete \param[out] none \retval none @@ -296,7 +293,7 @@ void hau_interrupt_disable(uint32_t interrupt) \brief get the HAU interrupt flag status \param[in] int_flag: HAU interrupt flag status only one parameter can be selected which is shown as below - \arg HAU_INT_FLAG_DATA_INPUT: there is enough space (16 bytes) in the input FIFO + \arg HAU_INT_FLAG_DATA_INPUT: there is enough space (16 bytes) in the input FIFO \arg HAU_INT_FLAG_CALCULATION_COMPLETE: digest calculation is completed \param[out] none \retval FlagStatus: SET or RESET @@ -309,10 +306,10 @@ FlagStatus hau_interrupt_flag_get(uint32_t int_flag) /* return the status of the interrupt */ ret = HAU_STAT; - if(RESET != ((HAU_INTEN & ret) & int_flag)){ + if(RESET != ((HAU_INTEN & ret) & int_flag)) { flag = SET; } - + return flag; } @@ -320,7 +317,7 @@ FlagStatus hau_interrupt_flag_get(uint32_t int_flag) \brief clear the HAU interrupt flag status \param[in] int_flag: HAU interrupt flag status one or more parameters can be selected which are shown as below - \arg HAU_INT_FLAG_DATA_INPUT: there is enough space (16 bytes) in the input FIFO + \arg HAU_INT_FLAG_DATA_INPUT: there is enough space (16 bytes) in the input FIFO \arg HAU_INT_FLAG_CALCULATION_COMPLETE: digest calculation is completed \param[out] none \retval none diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_hau_sha_md5.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_hau_sha_md5.c index a486f9b6..4b456d66 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_hau_sha_md5.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_hau_sha_md5.c @@ -2,36 +2,33 @@ \file gd32f20x_hau_sha_md5.c \brief HAU_SHA_MD5 driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -42,15 +39,15 @@ OF SUCH DAMAGE. /* HAU SHA/MD5 digest read in HASH mode */ static void hau_sha_md5_digest_read(uint32_t algo, uint8_t *output); /* HAU digest calculate process in HASH mode */ -static ErrStatus hau_hash_calculate(uint32_t algo, uint8_t *input, uint32_t in_length, uint8_t *output); +static ErrStatus hau_hash_calculate(uint32_t algo, uint8_t *input, uint32_t in_length, uint8_t *output); /* HAU digest calculate process in HMAC mode */ static ErrStatus hau_hmac_calculate(uint32_t algo, uint8_t *key, uint32_t keysize, uint8_t *input, uint32_t in_length, uint8_t *output); /*! - \brief calculate digest using SHA1 in HASH mode - \param[in] input: pointer to the input buffer - \param[in] in_length: length of the input buffer - \param[in] output: the result digest + \brief calculate digest using SHA1 in HASH mode + \param[in] input: pointer to the input buffer + \param[in] in_length: length of the input buffer + \param[in] output: the result digest \param[out] none \retval ErrStatus: SUCCESS or ERROR */ @@ -64,10 +61,10 @@ ErrStatus hau_hash_sha_1(uint8_t *input, uint32_t in_length, uint8_t output[20]) /*! \brief calculate digest using SHA1 in HMAC mode \param[in] key: pointer to the key used for HMAC - \param[in] keysize: length of the key used for HMAC - \param[in] input: pointer to the input buffer - \param[in] in_length: length of the input buffer - \param[in] output: the result digest + \param[in] keysize: length of the key used for HMAC + \param[in] input: pointer to the input buffer + \param[in] in_length: length of the input buffer + \param[in] output: the result digest \param[out] none \retval ErrStatus: SUCCESS or ERROR */ @@ -80,9 +77,9 @@ ErrStatus hau_hmac_sha_1(uint8_t *key, uint32_t keysize, uint8_t *input, uint32_ /*! \brief calculate digest using SHA224 in HASH mode - \param[in] input: pointer to the input buffer - \param[in] in_length: length of the input buffer - \param[in] output: the result digest + \param[in] input: pointer to the input buffer + \param[in] in_length: length of the input buffer + \param[in] output: the result digest \param[out] none \retval ErrStatus: SUCCESS or ERROR */ @@ -96,10 +93,10 @@ ErrStatus hau_hash_sha_224(uint8_t *input, uint32_t in_length, uint8_t output[28 /*! \brief calculate digest using SHA224 in HMAC mode \param[in] key: pointer to the key used for HMAC - \param[in] keysize: length of the key used for HMAC - \param[in] input: pointer to the input buffer - \param[in] in_length: length of the input buffer - \param[in] output: the result digest + \param[in] keysize: length of the key used for HMAC + \param[in] input: pointer to the input buffer + \param[in] in_length: length of the input buffer + \param[in] output: the result digest \param[out] none \retval ErrStatus: SUCCESS or ERROR */ @@ -112,9 +109,9 @@ ErrStatus hau_hmac_sha_224(uint8_t *key, uint32_t keysize, uint8_t *input, uint3 /*! \brief calculate digest using SHA256 in HASH mode - \param[in] input: pointer to the input buffer - \param[in] in_length: length of the input buffer - \param[in] output: the result digest + \param[in] input: pointer to the input buffer + \param[in] in_length: length of the input buffer + \param[in] output: the result digest \param[out] none \retval ErrStatus: SUCCESS or ERROR */ @@ -128,10 +125,10 @@ ErrStatus hau_hash_sha_256(uint8_t *input, uint32_t in_length, uint8_t output[32 /*! \brief calculate digest using SHA256 in HMAC mode \param[in] key: pointer to the key used for HMAC - \param[in] keysize: length of the key used for HMAC - \param[in] input: pointer to the input buffer - \param[in] in_length: length of the input buffer - \param[in] output: the result digest + \param[in] keysize: length of the key used for HMAC + \param[in] input: pointer to the input buffer + \param[in] in_length: length of the input buffer + \param[in] output: the result digest \param[out] none \retval ErrStatus: SUCCESS or ERROR */ @@ -139,14 +136,14 @@ ErrStatus hau_hmac_sha_256(uint8_t *key, uint32_t keysize, uint8_t *input, uint3 { ErrStatus ret = ERROR; ret = hau_hmac_calculate(HAU_ALGO_SHA256, key, keysize, input, in_length, output); - return ret; + return ret; } /*! - \brief calculate digest using MD5 in HASH mode - \param[in] input: pointer to the input buffer - \param[in] in_length: length of the input buffer - \param[in] output: the result digest + \brief calculate digest using MD5 in HASH mode + \param[in] input: pointer to the input buffer + \param[in] in_length: length of the input buffer + \param[in] output: the result digest \param[out] none \retval ErrStatus: SUCCESS or ERROR */ @@ -160,10 +157,10 @@ ErrStatus hau_hash_md5(uint8_t *input, uint32_t in_length, uint8_t output[16]) /*! \brief calculate digest using MD5 in HMAC mode \param[in] key: pointer to the key used for HMAC - \param[in] keysize: length of the key used for HMAC - \param[in] input: pointer to the input buffer - \param[in] in_length: length of the input buffer - \param[in] output: the result digest + \param[in] keysize: length of the key used for HMAC + \param[in] input: pointer to the input buffer + \param[in] in_length: length of the input buffer + \param[in] output: the result digest \param[out] none \retval ErrStatus: SUCCESS or ERROR */ @@ -176,72 +173,72 @@ ErrStatus hau_hmac_md5(uint8_t *key, uint32_t keysize, uint8_t *input, uint32_t /*! \brief HAU SHA/MD5 digest read - \param[in] algo: algorithm selection + \param[in] algo: algorithm selection \param[out] output: the result digest \retval none */ static void hau_sha_md5_digest_read(uint32_t algo, uint8_t *output) { hau_digest_parameter_struct digest_para; - uint32_t outputaddr = (uint32_t)output; - - switch(algo){ - case HAU_ALGO_SHA1: + uint32_t outputaddr = (uint32_t)output; + + switch(algo) { + case HAU_ALGO_SHA1: hau_digest_read(&digest_para); - *(uint32_t*)(outputaddr) = __REV(digest_para.out[0]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[0]); outputaddr += 4U; - *(uint32_t*)(outputaddr) = __REV(digest_para.out[1]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[1]); outputaddr += 4U; - *(uint32_t*)(outputaddr) = __REV(digest_para.out[2]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[2]); outputaddr += 4U; - *(uint32_t*)(outputaddr) = __REV(digest_para.out[3]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[3]); outputaddr += 4U; - *(uint32_t*)(outputaddr) = __REV(digest_para.out[4]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[4]); break; case HAU_ALGO_SHA224: hau_digest_read(&digest_para); - *(uint32_t*)(outputaddr) = __REV(digest_para.out[0]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[0]); outputaddr += 4U; - *(uint32_t*)(outputaddr) = __REV(digest_para.out[1]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[1]); outputaddr += 4U; - *(uint32_t*)(outputaddr) = __REV(digest_para.out[2]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[2]); outputaddr += 4U; - *(uint32_t*)(outputaddr) = __REV(digest_para.out[3]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[3]); outputaddr += 4U; - *(uint32_t*)(outputaddr) = __REV(digest_para.out[4]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[4]); outputaddr += 4U; - *(uint32_t*)(outputaddr) = __REV(digest_para.out[5]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[5]); outputaddr += 4U; - *(uint32_t*)(outputaddr) = __REV(digest_para.out[6]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[6]); break; case HAU_ALGO_SHA256: hau_digest_read(&digest_para); - *(uint32_t*)(outputaddr) = __REV(digest_para.out[0]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[0]); outputaddr += 4U; - *(uint32_t*)(outputaddr) = __REV(digest_para.out[1]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[1]); outputaddr += 4U; - *(uint32_t*)(outputaddr) = __REV(digest_para.out[2]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[2]); outputaddr += 4U; - *(uint32_t*)(outputaddr) = __REV(digest_para.out[3]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[3]); outputaddr += 4U; - *(uint32_t*)(outputaddr) = __REV(digest_para.out[4]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[4]); outputaddr += 4U; - *(uint32_t*)(outputaddr) = __REV(digest_para.out[5]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[5]); outputaddr += 4U; - *(uint32_t*)(outputaddr) = __REV(digest_para.out[6]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[6]); outputaddr += 4U; - *(uint32_t*)(outputaddr) = __REV(digest_para.out[7]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[7]); break; case HAU_ALGO_MD5: hau_digest_read(&digest_para); - *(uint32_t*)(outputaddr) = __REV(digest_para.out[0]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[0]); outputaddr += 4U; - *(uint32_t*)(outputaddr) = __REV(digest_para.out[1]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[1]); outputaddr += 4U; - *(uint32_t*)(outputaddr) = __REV(digest_para.out[2]); + *(uint32_t *)(outputaddr) = __REV(digest_para.out[2]); outputaddr += 4U; - *(uint32_t*)(outputaddr) = __REV(digest_para.out[3]); - break; + *(uint32_t *)(outputaddr) = __REV(digest_para.out[3]); + break; default: break; } @@ -250,16 +247,16 @@ static void hau_sha_md5_digest_read(uint32_t algo, uint8_t *output) /*! \brief HAU digest calculate process in HASH mode \param[in] algo: algorithm selection - \param[in] input: pointer to the input buffer - \param[in] in_length: length of the input buffer - \param[in] output: the result digest + \param[in] input: pointer to the input buffer + \param[in] in_length: length of the input buffer + \param[in] output: the result digest \param[out] none \retval ErrStatus: SUCCESS or ERROR */ static ErrStatus hau_hash_calculate(uint32_t algo, uint8_t *input, uint32_t in_length, uint8_t *output) { hau_init_parameter_struct init_para; - + __IO uint32_t num_last_valid = 0U; uint32_t i = 0U; __IO uint32_t counter = 0U; @@ -282,8 +279,8 @@ static ErrStatus hau_hash_calculate(uint32_t algo, uint8_t *input, uint32_t in_l hau_last_word_validbits_num_config(num_last_valid); /* write data to the IN FIFO */ - for(i = 0U; i < in_length; i += 4U){ - hau_data_write(*(uint32_t*)inputaddr); + for(i = 0U; i < in_length; i += 4U) { + hau_data_write(*(uint32_t *)inputaddr); inputaddr += 4U; } @@ -291,14 +288,14 @@ static ErrStatus hau_hash_calculate(uint32_t algo, uint8_t *input, uint32_t in_l hau_digest_calculation_enable(); /* wait until the busy flag is reset */ - do{ + do { busystatus = hau_flag_get(HAU_FLAG_BUSY); counter++; - }while((SHAMD5_BSY_TIMEOUT != counter) && (RESET != busystatus)); + } while((SHAMD5_BSY_TIMEOUT != counter) && (RESET != busystatus)); - if(RESET != busystatus){ + if(RESET != busystatus) { return ERROR; - }else{ + } else { /* read the message digest */ hau_sha_md5_digest_read(algo, output); } @@ -309,10 +306,10 @@ static ErrStatus hau_hash_calculate(uint32_t algo, uint8_t *input, uint32_t in_l \brief HAU digest calculate process in HMAC mode \param[in] algo: algorithm selection \param[in] key: pointer to the key used for HMAC - \param[in] keysize: length of the key used for HMAC - \param[in] input: pointer to the input buffer - \param[in] in_length: length of the input buffer - \param[in] output: the result digest + \param[in] keysize: length of the key used for HMAC + \param[in] input: pointer to the input buffer + \param[in] in_length: length of the input buffer + \param[in] output: the result digest \param[out] none \retval ErrStatus: SUCCESS or ERROR */ @@ -340,9 +337,9 @@ static ErrStatus hau_hmac_calculate(uint32_t algo, uint8_t *key, uint32_t keysiz init_para.algo = algo; init_para.mode = HAU_MODE_HMAC; init_para.datatype = HAU_SWAPPING_8BIT; - if(keysize > 64U){ + if(keysize > 64U) { init_para.keytype = HAU_KEY_LONGGER_64; - }else{ + } else { init_para.keytype = HAU_KEY_SHORTER_64; } hau_init(&init_para); @@ -351,8 +348,8 @@ static ErrStatus hau_hmac_calculate(uint32_t algo, uint8_t *key, uint32_t keysiz hau_last_word_validbits_num_config((uint32_t)num_key_valid); /* write the key */ - for(i = 0U; i < keysize; i += 4U){ - hau_data_write(*(uint32_t*)keyaddr); + for(i = 0U; i < keysize; i += 4U) { + hau_data_write(*(uint32_t *)keyaddr); keyaddr += 4U; } @@ -360,20 +357,20 @@ static ErrStatus hau_hmac_calculate(uint32_t algo, uint8_t *key, uint32_t keysiz hau_digest_calculation_enable(); /* wait until the busy flag is reset */ - do{ + do { busystatus = hau_flag_get(HAU_FLAG_BUSY); counter++; - }while((SHAMD5_BSY_TIMEOUT != counter) && (RESET != busystatus)); + } while((SHAMD5_BSY_TIMEOUT != counter) && (RESET != busystatus)); - if(RESET != busystatus){ + if(RESET != busystatus) { return ERROR; - }else{ + } else { /* configure the number of valid bits in last word of the message */ hau_last_word_validbits_num_config((uint32_t)num_last_valid); /* write data to the IN FIFO */ - for(i = 0U; i < in_length; i += 4U){ - hau_data_write(*(uint32_t*)inputaddr); + for(i = 0U; i < in_length; i += 4U) { + hau_data_write(*(uint32_t *)inputaddr); inputaddr += 4U; } @@ -382,21 +379,21 @@ static ErrStatus hau_hmac_calculate(uint32_t algo, uint8_t *key, uint32_t keysiz /* wait until the busy flag is reset */ counter = 0U; - do{ + do { busystatus = hau_flag_get(HAU_FLAG_BUSY); counter++; - }while((SHAMD5_BSY_TIMEOUT != counter) && (RESET != busystatus)); + } while((SHAMD5_BSY_TIMEOUT != counter) && (RESET != busystatus)); - if(RESET != busystatus){ + if(RESET != busystatus) { return ERROR; - }else{ + } else { /* configure the number of valid bits in last word of the key */ hau_last_word_validbits_num_config((uint32_t)num_key_valid); /* write the key */ keyaddr = (uint32_t)key; - for(i = 0U; i < keysize; i += 4U){ - hau_data_write(*(uint32_t*)keyaddr); + for(i = 0U; i < keysize; i += 4U) { + hau_data_write(*(uint32_t *)keyaddr); keyaddr += 4U; } @@ -404,19 +401,19 @@ static ErrStatus hau_hmac_calculate(uint32_t algo, uint8_t *key, uint32_t keysiz hau_digest_calculation_enable(); /* wait until the busy flag is reset */ - counter =0U; - do{ + counter = 0U; + do { busystatus = hau_flag_get(HAU_FLAG_BUSY); counter++; - }while((SHAMD5_BSY_TIMEOUT != counter) && (RESET != busystatus)); + } while((SHAMD5_BSY_TIMEOUT != counter) && (RESET != busystatus)); - if(RESET != busystatus){ + if(RESET != busystatus) { return ERROR; - }else{ + } else { /* read the message digest */ hau_sha_md5_digest_read(algo, output); } - } + } } - return SUCCESS; + return SUCCESS; } diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_i2c.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_i2c.c index 1911cd73..9947df63 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_i2c.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_i2c.c @@ -2,51 +2,47 @@ \file gd32f20x_i2c.c \brief I2C driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x - \version 2019-04-16, V2.1.1, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f20x_i2c.h" /* I2C register bit mask */ -#define I2CCLK_MAX ((uint32_t)0x0000003FU) /*!< i2cclk maximum value */ +#define I2CCLK_MAX ((uint32_t)0x0000003CU) /*!< i2cclk maximum value */ #define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ #define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ #define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ #define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */ /* I2C register bit offset */ -#define STAT1_PECV_OFFSET ((uint32_t)8U) /* bit offset of PECV in I2C_STAT1 */ +#define STAT1_PECV_OFFSET ((uint32_t)0x00000008U) /* bit offset of PECV in I2C_STAT1 */ /*! \brief reset I2C @@ -56,7 +52,7 @@ OF SUCH DAMAGE. */ void i2c_deinit(uint32_t i2c_periph) { - switch(i2c_periph){ + switch(i2c_periph) { case I2C0: /* reset I2C0 */ rcu_periph_reset_enable(RCU_I2C0RST); @@ -74,7 +70,6 @@ void i2c_deinit(uint32_t i2c_periph) break; default: break; - } } @@ -82,92 +77,92 @@ void i2c_deinit(uint32_t i2c_periph) \brief configure I2C clock \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) - and fast mode plus (up to 1MHz) - \param[in] dutycyc: duty cycle in fast mode or fast mode plus + \param[in] dutycyc: duty cycle in fast mode only one parameter can be selected which is shown as below: - \arg I2C_DTCY_2: T_low/T_high=2 - \arg I2C_DTCY_16_9: T_low/T_high=16/9 + \arg I2C_DTCY_2: T_low/T_high = 2 in fast mode + \arg I2C_DTCY_16_9: T_low/T_high = 16/9 in fast mode \param[out] none \retval none */ -void i2c_clock_config(uint32_t i2c_periph,uint32_t clkspeed,uint32_t dutycyc) +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) { - uint32_t pclk1,clkc,freq,risetime; + uint32_t pclk1, clkc, freq, risetime; uint32_t temp; - + pclk1 = rcu_clock_freq_get(CK_APB1); /* I2C peripheral clock frequency */ - freq = (uint32_t)(pclk1/1000000U); - if(freq >= I2CCLK_MAX){ + freq = (uint32_t)(pclk1 / 1000000U); + if(freq >= I2CCLK_MAX) { freq = I2CCLK_MAX; } temp = I2C_CTL1(i2c_periph); temp &= ~I2C_CTL1_I2CCLK; temp |= freq; - + I2C_CTL1(i2c_periph) = temp; - - if(100000U >= clkspeed){ + + if(100000U >= clkspeed) { /* the maximum SCL rise time is 1000ns in standard mode */ - risetime = (uint32_t)((pclk1/1000000U)+1U); - if(risetime >= I2CCLK_MAX){ + risetime = (uint32_t)((pclk1 / 1000000U) + 1U); + if(risetime >= I2CCLK_MAX) { I2C_RT(i2c_periph) = I2CCLK_MAX; - }else if(risetime <= I2CCLK_MIN){ + } else if(risetime <= I2CCLK_MIN) { I2C_RT(i2c_periph) = I2CCLK_MIN; - }else{ + } else { I2C_RT(i2c_periph) = risetime; } - clkc = (uint32_t)(pclk1/(clkspeed*2U)); - if(clkc < 0x04U){ - /* the CLKC in standard mode minmum value is 4 */ + clkc = (uint32_t)(pclk1 / (clkspeed * 2U)); + if(clkc < 0x04U) { + /* the CLKC in standard mode minimum value is 4 */ clkc = 0x04U; } + I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); - }else if(400000U >= clkspeed){ + } else if(400000U >= clkspeed) { /* the maximum SCL rise time is 300ns in fast mode */ - I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U); - if(I2C_DTCY_2 == dutycyc){ + I2C_RT(i2c_periph) = (uint32_t)(((freq * (uint32_t)300U) / (uint32_t)1000U) + (uint32_t)1U); + if(I2C_DTCY_2 == dutycyc) { /* I2C duty cycle is 2 */ - clkc = (uint32_t)(pclk1/(clkspeed*3U)); + clkc = (uint32_t)(pclk1 / (clkspeed * 3U)); I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; - }else{ + } else { /* I2C duty cycle is 16/9 */ - clkc = (uint32_t)(pclk1/(clkspeed*25U)); + clkc = (uint32_t)(pclk1 / (clkspeed * 25U)); I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; } - if(0U == (clkc & I2C_CKCFG_CLKC)){ - /* the CLKC in fast mode minmum value is 1 */ - clkc |= 0x0001U; + if(0U == (clkc & I2C_CKCFG_CLKC)) { + /* the CLKC in fast mode minimum value is 1 */ + clkc |= 0x0001U; } I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; I2C_CKCFG(i2c_periph) |= clkc; - }else{ + } else { } } /*! - \brief configure I2C address + \brief configure I2C address \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] mod: + \param[in] mode: only one parameter can be selected which is shown as below: - \arg I2C_I2CMODE_ENABLE: I2C mode + \arg I2C_I2CMODE_ENABLE: I2C mode \arg I2C_SMBUSMODE_ENABLE: SMBus mode \param[in] addformat: 7bits or 10bits only one parameter can be selected which is shown as below: - \arg I2C_ADDFORMAT_7BITS: 7bits - \arg I2C_ADDFORMAT_10BITS: 10bits + \arg I2C_ADDFORMAT_7BITS: address format is 7 bits + \arg I2C_ADDFORMAT_10BITS: address format is 10 bits \param[in] addr: I2C address \param[out] none \retval none */ -void i2c_mode_addr_config(uint32_t i2c_periph,uint32_t mode,uint32_t addformat,uint32_t addr) +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) { /* SMBus/I2C mode selected */ uint32_t ctl = 0U; - + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SMBEN); + ctl &= ~(I2C_CTL0_SMBEN); ctl |= mode; I2C_CTL0(i2c_periph) = ctl; /* configure address */ @@ -176,20 +171,20 @@ void i2c_mode_addr_config(uint32_t i2c_periph,uint32_t mode,uint32_t addformat,u } /*! - \brief SMBus type selection + \brief select SMBus type \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] type: only one parameter can be selected which is shown as below: - \arg I2C_SMBUS_DEVICE: device - \arg I2C_SMBUS_HOST: host + \arg I2C_SMBUS_DEVICE: SMBus mode device type + \arg I2C_SMBUS_HOST: SMBus mode host type \param[out] none \retval none */ void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) { - if(I2C_SMBUS_HOST == type){ + if(I2C_SMBUS_HOST == type) { I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; - }else{ + } else { I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); } } @@ -206,11 +201,12 @@ void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) */ void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) { - if(I2C_ACK_ENABLE == ack){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); - } + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_ACKEN); + ctl |= ack; + I2C_CTL0(i2c_periph) = ctl; } /*! @@ -218,38 +214,38 @@ void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] pos: only one parameter can be selected which is shown as below: - \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current - \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte + \arg I2C_ACKPOS_CURRENT: ACKEN bit decides whether or not to send ACK or not for the current byte + \arg I2C_ACKPOS_NEXT: ACKEN bit decides whether or not to send ACK for the next byte \param[out] none \retval none */ void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) { + uint32_t ctl = 0U; /* configure I2C POAP position */ - if(I2C_ACKPOS_NEXT == pos){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); - } + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_POAP); + ctl |= pos; + I2C_CTL0(i2c_periph) = ctl; } /*! \brief master sends slave address \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] addr: slave address + \param[in] addr: slave address \param[in] trandirection: transmitter or receiver only one parameter can be selected which is shown as below: - \arg I2C_TRANSMITTER: transmitter - \arg I2C_RECEIVER: receiver + \arg I2C_TRANSMITTER: transmitter + \arg I2C_RECEIVER: receiver \param[out] none \retval none */ void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) { /* master is a transmitter or a receiver */ - if(I2C_TRANSMITTER == trandirection){ + if(I2C_TRANSMITTER == trandirection) { addr = addr & I2C_TRANSMITTER; - }else{ + } else { addr = addr | I2C_RECEIVER; } /* send slave address */ @@ -272,7 +268,7 @@ void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr) /*! \brief disable dual-address mode - \param[in] i2c_periph: I2Cx(x=0,1,2) + \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none */ @@ -283,7 +279,7 @@ void i2c_dualaddr_disable(uint32_t i2c_periph) /*! \brief enable I2C - \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none */ @@ -294,7 +290,7 @@ void i2c_enable(uint32_t i2c_periph) /*! \brief disable I2C - \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval none */ @@ -328,7 +324,7 @@ void i2c_stop_on_bus(uint32_t i2c_periph) /*! \brief I2C transmit data function \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] data: data of transmission + \param[in] data: data of transmission \param[out] none \retval none */ @@ -349,20 +345,20 @@ uint8_t i2c_data_receive(uint32_t i2c_periph) } /*! - \brief enable I2C DMA mode + \brief configure I2C DMA mode \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] dmastate: only one parameter can be selected which is shown as below: - \arg I2C_DMA_ON: DMA mode enable - \arg I2C_DMA_OFF: DMA mode disable + \arg I2C_DMA_ON: enable DMA mode + \arg I2C_DMA_OFF: disable DMA mode \param[out] none \retval none */ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) +void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate) { /* configure I2C DMA function */ uint32_t ctl = 0U; - + ctl = I2C_CTL1(i2c_periph); ctl &= ~(I2C_CTL1_DMAON); ctl |= dmastate; @@ -372,7 +368,7 @@ void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) /*! \brief configure whether next DMA EOT is DMA last transfer or not \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] dmalast: + \param[in] dmalast: only one parameter can be selected which is shown as below: \arg I2C_DMALST_ON: next DMA EOT is the last transfer \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer @@ -383,7 +379,7 @@ void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) { /* configure DMA last transfer */ uint32_t ctl = 0U; - + ctl = I2C_CTL1(i2c_periph); ctl &= ~(I2C_CTL1_DMALST); ctl |= dmalast; @@ -391,28 +387,28 @@ void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) } /*! - \brief whether to stretch SCL low when data is not ready in slave mode + \brief whether to stretch SCL low when data is not ready in slave mode \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] stretchpara: only one parameter can be selected which is shown as below: - \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled - \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled + \arg I2C_SCLSTRETCH_ENABLE: enable SCL stretching + \arg I2C_SCLSTRETCH_DISABLE: disable SCL stretching \param[out] none \retval none */ void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) { - /* configure I2C SCL strerching enable or disable */ + /* configure I2C SCL strerching */ uint32_t ctl = 0U; - + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_DISSTRC); + ctl &= ~(I2C_CTL0_SS); ctl |= stretchpara; I2C_CTL0(i2c_periph) = ctl; } /*! - \brief whether or not to response to a general call + \brief whether or not to response to a general call \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] gcallpara: only one parameter can be selected which is shown as below: @@ -425,15 +421,15 @@ void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) { /* configure slave response to a general call enable or disable */ uint32_t ctl = 0U; - + ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_GCEN); + ctl &= ~(I2C_CTL0_GCEN); ctl |= gcallpara; I2C_CTL0(i2c_periph) = ctl; } /*! - \brief software reset I2C + \brief configure software reset of I2C \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] sreset: only one parameter can be selected which is shown as below: @@ -454,16 +450,16 @@ void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) } /*! - \brief I2C PEC calculation on or off + \brief configure I2C PEC calculation \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] pecpara: + \param[in] pecstate: only one parameter can be selected which is shown as below: - \arg I2C_PEC_ENABLE: PEC calculation on - \arg I2C_PEC_DISABLE: PEC calculation off + \arg I2C_PEC_ENABLE: PEC calculation on + \arg I2C_PEC_DISABLE: PEC calculation off \param[out] none \retval none */ -void i2c_pec_enable(uint32_t i2c_periph,uint32_t pecstate) +void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate) { /* on/off PEC calculation */ uint32_t ctl = 0U; @@ -475,19 +471,20 @@ void i2c_pec_enable(uint32_t i2c_periph,uint32_t pecstate) } /*! - \brief I2C whether to transfer PEC value + \brief configure whether to transfer PEC value \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] pecpara: only one parameter can be selected which is shown as below: - \arg I2C_PECTRANS_ENABLE: transfer PEC - \arg I2C_PECTRANS_DISABLE: not transfer PEC + \arg I2C_PECTRANS_ENABLE: transfer PEC value + \arg I2C_PECTRANS_DISABLE: not transfer PEC value \param[out] none \retval none */ -void i2c_pec_transfer_enable(uint32_t i2c_periph,uint32_t pecpara) +void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara) { /* whether to transfer PEC */ uint32_t ctl = 0U; + ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_PECTRANS); ctl |= pecpara; @@ -495,31 +492,31 @@ void i2c_pec_transfer_enable(uint32_t i2c_periph,uint32_t pecpara) } /*! - \brief get packet error checking value + \brief get packet error checking value \param[in] i2c_periph: I2Cx(x=0,1,2) \param[out] none \retval PEC value */ uint8_t i2c_pec_value_get(uint32_t i2c_periph) { - return (uint8_t)((I2C_STAT1(i2c_periph) &I2C_STAT1_ECV) >> STAT1_PECV_OFFSET); + return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV) >> STAT1_PECV_OFFSET); } /*! - \brief I2C issue alert through SMBA pin + \brief configure I2C alert through SMBA pin \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] smbuspara: only one parameter can be selected which is shown as below: - \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin - \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin + \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin + \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin \param[out] none \retval none */ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) +void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara) { - /* issue alert through SMBA pin configure*/ + /* configure smbus alert through SMBA pin */ uint32_t ctl = 0U; - + ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_SALT); ctl |= smbuspara; @@ -527,7 +524,7 @@ void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) } /*! - \brief enable or disable I2C ARP protocol in SMBus switch + \brief configure I2C ARP protocol in SMBus \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] arpstate: only one parameter can be selected which is shown as below: @@ -536,11 +533,11 @@ void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) \param[out] none \retval none */ -void i2c_smbus_arp_enable(uint32_t i2c_periph,uint32_t arpstate) +void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate) { /* enable or disable I2C ARP protocol*/ uint32_t ctl = 0U; - + ctl = I2C_CTL0(i2c_periph); ctl &= ~(I2C_CTL0_ARPEN); ctl |= arpstate; @@ -552,23 +549,23 @@ void i2c_smbus_arp_enable(uint32_t i2c_periph,uint32_t arpstate) \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] flag: I2C flags, refer to i2c_flag_enum only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SBSEND: start condition send out + \arg I2C_FLAG_SBSEND: start condition sent out in master mode \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode \arg I2C_FLAG_BTC: byte transmission finishes \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode \arg I2C_FLAG_STPDET: stop condition detected in slave mode - \arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving + \arg I2C_FLAG_RBNE: I2C_DATA is not empty during receiving \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus \arg I2C_FLAG_LOSTARB: arbitration lost in master mode \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode + \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode \arg I2C_FLAG_PECERR: PEC error when receiving data \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode \arg I2C_FLAG_SMBALT: SMBus alert status \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode \arg I2C_FLAG_I2CBSY: busy flag - \arg I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver + \arg I2C_FLAG_TR: whether the I2C is a transmitter or a receiver \arg I2C_FLAG_RXGC: general call address (00h) received \arg I2C_FLAG_DEFSMB: default address of SMBus device \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode @@ -578,36 +575,36 @@ void i2c_smbus_arp_enable(uint32_t i2c_periph,uint32_t arpstate) */ FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) { - if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))){ + if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear I2C flag + \brief clear I2C flag status \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] flag: I2C flags, refer to i2c_flag_enum only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SMBALT: SMBus Alert status + \arg I2C_FLAG_SMBALT: SMBus alert status \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode \arg I2C_FLAG_PECERR: PEC error when receiving data - \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode + \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_BERR: a bus error - \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus + \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode \param[out] none \retval none */ void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) { - if(I2C_FLAG_ADDSEND == flag){ + if(I2C_FLAG_ADDSEND == flag) { /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ I2C_STAT0(i2c_periph); I2C_STAT1(i2c_periph); - }else{ + } else { I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); } } @@ -617,9 +614,9 @@ void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable + \arg I2C_INT_ERR: error interrupt + \arg I2C_INT_EV: event interrupt + \arg I2C_INT_BUF: buffer interrupt \param[out] none \retval none */ @@ -631,11 +628,11 @@ void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) /*! \brief disable I2C interrupt \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] interrupt: I2C interrupts, refer to i2c_flag_enum + \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable + \arg I2C_INT_ERR: error interrupt + \arg I2C_INT_EV: event interrupt + \arg I2C_INT_BUF: buffer interrupt \param[out] none \retval none */ @@ -645,15 +642,15 @@ void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) } /*! - \brief check I2C interrupt flag + \brief get I2C interrupt flag status \param[in] i2c_periph: I2Cx(x=0,1,2) \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum only one parameter can be selected which is shown as below: \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BTC: byte transmission finishes + \arg I2C_INT_FLAG_BTC: byte transmission finishes interrupt flag \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag - \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag + \arg I2C_INT_FLAG_STPDET: stop condition detected in slave mode interrupt flag \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag @@ -662,40 +659,40 @@ void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus alert status interrupt flag \param[out] none - \retval FlagStatus SET or RESET + \retval FlagStatus: SET or RESET */ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) { uint32_t intenable = 0U, flagstatus = 0U, bufie; - + /* check BUFIE */ bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; - + /* get the interrupt enable bit status */ intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); /* get the corresponding flag bit status */ flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); - if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)){ - if(intenable && bufie){ + if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)) { + if(intenable && bufie) { intenable = 1U; - }else{ + } else { intenable = 0U; } } - if((0U != flagstatus) && (0U != intenable)){ + if((0U != flagstatus) && (0U != intenable)) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear I2C interrupt flag + \brief clear I2C interrupt flag status \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] intflag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum only one parameter can be selected which is shown as below: \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag @@ -704,17 +701,17 @@ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum i \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus alert status interrupt flag \param[out] none \retval none */ void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) { - if(I2C_INT_FLAG_ADDSEND == int_flag){ + if(I2C_INT_FLAG_ADDSEND == int_flag) { /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ I2C_STAT0(i2c_periph); I2C_STAT1(i2c_periph); - }else{ + } else { I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); } } diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_misc.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_misc.c index 4a45def6..2f0fe097 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_misc.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_misc.c @@ -2,36 +2,33 @@ \file gd32f20x_misc.c \brief MISC driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -40,11 +37,11 @@ OF SUCH DAMAGE. /*! \brief set the priority group \param[in] nvic_prigroup: the NVIC priority group - \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority - \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority - \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority - \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority - \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority + \arg NVIC_PRIGROUP_PRE0_SUB4: 0 bits for pre-emption priority, 4 bits for subpriority + \arg NVIC_PRIGROUP_PRE1_SUB3: 1 bits for pre-emption priority, 3 bits for subpriority + \arg NVIC_PRIGROUP_PRE2_SUB2: 2 bits for pre-emption priority, 2 bits for subpriority + \arg NVIC_PRIGROUP_PRE3_SUB1: 3 bits for pre-emption priority, 1 bits for subpriority + \arg NVIC_PRIGROUP_PRE4_SUB0: 4 bits for pre-emption priority, 0 bits for subpriority \param[out] none \retval none */ @@ -55,21 +52,21 @@ void nvic_priority_group_set(uint32_t nvic_prigroup) } /*! - \brief enable NVIC request + \brief enable NVIC interrupt request \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set \param[in] nvic_irq_sub_priority: the subpriority needed to set \param[out] none \retval none */ -void nvic_irq_enable(uint8_t nvic_irq, - uint8_t nvic_irq_pre_priority, +void nvic_irq_enable(uint8_t nvic_irq, + uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority) { uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; /* use the priority group value to get the temp_pre and the temp_sub */ - switch ((SCB->AIRCR) & (uint32_t)0x700U) { + switch((SCB->AIRCR) & (uint32_t)0x700U) { case NVIC_PRIGROUP_PRE0_SUB4: temp_pre = 0U; temp_sub = 0x4U; @@ -99,7 +96,7 @@ void nvic_irq_enable(uint8_t nvic_irq, /* get the temp_priority to fill the NVIC->IP register */ temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); - temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub)); + temp_priority |= nvic_irq_sub_priority & (0x0FU >> (0x4U - temp_sub)); temp_priority = temp_priority << 0x04U; NVIC->IP[nvic_irq] = (uint8_t)temp_priority; @@ -108,7 +105,7 @@ void nvic_irq_enable(uint8_t nvic_irq, } /*! - \brief disable NVIC request + \brief disable NVIC interrupt request \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type \param[out] none \retval none @@ -124,22 +121,24 @@ void nvic_irq_disable(uint8_t nvic_irq) \param[in] nvic_vict_tab: the RAM or FLASH base address \arg NVIC_VECTTAB_RAM: RAM base address \are NVIC_VECTTAB_FLASH: Flash base address - \param[in] offset: Vector Table offset + \param[in] offset: vector table offset \param[out] none \retval none */ void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) { SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); + + __DSB(); } /*! \brief set the state of the low power mode \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power mode by exiting from ISR \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the low power mode can be woke up by all the enable and disable interrupts \param[out] none \retval none @@ -152,10 +151,10 @@ void system_lowpower_set(uint8_t lowpower_mode) /*! \brief reset the state of the low power mode \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power mode by exiting from ISR \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the low power mode only can be woke up by the enable interrupts \param[out] none \retval none @@ -176,10 +175,10 @@ void system_lowpower_reset(uint8_t lowpower_mode) void systick_clksource_set(uint32_t systick_clksource) { - if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){ + if(SYSTICK_CLKSOURCE_HCLK == systick_clksource) { /* set the systick clock source from HCLK */ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - }else{ + } else { /* set the systick clock source from HCLK/8 */ SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; } diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_pmu.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_pmu.c index f66e5fc5..e284d06a 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_pmu.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_pmu.c @@ -2,36 +2,33 @@ \file gd32f20x_pmu.c \brief PMU driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -90,7 +87,7 @@ void pmu_lvd_disable(void) } /*! - \brief PMU work at sleep mode + \brief PMU work in sleep mode \param[in] sleepmodecmd: only one parameter can be selected which is shown as below: \arg WFI_CMD: use WFI command @@ -102,98 +99,96 @@ void pmu_to_sleepmode(uint8_t sleepmodecmd) { /* clear sleepdeep bit of Cortex-M3 system control register */ SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - + /* select WFI or WFE command to enter sleep mode */ - if(WFI_CMD == sleepmodecmd){ + if(WFI_CMD == sleepmodecmd) { __WFI(); - }else{ + } else { __WFE(); } } /*! - \brief PMU work at deepsleep mode + \brief PMU work in deepsleep mode \param[in] ldo: only one parameter can be selected which is shown as below: \arg PMU_LDO_NORMAL: LDO work at normal power mode when pmu enter deepsleep mode \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode \param[in] deepsleepmodecmd: - only one parameter can be selected which is shown as below: + only one parameter can be selected which is shown as below: \arg WFI_CMD: use WFI command \arg WFE_CMD: use WFE command \param[out] none \retval none */ -void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) +void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd) { - static uint32_t reg_snap[ 4 ]; + static uint32_t reg_snap[4]; /* clear stbmod and ldolp bits */ PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); - + /* set ldolp bit according to pmu_ldo */ PMU_CTL |= ldo; - + /* set sleepdeep bit of Cortex-M3 system control register */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - reg_snap[ 0 ] = REG32( 0xE000E010U ); - reg_snap[ 1 ] = REG32( 0xE000E100U ); - reg_snap[ 2 ] = REG32( 0xE000E104U ); - reg_snap[ 3 ] = REG32( 0xE000E108U ); - - REG32( 0xE000E010U ) &= 0x00010004U; - REG32( 0xE000E180U ) = 0XFF7FF83DU; - REG32( 0xE000E184U ) = 0XBFFFF8FFU; - REG32( 0xE000E188U ) = 0xFFFFFFFFU; - + reg_snap[0] = REG32(0xE000E010U); + reg_snap[1] = REG32(0xE000E100U); + reg_snap[2] = REG32(0xE000E104U); + reg_snap[3] = REG32(0xE000E108U); + + REG32(0xE000E010U) &= 0x00010004U; + REG32(0xE000E180U) = 0XFF7FF83DU; + REG32(0xE000E184U) = 0XBFFFF8FFU; + REG32(0xE000E188U) = 0xFFFFFFFFU; + /* select WFI or WFE command to enter deepsleep mode */ - if(WFI_CMD == deepsleepmodecmd){ + if(WFI_CMD == deepsleepmodecmd) { __WFI(); - }else{ + } else { __SEV(); __WFE(); __WFE(); } - - REG32( 0xE000E010U ) = reg_snap[ 0 ] ; - REG32( 0xE000E100U ) = reg_snap[ 1 ] ; - REG32( 0xE000E104U ) = reg_snap[ 2 ] ; - REG32( 0xE000E108U ) = reg_snap[ 3 ] ; - + + REG32(0xE000E010U) = reg_snap[0] ; + REG32(0xE000E100U) = reg_snap[1] ; + REG32(0xE000E104U) = reg_snap[2] ; + REG32(0xE000E108U) = reg_snap[3] ; + /* reset sleepdeep bit of Cortex-M3 system control register */ SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); } /*! - \brief pmu work at standby mode - \param[in] standbymodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command + \brief pmu work in standby mode + \param[in] none \param[out] none \retval none */ -void pmu_to_standbymode(uint8_t standbymodecmd) +void pmu_to_standbymode(void) { - /* set sleepdeep bit of Cortex-M3 system control register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - /* set stbmod bit */ PMU_CTL |= PMU_CTL_STBMOD; - + /* reset wakeup flag */ PMU_CTL |= PMU_CTL_WURST; - + + /* set sleepdeep bit of Cortex-M3 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + REG32(0xE000E010U) &= 0x00010004U; + REG32(0xE000E180U) = 0XFFFFFFF7U; + REG32(0xE000E184U) = 0XFFFFFDFFU; + REG32(0xE000E188U) = 0xFFFFFFFFU; + /* select WFI or WFE command to enter standby mode */ - if(WFI_CMD == standbymodecmd){ - __WFI(); - }else{ - __WFE(); - } + __WFI(); } /*! - \brief enable wakeup pin + \brief enable PMU wakeup pin \param[in] none \param[out] none \retval none @@ -204,7 +199,7 @@ void pmu_wakeup_pin_enable(void) } /*! - \brief disable wakeup pin + \brief disable PMU wakeup pin \param[in] none \param[out] none \retval none @@ -248,25 +243,25 @@ void pmu_backup_write_disable(void) */ FlagStatus pmu_flag_get(uint32_t flag) { - if(PMU_CS & flag){ + if(PMU_CS & flag) { return SET; - }else{ + } else { return RESET; } } /*! \brief clear flag bit - \param[in] flag_reset: + \param[in] flag: only one parameter can be selected which is shown as below: \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag \arg PMU_FLAG_RESET_STANDBY: reset standby flag \param[out] none \retval none */ -void pmu_flag_clear(uint32_t flag_reset) +void pmu_flag_clear(uint32_t flag) { - switch(flag_reset){ + switch(flag) { case PMU_FLAG_RESET_WAKEUP: /* reset wakeup flag */ PMU_CTL |= PMU_CTL_WURST; diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_rcu.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_rcu.c index 69e3341c..3f7bc64e 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_rcu.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_rcu.c @@ -2,36 +2,33 @@ \file gd32f20x_rcu.c \brief RCU driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -58,16 +55,20 @@ void rcu_deinit(void) RCU_CTL |= RCU_CTL_IRC8MEN; rcu_osci_stab_wait(RCU_IRC8M); + RCU_CFG0 &= ~RCU_CFG0_SCS; + /* reset HXTALEN, CKMEN, PLLEN bits */ + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); + /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */ RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL); /* reset HXTALEN, CKMEN, PLLEN bits */ - RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN ); + RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); /* Reset HXTALBPS bit */ RCU_CTL &= ~(RCU_CTL_HXTALBPS); - + /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */ RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4); @@ -77,16 +78,16 @@ void rcu_deinit(void) /* reset CFG1 register */ RCU_CFG1 = 0x00000000U; - + /* reset INT register */ RCU_INT = 0x00FF0000U; - + /* reset CFG2 register */ RCU_CFG2 = 0x00000000U; - + /* reset PLLTCTL register */ - RCU_PLLTCTL &= (~RCU_PLLTCTL_PLLTEN); - + RCU_PLLTCTL &= (~RCU_PLLTCTL_PLLTEN); + /* reset PLLTINT register */ RCU_PLLTINT = 0x00400000U; @@ -217,7 +218,7 @@ void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) \arg RCU_CANxRST (x=0,1): reset CAN \arg RCU_PMURST: reset PMU \arg RCU_DACRST: reset DAC - \arg RCU_ADCRST (x=0,1,2): reset ADC + \arg RCU_ADCxRST (x=0,1,2): reset ADC \arg RCU_BKPIRST: reset BKPI \arg RCU_TLIRST: reset TLI \arg RCU_DCIRST: reset DCI @@ -249,7 +250,7 @@ void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) \arg RCU_CANxRST (x=0,1): reset CAN \arg RCU_PMURST: reset PMU \arg RCU_DACRST: reset DAC - \arg RCU_ADCRST (x=0,1,2): reset ADC + \arg RCU_ADCxRST (x=0,1,2): reset ADC \arg RCU_BKPIRST: reset BKPI \arg RCU_TLIRST: reset TLI \arg RCU_DCIRST: reset DCI @@ -299,7 +300,7 @@ void rcu_bkp_reset_disable(void) void rcu_system_clock_source_config(uint32_t ck_sys) { uint32_t reg; - + reg = RCU_CFG0; /* reset the SCS bits and set according to ck_sys */ reg &= ~RCU_CFG0_SCS; @@ -324,14 +325,14 @@ uint32_t rcu_system_clock_source_get(void) \brief configure the AHB clock prescaler selection \param[in] ck_ahb: AHB clock prescaler selection only one parameter can be selected which is shown as below: - \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 +\arg RCU_AHB_CKSYS_DIVx (x=1, 2, 4, 8, 16, 64, 128, 256, 512): select CK_SYS / x as CK_AHB \param[out] none \retval none */ void rcu_ahb_clock_config(uint32_t ck_ahb) { uint32_t reg; - + reg = RCU_CFG0; /* reset the AHBPSC bits and set according to ck_ahb */ @@ -354,7 +355,7 @@ void rcu_ahb_clock_config(uint32_t ck_ahb) void rcu_apb1_clock_config(uint32_t ck_apb1) { uint32_t reg; - + reg = RCU_CFG0; /* reset the APB1PSC and set according to ck_apb1 */ @@ -377,7 +378,7 @@ void rcu_apb1_clock_config(uint32_t ck_apb1) void rcu_apb2_clock_config(uint32_t ck_apb2) { uint32_t reg; - + reg = RCU_CFG0; /* reset the APB2PSC and set according to ck_apb2 */ @@ -398,7 +399,7 @@ void rcu_apb2_clock_config(uint32_t ck_apb2) \arg RCU_CKOUT0SRC_CKPLL2_DIV2: CK_PLL2/2 selected \arg RCU_CKOUT0SRC_EXT1: EXT1 selected \arg RCU_CKOUT0SRC_CKPLL2: PLL selected - \param[in] ckout0_div: CK_OUT0 divider + \param[in] ckout0_div: CK_OUT0 divider \arg RCU_CKOUT0_DIVx(x=1..64): CK_OUT0 is divided by x \param[out] none \retval none @@ -406,15 +407,15 @@ void rcu_apb2_clock_config(uint32_t ck_apb2) void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div) { uint32_t reg; - + reg = RCU_CFG0; - + /* set the CKOUT0SEL according to ckout0_src */ reg &= ~RCU_CFG0_CKOUT0SEL; RCU_CFG0 = (reg | ckout0_src); - + reg = RCU_CFG2; - + /* set the CKOUT0DIV according to ckout0_div */ reg &= ~RCU_CFG2_CKOUT0DIV; RCU_CFG2 = (reg | ckout0_div); @@ -433,7 +434,7 @@ void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div) \arg RCU_CKOUT1SRC_CKPLL2_DIV2: CK_PLL2/2 selected \arg RCU_CKOUT1SRC_EXT1: EXT1 selected \arg RCU_CKOUT1SRC_CKPLL2: PLL selected - \param[in] ckout1_div: CK_OUT1 divider + \param[in] ckout1_div: CK_OUT1 divider \arg RCU_CKOUT1_DIVx(x=1..64): CK_OUT1 is divided by x \param[out] none \retval none @@ -441,7 +442,7 @@ void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div) void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div) { uint32_t reg; - + reg = RCU_CFG2; /* set the CKOUT1SEL and CKOUT1DIV according to ckout1_src and ckout1_div */ reg &= ~(RCU_CFG2_CKOUT1SEL | RCU_CFG2_CKOUT1DIV); @@ -450,12 +451,12 @@ void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div) } /*! - \brief configure the main PLL clock + \brief configure the main PLL clock \param[in] pll_src: PLL clock source selection \arg RCU_PLLSRC_IRC8M_DIV2: IRC8M/2 clock selected as source clock of PLL \arg RCU_PLLSRC_HXTAL: HXTAL selected as source clock of PLL \param[in] pll_mul: PLL clock multiplication factor - \arg RCU_PLL_MULx (x = 2..14,16..32,6.5) + \arg RCU_PLL_MULx (x = 2..14,16..32,6.5): PLL clock * x \param[out] none \retval none */ @@ -480,14 +481,14 @@ void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) \arg RCU_PREDV0SRC_CKPLL1: CK_PLL1 selected as PREDV0 input source clock \param[in] predv0_div: PREDV0 division factor only one parameter can be selected which is shown as below: - \arg RCU_PREDV0_DIVx, x = 1..16 + \arg RCU_PREDV0_DIVx (x= 1..16): PREDV0 input source clock is divided x \param[out] none \retval none */ void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div) { uint32_t reg = 0U; - + reg = RCU_CFG1; /* reset PREDV0SEL and PREDV0 bits */ reg &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV0); @@ -501,14 +502,14 @@ void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div) \brief configure the PREDV1 division factor \param[in] predv1_div: PREDV1 division factor only one parameter can be selected which is shown as below: - \arg RCU_PREDV1_DIVx, x = 1..16 + \arg RCU_PREDV1_DIVx (x = 1..16): PREDV1 input source clock is divided x \param[out] none \retval none */ void rcu_predv1_config(uint32_t predv1_div) { uint32_t reg = 0U; - + reg = RCU_CFG1; /* reset the PREDV1 bits */ reg &= ~RCU_CFG1_PREDV1; @@ -519,10 +520,10 @@ void rcu_predv1_config(uint32_t predv1_div) } /*! - \brief configure the PLL1 clock + \brief configure the PLL1 clock \param[in] pll_mul: PLL clock multiplication factor only one parameter can be selected which is shown as below: - \arg RCU_PLL1_MULx (x = 8..16, 20) + \arg RCU_PLL1_MULx (x = 8..16, 20): PLL1 clock * x \param[out] none \retval none */ @@ -533,17 +534,17 @@ void rcu_pll1_config(uint32_t pll_mul) } /*! - \brief configure the PLL2 clock + \brief configure the PLL2 clock \param[in] pll_mul: PLL clock multiplication factor only one parameter can be selected which is shown as below: - \arg RCU_PLL2_MULx (x = 8..16, 20) + \arg RCU_PLL2_MULx (x = 8..16, 20): PLL2 clock * x \param[out] none \retval none */ void rcu_pll2_config(uint32_t pll_mul) { RCU_CFG1 &= ~RCU_CFG1_PLL2MF; - RCU_CFG1 |= pll_mul; + RCU_CFG1 |= pll_mul; } /*! @@ -568,22 +569,22 @@ void rcu_adc_clock_config(uint32_t adc_psc) reg0 &= ~(RCU_CFG0_ADCPSC_2 | RCU_CFG0_ADCPSC); /* set the ADC prescaler factor */ - switch(adc_psc){ - case RCU_CKADC_CKAPB2_DIV2: - case RCU_CKADC_CKAPB2_DIV4: - case RCU_CKADC_CKAPB2_DIV6: - case RCU_CKADC_CKAPB2_DIV8: - reg0 |= (adc_psc << 14); - break; - - case RCU_CKADC_CKAPB2_DIV12: - case RCU_CKADC_CKAPB2_DIV16: - adc_psc &= ~BIT(2); - reg0 |= (adc_psc << 14 | RCU_CFG0_ADCPSC_2); - break; - - default: - break; + switch(adc_psc) { + case RCU_CKADC_CKAPB2_DIV2: + case RCU_CKADC_CKAPB2_DIV4: + case RCU_CKADC_CKAPB2_DIV6: + case RCU_CKADC_CKAPB2_DIV8: + reg0 |= (adc_psc << 14); + break; + + case RCU_CKADC_CKAPB2_DIV12: + case RCU_CKADC_CKAPB2_DIV16: + adc_psc &= ~BIT(2); + reg0 |= (adc_psc << 14 | RCU_CFG0_ADCPSC_2); + break; + + default: + break; } /* set the register */ @@ -603,7 +604,7 @@ void rcu_adc_clock_config(uint32_t adc_psc) void rcu_usbfs_trng_clock_config(uint32_t usbfs_trng_psc) { uint32_t reg = 0U; - + reg = RCU_CFG0; /* configure the USBFS/TRNG prescaler factor */ @@ -611,7 +612,6 @@ void rcu_usbfs_trng_clock_config(uint32_t usbfs_trng_psc) RCU_CFG0 = (reg | usbfs_trng_psc); } - /*! \brief configure the RTC clock source selection \param[in] rtc_clock_source: RTC clock source selection @@ -626,8 +626,8 @@ void rcu_usbfs_trng_clock_config(uint32_t usbfs_trng_psc) void rcu_rtc_clock_config(uint32_t rtc_clock_source) { uint32_t reg; - - reg = RCU_BDCTL; + + reg = RCU_BDCTL; /* reset the RTCSRC bits and set according to rtc_clock_source */ reg &= ~RCU_BDCTL_RTCSRC; RCU_BDCTL = (reg | rtc_clock_source); @@ -645,8 +645,8 @@ void rcu_rtc_clock_config(uint32_t rtc_clock_source) void rcu_i2s1_clock_config(uint32_t i2s_clock_source) { uint32_t reg; - - reg = RCU_CFG1; + + reg = RCU_CFG1; /* reset the I2S1SEL bit and set according to i2s_clock_source */ reg &= ~RCU_CFG1_I2S1SEL; RCU_CFG1 = (reg | i2s_clock_source); @@ -664,140 +664,98 @@ void rcu_i2s1_clock_config(uint32_t i2s_clock_source) void rcu_i2s2_clock_config(uint32_t i2s_clock_source) { uint32_t reg; - - reg = RCU_CFG1; + + reg = RCU_CFG1; /* reset the I2S2SEL bit and set according to i2s_clock_source */ reg &= ~RCU_CFG1_I2S2SEL; RCU_CFG1 = (reg | i2s_clock_source); } /*! - \brief get the clock stabilization and periphral reset flags - \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag - \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag - \arg RCU_FLAG_PLLSTB: PLL stabilization flag - \arg RCU_FLAG_PLL1STB: PLL1 stabilization flag - \arg RCU_FLAG_PLL2STB: PLL2 stabilization flag - \arg RCU_FLAG_PLLTSTB: PLLT stabilization flag - \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag - \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag - \arg RCU_FLAG_EPRST: external PIN reset flag - \arg RCU_FLAG_PORRST: power reset flag - \arg RCU_FLAG_SWRST: software reset flag - \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag - \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag - \arg RCU_FLAG_LPRST: low-power reset flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rcu_flag_get(rcu_flag_enum flag) -{ - /* get the rcu flag */ - if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear all the reset flag - \param[in] none + \brief configure the PLLT clock selection + \param[in] pllt_src: PLLT clock source selection + \arg RCU_PLLTSRC_IRC8M: IRC8M selected as source clock of PLLT + \arg RCU_PLLTSRC_HXTAL: HXTAL selected as source clock of PLLT \param[out] none \retval none */ -void rcu_all_reset_flag_clear(void) +void rcu_pllt_config(uint32_t pllt_src) { - RCU_RSTSCK |= RCU_RSTSCK_RSTFC; + uint32_t reg = 0U; + + reg = RCU_PLLTCFG; + + /* reset the PLLT clock source bit PLLTSEL */ + reg &= ~RCU_PLLTCFG_PLLTSEL; + + RCU_PLLTCFG = (reg | pllt_src); } /*! - \brief get the clock stabilization and ckm interrupt flags - \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag - \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag - \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag - \arg RCU_INT_FLAG_PLL1STB: PLL1 stabilization interrupt flag - \arg RCU_INT_FLAG_PLL2STB: PLL2 stabilization interrupt flag - \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag - \arg RCU_INT_FLAG_PLLTSTB: PLLT stabilization interrupt flag + \brief configure the PLLT clock multiplication and division factors + \param[in] pllt_psc: the PLLT VCO input clock division factor + \arg this parameter should be selected between 2 and 63. And this parameter should + be selected correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz + \param[in] pllt_mul: he PLLT VCO output clock multiplication factor + \arg this parameter should be selected between 49 and 432 + \param[in] ppltr_psc: the PLLTR division factor + \arg this parameter should be selected between 2 and 7 \param[out] none - \retval FlagStatus: SET or RESET + \retval ErrStatus: SUCCESS or ERROR */ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) +ErrStatus rcu_pllt_vco_config(uint32_t pllt_psc, uint32_t pllt_mul, uint32_t ppltr_psc) { - /* get the rcu interrupt flag */ - if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ - return SET; - }else{ - return RESET; + uint32_t reg = 0U; + + /* check the function parameter */ + if((pllt_psc < 2U) || (pllt_psc > 63U)) { + return ERROR; + } else { } -} -/*! - \brief clear the interrupt flags - \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear - \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear - \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLL1STB_CLR: PLL1 stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLL2STB_CLR: PLL2 stabilization interrupt flag clear - \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear - \arg RCU_INT_FLAG_PLLTSTB_CLR: PLLT stabilization interrupt flag clear - \param[out] none - \retval none -*/ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) -{ - RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); -} + if((pllt_mul < 49U) || (pllt_mul > 432U)) { + return ERROR; + } else { + } -/*! - \brief enable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum - Only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable - \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable - \arg RCU_INT_PLLTSTB: PLLT stabilization interrupt enable - \param[out] none - \retval none -*/ -void rcu_interrupt_enable(rcu_int_enum stab_int) -{ - RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); + if((ppltr_psc < 2U) || (ppltr_psc > 7U)) { + return ERROR; + } else { + } + + reg = RCU_PLLTCFG; + + /* reset the PLLTRPSC bits, PLLTMF bits and PLLTPSC bits */ + reg &= ~(RCU_PLLTCFG_PLLTRPSC | RCU_PLLTCFG_PLLTMF | RCU_PLLTCFG_PLLTPSC); + + reg |= (PLLTCFG_PLLTPSC(pllt_psc) | PLLTCFG_PLLTMF(pllt_mul) | PLLTCFG_PLLTRPSC(ppltr_psc)); + + RCU_PLLTCFG = reg; + + return SUCCESS; } /*! - \brief disable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + \brief configure the TLI prescaler factor from PLLTR clock + \param[in] tli_psc: TLI prescaler factor only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable - \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable - \arg RCU_INT_PLLTSTB: PLLT stabilization interrupt enable + \arg RCU_CKTLI_CKPLLTR_DIV2: TLI prescaler select CK_PLLTR/2 + \arg RCU_CKTLI_CKPLLTR_DIV4: TLI prescaler select CK_PLLTR/4 + \arg RCU_CKTLI_CKPLLTR_DIV8: TLI prescaler select CK_PLLTR/8 + \arg RCU_CKTLI_CKPLLTR_DIV16: TLI prescaler select CK_PLLTR/16 \param[out] none \retval none */ -void rcu_interrupt_disable(rcu_int_enum stab_int) +void rcu_tli_clock_config(uint32_t tli_psc) { - RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); + uint32_t reg = 0U; + + reg = RCU_PLLTCFG; + + /* reset the TLIPSC bits */ + reg &= ~RCU_PLLTCFG_TLIPSC; + + RCU_PLLTCFG = (reg | tli_psc); } /*! @@ -814,9 +772,9 @@ void rcu_interrupt_disable(rcu_int_enum stab_int) void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap) { uint32_t reg; - + reg = RCU_BDCTL; - + /* reset the LXTALDRI bits and set according to lxtal_dricap */ reg &= ~RCU_BDCTL_LXTALDRI; RCU_BDCTL = (reg | lxtal_dricap); @@ -842,112 +800,112 @@ ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) uint32_t stb_cnt = 0U; ErrStatus reval = ERROR; FlagStatus osci_stat = RESET; - - switch(osci){ + + switch(osci) { /* wait HXTAL stable */ case RCU_HXTAL: - while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); stb_cnt++; } /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)) { reval = SUCCESS; } break; /* wait LXTAL stable */ case RCU_LXTAL: - while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); stb_cnt++; } /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)) { reval = SUCCESS; } break; /* wait IRC8M stable */ case RCU_IRC8M: - while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); stb_cnt++; } /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)) { reval = SUCCESS; } break; /* wait IRC40K stable */ case RCU_IRC40K: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); stb_cnt++; } /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)) { reval = SUCCESS; } break; /* wait PLL stable */ case RCU_PLL_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); stb_cnt++; } /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)) { reval = SUCCESS; } break; /* wait PLL1 stable */ case RCU_PLL1_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB); stb_cnt++; } /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB)){ + if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB)) { reval = SUCCESS; } break; - + /* wait PLL2 stable */ case RCU_PLL2_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB); stb_cnt++; } /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB)){ + if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB)) { reval = SUCCESS; } break; /* wait PLLT stable */ case RCU_PLLT_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { osci_stat = rcu_flag_get(RCU_FLAG_PLLTSTB); stb_cnt++; } /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_PLLTSTB)){ + if(RESET != rcu_flag_get(RCU_FLAG_PLLTSTB)) { reval = SUCCESS; } break; - + default: break; } @@ -1009,7 +967,7 @@ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) { uint32_t reg; - switch(osci){ + switch(osci) { /* enable HXTAL to bypass mode */ case RCU_HXTAL: reg = RCU_CTL; @@ -1046,8 +1004,8 @@ void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) { uint32_t reg; - - switch(osci){ + + switch(osci) { /* disable HXTAL to bypass mode */ case RCU_HXTAL: reg = RCU_CTL; @@ -1078,7 +1036,6 @@ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) \param[out] none \retval none */ - void rcu_hxtal_clock_monitor_enable(void) { RCU_CTL |= RCU_CTL_CKMEN; @@ -1104,7 +1061,7 @@ void rcu_hxtal_clock_monitor_disable(void) void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval) { uint32_t reg; - + reg = RCU_CTL; /* reset the IRC8MADJ bits and set according to irc8m_adjval */ reg &= ~RCU_CTL_IRC8MADJ; @@ -1123,7 +1080,7 @@ void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval) \retval none */ void rcu_deepsleep_voltage_set(uint32_t dsvol) -{ +{ dsvol &= RCU_DSV_DSLPVS; RCU_DSV = dsvol; } @@ -1143,7 +1100,7 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) { uint32_t sws, ck_freq = 0U; uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; - uint32_t pllsel, predv0sel, pllmf,ck_src, idx, clk_exp; + uint32_t pllsel, predv0sel, pllmf, ck_src, idx, clk_exp; uint32_t predv0, predv1, pll1mf; /* exponent of AHB, APB1 and APB2 clock divider */ @@ -1152,7 +1109,7 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; sws = GET_BITS(RCU_CFG0, 2, 3); - switch(sws){ + switch(sws) { /* IRC8M is selected as CK_SYS */ case SEL_IRC8M: cksys_freq = IRC8M_VALUE; @@ -1169,41 +1126,41 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) if(RCU_PLLSRC_HXTAL == pllsel) { /* PLL clock source is HXTAL */ ck_src = HXTAL_VALUE; - + predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); /* source clock use PLL1 */ - if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ + if(RCU_PREDV0SRC_CKPLL1 == predv0sel) { predv1 = (uint32_t)((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; - if(17U == pll1mf){ + if(17U == pll1mf) { pll1mf = 20U; } - ck_src = (ck_src/predv1)*pll1mf; + ck_src = (ck_src / predv1) * pll1mf; } predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; ck_src /= predv0; - }else{ + } else { /* PLL clock source is IRC8M/2 */ - ck_src = IRC8M_VALUE/2U; + ck_src = IRC8M_VALUE / 2U; } /* PLL multiplication factor */ pllmf = GET_BITS(RCU_CFG0, 18, 21); - if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ + if((RCU_CFG0 & RCU_CFG0_PLLMF_4)) { pllmf |= 0x10U; } - if(13U == pllmf){ + if(13U == pllmf) { /* PLL source clock multiply by 6.5 */ - cksys_freq = ck_src*6U + ck_src/2U; - }else{ - if(pllmf < 15U){ + cksys_freq = ck_src * 6U + ck_src / 2U; + } else { + if(pllmf < 15U) { pllmf += 2U; - }else{ + } else { pllmf += 1U; } - cksys_freq = ck_src*pllmf; + cksys_freq = ck_src * pllmf; } break; /* IRC8M is selected as CK_SYS */ @@ -1216,19 +1173,19 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) idx = GET_BITS(RCU_CFG0, 4, 7); clk_exp = ahb_exp[idx]; ahb_freq = cksys_freq >> clk_exp; - + /* calculate APB1 clock frequency */ idx = GET_BITS(RCU_CFG0, 8, 10); clk_exp = apb1_exp[idx]; apb1_freq = ahb_freq >> clk_exp; - + /* calculate APB2 clock frequency */ idx = GET_BITS(RCU_CFG0, 11, 13); clk_exp = apb2_exp[idx]; apb2_freq = ahb_freq >> clk_exp; - + /* return the clocks frequency */ - switch(clock){ + switch(clock) { case CK_SYS: ck_freq = cksys_freq; break; @@ -1248,89 +1205,130 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) } /*! - \brief configure the PLLT clock selection - \param[in] pllt_src: PLLT clock source selection - \arg RCU_PLLTSRC_IRC8M: IRC8M selected as source clock of PLLT - \arg RCU_PLLTSRC_HXTAL: HXTAL selected as source clock of PLLT + \brief get the clock stabilization and periphral reset flags + \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag + \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag + \arg RCU_FLAG_PLLSTB: PLL stabilization flag + \arg RCU_FLAG_PLL1STB: PLL1 stabilization flag + \arg RCU_FLAG_PLL2STB: PLL2 stabilization flag + \arg RCU_FLAG_PLLTSTB: PLLT stabilization flag + \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag + \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag + \arg RCU_FLAG_EPRST: external PIN reset flag + \arg RCU_FLAG_PORRST: power reset flag + \arg RCU_FLAG_SWRST: software reset flag + \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag + \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag + \arg RCU_FLAG_LPRST: low-power reset flag \param[out] none - \retval none + \retval FlagStatus: SET or RESET */ -void rcu_pllt_config(uint32_t pllt_src) +FlagStatus rcu_flag_get(rcu_flag_enum flag) { - uint32_t reg = 0U; + /* get the rcu flag */ + if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} - reg = RCU_PLLTCFG; +/*! + \brief clear all the reset flag + \param[in] none + \param[out] none + \retval none +*/ +void rcu_all_reset_flag_clear(void) +{ + RCU_RSTSCK |= RCU_RSTSCK_RSTFC; +} - /* reset the PLLT clock source bit PLLTSEL */ - reg &= ~RCU_PLLTCFG_PLLTSEL; +/*! + \brief enable the stabilization interrupt + \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + Only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable + \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable + \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable + \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable + \arg RCU_INT_PLLTSTB: PLLT stabilization interrupt enable + \param[out] none + \retval none +*/ +void rcu_interrupt_enable(rcu_int_enum stab_int) +{ + RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); +} - RCU_PLLTCFG = (reg | pllt_src); +/*! + \brief disable the stabilization interrupt + \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable + \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable + \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable + \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable + \arg RCU_INT_PLLTSTB: PLLT stabilization interrupt enable + \param[out] none + \retval none +*/ +void rcu_interrupt_disable(rcu_int_enum stab_int) +{ + RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); } /*! - \brief configure the PLLT clock multiplication and division factors - \param[in] pllt_psc: the PLLT VCO input clock division factor - \arg this parameter should be selected between 2 and 63. And this parameter should - be selected correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz - \param[in] pllt_mul: he PLLT VCO output clock multiplication factor - \arg this parameter should be selected between 49 and 432 - \param[in] ppltr_psc: the PLLTR division factor - \arg this parameter should be selected between 2 and 7 + \brief get the clock stabilization and ckm interrupt flags + \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag + \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag + \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag + \arg RCU_INT_FLAG_PLL1STB: PLL1 stabilization interrupt flag + \arg RCU_INT_FLAG_PLL2STB: PLL2 stabilization interrupt flag + \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag + \arg RCU_INT_FLAG_PLLTSTB: PLLT stabilization interrupt flag \param[out] none - \retval ErrStatus: SUCCESS or ERROR + \retval FlagStatus: SET or RESET */ -ErrStatus rcu_pllt_vco_config(uint32_t pllt_psc, uint32_t pllt_mul, uint32_t ppltr_psc) +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) { - uint32_t reg = 0U; - - /* check the function parameter */ - if((pllt_psc < 2U) || (pllt_psc > 63U)){ - return ERROR; - }else{ - } - - if((pllt_mul < 49U) || (pllt_mul > 432U)){ - return ERROR; - }else{ - } - - if((ppltr_psc < 2U) || (ppltr_psc > 7U)){ - return ERROR; - }else{ + /* get the rcu interrupt flag */ + if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) { + return SET; + } else { + return RESET; } - - reg = RCU_PLLTCFG; - - /* reset the PLLTRPSC bits, PLLTMF bits and PLLTPSC bits */ - reg &= ~(RCU_PLLTCFG_PLLTRPSC | RCU_PLLTCFG_PLLTMF | RCU_PLLTCFG_PLLTPSC); - - reg |= (PLLTCFG_PLLTPSC(pllt_psc) | PLLTCFG_PLLTMF(pllt_mul) | PLLTCFG_PLLTRPSC(ppltr_psc)); - - RCU_PLLTCFG = reg; - - return SUCCESS; } /*! - \brief configure the TLI prescaler factor from PLLTR clock - \param[in] tli_psc: TLI prescaler factor + \brief clear the interrupt flags + \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum only one parameter can be selected which is shown as below: - \arg RCU_CKTLI_CKPLLTR_DIV2: TLI prescaler select CK_PLLTR/2 - \arg RCU_CKTLI_CKPLLTR_DIV4: TLI prescaler select CK_PLLTR/4 - \arg RCU_CKTLI_CKPLLTR_DIV8: TLI prescaler select CK_PLLTR/8 - \arg RCU_CKTLI_CKPLLTR_DIV16: TLI prescaler select CK_PLLTR/16 + \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear + \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear + \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLL1STB_CLR: PLL1 stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLL2STB_CLR: PLL2 stabilization interrupt flag clear + \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear + \arg RCU_INT_FLAG_PLLTSTB_CLR: PLLT stabilization interrupt flag clear \param[out] none \retval none */ -void rcu_tli_clock_config(uint32_t tli_psc) +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) { - uint32_t reg = 0U; - - reg = RCU_PLLTCFG; - - /* reset the TLIPSC bits */ - reg &= ~RCU_PLLTCFG_TLIPSC; - - RCU_PLLTCFG = (reg | tli_psc); + RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); } - diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_rtc.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_rtc.c index 2f2b1004..b6c5b923 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_rtc.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_rtc.c @@ -2,36 +2,33 @@ \file gd32f20x_rtc.c \brief RTC driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -56,7 +53,7 @@ void rtc_configuration_mode_enter(void) } /*! - \brief exit RTC configuration mode + \brief exit RTC configuration mode \param[in] none \param[out] none \retval none @@ -66,6 +63,49 @@ void rtc_configuration_mode_exit(void) RTC_CTL &= ~RTC_CTL_CMF; } +/*! + \brief wait RTC last write operation finished flag set + \param[in] none + \param[out] none + \retval none +*/ +void rtc_lwoff_wait(void) +{ + /* loop until LWOFF flag is set */ + while(RESET == (RTC_CTL & RTC_CTL_LWOFF)) { + } +} + +/*! + \brief wait RTC registers synchronized flag set + \param[in] none + \param[out] none + \retval none +*/ +void rtc_register_sync_wait(void) +{ + /* clear RSYNF flag */ + RTC_CTL &= ~RTC_CTL_RSYNF; + /* loop until RSYNF flag is set */ + while(RESET == (RTC_CTL & RTC_CTL_RSYNF)) { + } +} + +/*! + \brief get RTC counter value + \param[in] none + \param[out] none + \retval RTC counter value +*/ +uint32_t rtc_counter_get(void) +{ + uint32_t temp = 0x0U; + + temp = RTC_CNTL; + temp |= (RTC_CNTH << RTC_HIGH_BITS_OFFSET); + return temp; +} + /*! \brief set RTC counter value \param[in] cnt: RTC counter value @@ -98,33 +138,6 @@ void rtc_prescaler_set(uint32_t psc) rtc_configuration_mode_exit(); } -/*! - \brief wait RTC last write operation finished flag set - \param[in] none - \param[out] none - \retval none -*/ -void rtc_lwoff_wait(void) -{ - /* loop until LWOFF flag is set */ - while(RESET == (RTC_CTL & RTC_CTL_LWOFF)){ - } -} - -/*! - \brief wait RTC registers synchronized flag set - \param[in] none - \param[out] none - \retval none -*/ -void rtc_register_sync_wait(void) -{ - /* clear RSYNF flag */ - RTC_CTL &= ~RTC_CTL_RSYNF; - /* loop until RSYNF flag is set */ - while(RESET == (RTC_CTL & RTC_CTL_RSYNF)){ - } -} /*! \brief set RTC alarm value @@ -142,20 +155,6 @@ void rtc_alarm_config(uint32_t alarm) rtc_configuration_mode_exit(); } -/*! - \brief get RTC counter value - \param[in] none - \param[out] none - \retval RTC counter value -*/ -uint32_t rtc_counter_get(void) -{ - uint32_t temp = 0x0U; - - temp = RTC_CNTL; - temp |= (RTC_CNTH << RTC_HIGH_BITS_OFFSET); - return temp; -} /*! \brief get RTC divider value @@ -166,111 +165,76 @@ uint32_t rtc_counter_get(void) uint32_t rtc_divider_get(void) { uint32_t temp = 0x00U; - + temp = ((RTC_DIVH & RTC_DIVH_DIV) << RTC_HIGH_BITS_OFFSET); temp |= RTC_DIVL; return temp; } /*! - \brief get RTC flag status - \param[in] flag: specify which flag status to get - only one parameter can be selected which is shown as below: - \arg RTC_FLAG_SECOND: second interrupt flag - \arg RTC_FLAG_ALARM: alarm interrupt flag - \arg RTC_FLAG_OVERFLOW: overflow interrupt flag - \arg RTC_FLAG_RSYN: registers synchronized flag - \arg RTC_FLAG_LWOF: last write operation finished flag + \brief enable RTC interrupt + \param[in] interrupt: specify which interrupt to enbale + one or more parameters can be selected which are shown as below: + \arg RTC_INT_SECOND: second interrupt + \arg RTC_INT_ALARM: alarm interrupt + \arg RTC_INT_OVERFLOW: overflow interrupt \param[out] none - \retval SET or RESET + \retval none */ -FlagStatus rtc_flag_get(uint32_t flag) +void rtc_interrupt_enable(uint32_t interrupt) { - if(RESET != (RTC_CTL & flag)){ - return SET; - }else{ - return RESET; - } + RTC_INTEN |= interrupt; } /*! - \brief clear RTC flag status - \param[in] flag: specify which flag status to clear + \brief disable RTC interrupt + \param[in] interrupt: specify which interrupt to disable one or more parameters can be selected which are shown as below: - \arg RTC_FLAG_SECOND: second interrupt flag - \arg RTC_FLAG_ALARM: alarm interrupt flag - \arg RTC_FLAG_OVERFLOW: overflow interrupt flag - \arg RTC_FLAG_RSYN: registers synchronized flag + \arg RTC_INT_SECOND: second interrupt + \arg RTC_INT_ALARM: alarm interrupt + \arg RTC_INT_OVERFLOW: overflow interrupt \param[out] none \retval none */ -void rtc_flag_clear(uint32_t flag) +void rtc_interrupt_disable(uint32_t interrupt) { - /* clear RTC flag */ - RTC_CTL &= ~flag; + RTC_INTEN &= ~interrupt; } /*! - \brief get RTC interrupt flag status + \brief get RTC flag status \param[in] flag: specify which flag status to get only one parameter can be selected which is shown as below: - \arg RTC_INT_FLAG_SECOND: second interrupt flag - \arg RTC_INT_FLAG_ALARM: alarm interrupt flag - \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag + \arg RTC_FLAG_SECOND: second interrupt flag + \arg RTC_FLAG_ALARM: alarm interrupt flag + \arg RTC_FLAG_OVERFLOW: overflow interrupt flag + \arg RTC_FLAG_RSYN: registers synchronized flag + \arg RTC_FLAG_LWOF: last write operation finished flag \param[out] none \retval SET or RESET */ -FlagStatus rtc_interrupt_flag_get(uint32_t flag) +FlagStatus rtc_flag_get(uint32_t flag) { - if(RESET != (RTC_CTL & flag)){ + if(RESET != (RTC_CTL & flag)) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear RTC interrupt flag status + \brief clear RTC flag status \param[in] flag: specify which flag status to clear one or more parameters can be selected which are shown as below: - \arg RTC_INT_FLAG_SECOND: second interrupt flag - \arg RTC_INT_FLAG_ALARM: alarm interrupt flag - \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag + \arg RTC_FLAG_SECOND: second interrupt flag + \arg RTC_FLAG_ALARM: alarm interrupt flag + \arg RTC_FLAG_OVERFLOW: overflow interrupt flag + \arg RTC_FLAG_RSYN: registers synchronized flag \param[out] none \retval none */ -void rtc_interrupt_flag_clear(uint32_t flag) +void rtc_flag_clear(uint32_t flag) { - /* clear RTC interrupt flag */ + /* clear RTC flag */ RTC_CTL &= ~flag; } - -/*! - \brief enable RTC interrupt - \param[in] interrupt: specify which interrupt to enbale - one or more parameters can be selected which are shown as below: - \arg RTC_INT_SECOND: second interrupt - \arg RTC_INT_ALARM: alarm interrupt - \arg RTC_INT_OVERFLOW: overflow interrupt - \param[out] none - \retval none -*/ -void rtc_interrupt_enable(uint32_t interrupt) -{ - RTC_INTEN |= interrupt; -} - -/*! - \brief disable RTC interrupt - \param[in] interrupt: specify which interrupt to disbale - one or more parameters can be selected which are shown as below: - \arg RTC_INT_SECOND: second interrupt - \arg RTC_INT_ALARM: alarm interrupt - \arg RTC_INT_OVERFLOW: overflow interrupt - \param[out] none - \retval none -*/ -void rtc_interrupt_disable(uint32_t interrupt) -{ - RTC_INTEN &= ~interrupt; -} diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_sdio.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_sdio.c index 84b0d733..ba7505bf 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_sdio.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_sdio.c @@ -2,36 +2,33 @@ \file gd32f20x_sdio.c \brief SDIO driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -83,7 +80,7 @@ void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t cloc /* reset the CLKEDGE, CLKBYP, CLKPWRSAV, DIV */ clock_config &= ~(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV8 | SDIO_CLKCTL_DIV); /* if the clock division is greater or equal to 256, set the DIV[8] */ - if(clock_division >= 256U){ + if(clock_division >= 256U) { clock_config |= SDIO_CLKCTL_DIV8; clock_division -= 256U; } @@ -271,7 +268,7 @@ uint8_t sdio_command_index_get(void) uint32_t sdio_response_get(uint32_t responsex) { uint32_t resp_content = 0U; - switch(responsex){ + switch(responsex) { case SDIO_RESPONSE0: resp_content = SDIO_RESP0; break; @@ -492,9 +489,9 @@ void sdio_stop_readwait_disable(void) */ void sdio_readwait_type_set(uint32_t readwait_type) { - if(SDIO_READWAITTYPE_CLK == readwait_type){ + if(SDIO_READWAITTYPE_CLK == readwait_type) { SDIO_DATACTL |= SDIO_DATACTL_RWTYPE; - }else{ + } else { SDIO_DATACTL &= ~SDIO_DATACTL_RWTYPE; } } @@ -643,7 +640,7 @@ void sdio_ceata_command_completion_disable(void) FlagStatus sdio_flag_get(uint32_t flag) { FlagStatus temp_flag = RESET; - if(RESET != (SDIO_STAT & flag)){ + if(RESET != (SDIO_STAT & flag)) { temp_flag = SET; } return temp_flag; @@ -781,10 +778,10 @@ FlagStatus sdio_interrupt_flag_get(uint32_t int_flag) { uint32_t state = 0U; state = SDIO_STAT; - if(state & int_flag){ + if(state & int_flag) { state = SDIO_INTEN; /* check whether the corresponding bit in SDIO_INTEN is set or not */ - if(state & int_flag){ + if(state & int_flag) { return SET; } } diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_spi.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_spi.c index d491db22..ef61dad4 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_spi.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_spi.c @@ -2,36 +2,33 @@ \file gd32f20x_spi.c \brief SPI driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -53,14 +50,14 @@ OF SUCH DAMAGE. #define RCU_CFG1_PLL2MF_OFFSET 12U /* PLL2MF offset in RCU_CFG1 */ /*! - \brief reset SPI and I2S + \brief reset SPI and I2S \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none */ void spi_i2s_deinit(uint32_t spi_periph) { - switch(spi_periph){ + switch(spi_periph) { case SPI0: /* reset SPI0 */ rcu_periph_reset_enable(RCU_SPI0RST); @@ -76,32 +73,33 @@ void spi_i2s_deinit(uint32_t spi_periph) rcu_periph_reset_enable(RCU_SPI2RST); rcu_periph_reset_disable(RCU_SPI2RST); break; - default : + default: break; } } /*! - \brief initialize the parameters of SPI struct with the default values - \param[in] spi_struct: SPI parameter stuct - \param[out] none + \brief initialize the parameters of SPI structure with the default values + \param[in] none + \param[out] spi_struct: the initialized structure spi_parameter_struct pointer \retval none */ -void spi_struct_para_init(spi_parameter_struct* spi_struct) +void spi_struct_para_init(spi_parameter_struct *spi_struct) { - /* set the SPI struct with the default values */ - spi_struct->device_mode = SPI_SLAVE; - spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; - spi_struct->frame_size = SPI_FRAMESIZE_8BIT; - spi_struct->nss = SPI_NSS_HARD; + /* configure the SPI structure with the default values */ + spi_struct->device_mode = SPI_SLAVE; + spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_struct->frame_size = SPI_FRAMESIZE_8BIT; + spi_struct->nss = SPI_NSS_HARD; + spi_struct->endian = SPI_ENDIAN_MSB; spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; - spi_struct->prescale = SPI_PSC_2; + spi_struct->prescale = SPI_PSC_2; } /*! \brief initialize SPI parameter \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] spi_struct: SPI parameter initialization stuct members of the structure + \param[in] spi_struct: SPI parameter initialization struct members of the structure and the member values are shown as below: device_mode: SPI_MASTER, SPI_SLAVE trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, @@ -115,8 +113,8 @@ void spi_struct_para_init(spi_parameter_struct* spi_struct) \param[out] none \retval none */ -void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) -{ +void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct) +{ uint32_t reg = 0U; reg = SPI_CTL0(spi_periph); reg &= SPI_INIT_MASK; @@ -133,7 +131,7 @@ void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) reg |= spi_struct->endian; /* select SPI polarity and phase */ reg |= spi_struct->clock_polarity_phase; - /* select SPI prescale to adjust transmit speed */ + /* select SPI prescaler to adjust transmit speed */ reg |= spi_struct->prescale; /* write to SPI_CTL0 register */ @@ -154,7 +152,7 @@ void spi_enable(uint32_t spi_periph) } /*! - \brief disable SPI + \brief disable SPI \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none @@ -165,7 +163,7 @@ void spi_disable(uint32_t spi_periph) } /*! - \brief initialize I2S parameter + \brief initialize I2S parameters \param[in] spi_periph: SPIx(x=1,2) \param[in] mode: I2S operation mode only one parameter can be selected which is shown as below: @@ -194,7 +192,7 @@ void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ck reg &= I2S_INIT_MASK; /* enable I2S mode */ - reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; /* select I2S mode */ reg |= (uint32_t)mode; /* select I2S standard */ @@ -207,7 +205,7 @@ void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ck } /*! - \brief configure I2S prescaler + \brief configure I2S prescaler \param[in] spi_periph: SPIx(x=1,2) \param[in] audiosample: I2S audio sample rate only one parameter can be selected which is shown as below: @@ -228,8 +226,8 @@ void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ck \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit \param[in] mckout: I2S master clock output only one parameter can be selected which is shown as below: - \arg I2S_MCKOUT_ENABLE: I2S master clock output enable - \arg I2S_MCKOUT_DISABLE: I2S master clock output disable + \arg I2S_MCKOUT_ENABLE: enable I2S master clock output + \arg I2S_MCKOUT_DISABLE: disable I2S master clock output \param[out] none \retval none */ @@ -239,52 +237,52 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t framefor uint32_t clks = 0U; uint32_t i2sclock = 0U; - /* deinit SPI_I2SPSC register */ + /* deinitialize SPI_I2SPSC register */ SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE; /* get the I2S clock source */ - if(SPI1 == ((uint32_t)spi_periph)){ + if(SPI1 == ((uint32_t)spi_periph)) { /* I2S1 clock source selection */ clks = I2S1_CLOCK_SEL; - }else{ + } else { /* I2S2 clock source selection */ clks = I2S2_CLOCK_SEL; } - - if(0U != (RCU_CFG1 & clks)){ + + if(0U != (RCU_CFG1 & clks)) { /* get RCU PLL2 clock multiplication factor */ clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> RCU_CFG1_PLL2MF_OFFSET); - - if((clks > 5U) && (clks < 15U)){ + + if((clks > 5U) && (clks < 15U)) { /* multiplier is between 8 and 14 */ clks += 2U; - }else{ - if(15U == clks){ + } else { + if(15U == clks) { /* multiplier is 20 */ clks = 20U; } } - + /* get the PREDV1 value */ - i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> RCU_CFG1_PREDV1_OFFSET) + 1U); + i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> RCU_CFG1_PREDV1_OFFSET) + 1U); /* calculate I2S clock based on PLL2 and PREDV1 */ - i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U); - }else{ + i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U); + } else { /* get system clock */ i2sclock = rcu_clock_freq_get(CK_SYS); } - - /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ - if(I2S_MCKOUT_ENABLE == mckout){ + + /* configure the prescaler depending on the mclk output state, the frame format and audio sample rate */ + if(I2S_MCKOUT_ENABLE == mckout) { clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample); - }else{ - if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){ - clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample); - }else{ - clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample); + } else { + if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat) { + clks = (uint32_t)(((i2sclock / 32U) * 10U) / audiosample); + } else { + clks = (uint32_t)(((i2sclock / 64U) * 10U) / audiosample); } } - + /* remove the floating point */ clks = (clks + 5U) / 10U; i2sof = (clks & 0x00000001U); @@ -292,7 +290,7 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t framefor i2sof = (i2sof << 8U); /* set the default values */ - if((i2sdiv < 2U) || (i2sdiv > 255U)){ + if((i2sdiv < 2U) || (i2sdiv > 255U)) { i2sdiv = 2U; i2sof = 0U; } @@ -302,12 +300,13 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t framefor /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); + /* configure data frame format */ SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat; } /*! - \brief enable I2S + \brief enable I2S \param[in] spi_periph: SPIx(x=1,2) \param[out] none \retval none @@ -318,7 +317,7 @@ void i2s_enable(uint32_t spi_periph) } /*! - \brief disable I2S + \brief disable I2S \param[in] spi_periph: SPIx(x=1,2) \param[out] none \retval none @@ -329,7 +328,7 @@ void i2s_disable(uint32_t spi_periph) } /*! - \brief enable SPI NSS output + \brief enable SPI NSS output \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none @@ -340,7 +339,7 @@ void spi_nss_output_enable(uint32_t spi_periph) } /*! - \brief disable SPI NSS output + \brief disable SPI NSS output \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none @@ -373,7 +372,7 @@ void spi_nss_internal_low(uint32_t spi_periph) } /*! - \brief enable SPI DMA send or receive + \brief enable SPI DMA send or receive \param[in] spi_periph: SPIx(x=0,1,2) \param[in] dma: SPI DMA mode only one parameter can be selected which is shown as below: @@ -384,15 +383,15 @@ void spi_nss_internal_low(uint32_t spi_periph) */ void spi_dma_enable(uint32_t spi_periph, uint8_t dma) { - if(SPI_DMA_TRANSMIT == dma){ + if(SPI_DMA_TRANSMIT == dma) { SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; - }else{ + } else { SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; } } /*! - \brief disable SPI DMA send or receive + \brief disable SPI DMA send or receive \param[in] spi_periph: SPIx(x=0,1,2) \param[in] dma: SPI DMA mode only one parameter can be selected which is shown as below: @@ -403,15 +402,15 @@ void spi_dma_enable(uint32_t spi_periph, uint8_t dma) */ void spi_dma_disable(uint32_t spi_periph, uint8_t dma) { - if(SPI_DMA_TRANSMIT == dma){ + if(SPI_DMA_TRANSMIT == dma) { SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); - }else{ + } else { SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); } } /*! - \brief configure SPI/I2S data frame format + \brief configure SPI data frame format \param[in] spi_periph: SPIx(x=0,1,2) \param[in] frame_format: SPI frame size only one parameter can be selected which is shown as below: @@ -428,6 +427,27 @@ void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format SPI_CTL0(spi_periph) |= (uint32_t)frame_format; } +/*! + \brief configure SPI bidirectional transfer direction + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] transfer_direction: SPI transfer direction + only one parameter can be selected which is shown as below: + \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode + \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode + \param[out] none + \retval none +*/ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) +{ + if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction) { + /* set the transmit only mode */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; + } else { + /* set the receive only mode */ + SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; + } +} + /*! \brief SPI transmit data \param[in] spi_periph: SPIx(x=0,1,2) @@ -452,28 +472,7 @@ uint16_t spi_i2s_data_receive(uint32_t spi_periph) } /*! - \brief configure SPI bidirectional transfer direction - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] transfer_direction: SPI transfer direction - only one parameter can be selected which is shown as below: - \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode - \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode - \param[out] none - \retval none -*/ -void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) -{ - if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){ - /* set the transmit only mode */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; - }else{ - /* set the receive only mode */ - SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; - } -} - -/*! - \brief set CRC polynomial + \brief set CRC polynomial \param[in] spi_periph: SPIx(x=0,1,2) \param[in] crc_poly: CRC polynomial value \param[out] none @@ -481,14 +480,12 @@ void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_di */ void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly) { - /* enable SPI CRC */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; /* set SPI CRC polynomial */ SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; } /*! - \brief get SPI CRC polynomial + \brief get SPI CRC polynomial \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval 16-bit CRC polynomial @@ -499,7 +496,7 @@ uint16_t spi_crc_polynomial_get(uint32_t spi_periph) } /*! - \brief turn on CRC function + \brief turn on CRC function \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none @@ -510,7 +507,7 @@ void spi_crc_on(uint32_t spi_periph) } /*! - \brief turn off CRC function + \brief turn off CRC function \param[in] spi_periph: SPIx(x=0,1,2) \param[out] none \retval none @@ -543,75 +540,151 @@ void spi_crc_next(uint32_t spi_periph) */ uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc) { - if(SPI_CRC_TX == crc){ + if(SPI_CRC_TX == crc) { return ((uint16_t)(SPI_TCRC(spi_periph))); - }else{ + } else { return ((uint16_t)(SPI_RCRC(spi_periph))); } } /*! - \brief enable SPI and I2S interrupt + \brief clear SPI CRC error flag status + \param[in] spi_periph: SPIx(x=0,1,2) + \param[out] none + \retval none +*/ +void spi_crc_error_clear(uint32_t spi_periph) +{ + SPI_STAT(spi_periph) = (uint32_t)(~SPI_FLAG_CRCERR); +} + +/*! + \brief enable quad wire SPI + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void spi_quad_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD; +} + +/*! + \brief disable quad wire SPI + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void spi_quad_disable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD); +} + +/*! + \brief enable quad wire SPI write + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void spi_quad_write_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD); +} + +/*! + \brief enable quad wire SPI read + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void spi_quad_read_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD; +} + +/*! + \brief enable SPI_IO2 and SPI_IO3 pin output + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void spi_quad_io23_output_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; +} + +/*! + \brief disable SPI_IO2 and SPI_IO3 pin output + \param[in] spi_periph: SPIx(only x=0) + \param[out] none + \retval none +*/ +void spi_quad_io23_output_disable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); +} + +/*! + \brief get SPI and I2S flag status + \param[in] spi_periph: SPIx(x=0,1,2) + \param[in] flag: SPI/I2S flag status + only one parameter can be selected which is shown as below: + \arg SPI_FLAG_TBE: transmit buffer empty flag + \arg SPI_FLAG_RBNE: receive buffer not empty flag + \arg SPI_FLAG_TRANS: transmit on-going flag + \arg SPI_FLAG_RXORERR: receive overrun error flag + \arg SPI_FLAG_CONFERR: mode config error flag + \arg SPI_FLAG_CRCERR: CRC error flag + \arg I2S_FLAG_TBE: transmit buffer empty flag + \arg I2S_FLAG_RBNE: receive buffer not empty flag + \arg I2S_FLAG_TRANS: transmit on-going flag + \arg I2S_FLAG_RXORERR: overrun error flag + \arg I2S_FLAG_TXURERR: underrun error flag + \arg I2S_FLAG_CH: channel side flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) +{ + if(RESET != (SPI_STAT(spi_periph) & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief enable SPI and I2S interrupt \param[in] spi_periph: SPIx(x=0,1,2) \param[in] interrupt: SPI/I2S interrupt only one parameter can be selected which is shown as below: \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + \arg SPI_I2S_INT_ERR: CRC error, configuration error, reception overrun error, transmission underrun error and format error interrupt \param[out] none \retval none */ void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) { - switch(interrupt){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_TBE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_RBNE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; - break; - /* SPI/I2S error */ - case SPI_I2S_INT_ERR: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; - break; - default: - break; - } + SPI_CTL1(spi_periph) |= (uint32_t)interrupt; } /*! - \brief disable SPI and I2S interrupt + \brief disable SPI and I2S interrupt \param[in] spi_periph: SPIx(x=0,1,2) \param[in] interrupt: SPI/I2S interrupt only one parameter can be selected which is shown as below: \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + \arg SPI_I2S_INT_ERR: CRC error, configuration error, reception overrun error, transmission underrun error and format error interrupt \param[out] none \retval none */ void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) { - switch(interrupt){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_TBE: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_RBNE: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); - break; - /* SPI/I2S error */ - case SPI_I2S_INT_ERR: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); - break; - default : - break; - } + SPI_CTL1(spi_periph) &= ~(uint32_t)interrupt; } /*! @@ -633,7 +706,7 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) uint32_t reg1 = SPI_STAT(spi_periph); uint32_t reg2 = SPI_CTL1(spi_periph); - switch(interrupt){ + switch(interrupt) { /* SPI/I2S transmit buffer empty interrupt */ case SPI_I2S_INT_FLAG_TBE: reg1 = reg1 & SPI_STAT_TBE; @@ -664,119 +737,13 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) reg1 = reg1 & SPI_STAT_TXURERR; reg2 = reg2 & SPI_CTL1_ERRIE; break; - default : + default: break; } /*get SPI/I2S interrupt flag status */ - if((0U != reg1) && (0U != reg2)){ + if((0U != reg1) && (0U != reg2)) { return SET; - }else{ + } else { return RESET; } } - -/*! - \brief get SPI and I2S flag status - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] flag: SPI/I2S flag status - only one parameter can be selected which is shown as below: - \arg SPI_FLAG_TBE: transmit buffer empty flag - \arg SPI_FLAG_RBNE: receive buffer not empty flag - \arg SPI_FLAG_TRANS: transmit on-going flag - \arg SPI_FLAG_RXORERR: receive overrun error flag - \arg SPI_FLAG_CONFERR: mode config error flag - \arg SPI_FLAG_CRCERR: CRC error flag - \arg I2S_FLAG_TBE: transmit buffer empty flag - \arg I2S_FLAG_RBNE: receive buffer not empty flag - \arg I2S_FLAG_TRANS: transmit on-going flag - \arg I2S_FLAG_RXORERR: overrun error flag - \arg I2S_FLAG_TXURERR: underrun error flag - \arg I2S_FLAG_CH: channel side flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) -{ - if(RESET != (SPI_STAT(spi_periph) & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear SPI CRC error flag status - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_error_clear(uint32_t spi_periph) -{ - SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); -} - -/*! - \brief enable quad wire SPI - \param[in] spi_periph: SPIx(only x=0) - \param[out] none - \retval none -*/ -void qspi_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD; -} - -/*! - \brief disable quad wire SPI - \param[in] spi_periph: SPIx(only x=0) - \param[out] none - \retval none -*/ -void qspi_disable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD); -} - -/*! - \brief enable quad wire SPI write - \param[in] spi_periph: SPIx(only x=0) - \param[out] none - \retval none -*/ -void qspi_write_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD); -} - -/*! - \brief enable quad wire SPI read - \param[in] spi_periph: SPIx(only x=0) - \param[out] none - \retval none -*/ -void qspi_read_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD; -} - -/*! - \brief enable SPI_IO2 and SPI_IO3 pin output - \param[in] spi_periph: SPIx(only x=0) - \param[out] none - \retval none -*/ -void qspi_io23_output_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; -} - - /*! - \brief disable SPI_IO2 and SPI_IO3 pin output - \param[in] spi_periph: SPIx(only x=0) - \param[out] none - \retval none -*/ -void qspi_io23_output_disable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); -} diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_timer.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_timer.c index 2b893913..8318da69 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_timer.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_timer.c @@ -2,40 +2,38 @@ \file gd32f20x_timer.c \brief TIMER driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f20x_timer.h" + /* TIMER init parameter mask */ #define ALIGNEDMODE_MASK ((uint32_t)0x00000060U) /*!< TIMER init parameter aligne dmode mask */ #define COUNTERDIRECTION_MASK ((uint32_t)0x00000010U) /*!< TIMER init parameter counter direction mask */ @@ -49,7 +47,7 @@ OF SUCH DAMAGE. */ void timer_deinit(uint32_t timer_periph) { - switch(timer_periph){ + switch(timer_periph) { case TIMER0: /* reset TIMER0 */ rcu_periph_reset_enable(RCU_TIMER0RST); @@ -127,11 +125,11 @@ void timer_deinit(uint32_t timer_periph) /*! \brief initialize TIMER init parameter struct with a default value - \param[in] initpara: init parameter struct - \param[out] none + \param[in] none + \param[out] initpara: init parameter struct \retval none */ -void timer_struct_para_init(timer_parameter_struct* initpara) +void timer_struct_para_init(timer_parameter_struct *initpara) { /* initialize the init parameter struct member with the default value */ initpara->prescaler = 0U; @@ -146,24 +144,24 @@ void timer_struct_para_init(timer_parameter_struct* initpara) \brief initialize TIMER counter \param[in] timer_periph: TIMERx(x=0..13) \param[in] initpara: init parameter struct - prescaler: prescaler value of the counter clock,0~65535 - alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH - counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN - period: counter auto reload value,0~65535 - clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4 - repetitioncounter: counter repetition value,0~255 + prescaler: prescaler value of the counter clock,0~65535 + alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH + counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN + period: counter auto reload value,0~65535 + clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4 + repetitioncounter: counter repetition value,0~255 \param[out] none \retval none */ -void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) +void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara) { /* configure the counter prescaler value */ TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; /* configure the counter direction and aligned mode */ if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) || (TIMER3 == timer_periph) || - (TIMER4 == timer_periph) || (TIMER7 == timer_periph) || (TIMER8 == timer_periph) || (TIMER9 == timer_periph) || - (TIMER10 == timer_periph) || (TIMER11 == timer_periph) || (TIMER12 == timer_periph) || (TIMER13 == timer_periph)){ + (TIMER4 == timer_periph) || (TIMER7 == timer_periph) || (TIMER8 == timer_periph) || (TIMER9 == timer_periph) || + (TIMER10 == timer_periph) || (TIMER11 == timer_periph) || (TIMER12 == timer_periph) || (TIMER13 == timer_periph)) { TIMER_CTL0(timer_periph) &= (~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM)); TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->alignedmode & ALIGNEDMODE_MASK); TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK); @@ -172,13 +170,13 @@ void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) /* configure the autoreload value */ TIMER_CAR(timer_periph) = (uint32_t)initpara->period; - if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){ + if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)) { /* reset the CKDIV bit */ TIMER_CTL0(timer_periph) &= (~(uint32_t)TIMER_CTL0_CKDIV); TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->clockdivision & CLOCKDIVISION_MASK); } - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { /* configure the repetition counter value */ TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; } @@ -267,7 +265,7 @@ void timer_update_event_disable(uint32_t timer_periph) */ void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) { - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM; + TIMER_CTL0(timer_periph) &= (uint32_t)(~TIMER_CTL0_CAM); TIMER_CTL0(timer_periph) |= (uint32_t)aligned; } @@ -296,7 +294,7 @@ void timer_counter_down_direction(uint32_t timer_periph) /*! \brief configure TIMER prescaler \param[in] timer_periph: TIMERx(x=0..13) - \param[in] prescaler: prescaler value + \param[in] prescaler: prescaler value, 0~65535 \param[in] pscreload: prescaler reload mode only one parameter can be selected which is shown as below: \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now @@ -307,8 +305,8 @@ void timer_counter_down_direction(uint32_t timer_periph) void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload) { TIMER_PSC(timer_periph) = (uint32_t)prescaler; - - if(TIMER_PSC_RELOAD_NOW == pscreload){ + + if(TIMER_PSC_RELOAD_NOW == pscreload) { TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; } } @@ -316,22 +314,22 @@ void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t /*! \brief configure TIMER repetition register value \param[in] timer_periph: TIMERx(x=0,7) - \param[in] repetition: the counter repetition value,0~255 + \param[in] repetition: the counter repetition value, 0~255 \param[out] none \retval none */ -void timer_repetition_value_config(uint32_t timer_periph, uint8_t repetition) +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) { TIMER_CREP(timer_periph) = (uint32_t)repetition; -} - +} + /*! \brief configure TIMER autoreload register value \param[in] timer_periph: TIMERx(x=0..13) - \param[in] autoreload: the counter auto-reload value + \param[in] autoreload: the counter auto-reload value, 0~65535 \param[out] none \retval none -*/ +*/ void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload) { TIMER_CAR(timer_periph) = (uint32_t)autoreload; @@ -340,10 +338,10 @@ void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload) /*! \brief configure TIMER counter register value \param[in] timer_periph: TIMERx(x=0..13) - \param[in] counter: the counter value + \param[in] counter: the counter value, 0~65535 \param[out] none \retval none -*/ +*/ void timer_counter_value_config(uint32_t timer_periph, uint32_t counter) { TIMER_CNT(timer_periph) = (uint32_t)counter; @@ -353,8 +351,8 @@ void timer_counter_value_config(uint32_t timer_periph, uint32_t counter) \brief read TIMER counter value \param[in] timer_periph: TIMERx(x=0..13) \param[out] none - \retval counter value -*/ + \retval counter value, 0~65535 +*/ uint32_t timer_counter_read(uint32_t timer_periph) { uint32_t count_value = 0U; @@ -366,8 +364,8 @@ uint32_t timer_counter_read(uint32_t timer_periph) \brief read TIMER prescaler value \param[in] timer_periph: TIMERx(x=0..13) \param[out] none - \retval prescaler register value -*/ + \retval prescaler register value, 0~65535 +*/ uint16_t timer_prescaler_read(uint32_t timer_periph) { uint16_t prescaler_value = 0U; @@ -387,17 +385,17 @@ uint16_t timer_prescaler_read(uint32_t timer_periph) */ void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) { - if(TIMER_SP_MODE_SINGLE == spmode){ + if(TIMER_SP_MODE_SINGLE == spmode) { TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; - }else if(TIMER_SP_MODE_REPETITIVE == spmode){ + } else if(TIMER_SP_MODE_REPETITIVE == spmode) { TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); - }else{ - /* illegal parameters */ + } else { + /* illegal parameters */ } } /*! - \brief configure TIMER update source + \brief configure TIMER update source \param[in] timer_periph: TIMERx(x=0..13) \param[in] update: only one parameter can be selected which is shown as below: @@ -409,19 +407,19 @@ void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) */ void timer_update_source_config(uint32_t timer_periph, uint32_t update) { - if(TIMER_UPDATE_SRC_REGULAR == update){ + if(TIMER_UPDATE_SRC_REGULAR == update) { TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; - }else if(TIMER_UPDATE_SRC_GLOBAL == update){ + } else if(TIMER_UPDATE_SRC_GLOBAL == update) { TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; - }else{ + } else { /* illegal parameters */ } } /*! \brief enable the TIMER DMA - \param[in] timer_periph: TIMERx(x=0,1,2,5,14,15,16) - \param[in] dma: timer DMA source enable + \param[in] timer_periph: TIMERx(x=0..7) + \param[in] dma: timer DMA source enable only one parameter can be selected which is shown as below: \arg TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7) \arg TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7) @@ -435,12 +433,12 @@ void timer_update_source_config(uint32_t timer_periph, uint32_t update) */ void timer_dma_enable(uint32_t timer_periph, uint16_t dma) { - TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; + TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; } /*! \brief disable the TIMER DMA - \param[in] timer_periph: please refer to the following parameters + \param[in] timer_periph: TIMERx(x=0..7) \param[in] dma: timer DMA source disable only one parameter can be selected which is shown as below: \arg TIMER_DMA_UPD: update DMA disable,TIMERx(x=0..7) @@ -448,14 +446,14 @@ void timer_dma_enable(uint32_t timer_periph, uint16_t dma) \arg TIMER_DMA_CH1D: channel 1 DMA disable,TIMERx(x=0..4,7) \arg TIMER_DMA_CH2D: channel 2 DMA disable,TIMERx(x=0..4,7) \arg TIMER_DMA_CH3D: channel 3 DMA disable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CMTD: commutation DMA request disable,TIMERx(x=0,7) + \arg TIMER_DMA_CMTD: commutation DMA request disable, TIMERx(x=0,7) \arg TIMER_DMA_TRGD: trigger DMA disable,TIMERx(x=0..4,7) \param[out] none \retval none */ void timer_dma_disable(uint32_t timer_periph, uint16_t dma) { - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); } /*! @@ -464,18 +462,18 @@ void timer_dma_disable(uint32_t timer_periph, uint16_t dma) \param[in] dma_request: channel DMA request source selection only one parameter can be selected which is shown as below: \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs - \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs + \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs \param[out] none \retval none */ void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request) { - if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){ + if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request) { TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; - }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){ + } else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request) { TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; - }else{ - /* illegal parameters */ + } else { + /* illegal parameters */ } } @@ -512,21 +510,24 @@ void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma */ void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) { - TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); - TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); + uint32_t reg = 0U; + reg = TIMER_DMACFG(timer_periph); + reg &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); + reg |= (uint32_t)(dma_baseaddr | dma_lenth); + TIMER_DMACFG(timer_periph) = (uint32_t)reg; } /*! - \brief software generate events + \brief software generate events \param[in] timer_periph: please refer to the following parameters \param[in] event: the timer software event generation sources one or more parameters can be selected which are shown as below: \arg TIMER_EVENT_SRC_UPG: update event generation, TIMERx(x=0..13) - \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..4,7..13) + \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..4,7..13) \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..4,7,8,11) - \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..4,7) - \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..4,7) - \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,7) + \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..4,7) + \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,7) \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0..4,7,8,11) \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0,7) \param[out] none @@ -539,11 +540,11 @@ void timer_event_software_generate(uint32_t timer_periph, uint16_t event) /*! \brief initialize TIMER break parameter struct with a default value - \param[in] breakpara: TIMER break parameter struct - \param[out] none + \param[in] none + \param[out] breakpara: TIMER break parameter struct \retval none */ -void timer_break_struct_para_init(timer_break_parameter_struct* breakpara) +void timer_break_struct_para_init(timer_break_parameter_struct *breakpara) { /* initialize the break parameter struct member with the default value */ breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; @@ -556,20 +557,20 @@ void timer_break_struct_para_init(timer_break_parameter_struct* breakpara) } /*! - \brief configure TIMER break function + \brief configure TIMER break function \param[in] timer_periph: TIMERx(x=0,7) \param[in] breakpara: TIMER break parameter struct - runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE - ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE + runoffstate: TIMER_ROS_STATE_ENABLE, TIMER_ROS_STATE_DISABLE + ideloffstate: TIMER_IOS_STATE_ENABLE, TIMER_IOS_STATE_DISABLE deadtime: 0~255 - breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH - outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE - protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 + breakpolarity: TIMER_BREAK_POLARITY_LOW, TIMER_BREAK_POLARITY_HIGH + outputautostate: TIMER_OUTAUTO_ENABLE ,TIMER_OUTAUTO_DISABLE + protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0, TIMER_CCHP_PROT_1, TIMER_CCHP_PROT_2 breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE \param[out] none \retval none */ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara) +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara) { TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | ((uint32_t)(breakpara->ideloffstate)) | @@ -625,7 +626,7 @@ void timer_automatic_output_disable(uint32_t timer_periph) } /*! - \brief enable or disable TIMER primary output function + \brief configure TIMER primary output function \param[in] timer_periph: TIMERx(x=0,7) \param[in] newvalue: ENABLE or DISABLE \param[out] none @@ -633,25 +634,25 @@ void timer_automatic_output_disable(uint32_t timer_periph) */ void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) { - if(ENABLE == newvalue){ + if(ENABLE == newvalue) { TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; - }else{ + } else { TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); } } /*! - \brief enable or disable channel capture/compare control shadow register + \brief enable or disable channel capture/compare control shadow register \param[in] timer_periph: TIMERx(x=0,7) - \param[in] newvalue: ENABLE or DISABLE + \param[in] newvalue: ENABLE or DISABLE \param[out] none \retval none */ void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) { - if(ENABLE == newvalue){ + if(ENABLE == newvalue) { TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; - }else{ + } else { TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); } } @@ -662,28 +663,28 @@ void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus ne \param[in] ccuctl: channel control shadow register update control only one parameter can be selected which is shown as below: \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set - \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs + \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs \param[out] none \retval none -*/ +*/ void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl) { - if(TIMER_UPDATECTL_CCU == ccuctl){ + if(TIMER_UPDATECTL_CCU == ccuctl) { TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); - }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){ + } else if(TIMER_UPDATECTL_CCUTRI == ccuctl) { TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; - }else{ - /* illegal parameters */ + } else { + /* illegal parameters */ } } /*! \brief initialize TIMER channel output parameter struct with a default value - \param[in] ocpara: TIMER channel n output parameter struct - \param[out] none + \param[in] none + \param[out] ocpara: TIMER channel n output parameter struct \retval none */ -void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara) +void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara) { /* initialize the channel output parameter struct member with the default value */ ocpara->outputstate = TIMER_CCX_DISABLE; @@ -704,18 +705,18 @@ void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara) \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) \param[in] ocpara: TIMER channeln output parameter struct - outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE - outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE - ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW - ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW - ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH - ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH + outputstate: TIMER_CCX_ENABLE, TIMER_CCX_DISABLE + outputnstate: TIMER_CCXN_ENABLE, TIMER_CCXN_DISABLE + ocpolarity: TIMER_OC_POLARITY_HIGH, TIMER_OC_POLARITY_LOW + ocnpolarity: TIMER_OCN_POLARITY_HIGH, TIMER_OCN_POLARITY_LOW + ocidlestate: TIMER_OC_IDLE_STATE_LOW, TIMER_OC_IDLE_STATE_HIGH + ocnidlestate: TIMER_OCN_IDLE_STATE_LOW, TIMER_OCN_IDLE_STATE_HIGH \param[out] none \retval none */ -void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara) +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: /* reset the CH0EN bit */ @@ -728,7 +729,7 @@ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_ /* set the CH0P bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { /* reset the CH0NEN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); /* set the CH0NEN bit */ @@ -757,25 +758,25 @@ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_ /* reset the CH1P bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); /* set the CH1P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U); - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { /* reset the CH1NEN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); /* set the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U); /* reset the CH1NP bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U); /* reset the ISO1 bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); /* set the ISO1 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 2U); + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); /* reset the ISO1N bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); /* set the ISO1N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 2U); + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U); } break; /* configure TIMER_CH_2 */ @@ -788,44 +789,44 @@ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_ /* reset the CH2P bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); /* set the CH2P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U); - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { /* reset the CH2NEN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); /* set the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U); /* reset the CH2NP bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); /* set the CH2NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 8U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U); /* reset the ISO2 bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); /* set the ISO2 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 4U); + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U); /* reset the ISO2N bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); /* set the ISO2N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 4U); + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U); } break; /* configure TIMER_CH_3 */ case TIMER_CH_3: /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; /* set the CH3EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 12U); /* reset the CH3P bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); /* set the CH3P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 12U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U); - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ + if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) { /* reset the ISO3 bit */ TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); /* set the ISO3 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 6U); + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U); } break; default: @@ -850,14 +851,14 @@ void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_ \arg TIMER_OC_MODE_TOGGLE: toggle mode \arg TIMER_OC_MODE_LOW: force low mode \arg TIMER_OC_MODE_HIGH: force high mode - \arg TIMER_OC_MODE_PWM0: PWM0 mode - \arg TIMER_OC_MODE_PWM1: PWM1 mode + \arg TIMER_OC_MODE_PWM0: PWM mode 0 + \arg TIMER_OC_MODE_PWM1: PWM mode 1 \param[out] none \retval none */ void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); @@ -866,7 +867,7 @@ void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, u /* configure TIMER_CH_1 */ case TIMER_CH_1: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); break; /* configure TIMER_CH_2 */ case TIMER_CH_2: @@ -876,7 +877,7 @@ void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, u /* configure TIMER_CH_3 */ case TIMER_CH_3: TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); break; default: break; @@ -892,13 +893,13 @@ void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, u \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] pulse: channel output pulse value + \param[in] pulse: channel output pulse value, 0~65535 \param[out] none \retval none */ -void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint16_t pulse) +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CH0CV(timer_periph) = (uint32_t)pulse; @@ -913,7 +914,7 @@ void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t cha break; /* configure TIMER_CH_3 */ case TIMER_CH_3: - TIMER_CH3CV(timer_periph) = (uint32_t)pulse; + TIMER_CH3CV(timer_periph) = (uint32_t)pulse; break; default: break; @@ -938,7 +939,7 @@ void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t cha */ void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); @@ -982,7 +983,7 @@ void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, */ void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); @@ -1026,7 +1027,7 @@ void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, u */ void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); @@ -1053,7 +1054,7 @@ void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, } /*! - \brief configure TIMER channel output polarity + \brief configure TIMER channel output polarity \param[in] timer_periph: please refer to the following parameters \param[in] channel: only one parameter can be selected which is shown as below: @@ -1070,7 +1071,7 @@ void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, */ void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); @@ -1097,14 +1098,14 @@ void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channe } /*! - \brief configure TIMER channel complementary output polarity + \brief configure TIMER channel complementary output polarity \param[in] timer_periph: TIMERx(x=0,7) - \param[in] channel: + \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \param[in] ocnpolarity: channel complementary output polarity + \param[in] ocnpolarity: channel complementary output polarity only one parameter can be selected which is shown as below: \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low @@ -1113,7 +1114,7 @@ void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channe */ void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); @@ -1145,14 +1146,14 @@ void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, u \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) \param[in] state: TIMER channel enable state only one parameter can be selected which is shown as below: - \arg TIMER_CCX_ENABLE: channel enable - \arg TIMER_CCX_DISABLE: channel disable + \arg TIMER_CCX_ENABLE: channel enable + \arg TIMER_CCX_DISABLE: channel disable \param[out] none \retval none */ void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); @@ -1188,14 +1189,14 @@ void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, \arg TIMER_CH_2: TIMER channel2 \param[in] ocnstate: TIMER channel complementary output enable state only one parameter can be selected which is shown as below: - \arg TIMER_CCXN_ENABLE: channel complementary enable - \arg TIMER_CCXN_DISABLE: channel complementary disable + \arg TIMER_CCXN_ENABLE: channel complementary enable + \arg TIMER_CCXN_DISABLE: channel complementary disable \param[out] none \retval none */ void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); @@ -1218,11 +1219,11 @@ void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint /*! \brief initialize TIMER channel input parameter struct with a default value - \param[in] icpara: TIMER channel intput parameter struct - \param[out] none + \param[in] none + \param[out] icpara: TIMER channel intput parameter struct \retval none */ -void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) +void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara) { /* initialize the channel input parameter struct member with the default value */ icpara->icpolarity = TIMER_IC_POLARITY_RISING; @@ -1232,17 +1233,17 @@ void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) } /*! - \brief configure TIMER input capture parameter + \brief configure TIMER input capture parameter \param[in] timer_periph: please refer to the following parameters \param[in] channel: - only one parameter can be selected which is shown as below: + only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) \param[in] icpara: TIMER channel intput parameter struct icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING, - TIMER_IC_POLARITY_BOTH_EDGE(only for TIMER1~TIMER8) + TIMER_IC_POLARITY_BOTH_EDGE(only for TIMERx(x=0, 7..13)) icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI, TIMER_IC_SELECTION_ITS icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4, @@ -1251,9 +1252,9 @@ void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) \param[out] none \retval none */ -void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara) +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: /* reset the CH0EN bit */ @@ -1272,7 +1273,7 @@ void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_i /* set the CH0EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; break; - + /* configure TIMER_CH_1 */ case TIMER_CH_1: /* reset the CH1EN bit */ @@ -1335,7 +1336,7 @@ void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_i break; } /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,channel,(uint16_t)(icpara->icprescaler)); + timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler)); } /*! @@ -1358,7 +1359,7 @@ void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_i */ void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) { - switch(channel){ + switch(channel) { /* configure TIMER_CH_0 */ case TIMER_CH_0: TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); @@ -1394,13 +1395,13 @@ void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_ \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) \param[out] none - \retval channel capture compare register value + \retval channel capture compare register value, 0~65535 */ uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) { uint32_t count_value = 0U; - switch(channel){ + switch(channel) { case TIMER_CH_0: /* read TIMER channel 0 capture compare register value */ count_value = TIMER_CH0CV(timer_periph); @@ -1424,39 +1425,39 @@ uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16 } /*! - \brief configure TIMER input pwm capture function + \brief configure TIMER input pwm capture function \param[in] timer_periph: TIMERx(x=0..4,7,8,11) \param[in] channel: only one parameter can be selected which is shown as below: \arg TIMER_CH_0: TIMER channel0 \arg TIMER_CH_1: TIMER channel1 \param[in] icpwm:TIMER channel intput pwm parameter struct - icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING - icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI - icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 + icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING + icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI + icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4, TIMER_IC_PSC_DIV8 icfilter: 0~15 \param[out] none \retval none */ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm) +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm) { uint16_t icpolarity = 0x0U; uint16_t icselection = 0x0U; /* Set channel input polarity */ - if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){ + if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity) { icpolarity = TIMER_IC_POLARITY_FALLING; - }else{ + } else { icpolarity = TIMER_IC_POLARITY_RISING; } /* Set channel input mode selection */ - if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){ + if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection) { icselection = TIMER_IC_SELECTION_INDIRECTTI; - }else{ + } else { icselection = TIMER_IC_SELECTION_DIRECTTI; } - if(TIMER_CH_0 == channel){ + if(TIMER_CH_0 == channel) { /* reset the CH0EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); /* reset the CH0P and CH0NP bits */ @@ -1474,50 +1475,50 @@ void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, tim /* set the CH0EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity<< 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U); /* reset the CH1MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection<< 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U); /* reset the CH1CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); /* set the CH1EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); - }else{ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); + } else { /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity)<< 4U); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U); /* reset the CH1MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection)<< 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U); /* reset the CH1CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); /* set the CH1EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); /* reset the CH0EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); /* set the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; /* reset the CH0MS bit */ @@ -1531,7 +1532,7 @@ void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, tim /* set the CH0EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); } } @@ -1545,44 +1546,48 @@ void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, tim \param[out] none \retval none */ -void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) { - if(TIMER_HALLINTERFACE_ENABLE == hallmode){ + if(TIMER_HALLINTERFACE_ENABLE == hallmode) { TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; - }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){ + } else if(TIMER_HALLINTERFACE_DISABLE == hallmode) { TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; - }else{ - /* illegal parameters */ + } else { + /* illegal parameters */ } } /*! - \brief select TIMER input trigger source + \brief select TIMER input trigger source \param[in] timer_periph: please refer to the following parameters \param[in] intrigger: only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0,TIMERx(x=0..4,7,8,11) - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1,TIMERx(x=0..4,7,8,11) - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2,TIMERx(x=0..4,7,8,11) - \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3,TIMERx(x=0..4,7,8,11) - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector,TIMERx(x=0..4,7,8,11) - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0,TIMERx(x=0..4,7,8,11) - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1,TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0, TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1, TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2, TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3, TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector, TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0, TIMERx(x=0..4,7,8,11) + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1, TIMERx(x=0..4,7,8,11) \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger,TIMERx(x=0..4,7) \param[out] none \retval none */ void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) { - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); - TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; + uint32_t reg; + + reg = TIMER_SMCFG(timer_periph); + reg &= (~(uint32_t)TIMER_SMCFG_TRGS); + reg |= (uint32_t)intrigger; + TIMER_SMCFG(timer_periph) = reg; } /*! - \brief select TIMER master mode output trigger source + \brief select TIMER master mode output trigger source \param[in] timer_periph: TIMERx(x=0..7) \param[in] outrigger: - only one parameter can be selected which is shown as below: + only one parameter can be selected which is shown as below: \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..7)) \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..7)) \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..7)) @@ -1601,14 +1606,14 @@ void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t o } /*! - \brief select TIMER slave mode + \brief select TIMER slave mode \param[in] timer_periph: TIMERx(x=0..4,7,8,11) \param[in] slavemode: only one parameter can be selected which is shown as below: \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable - \arg TIMER_ENCODER_MODE0: encoder mode 0 - \arg TIMER_ENCODER_MODE1: encoder mode 1 - \arg TIMER_ENCODER_MODE2: encoder mode 2 + \arg TIMER_QUAD_DECODER_MODE0: quadrature decoder mode 0 + \arg TIMER_QUAD_DECODER_MODE1: quadrature decoder mode 1 + \arg TIMER_QUAD_DECODER_MODE2: quadrature decoder mode 2 \arg TIMER_SLAVE_MODE_RESTART: restart mode \arg TIMER_SLAVE_MODE_PAUSE: pause mode \arg TIMER_SLAVE_MODE_EVENT: event mode @@ -1625,7 +1630,7 @@ void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) } /*! - \brief configure TIMER master slave mode + \brief configure TIMER master slave mode \param[in] timer_periph: TIMERx(x=0..4,7,8,11) \param[in] masterslave: only one parameter can be selected which is shown as below: @@ -1633,15 +1638,15 @@ void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable \param[out] none \retval none -*/ +*/ void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) { - if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){ + if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave) { TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; - }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){ + } else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave) { TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; - }else{ - /* illegal parameters */ + } else { + /* illegal parameters */ } } @@ -1662,7 +1667,7 @@ void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) \param[out] none \retval none */ -void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint8_t extfilter) +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) { TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); @@ -1671,12 +1676,12 @@ void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, /*! \brief configure TIMER quadrature decoder mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) + \param[in] timer_periph: TIMERx(x=0..4,7) \param[in] decomode: only one parameter can be selected which is shown as below: - \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level - \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level - \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input + \arg TIMER_QUAD_DECODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level + \arg TIMER_QUAD_DECODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level + \arg TIMER_QUAD_DECODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input \param[in] ic0polarity: only one parameter can be selected which is shown as below: \arg TIMER_IC_POLARITY_RISING: capture rising edge @@ -1716,7 +1721,7 @@ void timer_internal_clock_config(uint32_t timer_periph) /*! \brief configure TIMER the internal trigger as external clock input \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] intrigger: + \param[in] intrigger: only one parameter can be selected which is shown as below: \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 @@ -1727,7 +1732,7 @@ void timer_internal_clock_config(uint32_t timer_periph) */ void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) { - timer_input_trigger_source_select(timer_periph,intrigger); + timer_input_trigger_source_select(timer_periph, intrigger); TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; } @@ -1740,7 +1745,7 @@ void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 - \param[in] expolarity: + \param[in] extpolarity: only one parameter can be selected which is shown as below: \arg TIMER_IC_POLARITY_RISING: active high or rising edge active \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active @@ -1748,30 +1753,30 @@ void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint \param[out] none \retval none */ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint8_t extfilter) +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter) { - if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){ + if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger) { /* reset the CH1EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); /* set the CH1NP bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); /* reset the CH1MS bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI<< 8U); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U); /* reset the CH1CAPFLT bit */ TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); /* set the CH1CAPFLT bit */ TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U); /* set the CH1EN bit */ TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - }else{ + } else { /* reset the CH0EN bit */ TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); /* set the CH0P and CH0NP bits */ TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; /* reset the CH0MS bit */ @@ -1802,7 +1807,7 @@ void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] expolarity: + \param[in] extpolarity: only one parameter can be selected which is shown as below: \arg TIMER_ETP_FALLING: active low or falling edge active \arg TIMER_ETP_RISING: active high or rising edge active @@ -1810,14 +1815,17 @@ void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint \param[out] none \retval none */ -void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint8_t extfilter) +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) { + uint32_t reg = 0U; + reg = TIMER_SMCFG(timer_periph); + /* configure TIMER external trigger input */ timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); - /* reset the SMC bit,TRGS bit */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); - /* set the SMC bit,TRGS bit */ - TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); + /* set the SMC bit, TRGS bit */ + reg &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); + reg |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); + TIMER_SMCFG(timer_periph) = reg; } /*! @@ -1830,14 +1838,14 @@ void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extpresca \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 \param[in] extpolarity: - only one parameter can be selected which is shown as below: + only one parameter can be selected which is shown as below: \arg TIMER_ETP_FALLING: active low or falling edge active \arg TIMER_ETP_RISING: active high or rising edge active \param[in] extfilter: a value between 0 and 15 \param[out] none \retval none */ -void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint8_t extfilter) +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) { /* configure TIMER external trigger input */ timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); @@ -1855,9 +1863,64 @@ void timer_external_clock_mode1_disable(uint32_t timer_periph) TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; } + +/*! + \brief get TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) + \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) + \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CMT: channel commutation flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) +{ + if(RESET != (TIMER_INTF(timer_periph) & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) + \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) + \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) + \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) + \param[out] none + \retval none +*/ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag) +{ + TIMER_INTF(timer_periph) = (~(uint32_t)flag); +} + /*! \brief enable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters + \param[in] timer_periph: please refer to the following parameters \param[in] interrupt: timer interrupt enable source only one parameter can be selected which is shown as below: \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) @@ -1873,7 +1936,7 @@ void timer_external_clock_mode1_disable(uint32_t timer_periph) */ void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) { - TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; + TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; } /*! @@ -1894,32 +1957,32 @@ void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) */ void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) { - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); } /*! \brief get timer interrupt flag \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: the timer interrupt bits + \param[in] int_flag: the timer interrupt flag only one parameter can be selected which is shown as below: \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) \param[out] none \retval FlagStatus: SET or RESET */ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t int_flag) { uint32_t val; - val = (TIMER_DMAINTEN(timer_periph) & interrupt); - if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){ + val = (TIMER_DMAINTEN(timer_periph) & int_flag); + if((RESET != (TIMER_INTF(timer_periph) & int_flag)) && (RESET != val)) { return SET; - }else{ + } else { return RESET; } } @@ -1927,74 +1990,20 @@ FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) /*! \brief clear TIMER interrupt flag \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: the timer interrupt bits + \param[in] int_flag: the timer interrupt flag only one parameter can be selected which is shown as below: \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) \param[out] none \retval none */ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t int_flag) { - TIMER_INTF(timer_periph) = (~(uint32_t)interrupt); -} - -/*! - \brief get TIMER flags - \param[in] timer_periph: please refer to the following parameters - \param[in] flag: the timer interrupt flags - only one parameter can be selected which is shown as below: - \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) - \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) - \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CMT: channel commutation flag,TIMERx(x=0,7) - \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) - \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) - \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) - \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) -{ - if(RESET != (TIMER_INTF(timer_periph) & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear TIMER flags - \param[in] timer_periph: please refer to the following parameters - \param[in] flag: the timer interrupt flags - only one parameter can be selected which is shown as below: - \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) - \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) - \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) - \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) - \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) - \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) - \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag) -{ - TIMER_INTF(timer_periph) = (~(uint32_t)flag); + TIMER_INTF(timer_periph) = (~(uint32_t)int_flag); } diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_tli.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_tli.c index 9b1362ea..26dc3f0d 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_tli.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_tli.c @@ -2,43 +2,43 @@ \file gd32f20x_tli.c \brief TLI driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f20x_tli.h" +#define TLI_DEFAULT_VALUE 0x00000000U +#define TLI_OPAQUE_VALUE 0x000000FFU + /*! - \brief deinitialize TLI registers + \brief deinitialize TLI registers \param[in] none \param[out] none \retval none @@ -50,22 +50,64 @@ void tli_deinit(void) } /*! - \brief initialize TLI display timing parameters - \param[in] tli_struct: the data needed to initialize tli + \brief initialize the parameters of TLI parameter structure with the default values, it is suggested + that call this function after a tli_parameter_struct structure is defined + \param[in] none + \param[out] tli_struct: the data needed to initialize TLI synpsz_vpsz: size of the vertical synchronous pulse synpsz_hpsz: size of the horizontal synchronous pulse - backpsz_vbpsz: size of the vertical back porch plus synchronous pulse + backpsz_vbpsz: size of the vertical back porch plus synchronous pulse backpsz_hbpsz: size of the horizontal back porch plus synchronous pulse activesz_vasz: size of the vertical active area width plus back porch and synchronous pulse activesz_hasz: size of the horizontal active area width plus back porch and synchronous pulse - totalsz_vtsz: vertical total size of the display, including active area, back porch, synchronous + totalsz_vtsz: vertical total size of the display, including active area, back porch, synchronous totalsz_htsz: vorizontal total size of the display, including active area, back porch, synchronous backcolor_red: background value red backcolor_green: background value green backcolor_blue: background value blue - signalpolarity_hs: TLI_HSYN_ACTLIVE_LOW,TLI_HSYN_ACTLIVE_HIGHT - signalpolarity_vs: TLI_VSYN_ACTLIVE_LOW,TLI_VSYN_ACTLIVE_HIGHT - signalpolarity_de: TLI_DE_ACTLIVE_LOW,TLI_DE_ACTLIVE_HIGHT + signalpolarity_hs: TLI_HSYN_ACTLIVE_LOW,TLI_HSYN_ACTLIVE_HIGH + signalpolarity_vs: TLI_VSYN_ACTLIVE_LOW,TLI_VSYN_ACTLIVE_HIGH + signalpolarity_de: TLI_DE_ACTLIVE_LOW,TLI_DE_ACTLIVE_HIGH + signalpolarity_pixelck: TLI_PIXEL_CLOCK_TLI,TLI_PIXEL_CLOCK_INVERTEDTLI + \retval none +*/ +void tli_struct_para_init(tli_parameter_struct *tli_struct) +{ + /* initialize the struct parameters with default values */ + tli_struct->synpsz_vpsz = TLI_DEFAULT_VALUE; + tli_struct->synpsz_hpsz = TLI_DEFAULT_VALUE; + tli_struct->backpsz_vbpsz = TLI_DEFAULT_VALUE; + tli_struct->backpsz_hbpsz = TLI_DEFAULT_VALUE; + tli_struct->activesz_vasz = TLI_DEFAULT_VALUE; + tli_struct->activesz_hasz = TLI_DEFAULT_VALUE; + tli_struct->totalsz_vtsz = TLI_DEFAULT_VALUE; + tli_struct->totalsz_htsz = TLI_DEFAULT_VALUE; + tli_struct->backcolor_red = TLI_DEFAULT_VALUE; + tli_struct->backcolor_green = TLI_DEFAULT_VALUE; + tli_struct->backcolor_blue = TLI_DEFAULT_VALUE; + tli_struct->signalpolarity_hs = TLI_HSYN_ACTLIVE_LOW; + tli_struct->signalpolarity_vs = TLI_VSYN_ACTLIVE_LOW; + tli_struct->signalpolarity_de = TLI_DE_ACTLIVE_LOW; + tli_struct->signalpolarity_pixelck = TLI_PIXEL_CLOCK_TLI; +} + +/*! + \brief initialize TLI display timing parameters + \param[in] tli_struct: the data needed to initialize TLI + synpsz_vpsz: size of the vertical synchronous pulse + synpsz_hpsz: size of the horizontal synchronous pulse + backpsz_vbpsz: size of the vertical back porch plus synchronous pulse + backpsz_hbpsz: size of the horizontal back porch plus synchronous pulse + activesz_vasz: size of the vertical active area width plus back porch and synchronous pulse + activesz_hasz: size of the horizontal active area width plus back porch and synchronous pulse + totalsz_vtsz: vertical total size of the display, including active area, back porch, synchronous + totalsz_htsz: horizontal total size of the display, including active area, back porch, synchronous + backcolor_red: background value red + backcolor_green: background value green + backcolor_blue: background value blue + signalpolarity_hs: TLI_HSYN_ACTLIVE_LOW,TLI_HSYN_ACTLIVE_HIGH + signalpolarity_vs: TLI_VSYN_ACTLIVE_LOW,TLI_VSYN_ACTLIVE_HIGH + signalpolarity_de: TLI_DE_ACTLIVE_LOW,TLI_DE_ACTLIVE_HIGH signalpolarity_pixelck: TLI_PIXEL_CLOCK_TLI,TLI_PIXEL_CLOCK_INVERTEDTLI \param[out] none \retval none @@ -73,44 +115,45 @@ void tli_deinit(void) void tli_init(tli_parameter_struct *tli_struct) { /* synchronous pulse size configuration */ - TLI_SPSZ &= ~(TLI_SPSZ_VPSZ|TLI_SPSZ_HPSZ); - TLI_SPSZ = (tli_struct->synpsz_vpsz|(tli_struct->synpsz_hpsz<<16U)); + TLI_SPSZ &= ~(TLI_SPSZ_VPSZ | TLI_SPSZ_HPSZ); + TLI_SPSZ = (uint32_t)((uint32_t)tli_struct->synpsz_vpsz | ((uint32_t)tli_struct->synpsz_hpsz << 16U)); /* back-porch size configuration */ - TLI_BPSZ &= ~(TLI_BPSZ_VBPSZ|TLI_BPSZ_HBPSZ); - TLI_BPSZ = (tli_struct->backpsz_vbpsz|(tli_struct->backpsz_hbpsz<<16U)); - /* active size configuration */ - TLI_ASZ &= ~(TLI_ASZ_VASZ|TLI_ASZ_HASZ); - TLI_ASZ = (tli_struct->activesz_vasz|(tli_struct->activesz_hasz<<16U)); - /* total size configuration */ - TLI_TSZ &= ~(TLI_TSZ_VTSZ|TLI_TSZ_HTSZ); - TLI_TSZ = (tli_struct->totalsz_vtsz|(tli_struct->totalsz_htsz<<16U)); - /* background color configuration */ - TLI_BGC &= ~(TLI_BGC_BVB|(TLI_BGC_BVG)|(TLI_BGC_BVR)); - TLI_BGC = (tli_struct->backcolor_blue|(tli_struct->backcolor_green<<8U)|(tli_struct->backcolor_red<<16U)); - TLI_CTL &= ~(TLI_CTL_HPPS|TLI_CTL_VPPS|TLI_CTL_DEPS|TLI_CTL_CLKPS); - TLI_CTL |= (tli_struct->signalpolarity_hs|tli_struct->signalpolarity_vs|\ - tli_struct->signalpolarity_de|tli_struct->signalpolarity_pixelck); + TLI_BPSZ &= ~(TLI_BPSZ_VBPSZ | TLI_BPSZ_HBPSZ); + TLI_BPSZ = (uint32_t)((uint32_t)tli_struct->backpsz_vbpsz | ((uint32_t)tli_struct->backpsz_hbpsz << 16U)); + /* active size configuration */ + TLI_ASZ &= ~(TLI_ASZ_VASZ | TLI_ASZ_HASZ); + TLI_ASZ = (tli_struct->activesz_vasz | (tli_struct->activesz_hasz << 16U)); + /* total size configuration */ + TLI_TSZ &= ~(TLI_TSZ_VTSZ | TLI_TSZ_HTSZ); + TLI_TSZ = (tli_struct->totalsz_vtsz | (tli_struct->totalsz_htsz << 16U)); + /* background color configuration */ + TLI_BGC &= ~(TLI_BGC_BVB | (TLI_BGC_BVG) | (TLI_BGC_BVR)); + TLI_BGC = (tli_struct->backcolor_blue | (tli_struct->backcolor_green << 8U) | (tli_struct->backcolor_red << 16U)); + TLI_CTL &= ~(TLI_CTL_HPPS | TLI_CTL_VPPS | TLI_CTL_DEPS | TLI_CTL_CLKPS); + TLI_CTL |= (tli_struct->signalpolarity_hs | tli_struct->signalpolarity_vs | \ + tli_struct->signalpolarity_de | tli_struct->signalpolarity_pixelck); } /*! - \brief configure TLI dither function - \param[in] ditherstat + \brief configure TLI dither function + \param[in] dither_stat + only one parameter can be selected which is shown as below: \arg TLI_DITHER_ENABLE \arg TLI_DITHER_DISABLE \param[out] none \retval none */ -void tli_dither_config(uint8_t ditherstat) +void tli_dither_config(uint8_t dither_stat) { - if(TLI_DITHER_ENABLE == ditherstat){ + if(TLI_DITHER_ENABLE == dither_stat) { TLI_CTL |= TLI_CTL_DFEN; - }else{ + } else { TLI_CTL &= ~(TLI_CTL_DFEN); } } /*! - \brief TLI enable + \brief enable TLI \param[in] none \param[out] none \retval none @@ -121,7 +164,7 @@ void tli_enable(void) } /*! - \brief TLI disable + \brief disable TLI \param[in] none \param[out] none \retval none @@ -132,118 +175,78 @@ void tli_disable(void) } /*! - \brief configure TLI reload mode - \param[in] reloadmode + \brief configure TLI reload mode + \param[in] reload_mod + only one parameter can be selected which is shown as below: \arg TLI_FRAME_BLANK_RELOAD_EN \arg TLI_REQUEST_RELOAD_EN \param[out] none \retval none */ -void tli_reload_config(uint8_t reloadmode) +void tli_reload_config(uint8_t reload_mod) { - if(TLI_FRAME_BLANK_RELOAD_EN == reloadmode){ + if(TLI_FRAME_BLANK_RELOAD_EN == reload_mod) { + /* the layer configuration will be reloaded at frame blank */ TLI_RL |= TLI_RL_FBR; - }else{ + } else { + /* the layer configuration will be reloaded after this bit sets */ TLI_RL |= TLI_RL_RQR; } } /*! - \brief set line mark value - \param[in] linenum: line number - \param[out] none - \retval none -*/ -void tli_line_mark_set(uint32_t linenum) -{ - TLI_LM &= ~(TLI_LM_LM); - TLI_LM = linenum; -} - -/*! - \brief get current displayed position - \param[in] none - \param[out] none - \retval none -*/ -uint32_t tli_current_pos_get(void) -{ - return TLI_CPPOS; -} - -/*! - \brief TLI layer enable - \param[in] layerx: LAYERx(x=0,1) - \param[out] none - \retval none -*/ -void tli_layer_enable(uint32_t layerx) -{ - TLI_LxCTL(layerx) |= TLI_LxCTL_LEN; -} - -/*! - \brief TLI layer disable - \param[in] layerx: LAYERx(x=0,1) - \param[out] none - \retval none -*/ -void tli_layer_disable(uint32_t layerx) -{ - TLI_LxCTL(layerx) &= ~(TLI_LxCTL_LEN); -} - -/*! - \brief TLI layer color keying enable - \param[in] layerx: LAYERx(x=0,1) - \param[out] none - \retval none -*/ -void tli_color_key_enable(uint32_t layerx) -{ - TLI_LxCTL(layerx) |= TLI_LxCTL_CKEYEN; -} - -/*! - \brief TLI layer color keying disable - \param[in] layerx: LAYERx(x=0,1) - \param[out] none - \retval none -*/ -void tli_color_key_disable(uint32_t layerx) -{ - TLI_LxCTL(layerx) &= ~(TLI_LxCTL_CKEYEN); -} - -/*! - \brief TLI layer LUT enable - \param[in] layerx: LAYERx(x=0,1) - \param[out] none - \retval none -*/ -void tli_lut_enable(uint32_t layerx) -{ - TLI_LxCTL(layerx) |= TLI_LxCTL_LUTEN; -} - -/*! - \brief TLI layer LUT disable - \param[in] layerx: LAYERx(x=0,1) - \param[out] none + \brief initialize the parameters of TLI layer structure with the default values, it is suggested + that call this function after a tli_layer_parameter_struct structure is defined + \param[in] none + \param[out] layer_struct: TLI Layer parameter struct + layer_window_rightpos: window right position + layer_window_leftpos: window left position + layer_window_bottompos: window bottom position + layer_window_toppos: window top position + layer_ppf: LAYER_PPF_ARGB8888,LAYER_PPF_RGB888,LAYER_PPF_RGB565, + LAYER_PPF_ARG1555,LAYER_PPF_ARGB4444,LAYER_PPF_L8, + LAYER_PPF_AL44,LAYER_PPF_AL88 + layer_sa: specified alpha + layer_default_alpha: the default color alpha + layer_default_red: the default color red + layer_default_green: the default color green + layer_default_blue: the default color blue + layer_acf1: LAYER_ACF1_SA,LAYER_ACF1_PASA + layer_acf2: LAYER_ACF2_SA,LAYER_ACF2_PASA + layer_frame_bufaddr: frame buffer base address + layer_frame_buf_stride_offset: frame buffer stride offset + layer_frame_line_length: frame line length + layer_frame_total_line_number: frame total line number \retval none */ -void tli_lut_disable(uint32_t layerx) +void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct) { - TLI_LxCTL(layerx) &= ~(TLI_LxCTL_LUTEN); + /* initialize the struct parameters with default values */ + layer_struct->layer_window_rightpos = TLI_DEFAULT_VALUE; + layer_struct->layer_window_leftpos = TLI_DEFAULT_VALUE; + layer_struct->layer_window_bottompos = TLI_DEFAULT_VALUE; + layer_struct->layer_window_toppos = TLI_DEFAULT_VALUE; + layer_struct->layer_ppf = LAYER_PPF_ARGB8888; + layer_struct->layer_sa = TLI_OPAQUE_VALUE; + layer_struct->layer_default_alpha = TLI_DEFAULT_VALUE; + layer_struct->layer_default_red = TLI_DEFAULT_VALUE; + layer_struct->layer_default_green = TLI_DEFAULT_VALUE; + layer_struct->layer_default_blue = TLI_DEFAULT_VALUE; + layer_struct->layer_acf1 = LAYER_ACF1_PASA; + layer_struct->layer_acf2 = LAYER_ACF2_PASA; + layer_struct->layer_frame_bufaddr = TLI_DEFAULT_VALUE; + layer_struct->layer_frame_buf_stride_offset = TLI_DEFAULT_VALUE; + layer_struct->layer_frame_line_length = TLI_DEFAULT_VALUE; + layer_struct->layer_frame_total_line_number = TLI_DEFAULT_VALUE; } /*! - \brief TLI layer initialize + \brief initialize TLI layer \param[in] layerx: LAYERx(x=0,1) \param[in] layer_struct: TLI Layer parameter struct layer_window_rightpos: window right position layer_window_leftpos: window left position - layer_window_bottompos: window bottom position + layer_window_bottompos: window bottom position layer_window_toppos: window top position layer_ppf: LAYER_PPF_ARGB8888,LAYER_PPF_RGB888,LAYER_PPF_RGB565, LAYER_PPF_ARG1555,LAYER_PPF_ARGB4444,LAYER_PPF_L8, @@ -262,14 +265,14 @@ void tli_lut_disable(uint32_t layerx) \param[out] none \retval none */ -void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct) +void tli_layer_init(uint32_t layerx, tli_layer_parameter_struct *layer_struct) { /* configure layer window horizontal position */ - TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP|(TLI_LxHPOS_WRP)); - TLI_LxHPOS(layerx) = (layer_struct->layer_window_leftpos | (layer_struct->layer_window_rightpos<<16U)); + TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP | (TLI_LxHPOS_WRP)); + TLI_LxHPOS(layerx) = (uint32_t)((uint32_t)layer_struct->layer_window_leftpos | ((uint32_t)layer_struct->layer_window_rightpos << 16U)); /* configure layer window vertical position */ - TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP|(TLI_LxVPOS_WBP)); - TLI_LxVPOS(layerx) = (layer_struct->layer_window_toppos |(layer_struct->layer_window_bottompos<<16U)); + TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP | (TLI_LxVPOS_WBP)); + TLI_LxVPOS(layerx) = (uint32_t)((uint32_t)layer_struct->layer_window_toppos | ((uint32_t)layer_struct->layer_window_bottompos << 16U)); /* configure layer packeted pixel format */ TLI_LxPPF(layerx) &= ~(TLI_LxPPF_PPF); TLI_LxPPF(layerx) = layer_struct->layer_ppf; @@ -277,173 +280,252 @@ void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct) TLI_LxSA(layerx) &= ~(TLI_LxSA_SA); TLI_LxSA(layerx) = layer_struct->layer_sa; /* configure layer default color */ - TLI_LxDC(layerx) &= ~(TLI_LxDC_DCB|(TLI_LxDC_DCG)|(TLI_LxDC_DCR)|(TLI_LxDC_DCA)); - TLI_LxDC(layerx) = (layer_struct->layer_default_blue |(layer_struct->layer_default_green<<8U) - |(layer_struct->layer_default_red<<16U) - |(layer_struct->layer_default_alpha<<24U)); + TLI_LxDC(layerx) &= ~(TLI_LxDC_DCB | (TLI_LxDC_DCG) | (TLI_LxDC_DCR) | (TLI_LxDC_DCA)); + TLI_LxDC(layerx) = (uint32_t)((uint32_t)layer_struct->layer_default_blue | ((uint32_t)layer_struct->layer_default_green << 8U) + | ((uint32_t)layer_struct->layer_default_red << 16U) + | ((uint32_t)layer_struct->layer_default_alpha << 24U)); /* configure layer alpha calculation factors */ - TLI_LxBLEND(layerx) &= ~(TLI_LxBLEND_ACF2|(TLI_LxBLEND_ACF1)); - TLI_LxBLEND(layerx) = ((layer_struct->layer_acf2)|(layer_struct->layer_acf1)); + TLI_LxBLEND(layerx) &= ~(TLI_LxBLEND_ACF2 | (TLI_LxBLEND_ACF1)); + TLI_LxBLEND(layerx) = ((layer_struct->layer_acf2) | (layer_struct->layer_acf1)); /* configure layer frame buffer base address */ TLI_LxFBADDR(layerx) &= ~(TLI_LxFBADDR_FBADD); TLI_LxFBADDR(layerx) = (layer_struct->layer_frame_bufaddr); /* configure layer frame line length */ - TLI_LxFLLEN(layerx) &= ~(TLI_LxFLLEN_FLL|(TLI_LxFLLEN_STDOFF)); - TLI_LxFLLEN(layerx) = (layer_struct->layer_frame_line_length|(layer_struct->layer_frame_buf_stride_offset<<16U)); - /* configure layer frame buffer base address */ - TLI_LxFBADDR(layerx) &= ~(TLI_LxFBADDR_FBADD); - TLI_LxFBADDR(layerx) = (layer_struct->layer_frame_bufaddr); + TLI_LxFLLEN(layerx) &= ~(TLI_LxFLLEN_FLL | (TLI_LxFLLEN_STDOFF)); + TLI_LxFLLEN(layerx) = (uint32_t)((uint32_t)layer_struct->layer_frame_line_length | ((uint32_t)layer_struct->layer_frame_buf_stride_offset << 16U)); /* configure layer frame total line number */ - TLI_LxFTLN(layerx) &= ~(TLI_LxFTLN_FTLN); - TLI_LxFTLN(layerx) = (layer_struct->layer_frame_total_line_number); + TLI_LxFTLN(layerx) &= ~(TLI_LxFTLN_FTLN); + TLI_LxFTLN(layerx) = (uint32_t)(layer_struct->layer_frame_total_line_number); + } /*! - \brief reconfigure window position - \param[in] layerx: LAYERx(x=0,1) - \param[in] offset_x: new horizontal offset - \param[in] offset_y: new vertical offset + \brief reconfigure window position + \param[in] layerx: LAYERx(x=0,1) + \param[in] offset_x: new horizontal offset + \param[in] offset_y: new vertical offset \param[out] none \retval none */ -void tli_layer_window_offset_modify(uint32_t layerx,uint32_t offset_x,uint32_t offset_y) +void tli_layer_window_offset_modify(uint32_t layerx, uint16_t offset_x, uint16_t offset_y) { /* configure window start position */ - uint32_t layer_ppf,line_length,line_num,hstart,vstart; - TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP|(TLI_LxHPOS_WRP)); - TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP|(TLI_LxVPOS_WBP)); - hstart = offset_x+(((TLI_BPSZ & TLI_BPSZ_HBPSZ)>>16U)+1U); - vstart = offset_y+((TLI_BPSZ & TLI_BPSZ_VBPSZ)+1U); + uint32_t layer_ppf, line_num, hstart, vstart; + uint32_t line_length = 0U; + TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP | (TLI_LxHPOS_WRP)); + TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP | (TLI_LxVPOS_WBP)); + hstart = (uint32_t)offset_x + (((TLI_BPSZ & TLI_BPSZ_HBPSZ) >> 16U) + 1U); + vstart = (uint32_t)offset_y + ((TLI_BPSZ & TLI_BPSZ_VBPSZ) + 1U); line_num = (TLI_LxFTLN(layerx) & TLI_LxFTLN_FTLN); layer_ppf = (TLI_LxPPF(layerx) & TLI_LxPPF_PPF); /* the bytes of a line equal TLI_LxFLLEN_FLL bits value minus 3 */ - switch(layer_ppf){ + switch(layer_ppf) { case LAYER_PPF_ARGB8888: /* each pixel includes 4bytes,when pixel format is ARGB8888 */ - line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/4U); + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL) - 3U) / 4U); break; case LAYER_PPF_RGB888: /* each pixel includes 3bytes,when pixel format is RGB888 */ - line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/3U); + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL) - 3U) / 3U); break; case LAYER_PPF_RGB565: case LAYER_PPF_ARGB1555: case LAYER_PPF_ARGB4444: case LAYER_PPF_AL88: /* each pixel includes 2bytes,when pixel format is RGB565,ARG1555,ARGB4444 or AL88 */ - line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/2U); + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL) - 3U) / 2U); break; case LAYER_PPF_L8: case LAYER_PPF_AL44: /* each pixel includes 1byte,when pixel format is L8 or AL44 */ - line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)); + line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL) - 3U)); break; default: break; } /* reconfigure window position */ - TLI_LxHPOS(layerx) = (hstart|((hstart+line_length-1U)<<16U)); - TLI_LxVPOS(layerx) = (vstart|((vstart+line_num-1U)<<16U)); + TLI_LxHPOS(layerx) = (hstart | ((hstart + line_length - 1U) << 16U)); + TLI_LxVPOS(layerx) = (vstart | ((vstart + line_num - 1U) << 16U)); } /*! - \brief TLI layer LUT initialize + \brief initialize the parameters of TLI layer LUT structure with the default values, it is suggested + that call this function after a tli_layer_lut_parameter_struct structure is defined + \param[in] none + \param[out] lut_struct: TLI layer LUT parameter struct + layer_table_addr: look up table write address + layer_lut_channel_red: red channel of a LUT entry + layer_lut_channel_green: green channel of a LUT entry + layer_lut_channel_blue: blue channel of a LUT entry + \retval none +*/ +void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct) +{ + /* initialize the struct parameters with default values */ + lut_struct->layer_table_addr = TLI_DEFAULT_VALUE; + lut_struct->layer_lut_channel_red = TLI_DEFAULT_VALUE; + lut_struct->layer_lut_channel_green = TLI_DEFAULT_VALUE; + lut_struct->layer_lut_channel_blue = TLI_DEFAULT_VALUE; +} + +/*! + \brief initialize TLI layer LUT \param[in] layerx: LAYERx(x=0,1) \param[in] lut_struct: TLI layer LUT parameter struct layer_table_addr: window right position layer_lut_channel_red: window left position - layer_window_bottompos: window bottom position + layer_window_bottompos: window bottom position layer_window_toppos: window top position \param[out] none \retval none */ -void tli_lut_init(uint32_t layerx,tli_layer_lut_parameter_struct *lut_struct) +void tli_lut_init(uint32_t layerx, tli_layer_lut_parameter_struct *lut_struct) { - TLI_LxLUT(layerx) &= ~(TLI_LxLUT_TB|TLI_LxLUT_TG|TLI_LxLUT_TR|TLI_LxLUT_TADD); - TLI_LxLUT(layerx) = ((lut_struct->layer_lut_channel_blue)|(lut_struct->layer_lut_channel_green<<8) - |(lut_struct->layer_lut_channel_red<<16 - |(lut_struct->layer_table_addr<<24))); + TLI_LxLUT(layerx) = (uint32_t)(((uint32_t)lut_struct->layer_lut_channel_blue) | ((uint32_t)lut_struct->layer_lut_channel_green << 8U) + | ((uint32_t)lut_struct->layer_lut_channel_red << 16U + | ((uint32_t)lut_struct->layer_table_addr << 24U))); } /*! - \brief TLI layer key initialize - \param[in] layerx: LAYERx(x=0,1) - \param[in] redkey: color key red - \param[in] greenkey: color key green - \param[in] bluekey: color key blue + \brief initialize TLI layer color key + \param[in] layerx: LAYERx(x=0,1) + \param[in] redkey: color key red + \param[in] greenkey: color key green + \param[in] bluekey: color key blue \param[out] none \retval none */ -void tli_ckey_init(uint32_t layerx,uint32_t redkey,uint32_t greenkey,uint32_t bluekey) +void tli_color_key_init(uint32_t layerx, uint8_t redkey, uint8_t greenkey, uint8_t bluekey) { - TLI_LxCKEY(layerx) = ((bluekey)|(greenkey<<8U)|(redkey<<16U)); + TLI_LxCKEY(layerx) = (((uint32_t)bluekey) | ((uint32_t)greenkey << 8U) | ((uint32_t)redkey << 16U)); } /*! - \brief get TLI flag or state - \param[in] flag: TLI flags or states - \arg TLI_FLAG_VDE: current VDE state - \arg TLI_FLAG_HDE: current HDE state - \arg TLI_FLAG_VS: current vs state - \arg TLI_FLAG_HS: current hs state - \arg TLI_FLAG_LM: line mark interrupt flag - \arg TLI_FLAG_FE: FIFO error interrupt flag - \arg TLI_FLAG_TE: transaction error interrupt flag - \arg TLI_FLAG_LCR: layer configuration reloaded interrupt flag + \brief enable TLI layer + \param[in] layerx: LAYERx(x=0,1) \param[out] none - \retval FlagStatus: SET or RESET + \retval none */ -FlagStatus tli_flag_get(uint32_t flag) +void tli_layer_enable(uint32_t layerx) { - uint32_t stat; - if(flag >> 31){ - /* get flag status from TLI_INTF register */ - stat = TLI_INTF; - }else{ - /* get flag status from TLI_STAT register */ - stat = TLI_STAT; - } - if(flag & stat){ - return SET; - }else{ - return RESET; - } + TLI_LxCTL(layerx) |= TLI_LxCTL_LEN; } /*! - \brief enable TLI interrupt - \param[in] interrupt: TLI interrupt flags - \arg TLI_INT_LM: line mark interrupt - \arg TLI_INT_FE: FIFO error interrupt - \arg TLI_INT_TE: transaction error interrupt - \arg TLI_INT_LCR: layer configuration reloaded interrupt + \brief disable TLI layer + \param[in] layerx: LAYERx(x=0,1) \param[out] none \retval none */ -void tli_interrupt_enable(uint32_t interrupt) +void tli_layer_disable(uint32_t layerx) { - TLI_INTEN |= (interrupt); + TLI_LxCTL(layerx) &= ~(TLI_LxCTL_LEN); } /*! - \brief disable TLI interrupt - \param[in] interrupt: TLI interrupt flags - \arg TLI_INT_LM: line mark interrupt - \arg TLI_INT_FE: FIFO error interrupt - \arg TLI_INT_TE: transaction error interrupt - \arg TLI_INT_LCR: layer configuration reloaded interrupt + \brief enable TLI layer color keying + \param[in] layerx: LAYERx(x=0,1) \param[out] none \retval none */ -void tli_interrupt_disable(uint32_t interrupt) +void tli_color_key_enable(uint32_t layerx) { - TLI_INTEN &= ~(interrupt); + TLI_LxCTL(layerx) |= TLI_LxCTL_CKEYEN; } /*! - \brief get TLI interrupt flag + \brief disable TLI layer color keying + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_color_key_disable(uint32_t layerx) +{ + TLI_LxCTL(layerx) &= ~(TLI_LxCTL_CKEYEN); +} + +/*! + \brief enable TLI layer LUT + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_lut_enable(uint32_t layerx) +{ + TLI_LxCTL(layerx) |= TLI_LxCTL_LUTEN; +} + +/*! + \brief disable TLI layer LUT + \param[in] layerx: LAYERx(x=0,1) + \param[out] none + \retval none +*/ +void tli_lut_disable(uint32_t layerx) +{ + TLI_LxCTL(layerx) &= ~(TLI_LxCTL_LUTEN); +} + +/*! + \brief set line mark value + \param[in] line_num: line number + \param[out] none + \retval none +*/ +void tli_line_mark_set(uint16_t line_num) +{ + TLI_LM &= ~(TLI_LM_LM); + TLI_LM = (uint32_t)line_num; +} + +/*! + \brief get current displayed position + \param[in] none + \param[out] none + \retval position of current pixel +*/ +uint32_t tli_current_pos_get(void) +{ + return TLI_CPPOS; +} + +/*! + \brief enable TLI interrupt + \param[in] int_flag: TLI interrupt flags + one or more parameters can be selected which are shown as below: + \arg TLI_INT_LM: line mark interrupt + \arg TLI_INT_FE: FIFO error interrupt + \arg TLI_INT_TE: transaction error interrupt + \arg TLI_INT_LCR: layer configuration reloaded interrupt + \param[out] none + \retval none +*/ +void tli_interrupt_enable(uint32_t int_flag) +{ + TLI_INTEN |= (int_flag); +} + +/*! + \brief disable TLI interrupt \param[in] int_flag: TLI interrupt flags + one or more parameters can be selected which are shown as below: + \arg TLI_INT_LM: line mark interrupt + \arg TLI_INT_FE: FIFO error interrupt + \arg TLI_INT_TE: transaction error interrupt + \arg TLI_INT_LCR: layer configuration reloaded interrupt + \param[out] none + \retval none +*/ +void tli_interrupt_disable(uint32_t int_flag) +{ + TLI_INTEN &= ~(int_flag); +} + +/*! + \brief get TLI interrupt flag + \param[in] int_flag: TLI interrupt flags + one or more parameters can be selected which are shown as below: \arg TLI_INT_FLAG_LM: line mark interrupt flag \arg TLI_INT_FLAG_FE: FIFO error interrupt flag \arg TLI_INT_FLAG_TE: transaction error interrupt flag @@ -455,10 +537,10 @@ FlagStatus tli_interrupt_flag_get(uint32_t int_flag) { uint32_t state; state = TLI_INTF; - if(state & int_flag){ + if(state & int_flag) { state = TLI_INTEN; /* check whether the corresponding bit in TLI_INTEN is set or not */ - if(state & int_flag){ + if(state & int_flag) { return SET; } } @@ -466,8 +548,9 @@ FlagStatus tli_interrupt_flag_get(uint32_t int_flag) } /*! - \brief clear TLI interrupt flag + \brief clear TLI interrupt flag \param[in] int_flag: TLI interrupt flags + one or more parameters can be selected which are shown as below: \arg TLI_INT_FLAG_LM: line mark interrupt flag \arg TLI_INT_FLAG_FE: FIFO error interrupt flag \arg TLI_INT_FLAG_TE: transaction error interrupt flag @@ -479,3 +562,34 @@ void tli_interrupt_flag_clear(uint32_t int_flag) { TLI_INTC |= (int_flag); } + +/*! + \brief get TLI flag or state in TLI_INTF register or TLI_STAT register + \param[in] flag: TLI flags or states + only one parameter can be selected which is shown as below: + \arg TLI_FLAG_VDE: current VDE state + \arg TLI_FLAG_HDE: current HDE state + \arg TLI_FLAG_VS: current VS status of the TLI + \arg TLI_FLAG_HS: current HS status of the TLI + \arg TLI_FLAG_LM: line mark interrupt flag + \arg TLI_FLAG_FE: FIFO error interrupt flag + \arg TLI_FLAG_TE: transaction error interrupt flag + \arg TLI_FLAG_LCR: layer configuration reloaded interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus tli_flag_get(uint32_t flag) +{ + uint32_t stat; + /* choose which register to get flag or state */ + if(flag >> 31U) { + stat = TLI_INTF; + } else { + stat = TLI_STAT; + } + if(flag & stat) { + return SET; + } else { + return RESET; + } +} diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_trng.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_trng.c index 0e098a56..35f5bb1c 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_trng.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_trng.c @@ -2,43 +2,40 @@ \file gd32f20x_trng.c \brief TRNG driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f20x_trng.h" /*! - \brief deinitialize the TRNG + \brief reset TRNG \param[in] none \param[out] none \retval none @@ -50,7 +47,7 @@ void trng_deinit(void) } /*! - \brief enable the TRNG interface + \brief enable TRNG \param[in] none \param[out] none \retval none @@ -61,7 +58,7 @@ void trng_enable(void) } /*! - \brief disable the TRNG interface + \brief disable TRNG \param[in] none \param[out] none \retval none @@ -75,7 +72,7 @@ void trng_disable(void) \brief get the true random data \param[in] none \param[out] none - \retval the generated random data + \retval the generated random data: 0 - 0xFFFFFFFF */ uint32_t trng_get_true_random_data(void) { @@ -83,7 +80,7 @@ uint32_t trng_get_true_random_data(void) } /*! - \brief get the trng status flags + \brief get TRNG flag status \param[in] flag: trng status flag, refer to trng_flag_enum only one parameter can be selected which is shown as below: \arg TRNG_FLAG_DRDY: Random Data ready status @@ -94,37 +91,37 @@ uint32_t trng_get_true_random_data(void) */ FlagStatus trng_flag_get(trng_flag_enum flag) { - if(RESET != (TRNG_STAT & flag)){ + if(RESET != (TRNG_STAT & flag)) { return SET; - }else{ + } else { return RESET; } } /*! - \brief enable the TRNG interrupt + \brief enable TRNG interrupt \param[in] none \param[out] none \retval none */ -void trng_interrupt_enable(void) +void trng_interrupt_enable(void) { - TRNG_CTL |= TRNG_CTL_IE; + TRNG_CTL |= TRNG_CTL_TRNGIE; } /*! - \brief disable the TRNG interrupt + \brief disable TRNG interrupt \param[in] none \param[out] none \retval none */ void trng_interrupt_disable(void) { - TRNG_CTL &= ~TRNG_CTL_IE; + TRNG_CTL &= ~TRNG_CTL_TRNGIE; } /*! - \brief get the trng interrupt flags + \brief get TRNG interrupt flag status \param[in] int_flag: trng interrupt flag, refer to trng_int_flag_enum only one parameter can be selected which is shown as below: \arg TRNG_INT_FLAG_CE: clock error interrupt flag @@ -134,15 +131,15 @@ void trng_interrupt_disable(void) */ FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag) { - if(RESET != (TRNG_STAT & int_flag)){ + if(RESET != (TRNG_STAT & int_flag)) { return SET; - }else{ + } else { return RESET; } } /*! - \brief clear the trng interrupt flags + \brief clear TRNG interrupt flag status \param[in] int_flag: trng interrupt flag, refer to trng_int_flag_enum only one parameter can be selected which is shown as below: \arg TRNG_INT_FLAG_CE: clock error interrupt flag diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_usart.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_usart.c index 1674afa9..2c829132 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_usart.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_usart.c @@ -2,51 +2,52 @@ \file gd32f20x_usart.c \brief USART driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x - \version 2019-04-11, V2.1.1, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f20x_usart.h" +/* USART register bit offset */ +#define GP_GUAT_OFFSET ((uint32_t)8U) /* bit offset of GUAT in USART_GP */ +#define CTL3_SCRTNUM_OFFSET ((uint32_t)1U) /* bit offset of SCRTNUM in USART_CTL3 */ +#define RT_BL_OFFSET ((uint32_t)24U) /* bit offset of BL in USART_RT */ + /*! - \brief reset USART/UART + \brief reset USART/UART \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none */ void usart_deinit(uint32_t usart_periph) { - switch(usart_periph){ + switch(usart_periph) { case USART0: /* reset USART0 */ rcu_periph_reset_enable(RCU_USART0RST); @@ -98,80 +99,80 @@ void usart_deinit(uint32_t usart_periph) \param[in] baudval: baud rate value \param[out] none \retval none -*/ +*/ void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) { - uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U; - switch(usart_periph){ - /* get clock frequency */ + uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U; + switch(usart_periph) { + /* get clock frequency */ case USART0: - /* get USART0 clock */ - uclk=rcu_clock_freq_get(CK_APB2); - break; + /* get USART0 clock */ + uclk = rcu_clock_freq_get(CK_APB2); + break; case USART5: - /* get USART5 clock */ - uclk=rcu_clock_freq_get(CK_APB2); - break; + /* get USART5 clock */ + uclk = rcu_clock_freq_get(CK_APB2); + break; case USART1: - /* get USART1 clock */ - uclk=rcu_clock_freq_get(CK_APB1); - break; + /* get USART1 clock */ + uclk = rcu_clock_freq_get(CK_APB1); + break; case USART2: - /* get USART2 clock */ - uclk=rcu_clock_freq_get(CK_APB1); - break; + /* get USART2 clock */ + uclk = rcu_clock_freq_get(CK_APB1); + break; case UART3: - /* get UART3 clock */ - uclk=rcu_clock_freq_get(CK_APB1); - break; + /* get UART3 clock */ + uclk = rcu_clock_freq_get(CK_APB1); + break; case UART4: - /* get UART4 clock */ - uclk=rcu_clock_freq_get(CK_APB1); - break; + /* get UART4 clock */ + uclk = rcu_clock_freq_get(CK_APB1); + break; case UART6: - /* get UART6 clock */ - uclk=rcu_clock_freq_get(CK_APB1); - break; + /* get UART6 clock */ + uclk = rcu_clock_freq_get(CK_APB1); + break; case UART7: - /* get UART7 clock */ - uclk=rcu_clock_freq_get(CK_APB1); - break; + /* get UART7 clock */ + uclk = rcu_clock_freq_get(CK_APB1); + break; default: - break; + break; } - /* when oversampling by 16, configure the value of USART_BAUD */ - udiv = (uclk+baudval/2U)/baudval; + /* oversampling by 16, configure the value of USART_BAUD */ + udiv = (uclk + baudval / 2U) / baudval; intdiv = udiv & 0xfff0U; fradiv = udiv & 0xfU; USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); } /*! - \brief configure USART parity - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] paritycfg: configure USART parity - only one parameter can be selected which is shown as below: - \arg USART_PM_NONE: no parity - \arg USART_PM_ODD: odd parity - \arg USART_PM_EVEN: even parity + \brief configure USART parity + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] paritycfg: configure USART parity + only one parameter can be selected which is shown as below: + \arg USART_PM_NONE: no parity + \arg USART_PM_ODD: odd parity + \arg USART_PM_EVEN: even parity \param[out] none \retval none */ void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) { - /* clear USART_CTL0 PM,PCEN Bits */ + /* clear USART_CTL0 PM,PCEN bits */ USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); /* configure USART parity mode */ USART_CTL0(usart_periph) |= paritycfg; } /*! - \brief configure USART word length - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] wlen: USART word length configure - only one parameter can be selected which is shown as below: - \arg USART_WL_8BIT: 8 bits - \arg USART_WL_9BIT: 9 bits + \brief configure USART word length + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] wlen: USART word length configure + only one parameter can be selected which is shown as below: + \arg USART_WL_8BIT: 8 bits + \arg USART_WL_9BIT: 9 bits \param[out] none \retval none */ @@ -184,11 +185,11 @@ void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) } /*! - \brief configure USART stop bit length - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] stblen: USART stop bit configure - only one parameter can be selected which is shown as below: - \arg USART_STB_1BIT: 1 bit + \brief configure USART stop bit length + \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) + \param[in] stblen: USART stop bit configure + only one parameter can be selected which is shown as below: + \arg USART_STB_1BIT: 1 bit \arg USART_STB_0_5BIT: 0.5 bit(not available for UARTx(x=3,4,6,7)) \arg USART_STB_2BIT: 2 bits \arg USART_STB_1_5BIT: 1.5 bits(not available for UARTx(x=3,4,6,7)) @@ -198,10 +199,11 @@ void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) { /* clear USART_CTL1 STB bits */ - USART_CTL1(usart_periph) &= ~USART_CTL1_STB; + USART_CTL1(usart_periph) &= ~USART_CTL1_STB; /* configure USART stop bits */ USART_CTL1(usart_periph) |= stblen; } + /*! \brief enable USART \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) @@ -230,19 +232,14 @@ void usart_disable(uint32_t usart_periph) \param[in] txconfig: enable or disable USART transmitter only one parameter can be selected which is shown as below: \arg USART_TRANSMIT_ENABLE: enable USART transmission - \arg USART_TRANSMIT_DISABLE: enable USART transmission + \arg USART_TRANSMIT_DISABLE: disable USART transmission \param[out] none \retval none */ void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) { - uint32_t ctl = 0U; - - ctl = USART_CTL0(usart_periph); - ctl &= ~USART_CTL0_TEN; - ctl |= txconfig; - /* configure transfer mode */ - USART_CTL0(usart_periph) = ctl; + USART_CTL0(usart_periph) &= ~(USART_CTL0_TEN); + USART_CTL0(usart_periph) |= (USART_CTL0_TEN & txconfig); } /*! @@ -257,19 +254,15 @@ void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) */ void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) { - uint32_t ctl = 0U; - - ctl = USART_CTL0(usart_periph); - ctl &= ~USART_CTL0_REN; - ctl |= rxconfig; - /* configure receiver mode */ - USART_CTL0(usart_periph) = ctl; + USART_CTL0(usart_periph) &= ~(USART_CTL0_REN); + USART_CTL0(usart_periph) |= (USART_CTL0_REN & rxconfig); } /*! \brief data is transmitted/received with the LSB/MSB first \param[in] usart_periph: USARTx(x=0,1,2,5) \param[in] msbf: LSB/MSB + only one parameter can be selected which is shown as below: \arg USART_MSBF_LSB: LSB first \arg USART_MSBF_MSB: MSB first \param[out] none @@ -277,14 +270,15 @@ void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) */ void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) { - USART_CTL3(usart_periph) &= ~(USART_CTL3_MSBF); + USART_CTL3(usart_periph) &= ~(USART_CTL3_MSBF); USART_CTL3(usart_periph) |= msbf; } /*! \brief configure USART inversion \param[in] usart_periph: USARTx(x=0,1,2,5) - \param[in] invertpara: refer to enum USART_INVERT_CONFIG + \param[in] invertpara: refer to enum usart_invert_enum + only one parameter can be selected which is shown as below: \arg USART_DINV_ENABLE: data bit level inversion \arg USART_DINV_DISABLE: data bit level not inversion \arg USART_TXPIN_ENABLE: TX pin level inversion @@ -296,24 +290,30 @@ void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) */ void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) { - /* inverted or not the specified siginal */ - switch(invertpara){ + /* inverted or not the specified siginal */ + switch(invertpara) { case USART_DINV_ENABLE: + /* data bit level inversion */ USART_CTL3(usart_periph) |= USART_CTL3_DINV; break; case USART_TXPIN_ENABLE: + /* TX pin level inversion */ USART_CTL3(usart_periph) |= USART_CTL3_TINV; break; case USART_RXPIN_ENABLE: + /* RX pin level inversion */ USART_CTL3(usart_periph) |= USART_CTL3_RINV; break; case USART_DINV_DISABLE: + /* data bit level not inversion */ USART_CTL3(usart_periph) &= ~(USART_CTL3_DINV); break; case USART_TXPIN_DISABLE: + /* TX pin level not inversion */ USART_CTL3(usart_periph) &= ~(USART_CTL3_TINV); break; case USART_RXPIN_DISABLE: + /* RX pin level not inversion */ USART_CTL3(usart_periph) &= ~(USART_CTL3_RINV); break; default: @@ -322,7 +322,7 @@ void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) } /*! - \brief enable receiver timeout of USART + \brief enable receiver timeout \param[in] usart_periph: USARTx(x=0,1,2,5) \param[out] none \retval none @@ -333,7 +333,7 @@ void usart_receiver_timeout_enable(uint32_t usart_periph) } /*! - \brief disable receiver timeout of USART + \brief disable receiver timeout \param[in] usart_periph: USARTx(x=0,1,2,5) \param[out] none \retval none @@ -344,7 +344,7 @@ void usart_receiver_timeout_disable(uint32_t usart_periph) } /*! - \brief set the receiver timeout threshold of USART + \brief configure receiver timeout threshold \param[in] usart_periph: USARTx(x=0,1,2,5) \param[in] rtimeout: 0-0xFFFFFF \param[out] none @@ -359,13 +359,13 @@ void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rti /*! \brief USART transmit data function \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] data: data of transmission + \param[in] data: data to be transmitted \param[out] none \retval none */ void usart_data_transmit(uint32_t usart_periph, uint16_t data) { - USART_DATA(usart_periph) = ((uint16_t)USART_DATA_DATA & data); + USART_DATA(usart_periph) = USART_DATA_DATA & (uint32_t)data; } /*! @@ -389,11 +389,11 @@ uint16_t usart_data_receive(uint32_t usart_periph) void usart_address_config(uint32_t usart_periph, uint8_t addr) { USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); - USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); + USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & (uint32_t)addr); } /*! - \brief receiver in mute mode + \brief enable mute mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none @@ -404,7 +404,7 @@ void usart_mute_mode_enable(uint32_t usart_periph) } /*! - \brief receiver in active mode + \brief disable mute mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none @@ -437,7 +437,7 @@ void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) \retval none */ void usart_lin_mode_enable(uint32_t usart_periph) -{ +{ USART_CTL1(usart_periph) |= USART_CTL1_LMEN; } @@ -448,7 +448,7 @@ void usart_lin_mode_enable(uint32_t usart_periph) \retval none */ void usart_lin_mode_disable(uint32_t usart_periph) -{ +{ USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); } @@ -480,18 +480,18 @@ void usart_send_break(uint32_t usart_periph) } /*! - \brief enable half duplex mode + \brief enable half-duplex mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none */ void usart_halfduplex_enable(uint32_t usart_periph) -{ +{ USART_CTL2(usart_periph) |= USART_CTL2_HDEN; } /*! - \brief disable half duplex mode + \brief disable half-duplex mode \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[out] none \retval none @@ -528,43 +528,36 @@ void usart_synchronous_clock_disable(uint32_t usart_periph) \param[in] usart_periph: USARTx(x=0,1,2,5) \param[in] clen: CK length only one parameter can be selected which is shown as below: - \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame + \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame \param[in] cph: clock phase only one parameter can be selected which is shown as below: - \arg USART_CPH_1CK: first clock transition is the first data capture edge + \arg USART_CPH_1CK: first clock transition is the first data capture edge \arg USART_CPH_2CK: second clock transition is the first data capture edge \param[in] cpl: clock polarity only one parameter can be selected which is shown as below: - \arg USART_CPL_LOW: steady low value on CK pin + \arg USART_CPL_LOW: steady low value on CK pin \arg USART_CPL_HIGH: steady high value on CK pin \param[out] none \retval none */ void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) { - uint32_t ctl = 0U; - - /* read USART_CTL1 register */ - ctl = USART_CTL1(usart_periph); - ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); - /* set CK length, CK phase, CK polarity */ - ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); - - USART_CTL1(usart_periph) = ctl; + USART_CTL1(usart_periph) &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); + USART_CTL1(usart_periph) |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); } /*! \brief configure guard time value in smartcard mode \param[in] usart_periph: USARTx(x=0,1,2,5) - \param[in] guat: guard time value + \param[in] guat: guard time value, 0-0xFF \param[out] none \retval none */ -void usart_guard_time_config(uint32_t usart_periph,uint32_t guat) +void usart_guard_time_config(uint32_t usart_periph, uint8_t guat) { USART_GP(usart_periph) &= ~(USART_GP_GUAT); - USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat)<<8)); + USART_GP(usart_periph) |= (USART_GP_GUAT & ((uint32_t)guat << GP_GUAT_OFFSET)); } /*! @@ -618,23 +611,23 @@ void usart_smartcard_mode_nack_disable(uint32_t usart_periph) \param[out] none \retval none */ -void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum) +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint8_t scrtnum) { USART_CTL3(usart_periph) &= ~(USART_CTL3_SCRTNUM); - USART_CTL3(usart_periph) |= (USART_CTL3_SCRTNUM & ((scrtnum)<<1)); + USART_CTL3(usart_periph) |= (USART_CTL3_SCRTNUM & ((uint32_t)scrtnum << CTL3_SCRTNUM_OFFSET)); } /*! - \brief configure block length in Smartcard T=1 reception + \brief configure block length \param[in] usart_periph: USARTx(x=0,1,2,5) \param[in] bl: block length \param[out] none \retval none */ -void usart_block_length_config(uint32_t usart_periph, uint32_t bl) +void usart_block_length_config(uint32_t usart_periph, uint8_t bl) { USART_RT(usart_periph) &= ~(USART_RT_BL); - USART_RT(usart_periph) |= (USART_RT_BL & ((bl)<<24)); + USART_RT(usart_periph) |= (USART_RT_BL & ((uint32_t)bl << RT_BL_OFFSET)); } /*! @@ -660,7 +653,7 @@ void usart_irda_mode_disable(uint32_t usart_periph) } /*! - \brief configure the peripheral clock prescaler in USART IrDA low-power mode + \brief configure the peripheral clock prescaler \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] psc: 0x00-0xFF \param[out] none @@ -669,7 +662,7 @@ void usart_irda_mode_disable(uint32_t usart_periph) void usart_prescaler_config(uint32_t usart_periph, uint8_t psc) { USART_GP(usart_periph) &= ~(USART_GP_PSC); - USART_GP(usart_periph) |= psc; + USART_GP(usart_periph) |= (uint32_t)psc; } /*! @@ -691,7 +684,7 @@ void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) /*! \brief configure hardware flow control RTS \param[in] usart_periph: USARTx(x=0,1,2,5) - \param[in] hardwareflow: enable or disable RTS + \param[in] rtsconfig: enable or disable RTS only one parameter can be selected which is shown as below: \arg USART_RTS_ENABLE: enable RTS \arg USART_RTS_DISABLE: disable RTS @@ -700,19 +693,14 @@ void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) */ void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) { - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_RTSEN; - ctl |= rtsconfig; - /* configure RTS */ - USART_CTL2(usart_periph) = ctl; + USART_CTL2(usart_periph) &= ~(USART_CTL2_RTSEN); + USART_CTL2(usart_periph) |= (USART_CTL2_RTSEN & rtsconfig); } /*! \brief configure hardware flow control CTS \param[in] usart_periph: USARTx(x=0,1,2,5) - \param[in] hardwareflow: enable or disable CTS + \param[in] ctsconfig: enable or disable CTS only one parameter can be selected which is shown as below: \arg USART_CTS_ENABLE: enable CTS \arg USART_CTS_DISABLE: disable CTS @@ -721,55 +709,40 @@ void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) */ void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) { - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_CTSEN; - ctl |= ctsconfig; - /* configure CTS */ - USART_CTL2(usart_periph) = ctl; + USART_CTL2(usart_periph) &= ~(USART_CTL2_CTSEN); + USART_CTL2(usart_periph) |= (USART_CTL2_CTSEN & ctsconfig); } /*! \brief configure USART DMA reception \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] dmacmd: enable or disable DMA for reception + \param[in] dmaconfig: USART DMA mode only one parameter can be selected which is shown as below: - \arg USART_DENR_ENABLE: DMA enable for reception - \arg USART_DENR_DISABLE: DMA disable for reception + \arg USART_RECEIVE_DMA_ENABLE: enable USART DMA for reception + \arg USART_RECEIVE_DMA_DISABLE: disable USART DMA for reception \param[out] none \retval none */ -void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) +void usart_dma_receive_config(uint32_t usart_periph, uint8_t dmaconfig) { - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_DENR; - ctl |= dmacmd; - /* configure DMA reception */ - USART_CTL2(usart_periph) = ctl; + USART_CTL2(usart_periph) &= ~(USART_CTL2_DENR); + USART_CTL2(usart_periph) |= (USART_CTL2_DENR & dmaconfig); } /*! \brief configure USART DMA transmission \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] dmacmd: enable or disable DMA for transmission + \param[in] dmaconfig: USART DMA mode only one parameter can be selected which is shown as below: - \arg USART_DENT_ENABLE: DMA enable for transmission - \arg USART_DENT_DISABLE: DMA disable for transmission + \arg USART_TRANSMIT_DMA_ENABLE: enable USART DMA for transmission + \arg USART_TRANSMIT_DMA_DISABLE: disable USART DMA for transmission \param[out] none \retval none */ -void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) +void usart_dma_transmit_config(uint32_t usart_periph, uint8_t dmaconfig) { - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_DENT; - ctl |= dmacmd; - /* configure DMA transmission */ - USART_CTL2(usart_periph) = ctl; + USART_CTL2(usart_periph) &= ~(USART_CTL2_DENT); + USART_CTL2(usart_periph) |= (USART_CTL2_DENT & dmaconfig); } /*! @@ -795,9 +768,9 @@ void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) */ FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) { - if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){ + if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))) { return SET; - }else{ + } else { return RESET; } } @@ -807,8 +780,8 @@ FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) \param[in] flag: USART flags, refer to usart_flag_enum only one parameter can be selected which is shown as below: - \arg USART_FLAG_CTS: CTS change flag - \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_CTSF: CTS change flag + \arg USART_FLAG_LBDF: LIN break detected flag \arg USART_FLAG_TC: transmission complete \arg USART_FLAG_RBNE: read data buffer not empty \arg USART_FLAG_EB: end of block flag @@ -818,13 +791,13 @@ FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) */ void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) { - USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag)); + USART_REG_VAL(usart_periph, flag) = ~BIT(USART_BIT_POS(flag)); } /*! \brief enable USART interrupt \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] int_flag + \param[in] interrupt: USART interrupts, refer to usart_interrupt_enum only one parameter can be selected which is shown as below: \arg USART_INT_PERR: parity error interrupt \arg USART_INT_TBE: transmitter buffer empty interrupt @@ -839,15 +812,15 @@ void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) \param[out] none \retval none */ -void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag) +void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt) { - USART_REG_VAL(usart_periph, int_flag) |= BIT(USART_BIT_POS(int_flag)); + USART_REG_VAL(usart_periph, interrupt) |= BIT(USART_BIT_POS(interrupt)); } /*! \brief disable USART interrupt \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] int_flag + \param[in] interrupt: USART interrupts, refer to usart_interrupt_enum only one parameter can be selected which is shown as below: \arg USART_INT_PERR: parity error interrupt \arg USART_INT_TBE: transmitter buffer empty interrupt @@ -862,9 +835,9 @@ void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag) \param[out] none \retval none */ -void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag) +void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt) { - USART_REG_VAL(usart_periph, int_flag) &= ~BIT(USART_BIT_POS(int_flag)); + USART_REG_VAL(usart_periph, interrupt) &= ~BIT(USART_BIT_POS(interrupt)); } /*! @@ -886,9 +859,9 @@ void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag) \arg USART_INT_FLAG_EB: interrupt enable bit of end of block event and flag \arg USART_INT_FLAG_RT: interrupt enable bit of receive timeout event and flag \param[out] none - \retval FlagStatus + \retval FlagStatus: SET or RESET */ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag) +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) { uint32_t intenable = 0U, flagstatus = 0U; /* get the interrupt enable bit status */ @@ -896,28 +869,28 @@ FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag) /* get the corresponding flag bit status */ flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); - if(flagstatus && intenable){ + if((0U != flagstatus) && (0U != intenable)) { return SET; - }else{ - return RESET; + } else { + return RESET; } } /*! \brief clear USART interrupt flag in STAT0/STAT1 register \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] flag: USART interrupt flag + \param[in] int_flag: USART interrupt flags, refer to usart_interrupt_flag_enum only one parameter can be selected which is shown as below: - \arg USART_INT_FLAG_CTS: CTS interrupt and flag - \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag - \arg USART_INT_FLAG_TC: transmission complete interrupt and flag - \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag - \arg USART_INT_FLAG_EB: interrupt enable bit of end of block event and flag - \arg USART_INT_FLAG_RT: interrupt enable bit of receive timeout event and flag + \arg USART_INT_FLAG_CTS: CTS change flag + \arg USART_INT_FLAG_LBD: LIN break detected flag + \arg USART_INT_FLAG_TC: transmission complete + \arg USART_INT_FLAG_RBNE: read data buffer not empty + \arg USART_INT_FLAG_EB: end of block flag + \arg USART_INT_FLAG_RT: receiver timeout flag \param[out] none \retval none */ -void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag) +void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) { - USART_REG_VAL2(usart_periph, flag) &= ~BIT(USART_BIT_POS2(flag)); + USART_REG_VAL2(usart_periph, int_flag) = ~BIT(USART_BIT_POS2(int_flag)); } diff --git a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_wwdgt.c b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_wwdgt.c index f205b0c2..7c3f7a27 100644 --- a/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_wwdgt.c +++ b/lib-gd32/gd32f20x/GD32F20x_standard_peripheral/Source/gd32f20x_wwdgt.c @@ -2,46 +2,38 @@ \file gd32f20x_wwdgt.c \brief WWDGT driver - \version 2015-07-15, V1.0.0, firmware for GD32F20x - \version 2017-06-05, V2.0.0, firmware for GD32F20x - \version 2018-10-31, V2.1.0, firmware for GD32F20x - \version 2020-09-30, V2.2.0, firmware for GD32F20x + \version 2023-06-30, V2.5.0, firmware for GD32F20x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2023, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "gd32f20x_wwdgt.h" -/* write value to WWDGT_CTL_CNT bit field */ -#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) -/* write value to WWDGT_CFG_WIN bit field */ -#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) - /*! \brief reset the window watchdog timer configuration \param[in] none @@ -73,17 +65,12 @@ void wwdgt_enable(void) */ void wwdgt_counter_update(uint16_t counter_value) { - uint32_t reg = 0U; - - reg = (WWDGT_CTL & (~WWDGT_CTL_CNT)); - reg |= CTL_CNT(counter_value); - - WWDGT_CTL = reg; + WWDGT_CTL = (uint32_t)(CTL_CNT(counter_value)); } /*! - \brief configure counter value, window value, and prescaler divider value - \param[in] counter: 0x00 - 0x7F + \brief configure counter value, window value, and prescaler divider value + \param[in] counter: 0x00 - 0x7F \param[in] window: 0x00 - 0x7F \param[in] prescaler: wwdgt prescaler value only one parameter can be selected which is shown as below: @@ -96,41 +83,36 @@ void wwdgt_counter_update(uint16_t counter_value) */ void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) { - uint32_t reg_cfg = 0U, reg_ctl = 0U; - - /* clear WIN and PSC bits, clear CNT bit */ - reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC))); - reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT)); - - /* configure WIN and PSC bits, configure CNT bit */ - reg_cfg |= CFG_WIN(window); - reg_cfg |= prescaler; - reg_ctl |= CTL_CNT(counter); - - WWDGT_CTL = reg_ctl; - WWDGT_CFG = reg_cfg; + WWDGT_CTL = (uint32_t)(CTL_CNT(counter)); + WWDGT_CFG = (uint32_t)(CFG_WIN(window) | prescaler); } /*! - \brief enable early wakeup interrupt of WWDGT + \brief get early wakeup interrupt flag of WWDGT \param[in] none \param[out] none - \retval none + \retval FlagStatus: SET or RESET */ -void wwdgt_interrupt_enable(void) +FlagStatus wwdgt_interrupt_flag_get(void) { - WWDGT_CFG |= WWDGT_CFG_EWIE; + uint32_t state; + state = WWDGT_STAT & WWDGT_STAT_EWIF; + if((WWDGT_CFG & WWDGT_CFG_EWIE) & state) { + return SET; + } + + return RESET; } /*! - \brief check early wakeup interrupt state of WWDGT + \brief get early wakeup flag of WWDGT \param[in] none \param[out] none \retval FlagStatus: SET or RESET */ FlagStatus wwdgt_flag_get(void) { - if(WWDGT_STAT & WWDGT_STAT_EWIF){ + if(WWDGT_STAT & WWDGT_STAT_EWIF) { return SET; } @@ -145,5 +127,16 @@ FlagStatus wwdgt_flag_get(void) */ void wwdgt_flag_clear(void) { - WWDGT_STAT &= (~WWDGT_STAT_EWIF); + WWDGT_STAT = (uint32_t)(RESET); +} + +/*! + \brief enable early wakeup interrupt of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_interrupt_enable(void) +{ + WWDGT_CFG |= WWDGT_CFG_EWIE; } diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/audio/Include/audio_core.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/audio/Include/audio_core.h new file mode 100644 index 00000000..d7b914d6 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/audio/Include/audio_core.h @@ -0,0 +1,320 @@ +/*! + \file audio_core.h + \brief the header file of USB audio device class core functions + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __AUDIO_CORE_H +#define __AUDIO_CORE_H + +#include "usbd_enum.h" + +#define FORMAT_24BIT(x) (uint8_t)(x);(uint8_t)((x) >> 8U);(uint8_t)((x) >> 16U) + +/* number of sub-packets in the audio transfer buffer. you can modify this value but always make sure + that it is an even number and higher than 3 */ +#define OUT_PACKET_NUM 200U + +/* total size of the audio transfer buffer */ +#define OUT_BUF_MARGIN 0U +#define TOTAL_OUT_BUF_SIZE ((uint32_t)((SPEAKER_OUT_PACKET + OUT_BUF_MARGIN) * OUT_PACKET_NUM)) + +#define AD_CONFIG_DESC_SET_LEN (sizeof(usb_desc_config_set)) +#define AD_INTERFACE_DESC_SIZE 9U + +#define USB_AD_DESC_SIZ 0x09U +#define AD_STANDARD_EP_DESC_SIZE 0x09U +#define AD_STREAMING_EP_DESC_SIZE 0x07U + +/* audio interface class code */ +#define USB_CLASS_AUDIO 0x01U + +/* audio interface subclass codes */ +#define AD_SUBCLASS_CONTROL 0x01U +#define AD_SUBCLASS_AUDIOSTREAMING 0x02U +#define AD_SUBCLASS_MIDISTREAMING 0x03U + +/* audio interface protocol codes */ +#define AD_PROTOCOL_UNDEFINED 0x00U +#define AD_STREAMING_GENERAL 0x01U +#define AD_STREAMING_FORMAT_TYPE 0x02U + +/* audio class-specific descriptor types */ +#define AD_DESCTYPE_UNDEFINED 0x20U +#define AD_DESCTYPE_DEVICE 0x21U +#define AD_DESCTYPE_CONFIGURATION 0x22U +#define AD_DESCTYPE_STRING 0x23U +#define AD_DESCTYPE_INTERFACE 0x24U +#define AD_DESCTYPE_ENDPOINT 0x25U + +/* audio control interface descriptor subtypes */ +#define AD_CONTROL_HEADER 0x01U +#define AD_CONTROL_INPUT_TERMINAL 0x02U +#define AD_CONTROL_OUTPUT_TERMINAL 0x03U +#define AD_CONTROL_MIXER_UNIT 0x04U +#define AD_CONTROL_SELECTOR_UNIT 0x05U +#define AD_CONTROL_FEATURE_UNIT 0x06U +#define AD_CONTROL_PROCESSING_UNIT 0x07U +#define AD_CONTROL_EXTENSION_UNIT 0x08U + +#define AD_INPUT_TERMINAL_DESC_SIZE 0x0CU +#define AD_OUTPUT_TERMINAL_DESC_SIZE 0x09U +#define AD_STREAMING_INTERFACE_DESC_SIZE 0x07U + +#define AD_CONTROL_MUTE 0x01U +#define AD_CONTROL_VOLUME 0x02U + +#define AD_FORMAT_TYPE_I 0x01U +#define AD_FORMAT_TYPE_III 0x03U + +#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01U +#define AD_ENDPOINT_GENERAL 0x01U + +#define AD_REQ_UNDEFINED 0x00U +#define AD_REQ_SET_CUR 0x01U +#define AD_REQ_GET_CUR 0x81U +#define AD_REQ_SET_MIN 0x02U +#define AD_REQ_GET_MIN 0x82U +#define AD_REQ_SET_MAX 0x03U +#define AD_REQ_GET_MAX 0x83U +#define AD_REQ_SET_RES 0x04U +#define AD_REQ_GET_RES 0x84U +#define AD_REQ_SET_MEM 0x05U +#define AD_REQ_GET_MEM 0x85U +#define AD_REQ_GET_STAT 0xFFU + +#define AD_OUT_STREAMING_CTRL 0x05U +#define AD_IN_STREAMING_CTRL 0x02U + +/* audio stream interface number */ +enum +{ +#ifdef USE_USB_AD_MICPHONE + MIC_INTERFACE_COUNT, +#endif /* USE_USB_AD_MICPHONE */ + +#ifdef USE_USB_AD_SPEAKER + SPEAK_INTERFACE_COUNT, +#endif /* USE_USB_AD_SPEAKER */ + CONFIG_DESC_AS_ITF_COUNT, +}; + +#define AC_ITF_TOTAL_LEN (sizeof(usb_desc_AC_itf) + CONFIG_DESC_AS_ITF_COUNT*(sizeof(usb_desc_input_terminal) + \ + sizeof(usb_desc_mono_feature_unit) + sizeof(usb_desc_output_terminal))) + +#pragma pack(1) + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bDescriptorSubtype; /*!< header descriptor subtype */ + uint16_t bcdADC; /*!< audio device class specification release number in binary-coded decimal */ + uint16_t wTotalLength; /*!< total number of bytes */ + uint8_t bInCollection; /*!< the number of the streaming interfaces */ +#ifdef USE_USB_AD_MICPHONE + uint8_t baInterfaceNr0; /*!< interface number of the streaming interfaces */ +#endif /* USE_USB_AD_MICPHONE */ + +#ifdef USE_USB_AD_SPEAKER + uint8_t baInterfaceNr1; /*!< interface number of the streaming interfaces */ +#endif /* USE_USB_AD_SPEAKER */ +} usb_desc_AC_itf; + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bDescriptorSubtype; /*!< AS_GENERAL descriptor subtype */ + uint8_t bTerminalLink; /*!< the terminal ID */ + uint8_t bDelay; /*!< delay introduced by the data path */ + uint16_t wFormatTag; /*!< the audio data format */ +} usb_desc_AS_itf; + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bDescriptorSubtype; /*!< INPUT_TERMINAL descriptor subtype. */ + uint8_t bTerminalID; /*!< constant uniquely identifying the terminal within the audio function */ + uint16_t wTerminalType; /*!< constant characterizing the type of terminal */ + uint8_t bAssocTerminal; /*!< ID of the output terminal */ + uint8_t bNrChannels; /*!< number of logical output channels */ + uint16_t wChannelConfig; /*!< describes the spatial location of the logical channels */ + uint8_t iChannelNames; /*!< index of a string descriptor */ + uint8_t iTerminal; /*!< index of a string descriptor */ +} usb_desc_input_terminal; + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bDescriptorSubtype; /*!< OUTPUT_TERMINAL descriptor subtype */ + uint8_t bTerminalID; /*!< constant uniquely identifying the terminal within the audio function */ + uint16_t wTerminalType; /*!< constant characterizing the type of terminal */ + uint8_t bAssocTerminal; /*!< constant, identifying the input terminal to which this output terminal is associated */ + uint8_t bSourceID; /*!< ID of the unit or terminal */ + uint8_t iTerminal; /*!< index of a string descriptor */ +} usb_desc_output_terminal; + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bDescriptorSubtype; /*!< FEATURE_UNIT descriptor subtype */ + uint8_t bUnitID; /*!< constant uniquely identifying the unit within the audio function */ + uint8_t bSourceID; /*!< ID of the unit or terminal */ + uint8_t bControlSize; /*!< size in bytes of an element of the bmaControls() array */ + uint8_t bmaControls0; /*!< a bit set to 1 indicates that the mentioned control is supported for master channel 0 */ + uint8_t bmaControls1; /*!< a bit set to 1 indicates that the mentioned control is supported for logical channel 1 */ + uint8_t iFeature; /*!< index of a string descriptor */ +} usb_desc_mono_feature_unit; + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bDescriptorSubtype; /*!< FEATURE_UNIT descriptor subtype */ + uint8_t bUnitID; /*!< constant uniquely identifying the unit within the audio function */ + uint8_t bSourceID; /*!< ID of the unit or terminal */ + uint8_t bControlSize; /*!< size in bytes of an element of the bmaControls() array */ + uint16_t bmaControls0; /*!< a bit set to 1 indicates that the mentioned control is supported for master channel 0 */ + uint16_t bmaControls1; /*!< a bit set to 1 indicates that the mentioned control is supported for logical channel 1 */ + uint16_t bmaControls2; /*!< a bit set to 1 indicates that the mentioned control is supported for logical channel 2 */ + uint8_t iFeature; /*!< index of a string descriptor */ +} usb_desc_stereo_feature_unit; + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bDescriptorSubtype; /*!< FORMAT_TYPE descriptor subtype */ + uint8_t bFormatType; /*!< constant identifying the format type */ + uint8_t bNrChannels; /*!< indicates the number of physical channels in the audio data stream */ + uint8_t bSubFrameSize; /*!< the number of bytes occupied by one audio subframe */ + uint8_t bBitResolution; /*!< the number of effectively used bits from the available bits in an audio subframe */ + uint8_t bSamFreqType; /*!< indicates how the sampling frequency can be programmed */ + uint8_t bSamFreq[3]; /*!< sampling frequency ns in Hz for this isochronous data endpoint */ +} usb_desc_format_type; + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bEndpointAddress; /*!< the address of the endpoint */ + uint8_t bmAttributes; /*!< transfer type and synchronization type */ + uint16_t wMaxPacketSize; /*!< maximum packet size this endpoint is capable of sending or receiving */ + uint8_t bInterval; /*!< left to the designer's discretion */ + uint8_t bRefresh; /*!< reset to 0 */ + uint8_t bSynchAddress; /*!< reset to 0 */ +} usb_desc_std_ep; + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bDescriptorSubtype; /*!< EP_GENERAL descriptor subtype */ + uint8_t bmAttributes; /*!< transfer type and synchronization type */ + uint8_t bLockDelayUnits; /*!< indicates the units used for the wLockDelay field */ + uint16_t wLockDelay; /*!< indicates the time it takes this endpoint to reliably lock its internal clock recovery circuitry */ +} usb_desc_AS_ep; + +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bEndpointAddress; /*!< EP_GENERAL descriptor subtype */ + uint8_t bmAttributes; /*!< transfer type and synchronization type */ + uint16_t wMaxPacketSize; /*!< maximum packet size this endpoint is capable of sending or receiving */ + uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */ + uint8_t Refresh; /*!< bRefresh 1~9, power of 2 */ + uint8_t bSynchAddress; /* bSynchAddress */ +} usb_desc_FeedBack_ep; + +#pragma pack() + +/* USB configuration descriptor structure */ +typedef struct +{ + usb_desc_config config; + usb_desc_itf std_itf; + usb_desc_AC_itf ac_itf; + +#ifdef USE_USB_AD_MICPHONE + usb_desc_input_terminal mic_in_terminal; + usb_desc_mono_feature_unit mic_feature_unit; + usb_desc_output_terminal mic_out_terminal; +#endif + +#ifdef USE_USB_AD_SPEAKER + usb_desc_input_terminal speak_in_terminal; + usb_desc_mono_feature_unit speak_feature_unit; + usb_desc_output_terminal speak_out_terminal; +#endif /* USE_USB_AD_SPEAKER */ + +#ifdef USE_USB_AD_MICPHONE + usb_desc_itf mic_std_as_itf_zeroband; + usb_desc_itf mic_std_as_itf_opera; + usb_desc_AS_itf mic_as_itf; + usb_desc_format_type mic_format_typeI; + usb_desc_std_ep mic_std_endpoint; + usb_desc_AS_ep mic_as_endpoint; +#endif /* USE_USB_AD_MICPHONE */ + +#ifdef USE_USB_AD_SPEAKER + usb_desc_itf speak_std_as_itf_zeroband; + usb_desc_itf speak_std_as_itf_opera; + usb_desc_AS_itf speak_as_itf; + usb_desc_format_type speak_format_typeI; + usb_desc_std_ep speak_std_endpoint; + usb_desc_AS_ep speak_as_endpoint; + usb_desc_FeedBack_ep speak_feedback_endpoint; +#endif /* USE_USB_AD_SPEAKER */ +} usb_desc_config_set; + +typedef struct +{ + /* main buffer for audio data out transfers and its relative pointers */ + uint8_t isoc_out_buff[TOTAL_OUT_BUF_SIZE]; + uint8_t* isoc_out_wrptr; + uint8_t* isoc_out_rdptr; + uint16_t buf_free_size; + uint16_t dam_tx_len; + + __IO uint32_t actual_freq; + __IO uint8_t play_flag; + uint8_t feedback_freq[3]; + uint32_t cur_sam_freq; + + /* usb receive buffer */ + uint8_t usb_rx_buffer[SPEAKER_OUT_MAX_PACKET]; + + /* main buffer for audio control requests transfers and its relative variables */ + uint8_t audioctl[64]; + uint8_t audioctl_unit; + uint32_t audioctl_len; +} usbd_audio_handler; + +extern usb_desc audio_desc; +extern usb_class_core usbd_audio_cb; +extern usbd_audio_handler audio_handler; + +#endif /* __AUDIO_CORE_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/audio/Include/audio_out_itf.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/audio/Include/audio_out_itf.h new file mode 100644 index 00000000..0ed8b58c --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/audio/Include/audio_out_itf.h @@ -0,0 +1,49 @@ +/*! + \file audio_out_itf.h + \brief audio OUT (playback) interface header file + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __AUDIO_OUT_ITF_H +#define __AUDIO_OUT_ITF_H + +#include "usbd_conf.h" +#include "string.h" + +typedef struct { + uint8_t (*audio_init) (uint32_t audio_freq, uint32_t volume); + uint8_t (*audio_deinit) (void); + uint8_t (*audio_cmd) (uint8_t* pbuf, uint32_t size, uint8_t cmd); +} audio_fops_struct; + +extern audio_fops_struct audio_out_fops; + +#endif /* __AUDIO_OUT_ITF_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/audio/Source/audio_core.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/audio/Source/audio_core.c new file mode 100644 index 00000000..05ad7d17 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/audio/Source/audio_core.c @@ -0,0 +1,959 @@ +/*! + \file audio_core.c + \brief USB audio device class core functions + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "audio_out_itf.h" +#include "audio_core.h" +#include +#include + +#define USBD_VID 0x28E9U +#define USBD_PID 0x9574U + +#define VOL_MIN 0U /* volume Minimum Value */ +#define VOL_MAX 100U /* volume Maximum Value */ +#define VOL_RES 1U /* volume Resolution */ +#define VOL_0dB 70U /* 0dB is in the middle of VOL_MIN and VOL_MAX */ + +#ifdef USE_USB_AD_MICPHONE +extern volatile uint32_t count_data; +extern const char wavetestdata[]; +#define LENGTH_DATA (1747 * 32) +#endif /* USE_USB_AD_MICPHONE */ + +usbd_audio_handler audio_handler; + +/* local function prototypes ('static') */ +static uint8_t audio_init (usb_dev *udev, uint8_t config_index); +static uint8_t audio_deinit (usb_dev *udev, uint8_t config_index); +static uint8_t audio_req_handler (usb_dev *udev, usb_req *req); +static uint8_t audio_set_intf (usb_dev *udev, usb_req *req); +static uint8_t audio_ctlx_out (usb_dev *udev); +static uint8_t audio_data_in (usb_dev *udev, uint8_t ep_num); +static uint8_t audio_data_out (usb_dev *udev, uint8_t ep_num); +static uint8_t audio_sof (usb_dev *udev); +static uint8_t audio_iso_in_incomplete (usb_dev *udev); +static uint8_t audio_iso_out_incomplete (usb_dev *udev); +static uint32_t usbd_audio_spk_get_feedback(usb_dev *udev); +static void get_feedback_fs_rate(uint32_t rate, uint8_t *buf); + +usb_class_core usbd_audio_cb = { + .init = audio_init, + .deinit = audio_deinit, + .req_proc = audio_req_handler, + .set_intf = audio_set_intf, + .ctlx_out = audio_ctlx_out, + .data_in = audio_data_in, + .data_out = audio_data_out, + .SOF = audio_sof, + .incomplete_isoc_in = audio_iso_in_incomplete, + .incomplete_isoc_out = audio_iso_out_incomplete +}; + +/* note:it should use the c99 standard when compiling the below codes */ +/* USB standard device descriptor */ +const usb_desc_dev audio_dev_desc = +{ + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, + .bcdUSB = 0x0200U, + .bDeviceClass = 0x00U, + .bDeviceSubClass = 0x00U, + .bDeviceProtocol = 0x00U, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100U, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM +}; + +/* USB device configuration descriptor */ +const usb_desc_config_set audio_config_set = +{ + .config = + { + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, + .wTotalLength = AD_CONFIG_DESC_SET_LEN, + .bNumInterfaces = 0x01U + CONFIG_DESC_AS_ITF_COUNT, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0xC0U, + .bMaxPower = 0x32U + }, + + .std_itf = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x00U, + .bInterfaceClass = USB_CLASS_AUDIO, + .bInterfaceSubClass = AD_SUBCLASS_CONTROL, + .bInterfaceProtocol = AD_PROTOCOL_UNDEFINED, + .iInterface = 0x00U + }, + + .ac_itf = + { + .header = + { + .bLength = sizeof(usb_desc_AC_itf), + .bDescriptorType = AD_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = 0x01U, + .bcdADC = 0x0100U, + .wTotalLength = AC_ITF_TOTAL_LEN, + .bInCollection = CONFIG_DESC_AS_ITF_COUNT, +#ifdef USE_USB_AD_MICPHONE + .baInterfaceNr0 = 0x01U, +#endif /* USE_USB_AD_MICPHONE */ + +#ifdef USE_USB_AD_SPEAKER + .baInterfaceNr1 = 0x02U +#endif /* USE_USB_AD_SPEAKER */ + }, + +#ifdef USE_USB_AD_MICPHONE + .mic_in_terminal = + { + .header = + { + .bLength = sizeof(usb_desc_input_terminal), + .bDescriptorType = AD_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = 0x02U, + .bTerminalID = 0x01U, + .wTerminalType = 0x0201U, + .bAssocTerminal = 0x00U, + .bNrChannels = 0x02U, + .wChannelConfig = 0x0003U, + .iChannelNames = 0x00U, + .iTerminal = 0x00U + }, + + .mic_feature_unit = + { + .header = + { + .bLength = sizeof(usb_desc_mono_feature_unit), + .bDescriptorType = AD_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = AD_CONTROL_FEATURE_UNIT, + .bUnitID = AD_IN_STREAMING_CTRL, + .bSourceID = 0x01U, + .bControlSize = 0x01U, + .bmaControls0 = AD_CONTROL_MUTE | AD_CONTROL_VOLUME, + .bmaControls1 = 0x00U, + .iFeature = 0x00U + }, + + .mic_out_terminal = + { + .header = + { + .bLength = sizeof(usb_desc_output_terminal), + .bDescriptorType = AD_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = AD_CONTROL_OUTPUT_TERMINAL, + .bTerminalID = 0x03U, + .wTerminalType = 0x0101U, + .bAssocTerminal = 0x00U, + .bSourceID = 0x02U, + .iTerminal = 0x00U + }, +#endif /* USE_USB_AD_MICPHONE */ + +#ifdef USE_USB_AD_SPEAKER + .speak_in_terminal = + { + .header = + { + .bLength = sizeof(usb_desc_input_terminal), + .bDescriptorType = AD_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = AD_CONTROL_INPUT_TERMINAL, + .bTerminalID = 0x04U, + .wTerminalType = 0x0101U, + .bAssocTerminal = 0x00U, + .bNrChannels = 0x02U, + .wChannelConfig = 0x0003U, + .iChannelNames = 0x00U, + .iTerminal = 0x00U + }, + + .speak_feature_unit = + { + .header = + { + .bLength = sizeof(usb_desc_mono_feature_unit), + .bDescriptorType = AD_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = AD_CONTROL_FEATURE_UNIT, + .bUnitID = AD_OUT_STREAMING_CTRL, + .bSourceID = 0x04U, + .bControlSize = 0x01U, + .bmaControls0 = AD_CONTROL_MUTE | AD_CONTROL_VOLUME, + .bmaControls1 = 0x00U, + .iFeature = 0x00U + }, + + .speak_out_terminal = + { + .header = + { + .bLength = sizeof(usb_desc_output_terminal), + .bDescriptorType = AD_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = AD_CONTROL_OUTPUT_TERMINAL, + .bTerminalID = 0x06U, + .wTerminalType = 0x0301U, + .bAssocTerminal = 0x00U, + .bSourceID = 0x05U, + .iTerminal = 0x00U + }, +#endif /* USE_USB_AD_SPEAKER */ + +#ifdef USE_USB_AD_MICPHONE + .mic_std_as_itf_zeroband = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x01U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x00U, + .bInterfaceClass = USB_CLASS_AUDIO, + .bInterfaceSubClass = AD_SUBCLASS_AUDIOSTREAMING, + .bInterfaceProtocol = AD_PROTOCOL_UNDEFINED, + .iInterface = 0x00U + }, + + .mic_std_as_itf_opera = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x01U, + .bAlternateSetting = 0x01U, + .bNumEndpoints = 0x01U, + .bInterfaceClass = USB_CLASS_AUDIO, + .bInterfaceSubClass = AD_SUBCLASS_AUDIOSTREAMING, + .bInterfaceProtocol = AD_PROTOCOL_UNDEFINED, + .iInterface = 0x00U + }, + + .mic_as_itf = + { + .header = + { + .bLength = sizeof(usb_desc_AS_itf), + .bDescriptorType = AD_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = AD_STREAMING_GENERAL, + .bTerminalLink = 0x03U, + .bDelay = 0x01U, + .wFormatTag = 0x0001U, + }, + + .mic_format_typeI = + { + .header = + { + .bLength = sizeof(usb_desc_format_type), + .bDescriptorType = AD_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = AD_STREAMING_FORMAT_TYPE, + .bFormatType = AD_FORMAT_TYPE_I, + .bNrChannels = MIC_IN_CHANNEL_NBR, + .bSubFrameSize = 0x02U, + .bBitResolution = MIC_IN_BIT_RESOLUTION, + .bSamFreqType = 0x01U, + .bSamFreq[0] = (uint8_t)USBD_MIC_FREQ, + .bSamFreq[1] = USBD_MIC_FREQ >> 8U, + .bSamFreq[2] = USBD_MIC_FREQ >> 16U + }, + + .mic_std_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_std_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = AD_IN_EP, + .bmAttributes = USB_ENDPOINT_TYPE_ISOCHRONOUS, + .wMaxPacketSize = MIC_IN_PACKET, + .bInterval = 0x01U, + .bRefresh = 0x00U, + .bSynchAddress = 0x00U + }, + + .mic_as_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_AS_ep), + .bDescriptorType = AD_DESCTYPE_ENDPOINT + }, + .bDescriptorSubtype = AD_ENDPOINT_GENERAL, + .bmAttributes = 0x00U, + .bLockDelayUnits = 0x00U, + .wLockDelay = 0x0000U, + }, +#endif /* USE_USB_AD_MICPHONE */ + +#ifdef USE_USB_AD_SPEAKER + .speak_std_as_itf_zeroband = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x02U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x00U, + .bInterfaceClass = USB_CLASS_AUDIO, + .bInterfaceSubClass = AD_SUBCLASS_AUDIOSTREAMING, + .bInterfaceProtocol = AD_PROTOCOL_UNDEFINED, + .iInterface = 0x00U + }, + + .speak_std_as_itf_opera = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x02U, + .bAlternateSetting = 0x01U, + .bNumEndpoints = 0x02U, + .bInterfaceClass = USB_CLASS_AUDIO, + .bInterfaceSubClass = AD_SUBCLASS_AUDIOSTREAMING, + .bInterfaceProtocol = AD_PROTOCOL_UNDEFINED, + .iInterface = 0x00U + }, + + .speak_as_itf = + { + .header = + { + .bLength = sizeof(usb_desc_AS_itf), + .bDescriptorType = AD_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = AD_STREAMING_GENERAL, + .bTerminalLink = 0x04U, + .bDelay = 0x01U, + .wFormatTag = 0x0001U, + }, + + .speak_format_typeI = + { + .header = + { + .bLength = sizeof(usb_desc_format_type), + .bDescriptorType = AD_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = AD_STREAMING_FORMAT_TYPE, + .bFormatType = AD_FORMAT_TYPE_I, + .bNrChannels = SPEAKER_OUT_CHANNEL_NBR, + .bSubFrameSize = 0x02U, + .bBitResolution = SPEAKER_OUT_BIT_RESOLUTION, + .bSamFreqType = 0x01U, + .bSamFreq[0] = (uint8_t)USBD_SPEAKER_FREQ, + .bSamFreq[1] = USBD_SPEAKER_FREQ >> 8U, + .bSamFreq[2] = USBD_SPEAKER_FREQ >> 16U + }, + + .speak_std_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_std_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = AD_OUT_EP, + .bmAttributes = USB_EP_ATTR_ISO | USB_EP_ATTR_ASYNC, + .wMaxPacketSize = SPEAKER_OUT_PACKET, + .bInterval = 0x01U, + .bRefresh = 0x00U, + .bSynchAddress = AD_FEEDBACK_IN_EP, + }, + + .speak_as_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_AS_ep), + .bDescriptorType = AD_DESCTYPE_ENDPOINT + }, + .bDescriptorSubtype = AD_ENDPOINT_GENERAL, + .bmAttributes = 0x00U, + .bLockDelayUnits = 0x00U, + .wLockDelay = 0x0000U, + }, + + .speak_feedback_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_FeedBack_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = AD_FEEDBACK_IN_EP, + .bmAttributes = USB_EP_ATTR_ISO | USB_EP_ATTR_ASYNC | USB_EP_ATTR_FEEDBACK, + .wMaxPacketSize = FEEDBACK_IN_PACKET, + .bInterval = 0x01U, + .Refresh = FEEDBACK_IN_INTERVAL, /* refresh every 32(2^5) ms */ + .bSynchAddress = 0x00U, + }, +#endif /* USE_USB_AD_SPEAKER */ +}; + +/* USB language ID descriptor */ +static const usb_desc_LANGID usbd_language_id_desc = +{ + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, + + .wLANGID = ENG_LANGID +}; + +/* USB manufacture string */ +static const usb_desc_str manufacturer_string = +{ + .header = + { + .bLength = USB_STRING_LEN(10), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} +}; + +/* USB product string */ +static const usb_desc_str product_string = +{ + .header = + { + .bLength = USB_STRING_LEN(14), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'A', 'u', 'd', 'i', 'o'} +}; + +/* USBD serial string */ +static usb_desc_str serial_string = +{ + .header = + { + .bLength = USB_STRING_LEN(12), + .bDescriptorType = USB_DESCTYPE_STR, + } +}; + +/* USB string descriptor */ +void *const usbd_audio_strings[] = +{ + [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *)&manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *)&product_string, + [STR_IDX_SERIAL] = (uint8_t *)&serial_string +}; + +/* USB descriptor configure */ +usb_desc audio_desc = { + .dev_desc = (uint8_t *)&audio_dev_desc, + .config_desc = (uint8_t *)&audio_config_set, + .strings = usbd_audio_strings +}; + +/*! + \brief initialize the AUDIO device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_init (usb_dev *udev, uint8_t config_index) +{ + memset((void *)&audio_handler, 0, sizeof(usbd_audio_handler)); + +#ifdef USE_USB_AD_MICPHONE +{ + usb_desc_std_ep std_ep = audio_config_set.mic_std_endpoint; + + usb_desc_ep ep = { + .header = std_ep.header, + .bEndpointAddress = std_ep.bEndpointAddress, + .bmAttributes = std_ep.bmAttributes, + .wMaxPacketSize = std_ep.wMaxPacketSize, + .bInterval = std_ep.bInterval + }; + + /* initialize TX endpoint */ + usbd_ep_setup (udev, &ep); +} +#endif /* USE_USB_AD_MICPHONE */ + +#ifdef USE_USB_AD_SPEAKER +{ + audio_handler.isoc_out_rdptr = audio_handler.isoc_out_buff; + audio_handler.isoc_out_wrptr = audio_handler.isoc_out_buff; + + usb_desc_std_ep std_ep = audio_config_set.speak_std_endpoint; + + usb_desc_ep ep1 = { + .header = std_ep.header, + .bEndpointAddress = std_ep.bEndpointAddress, + .bmAttributes = std_ep.bmAttributes, + .wMaxPacketSize = SPEAKER_OUT_MAX_PACKET, + .bInterval = std_ep.bInterval + }; + + /* initialize RX endpoint */ + usbd_ep_setup (udev, &ep1); + + /* prepare out endpoint to receive next audio packet */ + usbd_ep_recev (udev, AD_OUT_EP, audio_handler.usb_rx_buffer, SPEAKER_OUT_MAX_PACKET); + + /* initialize the audio output hardware layer */ + if (USBD_OK != audio_out_fops.audio_init(USBD_SPEAKER_FREQ, DEFAULT_VOLUME)) { + return USBD_FAIL; + } + + usb_desc_FeedBack_ep feedback_ep = audio_config_set.speak_feedback_endpoint; + + usb_desc_ep ep2 = { + .header = feedback_ep.header, + .bEndpointAddress = feedback_ep.bEndpointAddress, + .bmAttributes = feedback_ep.bmAttributes, + .wMaxPacketSize = feedback_ep.wMaxPacketSize, + .bInterval = feedback_ep.bInterval + }; + + /* initialize Tx endpoint */ + usbd_ep_setup (udev, &ep2); +} +#endif /* USE_USB_AD_SPEAKER */ + + return USBD_OK; +} + +/*! + \brief de-initialize the AUDIO device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_deinit (usb_dev *udev, uint8_t config_index) +{ +#ifdef USE_USB_AD_MICPHONE + /* deinitialize AUDIO endpoints */ + usbd_ep_clear(udev, AD_IN_EP); +#endif /* USE_USB_AD_MICPHONE */ + +#ifdef USE_USB_AD_SPEAKER + /* deinitialize AUDIO endpoints */ + usbd_ep_clear(udev, AD_OUT_EP); + + /* deinitialize the audio output hardware layer */ + if (USBD_OK != audio_out_fops.audio_deinit()) { + return USBD_FAIL; + } + + /* deinitialize AUDIO endpoints */ + usbd_ep_clear(udev, AD_FEEDBACK_IN_EP); +#endif /* USE_USB_AD_SPEAKER */ + + return USBD_OK; +} + +/*! + \brief handle the AUDIO class-specific requests + \param[in] udev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_req_handler (usb_dev *udev, usb_req *req) +{ + uint8_t status = REQ_NOTSUPP; + + usb_transc *transc_in = &udev->dev.transc_in[0]; + usb_transc *transc_out = &udev->dev.transc_out[0]; + + switch (req->bRequest) { + case AD_REQ_GET_CUR: + transc_in->xfer_buf = audio_handler.audioctl; + transc_in->remain_len = req->wLength; + + status = REQ_SUPP; + break; + + case AD_REQ_SET_CUR: + if (req->wLength) { + transc_out->xfer_buf = audio_handler.audioctl; + transc_out->remain_len = req->wLength; + + udev->dev.class_core->command = AD_REQ_SET_CUR; + + audio_handler.audioctl_len = req->wLength; + audio_handler.audioctl_unit = BYTE_HIGH(req->wIndex); + + status = REQ_SUPP; + } + break; + + case AD_REQ_GET_MIN: + *((uint16_t *)audio_handler.audioctl) = VOL_MIN; + transc_in->xfer_buf = audio_handler.audioctl; + transc_in->remain_len = req->wLength; + status = REQ_SUPP; + break; + + case AD_REQ_GET_MAX: + *((uint16_t *)audio_handler.audioctl) = VOL_MAX; + transc_in->xfer_buf = audio_handler.audioctl; + transc_in->remain_len = req->wLength; + status = REQ_SUPP; + break; + + case AD_REQ_GET_RES: + *((uint16_t *)audio_handler.audioctl) = VOL_RES; + transc_in->xfer_buf = audio_handler.audioctl; + transc_in->remain_len = req->wLength; + status = REQ_SUPP; + break; + + default: + break; + } + + return status; +} + +/*! + \brief handle the AUDIO set interface requests + \param[in] udev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_set_intf(usb_dev *udev, usb_req *req) +{ + udev->dev.class_core->alter_set = req->wValue; + + if(0xFF != req->wValue){ + if (req->wValue != 0){ + /* deinit audio handler */ + memset((void *)&audio_handler, 0, sizeof(usbd_audio_handler)); + + audio_handler.play_flag = 0; + audio_handler.isoc_out_rdptr = audio_handler.isoc_out_buff; + audio_handler.isoc_out_wrptr = audio_handler.isoc_out_buff; + + /* feedback calculate sample freq */ + audio_handler.actual_freq = I2S_ACTUAL_SAM_FREQ(USBD_SPEAKER_FREQ); + get_feedback_fs_rate(audio_handler.actual_freq, audio_handler.feedback_freq); + + /* send feedback data of estimated frequence*/ + usbd_ep_send(udev, AD_FEEDBACK_IN_EP, audio_handler.feedback_freq, FEEDBACK_IN_PACKET); + } else { + /* stop audio output */ + audio_out_fops.audio_cmd(audio_handler.isoc_out_rdptr, SPEAKER_OUT_PACKET/2, AD_CMD_STOP); + + audio_handler.play_flag = 0; + audio_handler.isoc_out_rdptr = audio_handler.isoc_out_buff; + audio_handler.isoc_out_wrptr = audio_handler.isoc_out_buff; + + usbd_fifo_flush (udev, AD_IN_EP); + usbd_fifo_flush (udev, AD_FEEDBACK_IN_EP); + usbd_fifo_flush (udev, AD_OUT_EP); + } + } + + return 0; +} + +/*! + \brief handles the control transfer OUT callback + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_ctlx_out (usb_dev *udev) +{ +#ifdef USE_USB_AD_SPEAKER + /* handles audio control requests data */ + /* check if an audio_control request has been issued */ + if (AD_REQ_SET_CUR == udev->dev.class_core->command) { + /* in this driver, to simplify code, only SET_CUR request is managed */ + + /* check for which addressed unit the audio_control request has been issued */ + if (AD_OUT_STREAMING_CTRL == audio_handler.audioctl_unit) { + /* in this driver, to simplify code, only one unit is manage */ + + /* reset the audioctl_cmd variable to prevent re-entering this function */ + udev->dev.class_core->command = 0U; + + audio_handler.audioctl_len = 0U; + } + } +#endif /* USE_USB_AD_SPEAKER */ + + return USBD_OK; +} + +/*! + \brief handles the audio IN data stage + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_data_in (usb_dev *udev, uint8_t ep_num) +{ +#ifdef USE_USB_AD_MICPHONE + if(ep_num == EP_ID(AD_IN_EP)){ + if(count_data < LENGTH_DATA){ + /* Prepare next buffer to be sent: dummy data */ + usbd_ep_send(udev, AD_IN_EP,(uint8_t*)&wavetestdata[count_data],MIC_IN_PACKET); + count_data += MIC_IN_PACKET; + } else { + usbd_ep_send(udev, AD_IN_EP,(uint8_t*)wavetestdata,MIC_IN_PACKET); + count_data = MIC_IN_PACKET; + } + } +#endif /* USE_USB_AD_MICPHONE */ + +#ifdef USE_USB_AD_SPEAKER + if(ep_num == EP_ID(AD_FEEDBACK_IN_EP)){ + /* calculate feedback actual freq */ + audio_handler.actual_freq = usbd_audio_spk_get_feedback(udev); + get_feedback_fs_rate(audio_handler.actual_freq, audio_handler.feedback_freq); + + usbd_ep_send(udev, AD_FEEDBACK_IN_EP, audio_handler.feedback_freq, FEEDBACK_IN_PACKET); + } +#endif /* USE_USB_AD_SPEAKER */ + + return USBD_OK; +} + +/*! + \brief handles the audio OUT data stage + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_data_out (usb_dev *udev, uint8_t ep_num) +{ + uint16_t usb_rx_length, tail_len; + + /* get receive length */ + usb_rx_length = ((usb_core_driver *)udev)->dev.transc_out[ep_num].xfer_count; + + if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr){ + audio_handler.buf_free_size = TOTAL_OUT_BUF_SIZE + audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr; + }else{ + audio_handler.buf_free_size = audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr; + } + + /* free buffer enough to save rx data */ + if(audio_handler.buf_free_size > usb_rx_length){ + if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr){ + tail_len = audio_handler.isoc_out_buff + TOTAL_OUT_BUF_SIZE - audio_handler.isoc_out_wrptr; + + if(tail_len >= usb_rx_length){ + memcpy(audio_handler.isoc_out_wrptr, audio_handler.usb_rx_buffer, usb_rx_length); + + /* increment the buffer pointer */ + audio_handler.isoc_out_wrptr += usb_rx_length; + + /* increment the Buffer pointer or roll it back when all buffers are full */ + if(audio_handler.isoc_out_wrptr >= (audio_handler.isoc_out_buff + TOTAL_OUT_BUF_SIZE)){ + /* all buffers are full: roll back */ + audio_handler.isoc_out_wrptr = audio_handler.isoc_out_buff; + } + }else{ + memcpy(audio_handler.isoc_out_wrptr, audio_handler.usb_rx_buffer, tail_len); + /* adjust write pointer */ + audio_handler.isoc_out_wrptr = audio_handler.isoc_out_buff; + + memcpy(audio_handler.isoc_out_wrptr, &audio_handler.usb_rx_buffer[tail_len], usb_rx_length - tail_len); + /* adjust write pointer */ + audio_handler.isoc_out_wrptr += usb_rx_length - tail_len; + } + }else{ + memcpy(audio_handler.isoc_out_wrptr, audio_handler.usb_rx_buffer, usb_rx_length); + + /* increment the buffer pointer */ + audio_handler.isoc_out_wrptr += usb_rx_length; + } + } + + /* Toggle the frame index */ + udev->dev.transc_out[ep_num].frame_num = (udev->dev.transc_out[ep_num].frame_num)? 0U:1U; + + /* prepare out endpoint to receive next audio packet */ + usbd_ep_recev (udev, AD_OUT_EP, audio_handler.usb_rx_buffer, SPEAKER_OUT_MAX_PACKET); + + if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr){ + audio_handler.buf_free_size = TOTAL_OUT_BUF_SIZE + audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr; + }else{ + audio_handler.buf_free_size = audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr; + } + + if ((0U == audio_handler.play_flag) && (audio_handler.buf_free_size < TOTAL_OUT_BUF_SIZE/2)) { + /* enable start of streaming */ + audio_handler.play_flag = 1U; + + /* initialize the audio output hardware layer */ + if (USBD_OK != audio_out_fops.audio_cmd(audio_handler.isoc_out_rdptr, SPEAKER_OUT_MAX_PACKET/2, AD_CMD_PLAY)) { + return USBD_FAIL; + } + + audio_handler.dam_tx_len = SPEAKER_OUT_MAX_PACKET; + } + + return USBD_OK; +} + +/*! + \brief handles the SOF event (data buffer update and synchronization) + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_sof (usb_dev *udev) +{ + return USBD_OK; +} + +/*! + \brief handles the audio ISO IN Incomplete event + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_iso_in_incomplete (usb_dev *udev) +{ + (void)usb_txfifo_flush (&udev->regs, EP_ID(AD_FEEDBACK_IN_EP)); + + audio_handler.actual_freq = usbd_audio_spk_get_feedback(udev); + get_feedback_fs_rate(audio_handler.actual_freq, audio_handler.feedback_freq); + + /* send feedback data of estimated frequence*/ + usbd_ep_send(udev, AD_FEEDBACK_IN_EP, audio_handler.feedback_freq, FEEDBACK_IN_PACKET); + + return USBD_OK; +} + +/*! + \brief handles the audio ISO OUT Incomplete event + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_iso_out_incomplete (usb_dev *udev) +{ + return USBD_OK; +} + +/*! + \brief calculate feedback sample frequency + \param[in] udev: pointer to USB device instance + \param[out] none + \retval feedback frequency value +*/ +static uint32_t usbd_audio_spk_get_feedback(usb_dev *udev) +{ + static uint32_t fb_freq; + + /* calculate buffer free size */ + if(audio_handler.isoc_out_wrptr >= audio_handler.isoc_out_rdptr){ + audio_handler.buf_free_size = TOTAL_OUT_BUF_SIZE + audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr; + }else{ + audio_handler.buf_free_size = audio_handler.isoc_out_rdptr - audio_handler.isoc_out_wrptr; + } + + /* calculate feedback frequency */ + if(audio_handler.buf_free_size <= (TOTAL_OUT_BUF_SIZE/4)){ + fb_freq = I2S_ACTUAL_SAM_FREQ(USBD_SPEAKER_FREQ) - FEEDBACK_FREQ_OFFSET; + }else if(audio_handler.buf_free_size >= (TOTAL_OUT_BUF_SIZE*3/4)){ + fb_freq = I2S_ACTUAL_SAM_FREQ(USBD_SPEAKER_FREQ) + FEEDBACK_FREQ_OFFSET; + }else{ + fb_freq = I2S_ACTUAL_SAM_FREQ(USBD_SPEAKER_FREQ); + } + + return fb_freq; +} + +/*! + \brief get feedback value from rate in USB full speed + \param[in] rate: sample frequence + \param[in] buf: pointer to result buffer + \param[out] none + \retval USB device operation status +*/ +static void get_feedback_fs_rate(uint32_t rate, uint8_t *buf) +{ + rate = ((rate / 1000) << 14) | ((rate % 1000) << 4); + + buf[0] = rate; + buf[1] = rate >> 8; + buf[2] = rate >> 16; +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/audio/Source/audio_out_itf.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/audio/Source/audio_out_itf.c new file mode 100644 index 00000000..68d8842b --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/audio/Source/audio_out_itf.c @@ -0,0 +1,168 @@ +/*! + \file audio_out_itf.c + \brief audio OUT (playback) interface functions + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "audio_core.h" +#include "audio_out_itf.h" + +/* local function prototypes ('static') */ +static uint8_t init (uint32_t audio_freq, uint32_t volume); +static uint8_t deinit (void); +static uint8_t audio_cmd (uint8_t* pbuf, uint32_t size, uint8_t cmd); + +/* local variable defines */ +static uint8_t audio_state = AD_STATE_INACTIVE; + +audio_fops_struct audio_out_fops = +{ + .audio_init = init, + .audio_deinit = deinit, + .audio_cmd = audio_cmd, +}; + +/*! + \brief initialize and configures all required resources + \param[in] audio_freq: statrt_up audio frequency + \param[in] volume: start_up volume to be set + \param[out] none + \retval AD_OK if all operations succeed, otherwise, AD_FAIL. +*/ +static uint8_t init (uint32_t audio_freq, uint32_t volume) +{ + static uint32_t initialized = 0U; + + /* check if the low layer has already been initialized */ + if (0U == initialized) { + /* initialize GPIO */ + codec_gpio_init(); + + /* initialize i2s */ + codec_audio_interface_init(audio_freq); + + /* initialize DMA */ + codec_i2s_dma_init(); + + /* prevent reinitializing the interface again */ + initialized = 1U; + } + + /* update the audio state machine */ + audio_state = AD_STATE_ACTIVE; + + return AD_OK; +} + +/*! + \brief free all resources used by low layer and stops audio-play function + \param[in] none + \param[out] none + \retval AD_OK if all operations succeed, otherwise, AD_FAIL. +*/ +static uint8_t deinit (void) +{ + /* update the audio state machine */ + audio_state = AD_STATE_INACTIVE; + + return AD_OK; +} + +/*! + \brief play, stop, pause or resume current file + \param[in] pbuf: address from which file should be played + \param[in] size: size of the current buffer/file + \param[in] cmd: command to be executed, can be: + \arg AD_CMD_PLAY + \arg AD_CMD_PAUSE + \arg AD_CMD_RESUME + \arg AD_CMD_STOP + \param[out] none + \retval AD_OK if all operations succeed, otherwise, AD_FAIL. +*/ +static uint8_t audio_cmd (uint8_t* pbuf, uint32_t size, uint8_t cmd) +{ + /* check the current state */ + if ((AD_STATE_INACTIVE == audio_state) || (AD_STATE_ERROR == audio_state)) { + audio_state = AD_STATE_ERROR; + + return AD_FAIL; + } + + switch (cmd) { + /* process the play command */ + case AD_CMD_PLAY: + /* if current state is active or stopped */ + if ((AD_STATE_ACTIVE == audio_state) || \ + (AD_STATE_STOPPED == audio_state) || \ + (AD_STATE_PLAYING == audio_state)) { + audio_play((uint32_t)pbuf, size); + audio_state = AD_STATE_PLAYING; + + return AD_OK; + } else if (AD_STATE_PAUSED == audio_state) { + audio_pause_resume(AD_RESUME, (uint32_t)pbuf, (size/2)); + audio_state = AD_STATE_PLAYING; + + return AD_OK; + } else { + return AD_FAIL; + } + + /* process the stop command */ + case AD_CMD_STOP: + if (AD_STATE_PLAYING != audio_state) { + /* unsupported command */ + return AD_FAIL; + } else { + audio_stop(); + audio_state = AD_STATE_STOPPED; + + return AD_OK; + } + + /* process the pause command */ + case AD_CMD_PAUSE: + if (AD_STATE_PLAYING != audio_state) { + /* unsupported command */ + return AD_FAIL; + } else { + audio_pause_resume(AD_PAUSE, (uint32_t)pbuf, (size/2)); + audio_state = AD_STATE_PAUSED; + + return AD_OK; + } + + /* unsupported command */ + default: + return AD_FAIL; + } +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/cdc/Include/cdc_acm_core.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/cdc/Include/cdc_acm_core.h new file mode 100644 index 00000000..493eb669 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/cdc/Include/cdc_acm_core.h @@ -0,0 +1,66 @@ +/*! + \file cdc_acm_core.h + \brief the header file of CDC ACM driver + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __CDC_ACM_CORE_H +#define __CDC_ACM_CORE_H + +#include "usbd_enum.h" +#include "usb_cdc.h" + +#define USB_CDC_RX_LEN USB_CDC_DATA_PACKET_SIZE + +typedef struct { + uint8_t packet_sent; + uint8_t packet_receive; + + uint8_t data[USB_CDC_RX_LEN]; + uint8_t cmd[USB_CDC_CMD_PACKET_SIZE]; + + uint32_t receive_length; + + acm_line line_coding; +} usb_cdc_handler; + +extern usb_desc cdc_desc; +extern usb_class_core cdc_class; + +/* function declarations */ +/* check CDC ACM is ready for data transfer */ +uint8_t cdc_acm_check_ready(usb_dev *udev); +/* send CDC ACM data */ +void cdc_acm_data_send(usb_dev *udev); +/* receive CDC ACM data */ +void cdc_acm_data_receive(usb_dev *udev); + +#endif /* __CDC_ACM_CORE_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/cdc/Source/cdc_acm_core.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/cdc/Source/cdc_acm_core.c new file mode 100644 index 00000000..6904c850 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/cdc/Source/cdc_acm_core.c @@ -0,0 +1,529 @@ +/*! + \file cdc_acm_core.c + \brief CDC ACM driver + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "cdc_acm_core.h" + +#define USBD_VID 0x28E9U +#define USBD_PID 0x018AU + +/* note:it should use the C99 standard when compiling the below codes */ +/* USB standard device descriptor */ +const usb_desc_dev cdc_dev_desc = +{ + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV, + }, + .bcdUSB = 0x0200U, + .bDeviceClass = USB_CLASS_CDC, + .bDeviceSubClass = 0x00U, + .bDeviceProtocol = 0x00U, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100U, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM, +}; + +/* USB device configuration descriptor */ +const usb_cdc_desc_config_set cdc_config_desc = +{ + .config = + { + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG, + }, + .wTotalLength = USB_CDC_ACM_CONFIG_DESC_SIZE, + .bNumInterfaces = 0x02U, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0x80U, + .bMaxPower = 0x32U + }, + + .cmd_itf = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x01U, + .bInterfaceClass = USB_CLASS_CDC, + .bInterfaceSubClass = USB_CDC_SUBCLASS_ACM, + .bInterfaceProtocol = USB_CDC_PROTOCOL_AT, + .iInterface = 0x00U + }, + + .cdc_header = + { + .header = + { + .bLength = sizeof(usb_desc_header_func), + .bDescriptorType = USB_DESCTYPE_CS_INTERFACE + }, + .bDescriptorSubtype = 0x00U, + .bcdCDC = 0x0110U + }, + + .cdc_call_managment = + { + .header = + { + .bLength = sizeof(usb_desc_call_managment_func), + .bDescriptorType = USB_DESCTYPE_CS_INTERFACE + }, + .bDescriptorSubtype = 0x01U, + .bmCapabilities = 0x00U, + .bDataInterface = 0x01U + }, + + .cdc_acm = + { + .header = + { + .bLength = sizeof(usb_desc_acm_func), + .bDescriptorType = USB_DESCTYPE_CS_INTERFACE + }, + .bDescriptorSubtype = 0x02U, + .bmCapabilities = 0x02U, + }, + + .cdc_union = + { + .header = + { + .bLength = sizeof(usb_desc_union_func), + .bDescriptorType = USB_DESCTYPE_CS_INTERFACE + }, + .bDescriptorSubtype = 0x06U, + .bMasterInterface = 0x00U, + .bSlaveInterface0 = 0x01U, + }, + + .cdc_cmd_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP, + }, + .bEndpointAddress = CDC_CMD_EP, + .bmAttributes = USB_EP_ATTR_INT, + .wMaxPacketSize = USB_CDC_CMD_PACKET_SIZE, + .bInterval = 0x0AU + }, + + .cdc_data_interface = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF, + }, + .bInterfaceNumber = 0x01U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x02U, + .bInterfaceClass = USB_CLASS_DATA, + .bInterfaceSubClass = 0x00U, + .bInterfaceProtocol = USB_CDC_PROTOCOL_NONE, + .iInterface = 0x00U + }, + + .cdc_out_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP, + }, + .bEndpointAddress = CDC_DATA_OUT_EP, + .bmAttributes = USB_EP_ATTR_BULK, + .wMaxPacketSize = USB_CDC_DATA_PACKET_SIZE, + .bInterval = 0x00U + }, + + .cdc_in_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = CDC_DATA_IN_EP, + .bmAttributes = USB_EP_ATTR_BULK, + .wMaxPacketSize = USB_CDC_DATA_PACKET_SIZE, + .bInterval = 0x00U + } +}; + +/* USB language ID Descriptor */ +static const usb_desc_LANGID usbd_language_id_desc = +{ + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .wLANGID = ENG_LANGID +}; + +/* USB manufacture string */ +static const usb_desc_str manufacturer_string = +{ + .header = + { + .bLength = USB_STRING_LEN(10), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} +}; + +/* USB product string */ +static const usb_desc_str product_string = +{ + .header = + { + .bLength = USB_STRING_LEN(12), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'D', '3', '2', '-', 'C', 'D', 'C', '_', 'A', 'C', 'M'} +}; + +/* USBD serial string */ +static usb_desc_str serial_string = +{ + .header = + { + .bLength = USB_STRING_LEN(12), + .bDescriptorType = USB_DESCTYPE_STR, + } +}; + +/* USB string descriptor set */ +void *const usbd_cdc_strings[] = +{ + [STR_IDX_LANGID] = (uint8_t *) &usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *) &manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *) &product_string, + [STR_IDX_SERIAL] = (uint8_t *) &serial_string +}; + +usb_desc cdc_desc = +{ + .dev_desc = (uint8_t *) &cdc_dev_desc, + .config_desc = (uint8_t *) &cdc_config_desc, + .strings = usbd_cdc_strings +}; + +/* local function prototypes ('static') */ +static uint8_t cdc_acm_init (usb_dev *udev, uint8_t config_index); +static uint8_t cdc_acm_deinit (usb_dev *udev, uint8_t config_index); +static uint8_t cdc_acm_req (usb_dev *udev, usb_req *req); +static uint8_t cdc_acm_ctlx_out (usb_dev *udev); +static uint8_t cdc_acm_in (usb_dev *udev, uint8_t ep_num); +static uint8_t cdc_acm_out (usb_dev *udev, uint8_t ep_num); + +/* USB CDC device class callbacks structure */ +usb_class_core cdc_class = +{ + .command = NO_CMD, + .alter_set = 0U, + + .init = cdc_acm_init, + .deinit = cdc_acm_deinit, + .req_proc = cdc_acm_req, + .ctlx_out = cdc_acm_ctlx_out, + .data_in = cdc_acm_in, + .data_out = cdc_acm_out +}; + +/*! + \brief check CDC ACM is ready for data transfer + \param[in] udev: pointer to USB device instance + \param[out] none + \retval 0 if CDC is ready, 5 else +*/ +uint8_t cdc_acm_check_ready(usb_dev *udev) +{ + if (udev->dev.class_data[CDC_COM_INTERFACE] != NULL) { + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + if ((1U == cdc->packet_receive) && (1U == cdc->packet_sent)) { + return 0U; + } + } + + return 1U; +} + +/*! + \brief send CDC ACM data + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +void cdc_acm_data_send (usb_dev *udev) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + if (0U != cdc->receive_length) { + cdc->packet_sent = 0U; + + usbd_ep_send (udev, CDC_DATA_IN_EP, (uint8_t*)(cdc->data), cdc->receive_length); + + cdc->receive_length = 0U; + } +} + +/*! + \brief receive CDC ACM data + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +void cdc_acm_data_receive (usb_dev *udev) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + cdc->packet_receive = 0U; + cdc->packet_sent = 0U; + + usbd_ep_recev (udev, CDC_DATA_OUT_EP, (uint8_t*)(cdc->data), USB_CDC_DATA_PACKET_SIZE); +} + +/*! + \brief initialize the CDC ACM device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_init (usb_dev *udev, uint8_t config_index) +{ + static usb_cdc_handler cdc_handler; + + /* initialize the data Tx endpoint */ + usbd_ep_setup (udev, &(cdc_config_desc.cdc_in_endpoint)); + + /* initialize the data Rx endpoint */ + usbd_ep_setup (udev, &(cdc_config_desc.cdc_out_endpoint)); + + /* initialize the command Tx endpoint */ + usbd_ep_setup (udev, &(cdc_config_desc.cdc_cmd_endpoint)); + + /* initialize CDC handler structure */ + cdc_handler.packet_receive = 1U; + cdc_handler.packet_sent = 1U; + cdc_handler.receive_length = 0U; + + cdc_handler.line_coding = (acm_line){ + .dwDTERate = 115200U, + .bCharFormat = 0U, + .bParityType = 0U, + .bDataBits = 0x08U + }; + + udev->dev.class_data[CDC_COM_INTERFACE] = (void *)&cdc_handler; + + return USBD_OK; +} + +/*! + \brief deinitialize the CDC ACM device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_deinit (usb_dev *udev, uint8_t config_index) +{ + /* deinitialize the data Tx/Rx endpoint */ + usbd_ep_clear (udev, CDC_DATA_IN_EP); + usbd_ep_clear (udev, CDC_DATA_OUT_EP); + + /* deinitialize the command Tx endpoint */ + usbd_ep_clear (udev, CDC_CMD_EP); + + return USBD_OK; +} + +/*! + \brief handle the CDC ACM class-specific requests + \param[in] udev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_req (usb_dev *udev, usb_req *req) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + usb_transc *transc = NULL; + + switch (req->bRequest) { + case SEND_ENCAPSULATED_COMMAND: + /* no operation for this driver */ + break; + + case GET_ENCAPSULATED_RESPONSE: + /* no operation for this driver */ + break; + + case SET_COMM_FEATURE: + /* no operation for this driver */ + break; + + case GET_COMM_FEATURE: + /* no operation for this driver */ + break; + + case CLEAR_COMM_FEATURE: + /* no operation for this driver */ + break; + + case SET_LINE_CODING: + transc = &udev->dev.transc_out[0]; + + /* set the value of the current command to be processed */ + udev->dev.class_core->alter_set = req->bRequest; + + /* enable EP0 prepare to receive command data packet */ + transc->remain_len = req->wLength; + transc->xfer_buf = cdc->cmd; + break; + + case GET_LINE_CODING: + transc = &udev->dev.transc_in[0]; + + cdc->cmd[0] = (uint8_t)(cdc->line_coding.dwDTERate); + cdc->cmd[1] = (uint8_t)(cdc->line_coding.dwDTERate >> 8); + cdc->cmd[2] = (uint8_t)(cdc->line_coding.dwDTERate >> 16); + cdc->cmd[3] = (uint8_t)(cdc->line_coding.dwDTERate >> 24); + cdc->cmd[4] = cdc->line_coding.bCharFormat; + cdc->cmd[5] = cdc->line_coding.bParityType; + cdc->cmd[6] = cdc->line_coding.bDataBits; + + transc->xfer_buf = cdc->cmd; + transc->remain_len = 7U; + break; + + case SET_CONTROL_LINE_STATE: + /* no operation for this driver */ + break; + + case SEND_BREAK: + /* no operation for this driver */ + break; + + default: + break; + } + + return USBD_OK; +} + +/*! + \brief command data received on control endpoint + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_ctlx_out (usb_dev *udev) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + if (udev->dev.class_core->alter_set != NO_CMD) { + /* process the command data */ + cdc->line_coding.dwDTERate = (uint32_t)((uint32_t)cdc->cmd[0] | + ((uint32_t)cdc->cmd[1] << 8U) | + ((uint32_t)cdc->cmd[2] << 16U) | + ((uint32_t)cdc->cmd[3] << 24U)); + + cdc->line_coding.bCharFormat = cdc->cmd[4]; + cdc->line_coding.bParityType = cdc->cmd[5]; + cdc->line_coding.bDataBits = cdc->cmd[6]; + + udev->dev.class_core->alter_set = NO_CMD; + } + + return USBD_OK; +} + +/*! + \brief handle CDC ACM data in + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_in (usb_dev *udev, uint8_t ep_num) +{ + usb_transc *transc = &udev->dev.transc_in[EP_ID(ep_num)]; + + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + if ((0U == transc->xfer_len % transc->max_len) && (0U != transc->xfer_len)) { + usbd_ep_send (udev, ep_num, NULL, 0U); + } else { + cdc->packet_sent = 1U; + } + + return USBD_OK; +} + +/*! + \brief handle CDC ACM data out + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_out (usb_dev *udev, uint8_t ep_num) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + cdc->packet_receive = 1U; + cdc->receive_length = ((usb_core_driver *)udev)->dev.transc_out[ep_num].xfer_count; + + return USBD_OK; +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/dfu/Include/dfu_core.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/dfu/Include/dfu_core.h new file mode 100644 index 00000000..469e1e1d --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/dfu/Include/dfu_core.h @@ -0,0 +1,175 @@ +/*! + \file dfu_core.h + \brief the header file of USB DFU device class core functions + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DFU_CORE_H +#define __DFU_CORE_H + +#include "usbd_enum.h" + +/* DFU class code */ +#define USB_DFU_CLASS 0xFEU + +/* DFU subclass code */ +#define USB_DFU_SUBCLASS_UPGRADE 0x01U + +/* DFU protocol code */ +#define USB_DFU_PROTOCL_RUNTIME 0x01U +#define USB_DFU_PROTOCL_DFU 0x02U + +/* manifestation state */ +#define MANIFEST_COMPLETE 0x00U +#define MANIFEST_IN_PROGRESS 0x01U + +/* DFU attributes code */ +#define USB_DFU_CAN_DOWNLOAD 0x01U +#define USB_DFU_CAN_UPLOAD 0x02U +#define USB_DFU_MANIFEST_TOLERANT 0x04U +#define USB_DFU_WILL_DETACH 0x08U + +/* special commands with download request */ +#define GET_COMMANDS 0x00U +#define SET_ADDRESS_POINTER 0x21U +#define ERASE 0x41U + +/* memory operation command */ +#define CMD_ERASE 0U +#define CMD_WRITE 1U + +#define _BYTE1(x) (uint8_t)((x) & 0xFFU) /*!< addressing cycle 1st byte */ +#define _BYTE2(x) (uint8_t)(((x) & 0xFF00U) >> 8U) /*!< addressing cycle 2nd byte */ +#define _BYTE3(x) (uint8_t)(((x) & 0xFF0000U) >> 16U) /*!< addressing cycle 3rd byte */ + +#define FLASH_ERASE_TIMEOUT 60U +#define FLASH_WRITE_TIMEOUT 80U + +/* bit detach capable = bit 3 in bmAttributes field */ +#define DFU_DETACH_MASK (uint8_t)(0x10U) + +#define DFU_DESC_TYPE 0x21U + +/* DFU device state defines */ +typedef enum { + STATE_APP_IDLE = 0x00U, + STATE_APP_DETACH, + STATE_DFU_IDLE, + STATE_DFU_DNLOAD_SYNC, + STATE_DFU_DNBUSY, + STATE_DFU_DNLOAD_IDLE, + STATE_DFU_MANIFEST_SYNC, + STATE_DFU_MANIFEST, + STATE_DFU_MANIFEST_WAIT_RESET, + STATE_DFU_UPLOAD_IDLE, + STATE_DFU_ERROR +} dfu_state; + +/* DFU device status defines */ +typedef enum { + STATUS_OK = 0x00U, + STATUS_ERR_TARGET, + STATUS_ERR_FILE, + STATUS_ERR_WRITE, + STATUS_ERR_ERASE, + STATUS_ERR_CHECK_ERASED, + STATUS_ERR_PROG, + STATUS_ERR_VERIFY, + STATUS_ERR_ADDRESS, + STATUS_ERR_NOTDONE, + STATUS_ERR_FIRMWARE, + STATUS_ERR_VENDOR, + STATUS_ERR_USBR, + STATUS_ERR_POR, + STATUS_ERR_UNKNOWN, + STATUS_ERR_STALLEDPKT +} dfu_status; + +/* DFU class-specific requests */ +typedef enum { + DFU_DETACH = 0U, + DFU_DNLOAD, + DFU_UPLOAD, + DFU_GETSTATUS, + DFU_CLRSTATUS, + DFU_GETSTATE, + DFU_ABORT, + DFU_REQ_MAX +} dfu_requests; + +#pragma pack(1) + +/* USB DFU function descriptor structure */ +typedef struct +{ + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bmAttributes; /*!< DFU attributes */ + uint16_t wDetachTimeOut; /*!< time, in milliseconds, that the device will wait after receipt of the DFU_DETACH request. If */ + uint16_t wTransferSize; /*!< maximum number of bytes that the device can accept per control-write transaction */ + uint16_t bcdDFUVersion; /*!< numeric expression identifying the version of the DFU specification release. */ +} usb_desc_dfu_func; + +#pragma pack() + +/* USB configuration descriptor structure */ +typedef struct +{ + usb_desc_config config; + usb_desc_itf dfu_itf0; + usb_desc_itf dfu_itf1; + usb_desc_itf dfu_itf2; + usb_desc_dfu_func dfu_func; +} usb_dfu_desc_config_set; + +/* USB DFU handler structure */ +typedef struct +{ + uint8_t bStatus; + uint8_t bwPollTimeout0; + uint8_t bwPollTimeout1; + uint8_t bwPollTimeout2; + uint8_t bState; + uint8_t iString; + + uint8_t manifest_state; + uint32_t data_len; + uint16_t block_num; + uint32_t base_addr; + + uint8_t buf[TRANSFER_SIZE]; +} usbd_dfu_handler; + +typedef void (*app_func) (void); + +extern usb_desc dfu_desc; +extern usb_class_core dfu_class; + +#endif /* DFU_CORE_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/dfu/Include/dfu_mem.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/dfu/Include/dfu_mem.h new file mode 100644 index 00000000..39e46d5a --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/dfu/Include/dfu_mem.h @@ -0,0 +1,83 @@ +/*! + \file dfu_mem.h + \brief USB DFU device media access layer header file + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DFU_MEM_H +#define __DFU_MEM_H + +#include "usb_conf.h" + +typedef struct _dfu_mem_prop +{ + const uint8_t* pstr_desc; + + uint8_t (*mem_init)(void); + uint8_t (*mem_deinit)(void); + uint8_t (*mem_erase)(uint32_t addr); + uint8_t (*mem_write)(uint8_t *buf, uint32_t addr, uint32_t len); + uint8_t *(*mem_read)(uint8_t *buf, uint32_t addr, uint32_t len); + uint8_t (*mem_checkaddr)(uint32_t addr); + + const uint32_t erase_timeout; + const uint32_t write_timeout; +} dfu_mem_prop; + +typedef enum +{ + MEM_OK = 0, + MEM_FAIL +} mem_status; + +#define _1ST_BYTE(x) (uint8_t)((x) & 0xFF) /*!< addressing cycle 1st byte */ +#define _2ND_BYTE(x) (uint8_t)(((x) & 0xFF00) >> 8) /*!< addressing cycle 2nd byte */ +#define _3RD_BYTE(x) (uint8_t)(((x) & 0xFF0000) >> 16) /*!< addressing cycle 3rd byte */ + +#define POLLING_TIMEOUT_SET(x) buffer[0] = _1ST_BYTE(x);\ + buffer[1] = _2ND_BYTE(x);\ + buffer[2] = _3RD_BYTE(x); + +/* function declarations */ +/* initialize the memory media on the GD32 */ +uint8_t dfu_mem_init(void); +/* deinitialize the memory media on the GD32 */ +uint8_t dfu_mem_deinit(void); +/* erase a memory sector */ +uint8_t dfu_mem_erase(uint32_t addr); +/* write data to sectors of memory */ +uint8_t dfu_mem_write(uint8_t *buf, uint32_t addr, uint32_t len); +/* read data from sectors of memory */ +uint8_t* dfu_mem_read(uint8_t *buf, uint32_t addr, uint32_t len); +/* get the status of a given memory and store in buffer */ +uint8_t dfu_mem_getstatus(uint32_t addr, uint8_t cmd, uint8_t *buffer); + +#endif /* __DFU_MEM_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/dfu/Source/dfu_core.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/dfu/Source/dfu_core.c new file mode 100644 index 00000000..44b73a13 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/dfu/Source/dfu_core.c @@ -0,0 +1,733 @@ +/*! + \file dfu_core.c + \brief USB DFU device class core functions + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "dfu_core.h" +#include "dfu_mem.h" +#include "drv_usb_hw.h" +#include + +#define USBD_VID 0x28E9U +#define USBD_PID 0x0189U + +/* local function prototypes ('static') */ +static uint8_t dfu_init(usb_dev *udev, uint8_t config_index); +static uint8_t dfu_deinit(usb_dev *udev, uint8_t config_index); +static uint8_t dfu_req_handler(usb_dev *udev, usb_req *req); +static uint8_t dfu_ctlx_in(usb_dev *udev); + +static void dfu_mode_leave(usb_dev *udev); +static uint8_t dfu_getstatus_complete (usb_dev *udev); + +/* DFU requests management functions */ +static void dfu_detach(usb_dev *udev, usb_req *req); +static void dfu_dnload(usb_dev *udev, usb_req *req); +static void dfu_upload(usb_dev *udev, usb_req *req); +static void dfu_getstatus(usb_dev *udev, usb_req *req); +static void dfu_clrstatus(usb_dev *udev, usb_req *req); +static void dfu_getstate(usb_dev *udev, usb_req *req); +static void dfu_abort(usb_dev *udev, usb_req *req); + +static void string_to_unicode (uint8_t *str, uint16_t *pbuf); + +static void (*dfu_request_process[])(usb_dev *udev, usb_req *req) = +{ + [DFU_DETACH] = dfu_detach, + [DFU_DNLOAD] = dfu_dnload, + [DFU_UPLOAD] = dfu_upload, + [DFU_GETSTATUS] = dfu_getstatus, + [DFU_CLRSTATUS] = dfu_clrstatus, + [DFU_GETSTATE] = dfu_getstate, + [DFU_ABORT] = dfu_abort +}; + +/* note:it should use the c99 standard when compiling the below codes */ +/* USB standard device descriptor */ +const usb_desc_dev dfu_dev_desc = +{ + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, + .bcdUSB = 0x0200U, + .bDeviceClass = 0x00U, + .bDeviceSubClass = 0x00U, + .bDeviceProtocol = 0x00U, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100U, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM +}; + +/* USB device configuration descriptor */ +const usb_dfu_desc_config_set dfu_config_desc = +{ + .config = + { + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, + .wTotalLength = sizeof(usb_dfu_desc_config_set), + .bNumInterfaces = 0x01U, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0x80U, + .bMaxPower = 0x32U + }, + + .dfu_itf0 = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x00U, + .bInterfaceClass = USB_DFU_CLASS, + .bInterfaceSubClass = USB_DFU_SUBCLASS_UPGRADE, + .bInterfaceProtocol = USB_DFU_PROTOCL_DFU, + .iInterface = STR_IDX_ALT_ITF0 + }, + + .dfu_itf1 = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x01U, + .bNumEndpoints = 0x00U, + .bInterfaceClass = USB_DFU_CLASS, + .bInterfaceSubClass = USB_DFU_SUBCLASS_UPGRADE, + .bInterfaceProtocol = USB_DFU_PROTOCL_DFU, + .iInterface = STR_IDX_ALT_ITF1 + }, + + .dfu_itf2 = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x02U, + .bNumEndpoints = 0x00U, + .bInterfaceClass = USB_DFU_CLASS, + .bInterfaceSubClass = USB_DFU_SUBCLASS_UPGRADE, + .bInterfaceProtocol = USB_DFU_PROTOCL_DFU, + .iInterface = STR_IDX_ALT_ITF2 + }, + + .dfu_func= + { + .header = + { + .bLength = sizeof(usb_desc_dfu_func), + .bDescriptorType = DFU_DESC_TYPE + }, + .bmAttributes = USB_DFU_CAN_DOWNLOAD | USB_DFU_CAN_UPLOAD | USB_DFU_WILL_DETACH, + .wDetachTimeOut = 0x00FFU, + .wTransferSize = TRANSFER_SIZE, + .bcdDFUVersion = 0x0110U, + }, +}; + +/* USB language ID descriptor */ +static const usb_desc_LANGID usbd_language_id_desc = +{ + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, + .wLANGID = ENG_LANGID +}; + +/* USB manufacture string */ +static const usb_desc_str manufacturer_string = +{ + .header = + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} +}; + +/* USB product string */ +static const usb_desc_str product_string = +{ + .header = + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'D', 'F', 'U'} +}; + +/* USB serial string */ +static usb_desc_str serial_string = +{ + .header = + { + .bLength = USB_STRING_LEN(2U), + .bDescriptorType = USB_DESCTYPE_STR, + } +}; + +/* USB configure string */ +static const usb_desc_str config_string = +{ + .header = + { + .bLength = USB_STRING_LEN(15U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'D', '3', '2', ' ', 'U', 'S', 'B', ' ', 'C', 'O', 'N', 'F', 'I', 'G'} +}; + +/* alternate interface 0 string */ +static usb_desc_str interface_string0 = +{ + .header = + { + .bLength = USB_STRING_LEN(2U), + .bDescriptorType = USB_DESCTYPE_STR, + }, +}; + +/* alternate interface 1 string */ +static usb_desc_str interface_string1 = +{ + .header = + { + .bLength = USB_STRING_LEN(2U), + .bDescriptorType = USB_DESCTYPE_STR, + }, +}; + +/* alternate interface 2 string */ +static usb_desc_str interface_string2 = +{ + .header = + { + .bLength = USB_STRING_LEN(2U), + .bDescriptorType = USB_DESCTYPE_STR, + }, +}; + +void *const usbd_dfu_strings[] = +{ + [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *)&manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *)&product_string, + [STR_IDX_SERIAL] = (uint8_t *)&serial_string, + [STR_IDX_CONFIG] = (uint8_t *)&config_string, + [STR_IDX_ALT_ITF0] = (uint8_t *)&interface_string0, + [STR_IDX_ALT_ITF1] = (uint8_t *)&interface_string1, + [STR_IDX_ALT_ITF2] = (uint8_t *)&interface_string2, +}; + +usb_desc dfu_desc = { + .dev_desc = (uint8_t *)&dfu_dev_desc, + .config_desc = (uint8_t *)&dfu_config_desc, + .strings = usbd_dfu_strings +}; + +usb_class_core dfu_class = { + .init = dfu_init, + .deinit = dfu_deinit, + .req_proc = dfu_req_handler, + .ctlx_in = dfu_ctlx_in +}; + +/*! + \brief initialize the DFU device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t dfu_init (usb_dev *udev, uint8_t config_index) +{ + static usbd_dfu_handler dfu_handler; + + /* unlock the internal flash */ + dfu_mem_init(); + + memset((void *)&dfu_handler, 0, sizeof(usbd_dfu_handler)); + + dfu_handler.manifest_state = MANIFEST_COMPLETE; + dfu_handler.bState = STATE_DFU_IDLE; + dfu_handler.bStatus = STATUS_OK; + + udev->dev.class_data[USBD_DFU_INTERFACE] = (void *)&dfu_handler; + + /* create interface string */ + string_to_unicode((uint8_t *)dfu_inter_flash_cb.pstr_desc, udev->dev.desc->strings[STR_IDX_ALT_ITF0]); + string_to_unicode((uint8_t *)dfu_nor_flash_cb.pstr_desc, udev->dev.desc->strings[STR_IDX_ALT_ITF1]); + string_to_unicode((uint8_t *)dfu_nand_flash_cb.pstr_desc, udev->dev.desc->strings[STR_IDX_ALT_ITF2]); + + return USBD_OK; +} + +/*! + \brief deinitialize the DFU device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t dfu_deinit (usb_dev *udev, uint8_t config_index) +{ + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; + + /* restore device default state */ + memset(udev->dev.class_data[USBD_DFU_INTERFACE], 0, sizeof(usbd_dfu_handler)); + + dfu->bState = STATE_DFU_IDLE; + dfu->bStatus = STATUS_OK; + + /* deinit the memory */ + dfu_mem_deinit(); + + return USBD_OK; +} + +/*! + \brief handle the DFU class-specific requests + \param[in] udev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t dfu_req_handler (usb_dev *udev, usb_req *req) +{ + if (req->bRequest < DFU_REQ_MAX) { + dfu_request_process[req->bRequest](udev, req); + } else { + return USBD_FAIL; + } + + return USBD_OK; +} + +/*! + \brief handle data stage + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t dfu_ctlx_in (usb_dev *udev) +{ + dfu_getstatus_complete(udev); + + return USBD_OK; +} + +/*! + \brief leave DFU mode and reset device to jump to user loaded code + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +static void dfu_mode_leave (usb_dev *udev) +{ + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; + + dfu->manifest_state = MANIFEST_COMPLETE; + + if (dfu_config_desc.dfu_func.bmAttributes & 0x04U) { + dfu->bState = STATE_DFU_MANIFEST_SYNC; + } else { + dfu->bState = STATE_DFU_MANIFEST_WAIT_RESET; + + /* deinit the memory */ + dfu_mem_deinit(); + + /* generate system reset to allow jumping to the user code */ + NVIC_SystemReset(); + } +} + +/*! + \brief handle data IN stage in control endpoint 0 + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status + */ +static uint8_t dfu_getstatus_complete (usb_dev *udev) +{ + uint32_t addr; + + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; + + if (STATE_DFU_DNBUSY == dfu->bState) { + /* decode the special command */ + if (0U == dfu->block_num) { + if (1U == dfu->data_len){ + if (GET_COMMANDS == dfu->buf[0]) { + /* no operation */ + } + } else if (5U == dfu->data_len) { + if (SET_ADDRESS_POINTER == dfu->buf[0]) { + /* set flash operation address */ + dfu->base_addr = *(uint32_t *)(dfu->buf + 1U); + } else if (ERASE == dfu->buf[0]) { + dfu->base_addr = *(uint32_t *)(dfu->buf + 1U); + + dfu_mem_erase(dfu->base_addr); + } else { + /* no operation */ + } + } else { + /* no operation */ + } + } else if (dfu->block_num > 1U) { /* regular download command */ + /* decode the required address */ + addr = (dfu->block_num - 2U) * TRANSFER_SIZE + dfu->base_addr; + + dfu_mem_write (dfu->buf, addr, dfu->data_len); + + dfu->block_num = 0U; + } else { + /* no operation */ + } + + dfu->data_len = 0U; + + /* update the device state and poll timeout */ + dfu->bState = STATE_DFU_DNLOAD_SYNC; + + return USBD_OK; + } else if (dfu->bState == STATE_DFU_MANIFEST) { /* manifestation in progress */ + /* start leaving DFU mode */ + dfu_mode_leave(udev); + } else { + /* no operation */ + } + + return USBD_OK; +} + +/*! + \brief handle the DFU_DETACH request + \param[in] udev: pointer to USB device instance + \param[in] req: DFU class request + \param[out] none + \retval none. +*/ +static void dfu_detach(usb_dev *udev, usb_req *req) +{ + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; + + switch (dfu->bState) { + case STATE_DFU_IDLE: + case STATE_DFU_DNLOAD_SYNC: + case STATE_DFU_DNLOAD_IDLE: + case STATE_DFU_MANIFEST_SYNC: + case STATE_DFU_UPLOAD_IDLE: + dfu->bStatus = STATUS_OK; + dfu->bState = STATE_DFU_IDLE; + dfu->iString = 0U; /* iString */ + + dfu->block_num = 0U; + dfu->data_len = 0U; + break; + + default: + break; + } + + /* check the detach capability in the DFU functional descriptor */ + if (dfu_config_desc.dfu_func.wDetachTimeOut & DFU_DETACH_MASK) { + usbd_disconnect (udev); + + usbd_connect (udev); + } else { + /* wait for the period of time specified in detach request */ + usb_mdelay (4U); + } +} + +/*! + \brief handle the DFU_DNLOAD request + \param[in] udev: pointer to USB device instance + \param[in] req: DFU class request + \param[out] none + \retval none +*/ +static void dfu_dnload(usb_dev *udev, usb_req *req) +{ + usb_transc *transc = &udev->dev.transc_out[0]; + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; + + switch (dfu->bState) { + case STATE_DFU_IDLE: + case STATE_DFU_DNLOAD_IDLE: + if (req->wLength > 0U) { + /* update the global length and block number */ + dfu->block_num = req->wValue; + dfu->data_len = req->wLength; + + dfu->bState = STATE_DFU_DNLOAD_SYNC; + + transc->remain_len = dfu->data_len; + transc->xfer_buf = dfu->buf; + } else { + dfu->manifest_state = MANIFEST_IN_PROGRESS; + dfu->bState = STATE_DFU_MANIFEST_SYNC; + } + break; + + default: + break; + } +} + +/*! + \brief handles the DFU UPLOAD request. + \param[in] udev: pointer to USB device instance + \param[in] req: DFU class request + \param[out] none + \retval none +*/ +static void dfu_upload (usb_dev *udev, usb_req *req) +{ + uint8_t *phy_addr = NULL; + uint32_t addr = 0U; + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; + + usb_transc *transc = &udev->dev.transc_in[0]; + + if(req->wLength <= 0U) { + dfu->bState = STATE_DFU_IDLE; + return; + } + + switch (dfu->bState) { + case STATE_DFU_IDLE: + case STATE_DFU_UPLOAD_IDLE: + /* update the global length and block number */ + dfu->block_num = req->wValue; + dfu->data_len = req->wLength; + + /* DFU get command */ + if (0U == dfu->block_num) { + /* update the state machine */ + dfu->bState = (dfu->data_len > 3U) ? STATE_DFU_IDLE : STATE_DFU_UPLOAD_IDLE; + + /* store the values of all supported commands */ + dfu->buf[0] = GET_COMMANDS; + dfu->buf[1] = SET_ADDRESS_POINTER; + dfu->buf[2] = ERASE; + + /* send the status data over EP0 */ + transc->xfer_buf = &(dfu->buf[0]); + transc->remain_len = 3U; + } else if (dfu->block_num > 1U) { + dfu->bState = STATE_DFU_UPLOAD_IDLE; + + /* change is accelerated */ + addr = (dfu->block_num - 2U) * TRANSFER_SIZE + dfu->base_addr; + + /* return the physical address where data are stored */ + phy_addr = dfu_mem_read (dfu->buf, addr, dfu->data_len); + + /* send the status data over EP0 */ + transc->xfer_buf = phy_addr; + transc->remain_len = dfu->data_len; + } else { + dfu->bState = STATUS_ERR_STALLEDPKT; + } + break; + + default: + dfu->data_len = 0U; + dfu->block_num = 0U; + break; + } +} + +/*! + \brief handle the DFU_GETSTATUS request + \param[in] udev: pointer to USB device instance + \param[in] req: DFU class request + \param[out] none + \retval none +*/ +static void dfu_getstatus (usb_dev *udev, usb_req *req) +{ + usb_transc *transc = &udev->dev.transc_in[0]; + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; + + switch (dfu->bState) { + case STATE_DFU_DNLOAD_SYNC: + if (0U != dfu->data_len) { + dfu->bState = STATE_DFU_DNBUSY; + + if (0U == dfu->block_num) { + if (ERASE == dfu->buf[0]) { + dfu_mem_getstatus (dfu->base_addr, CMD_ERASE, (uint8_t *)&dfu->bwPollTimeout0); + } else { + dfu_mem_getstatus (dfu->base_addr, CMD_WRITE, (uint8_t *)&dfu->bwPollTimeout0); + } + } + } else { + dfu->bState = STATE_DFU_DNLOAD_IDLE; + } + break; + + case STATE_DFU_MANIFEST_SYNC: + if (MANIFEST_IN_PROGRESS == dfu->manifest_state) { + dfu->bState = STATE_DFU_MANIFEST; + dfu->bwPollTimeout0 = 1U; + } else if ((MANIFEST_COMPLETE == dfu->manifest_state) && \ + (dfu_config_desc.dfu_func.bmAttributes & 0x04U)){ + dfu->bState = STATE_DFU_IDLE; + dfu->bwPollTimeout0 = 0U; + } else { + /* no operation */ + } + break; + + default: + break; + } + + /* send the status data of DFU interface to host over EP0 */ + transc->xfer_buf = (uint8_t *)&(dfu->bStatus); + transc->remain_len = 6U; +} + +/*! + \brief handle the DFU_CLRSTATUS request + \param[in] udev: pointer to USB device instance + \param[in] req: DFU class request + \param[out] none + \retval none +*/ +static void dfu_clrstatus (usb_dev *udev, usb_req *req) +{ + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; + + if (STATE_DFU_ERROR == dfu->bState) { + dfu->bStatus = STATUS_OK; + dfu->bState = STATE_DFU_IDLE; + } else { + /* state error */ + dfu->bStatus = STATUS_ERR_UNKNOWN; + dfu->bState = STATE_DFU_ERROR; + } + + dfu->iString = 0U; /* iString: index = 0 */ +} + +/*! + \brief handle the DFU_GETSTATE request + \param[in] udev: pointer to USB device instance + \param[in] req: DFU class request + \param[out] none + \retval none +*/ +static void dfu_getstate (usb_dev *udev, usb_req *req) +{ + usb_transc *transc = &udev->dev.transc_in[0]; + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; + + /* send the current state of the DFU interface to host */ + transc->xfer_buf = &(dfu->bState); + transc->remain_len = 1U; +} + +/*! + \brief handle the DFU_ABORT request + \param[in] udev: pointer to USB device instance + \param[in] req: DFU class request + \param[out] none + \retval none +*/ +static void dfu_abort (usb_dev *udev, usb_req *req) +{ + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; + + switch (dfu->bState){ + case STATE_DFU_IDLE: + case STATE_DFU_DNLOAD_SYNC: + case STATE_DFU_DNLOAD_IDLE: + case STATE_DFU_MANIFEST_SYNC: + case STATE_DFU_UPLOAD_IDLE: + dfu->bStatus = STATUS_OK; + dfu->bState = STATE_DFU_IDLE; + dfu->iString = 0U; /* iString: index = 0 */ + + dfu->block_num = 0U; + dfu->data_len = 0U; + break; + + default: + break; + } +} + +/*! + \brief convert string value into unicode char + \param[in] str: pointer to plain string + \param[in] pbuf: buffer pointer to store unicode char + \param[out] none + \retval none +*/ +static void string_to_unicode (uint8_t *str, uint16_t *pbuf) +{ + uint8_t index = 0; + + if (str != NULL) { + pbuf[index++] = ((strlen((const char *)str) * 2U + 2U) & 0x00FFU) | ((USB_DESCTYPE_STR << 8U) & 0xFF00); + + while (*str != '\0') { + pbuf[index++] = *str++; + } + } +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/dfu/Source/dfu_mem.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/dfu/Source/dfu_mem.c new file mode 100644 index 00000000..7a1a3cec --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/dfu/Source/dfu_mem.c @@ -0,0 +1,243 @@ +/*! + \file dfu_mem.c + \brief USB DFU device media access layer functions + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "dfu_mem.h" +#include "drv_usb_hw.h" +#include "usbd_transc.h" + +extern usb_core_driver usb_dfu_dev; + +extern struct { + uint8_t buf[TRANSFER_SIZE]; + uint16_t data_len; + uint16_t block_num; + uint32_t base_addr; +} prog; + +dfu_mem_prop* mem_tab[MAX_USED_MEMORY_MEDIA] = { + &dfu_inter_flash_cb, + &dfu_nor_flash_cb, + &dfu_nand_flash_cb, +}; + +/* The list of memory interface string descriptor pointers. This list + can be updated whenever a memory has to be added or removed */ +const uint8_t* USBD_DFU_StringDesc[MAX_USED_MEMORY_MEDIA] = +{ + (const uint8_t *)INTER_FLASH_IF_STR, + (const uint8_t *)NOR_FLASH_IF_STR, + (const uint8_t *)NAND_FLASH_IF_STR +}; + +static uint8_t dfu_mem_checkaddr (uint32_t addr); + +/*! + \brief initialize the memory media on the GD32 + \param[in] none + \param[out] none + \retval MEM_OK +*/ +uint8_t dfu_mem_init (void) +{ + uint32_t mem_index = 0U; + + /* initialize all supported memory medias */ + for (mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++) { + /* check if the memory media exists */ + if (NULL != mem_tab[mem_index]->mem_init) { + mem_tab[mem_index]->mem_init(); + } + } + + return MEM_OK; +} + +/*! + \brief deinitialize the memory media on the GD32 + \param[in] none + \param[out] none + \retval MEM_OK +*/ +uint8_t dfu_mem_deinit (void) +{ + uint32_t mem_index = 0U; + + /* deinitialize all supported memory medias */ + for (mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++) { + /* check if the memory media exists */ + if (NULL != mem_tab[mem_index]->mem_deinit) { + mem_tab[mem_index]->mem_deinit(); + } + } + + return MEM_OK; +} + +/*! + \brief erase a memory sector + \param[in] addr: memory sector address/code + \param[out] none + \retval MEM_OK +*/ +uint8_t dfu_mem_erase (uint32_t addr) +{ + uint32_t mem_index = dfu_mem_checkaddr(addr); + + /* check if the address is in protected area */ + if (IS_PROTECTED_AREA(addr)) { + return MEM_FAIL; + } + + if (mem_index < MAX_USED_MEMORY_MEDIA) { + /* check if the operation is supported */ + if (NULL != mem_tab[mem_index]->mem_erase) { + return mem_tab[mem_index]->mem_erase(addr); + } else { + return MEM_FAIL; + } + } else { + return MEM_FAIL; + } +} + +/*! + \brief write data to sectors of memory + \param[in] buf: the data buffer to be write + \param[in] addr: memory sector address/code + \param[in] len: data length + \param[out] none + \retval MEM_OK +*/ +uint8_t dfu_mem_write (uint8_t *buf, uint32_t addr, uint32_t len) +{ + uint32_t mem_index = dfu_mem_checkaddr(addr); + + /* check if the address is in protected area */ + if (IS_PROTECTED_AREA(addr)) { + return MEM_FAIL; + } + + if ((addr & MAL_MASK_OB) == OB_RDPT) { + option_byte_write(addr, buf); + NVIC_SystemReset(); + + return MEM_OK; + } + + if (mem_index < MAX_USED_MEMORY_MEDIA) { + /* check if the operation is supported */ + if (NULL != mem_tab[mem_index]->mem_write) { + return mem_tab[mem_index]->mem_write(buf, addr, len); + } else { + return MEM_FAIL; + } + } else { + return MEM_FAIL; + } +} + +/*! + \brief read data from sectors of memory + \param[in] buf: the data buffer to be write + \param[in] addr: memory sector address/code + \param[in] len: data length + \param[out] none + \retval pointer to buffer +*/ +uint8_t* dfu_mem_read (uint8_t *buf, uint32_t addr, uint32_t len) +{ + uint32_t mem_index = 0U; + + if (OB_RDPT != addr) { + mem_index = dfu_mem_checkaddr(addr); + } + + if (mem_index < MAX_USED_MEMORY_MEDIA) { + /* check if the operation is supported */ + if (NULL != mem_tab[mem_index]->mem_read) { + return mem_tab[mem_index]->mem_read(buf, addr, len); + } else { + return buf; + } + } else { + return buf; + } +} + +/*! + \brief get the status of a given memory and store in buffer + \param[in] addr: memory sector address/code + \param[in] cmd: 0 for erase and 1 for write + \param[in] buffer: pointer to the buffer where the status data will be stored + \param[out] none + \retval MEM_OK if all operations are OK, MEM_FAIL else +*/ +uint8_t dfu_mem_getstatus (uint32_t addr, uint8_t cmd, uint8_t *buffer) +{ + uint32_t mem_index = dfu_mem_checkaddr(addr); + + if (mem_index < MAX_USED_MEMORY_MEDIA) { + if (cmd & 0x01U) { + POLLING_TIMEOUT_SET(mem_tab[mem_index]->write_timeout); + } else { + POLLING_TIMEOUT_SET(mem_tab[mem_index]->erase_timeout); + } + + return MEM_OK; + } else { + return MEM_FAIL; + } +} + +/*! + \brief check the address is supported + \param[in] addr: memory sector address/code + \param[out] none + \retval index of the addressed memory +*/ +static uint8_t dfu_mem_checkaddr (uint32_t addr) +{ + uint8_t mem_index = 0U; + + /* check with all supported memories */ + for (mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++) { + /* if the check address is supported, return the memory index */ + if (MEM_OK == mem_tab[mem_index]->mem_checkaddr(addr)) { + return mem_index; + } + } + + /* if there is no memory found, return MAX_USED_MEMORY_MEDIA */ + return (MAX_USED_MEMORY_MEDIA); +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/hid/Include/custom_hid_core.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/hid/Include/custom_hid_core.h new file mode 100644 index 00000000..6c86f1ee --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/hid/Include/custom_hid_core.h @@ -0,0 +1,69 @@ +/*! + \file custom_hid_core.h + \brief definitions for HID core + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __CUSTOM_HID_CORE_H +#define __CUSTOM_HID_CORE_H + +#include "usbd_enum.h" +#include "usb_hid.h" + +#define DESC_LEN_REPORT 96U +#define DESC_LEN_CONFIG 41U + +#define NO_CMD 0xFFU + +#define MAX_PERIPH_NUM 4U + +typedef struct { + uint8_t data[2]; + + uint8_t reportID; + uint8_t idlestate; + uint8_t protocol; +} custom_hid_handler; + +typedef struct { + void (*periph_config[MAX_PERIPH_NUM])(void); +} hid_fop_handler; + +extern usb_desc custom_hid_desc; +extern usb_class_core usbd_custom_hid_cb; + +/* function declarations */ +/* register HID interface operation functions */ +uint8_t custom_hid_itfop_register (usb_dev *udev, hid_fop_handler *hid_fop); +/* send custom HID report */ +uint8_t custom_hid_report_send (usb_dev *udev, uint8_t *report, uint32_t len); + +#endif /* __CUSTOM_HID_CORE_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/hid/Include/standard_hid_core.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/hid/Include/standard_hid_core.h new file mode 100644 index 00000000..1af49d32 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/hid/Include/standard_hid_core.h @@ -0,0 +1,68 @@ +/*! + \file standard_hid_core.h + \brief definitions for HID core + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __STANDARD_HID_CORE_H +#define __STANDARD_HID_CORE_H + +#include "usbd_enum.h" +#include "usb_hid.h" + +#define USB_HID_CONFIG_DESC_LEN 0x22U +#define USB_HID_REPORT_DESC_LEN 0x2EU + +#define NO_CMD 0xFFU + +typedef struct { + uint32_t protocol; + uint32_t idle_state; + + uint8_t data[HID_IN_PACKET]; + __IO uint8_t prev_transfer_complete; +} standard_hid_handler; + +typedef struct { + void (*hid_itf_config) (void); + void (*hid_itf_data_process) (usb_dev *udev); +} hid_fop_handler; + +extern usb_desc hid_desc; +extern usb_class_core usbd_hid_cb; + +/* function declarations */ +/* register HID interface operation functions */ +uint8_t hid_itfop_register (usb_dev *udev, hid_fop_handler *hid_fop); +/* send keyboard report */ +uint8_t hid_report_send (usb_dev *udev, uint8_t *report, uint32_t len); + +#endif /* __STANDARD_HID_CORE_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/hid/Source/custom_hid_core.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/hid/Source/custom_hid_core.c new file mode 100644 index 00000000..ef8bef6e --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/hid/Source/custom_hid_core.c @@ -0,0 +1,488 @@ +/*! + \file custom_hid_core.c + \brief custom HID class driver + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "custom_hid_core.h" +#include "usbd_enum.h" +#include + +#define USBD_VID 0x28E9U +#define USBD_PID 0x028AU + +/* Note:it should use the C99 standard when compiling the below codes */ +/* USB standard device descriptor */ +const usb_desc_dev custom_hid_dev_desc = +{ + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV, + }, + .bcdUSB = 0x0200U, + .bDeviceClass = 0x00U, + .bDeviceSubClass = 0x00U, + .bDeviceProtocol = 0x00U, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100U, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM, +}; + +/* USB device configuration descriptor */ +const usb_hid_desc_config_set custom_hid_config_desc = +{ + .config = + { + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, + .wTotalLength = DESC_LEN_CONFIG, + .bNumInterfaces = 0x01U, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0x80U, + .bMaxPower = 0x32U + }, + + .hid_itf = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x02U, + .bInterfaceClass = USB_HID_CLASS, + .bInterfaceSubClass = 0x00U, + .bInterfaceProtocol = 0x00U, + .iInterface = 0x00U + }, + + .hid_vendor = + { + .header = + { + .bLength = sizeof(usb_desc_hid), + .bDescriptorType = USB_DESCTYPE_HID + }, + .bcdHID = 0x0111U, + .bCountryCode = 0x00U, + .bNumDescriptors = 0x01U, + .bDescriptorType = USB_DESCTYPE_REPORT, + .wDescriptorLength = DESC_LEN_REPORT, + }, + + .hid_epin = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = CUSTOMHID_IN_EP, + .bmAttributes = USB_EP_ATTR_INT, + .wMaxPacketSize = CUSTOMHID_IN_PACKET, + .bInterval = 0x20U + }, + + .hid_epout = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = CUSTOMHID_OUT_EP, + .bmAttributes = USB_EP_ATTR_INT, + .wMaxPacketSize = CUSTOMHID_OUT_PACKET, + .bInterval = 0x20U + } +}; + +/* USB language ID descriptor */ +static const usb_desc_LANGID usbd_language_id_desc = +{ + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, + .wLANGID = ENG_LANGID +}; + +/* USB manufacture string */ +static const usb_desc_str manufacturer_string = +{ + .header = + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} +}; + +/* USB product string */ +static const usb_desc_str product_string = +{ + .header = + { + .bLength = USB_STRING_LEN(14U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'D', '3', '2', '-', 'C', 'u', 's', 't', 'o', 'm', 'H', 'I', 'D'} +}; + +/* USBD serial string */ +static usb_desc_str serial_string = +{ + .header = + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + } +}; + +/* USB string descriptor set */ +void *const usbd_hid_strings[] = +{ + [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *)&manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *)&product_string, + [STR_IDX_SERIAL] = (uint8_t *)&serial_string +}; + +usb_desc custom_hid_desc = { + .dev_desc = (uint8_t *)&custom_hid_dev_desc, + .config_desc = (uint8_t *)&custom_hid_config_desc, + .strings = usbd_hid_strings +}; + +const uint8_t customhid_report_descriptor[DESC_LEN_REPORT] = +{ + 0x06, 0x00, 0xFF, /* USAGE_PAGE (Vendor Defined: 0xFF00) */ + 0x09, 0x00, /* USAGE (Custom Device) */ + 0xa1, 0x01, /* COLLECTION (Application) */ + + /* led 1 */ + 0x85, 0x11, /* REPORT_ID (0x11) */ + 0x09, 0x01, /* USAGE (LED 1) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ + + /* led 2 */ + 0x85, 0x12, /* REPORT_ID (0x12) */ + 0x09, 0x02, /* USAGE (LED 2) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ + + /* led 3 */ + 0x85, 0x13, /* REPORT_ID (0x13) */ + 0x09, 0x03, /* USAGE (LED 3) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ + + /* led 4 */ + 0x85, 0x14, /* REPORT_ID (0x14) */ + 0x09, 0x04, /* USAGE (LED 4) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ + + /* wakeup key */ + 0x85, 0x15, /* REPORT_ID (0x15) */ + 0x09, 0x05, /* USAGE (Push Button) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x01, /* REPORT_SIZE (1) */ + 0x81, 0x02, /* INPUT (Data,Var,Abs,Vol) */ + + 0x75, 0x07, /* REPORT_SIZE (7) */ + 0x81, 0x03, /* INPUT (Cnst,Var,Abs,Vol) */ + + /* tamper key */ + 0x85, 0x16, /* REPORT_ID (0x16) */ + 0x09, 0x06, /* USAGE (Push Button) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x01, /* REPORT_SIZE (1) */ + 0x81, 0x02, /* INPUT (Data,Var,Abs,Vol) */ + + 0x75, 0x07, /* REPORT_SIZE (7) */ + 0x81, 0x03, /* INPUT (Cnst,Var,Abs,Vol) */ + + 0xc0 /* END_COLLECTION */ +}; + +/* local function prototypes ('static') */ +static uint8_t custom_hid_init (usb_dev *udev, uint8_t config_index); +static uint8_t custom_hid_deinit (usb_dev *udev, uint8_t config_index); +static uint8_t custom_hid_req_handler (usb_dev *udev, usb_req *req); + +static uint8_t custom_hid_data_in (usb_dev *udev, uint8_t ep_num); +static uint8_t custom_hid_data_out (usb_dev *udev, uint8_t ep_num); + +usb_class_core usbd_custom_hid_cb = +{ + .command = NO_CMD, + .alter_set = 0U, + + .init = custom_hid_init, + .deinit = custom_hid_deinit, + + .req_proc = custom_hid_req_handler, + + .data_in = custom_hid_data_in, + .data_out = custom_hid_data_out +}; + +/*! + \brief register HID interface operation functions + \param[in] udev: pointer to USB device instance + \param[in] hid_fop: HID operation functions structure + \param[out] none + \retval USB device operation status +*/ +uint8_t custom_hid_itfop_register (usb_dev *udev, hid_fop_handler *hid_fop) +{ + if (NULL != hid_fop) { + udev->dev.user_data = hid_fop; + + return USBD_OK; + } + + return USBD_FAIL; +} + +/*! + \brief send custom HID report + \param[in] udev: pointer to USB device instance + \param[in] report: pointer to HID report + \param[in] len: data length + \param[out] none + \retval USB device operation status +*/ +uint8_t custom_hid_report_send (usb_dev *udev, uint8_t *report, uint32_t len) +{ + usbd_ep_send (udev, CUSTOMHID_IN_EP, report, len); + + return USBD_OK; +} + +/*! + \brief initialize the HID device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t custom_hid_init (usb_dev *udev, uint8_t config_index) +{ + static custom_hid_handler hid_handler; + + memset((void *)&hid_handler, 0U, sizeof(custom_hid_handler)); + + /* initialize the data Tx endpoint */ + usbd_ep_setup (udev, &(custom_hid_config_desc.hid_epin)); + + /* initialize the data Rx endpoint */ + usbd_ep_setup (udev, &(custom_hid_config_desc.hid_epout)); + + /* prepare receive data */ + usbd_ep_recev (udev, CUSTOMHID_OUT_EP, hid_handler.data, 2U); + + udev->dev.class_data[CUSTOM_HID_INTERFACE] = (void *)&hid_handler; + + if (udev->dev.user_data != NULL) { + for (uint8_t i = 0U; i < MAX_PERIPH_NUM; i++) { + if (((hid_fop_handler *)udev->dev.user_data)->periph_config[i] != NULL) { + ((hid_fop_handler *)udev->dev.user_data)->periph_config[i](); + } + } + } + + return USBD_OK; +} + +/*! + \brief deinitialize the HID device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t custom_hid_deinit (usb_dev *udev, uint8_t config_index) +{ + /* deinitialize HID endpoints */ + usbd_ep_clear(udev, CUSTOMHID_IN_EP); + usbd_ep_clear(udev, CUSTOMHID_OUT_EP); + + return USBD_OK; +} + +/*! + \brief handle the HID class-specific requests + \param[in] udev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t custom_hid_req_handler (usb_dev *udev, usb_req *req) +{ + usb_transc *transc = &udev->dev.transc_in[0]; + + custom_hid_handler *hid = (custom_hid_handler *)udev->dev.class_data[CUSTOM_HID_INTERFACE]; + + switch (req->bRequest) { + case GET_REPORT: + break; + + case GET_IDLE: + transc->xfer_buf = (uint8_t *)&hid->idlestate; + transc->remain_len = 1U; + break; + + case GET_PROTOCOL: + transc->xfer_buf = (uint8_t *)&hid->protocol; + transc->remain_len = 1U; + break; + + case SET_REPORT: + hid->reportID = (uint8_t)(req->wValue); + break; + + case SET_IDLE: + hid->idlestate = (uint8_t)(req->wValue >> 8U); + break; + + case SET_PROTOCOL: + hid->protocol = (uint8_t)(req->wValue); + break; + + case USB_GET_DESCRIPTOR: + if (USB_DESCTYPE_REPORT == (req->wValue >> 8U)) { + transc->remain_len = USB_MIN(DESC_LEN_REPORT, req->wLength); + transc->xfer_buf = (uint8_t *)customhid_report_descriptor; + } + break; + + default: + return USBD_FAIL; + } + + return USBD_OK; +} + +/*! + \brief handle custom HID data + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier + \param[out] none + \retval USB device operation status +*/ +static uint8_t custom_hid_data_in (usb_dev *udev, uint8_t ep_num) +{ + return USBD_OK; +} + +/*! + \brief handle custom HID data + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier + \param[out] none + \retval USB device operation status +*/ +static uint8_t custom_hid_data_out (usb_dev *udev, uint8_t ep_num) +{ + custom_hid_handler *hid = (custom_hid_handler *)udev->dev.class_data[CUSTOM_HID_INTERFACE]; + + /* light the LED */ + switch (hid->data[0]){ + case 0x11U: + if (RESET != hid->data[1]) { + gd_eval_led_on(LED1); + } else { + gd_eval_led_off(LED1); + } + break; + + case 0x12U: + if (RESET != hid->data[1]) { + gd_eval_led_on(LED2); + } else { + gd_eval_led_off(LED2); + } + break; + + case 0x13U: + if (RESET != hid->data[1]) { + gd_eval_led_on(LED3); + } else { + gd_eval_led_off(LED3); + } + break; + + case 0x14U: + if(RESET != hid->data[1]) { + gd_eval_led_on(LED4); + } else { + gd_eval_led_off(LED4); + } + break; + + default: + break; + } + + usbd_ep_recev (udev, CUSTOMHID_OUT_EP, hid->data, 2U); + + return USBD_OK; +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/hid/Source/standard_hid_core.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/hid/Source/standard_hid_core.c new file mode 100644 index 00000000..d05bd9e7 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/hid/Source/standard_hid_core.c @@ -0,0 +1,389 @@ +/*! + \file standard_hid_core.c + \brief HID class driver + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "standard_hid_core.h" +#include + +#define USBD_VID 0x28e9U +#define USBD_PID 0x0380U + +/* Note:it should use the C99 standard when compiling the below codes */ +/* USB standard device descriptor */ +const usb_desc_dev hid_dev_desc = +{ + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, + .bcdUSB = 0x0200U, + .bDeviceClass = 0x00U, + .bDeviceSubClass = 0x00U, + .bDeviceProtocol = 0x00U, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100U, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM +}; + +const usb_hid_desc_config_set hid_config_desc = +{ + .config = + { + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, + .wTotalLength = USB_HID_CONFIG_DESC_LEN, + .bNumInterfaces = 0x01U, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0xA0U, + .bMaxPower = 0x32U + }, + + .hid_itf = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x01U, + .bInterfaceClass = USB_HID_CLASS, + .bInterfaceSubClass = USB_HID_SUBCLASS_BOOT_ITF, + .bInterfaceProtocol = USB_HID_PROTOCOL_KEYBOARD, + .iInterface = 0x00U + }, + + .hid_vendor = + { + .header = + { + .bLength = sizeof(usb_desc_hid), + .bDescriptorType = USB_DESCTYPE_HID + }, + .bcdHID = 0x0111U, + .bCountryCode = 0x00U, + .bNumDescriptors = 0x01U, + .bDescriptorType = USB_DESCTYPE_REPORT, + .wDescriptorLength = USB_HID_REPORT_DESC_LEN, + }, + + .hid_epin = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = HID_IN_EP, + .bmAttributes = USB_EP_ATTR_INT, + .wMaxPacketSize = HID_IN_PACKET, + .bInterval = 0x10U + } +}; + +/* USB language ID Descriptor */ +const usb_desc_LANGID usbd_language_id_desc = +{ + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, + .wLANGID = ENG_LANGID +}; + +/* USB manufacture string */ +static const usb_desc_str manufacturer_string = +{ + .header = + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} +}; + +/* USB product string */ +static const usb_desc_str product_string = +{ + .header = + { + .bLength = USB_STRING_LEN(17U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'K', 'e', 'y', 'b', 'o', 'a', 'r', 'd'} +}; + +/* USBD serial string */ +static usb_desc_str serial_string = +{ + .header = + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + } +}; + +void *const usbd_hid_strings[] = +{ + [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *)&manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *)&product_string, + [STR_IDX_SERIAL] = (uint8_t *)&serial_string +}; + +usb_desc hid_desc = { + .dev_desc = (uint8_t *)&hid_dev_desc, + .config_desc = (uint8_t *)&hid_config_desc, + .strings = usbd_hid_strings +}; + +const uint8_t hid_report_desc[USB_HID_REPORT_DESC_LEN] = +{ + 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */ + 0x09, 0x06, /* USAGE (Keyboard) */ + 0xa1, 0x01, /* COLLECTION (Application) */ + + 0x05, 0x07, /* USAGE_PAGE (Keyboard/Keypad) */ + 0x19, 0xe0, /* USAGE_MINIMUM (Keyboard LeftControl) */ + 0x29, 0xe7, /* USAGE_MAXIMUM (Keyboard Right GUI) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x95, 0x08, /* REPORT_COUNT (8) */ + 0x75, 0x01, /* REPORT_SIZE (1) */ + 0x81, 0x02, /* INPUT (Data,Var,Abs) */ + + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x81, 0x03, /* INPUT (Cnst,Var,Abs) */ + + 0x95, 0x06, /* REPORT_COUNT (6) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x26, 0xFF, 0x00, /* LOGICAL_MAXIMUM (255) */ + 0x05, 0x07, /* USAGE_PAGE (Keyboard/Keypad) */ + 0x19, 0x00, /* USAGE_MINIMUM (Reserved (no event indicated)) */ + 0x29, 0x65, /* USAGE_MAXIMUM (Keyboard Application) */ + 0x81, 0x00, /* INPUT (Data,Ary,Abs) */ + + 0xc0 /* END_COLLECTION */ +}; + +/* local function prototypes ('static') */ +static uint8_t hid_init (usb_dev *udev, uint8_t config_index); +static uint8_t hid_deinit (usb_dev *udev, uint8_t config_index); +static uint8_t hid_req (usb_dev *udev, usb_req *req); +static uint8_t hid_data_in (usb_dev *udev, uint8_t ep_num); + +usb_class_core usbd_hid_cb = { + .command = NO_CMD, + .alter_set = 0U, + + .init = hid_init, + .deinit = hid_deinit, + .req_proc = hid_req, + .data_in = hid_data_in +}; + +/*! + \brief register HID interface operation functions + \param[in] udev: pointer to USB device instance + \param[in] hid_fop: HID operation function structure + \param[out] none + \retval USB device operation status +*/ +uint8_t hid_itfop_register (usb_dev *udev, hid_fop_handler *hid_fop) +{ + if (NULL != hid_fop) { + udev->dev.user_data = (void *)hid_fop; + + return USBD_OK; + } + + return USBD_FAIL; +} + +/*! + \brief send keyboard report + \param[in] udev: pointer to USB device instance + \param[in] report: pointer to HID report + \param[in] len: data length + \param[out] none + \retval USB device operation status +*/ +uint8_t hid_report_send (usb_dev *udev, uint8_t *report, uint32_t len) +{ + standard_hid_handler *hid = (standard_hid_handler *)udev->dev.class_data[USBD_HID_INTERFACE]; + + hid->prev_transfer_complete = 0U; + + usbd_ep_send(udev, HID_IN_EP, report, len); + + return USBD_OK; +} + +/*! + \brief initialize the HID device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t hid_init(usb_dev *udev, uint8_t config_index) +{ + static standard_hid_handler hid_handler; + + memset((void *)&hid_handler, 0U, sizeof(standard_hid_handler)); + + /* initialize the data TX endpoint */ + usbd_ep_setup (udev, &(hid_config_desc.hid_epin)); + + hid_handler.prev_transfer_complete = 1U; + + udev->dev.class_data[USBD_HID_INTERFACE] = (void *)&hid_handler; + + if (NULL != udev->dev.user_data) { + ((hid_fop_handler *)udev->dev.user_data)->hid_itf_config(); + } + + return USBD_OK; +} + +/*! + \brief deinitialize the HID device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t hid_deinit (usb_dev *udev, uint8_t config_index) +{ + /* deinitialize HID endpoints */ + usbd_ep_clear(udev, HID_IN_EP); + + return USBD_OK; +} + +/*! + \brief handle the HID class-specific requests + \param[in] udev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t hid_req (usb_dev *udev, usb_req *req) +{ + usb_transc *transc = &udev->dev.transc_in[0]; + + standard_hid_handler *hid = (standard_hid_handler *)udev->dev.class_data[USBD_HID_INTERFACE]; + + switch (req->bRequest) { + case GET_REPORT: + /* no use for this driver */ + break; + + case GET_IDLE: + transc->xfer_buf = (uint8_t *)&hid->idle_state; + + transc->remain_len = 1U; + break; + + case GET_PROTOCOL: + transc->xfer_buf = (uint8_t *)&hid->protocol; + + transc->remain_len = 1U; + break; + + case SET_REPORT: + /* no use for this driver */ + break; + + case SET_IDLE: + hid->idle_state = (uint8_t)(req->wValue >> 8U); + break; + + case SET_PROTOCOL: + hid->protocol = (uint8_t)(req->wValue); + break; + + case USB_GET_DESCRIPTOR: + if (USB_DESCTYPE_REPORT == (req->wValue >> 8U)) { + transc->remain_len = USB_MIN(USB_HID_REPORT_DESC_LEN, req->wLength); + transc->xfer_buf = (uint8_t *)hid_report_desc; + + return REQ_SUPP; + } else if (USB_DESCTYPE_HID == (req->wValue >> 8U)) { + transc->remain_len = USB_MIN(9U, req->wLength); + transc->xfer_buf = (uint8_t *)(&(hid_config_desc.hid_vendor)); + } + break; + + default: + break; + } + + return USBD_OK; +} + +/*! + \brief handle data stage + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier + \param[out] none + \retval USB device operation status +*/ +static uint8_t hid_data_in (usb_dev *udev, uint8_t ep_num) +{ + standard_hid_handler *hid = (standard_hid_handler *)udev->dev.class_data[USBD_HID_INTERFACE]; + + if (0U != hid->data[2]) { + hid->data[2] = 0x00U; + + usbd_ep_send(udev, HID_IN_EP, hid->data, HID_IN_PACKET); + } else { + hid->prev_transfer_complete = 1U; + } + + return USBD_OK; +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/iap/Include/usb_iap_core.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/iap/Include/usb_iap_core.h new file mode 100644 index 00000000..17668ac7 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/iap/Include/usb_iap_core.h @@ -0,0 +1,89 @@ +/*! + \file usb_iap_core.h + \brief the header file of IAP driver + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_IAP_CORE_H +#define __USB_IAP_CORE_H + +#include "usbd_enum.h" +#include "usb_hid.h" + +#define USB_SERIAL_STRING_SIZE 0x06U + +#ifdef USE_USB_FS + #define USB_DESC_LEN_IAP_REPORT 35U +#endif /* USE_USB_FS */ + +#define USB_DESC_LEN_IAP_CONFIG_SET 41U + +/* special commands with download request */ +#define IAP_OPTION_BYTE1 0x01U +#define IAP_ERASE 0x02U +#define IAP_DNLOAD 0x03U +#define IAP_LEAVE 0x04U +#define IAP_GETBIN_ADDRESS 0x05U +#define IAP_OPTION_BYTE2 0x06U + +typedef struct +{ + uint8_t option_byte[IAP_IN_PACKET]; + + /* state machine variables */ + uint8_t dev_status[IAP_IN_PACKET]; + uint8_t bin_addr[IAP_IN_PACKET]; + + uint8_t report_buf[IAP_OUT_PACKET + 1U]; + + uint8_t reportID; + uint8_t flag; + + uint32_t protocol; + uint32_t idlestate; + + uint16_t transfer_times; + uint16_t page_count; + uint16_t lps; /* last packet size */ + uint32_t file_length; + uint32_t base_address; +} usbd_iap_handler; + +typedef void (*app_func)(void); + +extern usb_desc iap_desc; +extern usb_class_core iap_class; + +/* function declarations */ +/* send IAP report */ +uint8_t iap_report_send (usb_dev *udev, uint8_t *report, uint32_t len); + +#endif /* __USB_IAP_CORE_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/iap/Source/usb_iap_core.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/iap/Source/usb_iap_core.c new file mode 100644 index 00000000..3e125d81 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/iap/Source/usb_iap_core.c @@ -0,0 +1,561 @@ +/*! + \file usb_iap_core.c + \brief IAP driver + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usb_iap_core.h" +#include "flash_operation.h" +#include + +#define USBD_VID 0x28E9U +#define USBD_PID 0x0228U + +/* Note:it should use the C99 standard when compiling the below codes */ +/* USB standard device descriptor */ +__ALIGN_BEGIN const usb_desc_dev iap_dev_desc __ALIGN_END = +{ + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, + .bcdUSB = 0x0200U, + .bDeviceClass = 0x00U, + .bDeviceSubClass = 0x00U, + .bDeviceProtocol = 0x00U, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100U, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM +}; + +__ALIGN_BEGIN const usb_hid_desc_config_set iap_config_desc __ALIGN_END = +{ + .config = + { + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, + .wTotalLength = USB_DESC_LEN_IAP_CONFIG_SET, + .bNumInterfaces = 0x01U, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0x80U, + .bMaxPower = 0x32U + }, + + .hid_itf = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x02U, + .bInterfaceClass = USB_HID_CLASS, + .bInterfaceSubClass = 0x00U, + .bInterfaceProtocol = 0x00U, + .iInterface = 0x00U + }, + + .hid_vendor = + { + .header = + { + .bLength = sizeof(usb_desc_hid), + .bDescriptorType = USB_DESCTYPE_HID + }, + .bcdHID = 0x0111U, + .bCountryCode = 0x00U, + .bNumDescriptors = 0x01U, + .bDescriptorType = USB_DESCTYPE_REPORT, + .wDescriptorLength = USB_DESC_LEN_IAP_REPORT, + }, + + .hid_epin = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = IAP_IN_EP, + .bmAttributes = USB_EP_ATTR_INT, + .wMaxPacketSize = IAP_IN_PACKET, + .bInterval = 0x01U + }, + + .hid_epout = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = IAP_OUT_EP, + .bmAttributes = USB_EP_ATTR_INT, + .wMaxPacketSize = IAP_OUT_PACKET, + .bInterval = 0x01U + } +}; + +/* USB language ID Descriptor */ +static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = +{ + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, + .wLANGID = ENG_LANGID +}; + +/* USB manufacture string */ +static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = +{ + .header = + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} +}; + +/* USB product string */ +static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = +{ + .header = + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'I', 'A', 'P'} +}; + +/* USBD serial string */ +static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = +{ + .header = + { + .bLength = USB_STRING_LEN(2U), + .bDescriptorType = USB_DESCTYPE_STR, + } +}; + +void *const usbd_iap_strings[] = +{ + [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *)&manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *)&product_string, + [STR_IDX_SERIAL] = (uint8_t *)&serial_string +}; + +usb_desc iap_desc = { + .dev_desc = (uint8_t *)&iap_dev_desc, + .config_desc = (uint8_t *)&iap_config_desc, + .strings = usbd_iap_strings +}; + +/* local function prototypes ('static') */ +static uint8_t iap_init (usb_dev *udev, uint8_t config_index); +static uint8_t iap_deinit (usb_dev *udev, uint8_t config_index); +static uint8_t iap_req_handler (usb_dev *udev, usb_req *req); +static uint8_t iap_data_out (usb_dev *udev, uint8_t ep_num); + +/* IAP requests management functions */ +static void iap_req_erase (usb_dev *udev); +static void iap_req_dnload (usb_dev *udev); +static void iap_req_optionbyte (usb_dev *udev, uint8_t option_num); +static void iap_req_leave (usb_dev *udev); +static void iap_address_send (usb_dev *udev); + +usb_class_core iap_class = { + .init = iap_init, + .deinit = iap_deinit, + .req_proc = iap_req_handler, + .data_out = iap_data_out +}; + +/* USB custom HID device report descriptor */ +__ALIGN_BEGIN const uint8_t iap_report_desc[USB_DESC_LEN_IAP_REPORT] __ALIGN_END = +{ + 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */ + 0x09, 0x00, /* USAGE (Custom Device) */ + 0xa1, 0x01, /* COLLECTION (Application) */ + + /* IAP command and data */ + 0x85, 0x01, /* REPORT_ID (0x01) */ + 0x09, 0x01, /* USAGE (IAP command) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0xff, /* LOGICAL_MAXIMUM (255) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, REPORT_OUT_COUNT, + 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ + + /* device status and option byte */ + 0x85, 0x02, /* REPORT_ID (0x02) */ + 0x09, 0x02, /* USAGE (Status and option byte) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0xff, /* LOGICAL_MAXIMUM (255) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, REPORT_IN_COUNT, /* REPORT_COUNT (23) */ + 0x81, 0x82, /* INPUT (Data,Var,Abs,Vol) */ + + 0xc0 /* END_COLLECTION */ +}; + +/*! + \brief send IAP report + \param[in] udev: pointer to USB device instance + \param[in] report: pointer to HID report + \param[in] len: data length + \param[out] none + \retval USB device operation status +*/ +uint8_t iap_report_send (usb_dev *udev, uint8_t *report, uint32_t len) +{ + usbd_ep_send (udev, IAP_IN_EP, report, len); + + return USBD_OK; +} + +/*! + \brief initialize the IAP device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t iap_init (usb_dev *udev, uint8_t config_index) +{ + static __ALIGN_BEGIN usbd_iap_handler iap_handler __ALIGN_END; + + /* initialize Tx endpoint */ + usbd_ep_setup(udev, &(iap_config_desc.hid_epin)); + + /* initialize Rx endpoint */ + usbd_ep_setup(udev, &(iap_config_desc.hid_epout)); + + /* unlock the internal flash */ + fmc_unlock(); + + memset((void *)&iap_handler, 0U, sizeof(usbd_iap_handler)); + + /* prepare receive data */ + usbd_ep_recev(udev, IAP_OUT_EP, iap_handler.report_buf, IAP_OUT_PACKET); + + iap_handler.base_address = APP_LOADED_ADDR; + + udev->dev.class_data[USBD_IAP_INTERFACE] = (void *)&iap_handler; + + return USBD_OK; +} + +/*! + \brief deinitialize the IAP device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t iap_deinit (usb_dev *udev, uint8_t config_index) +{ + /* deinitialize IAP endpoints */ + usbd_ep_clear (udev, IAP_IN_EP); + usbd_ep_clear (udev, IAP_OUT_EP); + + /* lock the internal flash */ + fmc_lock(); + + return USBD_OK; +} + +/*! + \brief handle the IAP class-specific requests + \param[in] udev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t iap_req_handler (usb_dev *udev, usb_req *req) +{ + usb_transc *transc = &udev->dev.transc_in[0]; + + usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE]; + + switch (req->bRequest) { + case GET_REPORT: + /* no use for this driver */ + break; + + case GET_IDLE: + transc->xfer_buf = (uint8_t *)&iap->idlestate; + transc->remain_len = 1U; + break; + + case GET_PROTOCOL: + transc->xfer_buf = (uint8_t *)&iap->protocol; + transc->remain_len = 1U; + break; + + case SET_REPORT: + iap->reportID = (uint8_t)(req->wValue); + break; + + case SET_IDLE: + iap->idlestate = (uint8_t)(req->wValue >> 8U); + break; + + case SET_PROTOCOL: + iap->protocol = (uint8_t)(req->wValue); + break; + + case USB_GET_DESCRIPTOR: + if (USB_DESCTYPE_REPORT == (req->wValue >> 8U)) { + transc->remain_len = USB_MIN(USB_DESC_LEN_IAP_REPORT, req->wLength); + transc->xfer_buf = (uint8_t *)iap_report_desc; + } + break; + + default: + return USBD_FAIL; + } + + return USBD_OK; +} + +/*! + \brief handle data out stage + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier + \param[out] none + \retval none +*/ +static uint8_t iap_data_out (usb_dev *udev ,uint8_t ep_num) +{ + usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE]; + + if (0x01U == iap->report_buf[0]) { + switch (iap->report_buf[1]) { + case IAP_DNLOAD: + iap_req_dnload(udev); + break; + + case IAP_ERASE: + iap_req_erase(udev); + break; + + case IAP_OPTION_BYTE1: + iap_req_optionbyte(udev, 0x01U); + break; + + case IAP_LEAVE: + iap_req_leave(udev); + break; + + case IAP_GETBIN_ADDRESS: + iap_address_send(udev); + break; + + case IAP_OPTION_BYTE2: + iap_req_optionbyte(udev, 0x02U); + break; + + default: + break; + } + } + + usbd_ep_recev(udev, IAP_OUT_EP, iap->report_buf, IAP_OUT_PACKET); + + return USBD_OK; +} + +/*! + \brief handle the IAP_DNLOAD request + \param[in] udev: pointer to usb device instance + \param[out] none + \retval none +*/ +static void iap_req_dnload(usb_dev *udev) +{ + usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE]; + + if (0U != iap->transfer_times) { + if (1U == iap->transfer_times) { + if (0U == iap->lps) { + iap_data_write(&iap->report_buf[2], iap->base_address, TRANSFER_SIZE); + } else { + iap_data_write(&iap->report_buf[2], iap->base_address, iap->file_length % TRANSFER_SIZE); + iap->lps = 0U; + } + + iap->dev_status[0] = 0x02U; + iap->dev_status[1] = 0x02U; + iap_report_send (udev, iap->dev_status, IAP_IN_PACKET); + } else { + iap_data_write(&iap->report_buf[2], iap->base_address, TRANSFER_SIZE); + + iap->base_address += TRANSFER_SIZE; + } + + iap->transfer_times--; + } +} + +/*! + \brief handle the IAP_ERASE request + \param[in] udev: pointer to usb device instance + \param[out] none + \retval none +*/ +static void iap_req_erase(usb_dev *udev) +{ + uint32_t addr = 0U; + + usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE]; + + /* get base address to erase */ + iap->base_address = iap->report_buf[2]; + iap->base_address |= iap->report_buf[3] << 8U; + iap->base_address |= iap->report_buf[4] << 16U; + iap->base_address |= iap->report_buf[5] << 24U; + + /* get file length */ + iap->file_length = iap->report_buf[7]; + iap->file_length |= iap->report_buf[8] << 8U; + iap->file_length |= iap->report_buf[9] << 16U; + iap->file_length |= iap->report_buf[10] << 24U; + + iap->lps = iap->file_length % TRANSFER_SIZE; + if (0U == iap->lps) { + iap->transfer_times = iap->file_length / TRANSFER_SIZE; + } else { + iap->transfer_times = iap->file_length / TRANSFER_SIZE + 1U; + } + + /* check if the address is in protected area */ + if (IS_PROTECTED_AREA(iap->base_address)) { + return; + } + + addr = iap->base_address; + + /* unlock the flash program erase controller */ + fmc_unlock(); + + flash_erase(addr, iap->file_length, iap->report_buf); + + fmc_lock(); + + iap->dev_status[0] = 0x02U; + iap->dev_status[1] = 0x01U; + + usbd_ep_send(udev, IAP_IN_EP, iap->dev_status, IAP_IN_PACKET); +} + +/*! + \brief handle the IAP_OPTION_BYTE request + \param[in] udev: pointer to USB device instance + \param[in] option_num: number of option byte + \param[out] none + \retval none +*/ +static void iap_req_optionbyte(usb_dev *udev, uint8_t option_num) +{ + uint8_t i = 0U; + uint32_t address = 0U; + + usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE]; + + iap->option_byte[0] = 0x02U; + + if (0x01U == option_num) { + address = OPT_BYTE_ADDR1; +#ifdef OPT_BYTE_ADDR2 + } else if (0x02U == option_num) { + address = OPT_BYTE_ADDR2; +#endif + } else { + return; + } + + for (i = 1U; i < 17U; i++) { + iap->option_byte[i] = *(uint8_t *)address; + address++; + } + + iap_report_send (udev, iap->option_byte, IAP_IN_PACKET); +} + +/*! + \brief handle the IAP_LEAVE request + \param[in] udev: pointer to usb device instance + \param[out] none + \retval none +*/ +static void iap_req_leave(usb_dev *udev) +{ + /* lock the internal flash */ + fmc_lock(); + + /* generate system reset to allow jumping to the user code */ + NVIC_SystemReset(); +} + +/*! + \brief handle the IAP_SEND_ADDRESS request + \param[in] udev: pointer to usb device instance + \param[out] none + \retval none +*/ +static void iap_address_send(usb_dev *udev) +{ + usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE]; + + iap->bin_addr[0] = 0x02U; + + iap->bin_addr[1] = (uint8_t)(APP_LOADED_ADDR); + iap->bin_addr[2] = (uint8_t)(APP_LOADED_ADDR >> 8U); + iap->bin_addr[3] = (uint8_t)(APP_LOADED_ADDR >> 16U); + iap->bin_addr[4] = (uint8_t)(APP_LOADED_ADDR >> 24U); + + iap_report_send (udev, iap->bin_addr, IAP_IN_PACKET); +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Include/usbd_msc_bbb.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Include/usbd_msc_bbb.h new file mode 100644 index 00000000..f5457744 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Include/usbd_msc_bbb.h @@ -0,0 +1,101 @@ +/*! + \file usbd_msc_bbb.h + \brief the header file of the usbd_msc_bbb.c file + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_MSC_BBB_H +#define __USBD_MSC_BBB_H + +#include "usbd_core.h" +#include "msc_bbb.h" +#include "usbd_msc_mem.h" +#include "usbd_msc_scsi.h" + +/* MSC BBB state */ +enum msc_bbb_state { + BBB_IDLE = 0U, /*!< idle state */ + BBB_DATA_OUT, /*!< data OUT state */ + BBB_DATA_IN, /*!< data IN state */ + BBB_LAST_DATA_IN, /*!< last data IN state */ + BBB_SEND_DATA /*!< send immediate data state */ +}; + +/* MSC BBB status */ +enum msc_bbb_status { + BBB_STATUS_NORMAL = 0U, /*!< normal status */ + BBB_STATUS_RECOVERY, /*!< recovery status*/ + BBB_STATUS_ERROR /*!< error status */ +}; + +typedef struct +{ + uint8_t bbb_data[MSC_MEDIA_PACKET_SIZE]; + + uint8_t max_lun; + uint8_t bbb_state; + uint8_t bbb_status; + + uint32_t bbb_datalen; + + msc_bbb_cbw bbb_cbw; + msc_bbb_csw bbb_csw; + + uint8_t scsi_sense_head; + uint8_t scsi_sense_tail; + + uint32_t scsi_blk_size[MEM_LUN_NUM]; + uint32_t scsi_blk_nbr[MEM_LUN_NUM]; + + uint32_t scsi_blk_addr; + uint32_t scsi_blk_len; + uint32_t scsi_disk_pop; + + msc_scsi_sense scsi_sense[SENSE_LIST_DEEPTH]; +} usbd_msc_handler; + +/* function declarations */ +/* initialize the bbb process */ +void msc_bbb_init (usb_core_driver *udev); +/* reset the BBB machine */ +void msc_bbb_reset (usb_core_driver *udev); +/* deinitialize the BBB machine */ +void msc_bbb_deinit (usb_core_driver *udev); +/* handle BBB data IN stage */ +void msc_bbb_data_in (usb_core_driver *udev, uint8_t ep_num); +/* handle BBB data OUT stage */ +void msc_bbb_data_out (usb_core_driver *udev, uint8_t ep_num); +/* send the CSW(command status wrapper) */ +void msc_bbb_csw_send (usb_core_driver *udev, uint8_t csw_status); +/* complete the clear feature request */ +void msc_bbb_clrfeature (usb_core_driver *udev, uint8_t ep_num); + +#endif /* __USBD_MSC_BBB_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Include/usbd_msc_core.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Include/usbd_msc_core.h new file mode 100644 index 00000000..730465d2 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Include/usbd_msc_core.h @@ -0,0 +1,59 @@ +/*! + \file usbd_msc_core.h + \brief the header file of USB MSC device class core functions + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_MSC_CORE_H +#define __USBD_MSC_CORE_H + +#include "usbd_core.h" +#include "usb_msc.h" + +#define USB_MSC_CONFIG_DESC_SIZE 32U + +#define MSC_EPIN_SIZE MSC_DATA_PACKET_SIZE +#define MSC_EPOUT_SIZE MSC_DATA_PACKET_SIZE + +/* USB configuration descriptor structure */ +typedef struct +{ + usb_desc_config config; + + usb_desc_itf msc_itf; + usb_desc_ep msc_epin; + usb_desc_ep msc_epout; +} usb_desc_config_set; + +extern usb_desc msc_desc; +extern usb_class_core msc_class; + +#endif /* __USBD_MSC_CORE_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Include/usbd_msc_mem.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Include/usbd_msc_mem.h new file mode 100644 index 00000000..eec6a256 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Include/usbd_msc_mem.h @@ -0,0 +1,59 @@ +/*! + \file usbd_msc_mem.h + \brief header file for storage memory + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_MSC_MEM_H +#define __USBD_MSC_MEM_H + +#include "usbd_conf.h" + +#define USBD_STD_INQUIRY_LENGTH 36U + +typedef struct +{ + int8_t (*mem_init) (uint8_t lun); + int8_t (*mem_ready) (uint8_t lun); + int8_t (*mem_protected) (uint8_t lun); + int8_t (*mem_read) (uint8_t lun, uint8_t *buf, uint32_t block_addr, uint16_t block_len); + int8_t (*mem_write) (uint8_t lun, uint8_t *buf, uint32_t block_addr, uint16_t block_len); + int8_t (*mem_maxlun) (void); + + uint8_t *mem_toc_data; + uint8_t *mem_inquiry_data[MEM_LUN_NUM]; + uint32_t mem_block_size[MEM_LUN_NUM]; + uint32_t mem_block_len[MEM_LUN_NUM]; +} usbd_mem_cb; + +extern usbd_mem_cb *usbd_mem_fops; + +#endif /* __USBD_MSC_MEM_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Include/usbd_msc_scsi.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Include/usbd_msc_scsi.h new file mode 100644 index 00000000..889a2551 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Include/usbd_msc_scsi.h @@ -0,0 +1,58 @@ +/*! + \file usbd_msc_scsi.h + \brief the header file of the usbd_msc_scsi.c file + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_MSC_SCSI_H +#define __USBD_MSC_SCSI_H + +#include "usbd_msc_bbb.h" +#include "msc_scsi.h" + +#define SENSE_LIST_DEEPTH 4U + +#define MODE_SENSE6_LENGTH 8U +#define MODE_SENSE10_LENGTH 8U +#define INQUIRY_PAGE00_LENGTH 96U +#define FORMAT_CAPACITIES_LENGTH 20U + +extern const uint8_t msc_page00_inquiry_data[]; +extern const uint8_t msc_mode_sense6_data[]; +extern const uint8_t msc_mode_sense10_data[]; + +/* function declarations */ +/* process SCSI commands */ +int8_t scsi_process_cmd (usb_core_driver *udev, uint8_t lun, uint8_t *cmd); +/* load the last error code in the error list */ +void scsi_sense_code (usb_core_driver *udev, uint8_t lun, uint8_t skey, uint8_t asc); + +#endif /* __USBD_MSC_SCSI_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Source/usbd_msc_bbb.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Source/usbd_msc_bbb.c new file mode 100644 index 00000000..b2bfbaaf --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Source/usbd_msc_bbb.c @@ -0,0 +1,287 @@ +/*! + \file usbd_msc_bbb.c + \brief USB BBB(Bulk/Bulk/Bulk) protocol core functions + \note BBB means Bulk-only transport protocol for USB MSC + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_enum.h" +#include "usbd_msc_bbb.h" + +/* local function prototypes ('static') */ +static void msc_bbb_cbw_decode (usb_core_driver *udev); +static void msc_bbb_data_send (usb_core_driver *udev, uint8_t *pbuf, uint32_t Len); +static void msc_bbb_abort (usb_core_driver *udev); + +/*! + \brief initialize the bbb process + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void msc_bbb_init (usb_core_driver *udev) +{ + uint8_t lun_num; + + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_state = BBB_IDLE; + msc->bbb_status = BBB_STATUS_NORMAL; + + /* initializes the storage logic unit */ + for(lun_num = 0U; lun_num < MEM_LUN_NUM; lun_num++) { + usbd_mem_fops->mem_init(lun_num); + } + + /* flush the Rx FIFO */ + usbd_fifo_flush (udev, MSC_OUT_EP); + + /* flush the Tx FIFO */ + usbd_fifo_flush (udev, MSC_IN_EP); + + /* prepare endpoint to receive the first BBB CBW */ + usbd_ep_recev (udev, MSC_OUT_EP, (uint8_t *)&msc->bbb_cbw, BBB_CBW_LENGTH); +} + +/*! + \brief reset the BBB machine + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void msc_bbb_reset (usb_core_driver *udev) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_state = BBB_IDLE; + msc->bbb_status = BBB_STATUS_RECOVERY; + + /* prepare endpoint to receive the first BBB command */ + usbd_ep_recev (udev, MSC_OUT_EP, (uint8_t *)&msc->bbb_cbw, BBB_CBW_LENGTH); +} + +/*! + \brief deinitialize the BBB machine + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void msc_bbb_deinit (usb_core_driver *udev) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_state = BBB_IDLE; +} + +/*! + \brief handle BBB data IN stage + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval none +*/ +void msc_bbb_data_in (usb_core_driver *udev, uint8_t ep_num) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + switch (msc->bbb_state) { + case BBB_DATA_IN: + if (scsi_process_cmd (udev, msc->bbb_cbw.bCBWLUN, &msc->bbb_cbw.CBWCB[0]) < 0) { + msc_bbb_csw_send (udev, CSW_CMD_FAILED); + } + break; + + case BBB_SEND_DATA: + case BBB_LAST_DATA_IN: + msc_bbb_csw_send (udev, CSW_CMD_PASSED); + break; + + default: + break; + } +} + +/*! + \brief handle BBB data OUT stage + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval none +*/ +void msc_bbb_data_out (usb_core_driver *udev, uint8_t ep_num) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + switch (msc->bbb_state) { + case BBB_IDLE: + msc_bbb_cbw_decode (udev); + break; + + case BBB_DATA_OUT: + if (scsi_process_cmd (udev, msc->bbb_cbw.bCBWLUN, &msc->bbb_cbw.CBWCB[0]) < 0) { + msc_bbb_csw_send (udev, CSW_CMD_FAILED); + } + break; + + default: + break; + } +} + +/*! + \brief send the CSW(command status wrapper) + \param[in] udev: pointer to USB device instance + \param[in] csw_status: CSW status + \param[out] none + \retval none +*/ +void msc_bbb_csw_send (usb_core_driver *udev, uint8_t csw_status) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_csw.dCSWSignature = BBB_CSW_SIGNATURE; + msc->bbb_csw.bCSWStatus = csw_status; + msc->bbb_state = BBB_IDLE; + + usbd_ep_send (udev, MSC_IN_EP, (uint8_t *)&msc->bbb_csw, BBB_CSW_LENGTH); + + /* prepare endpoint to receive next command */ + usbd_ep_recev (udev, MSC_OUT_EP, (uint8_t *)&msc->bbb_cbw, BBB_CBW_LENGTH); +} + +/*! + \brief complete the clear feature request + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval none +*/ +void msc_bbb_clrfeature (usb_core_driver *udev, uint8_t ep_num) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + if (msc->bbb_status == BBB_STATUS_ERROR){ /* bad CBW signature */ + usbd_ep_stall(udev, MSC_IN_EP); + + msc->bbb_status = BBB_STATUS_NORMAL; + } else if(((ep_num & 0x80U) == 0x80U) && (msc->bbb_status != BBB_STATUS_RECOVERY)) { + msc_bbb_csw_send (udev, CSW_CMD_FAILED); + } else { + + } +} + +/*! + \brief decode the CBW command and set the BBB state machine accordingly + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +static void msc_bbb_cbw_decode (usb_core_driver *udev) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_csw.dCSWTag = msc->bbb_cbw.dCBWTag; + msc->bbb_csw.dCSWDataResidue = msc->bbb_cbw.dCBWDataTransferLength; + + if((BBB_CBW_LENGTH != usbd_rxcount_get(udev, MSC_OUT_EP)) || + (BBB_CBW_SIGNATURE != msc->bbb_cbw.dCBWSignature) || + (msc->bbb_cbw.bCBWLUN > 1U) || + (msc->bbb_cbw.bCBWCBLength < 1U) || + (msc->bbb_cbw.bCBWCBLength > 16U)) { + /* illegal command handler */ + scsi_sense_code (udev, msc->bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB); + + msc->bbb_status = BBB_STATUS_ERROR; + + msc_bbb_abort (udev); + } else { + if (scsi_process_cmd (udev, msc->bbb_cbw.bCBWLUN, &msc->bbb_cbw.CBWCB[0]) < 0) { + msc_bbb_abort (udev); + } else if ((BBB_DATA_IN != msc->bbb_state) && + (BBB_DATA_OUT != msc->bbb_state) && + (BBB_LAST_DATA_IN != msc->bbb_state)) { /* burst xfer handled internally */ + if (msc->bbb_datalen > 0U) { + msc_bbb_data_send (udev, msc->bbb_data, msc->bbb_datalen); + } else if (0U == msc->bbb_datalen) { + msc_bbb_csw_send (udev, CSW_CMD_PASSED); + } else { + + } + } else { + + } + } +} + +/*! + \brief send the requested data + \param[in] udev: pointer to USB device instance + \param[in] buf: pointer to data buffer + \param[in] len: data length + \param[out] none + \retval none +*/ +static void msc_bbb_data_send (usb_core_driver *udev, uint8_t *buf, uint32_t len) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + len = USB_MIN (msc->bbb_cbw.dCBWDataTransferLength, len); + + msc->bbb_csw.dCSWDataResidue -= len; + msc->bbb_csw.bCSWStatus = CSW_CMD_PASSED; + msc->bbb_state = BBB_SEND_DATA; + + usbd_ep_send (udev, MSC_IN_EP, buf, len); +} + +/*! + \brief abort the current transfer + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +static void msc_bbb_abort (usb_core_driver *udev) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + if ((0U == msc->bbb_cbw.bmCBWFlags) && + (0U != msc->bbb_cbw.dCBWDataTransferLength) && + (BBB_STATUS_NORMAL == msc->bbb_status)) { + usbd_ep_stall(udev, MSC_OUT_EP); + } + + usbd_ep_stall(udev, MSC_IN_EP); + + if (msc->bbb_status == BBB_STATUS_ERROR) { + usbd_ep_recev (udev, MSC_OUT_EP, (uint8_t *)&msc->bbb_cbw, BBB_CBW_LENGTH); + } +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Source/usbd_msc_core.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Source/usbd_msc_core.c new file mode 100644 index 00000000..8bfdf77a --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Source/usbd_msc_core.c @@ -0,0 +1,318 @@ +/*! + \file usbd_msc_core.c + \brief USB MSC device class core functions + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_enum.h" +#include "usbd_msc_bbb.h" +#include "usbd_msc_core.h" +#include + +#define USBD_VID 0x28E9U +#define USBD_PID 0x028FU + +/* local function prototypes ('static') */ +static uint8_t msc_core_init (usb_dev *udev, uint8_t config_index); +static uint8_t msc_core_deinit (usb_dev *udev, uint8_t config_index); +static uint8_t msc_core_req (usb_dev *udev, usb_req *req); +static uint8_t msc_core_in (usb_dev *udev, uint8_t ep_num); +static uint8_t msc_core_out (usb_dev *udev, uint8_t ep_num); + +static __ALIGN_BEGIN uint8_t usbd_msc_maxlun = 0U __ALIGN_END; + +usb_class_core msc_class = +{ + .init = msc_core_init, + .deinit = msc_core_deinit, + + .req_proc = msc_core_req, + + .data_in = msc_core_in, + .data_out = msc_core_out +}; + +/* note: it should use the C99 standard when compiling the below codes */ +/* USB standard device descriptor */ +__ALIGN_BEGIN const usb_desc_dev msc_dev_desc __ALIGN_END = +{ + .header = { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, + .bcdUSB = 0x0200U, + .bDeviceClass = 0x00U, + .bDeviceSubClass = 0x00U, + .bDeviceProtocol = 0x00U, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100U, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM +}; + +/* USB device configuration descriptor */ +__ALIGN_BEGIN const usb_desc_config_set msc_config_desc __ALIGN_END = +{ + .config = + { + .header = { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, + .wTotalLength = USB_MSC_CONFIG_DESC_SIZE, + .bNumInterfaces = 0x01U, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0xC0U, + .bMaxPower = 0x32U + }, + + .msc_itf = + { + .header = { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x02U, + .bInterfaceClass = USB_CLASS_MSC, + .bInterfaceSubClass = USB_MSC_SUBCLASS_SCSI, + .bInterfaceProtocol = USB_MSC_PROTOCOL_BBB, + .iInterface = 0x00U + }, + + .msc_epin = + { + .header = { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = MSC_IN_EP, + .bmAttributes = USB_EP_ATTR_BULK, + .wMaxPacketSize = MSC_EPIN_SIZE, + .bInterval = 0x00U + }, + + .msc_epout = + { + .header = { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = MSC_OUT_EP, + .bmAttributes = USB_EP_ATTR_BULK, + .wMaxPacketSize = MSC_EPOUT_SIZE, + .bInterval = 0x00U + } +}; + +/* USB language ID descriptor */ +static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = +{ + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, + .wLANGID = ENG_LANGID +}; + +/* USB manufacture string */ +static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = +{ + .header = + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} +}; + +/* USB product string */ +static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = +{ + .header = + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'M', 'S', 'C'} +}; + +/* USBD serial string */ +static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = +{ + .header = + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + } +}; + +/* USB string descriptor */ +static void *const usbd_msc_strings[] = +{ + [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *)&manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *)&product_string, + [STR_IDX_SERIAL] = (uint8_t *)&serial_string +}; + +usb_desc msc_desc = { + .dev_desc = (uint8_t *)&msc_dev_desc, + .config_desc = (uint8_t *)&msc_config_desc, + .strings = usbd_msc_strings +}; + +/*! + \brief initialize the MSC device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t msc_core_init (usb_dev *udev, uint8_t config_index) +{ + static __ALIGN_BEGIN usbd_msc_handler msc_handler __ALIGN_END; + + memset((void *)&msc_handler, 0U, sizeof(usbd_msc_handler)); + + udev->dev.class_data[USBD_MSC_INTERFACE] = (void *)&msc_handler; + + /* configure MSC Tx endpoint */ + usbd_ep_setup (udev, &(msc_config_desc.msc_epin)); + + /* configure MSC Rx endpoint */ + usbd_ep_setup (udev, &(msc_config_desc.msc_epout)); + + /* initialize the BBB layer */ + msc_bbb_init(udev); + + return USBD_OK; +} + +/*! + \brief deinitialize the MSC device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t msc_core_deinit (usb_dev *udev, uint8_t config_index) +{ + /* clear MSC endpoints */ + usbd_ep_clear (udev, MSC_IN_EP); + usbd_ep_clear (udev, MSC_OUT_EP); + + /* deinitialize the BBB layer */ + msc_bbb_deinit(udev); + + return USBD_OK; +} + +/*! + \brief handle the MSC class-specific and standard requests + \param[in] udev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t msc_core_req (usb_dev *udev, usb_req *req) +{ + usb_transc *transc = &udev->dev.transc_in[0]; + + switch (req->bRequest) { + case BBB_GET_MAX_LUN : + if((0U == req->wValue) && + (1U == req->wLength) && + (0x80U == (req->bmRequestType & 0x80U))) { + usbd_msc_maxlun = (uint8_t)usbd_mem_fops->mem_maxlun(); + + transc->xfer_buf = &usbd_msc_maxlun; + transc->remain_len = 1U; + } else { + return USBD_FAIL; + } + break; + + case BBB_RESET : + if((0U == req->wValue) && + (0U == req->wLength) && + (0x80U != (req->bmRequestType & 0x80U))) { + msc_bbb_reset(udev); + } else { + return USBD_FAIL; + } + break; + + case USB_CLEAR_FEATURE: + msc_bbb_clrfeature (udev, (uint8_t)req->wIndex); + break; + + default: + return USBD_FAIL; + } + + return USBD_OK; +} + +/*! + \brief handle data in stage + \param[in] udev: pointer to USB device instance + \param[in] ep_num: the endpoint number + \param[out] none + \retval none +*/ +static uint8_t msc_core_in (usb_dev *udev, uint8_t ep_num) +{ + msc_bbb_data_in (udev, ep_num); + + return USBD_OK; +} + +/*! + \brief handle data out stage + \param[in] udev: pointer to USB device instance + \param[in] ep_num: the endpoint number + \param[out] none + \retval none +*/ +static uint8_t msc_core_out (usb_dev *udev, uint8_t ep_num) +{ + msc_bbb_data_out (udev, ep_num); + + return USBD_OK; +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Source/usbd_msc_scsi.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Source/usbd_msc_scsi.c new file mode 100644 index 00000000..66283cad --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/msc/Source/usbd_msc_scsi.c @@ -0,0 +1,761 @@ +/*! + \file usbd_msc_scsi.c + \brief USB SCSI layer functions + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_enum.h" +#include "usbd_msc_bbb.h" +#include "usbd_msc_scsi.h" + +/* USB mass storage page 0 inquiry data */ +const uint8_t msc_page00_inquiry_data[] = +{ + 0x00U, + 0x00U, + 0x00U, + 0x00U, + (INQUIRY_PAGE00_LENGTH - 4U), + 0x80U, + 0x83U, +}; + +/* USB mass storage sense 6 data */ +const uint8_t msc_mode_sense6_data[] = +{ + 0x00U, + 0x00U, + 0x00U, + 0x00U, + 0x00U, + 0x00U, + 0x00U, + 0x00U +}; + +/* USB mass storage sense 10 data */ +const uint8_t msc_mode_sense10_data[] = +{ + 0x00U, + 0x06U, + 0x00U, + 0x00U, + 0x00U, + 0x00U, + 0x00U, + 0x00U +}; + +/* local function prototypes ('static') */ +static int8_t scsi_test_unit_ready (usb_core_driver *udev, uint8_t lun, uint8_t *params); +static int8_t scsi_mode_select6 (usb_core_driver *udev, uint8_t lun, uint8_t *params); +static int8_t scsi_mode_select10 (usb_core_driver *udev, uint8_t lun, uint8_t *params); +static int8_t scsi_inquiry (usb_core_driver *udev, uint8_t lun, uint8_t *params); +static int8_t scsi_read_format_capacity (usb_core_driver *udev, uint8_t lun, uint8_t *params); +static int8_t scsi_read_capacity10 (usb_core_driver *udev, uint8_t lun, uint8_t *params); +static int8_t scsi_request_sense (usb_core_driver *udev, uint8_t lun, uint8_t *params); +static int8_t scsi_mode_sense6 (usb_core_driver *udev, uint8_t lun, uint8_t *params); +static int8_t scsi_toc_cmd_read (usb_core_driver *udev, uint8_t lun, uint8_t *params); +static int8_t scsi_mode_sense10 (usb_core_driver *udev, uint8_t lun, uint8_t *params); +static int8_t scsi_write10 (usb_core_driver *udev, uint8_t lun, uint8_t *params); +static int8_t scsi_read10 (usb_core_driver *udev, uint8_t lun, uint8_t *params); +static int8_t scsi_verify10 (usb_core_driver *udev, uint8_t lun, uint8_t *params); + +static int8_t scsi_process_read (usb_core_driver *udev, uint8_t lun); +static int8_t scsi_process_write (usb_core_driver *udev, uint8_t lun); + +static inline int8_t scsi_check_address_range (usb_core_driver *udev, uint8_t lun, uint32_t blk_offset, uint16_t blk_nbr); +static inline int8_t scsi_format_cmd (usb_core_driver *udev, uint8_t lun); +static inline int8_t scsi_start_stop_unit (usb_core_driver *udev, uint8_t lun, uint8_t *params); +static inline int8_t scsi_allow_medium_removal (usb_core_driver *udev, uint8_t lun, uint8_t *params); + +/*! + \brief process SCSI commands + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +int8_t scsi_process_cmd(usb_core_driver *udev, uint8_t lun, uint8_t *params) +{ + switch (params[0]) { + case SCSI_TEST_UNIT_READY: + return scsi_test_unit_ready (udev, lun, params); + + case SCSI_REQUEST_SENSE: + return scsi_request_sense (udev, lun, params); + + case SCSI_INQUIRY: + return scsi_inquiry (udev, lun, params); + + case SCSI_START_STOP_UNIT: + return scsi_start_stop_unit (udev, lun, params); + + case SCSI_ALLOW_MEDIUM_REMOVAL: + return scsi_allow_medium_removal (udev, lun, params); + + case SCSI_MODE_SENSE6: + return scsi_mode_sense6 (udev, lun, params); + + case SCSI_MODE_SENSE10: + return scsi_mode_sense10 (udev, lun, params); + + case SCSI_READ_FORMAT_CAPACITIES: + return scsi_read_format_capacity (udev, lun, params); + + case SCSI_READ_CAPACITY10: + return scsi_read_capacity10 (udev, lun, params); + + case SCSI_READ10: + return scsi_read10 (udev, lun, params); + + case SCSI_WRITE10: + return scsi_write10 (udev, lun, params); + + case SCSI_VERIFY10: + return scsi_verify10 (udev, lun, params); + + case SCSI_FORMAT_UNIT: + return scsi_format_cmd (udev, lun); + + case SCSI_READ_TOC_DATA: + return scsi_toc_cmd_read (udev, lun, params); + + case SCSI_MODE_SELECT6: + return scsi_mode_select6 (udev, lun, params); + + case SCSI_MODE_SELECT10: + return scsi_mode_select10 (udev, lun, params); + + default: + scsi_sense_code (udev, lun, ILLEGAL_REQUEST, INVALID_CDB); + return -1; + } +} + +/*! + \brief load the last error code in the error list + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] skey: sense key + \param[in] asc: additional sense key + \param[out] none + \retval none +*/ +void scsi_sense_code (usb_core_driver *udev, uint8_t lun, uint8_t skey, uint8_t asc) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->scsi_sense[msc->scsi_sense_tail].SenseKey = skey; + msc->scsi_sense[msc->scsi_sense_tail].ASC = asc; + msc->scsi_sense_tail++; + + if (SENSE_LIST_DEEPTH == msc->scsi_sense_tail) { + msc->scsi_sense_tail = 0U; + } +} + +/*! + \brief process SCSI Test Unit Ready command + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_test_unit_ready (usb_core_driver *udev, uint8_t lun, uint8_t *params) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + /* case 9 : Hi > D0 */ + if (0U != msc->bbb_cbw.dCBWDataTransferLength) { + scsi_sense_code (udev, msc->bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB); + + return -1; + } + + if (0 != usbd_mem_fops->mem_ready(lun)) { + scsi_sense_code(udev, lun, NOT_READY, MEDIUM_NOT_PRESENT); + + return -1; + } + + msc->bbb_datalen = 0U; + + return 0; +} + +/*! + \brief process Inquiry command + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_mode_select6 (usb_core_driver *udev, uint8_t lun, uint8_t *params) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_datalen = 0U; + + return 0; +} + +/*! + \brief process Inquiry command + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_mode_select10 (usb_core_driver *udev, uint8_t lun, uint8_t *params) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_datalen = 0U; + + return 0; +} + +/*! + \brief process Inquiry command + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_inquiry (usb_core_driver *udev, uint8_t lun, uint8_t *params) +{ + uint8_t *page = NULL; + uint16_t len = 0U; + + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + if (params[1] & 0x01U) { + page = (uint8_t *)msc_page00_inquiry_data; + + len = INQUIRY_PAGE00_LENGTH; + } else { + page = (uint8_t *)usbd_mem_fops->mem_inquiry_data[lun]; + + len = (uint16_t)(page[4] + 5U); + + if (params[4] <= len) { + len = params[4]; + } + } + + msc->bbb_datalen = len; + + while (len) { + len--; + msc->bbb_data[len] = page[len]; + } + + return 0; +} + +/*! + \brief process Read Capacity 10 command + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_read_capacity10 (usb_core_driver *udev, uint8_t lun, uint8_t *params) +{ + uint32_t blk_num = usbd_mem_fops->mem_block_len[lun] - 1U; + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->scsi_blk_nbr[lun] = usbd_mem_fops->mem_block_len[lun]; + msc->scsi_blk_size[lun] = usbd_mem_fops->mem_block_size[lun]; + + msc->bbb_data[0] = (uint8_t)(blk_num >> 24U); + msc->bbb_data[1] = (uint8_t)(blk_num >> 16U); + msc->bbb_data[2] = (uint8_t)(blk_num >> 8U); + msc->bbb_data[3] = (uint8_t)(blk_num); + + msc->bbb_data[4] = (uint8_t)(msc->scsi_blk_size[lun] >> 24U); + msc->bbb_data[5] = (uint8_t)(msc->scsi_blk_size[lun] >> 16U); + msc->bbb_data[6] = (uint8_t)(msc->scsi_blk_size[lun] >> 8U); + msc->bbb_data[7] = (uint8_t)(msc->scsi_blk_size[lun]); + + msc->bbb_datalen = 8U; + + return 0; +} + +/*! + \brief process Read Format Capacity command + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_read_format_capacity (usb_core_driver *udev, uint8_t lun, uint8_t *params) +{ + uint16_t i = 0U; + uint32_t blk_size = usbd_mem_fops->mem_block_size[lun]; + uint32_t blk_num = usbd_mem_fops->mem_block_len[lun]; + uint32_t blk_nbr = blk_num - 1U; + + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + for (i = 0U; i < 12U; i++) { + msc->bbb_data[i] = 0U; + } + + msc->bbb_data[3] = 0x08U; + msc->bbb_data[4] = (uint8_t)(blk_nbr >> 24U); + msc->bbb_data[5] = (uint8_t)(blk_nbr >> 16U); + msc->bbb_data[6] = (uint8_t)(blk_nbr >> 8U); + msc->bbb_data[7] = (uint8_t)(blk_nbr); + + msc->bbb_data[8] = 0x02U; + msc->bbb_data[9] = (uint8_t)(blk_size >> 16U); + msc->bbb_data[10] = (uint8_t)(blk_size >> 8U); + msc->bbb_data[11] = (uint8_t)(blk_size); + + msc->bbb_datalen = 12U; + + return 0; +} + +/*! + \brief process Mode Sense6 command + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_mode_sense6 (usb_core_driver *udev, uint8_t lun, uint8_t *params) +{ + uint16_t len = 8U; + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_datalen = len; + + while (len) { + len--; + msc->bbb_data[len] = msc_mode_sense6_data[len]; + } + + return 0; +} + +/*! + \brief process Mode Sense10 command + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_mode_sense10 (usb_core_driver *udev, uint8_t lun, uint8_t *params) +{ + uint16_t len = 8U; + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_datalen = len; + + while (len) { + len--; + msc->bbb_data[len] = msc_mode_sense10_data[len]; + } + + return 0; +} + +/*! + \brief process Request Sense command + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_request_sense (usb_core_driver *udev, uint8_t lun, uint8_t *params) +{ + uint8_t i = 0U; + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + for (i = 0U; i < REQUEST_SENSE_DATA_LEN; i++) { + msc->bbb_data[i] = 0U; + } + + msc->bbb_data[0] = 0x70U; + msc->bbb_data[7] = REQUEST_SENSE_DATA_LEN - 6U; + + if ((msc->scsi_sense_head != msc->scsi_sense_tail)) { + msc->bbb_data[2] = msc->scsi_sense[msc->scsi_sense_head].SenseKey; + msc->bbb_data[12] = msc->scsi_sense[msc->scsi_sense_head].ASC; + msc->bbb_data[13] = msc->scsi_sense[msc->scsi_sense_head].ASCQ; + msc->scsi_sense_head++; + + if (msc->scsi_sense_head == SENSE_LIST_DEEPTH) { + msc->scsi_sense_head = 0U; + } + } + + msc->bbb_datalen = USB_MIN(REQUEST_SENSE_DATA_LEN, params[4]); + + return 0; +} + +/*! + \brief process Start Stop Unit command + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static inline int8_t scsi_start_stop_unit (usb_core_driver *udev, uint8_t lun, uint8_t *params) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_datalen = 0U; + msc->scsi_disk_pop = 1U; + + return 0; +} + +/*! + \brief process Allow Medium Removal command + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static inline int8_t scsi_allow_medium_removal (usb_core_driver *udev, uint8_t lun, uint8_t *params) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_datalen = 0U; + + return 0; +} + +/*! + \brief process Read10 command + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_read10 (usb_core_driver *udev, uint8_t lun, uint8_t *params) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + if (msc->bbb_state == BBB_IDLE) { + /* direction is from device to host */ + if (0x80U != (msc->bbb_cbw.bmCBWFlags & 0x80U)) { + scsi_sense_code (udev, msc->bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB); + + return -1; + } + + if (0 != usbd_mem_fops->mem_ready(lun)) { + scsi_sense_code (udev, lun, NOT_READY, MEDIUM_NOT_PRESENT); + + return -1; + } + + msc->scsi_blk_addr = (params[2] << 24U) | (params[3] << 16U) | \ + (params[4] << 8U) | params[5]; + + msc->scsi_blk_len = (params[7] << 8U) | params[8]; + + if (scsi_check_address_range (udev, lun, msc->scsi_blk_addr, (uint16_t)msc->scsi_blk_len) < 0) { + return -1; /* error */ + } + + msc->bbb_state = BBB_DATA_IN; + + msc->scsi_blk_addr *= msc->scsi_blk_size[lun]; + msc->scsi_blk_len *= msc->scsi_blk_size[lun]; + + /* cases 4,5 : Hi <> Dn */ + if (msc->bbb_cbw.dCBWDataTransferLength != msc->scsi_blk_len) { + scsi_sense_code (udev, msc->bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB); + + return -1; + } + } + + msc->bbb_datalen = MSC_MEDIA_PACKET_SIZE; + + return scsi_process_read (udev, lun); +} + +/*! + \brief process Write10 command + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_write10 (usb_core_driver *udev, uint8_t lun, uint8_t *params) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + if (BBB_IDLE == msc->bbb_state) { + /* case 8 : Hi <> Do */ + if (0x80U == (msc->bbb_cbw.bmCBWFlags & 0x80U)) { + scsi_sense_code (udev, msc->bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB); + + return -1; + } + + /* check whether media is ready */ + if (0 != usbd_mem_fops->mem_ready(lun)) { + scsi_sense_code (udev, lun, NOT_READY, MEDIUM_NOT_PRESENT); + + return -1; + } + + /* check if media is write-protected */ + if (0 != usbd_mem_fops->mem_protected(lun)) { + scsi_sense_code (udev, lun, NOT_READY, WRITE_PROTECTED); + + return -1; + } + + msc->scsi_blk_addr = (params[2] << 24U) | (params[3] << 16U) | \ + (params[4] << 8U) | params[5]; + + msc->scsi_blk_len = (params[7] << 8U) | params[8]; + + /* check if LBA address is in the right range */ + if (scsi_check_address_range (udev, lun, msc->scsi_blk_addr, (uint16_t)msc->scsi_blk_len) < 0) { + return -1; /* error */ + } + + msc->scsi_blk_addr *= msc->scsi_blk_size[lun]; + msc->scsi_blk_len *= msc->scsi_blk_size[lun]; + + /* cases 3,11,13 : Hn,Ho <> D0 */ + if (msc->bbb_cbw.dCBWDataTransferLength != msc->scsi_blk_len) { + scsi_sense_code (udev, msc->bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB); + + return -1; + } + + /* prepare endpoint to receive first data packet */ + msc->bbb_state = BBB_DATA_OUT; + + usbd_ep_recev (udev, + MSC_OUT_EP, + msc->bbb_data, + USB_MIN (msc->scsi_blk_len, MSC_MEDIA_PACKET_SIZE)); + } else { /* write process ongoing */ + return scsi_process_write (udev, lun); + } + + return 0; +} + +/*! + \brief process Verify10 command + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_verify10 (usb_core_driver *udev, uint8_t lun, uint8_t *params) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + if (0x02U == (params[1] & 0x02U)) { + scsi_sense_code (udev, lun, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND); + + return -1; /* error, verify mode not supported*/ + } + + if (scsi_check_address_range (udev, lun, msc->scsi_blk_addr, (uint16_t)msc->scsi_blk_len) < 0) { + return -1; /* error */ + } + + msc->bbb_datalen = 0U; + + return 0; +} + +/*! + \brief check address range + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] blk_offset: block offset + \param[in] blk_nbr: number of block to be processed + \param[out] none + \retval status +*/ +static inline int8_t scsi_check_address_range (usb_core_driver *udev, uint8_t lun, uint32_t blk_offset, uint16_t blk_nbr) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + if ((blk_offset + blk_nbr) > msc->scsi_blk_nbr[lun]) { + scsi_sense_code (udev, lun, ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE); + + return -1; + } + + return 0; +} + +/*! + \brief handle read process + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[out] none + \retval status +*/ +static int8_t scsi_process_read (usb_core_driver *udev, uint8_t lun) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + uint32_t len = USB_MIN(msc->scsi_blk_len, MSC_MEDIA_PACKET_SIZE); + + if (usbd_mem_fops->mem_read(lun, + msc->bbb_data, + msc->scsi_blk_addr, + (uint16_t)(len / msc->scsi_blk_size[lun])) < 0) { + scsi_sense_code(udev, lun, HARDWARE_ERROR, UNRECOVERED_READ_ERROR); + + return -1; + } + + usbd_ep_send (udev, MSC_IN_EP, msc->bbb_data, len); + + msc->scsi_blk_addr += len; + msc->scsi_blk_len -= len; + + /* case 6 : Hi = Di */ + msc->bbb_csw.dCSWDataResidue -= len; + + if (0U == msc->scsi_blk_len) { + msc->bbb_state = BBB_LAST_DATA_IN; + } + + return 0; +} + +/*! + \brief handle write process + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[out] none + \retval status +*/ +static int8_t scsi_process_write (usb_core_driver *udev, uint8_t lun) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + uint32_t len = USB_MIN(msc->scsi_blk_len, MSC_MEDIA_PACKET_SIZE); + + if (usbd_mem_fops->mem_write (lun, + msc->bbb_data, + msc->scsi_blk_addr, + (uint16_t)(len / msc->scsi_blk_size[lun])) < 0) { + scsi_sense_code(udev, lun, HARDWARE_ERROR, WRITE_FAULT); + + return -1; + } + + msc->scsi_blk_addr += len; + msc->scsi_blk_len -= len; + + /* case 12 : Ho = Do */ + msc->bbb_csw.dCSWDataResidue -= len; + + if (0U == msc->scsi_blk_len) { + msc_bbb_csw_send (udev, CSW_CMD_PASSED); + } else { + /* prepare endpoint to receive next packet */ + usbd_ep_recev (udev, + MSC_OUT_EP, + msc->bbb_data, + USB_MIN (msc->scsi_blk_len, MSC_MEDIA_PACKET_SIZE)); + } + + return 0; +} + +/*! + \brief process Format Unit command + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[out] none + \retval status +*/ +static inline int8_t scsi_format_cmd (usb_core_driver *udev, uint8_t lun) +{ + return 0; +} + +/*! + \brief process Read_Toc command + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_toc_cmd_read (usb_core_driver *udev, uint8_t lun, uint8_t *params) +{ + uint8_t* pPage; + uint16_t len; + + usbd_msc_handler *msc = (usbd_msc_handler *)udev->dev.class_data[USBD_MSC_INTERFACE]; + + pPage = (uint8_t *)&usbd_mem_fops->mem_toc_data[lun * READ_TOC_CMD_LEN]; + len = (uint16_t)pPage[1] + 2U; + + msc->bbb_datalen = len; + + while (len) { + len--; + msc->bbb_data[len] = pPage[len]; + } + + return 0; +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/printer/Include/printer_core.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/printer/Include/printer_core.h new file mode 100644 index 00000000..bb1f66f9 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/printer/Include/printer_core.h @@ -0,0 +1,78 @@ +/*! + \file printer_core.h + \brief the header file of USB printer device class core functions + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __PRINTER_CORE_H +#define __PRINTER_CORE_H + +#include "usbd_enum.h" +#include "usb_ch9_std.h" + +/* USB printing device class code */ +#define USB_CLASS_PRINTER 0x07U + +/* printing device subclass code */ +#define USB_SUBCLASS_PRINTER 0x01U + +/* printing device protocol code */ +#define PROTOCOL_UNIDIRECTIONAL_ITF 0x01U +#define PROTOCOL_BI_DIRECTIONAL_ITF 0x02U +#define PROTOCOL_1284_4_ITF 0x03U +#define PROTOCOL_VENDOR 0xFFU + +#define DEVICE_ID_LEN 103U + +#define USB_PRINTER_CONFIG_DESC_LEN 32U + +/* printing device specific-class request */ +#define GET_DEVICE_ID 0x00U +#define GET_PORT_STATUS 0x01U +#define SOFT_RESET 0x02U + +#pragma pack(1) + +/* USB configuration descriptor structure */ +typedef struct +{ + usb_desc_config config; + usb_desc_itf printer_itf; + usb_desc_ep printer_epin; + usb_desc_ep printer_epout; +} usb_printer_desc_config_set; + +#pragma pack() + +extern usb_desc printer_desc; +extern usb_class_core usbd_printer_cb; + +#endif /* __PRINTER_CORE_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/printer/Source/printer_core.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/printer/Source/printer_core.c new file mode 100644 index 00000000..6bccaf4c --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/class/printer/Source/printer_core.c @@ -0,0 +1,310 @@ +/*! + \file printer_core.c + \brief USB printer device class core functions + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "printer_core.h" + +#define USBD_VID 0x28E9U +#define USBD_PID 0x0003U + +/* printer port status: paper not empty/selected/no error */ +static uint8_t g_port_status = 0x18U; + +uint8_t g_printer_data_buf[PRINTER_OUT_PACKET]; + +uint8_t PRINTER_DEVICE_ID[DEVICE_ID_LEN] = +{ + 0x00, 0x67, + 'M', 'A', 'N', 'U', 'F', 'A', 'C', 'T', 'U', 'R', 'E', 'R', ':', + 'G', 'I', 'G', 'A', ' ', 'D', 'E', 'V', 'I', 'C', 'E', '-', ';', + 'C', 'O', 'M', 'M', 'A', 'N', 'D', ' ', 'S', 'E', 'T', ':', + 'P', 'C', 'L', ',', 'M', 'P', 'L', ';', + 'M', 'O', 'D', 'E', 'L', ':', + 'L', 'a', 's', 'e', 'r', 'B', 'e', 'a', 'm', '?', ';', + 'C', 'O', 'M', 'M', 'E', 'N', 'T', ':', + 'G', 'o', 'o', 'd', ' ', '!', ';', + 'A', 'C', 'T', 'I', 'V', 'E', ' ', 'C', 'O', 'M', 'M', 'A', 'N', 'D', ' ', 'S', 'E', 'T', ':', + 'P', 'C', 'L', ';' +}; + +/* USB standard device descriptor */ +const usb_desc_dev printer_dev_desc = +{ + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV, + }, + .bcdUSB = 0x0200U, + .bDeviceClass = 0x00U, + .bDeviceSubClass = 0x00U, + .bDeviceProtocol = 0x00U, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100U, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM, +}; + +/* USB device configuration descriptor */ +const usb_printer_desc_config_set printer_config_desc = +{ + .config = + { + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, + .wTotalLength = USB_PRINTER_CONFIG_DESC_LEN, + .bNumInterfaces = 0x01U, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0xA0U, + .bMaxPower = 0x32U + }, + + .printer_itf = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x02U, + .bInterfaceClass = USB_CLASS_PRINTER, + .bInterfaceSubClass = USB_SUBCLASS_PRINTER, + .bInterfaceProtocol = PROTOCOL_BI_DIRECTIONAL_ITF, + .iInterface = 0x00U + }, + + .printer_epin = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = PRINTER_IN_EP, + .bmAttributes = USB_EP_ATTR_BULK, + .wMaxPacketSize = PRINTER_IN_PACKET, + .bInterval = 0x00U + }, + + .printer_epout = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = PRINTER_OUT_EP, + .bmAttributes = USB_EP_ATTR_BULK, + .wMaxPacketSize = PRINTER_OUT_PACKET, + .bInterval = 0x00U + }, +}; + +/* USB language ID Descriptor */ +static const usb_desc_LANGID usbd_language_id_desc = +{ + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .wLANGID = ENG_LANGID +}; + +/* USB manufacture string */ +static const usb_desc_str manufacturer_string = +{ + .header = + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} +}; + +/* USB product string */ +static const usb_desc_str product_string = +{ + .header = + { + .bLength = USB_STRING_LEN(16U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'P', 'r', 'i', 'n', 't', 'e', 'r'} +}; + +/* USBD serial string */ +static usb_desc_str serial_string = +{ + .header = + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + } +}; + +/* USB string descriptor */ +static void *const usbd_msc_strings[] = +{ + [STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *)&manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *)&product_string, + [STR_IDX_SERIAL] = (uint8_t *)&serial_string +}; + +usb_desc printer_desc = { + .dev_desc = (uint8_t *)&printer_dev_desc, + .config_desc = (uint8_t *)&printer_config_desc, + .strings = usbd_msc_strings +}; + +/* local function prototypes ('static') */ +static uint8_t printer_init (usb_dev *udev, uint8_t config_index); +static uint8_t printer_deinit (usb_dev *udev, uint8_t config_index); +static uint8_t printer_req (usb_dev *udev, usb_req *req); +static uint8_t printer_in (usb_dev *udev, uint8_t ep_num); +static uint8_t printer_out (usb_dev *udev, uint8_t ep_num); + +usb_class_core usbd_printer_cb = { + .init = printer_init, + .deinit = printer_deinit, + + .req_proc = printer_req, + + .data_in = printer_in, + .data_out = printer_out +}; + +/*! + \brief initialize the printer device + \param[in] udev: pointer to usb device instance + \param[in] config_index: configuration index + \param[out] none + \retval usb device operation status +*/ +static uint8_t printer_init (usb_dev *udev, uint8_t config_index) +{ + /* initialize the data Tx endpoint */ + usbd_ep_setup (udev, &(printer_config_desc.printer_epin)); + + /* initialize the data Rx endpoint */ + usbd_ep_setup (udev, &(printer_config_desc.printer_epout)); + + /* prepare to receive data */ + usbd_ep_recev(udev, PRINTER_OUT_EP, g_printer_data_buf, PRINTER_OUT_PACKET); + + return USBD_OK; +} + +/*! + \brief deinitialize the printer device + \param[in] udev: pointer to usb device instance + \param[in] config_index: configuration index + \param[out] none + \retval usb device operation status +*/ +static uint8_t printer_deinit (usb_dev *udev, uint8_t config_index) +{ + /* deinitialize the data Tx/Rx endpoint */ + usbd_ep_clear (udev, PRINTER_IN_EP); + usbd_ep_clear (udev, PRINTER_OUT_EP); + + return USBD_OK; +} + +/*! + \brief handle the printer class-specific requests + \param[in] udev: pointer to usb device instance + \param[in] req: device class-specific request + \param[out] none + \retval usb device operation status +*/ +static uint8_t printer_req(usb_dev *udev, usb_req *req) +{ + usb_transc *transc = &udev->dev.transc_in[0]; + + switch (req->bRequest) { + case GET_DEVICE_ID: + transc->xfer_buf = (uint8_t *)PRINTER_DEVICE_ID; + transc->remain_len = DEVICE_ID_LEN; + break; + + case GET_PORT_STATUS: + transc->xfer_buf = (uint8_t *)&g_port_status; + transc->remain_len = 1U; + break; + + case SOFT_RESET: + usbd_ep_recev(udev, PRINTER_OUT_EP, g_printer_data_buf, PRINTER_OUT_PACKET); + break; + + default: + return USBD_FAIL; + } + + return USBD_OK; +} + +/*! + \brief handle printer data + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval USB device operation status +*/ +static uint8_t printer_in (usb_dev *udev, uint8_t ep_num) +{ + return USBD_OK; +} + +/*! + \brief handle printer data + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval USB device operation status +*/ +static uint8_t printer_out (usb_dev *udev, uint8_t ep_num) +{ + return USBD_OK; +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/core/Include/usbd_core.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/core/Include/usbd_core.h new file mode 100644 index 00000000..2ee25bd2 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/core/Include/usbd_core.h @@ -0,0 +1,103 @@ +/*! + \file usbd_core.h + \brief USB device mode core functions prototype + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_CORE_H +#define __USBD_CORE_H + +#include "drv_usb_core.h" +#include "drv_usb_dev.h" + +typedef enum +{ + USBD_OK = 0U, /*!< status OK */ + USBD_BUSY, /*!< status busy */ + USBD_FAIL /*!< status fail */ +} usbd_status; + +enum _usbd_status { + USBD_DEFAULT = 1U, /*!< default status */ + USBD_ADDRESSED = 2U, /*!< address send status */ + USBD_CONFIGURED = 3U, /*!< configured status */ + USBD_SUSPENDED = 4U /*!< suspended status */ +}; + +/* static inline function definitions */ + +/*! + \brief set USB device address + \param[in] udev: pointer to USB core instance + \param[in] addr: device address to set + \param[out] none + \retval none +*/ +__STATIC_INLINE void usbd_addr_set (usb_core_driver *udev, uint8_t addr) +{ + usb_devaddr_set(udev, addr); +} + +/*! + \brief get the received data length + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval USB device operation cur_status +*/ +__STATIC_INLINE uint16_t usbd_rxcount_get (usb_core_driver *udev, uint8_t ep_num) +{ + return (uint16_t)udev->dev.transc_out[ep_num].xfer_count; +} + +/* function declarations */ +/* initializes the USB device-mode stack and load the class driver */ +void usbd_init (usb_core_driver *udev, usb_core_enum core, usb_desc *desc, usb_class_core *class_core); +/* endpoint initialization */ +uint32_t usbd_ep_setup (usb_core_driver *udev, const usb_desc_ep *ep_desc); +/* configure the endpoint when it is disabled */ +uint32_t usbd_ep_clear (usb_core_driver *udev, uint8_t ep_addr); +/* endpoint prepare to receive data */ +uint32_t usbd_ep_recev (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint32_t len); +/* endpoint prepare to transmit data */ +uint32_t usbd_ep_send (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint32_t len); +/* set an endpoint to STALL status */ +uint32_t usbd_ep_stall (usb_core_driver *udev, uint8_t ep_addr); +/* clear endpoint STALLed status */ +uint32_t usbd_ep_stall_clear (usb_core_driver *udev, uint8_t ep_addr); +/* flush the endpoint FIFOs */ +uint32_t usbd_fifo_flush (usb_core_driver *udev, uint8_t ep_addr); +/* device connect */ +void usbd_connect (usb_core_driver *udev); +/* device disconnect */ +void usbd_disconnect (usb_core_driver *udev); + +#endif /* __USBD_CORE_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/core/Include/usbd_enum.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/core/Include/usbd_enum.h new file mode 100644 index 00000000..baccdef1 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/core/Include/usbd_enum.h @@ -0,0 +1,106 @@ +/*! + \file usbd_enum.h + \brief USB enumeration definitions + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_ENUM_H +#define __USBD_ENUM_H + +#include "usbd_core.h" +#include "usbd_conf.h" +#include + +#ifndef NULL + #define NULL 0U +#endif + +typedef enum _usb_reqsta +{ + REQ_SUPP = 0x0U, /* request support */ + REQ_NOTSUPP = 0x1U, /* request not support */ +} usb_reqsta; + +/* string descriptor index */ +enum _str_index +{ + STR_IDX_LANGID = 0x00U, /* language ID string index */ + STR_IDX_MFC = 0x01U, /* manufacturer string index */ + STR_IDX_PRODUCT = 0x02U, /* product string index */ + STR_IDX_SERIAL = 0x03U, /* serial string index */ + STR_IDX_CONFIG = 0x04U, /* configuration string index */ + STR_IDX_ITF = 0x05U, /* interface string index */ +#ifndef WINUSB_EXEMPT_DRIVER + STR_IDX_MAX = 0x0AU, /* string maximum index */ +#else + STR_IDX_MAX = 0xEFU, /* string maximum index */ +#endif /* WINUSB_EXEMPT_DRIVER */ +}; + +typedef enum _usb_pwrsta { + USB_PWRSTA_SELF_POWERED = 0x1U, /* USB is in self powered status */ + USB_PWRSTA_REMOTE_WAKEUP = 0x2U, /* USB is in remote wakeup status */ +} usb_pwrsta; + +typedef enum _usb_feature +{ + USB_FEATURE_EP_HALT = 0x0U, /* USB has endpoint halt feature */ + USB_FEATURE_REMOTE_WAKEUP = 0x1U, /* USB has endpoint remote wakeup feature */ + USB_FEATURE_TEST_MODE = 0x2U, /* USB has endpoint test mode feature */ +} usb_feature; + +#define ENG_LANGID 0x0409U /* english language ID */ +#define CHN_LANGID 0x0804U /* chinese language ID */ + +/* USB device exported macros */ +#define CTL_EP(ep) (((ep) == 0x00U) || ((ep) == 0x80U)) + +#define DEVICE_ID1 (0x1FFFF7E8U) /* device ID1 */ +#define DEVICE_ID2 (0x1FFFF7ECU) /* device ID2 */ +#define DEVICE_ID3 (0x1FFFF7F0U) /* device ID3 */ + +#define DEVICE_ID (0x40022100U) + +/* function declarations */ +/* handle USB standard device request */ +usb_reqsta usbd_standard_request (usb_core_driver *udev, usb_req *req); +/* handle USB device class request */ +usb_reqsta usbd_class_request (usb_core_driver *udev, usb_req *req); +/* handle USB vendor request */ +usb_reqsta usbd_vendor_request (usb_core_driver *udev, usb_req *req); +/* handle USB enumeration error */ +void usbd_enum_error (usb_core_driver *udev, usb_req *req); +/* convert hex 32bits value into unicode char */ +void int_to_unicode (uint32_t value, uint8_t *pbuf, uint8_t len); +/* get serial string */ +void serial_string_get (uint16_t *unicode_str); + +#endif /* __USBD_ENUM_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/core/Include/usbd_transc.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/core/Include/usbd_transc.h new file mode 100644 index 00000000..0271f9f1 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/core/Include/usbd_transc.h @@ -0,0 +1,56 @@ +/*! + \file usbd_transc.h + \brief USB transaction core functions prototype + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_TRANSC_H +#define __USBD_TRANSC_H + +#include "usbd_core.h" + +/* function declarations */ +/* USB send data in the control transaction */ +usbd_status usbd_ctl_send (usb_core_driver *udev); +/* USB receive data in control transaction */ +usbd_status usbd_ctl_recev (usb_core_driver *udev); +/* USB send control transaction status */ +usbd_status usbd_ctl_status_send (usb_core_driver *udev); +/* USB control receive status */ +usbd_status usbd_ctl_status_recev (usb_core_driver *udev); +/* USB setup stage processing */ +uint8_t usbd_setup_transc (usb_core_driver *udev); +/* data out stage processing */ +uint8_t usbd_out_transc (usb_core_driver *udev, uint8_t ep_num); +/* data in stage processing */ +uint8_t usbd_in_transc (usb_core_driver *udev, uint8_t ep_num); + +#endif /* __USBD_TRANSC_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/core/Source/usbd_core.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/core/Source/usbd_core.c new file mode 100644 index 00000000..0c11e42a --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/core/Source/usbd_core.c @@ -0,0 +1,312 @@ +/*! + \file usbd_core.c + \brief USB device mode core functions + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_core.h" +#include "usbd_enum.h" +#include "drv_usb_hw.h" + +/* endpoint type */ +const uint32_t ep_type[] = { + [USB_EP_ATTR_CTL] = (uint32_t)USB_EPTYPE_CTRL, + [USB_EP_ATTR_BULK] = (uint32_t)USB_EPTYPE_BULK, + [USB_EP_ATTR_INT] = (uint32_t)USB_EPTYPE_INTR, + [USB_EP_ATTR_ISO] = (uint32_t)USB_EPTYPE_ISOC +}; + +/*! + \brief initializes the USB device-mode stack and load the class driver + \param[in] udev: pointer to USB core instance + \param[in] core: USB core type + \param[in] desc: pointer to USB descriptor + \param[in] class_core: class driver + \param[out] none + \retval none +*/ +void usbd_init (usb_core_driver *udev, usb_core_enum core, usb_desc *desc, usb_class_core *class_core) +{ + udev->dev.desc = desc; + + /* class callbacks */ + udev->dev.class_core = class_core; + + /* create serial string */ + serial_string_get(udev->dev.desc->strings[STR_IDX_SERIAL]); + + /* configure USB capabilities */ + (void)usb_basic_init (&udev->bp, &udev->regs, core); + + usb_globalint_disable(&udev->regs); + + /* initializes the USB core*/ + (void)usb_core_init (udev->bp, &udev->regs); + + /* set device disconnect */ + usbd_disconnect (udev); + +#ifndef USE_OTG_MODE + usb_curmode_set(&udev->regs, DEVICE_MODE); +#endif /* USE_OTG_MODE */ + + /* initializes device mode */ + (void)usb_devcore_init (udev); + + usb_globalint_enable(&udev->regs); + + /* set device connect */ + usbd_connect (udev); + + udev->dev.cur_status = (uint8_t)USBD_DEFAULT; +} + +/*! + \brief endpoint initialization + \param[in] udev: pointer to USB core instance + \param[in] ep_desc: pointer to endpoint descriptor + \param[out] none + \retval none +*/ +uint32_t usbd_ep_setup (usb_core_driver *udev, const usb_desc_ep *ep_desc) +{ + usb_transc *transc; + + uint8_t ep_addr = ep_desc->bEndpointAddress; + uint16_t max_len = ep_desc->wMaxPacketSize; + + /* set endpoint direction */ + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + + transc->ep_addr.dir = 1U; + } else { + transc = &udev->dev.transc_out[ep_addr]; + + transc->ep_addr.dir = 0U; + } + + transc->ep_addr.num = EP_ID(ep_addr); + transc->max_len = max_len; + transc->ep_type = (uint8_t)ep_type[ep_desc->bmAttributes & (uint8_t)USB_EPTYPE_MASK]; + + /* active USB endpoint function */ + (void)usb_transc_active (udev, transc); + + return 0U; +} + +/*! + \brief configure the endpoint when it is disabled + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_clear (usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc; + + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + /* deactivate USB endpoint function */ + (void)usb_transc_deactivate (udev, transc); + + return 0U; +} + +/*! + \brief endpoint prepare to receive data + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[in] pbuf: user buffer address pointer + \param[in] len: buffer length + \param[out] none + \retval none +*/ +uint32_t usbd_ep_recev (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint32_t len) +{ + usb_transc *transc = &udev->dev.transc_out[EP_ID(ep_addr)]; + + /* setup the transfer */ + transc->xfer_buf = pbuf; + transc->xfer_len = len; + transc->xfer_count = 0U; + + /* start the transfer */ + (void)usb_transc_outxfer (udev, transc); + + return 0U; +} + +/*! + \brief endpoint prepare to transmit data + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[in] pbuf: transmit buffer address pointer + \param[in] len: buffer length + \param[out] none + \retval none +*/ +uint32_t usbd_ep_send (usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint32_t len) +{ + usb_transc *transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + + /* setup the transfer */ + transc->xfer_buf = pbuf; + transc->xfer_len = len; + transc->xfer_count = 0U; + + /* start the transfer */ + (void)usb_transc_inxfer (udev, transc); + + return 0U; +} + +/*! + \brief set an endpoint to STALL status + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_stall (usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc = NULL; + + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + transc->ep_stall = 1U; + + (void)usb_transc_stall (udev, transc); + + return (0U); +} + +/*! + \brief clear endpoint STALLed status + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_stall_clear (usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc = NULL; + + if (EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + transc->ep_stall = 0U; + + (void)usb_transc_clrstall (udev, transc); + + return (0U); +} + +/*! + \brief flush the endpoint FIFOs + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_fifo_flush (usb_core_driver *udev, uint8_t ep_addr) +{ + if (EP_DIR(ep_addr)) { + (void)usb_txfifo_flush (&udev->regs, EP_ID(ep_addr)); + } else { + (void)usb_rxfifo_flush (&udev->regs); + } + + return (0U); +} + +/*! + \brief device connect + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void usbd_connect (usb_core_driver *udev) +{ +#ifndef USE_OTG_MODE + /* connect device */ + usb_dev_connect (udev); + + usb_mdelay(3U); +#endif /* USE_OTG_MODE */ +} + +/*! + \brief device disconnect + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void usbd_disconnect (usb_core_driver *udev) +{ +#ifndef USE_OTG_MODE + /* disconnect device for 3ms */ + usb_dev_disconnect (udev); + + usb_mdelay(3U); +#endif /* USE_OTG_MODE */ +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/core/Source/usbd_enum.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/core/Source/usbd_enum.c new file mode 100644 index 00000000..5fa9f3ab --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/core/Source/usbd_enum.c @@ -0,0 +1,764 @@ +/*! + \file usbd_enum.c + \brief USB enumeration function + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_enum.h" +#include "usb_ch9_std.h" + +#ifdef WINUSB_EXEMPT_DRIVER + +extern usbd_status usbd_OEM_req(usb_dev *udev, usb_req *req); + +#endif /* WINUSB_EXEMPT_DRIVER */ + +/* local function prototypes ('static') */ +static usb_reqsta _usb_std_reserved (usb_core_driver *udev, usb_req *req); +static uint8_t* _usb_dev_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +static uint8_t* _usb_config_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +static uint8_t* _usb_bos_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +static uint8_t* _usb_str_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len); +static usb_reqsta _usb_std_getstatus (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_clearfeature (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setfeature (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setaddress (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_getdescriptor (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setdescriptor (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_getconfiguration (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setconfiguration (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_getinterface (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setinterface (usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_synchframe (usb_core_driver *udev, usb_req *req); + +static usb_reqsta (*_std_dev_req[])(usb_core_driver *udev, usb_req *req) = +{ + [USB_GET_STATUS] = _usb_std_getstatus, + [USB_CLEAR_FEATURE] = _usb_std_clearfeature, + [USB_RESERVED2] = _usb_std_reserved, + [USB_SET_FEATURE] = _usb_std_setfeature, + [USB_RESERVED4] = _usb_std_reserved, + [USB_SET_ADDRESS] = _usb_std_setaddress, + [USB_GET_DESCRIPTOR] = _usb_std_getdescriptor, + [USB_SET_DESCRIPTOR] = _usb_std_setdescriptor, + [USB_GET_CONFIGURATION] = _usb_std_getconfiguration, + [USB_SET_CONFIGURATION] = _usb_std_setconfiguration, + [USB_GET_INTERFACE] = _usb_std_getinterface, + [USB_SET_INTERFACE] = _usb_std_setinterface, + [USB_SYNCH_FRAME] = _usb_std_synchframe, +}; + +/* get standard descriptor handler */ +static uint8_t* (*std_desc_get[])(usb_core_driver *udev, uint8_t index, uint16_t *len) = { + [(uint8_t)USB_DESCTYPE_DEV - 1U] = _usb_dev_desc_get, + [(uint8_t)USB_DESCTYPE_CONFIG - 1U] = _usb_config_desc_get, + [(uint8_t)USB_DESCTYPE_STR - 1U] = _usb_str_desc_get, +}; + +/*! + \brief handle USB standard device request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +usb_reqsta usbd_standard_request (usb_core_driver *udev, usb_req *req) +{ + return (*_std_dev_req[req->bRequest])(udev, req); +} + +/*! + \brief handle USB device class request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device class request + \param[out] none + \retval USB device request status +*/ +usb_reqsta usbd_class_request (usb_core_driver *udev, usb_req *req) +{ + if ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) { + if (BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) { + /* call device class handle function */ + return (usb_reqsta)udev->dev.class_core->req_proc(udev, req); + } + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB vendor request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB vendor request + \param[out] none + \retval USB device request status +*/ +usb_reqsta usbd_vendor_request (usb_core_driver *udev, usb_req *req) +{ + (void)udev; + (void)req; + + /* added by user... */ +#ifdef WINUSB_EXEMPT_DRIVER + usbd_OEM_req(udev, req); +#endif + + return REQ_SUPP; +} + +/*! + \brief handle USB enumeration error + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +void usbd_enum_error (usb_core_driver *udev, usb_req *req) +{ + (void)req; + + (void)usbd_ep_stall (udev, 0x80U); + (void)usbd_ep_stall (udev, 0x00U); + + usb_ctlep_startout(udev); +} + +/*! + \brief convert hex 32bits value into unicode char + \param[in] value: hex 32bits value + \param[in] pbuf: buffer pointer to store unicode char + \param[in] len: value length + \param[out] none + \retval none +*/ +void int_to_unicode (uint32_t value, uint8_t *pbuf, uint8_t len) +{ + uint8_t index; + + for (index = 0U; index < len; index++) { + if ((value >> 28U) < 0x0AU) { + pbuf[2U * index] = (uint8_t)((value >> 28U) + '0'); + } else { + pbuf[2U * index] = (uint8_t)((value >> 28U) + 'A' - 10U); + } + + value = value << 4U; + + pbuf[2U * index + 1U] = 0U; + } +} + +/*! + \brief convert hex 32bits value into unicode char + \param[in] unicode_str: pointer to unicode string + \param[out] none + \retval none +*/ +void serial_string_get (uint16_t *unicode_str) +{ + if ((unicode_str[0] & 0x00FFU) != 6U) { + uint32_t DeviceSerial0, DeviceSerial1, DeviceSerial2; + + DeviceSerial0 = *(uint32_t*)DEVICE_ID1; + DeviceSerial1 = *(uint32_t*)DEVICE_ID2; + DeviceSerial2 = *(uint32_t*)DEVICE_ID3; + + DeviceSerial0 += DeviceSerial2; + + if (0U != DeviceSerial0) { + int_to_unicode(DeviceSerial0, (uint8_t*)&(unicode_str[1]), 8U); + int_to_unicode(DeviceSerial1, (uint8_t*)&(unicode_str[9]), 4U); + } + } else { + uint32_t device_serial = *(uint32_t*)DEVICE_ID; + + if(0U != device_serial) { + unicode_str[1] = (uint16_t)(device_serial & 0x0000FFFFU); + unicode_str[2] = (uint16_t)((device_serial & 0xFFFF0000U) >> 16U); + + } + } +} + +/*! + \brief no operation, just for reserved + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB vendor request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_reserved (usb_core_driver *udev, usb_req *req) +{ + (void)udev; + (void)req; + + /* no operation... */ + + return REQ_NOTSUPP; +} + +/*! + \brief get the device descriptor + \param[in] udev: pointer to USB device instance + \param[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_dev_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + (void)index; + + *len = udev->dev.desc->dev_desc[0]; + + return udev->dev.desc->dev_desc; +} + +/*! + \brief get the configuration descriptor + \brief[in] udev: pointer to USB device instance + \brief[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_config_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + (void)index; + + *len = udev->dev.desc->config_desc[2] | (udev->dev.desc->config_desc[3]<< 8U); + + return udev->dev.desc->config_desc; +} + +/*! + \brief get the BOS descriptor + \brief[in] udev: pointer to USB device instance + \brief[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_bos_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + (void)index; + + *len = udev->dev.desc->bos_desc[2]; + + return udev->dev.desc->bos_desc; +} + +/*! + \brief get string descriptor + \param[in] udev: pointer to USB device instance + \param[in] index: string descriptor index + \param[out] len: pointer to string length + \retval descriptor buffer pointer +*/ +static uint8_t* _usb_str_desc_get (usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + uint8_t *desc = udev->dev.desc->strings[index]; + + *len = desc[0]; + + return desc; +} + +/*! + \brief handle Get_Status request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_getstatus (usb_core_driver *udev, usb_req *req) +{ + uint8_t recp = BYTE_LOW(req->wIndex); + usb_reqsta req_status = REQ_NOTSUPP; + usb_transc *transc = &udev->dev.transc_in[0]; + + static uint8_t status[2] = {0}; + + switch(req->bmRequestType & (uint8_t)USB_RECPTYPE_MASK) { + case USB_RECPTYPE_DEV: + if (((uint8_t)USBD_ADDRESSED == udev->dev.cur_status) || \ + ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)) { + + if (udev->dev.pm.power_mode) { + status[0] = USB_STATUS_SELF_POWERED; + } else { + status[0] = 0U; + } + + if (udev->dev.pm.dev_remote_wakeup) { + status[0] |= USB_STATUS_REMOTE_WAKEUP; + } else { + status[0] = 0U; + } + + req_status = REQ_SUPP; + } + break; + + case USB_RECPTYPE_ITF: + if (((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) && (recp <= USBD_ITF_MAX_NUM)) { + req_status = REQ_SUPP; + } + break; + + case USB_RECPTYPE_EP: + if ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) { + if (0x80U == (recp & 0x80U)) { + status[0] = udev->dev.transc_in[EP_ID(recp)].ep_stall; + } else { + status[0] = udev->dev.transc_out[recp].ep_stall; + } + + req_status = REQ_SUPP; + } + break; + + default: + break; + } + + if (REQ_SUPP == req_status) { + transc->xfer_buf = status; + transc->remain_len = 2U; + } + + return req_status; +} + +/*! + \brief handle USB Clear_Feature request + \param[in] udev: pointer to USB device instance + \param[in] req: USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_clearfeature (usb_core_driver *udev, usb_req *req) +{ + uint8_t ep = 0U; + + switch(req->bmRequestType & (uint8_t)USB_RECPTYPE_MASK) { + case USB_RECPTYPE_DEV: + if (((uint8_t)USBD_ADDRESSED == udev->dev.cur_status) || \ + ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)) { + + /* clear device remote wakeup feature */ + if ((uint16_t)USB_FEATURE_REMOTE_WAKEUP == req->wValue) { + udev->dev.pm.dev_remote_wakeup = 0U; + + return REQ_SUPP; + } + } + break; + + case USB_RECPTYPE_ITF: + break; + + case USB_RECPTYPE_EP: + /* get endpoint address */ + ep = BYTE_LOW(req->wIndex); + + if ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) { + /* clear endpoint halt feature */ + if (((uint16_t)USB_FEATURE_EP_HALT == req->wValue) && (!CTL_EP(ep))) { + (void)usbd_ep_stall_clear (udev, ep); + + (void)udev->dev.class_core->req_proc (udev, req); + } + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Set_Feature request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setfeature (usb_core_driver *udev, usb_req *req) +{ + uint8_t ep = 0U; + + switch (req->bmRequestType & (uint8_t)USB_RECPTYPE_MASK) { + case USB_RECPTYPE_DEV: + if (((uint8_t)USBD_ADDRESSED == udev->dev.cur_status) || \ + ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)) { + /* set device remote wakeup feature */ + if ((uint16_t)USB_FEATURE_REMOTE_WAKEUP == req->wValue) { + udev->dev.pm.dev_remote_wakeup = 1U; + } + + return REQ_SUPP; + } + break; + + case USB_RECPTYPE_ITF: + break; + + case USB_RECPTYPE_EP: + /* get endpoint address */ + ep = BYTE_LOW(req->wIndex); + + if ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) { + /* set endpoint halt feature */ + if (((uint16_t)USB_FEATURE_EP_HALT == req->wValue) && (!CTL_EP(ep))) { + (void)usbd_ep_stall (udev, ep); + } + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Set_Address request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setaddress (usb_core_driver *udev, usb_req *req) +{ + if ((0U == req->wIndex) && (0U == req->wLength)) { + udev->dev.dev_addr = (uint8_t)(req->wValue) & 0x7FU; + + if (udev->dev.cur_status != (uint8_t)USBD_CONFIGURED) { + usbd_addr_set (udev, udev->dev.dev_addr); + + if (udev->dev.dev_addr) { + udev->dev.cur_status = (uint8_t)USBD_ADDRESSED; + } else { + udev->dev.cur_status = (uint8_t)USBD_DEFAULT; + } + + return REQ_SUPP; + } + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Get_Descriptor request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_getdescriptor (usb_core_driver *udev, usb_req *req) +{ + uint8_t desc_type = 0U; + uint8_t desc_index = 0U; + + usb_reqsta status = REQ_NOTSUPP; + + usb_transc *transc = &udev->dev.transc_in[0]; + + /* get device standard descriptor */ + switch (req->bmRequestType & USB_RECPTYPE_MASK) { + case USB_RECPTYPE_DEV: + desc_type = BYTE_HIGH(req->wValue); + desc_index = BYTE_LOW(req->wValue); + + switch (desc_type) { + case USB_DESCTYPE_DEV: + transc->xfer_buf = std_desc_get[desc_type - 1U](udev, desc_index, (uint16_t *)&(transc->remain_len)); + + if (64U == req->wLength) { + transc->remain_len = 8U; + } + break; + + case USB_DESCTYPE_CONFIG: + transc->xfer_buf = std_desc_get[desc_type - 1U](udev, desc_index, (uint16_t *)&(transc->remain_len)); + break; + + case USB_DESCTYPE_STR: + if (desc_index < (uint8_t)STR_IDX_MAX) { + transc->xfer_buf = std_desc_get[desc_type - 1U](udev, desc_index, (uint16_t *)&(transc->remain_len)); + } + break; + + case USB_DESCTYPE_ITF: + case USB_DESCTYPE_EP: + case USB_DESCTYPE_DEV_QUALIFIER: + case USB_DESCTYPE_OTHER_SPD_CONFIG: + case USB_DESCTYPE_ITF_POWER: + break; + + case USB_DESCTYPE_BOS: + transc->xfer_buf = _usb_bos_desc_get(udev, desc_index, (uint16_t *)&(transc->remain_len)); + break; + + default: + break; + } + break; + + case USB_RECPTYPE_ITF: + /* get device class special descriptor */ + status = (usb_reqsta)(udev->dev.class_core->req_proc(udev, req)); + break; + + case USB_RECPTYPE_EP: + break; + + default: + break; + } + + if ((0U != transc->remain_len) && (0U != req->wLength)) { + if (transc->remain_len < req->wLength) { + if ((transc->remain_len >= transc->max_len) && (0U == (transc->remain_len % transc->max_len))) { + udev->dev.control.ctl_zlp = 1U; + } + } else { + transc->remain_len = req->wLength; + } + + status = REQ_SUPP; + } + + return status; +} + +/*! + \brief handle USB Set_Descriptor request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setdescriptor (usb_core_driver *udev, usb_req *req) +{ + (void)udev; + (void)req; + + /* no handle... */ + return REQ_SUPP; +} + +/*! + \brief handle USB Get_Configuration request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_getconfiguration (usb_core_driver *udev, usb_req *req) +{ + (void)req; + + usb_reqsta req_status = REQ_NOTSUPP; + usb_transc *transc = &udev->dev.transc_in[0]; + + switch (udev->dev.cur_status) { + case USBD_ADDRESSED: + if (USB_DEFAULT_CONFIG == udev->dev.config) { + req_status = REQ_SUPP; + } + break; + + case USBD_CONFIGURED: + if (udev->dev.config != USB_DEFAULT_CONFIG) { + req_status = REQ_SUPP; + } + break; + + default: + break; + } + + if (REQ_SUPP == req_status) { + transc->xfer_buf = &(udev->dev.config); + transc->remain_len = 1U; + } + + return req_status; +} + +/*! + \brief handle USB Set_Configuration request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setconfiguration (usb_core_driver *udev, usb_req *req) +{ + static uint8_t config; + usb_reqsta status = REQ_NOTSUPP; + + config = (uint8_t)(req->wValue); + + if (config <= USBD_CFG_MAX_NUM) { + switch (udev->dev.cur_status) { + case USBD_ADDRESSED: + if (config){ + (void)udev->dev.class_core->init(udev, config); + + udev->dev.config = config; + udev->dev.cur_status = (uint8_t)USBD_CONFIGURED; + } + + status = REQ_SUPP; + break; + + case USBD_CONFIGURED: + if (USB_DEFAULT_CONFIG == config) { + (void)udev->dev.class_core->deinit(udev, config); + + udev->dev.config = config; + udev->dev.cur_status = (uint8_t)USBD_ADDRESSED; + } else if (config != udev->dev.config) { + /* clear old configuration */ + (void)udev->dev.class_core->deinit(udev, config); + + /* set new configuration */ + udev->dev.config = config; + + (void)udev->dev.class_core->init(udev, config); + } else { + /* no operation */ + } + + status = REQ_SUPP; + break; + + case USBD_DEFAULT: + break; + + default: + break; + } + } + + return status; +} + +/*! + \brief handle USB Get_Interface request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_getinterface (usb_core_driver *udev, usb_req *req) +{ + switch (udev->dev.cur_status) { + case USBD_DEFAULT: + break; + + case USBD_ADDRESSED: + break; + + case USBD_CONFIGURED: + if (BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) { + usb_transc *transc = &udev->dev.transc_in[0]; + + transc->xfer_buf = &(udev->dev.class_core->alter_set); + transc->remain_len = 1U; + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Set_Interface request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setinterface (usb_core_driver *udev, usb_req *req) +{ + switch (udev->dev.cur_status) { + case USBD_DEFAULT: + break; + + case USBD_ADDRESSED: + break; + + case USBD_CONFIGURED: + if (BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) { + if (NULL != udev->dev.class_core->set_intf) { + (void)udev->dev.class_core->set_intf (udev, req); + } + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB SynchFrame request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_synchframe (usb_core_driver *udev, usb_req *req) +{ + (void)udev; + (void)req; + + /* no handle */ + return REQ_SUPP; +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/core/Source/usbd_transc.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/core/Source/usbd_transc.c new file mode 100644 index 00000000..04a77b81 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/device/core/Source/usbd_transc.c @@ -0,0 +1,256 @@ +/*! + \file usbd_transc.c + \brief USB transaction core functions + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_enum.h" +#include "usbd_transc.h" + +/*! + \brief USB send data in the control transaction + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +usbd_status usbd_ctl_send (usb_core_driver *udev) +{ + usb_transc *transc = &udev->dev.transc_in[0]; + + (void)usbd_ep_send(udev, 0U, transc->xfer_buf, transc->remain_len); + + if (transc->remain_len > transc->max_len) { + udev->dev.control.ctl_state = (uint8_t)USB_CTL_DATA_IN; + } else { + udev->dev.control.ctl_state = (uint8_t)USB_CTL_LAST_DATA_IN; + } + + return USBD_OK; +} + +/*! + \brief USB receive data in control transaction + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +usbd_status usbd_ctl_recev (usb_core_driver *udev) +{ + usb_transc *transc = &udev->dev.transc_out[0]; + + (void)usbd_ep_recev (udev, 0U, transc->xfer_buf, transc->remain_len); + + if (transc->remain_len > transc->max_len) { + udev->dev.control.ctl_state = (uint8_t)USB_CTL_DATA_OUT; + } else { + udev->dev.control.ctl_state = (uint8_t)USB_CTL_LAST_DATA_OUT; + } + + return USBD_OK; +} + +/*! + \brief USB send control transaction status + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +usbd_status usbd_ctl_status_send (usb_core_driver *udev) +{ + udev->dev.control.ctl_state = (uint8_t)USB_CTL_STATUS_IN; + + (void)usbd_ep_send (udev, 0U, NULL, 0U); + + usb_ctlep_startout(udev); + + return USBD_OK; +} + +/*! + \brief USB control receive status + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +usbd_status usbd_ctl_status_recev (usb_core_driver *udev) +{ + udev->dev.control.ctl_state = (uint8_t)USB_CTL_STATUS_OUT; + + (void)usbd_ep_recev (udev, 0U, NULL, 0U); + + usb_ctlep_startout(udev); + + return USBD_OK; +} + +/*! + \brief USB setup stage processing + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +uint8_t usbd_setup_transc (usb_core_driver *udev) +{ + usb_reqsta reqstat = REQ_NOTSUPP; + + usb_req req = udev->dev.control.req; + + switch (req.bmRequestType & USB_REQTYPE_MASK) { + /* standard device request */ + case USB_REQTYPE_STRD: + reqstat = usbd_standard_request (udev, &req); + break; + + /* device class request */ + case USB_REQTYPE_CLASS: + reqstat = usbd_class_request (udev, &req); + break; + + /* vendor defined request */ + case USB_REQTYPE_VENDOR: + reqstat = usbd_vendor_request (udev, &req); + break; + + default: + break; + } + + if (REQ_SUPP == reqstat) { + if (0U == req.wLength) { + (void)usbd_ctl_status_send (udev); + } else { + if (req.bmRequestType & 0x80U) { + (void)usbd_ctl_send (udev); + } else { + (void)usbd_ctl_recev (udev); + } + } + } else { + usbd_enum_error (udev, &req); + } + + return (uint8_t)USBD_OK; +} + +/*! + \brief data out stage processing + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier(0..7) + \param[out] none + \retval USB device operation cur_status +*/ +uint8_t usbd_out_transc (usb_core_driver *udev, uint8_t ep_num) +{ + if (0U == ep_num) { + usb_transc *transc = &udev->dev.transc_out[0]; + + switch (udev->dev.control.ctl_state) { + case USB_CTL_DATA_OUT: + /* update transfer length */ + transc->remain_len -= transc->max_len; + + (void)usbd_ctl_recev (udev); + break; + + case USB_CTL_LAST_DATA_OUT: + if (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) { + if (udev->dev.class_core->ctlx_out != NULL) { + (void)udev->dev.class_core->ctlx_out (udev); + } + } + + transc->remain_len = 0U; + + (void)usbd_ctl_status_send (udev); + break; + + default: + break; + } + } else if ((udev->dev.class_core->data_out != NULL) && (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED)) { + (void)udev->dev.class_core->data_out (udev, ep_num); + } else { + /* no operation */ + } + + return (uint8_t)USBD_OK; +} + +/*! + \brief data in stage processing + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier(0..7) + \param[out] none + \retval USB device operation cur_status +*/ +uint8_t usbd_in_transc (usb_core_driver *udev, uint8_t ep_num) +{ + if (0U == ep_num) { + usb_transc *transc = &udev->dev.transc_in[0]; + + switch (udev->dev.control.ctl_state) { + case USB_CTL_DATA_IN: + /* update transfer length */ + transc->remain_len -= transc->max_len; + + (void)usbd_ctl_send (udev); + break; + + case USB_CTL_LAST_DATA_IN: + /* last packet is MPS multiple, so send ZLP packet */ + if (udev->dev.control.ctl_zlp) { + (void)usbd_ep_send (udev, 0U, NULL, 0U); + + udev->dev.control.ctl_zlp = 0U; + } else { + if (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) { + if (udev->dev.class_core->ctlx_in != NULL) { + (void)udev->dev.class_core->ctlx_in (udev); + } + } + + transc->remain_len = 0U; + + (void)usbd_ctl_status_recev (udev); + } + break; + + default: + break; + } + } else { + if ((udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) && (udev->dev.class_core->data_in != NULL)) { + (void)udev->dev.class_core->data_in (udev, ep_num); + } + } + + return (uint8_t)USBD_OK; +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usb_core.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usb_core.h new file mode 100644 index 00000000..8ac36500 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usb_core.h @@ -0,0 +1,347 @@ +/*! + \file drv_usb_core.h + \brief USB core low level driver header file + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_CORE_H +#define __DRV_USB_CORE_H + +#include "drv_usb_regs.h" +#include "usb_ch9_std.h" + +#ifdef USE_DEVICE_MODE + #include "usbd_conf.h" +#endif /* USE_DEVICE_MODE */ + +#define USB_FS_EP0_MAX_LEN 64U /*!< maximum packet size of endpoint 0 */ +#define HC_MAX_PACKET_COUNT 140U /*!< maximum packet count */ + +#define EP_ID(x) ((uint8_t)((x) & 0x7FU)) /*!< endpoint number */ +#define EP_DIR(x) ((uint8_t)((x) >> 7)) /*!< endpoint direction */ + +enum _usb_mode { + DEVICE_MODE = 0U, /*!< device mode */ + HOST_MODE, /*!< host mode */ + OTG_MODE /*!< OTG mode */ +}; + +enum _usb_eptype { + USB_EPTYPE_CTRL = 0U, /*!< control endpoint type */ + USB_EPTYPE_ISOC = 1U, /*!< isochronous endpoint type */ + USB_EPTYPE_BULK = 2U, /*!< bulk endpoint type */ + USB_EPTYPE_INTR = 3U, /*!< interrupt endpoint type */ + USB_EPTYPE_MASK = 3U /*!< endpoint type mask */ +}; + +typedef enum +{ + USB_OTG_OK = 0U, /*!< USB OTG status OK*/ + USB_OTG_FAIL /*!< USB OTG status fail*/ +} usb_otg_status; + +typedef enum +{ + USB_OK = 0U, /*!< USB status OK*/ + USB_FAIL /*!< USB status fail*/ +} usb_status; + +typedef enum +{ + USB_USE_FIFO, /*!< USB use FIFO transfer mode */ +} usb_transfer_mode; + +typedef struct +{ + uint8_t core_enum; /*!< USB core type */ + uint8_t core_speed; /*!< USB core speed */ + uint8_t num_pipe; /*!< USB host channel numbers */ + uint8_t num_ep; /*!< USB device endpoint numbers */ + uint8_t transfer_mode; /*!< USB transfer mode */ + uint8_t phy_itf; /*!< USB core PHY interface */ + uint8_t sof_enable; /*!< USB SOF output */ + uint8_t low_power; /*!< USB low power */ + uint8_t lpm_enable; /*!< USB link power mode(LPM) */ + uint8_t vbus_sensing_enable; /*!< USB VBUS sensing feature */ + uint8_t use_dedicated_ep1; /*!< USB dedicated endpoint1 interrupt */ + uint8_t use_external_vbus; /*!< enable or disable the use of the external VBUS */ + uint32_t base_reg; /*!< base register address */ +} usb_core_basic; + +#ifdef USE_DEVICE_MODE + +/* USB descriptor */ +typedef struct _usb_desc { + uint8_t *dev_desc; /*!< device descriptor */ + uint8_t *config_desc; /*!< configure descriptor */ + uint8_t *bos_desc; /*!< BOS descriptor */ + void* const *strings; /*!< string descriptor */ +} usb_desc; + +/* USB power management */ +typedef struct _usb_pm { + uint8_t power_mode; /*!< power mode */ + uint8_t power_low; /*!< power low */ + uint8_t dev_remote_wakeup; /*!< remote wakeup */ + uint8_t remote_wakeup_on; /*!< remote wakeup on */ +} usb_pm; + +/* USB control information */ +typedef struct _usb_control { + usb_req req; /*!< USB standard device request */ + + uint8_t ctl_state; /*!< USB control transfer state */ + uint8_t ctl_zlp; /*!< zero length package */ +} usb_control; + +typedef struct +{ + struct { + uint8_t num: 4; /*!< the endpoint number.it can be from 0 to 6 */ + uint8_t pad: 3; /*!< padding between number and direction */ + uint8_t dir: 1; /*!< the endpoint direction */ + } ep_addr; + + uint8_t ep_type; /*!< USB endpoint type */ + uint8_t ep_stall; /*!< USB endpoint stall status */ + + uint8_t frame_num; /*!< number of frame */ + uint16_t max_len; /*!< Maximum packet length */ + + /* transaction level variables */ + uint8_t *xfer_buf; /*!< transmit buffer */ + uint32_t xfer_len; /*!< transmit buffer length */ + uint32_t xfer_count; /*!< transmit buffer count */ + + uint32_t remain_len; /*!< remain packet length */ +} usb_transc; + +typedef struct _usb_core_driver usb_dev; + +typedef struct _usb_class_core +{ + uint8_t command; /*!< device class request command */ + uint8_t alter_set; /*!< alternative set */ + + uint8_t (*init) (usb_dev *udev, uint8_t config_index); /*!< initialize handler */ + uint8_t (*deinit) (usb_dev *udev, uint8_t config_index); /*!< de-initialize handler */ + + uint8_t (*req_proc) (usb_dev *udev, usb_req *req); /*!< device request handler */ + + uint8_t (*set_intf) (usb_dev *udev, usb_req *req); /*!< device set interface callback */ + + uint8_t (*ctlx_in) (usb_dev *udev); /*!< device contrl in callback */ + uint8_t (*ctlx_out) (usb_dev *udev); + + uint8_t (*data_in) (usb_dev *udev, uint8_t ep_num); /*!< device data in handler */ + uint8_t (*data_out) (usb_dev *udev, uint8_t ep_num); /*!< device data out handler */ + + uint8_t (*SOF) (usb_dev *udev); /*!< Start of frame handler */ + + uint8_t (*incomplete_isoc_in) (usb_dev *udev); /*!< Incomplete synchronization IN transfer handler */ + uint8_t (*incomplete_isoc_out) (usb_dev *udev); /*!< Incomplete synchronization OUT transfer handler */ +} usb_class_core; + +typedef struct _usb_perp_dev +{ + uint8_t config; /*!< configuration */ + uint8_t dev_addr; /*!< device address */ + + __IO uint8_t cur_status; /*!< current status */ + __IO uint8_t backup_status; /*!< backup status */ + + usb_transc transc_in[USBFS_MAX_TX_FIFOS]; /*!< endpoint IN transaction */ + usb_transc transc_out[USBFS_MAX_TX_FIFOS]; /*!< endpoint OUT transaction */ + + usb_pm pm; /*!< power management */ + usb_control control; /*!< USB control information */ + usb_desc *desc; /*!< USB descriptors pointer */ + usb_class_core *class_core; /*!< class driver */ + void *class_data[USBD_ITF_MAX_NUM]; /*!< class data pointer */ + void *user_data; /*!< user data pointer */ + void *pdata; /*!< reserved data pointer */ +} usb_perp_dev; + +#endif /* USE_DEVICE_MODE */ + +#ifdef USE_HOST_MODE + +typedef enum _usb_pipe_status +{ + PIPE_IDLE = 0U, + PIPE_XF, + PIPE_HALTED, + PIPE_NAK, + PIPE_NYET, + PIPE_STALL, + PIPE_TRACERR, + PIPE_BBERR, + PIPE_REQOVR, + PIPE_DTGERR, +} usb_pipe_staus; + +typedef enum _usb_urb_state +{ + URB_IDLE = 0U, + URB_DONE, + URB_NOTREADY, + URB_ERROR, + URB_STALL, + URB_PING +} usb_urb_state; + +typedef struct _usb_pipe +{ + uint8_t in_used; + uint8_t dev_addr; + uint32_t dev_speed; + + struct { + uint8_t num; + uint8_t dir; + uint8_t type; + uint16_t mps; + } ep; + + __IO uint8_t supp_ping; + __IO uint8_t do_ping; + __IO uint32_t DPID; + + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t xfer_count; + + uint8_t data_toggle_in; + uint8_t data_toggle_out; + + __IO uint32_t err_count; + __IO usb_pipe_staus pp_status; + __IO usb_urb_state urb_state; +} usb_pipe; + +typedef struct _usb_host_drv +{ + __IO uint32_t connect_status; + __IO uint32_t port_enabled; + __IO uint32_t backup_xfercount[USBFS_MAX_TX_FIFOS]; + + usb_pipe pipe[USBFS_MAX_TX_FIFOS]; + void *data; +} usb_host_drv; + +#endif /* USE_HOST_MODE */ + +typedef struct _usb_core_driver +{ + usb_core_basic bp; /*!< USB basic parameters */ + usb_core_regs regs; /*!< USB registers */ + +#ifdef USE_DEVICE_MODE + usb_perp_dev dev; /*!< USB peripheral device */ +#endif /* USE_DEVICE_MODE */ + +#ifdef USE_HOST_MODE + usb_host_drv host; +#endif /* USE_HOST_MODE */ +} usb_core_driver; + +/* static inline function definitions */ + +/*! + \brief get the global interrupts + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval interrupt status +*/ +__STATIC_INLINE uint32_t usb_coreintr_get(usb_core_regs *usb_regs) +{ + uint32_t reg_data = usb_regs->gr->GINTEN; + + reg_data &= usb_regs->gr->GINTF; + + return reg_data; +} + +/*! + \brief set USB RX FIFO size + \param[in] usb_regs: pointer to USB core registers + \param[in] size: assigned FIFO size + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_set_rxfifo(usb_core_regs *usb_regs, uint16_t size) +{ + usb_regs->gr->GRFLEN = size; +} + +/*! + \brief enable the global interrupts + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_globalint_enable(usb_core_regs *usb_regs) +{ + /* enable USB global interrupt */ + usb_regs->gr->GAHBCS |= GAHBCS_GINTEN; +} + +/*! + \brief disable the global interrupts + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_globalint_disable(usb_core_regs *usb_regs) +{ + /* disable USB global interrupt */ + usb_regs->gr->GAHBCS &= ~GAHBCS_GINTEN; +} + +/* function declarations */ +/* configure core capabilities */ +usb_status usb_basic_init (usb_core_basic *usb_basic, usb_core_regs *usb_regs, usb_core_enum usb_core); +/* initializes the USB controller registers and prepares the core device mode or host mode operation */ +usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs); +/* write a packet into the Tx FIFO associated with the endpoint */ +usb_status usb_txfifo_write (usb_core_regs *usb_regs, uint8_t *src_buf, uint8_t fifo_num, uint16_t byte_count); +/* read a packet from the Rx FIFO associated with the endpoint */ +void *usb_rxfifo_read (usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count); +/* flush a Tx FIFO or all Tx FIFOs */ +usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num); +/* flush the entire Rx FIFO */ +usb_status usb_rxfifo_flush (usb_core_regs *usb_regs); +/* set endpoint or channel TX FIFO size */ +void usb_set_txfifo(usb_core_regs *usb_regs, uint8_t fifo, uint16_t size); +/* set USB current mode */ +void usb_curmode_set(usb_core_regs *usb_regs, uint8_t mode); + +#endif /* __DRV_USB_CORE_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usb_dev.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usb_dev.h new file mode 100644 index 00000000..655ed160 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usb_dev.h @@ -0,0 +1,197 @@ +/*! + \file drv_usb_dev.h + \brief USB device low level driver header file + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_DEV_H +#define __DRV_USB_DEV_H + +#include "usbd_conf.h" +#include "drv_usb_core.h" + +#define EP_IN(x) ((uint8_t)(0x80U | (x))) /*!< device IN endpoint */ +#define EP_OUT(x) ((uint8_t)(x)) /*!< device OUT endpoint */ + +enum usb_ctl_status { + USB_CTL_IDLE = 0U, /*!< USB control transfer idle state */ + USB_CTL_DATA_IN, /*!< USB control transfer data in state */ + USB_CTL_LAST_DATA_IN, /*!< USB control transfer last data in state */ + USB_CTL_DATA_OUT, /*!< USB control transfer data out state */ + USB_CTL_LAST_DATA_OUT, /*!< USB control transfer last data out state */ + USB_CTL_STATUS_IN, /*!< USB control transfer status in state*/ + USB_CTL_STATUS_OUT /*!< USB control transfer status out state */ +}; + +/* static inline function definitions */ + +/*! + \brief configure the USB device to be disconnected + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +__STATIC_INLINE void usb_dev_disconnect (usb_core_driver *udev) +{ + udev->regs.dr->DCTL |= DCTL_SD; +} + +/*! + \brief configure the USB device to be connected + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +__STATIC_INLINE void usb_dev_connect (usb_core_driver *udev) +{ + udev->regs.dr->DCTL &= ~DCTL_SD; +} + +/*! + \brief set the USB device address + \param[in] udev: pointer to USB device + \param[in] dev_addr: device address for setting + \param[out] none + \retval operation status +*/ +__STATIC_INLINE void usb_devaddr_set (usb_core_driver *udev, uint8_t dev_addr) +{ + udev->regs.dr->DCFG &= ~DCFG_DAR; + udev->regs.dr->DCFG |= (uint32_t)dev_addr << 4U; +} + +/*! + \brief read device all OUT endpoint interrupt register + \param[in] udev: pointer to USB device + \param[out] none + \retval interrupt status +*/ +__STATIC_INLINE uint32_t usb_oepintnum_read (usb_core_driver *udev) +{ + uint32_t value = udev->regs.dr->DAEPINT; + + value &= udev->regs.dr->DAEPINTEN; + + return (value & DAEPINT_OEPITB) >> 16U; +} + +/*! + \brief read device OUT endpoint interrupt flag register + \param[in] udev: pointer to USB device + \param[in] ep_num: endpoint number + \param[out] none + \retval interrupt status +*/ +__STATIC_INLINE uint32_t usb_oepintr_read (usb_core_driver *udev, uint8_t ep_num) +{ + uint32_t value = udev->regs.er_out[ep_num]->DOEPINTF; + + value &= udev->regs.dr->DOEPINTEN; + + return value; +} + +/*! + \brief read device all IN endpoint interrupt register + \param[in] udev: pointer to USB device + \param[out] none + \retval interrupt status +*/ +__STATIC_INLINE uint32_t usb_iepintnum_read (usb_core_driver *udev) +{ + uint32_t value = udev->regs.dr->DAEPINT; + + value &= udev->regs.dr->DAEPINTEN; + + return value & DAEPINT_IEPITB; +} + +/*! + \brief set remote wakeup signaling + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_rwkup_set (usb_core_driver *udev) +{ + if (udev->dev.pm.dev_remote_wakeup) { + /* enable remote wakeup signaling */ + udev->regs.dr->DCTL |= DCTL_RWKUP; + } +} + +/*! + \brief reset remote wakeup signaling + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_rwkup_reset (usb_core_driver *udev) +{ + if (udev->dev.pm.dev_remote_wakeup) { + /* disable remote wakeup signaling */ + udev->regs.dr->DCTL &= ~DCTL_RWKUP; + } +} + +/* function declarations */ +/* initialize USB core registers for device mode */ +usb_status usb_devcore_init (usb_core_driver *udev); +/* enable the USB device mode interrupts */ +usb_status usb_devint_enable (usb_core_driver *udev); +/* active the USB endpoint 0 transaction */ +usb_status usb_transc0_active (usb_core_driver *udev, usb_transc *transc); +/* active the USB transaction */ +usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc); +/* deactivate the USB transaction */ +usb_status usb_transc_deactivate (usb_core_driver *udev, usb_transc *transc); +/* configure USB transaction to start IN transfer */ +usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc); +/* configure USB transaction to start OUT transfer */ +usb_status usb_transc_outxfer (usb_core_driver *udev, usb_transc *transc); +/* set the USB transaction STALL status */ +usb_status usb_transc_stall (usb_core_driver *udev, usb_transc *transc); +/* clear the USB transaction STALL status */ +usb_status usb_transc_clrstall (usb_core_driver *udev, usb_transc *transc); +/* read device IN endpoint interrupt flag register */ +uint32_t usb_iepintr_read (usb_core_driver *udev, uint8_t ep_num); +/* configures OUT endpoint 0 to receive SETUP packets */ +void usb_ctlep_startout (usb_core_driver *udev); +/* active remote wakeup signaling */ +void usb_rwkup_active (usb_core_driver *udev); +/* active USB core clock */ +void usb_clock_active (usb_core_driver *udev); +/* USB device suspend */ +void usb_dev_suspend (usb_core_driver *udev); +/* stop the device and clean up FIFOs */ +void usb_dev_stop (usb_core_driver *udev); + +#endif /* __DRV_USB_DEV_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usb_host.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usb_host.h new file mode 100644 index 00000000..9d612d04 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usb_host.h @@ -0,0 +1,123 @@ +/*! + \file drv_usb_host.h + \brief USB host mode low level driver header file + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_HOST_H +#define __DRV_USB_HOST_H + +#include "drv_usb_regs.h" +#include "usb_ch9_std.h" +#include "drv_usb_core.h" + +typedef enum _usb_pipe_mode +{ + PIPE_PERIOD = 0U, + PIPE_NON_PERIOD = 1U +} usb_pipe_mode; + +/*! + \brief get USB even frame + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +__STATIC_INLINE uint8_t usb_frame_even (usb_core_driver *udev) +{ + return (uint8_t)!(udev->regs.hr->HFINFR & 0x01U); +} + +/*! + \brief configure USB clock of PHY + \param[in] udev: pointer to USB device + \param[in] clock: PHY clock + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_phyclock_config (usb_core_driver *udev, uint8_t clock) +{ + udev->regs.hr->HCTL &= ~HCTL_CLKSEL; + udev->regs.hr->HCTL |= clock; +} + +/*! + \brief read USB port + \param[in] udev: pointer to USB device + \param[out] none + \retval port status +*/ +__STATIC_INLINE uint32_t usb_port_read (usb_core_driver *udev) +{ + return *udev->regs.HPCS & ~(HPCS_PE | HPCS_PCD | HPCS_PEDC); +} + +/*! + \brief get USB current speed + \param[in] udev: pointer to USB device + \param[out] none + \retval USB current speed +*/ +__STATIC_INLINE uint32_t usb_curspeed_get (usb_core_driver *udev) +{ + return *udev->regs.HPCS & HPCS_PS; +} + +/*! + \brief get USB current frame + \param[in] udev: pointer to USB device + \param[out] none + \retval USB current frame +*/ +__STATIC_INLINE uint32_t usb_curframe_get (usb_core_driver *udev) +{ + return (udev->regs.hr->HFINFR & 0xFFFFU); +} + +/* function declarations */ +/* initializes USB core for host mode */ +usb_status usb_host_init (usb_core_driver *udev); +/* control the VBUS to power */ +void usb_portvbus_switch (usb_core_driver *udev, uint8_t state); +/* reset host port */ +uint32_t usb_port_reset (usb_core_driver *udev); +/* initialize host pipe */ +usb_status usb_pipe_init (usb_core_driver *udev, uint8_t pipe_num); +/* prepare host pipe for transferring packets */ +usb_status usb_pipe_xfer (usb_core_driver *udev, uint8_t pipe_num); +/* halt host pipe */ +usb_status usb_pipe_halt (usb_core_driver *udev, uint8_t pipe_num); +/* configure host pipe to do ping operation */ +usb_status usb_pipe_ping (usb_core_driver *udev, uint8_t pipe_num); +/* stop the USB host and clean up FIFO */ +void usb_host_stop (usb_core_driver *udev); + +#endif /* __DRV_USB_HOST_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usb_hw.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usb_hw.h new file mode 100644 index 00000000..2eb6e7c9 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usb_hw.h @@ -0,0 +1,63 @@ +/*! + \file drv_usb_hw.h + \brief usb hardware configuration header file + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_HW_H +#define __DRV_USB_HW_H + +#include "usb_conf.h" + +/* function declarations */ +/* configure USB clock */ +void usb_rcu_config (void); +/* configure USB interrupt */ +void usb_intr_config (void); +/* initializes delay unit using Timer2 */ +void usb_timer_init (void); +/* delay in micro seconds */ +void usb_udelay (const uint32_t usec); +/* delay in milliseconds */ +void usb_mdelay (const uint32_t msec); +/* configures system clock after wakeup from STOP mode */ +void system_clk_config_stop(void); + +#ifdef USE_HOST_MODE +/* configure systick */ +void systick_config(void); +/* configure USB VBus */ +void usb_vbus_config (void); +/* drive USB VBus */ +void usb_vbus_drive (uint8_t State); +#endif /* USE_HOST_MODE */ + +#endif /* __DRV_USB_HW_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usb_regs.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usb_regs.h new file mode 100644 index 00000000..91297049 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usb_regs.h @@ -0,0 +1,628 @@ +/*! + \file drv_usb_regs.h + \brief USB cell registers definition and handle macros + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_REGS_H +#define __DRV_USB_REGS_H + +#include "usb_conf.h" + +#define USBFS_REG_BASE 0x50000000L /*!< base address of USBFS registers */ + +#define USBFS_MAX_TX_FIFOS 15U /*!< FIFO number */ + +#define USBFS_MAX_PACKET_SIZE 64U /*!< USBFS max packet size */ +#define USBFS_MAX_CHANNEL_COUNT 8U /*!< USBFS host channel count */ +#define USBFS_MAX_EP_COUNT 4U /*!< USBFS device endpoint count */ +#define USBFS_MAX_FIFO_WORDLEN 320U /*!< USBFS max fifo size in words */ + +#define USB_DATA_FIFO_OFFSET 0x1000U /*!< USB data fifo offset */ +#define USB_DATA_FIFO_SIZE 0x1000U /*!< USB data fifo size */ + +typedef enum +{ + USB_CORE_ENUM_HS = 0, /*!< USB core type is HS */ + USB_CORE_ENUM_FS = 1 /*!< USB core type is FS */ +} usb_core_enum; + +enum USB_SPEED { + USB_SPEED_UNKNOWN = 0, /*!< USB speed unknown */ + USB_SPEED_LOW, /*!< USB speed low */ + USB_SPEED_FULL, /*!< USB speed full */ + USB_SPEED_HIGH /*!< USB speed high */ +}; + +enum usb_reg_offset { + USB_REG_OFFSET_CORE = 0x0000U, /*!< global OTG control and status register */ + USB_REG_OFFSET_DEV = 0x0800U, /*!< device mode control and status registers */ + USB_REG_OFFSET_EP = 0x0020U, + USB_REG_OFFSET_EP_IN = 0x0900U, /*!< device IN endpoint 0 control register */ + USB_REG_OFFSET_EP_OUT = 0x0B00U, /*!< device OUT endpoint 0 control register */ + USB_REG_OFFSET_HOST = 0x0400U, /*!< host control register */ + USB_REG_OFFSET_CH = 0x0020U, + USB_REG_OFFSET_PORT = 0x0440U, /*!< host port control and status register */ + USB_REG_OFFSET_CH_INOUT = 0x0500U, /*!< Host channel-x control registers */ + USB_REG_OFFSET_PWRCLKCTL = 0x0E00U, /*!< power and clock register */ +}; + +typedef struct +{ + __IO uint32_t GOTGCS; /*!< USB global OTG control and status register 000h */ + __IO uint32_t GOTGINTF; /*!< USB global OTG interrupt flag register 004h */ + __IO uint32_t GAHBCS; /*!< USB global AHB control and status register 008h */ + __IO uint32_t GUSBCS; /*!< USB global USB control and status register 00Ch */ + __IO uint32_t GRSTCTL; /*!< USB global reset control register 010h */ + __IO uint32_t GINTF; /*!< USB global interrupt flag register 014h */ + __IO uint32_t GINTEN; /*!< USB global interrupt enable register 018h */ + __IO uint32_t GRSTATR; /*!< USB receive status debug read register 01Ch */ + __IO uint32_t GRSTATP; /*!< USB receive status and pop register 020h */ + __IO uint32_t GRFLEN; /*!< USB global receive FIFO length register 024h */ + __IO uint32_t DIEP0TFLEN_HNPTFLEN; /*!< USB device IN endpoint 0/host non-periodic transmit FIFO length register 028h */ + __IO uint32_t HNPTFQSTAT; /*!< USB host non-periodic FIFO/queue status register 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< USB global core configuration register 038h */ + __IO uint32_t CID; /*!< USB core ID register 03Ch */ + uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */ + __IO uint32_t HPTFLEN; /*!< USB host periodic transmit FIFO length register 100h */ + __IO uint32_t DIEPTFLEN[15]; /*!< USB device IN endpoint transmit FIFO length register 104h */ +} usb_gr; + +typedef struct +{ + __IO uint32_t HCTL; /*!< USB host control register 400h */ + __IO uint32_t HFT; /*!< USB host frame interval register 404h */ + __IO uint32_t HFINFR; /*!< USB host frame information remaining register 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTFQSTAT; /*!< USB host periodic transmit FIFO/queue status register 410h */ + __IO uint32_t HACHINT; /*!< USB host all channels interrupt register 414h */ + __IO uint32_t HACHINTEN; /*!< USB host all channels interrupt enable register 418h */ +} usb_hr; + +typedef struct +{ + __IO uint32_t HCHCTL; /*!< USB host channel control register 500h */ + __IO uint32_t HCHSTCTL; /*!< Reserved 504h */ + __IO uint32_t HCHINTF; /*!< USB host channel interrupt flag register 508h */ + __IO uint32_t HCHINTEN; /*!< USB host channel interrupt enable register 50Ch */ + __IO uint32_t HCHLEN; /*!< USB host channel transfer length register 510h */ + uint32_t Reserved514; /*!< Reserved 514h*/ + uint32_t Reserved[2]; +} usb_pr; + +typedef struct +{ + __IO uint32_t DCFG; /*!< USB device configuration register 800h */ + __IO uint32_t DCTL; /*!< USB device control register 804h */ + __IO uint32_t DSTAT; /*!< USB device status register 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPINTEN; /*!< USB device IN endpoint common interrupt enable register 810h */ + __IO uint32_t DOEPINTEN; /*!< USB device OUT endpoint common interrupt enable register 814h */ + __IO uint32_t DAEPINT; /*!< USB device all endpoints interrupt register 818h */ + __IO uint32_t DAEPINTEN; /*!< USB device all endpoints interrupt enable register 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved24; /*!< Reserved 824h */ + __IO uint32_t DVBUSDT; /*!< USB device VBUS discharge time register 828h */ + __IO uint32_t DVBUSPT; /*!< USB device VBUS pulsing time register 82Ch */ + __IO uint32_t DTHRCTL; /*!< device threshold control 830h */ + __IO uint32_t DIEPFEINTEN; /*!< USB Device IN endpoint FIFO empty interrupt enable register 834h */ + __IO uint32_t DEP1INT; /*!< USB device endpoint 1 interrupt register 838h */ + __IO uint32_t DEP1INTEN; /*!< USB device endpoint 1 interrupt enable register 83Ch */ + uint32_t Reserved40; /*!< Reserved 840h */ + __IO uint32_t DIEP1INTEN; /*!< USB device IN endpoint-1 interrupt enable register 844h */ + uint32_t Reserved48[15]; /*!< Reserved 848-880h */ + __IO uint32_t DOEP1INTEN; /*!< USB device OUT endpoint-1 interrupt enable register 884h */ +} usb_dr; + +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< USB device IN endpoint control register 900h + (EpNum * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (EpNum * 20h) + 04h */ + __IO uint32_t DIEPINTF; /*!< USB device IN endpoint interrupt flag register 900h + (EpNum * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (EpNum * 20h) + 0Ch */ + __IO uint32_t DIEPLEN; /*!< USB device IN endpoint transfer length register 900h + (EpNum * 20h) + 10h */ + uint32_t Reserved14; /*!< Reserved 900h + (EpNum * 20h) + 14h */ + __IO uint32_t DIEPTFSTAT; /*!< USB device IN endpoint transmit FIFO status register 900h + (EpNum * 20h) + 18h */ +} usb_erin; + +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< USB device IN endpoint control register B00h + (EpNum * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (EpNum * 20h) + 04h */ + __IO uint32_t DOEPINTF; /*!< USB device IN endpoint interrupt flag register B00h + (EpNum * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (EpNum * 20h) + 0Ch */ + __IO uint32_t DOEPLEN; /*!< USB device IN endpoint transfer length register B00h + (EpNum * 20h) + 10h */ + uint32_t Reserved14; /*!< Reserved B00h + (EpNum * 20h) + 14h */ +} usb_erout; + +typedef struct _usb_regs +{ + usb_gr *gr; /*!< USBFS global registers */ + usb_dr *dr; /*!< Device control and status registers */ + usb_hr *hr; /*!< Host control and status registers */ + usb_erin *er_in[6]; /*!< USB device IN endpoint register */ + usb_erout *er_out[6]; /*!< USB device OUT endpoint register */ + usb_pr *pr[15]; /*!< USB Host channel-x control register */ + + __IO uint32_t *HPCS; /*!< USB host port control and status register */ + __IO uint32_t *DFIFO[USBFS_MAX_TX_FIFOS]; + __IO uint32_t *PWRCLKCTL; /*!< USB power and clock control register */ +} usb_core_regs; + +/* global OTG control and status register bits definitions */ +#define GOTGCS_BSV BIT(19) /*!< B-Session Valid */ +#define GOTGCS_ASV BIT(18) /*!< A-session valid */ +#define GOTGCS_DI BIT(17) /*!< debounce interval */ +#define GOTGCS_CIDPS BIT(16) /*!< id pin status */ +#define GOTGCS_DHNPEN BIT(11) /*!< device HNP enable */ +#define GOTGCS_HHNPEN BIT(10) /*!< host HNP enable */ +#define GOTGCS_HNPREQ BIT(9) /*!< HNP request */ +#define GOTGCS_HNPS BIT(8) /*!< HNP successes */ +#define GOTGCS_SRPREQ BIT(1) /*!< SRP request */ +#define GOTGCS_SRPS BIT(0) /*!< SRP successes */ + +/* global OTG interrupt flag register bits definitions */ +#define GOTGINTF_DF BIT(19) /*!< debounce finish */ +#define GOTGINTF_ADTO BIT(18) /*!< A-device timeout */ +#define GOTGINTF_HNPDET BIT(17) /*!< host negotiation request detected */ +#define GOTGINTF_HNPEND BIT(9) /*!< HNP end */ +#define GOTGINTF_SRPEND BIT(8) /*!< SRP end */ +#define GOTGINTF_SESEND BIT(2) /*!< session end */ + +/* global AHB control and status register bits definitions */ +#define GAHBCS_PTXFTH BIT(8) /*!< periodic Tx FIFO threshold */ +#define GAHBCS_TXFTH BIT(7) /*!< tx FIFO threshold */ +#define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */ + +/* global USB control and status register bits definitions */ +#define GUSBCS_FDM BIT(30) /*!< force device mode */ +#define GUSBCS_FHM BIT(29) /*!< force host mode */ +#define GUSBCS_ULPIEOI BIT(21) /*!< ULPI external over-current indicator */ +#define GUSBCS_ULPIEVD BIT(20) /*!< ULPI external VBUS driver */ +#define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */ +#define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */ +#define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */ +#define GUSBCS_EMBPHY BIT(6) /*!< embedded PHY selected */ +#define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */ + +/* global reset control register bits definitions */ +#define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx FIFO number */ +#define GRSTCTL_TXFF BIT(5) /*!< tx FIFO flush */ +#define GRSTCTL_RXFF BIT(4) /*!< rx FIFO flush */ +#define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */ +#define GRSTCTL_HCSRST BIT(1) /*!< HCLK soft reset */ +#define GRSTCTL_CSRST BIT(0) /*!< core soft reset */ + +/* global interrupt flag register bits definitions */ +#define GINTF_WKUPIF BIT(31) /*!< wakeup interrupt flag */ +#define GINTF_SESIF BIT(30) /*!< session interrupt flag */ +#define GINTF_DISCIF BIT(29) /*!< disconnect interrupt flag */ +#define GINTF_IDPSC BIT(28) /*!< id pin status change */ +#define GINTF_PTXFEIF BIT(26) /*!< periodic tx FIFO empty interrupt flag */ +#define GINTF_HCIF BIT(25) /*!< host channels interrupt flag */ +#define GINTF_HPIF BIT(24) /*!< host port interrupt flag */ +#define GINTF_PXNCIF BIT(21) /*!< periodic transfer not complete interrupt flag */ +#define GINTF_ISOONCIF BIT(21) /*!< isochronous OUT transfer not complete interrupt flag */ +#define GINTF_ISOINCIF BIT(20) /*!< isochronous IN transfer not complete interrupt flag */ +#define GINTF_OEPIF BIT(19) /*!< OUT endpoint interrupt flag */ +#define GINTF_IEPIF BIT(18) /*!< IN endpoint interrupt flag */ +#define GINTF_EOPFIF BIT(15) /*!< end of periodic frame interrupt flag */ +#define GINTF_ISOOPDIF BIT(14) /*!< isochronous OUT packet dropped interrupt flag */ +#define GINTF_ENUMFIF BIT(13) /*!< enumeration finished */ +#define GINTF_RST BIT(12) /*!< USB reset */ +#define GINTF_SP BIT(11) /*!< USB suspend */ +#define GINTF_ESP BIT(10) /*!< early suspend */ +#define GINTF_GONAK BIT(7) /*!< global OUT NAK effective */ +#define GINTF_GNPINAK BIT(6) /*!< global IN non-periodic NAK effective */ +#define GINTF_NPTXFEIF BIT(5) /*!< non-periodic tx FIFO empty interrupt flag */ +#define GINTF_RXFNEIF BIT(4) /*!< rx FIFO non-empty interrupt flag */ +#define GINTF_SOF BIT(3) /*!< start of frame */ +#define GINTF_OTGIF BIT(2) /*!< OTG interrupt flag */ +#define GINTF_MFIF BIT(1) /*!< mode fault interrupt flag */ +#define GINTF_COPM BIT(0) /*!< current operation mode */ + +/* global interrupt enable register bits definitions */ +#define GINTEN_WKUPIE BIT(31) /*!< wakeup interrupt enable */ +#define GINTEN_SESIE BIT(30) /*!< session interrupt enable */ +#define GINTEN_DISCIE BIT(29) /*!< disconnect interrupt enable */ +#define GINTEN_IDPSCIE BIT(28) /*!< id pin status change interrupt enable */ +#define GINTEN_PTXFEIE BIT(26) /*!< periodic tx FIFO empty interrupt enable */ +#define GINTEN_HCIE BIT(25) /*!< host channels interrupt enable */ +#define GINTEN_HPIE BIT(24) /*!< host port interrupt enable */ +#define GINTEN_IPXIE BIT(21) /*!< periodic transfer not complete interrupt enable */ +#define GINTEN_ISOONCIE BIT(21) /*!< isochronous OUT transfer not complete interrupt enable */ +#define GINTEN_ISOINCIE BIT(20) /*!< isochronous IN transfer not complete interrupt enable */ +#define GINTEN_OEPIE BIT(19) /*!< OUT endpoints interrupt enable */ +#define GINTEN_IEPIE BIT(18) /*!< IN endpoints interrupt enable */ +#define GINTEN_EOPFIE BIT(15) /*!< end of periodic frame interrupt enable */ +#define GINTEN_ISOOPDIE BIT(14) /*!< isochronous OUT packet dropped interrupt enable */ +#define GINTEN_ENUMFIE BIT(13) /*!< enumeration finish enable */ +#define GINTEN_RSTIE BIT(12) /*!< USB reset interrupt enable */ +#define GINTEN_SPIE BIT(11) /*!< USB suspend interrupt enable */ +#define GINTEN_ESPIE BIT(10) /*!< early suspend interrupt enable */ +#define GINTEN_GONAKIE BIT(7) /*!< global OUT NAK effective interrupt enable */ +#define GINTEN_GNPINAKIE BIT(6) /*!< global non-periodic IN NAK effective interrupt enable */ +#define GINTEN_NPTXFEIE BIT(5) /*!< non-periodic Tx FIFO empty interrupt enable */ +#define GINTEN_RXFNEIE BIT(4) /*!< receive FIFO non-empty interrupt enable */ +#define GINTEN_SOFIE BIT(3) /*!< start of frame interrupt enable */ +#define GINTEN_OTGIE BIT(2) /*!< OTG interrupt enable */ +#define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */ + +/* global receive status read and pop register bits definitions */ +#define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */ +#define GRSTATRP_DPID BITS(15, 16) /*!< data PID */ +#define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */ +#define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */ +#define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */ + +/* global receive FIFO length register bits definitions */ +#define GRFLEN_RXFD BITS(0, 15) /*!< rx FIFO depth */ + +/* host non-periodic transmit FIFO length register bits definitions */ +#define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic Tx FIFO depth */ +#define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic Tx RAM start address */ + +/* USB IN endpoint 0 transmit FIFO length register bits definitions */ +#define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ +#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ + +/* host non-periodic transmit FIFO/queue status register bits definitions */ +#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */ +#define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic Tx request queue space */ +#define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic Tx FIFO space */ +#define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number*/ +#define HNPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ +#define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ +#define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */ + +/* global core configuration register bits definitions */ +#define GCCFG_VBUSIG BIT(21) /*!< vbus ignored */ +#define GCCFG_SOFOEN BIT(20) /*!< SOF output enable */ +#define GCCFG_VBUSBCEN BIT(19) /*!< the VBUS B-device comparer enable */ +#define GCCFG_VBUSACEN BIT(18) /*!< the VBUS A-device comparer enable */ +#define GCCFG_PWRON BIT(16) /*!< power on */ + +/* core ID register bits definitions */ +#define CID_CID BITS(0, 31) /*!< core ID */ + +/* host periodic transmit FIFO length register bits definitions */ +#define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic Tx FIFO depth */ +#define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic Tx RAM start address */ + +/* device IN endpoint transmit FIFO length register bits definitions */ +#define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */ +#define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */ + +/* host control register bits definitions */ +#define HCTL_SPDFSLS BIT(2) /*!< speed limited to FS and LS */ +#define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */ + +/* host frame interval register bits definitions */ +#define HFT_FRI BITS(0, 15) /*!< frame interval */ + +/* host frame information remaining register bits definitions */ +#define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */ +#define HFINFR_FRNUM BITS(0, 15) /*!< frame number */ + +/* host periodic transmit FIFO/queue status register bits definitions */ +#define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic Tx request queue */ +#define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic Tx request queue space */ +#define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic Tx FIFO space */ +#define HPTFQSTAT_OEFRM BIT(31) /*!< odd/eveb frame */ +#define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ +#define HPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ +#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ +#define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ + +#define TFQSTAT_TXFS BITS(0, 15) +#define TFQSTAT_CNUM BITS(27, 30) + +/* host all channels interrupt register bits definitions */ +#define HACHINT_HACHINT BITS(0, 11) /*!< host all channel interrupts */ + +/* host all channels interrupt enable register bits definitions */ +#define HACHINTEN_CINTEN BITS(0, 11) /*!< channel interrupt enable */ + +/* host port control and status register bits definitions */ +#define HPCS_PS BITS(17, 18) /*!< port speed */ +#define HPCS_PP BIT(12) /*!< port power */ +#define HPCS_PLST BITS(10, 11) /*!< port line status */ +#define HPCS_PRST BIT(8) /*!< port reset */ +#define HPCS_PSP BIT(7) /*!< port suspend */ +#define HPCS_PREM BIT(6) /*!< port resume */ +#define HPCS_PEDC BIT(3) /*!< port enable/disable change */ +#define HPCS_PE BIT(2) /*!< port enable */ +#define HPCS_PCD BIT(1) /*!< port connect detected */ +#define HPCS_PCST BIT(0) /*!< port connect status */ + +/* host channel-x control register bits definitions */ +#define HCHCTL_CEN BIT(31) /*!< channel enable */ +#define HCHCTL_CDIS BIT(30) /*!< channel disable */ +#define HCHCTL_ODDFRM BIT(29) /*!< odd frame */ +#define HCHCTL_DAR BITS(22, 28) /*!< device address */ +#define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */ +#define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define HCHCTL_LSD BIT(17) /*!< low-speed device */ +#define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */ +#define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */ +#define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */ + +/* host channel-x split transaction register bits definitions */ +#define HCHSTCTL_SPLEN BIT(31) /*!< enable high-speed split transaction */ +#define HCHSTCTL_CSPLT BIT(16) /*!< complete-split enable */ +#define HCHSTCTL_ISOPCE BITS(14, 15) /*!< isochronous OUT payload continuation encoding */ +#define HCHSTCTL_HADDR BITS(7, 13) /*!< HUB address */ +#define HCHSTCTL_PADDR BITS(0, 6) /*!< port address */ + +/* host channel-x interrupt flag register bits definitions */ +#define HCHINTF_DTER BIT(10) /*!< data toggle error */ +#define HCHINTF_REQOVR BIT(9) /*!< request queue overrun */ +#define HCHINTF_BBER BIT(8) /*!< babble error */ +#define HCHINTF_USBER BIT(7) /*!< USB bus Error */ +#define HCHINTF_NYET BIT(6) /*!< NYET */ +#define HCHINTF_ACK BIT(5) /*!< ACK */ +#define HCHINTF_NAK BIT(4) /*!< NAK */ +#define HCHINTF_STALL BIT(3) /*!< STALL */ +#define HCHINTF_CH BIT(1) /*!< channel halted */ +#define HCHINTF_TF BIT(0) /*!< transfer finished */ + +/* host channel-x interrupt enable register bits definitions */ +#define HCHINTEN_DTERIE BIT(10) /*!< data toggle error interrupt enable */ +#define HCHINTEN_REQOVRIE BIT(9) /*!< request queue overrun interrupt enable */ +#define HCHINTEN_BBERIE BIT(8) /*!< babble error interrupt enable */ +#define HCHINTEN_USBERIE BIT(7) /*!< USB bus error interrupt enable */ +#define HCHINTEN_NYETIE BIT(6) /*!< NYET interrupt enable */ +#define HCHINTEN_ACKIE BIT(5) /*!< ACK interrupt enable */ +#define HCHINTEN_NAKIE BIT(4) /*!< NAK interrupt enable */ +#define HCHINTEN_STALLIE BIT(3) /*!< STALL interrupt enable */ +#define HCHINTEN_CHIE BIT(1) /*!< channel halted interrupt enable */ +#define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */ + +/* host channel-x transfer length register bits definitions */ +#define HCHLEN_PING BIT(31) /*!< PING token request */ +#define HCHLEN_DPID BITS(29, 30) /*!< data PID */ +#define HCHLEN_PCNT BITS(19, 28) /*!< packet count */ +#define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */ + +#define PORT_SPEED(x) (((uint32_t)(x) << 17) & HPCS_PS) /*!< Port speed */ + +#define PORT_SPEED_HIGH PORT_SPEED(0U) /*!< high speed */ +#define PORT_SPEED_FULL PORT_SPEED(1U) /*!< full speed */ +#define PORT_SPEED_LOW PORT_SPEED(2U) /*!< low speed */ + +#define PIPE_CTL_DAR(x) (((uint32_t)(x) << 22) & HCHCTL_DAR) /*!< device address */ +#define PIPE_CTL_EPTYPE(x) (((uint32_t)(x) << 18) & HCHCTL_EPTYPE) /*!< endpoint type */ +#define PIPE_CTL_EPNUM(x) (((uint32_t)(x) << 11) & HCHCTL_EPNUM) /*!< endpoint number */ +#define PIPE_CTL_EPDIR(x) (((uint32_t)(x) << 15) & HCHCTL_EPDIR) /*!< endpoint direction */ +#define PIPE_CTL_EPMPL(x) (((uint32_t)(x) << 0) & HCHCTL_MPL) /*!< maximum packet length */ +#define PIPE_CTL_LSD(x) (((uint32_t)(x) << 17) & HCHCTL_LSD) /*!< low-Speed device */ + +#define PIPE_XFER_PCNT(x) (((uint32_t)(x) << 19) & HCHLEN_PCNT) /*!< packet count */ +#define PIPE_XFER_DPID(x) (((uint32_t)(x) << 29) & HCHLEN_DPID) /*!< data PID */ + +#define PIPE_DPID_DATA0 PIPE_XFER_DPID(0) /*!< DATA0 */ +#define PIPE_DPID_DATA1 PIPE_XFER_DPID(2) /*!< DATA1 */ +#define PIPE_DPID_DATA2 PIPE_XFER_DPID(1) /*!< DATA2 */ +#define PIPE_DPID_SETUP PIPE_XFER_DPID(3) /*!< MDATA (non-control)/SETUP (control) */ + +extern const uint32_t PIPE_DPID[2]; + +/* device configuration registers bits definitions */ +#define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */ +#define DCFG_DAR BITS(4, 10) /*!< device address */ +#define DCFG_NZLSOH BIT(2) /*!< non-zero-length status OUT handshake */ +#define DCFG_DS BITS(0, 1) /*!< device speed */ + +/* device control registers bits definitions */ +#define DCTL_POIF BIT(11) /*!< power-on initialization finished */ +#define DCTL_CGONAK BIT(10) /*!< clear global OUT NAK */ +#define DCTL_SGONAK BIT(9) /*!< set global OUT NAK */ +#define DCTL_CGINAK BIT(8) /*!< clear global IN NAK */ +#define DCTL_SGINAK BIT(7) /*!< set global IN NAK */ +#define DCTL_GONS BIT(3) /*!< global OUT NAK status */ +#define DCTL_GINS BIT(2) /*!< global IN NAK status */ +#define DCTL_SD BIT(1) /*!< soft disconnect */ +#define DCTL_RWKUP BIT(0) /*!< remote wakeup */ + +/* device status registers bits definitions */ +#define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */ +#define DSTAT_ES BITS(1, 2) /*!< enumerated speed */ +#define DSTAT_SPST BIT(0) /*!< suspend status */ + +/* device IN endpoint common interrupt enable registers bits definitions */ +#define DIEPINTEN_NAKEN BIT(13) /*!< NAK handshake sent by USBFS interrupt enable bit */ +#define DIEPINTEN_TXFEEN BIT(7) /*!< transmit FIFO empty interrupt enable bit */ +#define DIEPINTEN_IEPNEEN BIT(6) /*!< IN endpoint NAK effective interrupt enable bit */ +#define DIEPINTEN_EPTXFUDEN BIT(4) /*!< endpoint Tx FIFO underrun interrupt enable bit */ +#define DIEPINTEN_CITOEN BIT(3) /*!< control In Timeout interrupt enable bit */ +#define DIEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ +#define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ + +/* device OUT endpoint common interrupt enable registers bits definitions */ +#define DOEPINTEN_NYETEN BIT(14) /*!< NYET handshake is sent interrupt enable bit */ +#define DOEPINTEN_BTBSTPEN BIT(6) /*!< back-to-back SETUP packets interrupt enable bit */ +#define DOEPINTEN_EPRXFOVREN BIT(4) /*!< endpoint Rx FIFO overrun interrupt enable bit */ +#define DOEPINTEN_STPFEN BIT(3) /*!< SETUP phase finished interrupt enable bit */ +#define DOEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ +#define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ + +/* device all endpoints interrupt registers bits definitions */ +#define DAEPINT_OEPITB BITS(16, 21) /*!< device all OUT endpoint interrupt bits */ +#define DAEPINT_IEPITB BITS(0, 5) /*!< device all IN endpoint interrupt bits */ + +/* device all endpoints interrupt enable registers bits definitions */ +#define DAEPINTEN_OEPIE BITS(16, 21) /*!< OUT endpoint interrupt enable */ +#define DAEPINTEN_IEPIE BITS(0, 3) /*!< IN endpoint interrupt enable */ + +/* device Vbus discharge time registers bits definitions */ +#define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */ + +/* device Vbus pulsing time registers bits definitions */ +#define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */ + +/* device IN endpoint FIFO empty interrupt enable register bits definitions */ +#define DIEPFEINTEN_IEPTXFEIE BITS(0, 5) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ + +/* device endpoint 0 control register bits definitions */ +#define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */ +#define DEP0CTL_EPD BIT(30) /*!< endpoint disable */ +#define DEP0CTL_SNAK BIT(27) /*!< set NAK */ +#define DEP0CTL_CNAK BIT(26) /*!< clear NAK */ +#define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ +#define DEP0CTL_STALL BIT(21) /*!< STALL handshake */ +#define DOEP0CTL_SNOOP BIT(20) /*!< snoop mode */ +#define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define DEP0CTL_NAKS BIT(17) /*!< NAK status */ +#define DEP0CTL_EPACT BIT(15) /*!< endpoint active */ +#define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ + +/* device endpoint x control register bits definitions */ +#define DEPCTL_EPEN BIT(31) /*!< endpoint enable */ +#define DEPCTL_EPD BIT(30) /*!< endpoint disable */ +#define DEPCTL_SODDFRM BIT(29) /*!< set odd frame */ +#define DEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */ +#define DEPCTL_SEVNFRM BIT(28) /*!< set even frame */ +#define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ +#define DEPCTL_SNAK BIT(27) /*!< set NAK */ +#define DEPCTL_CNAK BIT(26) /*!< clear NAK */ +#define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ +#define DEPCTL_STALL BIT(21) /*!< STALL handshake */ +#define DOEPCTL_SNOOP BIT(20) /*!< snoop mode */ +#define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define DEPCTL_NAKS BIT(17) /*!< NAK status */ +#define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */ +#define DEPCTL_DPID BIT(16) /*!< endpoint data PID */ +#define DEPCTL_EPACT BIT(15) /*!< endpoint active */ +#define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ + +/* device IN endpoint-x interrupt flag register bits definitions */ +#define DIEPINTF_NAK BIT(13) /*!< NAK handshake sent by USBFS */ +#define DIEPINTF_TXFE BIT(7) /*!< transmit FIFO empty */ +#define DIEPINTF_IEPNE BIT(6) /*!< IN endpoint NAK effective */ +#define DIEPINTF_EPTXFUD BIT(4) /*!< endpoint Tx FIFO underrun */ +#define DIEPINTF_CITO BIT(3) /*!< control In Timeout interrupt */ +#define DIEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ +#define DIEPINTF_TF BIT(0) /*!< transfer finished */ + +/* device OUT endpoint-x interrupt flag register bits definitions */ +#define DOEPINTF_NYET BIT(14) /*!< NYET handshake is sent */ +#define DOEPINTF_BTBSTP BIT(6) /*!< back-to-back SETUP packets */ +#define DOEPINTF_EPRXFOVR BIT(4) /*!< endpoint Rx FIFO overrun */ +#define DOEPINTF_STPF BIT(3) /*!< SETUP phase finished */ +#define DOEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ +#define DOEPINTF_TF BIT(0) /*!< transfer finished */ + +/* device IN endpoint 0 transfer length register bits definitions */ +#define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */ +#define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ + +/* device OUT endpoint 0 transfer length register bits definitions */ +#define DOEP0LEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ +#define DOEP0LEN_PCNT BIT(19) /*!< packet count */ +#define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ + +/* device OUT endpoint-x transfer length register bits definitions */ +#define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */ +#define DOEPLEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ +#define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */ +#define DEPLEN_PCNT BITS(19, 28) /*!< packet count */ +#define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */ + +/* device IN endpoint-x transmit FIFO status register bits definitions */ +#define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< IN endpoint Tx FIFO space remaining */ + +/* USB power and clock registers bits definition */ +#define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */ +#define PWRCLKCTL_SUCLK BIT(0) /*!< stop the USB clock */ + +#define RSTAT_GOUT_NAK 1U /*!< global OUT NAK (triggers an interrupt) */ +#define RSTAT_DATA_UPDT 2U /*!< OUT data packet received */ +#define RSTAT_XFER_COMP 3U /*!< OUT transfer completed (triggers an interrupt) */ +#define RSTAT_SETUP_COMP 4U /*!< SETUP transaction completed (triggers an interrupt) */ +#define RSTAT_SETUP_UPDT 6U /*!< SETUP data packet received */ + +#define DSTAT_EM_HS_PHY_30MHZ_60MHZ 0U /*!< USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */ +#define DSTAT_EM_FS_PHY_30MHZ_60MHZ 1U /*!< USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */ +#define DSTAT_EM_LS_PHY_6MHZ 2U /*!< USB enumerate speed use low-speed PHY clock in 6MHz */ +#define DSTAT_EM_FS_PHY_48MHZ 3U /*!< USB enumerate speed use full-speed PHY clock in 48MHz */ + +#define DPID_DATA0 0U /*!< device endpoint data PID is DATA0 */ +#define DPID_DATA1 2U /*!< device endpoint data PID is DATA1 */ +#define DPID_DATA2 1U /*!< device endpoint data PID is DATA2 */ +#define DPID_MDATA 3U /*!< device endpoint data PID is MDATA */ + +#define DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11)) /*!< end of periodic frame time configuration */ + +#define FRAME_INTERVAL_80 DCFG_PFRI(0U) /*!< 80% of the frame time */ +#define FRAME_INTERVAL_85 DCFG_PFRI(1U) /*!< 85% of the frame time */ +#define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */ +#define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */ + +#define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0)) /*!< device speed configuration */ + +#define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U) /*!< device external PHY high speed */ +#define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U) /*!< device external PHY full speed */ +#define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U) /*!< device internal PHY full speed */ + +#define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0)) /*!< maximum packet length configuration */ + +#define EP0MPL_64 DEP0_MPL(0U) /*!< maximum packet length 64 bytes */ +#define EP0MPL_32 DEP0_MPL(1U) /*!< maximum packet length 32 bytes */ +#define EP0MPL_16 DEP0_MPL(2U) /*!< maximum packet length 16 bytes */ +#define EP0MPL_8 DEP0_MPL(3U) /*!< maximum packet length 8 bytes */ + +#define DOEP0_TLEN(regval) (DOEP0LEN_TLEN & ((regval) << 0)) /*!< transfer length */ +#define DOEP0_PCNT(regval) (DOEP0LEN_PCNT & ((regval) << 19)) /*!< packet count */ +#define DOEP0_STPCNT(regval) (DOEP0LEN_STPCNT & ((regval) << 29)) /*!< SETUP packet count */ + +#define USB_ULPI_PHY 1U /*!< ULPI interface external PHY */ +#define USB_EMBEDDED_PHY 2U /*!< embedded PHY */ + +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U + +#define HCTL_30_60MHZ 0U /*!< USB clock 30-60MHZ */ +#define HCTL_48MHZ 1U /*!< USB clock 48MHZ */ +#define HCTL_6MHZ 2U /*!< USB clock 6MHZ */ + +#define EP0_OUT ((uint8_t)0x00) /*!< endpoint out 0 */ +#define EP0_IN ((uint8_t)0x80) /*!< endpoint in 0 */ +#define EP1_OUT ((uint8_t)0x01) /*!< endpoint out 1 */ +#define EP1_IN ((uint8_t)0x81) /*!< endpoint in 1 */ +#define EP2_OUT ((uint8_t)0x02) /*!< endpoint out 2 */ +#define EP2_IN ((uint8_t)0x82) /*!< endpoint in 2 */ +#define EP3_OUT ((uint8_t)0x03) /*!< endpoint out 3 */ +#define EP3_IN ((uint8_t)0x83) /*!< endpoint in 3 */ + +#endif /* __DRV_USB_REGS_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usbd_int.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usbd_int.h new file mode 100644 index 00000000..f1935212 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usbd_int.h @@ -0,0 +1,45 @@ +/*! + \file drv_usbd_int.h + \brief USB device mode interrupt header file + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USBD_INT_H +#define __DRV_USBD_INT_H + +#include "drv_usb_core.h" +#include "drv_usb_dev.h" + +/* function declarations */ +/* USB device-mode interrupts global service routine handler */ +void usbd_isr (usb_core_driver *udev); + +#endif /* __DRV_USBD_INT_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usbh_int.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usbh_int.h new file mode 100644 index 00000000..54f47d16 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Include/drv_usbh_int.h @@ -0,0 +1,54 @@ +/*! + \file drv_usbh_int.h.h + \brief USB host mode interrupt management header file + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USBH_INT_H +#define __DRV_USBH_INT_H + +#include "drv_usb_host.h" +#include "usbh_core.h" + +typedef struct _usbh_ev_cb +{ + uint8_t (*connect) (usbh_host *uhost); + uint8_t (*disconnect) (usbh_host *uhost); + uint8_t (*SOF) (usbh_host *uhost); +} usbh_ev_cb; + +extern usbh_ev_cb *usbh_int_fop; + +/* function declarations */ +/* handle global host interrupt */ +uint32_t usbh_isr (usb_core_driver *udev); + +#endif /* __DRV_USBH_INT_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usb_core.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usb_core.c new file mode 100644 index 00000000..8e86d210 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usb_core.c @@ -0,0 +1,330 @@ +/*! + \file drv_usb_core.c + \brief USB core driver which can operate in host and device mode + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_core.h" +#include "drv_usb_hw.h" + +/* local function prototypes ('static') */ +static void usb_core_reset(usb_core_regs *usb_regs); + +/*! + \brief configure USB core basic + \param[in] usb_basic: pointer to USB capabilities + \param[in] usb_regs: USB core registers + \param[in] usb_core: USB core + \param[out] none + \retval operation status +*/ +usb_status usb_basic_init(usb_core_basic *usb_basic, + usb_core_regs *usb_regs, + usb_core_enum usb_core) +{ + /* configure USB default transfer mode as FIFO mode */ + usb_basic->transfer_mode = (uint8_t)USB_USE_FIFO; + + /* USB default speed is full-speed */ + usb_basic->core_speed = (uint8_t)USB_SPEED_FULL; + + usb_basic->core_enum = (uint8_t)usb_core; + + switch(usb_core) { + case USB_CORE_ENUM_FS: + usb_basic->base_reg = (uint32_t)USBFS_REG_BASE; + + /* set the host channel numbers */ + usb_basic->num_pipe = USBFS_MAX_CHANNEL_COUNT; + + /* set the device endpoint numbers */ + usb_basic->num_ep = USBFS_MAX_EP_COUNT; + + /* USBFS core use embedded physical layer */ + usb_basic->phy_itf = USB_EMBEDDED_PHY; + break; + + default: + return USB_FAIL; + } + + usb_basic->sof_enable = USB_SOF_OUTPUT; + usb_basic->low_power = USB_LOW_POWER; + + /* assign main registers address */ + *usb_regs = (usb_core_regs) { + .gr = (usb_gr*) (usb_basic->base_reg + USB_REG_OFFSET_CORE), + .hr = (usb_hr*) (usb_basic->base_reg + USB_REG_OFFSET_HOST), + .dr = (usb_dr*) (usb_basic->base_reg + USB_REG_OFFSET_DEV), + + .HPCS = (uint32_t*) (usb_basic->base_reg + USB_REG_OFFSET_PORT), + .PWRCLKCTL = (uint32_t*) (usb_basic->base_reg + USB_REG_OFFSET_PWRCLKCTL) + }; + + /* assign device endpoint registers address */ + for (uint8_t i = 0U; i < usb_basic->num_ep; i++) { + usb_regs->er_in[i] = (usb_erin *) \ + (usb_basic->base_reg + USB_REG_OFFSET_EP_IN + (i * USB_REG_OFFSET_EP)); + + usb_regs->er_out[i] = (usb_erout *)\ + (usb_basic->base_reg + USB_REG_OFFSET_EP_OUT + (i * USB_REG_OFFSET_EP)); + } + + /* assign host pipe registers address */ + for (uint8_t i = 0U; i < usb_basic->num_pipe; i++) { + usb_regs->pr[i] = (usb_pr *) \ + (usb_basic->base_reg + USB_REG_OFFSET_CH_INOUT + (i * USB_REG_OFFSET_CH)); + + usb_regs->DFIFO[i] = (uint32_t *) \ + (usb_basic->base_reg + USB_DATA_FIFO_OFFSET + (i * USB_DATA_FIFO_SIZE)); + } + + return USB_OK; +} + +/*! + \brief initializes the USB controller registers and + prepares the core device mode or host mode operation + \param[in] usb_basic: pointer to USB capabilities + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval operation status +*/ +usb_status usb_core_init (usb_core_basic usb_basic, usb_core_regs *usb_regs) +{ + if (USB_ULPI_PHY == usb_basic.phy_itf) { + usb_regs->gr->GCCFG &= ~GCCFG_PWRON; + + if (usb_basic.sof_enable) { + usb_regs->gr->GCCFG |= GCCFG_SOFOEN; + } + + /* initialize the ULPI interface */ + usb_regs->gr->GUSBCS &= ~(GUSBCS_EMBPHY | GUSBCS_ULPIEOI); + + /* soft reset the core */ + usb_core_reset (usb_regs); + } else { + usb_regs->gr->GUSBCS |= GUSBCS_EMBPHY; + + /* soft reset the core */ + usb_core_reset (usb_regs); + + /* active the transceiver and enable VBUS sensing */ + usb_regs->gr->GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN; + +#ifndef VBUS_SENSING_ENABLED + usb_regs->gr->GCCFG |= GCCFG_VBUSIG; +#endif /* VBUS_SENSING_ENABLED */ + + /* enable SOF output */ + if (usb_basic.sof_enable) { + usb_regs->gr->GCCFG |= GCCFG_SOFOEN; + } + + usb_mdelay(20U); + } + +#ifdef USE_OTG_MODE + + /* enable USB OTG features */ + usb_regs->gr->GUSBCS |= GUSBCS_HNPCEN | GUSBCS_SRPCEN; + + /* enable the USB wakeup and suspend interrupts */ + usb_regs->gr->GINTF = 0xBFFFFFFFU; + + usb_regs->gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE | \ + GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE; + +#endif /* USE_OTG_MODE */ + + return USB_OK; +} + +/*! + \brief write a packet into the Tx FIFO associated with the endpoint + \param[in] usb_regs: pointer to USB core registers + \param[in] src_buf: pointer to source buffer + \param[in] fifo_num: FIFO number which is in (0..3) + \param[in] byte_count: packet byte count + \param[out] none + \retval operation status +*/ +usb_status usb_txfifo_write (usb_core_regs *usb_regs, + uint8_t *src_buf, + uint8_t fifo_num, + uint16_t byte_count) +{ + uint32_t word_count = (byte_count + 3U) / 4U; + + __IO uint32_t *fifo = usb_regs->DFIFO[fifo_num]; + + while (word_count-- > 0U) { + *fifo = *((__packed uint32_t *)src_buf); + + src_buf += 4U; + } + + return USB_OK; +} + +/*! + \brief read a packet from the Rx FIFO associated with the endpoint + \param[in] usb_regs: pointer to USB core registers + \param[in] dest_buf: pointer to destination buffer + \param[in] byte_count: packet byte count + \param[out] none + \retval void type pointer +*/ +void *usb_rxfifo_read (usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count) +{ + uint32_t word_count = (byte_count + 3U) / 4U; + + __IO uint32_t *fifo = usb_regs->DFIFO[0]; + + while (word_count-- > 0U) { + *(__packed uint32_t *)dest_buf = *fifo; + + dest_buf += 4U; + } + + return ((void *)dest_buf); +} + +/*! + \brief flush a Tx FIFO or all Tx FIFOs + \param[in] usb_regs: pointer to USB core registers + \param[in] fifo_num: FIFO number which is in (0..3) + \param[out] none + \retval operation status +*/ +usb_status usb_txfifo_flush (usb_core_regs *usb_regs, uint8_t fifo_num) +{ + usb_regs->gr->GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF; + + /* wait for Tx FIFO flush bit is set */ + while (usb_regs->gr->GRSTCTL & GRSTCTL_TXFF) { + /* no operation */ + } + + /* wait for 3 PHY clocks*/ + usb_udelay(3U); + + return USB_OK; +} + +/*! + \brief flush the entire Rx FIFO + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval operation status +*/ +usb_status usb_rxfifo_flush (usb_core_regs *usb_regs) +{ + usb_regs->gr->GRSTCTL = GRSTCTL_RXFF; + + /* wait for Rx FIFO flush bit is set */ + while (usb_regs->gr->GRSTCTL & GRSTCTL_RXFF) { + /* no operation */ + } + + /* wait for 3 PHY clocks */ + usb_udelay(3U); + + return USB_OK; +} + +/*! + \brief set endpoint or channel TX FIFO size + \param[in] usb_regs: pointer to USB core registers + \param[in] fifo: TX FIFO number + \param[in] size: assigned TX FIFO size + \param[out] none + \retval none +*/ +void usb_set_txfifo(usb_core_regs *usb_regs, uint8_t fifo, uint16_t size) +{ + uint32_t tx_offset; + + tx_offset = usb_regs->gr->GRFLEN; + + if(0U == fifo) { + usb_regs->gr->DIEP0TFLEN_HNPTFLEN = ((uint32_t)size << 16) | tx_offset; + } else { + tx_offset += (usb_regs->gr->DIEP0TFLEN_HNPTFLEN) >> 16; + + for (uint8_t i = 0U; i < (fifo - 1U); i++) { + tx_offset += (usb_regs->gr->DIEPTFLEN[i] >> 16); + } + + /* multiply Tx_Size by 2 to get higher performance */ + usb_regs->gr->DIEPTFLEN[fifo - 1U] = ((uint32_t)size << 16) | tx_offset; + } +} + +/*! + \brief set USB current mode + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval none +*/ +void usb_curmode_set(usb_core_regs *usb_regs, uint8_t mode) +{ + usb_regs->gr->GUSBCS &= ~(GUSBCS_FDM | GUSBCS_FHM); + + if (DEVICE_MODE == mode) { + usb_regs->gr->GUSBCS |= GUSBCS_FDM; + } else if (HOST_MODE == mode) { + usb_regs->gr->GUSBCS |= GUSBCS_FHM; + } else { + /* OTG mode and other mode can not be here! */ + } +} + +/*! + \brief configure USB core to soft reset + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval none +*/ +static void usb_core_reset (usb_core_regs *usb_regs) +{ + /* enable core soft reset */ + usb_regs->gr->GRSTCTL |= GRSTCTL_CSRST; + + /* wait for the core to be soft reset */ + while (usb_regs->gr->GRSTCTL & GRSTCTL_CSRST) { + /* no operation */ + } + + /* wait for additional 3 PHY clocks */ + usb_udelay(3U); +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usb_dev.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usb_dev.c new file mode 100644 index 00000000..39d4b9b5 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usb_dev.c @@ -0,0 +1,595 @@ +/*! + \file drv_usb_dev.c + \brief USB device mode low level driver + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "drv_usb_core.h" +#include "drv_usb_dev.h" + +/* endpoint 0 max packet length */ +static const uint8_t EP0_MAXLEN[4] = { + [DSTAT_EM_HS_PHY_30MHZ_60MHZ] = EP0MPL_64, + [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = EP0MPL_64, + [DSTAT_EM_FS_PHY_48MHZ] = EP0MPL_64, + [DSTAT_EM_LS_PHY_6MHZ] = EP0MPL_8 +}; + +#ifdef USB_FS_CORE + +/* USB endpoint Tx FIFO size */ +static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] = +{ + (uint16_t)TX0_FIFO_FS_SIZE, + (uint16_t)TX1_FIFO_FS_SIZE, + (uint16_t)TX2_FIFO_FS_SIZE, + (uint16_t)TX3_FIFO_FS_SIZE +}; + +#endif /* USBFS_CORE */ + +/*! + \brief initialize USB core registers for device mode + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +usb_status usb_devcore_init (usb_core_driver *udev) +{ + uint8_t i; + + /* restart the PHY clock (maybe don't need to...) */ + *udev->regs.PWRCLKCTL = 0U; + + /* configure periodic frame interval to default value */ + udev->regs.dr->DCFG &= ~DCFG_EOPFT; + udev->regs.dr->DCFG |= FRAME_INTERVAL_80; + + udev->regs.dr->DCFG &= ~DCFG_DS; + +#ifdef USB_FS_CORE + if (udev->bp.core_enum == (uint8_t)USB_CORE_ENUM_FS) { + /* set full-speed PHY */ + udev->regs.dr->DCFG |= USB_SPEED_INP_FULL; + + /* set Rx FIFO size */ + usb_set_rxfifo(&udev->regs, RX_FIFO_FS_SIZE); + + /* set endpoint 0 to 3's Tx FIFO length and RAM address */ + for(i = 0U; i < USBFS_MAX_EP_COUNT; i++) { + usb_set_txfifo(&udev->regs, i, USBFS_TX_FIFO_SIZE[i]); + } + } +#endif /* USB_FS_CORE */ + + /* make sure all FIFOs are flushed */ + + /* flush all Tx FIFOs */ + (void)usb_txfifo_flush (&udev->regs, 0x10U); + + /* flush entire Rx FIFO */ + (void)usb_rxfifo_flush (&udev->regs); + + /* clear all pending device interrupts */ + udev->regs.dr->DIEPINTEN = 0U; + udev->regs.dr->DOEPINTEN = 0U; + udev->regs.dr->DAEPINT = 0xFFFFFFFFU; + udev->regs.dr->DAEPINTEN = 0U; + + /* configure all IN/OUT endpoints */ + for (i = 0U; i < udev->bp.num_ep; i++) { + if (udev->regs.er_in[i]->DIEPCTL & DEPCTL_EPEN) { + udev->regs.er_in[i]->DIEPCTL |= DEPCTL_EPD | DEPCTL_SNAK; + } else { + udev->regs.er_in[i]->DIEPCTL = 0U; + } + + /* set IN endpoint transfer length to 0 */ + udev->regs.er_in[i]->DIEPLEN = 0U; + + /* clear all pending IN endpoint interrupts */ + udev->regs.er_in[i]->DIEPINTF = 0xFFU; + + if (udev->regs.er_out[i]->DOEPCTL & DEPCTL_EPEN) { + udev->regs.er_out[i]->DOEPCTL |= DEPCTL_EPD | DEPCTL_SNAK; + } else { + udev->regs.er_out[i]->DOEPCTL = 0U; + } + + /* set OUT endpoint transfer length to 0 */ + udev->regs.er_out[i]->DOEPLEN = 0U; + + /* clear all pending OUT endpoint interrupts */ + udev->regs.er_out[i]->DOEPINTF = 0xFFU; + } + + udev->regs.dr->DIEPINTEN |= DIEPINTEN_EPTXFUDEN; + + (void)usb_devint_enable (udev); + + return USB_OK; +} + +/*! + \brief enable the USB device mode interrupts + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +usb_status usb_devint_enable (usb_core_driver *udev) +{ + /* clear any pending USB OTG interrupts */ + udev->regs.gr->GOTGINTF = 0xFFFFFFFFU; + + /* clear any pending interrupts */ + udev->regs.gr->GINTF = 0xBFFFFFFFU; + + /* enable the USB wakeup and suspend interrupts */ + udev->regs.gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE; + + /* enable device_mode-related interrupts */ + if ((uint8_t)USB_USE_FIFO == udev->bp.transfer_mode) { + udev->regs.gr->GINTEN |= GINTEN_RXFNEIE; + } + + udev->regs.gr->GINTEN |= GINTEN_RSTIE | GINTEN_ENUMFIE | GINTEN_IEPIE | \ + GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_ISOONCIE | GINTEN_ISOINCIE; + +#ifdef VBUS_SENSING_ENABLED + udev->regs.gr->GINTEN |= GINTEN_SESIE | GINTEN_OTGIE; +#endif /* VBUS_SENSING_ENABLED */ + + return USB_OK; +} + +/*! + \brief active the USB endpoint0 transaction + \param[in] udev: pointer to USB device + \param[in] transc: the USB endpoint0 transaction + \param[out] none + \retval operation status +*/ +usb_status usb_transc0_active (usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + uint32_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES; + + /* get the endpoint number */ + uint8_t ep_num = transc->ep_addr.num; + + if (ep_num) { + /* not endpoint 0 */ + return USB_FAIL; + } + + if (transc->ep_addr.dir) { + reg_addr = &udev->regs.er_in[0]->DIEPCTL; + } else { + reg_addr = &udev->regs.er_out[0]->DOEPCTL; + } + + /* endpoint 0 is activated after USB clock is enabled */ + *reg_addr &= ~(DEPCTL_MPL | DEPCTL_EPTYPE | DIEPCTL_TXFNUM); + + /* set endpoint 0 maximum packet length */ + *reg_addr |= EP0_MAXLEN[enum_speed]; + + /* activate endpoint */ + *reg_addr |= ((uint32_t)transc->ep_type << 18U) | ((uint32_t)ep_num << 22U) | DEPCTL_SD0PID | DEPCTL_EPACT; + + return USB_OK; +} + +/*! + \brief active the USB transaction + \param[in] udev: pointer to USB device + \param[in] transc: the USB transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_active (usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + uint32_t epinten = 0U; + uint32_t enum_speed = udev->regs.dr->DSTAT & DSTAT_ES; + + /* get the endpoint number */ + uint8_t ep_num = transc->ep_addr.num; + + /* enable endpoint interrupt number */ + if (transc->ep_addr.dir) { + reg_addr = &udev->regs.er_in[ep_num]->DIEPCTL; + + epinten = 1U << ep_num; + } else { + reg_addr = &udev->regs.er_out[ep_num]->DOEPCTL; + + epinten = 1U << (16U + ep_num); + } + + /* if the endpoint is not active, need change the endpoint control register */ + if (!(*reg_addr & DEPCTL_EPACT)) { + *reg_addr &= ~(DEPCTL_MPL | DEPCTL_EPTYPE | DIEPCTL_TXFNUM); + + /* set endpoint maximum packet length */ + if (0U == ep_num) { + *reg_addr |= EP0_MAXLEN[enum_speed]; + } else { + *reg_addr |= transc->max_len; + } + + /* activate endpoint */ + *reg_addr |= ((uint32_t)transc->ep_type << 18U) | ((uint32_t)ep_num << 22U) | DEPCTL_SD0PID | DEPCTL_EPACT; + } + + /* enable the interrupts for this endpoint */ + udev->regs.dr->DAEPINTEN |= epinten; + + return USB_OK; +} + +/*! + \brief deactivate the USB transaction + \param[in] udev: pointer to USB device + \param[in] transc: the USB transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_deactivate(usb_core_driver *udev, usb_transc *transc) +{ + uint32_t epinten = 0U; + + uint8_t ep_num = transc->ep_addr.num; + + /* disable endpoint interrupt number */ + if (transc->ep_addr.dir) { + epinten = 1U << ep_num; + + udev->regs.er_in[ep_num]->DIEPCTL &= ~DEPCTL_EPACT; + } else { + epinten = 1U << (ep_num + 16U); + + udev->regs.er_out[ep_num]->DOEPCTL &= ~DEPCTL_EPACT; + } + + /* disable the interrupts for this endpoint */ + udev->regs.dr->DAEPINTEN &= ~epinten; + + return USB_OK; +} + +/*! + \brief configure USB transaction to start IN transfer + \param[in] udev: pointer to USB device + \param[in] transc: the USB IN transaction + \param[out] none + \retval operation status +*/ +usb_status usb_transc_inxfer (usb_core_driver *udev, usb_transc *transc) +{ + usb_status status = USB_OK; + + uint8_t ep_num = transc->ep_addr.num; + + __IO uint32_t epctl = udev->regs.er_in[ep_num]->DIEPCTL; + __IO uint32_t eplen = udev->regs.er_in[ep_num]->DIEPLEN; + + eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT); + + /* zero length packet or endpoint 0 */ + if (0U == transc->xfer_len) { + /* set transfer packet count to 1 */ + eplen |= 1U << 19U; + } else { + /* set transfer packet count */ + if (0U == ep_num) { + transc->xfer_len = USB_MIN(transc->xfer_len, transc->max_len); + + eplen |= 1U << 19U; + } else { + eplen |= (((transc->xfer_len - 1U) + transc->max_len) / transc->max_len) << 19U; + } + + /* set endpoint transfer length */ + eplen |= transc->xfer_len; + + if (transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) { + eplen |= DIEPLEN_MCNT & (1U << 29U); + } + } + + udev->regs.er_in[ep_num]->DIEPLEN = eplen; + + if (transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) { + if (((udev->regs.dr->DSTAT & DSTAT_FNRSOF) >> 8U) & 0x01U) { + epctl |= DEPCTL_SEVNFRM; + } else { + epctl |= DEPCTL_SODDFRM; + } + } + + /* enable the endpoint and clear the NAK */ + epctl |= DEPCTL_CNAK | DEPCTL_EPEN; + + udev->regs.er_in[ep_num]->DIEPCTL = epctl; + + if ((uint8_t)USB_USE_FIFO == udev->bp.transfer_mode) { + if (transc->ep_type != (uint8_t)USB_EPTYPE_ISOC) { + /* enable the Tx FIFO empty interrupt for this endpoint */ + if (transc->xfer_len > 0U) { + udev->regs.dr->DIEPFEINTEN |= 1U << ep_num; + } + } else { + (void)usb_txfifo_write (&udev->regs, transc->xfer_buf, ep_num, (uint16_t)transc->xfer_len); + } + } + + return status; +} + +/*! + \brief configure USB transaction to start OUT transfer + \param[in] udev: pointer to USB device + \param[in] transc: the USB OUT transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_outxfer (usb_core_driver *udev, usb_transc *transc) +{ + usb_status status = USB_OK; + + uint8_t ep_num = transc->ep_addr.num; + + uint32_t epctl = udev->regs.er_out[ep_num]->DOEPCTL; + uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN; + + eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT); + + /* zero length packet or endpoint 0 */ + if ((0U == transc->xfer_len) || (0U == ep_num)) { + /* set the transfer length to max packet size */ + eplen |= transc->max_len; + + /* set the transfer packet count to 1 */ + eplen |= 1U << 19U; + } else { + /* configure the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + uint32_t packet_count = (transc->xfer_len + transc->max_len - 1U) / transc->max_len; + + eplen |= packet_count << 19U; + eplen |= packet_count * transc->max_len; + } + + udev->regs.er_out[ep_num]->DOEPLEN = eplen; + + if (transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) { + if (transc->frame_num) { + epctl |= DEPCTL_SD1PID; + } else { + epctl |= DEPCTL_SD0PID; + } + } + + /* enable the endpoint and clear the NAK */ + epctl |= DEPCTL_EPEN | DEPCTL_CNAK; + + udev->regs.er_out[ep_num]->DOEPCTL = epctl; + + return status; +} + +/*! + \brief set the USB transaction STALL status + \param[in] udev: pointer to USB device + \param[in] transc: the USB transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_stall (usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + uint8_t ep_num = transc->ep_addr.num; + + if (transc->ep_addr.dir) { + reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL); + + /* set the endpoint disable bit */ + if (*reg_addr & DEPCTL_EPEN) { + *reg_addr |= DEPCTL_EPD; + } + } else { + /* set the endpoint stall bit */ + reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL); + } + + /* set the endpoint stall bit */ + *reg_addr |= DEPCTL_STALL; + + return USB_OK; +} + +/*! + \brief clear the USB transaction STALL status + \param[in] udev: pointer to USB device + \param[in] transc: the USB transaction + \param[out] none + \retval operation status +*/ +usb_status usb_transc_clrstall(usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + uint8_t ep_num = transc->ep_addr.num; + + if (transc->ep_addr.dir) { + reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL); + } else { + reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL); + } + + /* clear the endpoint stall bits */ + *reg_addr &= ~DEPCTL_STALL; + + /* reset data PID of the periodic endpoints */ + if ((transc->ep_type == (uint8_t)USB_EPTYPE_INTR) || (transc->ep_type == (uint8_t)USB_EPTYPE_BULK)) { + *reg_addr |= DEPCTL_SD0PID; + } + + return USB_OK; +} + +/*! + \brief read device IN endpoint interrupt flag register + \param[in] udev: pointer to USB device + \param[in] ep_num: endpoint number + \param[out] none + \retval interrupt value +*/ +uint32_t usb_iepintr_read (usb_core_driver *udev, uint8_t ep_num) +{ + uint32_t value = 0U, fifoemptymask, commonintmask; + + commonintmask = udev->regs.dr->DIEPINTEN; + fifoemptymask = udev->regs.dr->DIEPFEINTEN; + + /* check FIFO empty interrupt enable bit */ + commonintmask |= ((fifoemptymask >> ep_num) & 0x1U) << 7; + + value = udev->regs.er_in[ep_num]->DIEPINTF & commonintmask; + + return value; +} + +/*! + \brief configures OUT endpoint 0 to receive SETUP packets + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_ctlep_startout (usb_core_driver *udev) +{ + /* set OUT endpoint 0 receive length to 24 bytes, 1 packet and 3 setup packets */ + udev->regs.er_out[0]->DOEPLEN = DOEP0_TLEN(8U * 3U) | DOEP0_PCNT(1U) | DOEP0_STPCNT(3U); +} + +/*! + \brief active remote wakeup signaling + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_rwkup_active (usb_core_driver *udev) +{ + if (udev->dev.pm.dev_remote_wakeup) { + if (udev->regs.dr->DSTAT & DSTAT_SPST) { + if (udev->bp.low_power) { + /* ungate USB core clock */ + *udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK); + } + + /* active remote wakeup signaling */ + udev->regs.dr->DCTL |= DCTL_RWKUP; + + usb_mdelay(5U); + + udev->regs.dr->DCTL &= ~DCTL_RWKUP; + } + } +} + +/*! + \brief active USB core clock + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_clock_active (usb_core_driver *udev) +{ + if (udev->bp.low_power) { + if (udev->regs.dr->DSTAT & DSTAT_SPST) { + /* ungate USB Core clock */ + *udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK); + } + } +} + +/*! + \brief USB device suspend + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_dev_suspend (usb_core_driver *udev) +{ + __IO uint32_t devstat = udev->regs.dr->DSTAT; + + if ((udev->bp.low_power) && (devstat & DSTAT_SPST)) { + /* switch-off the USB clocks */ + *udev->regs.PWRCLKCTL |= PWRCLKCTL_SHCLK; + + /* enter DEEP_SLEEP mode with LDO in low power mode */ + pmu_to_deepsleepmode (PMU_LDO_LOWPOWER, WFI_CMD); + } +} + +/*! + \brief stop the device and clean up FIFOs + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_dev_stop (usb_core_driver *udev) +{ + uint32_t i; + + udev->dev.cur_status = 1U; + + /* clear all interrupt flag and enable bits */ + for (i = 0U; i < udev->bp.num_ep; i++) { + udev->regs.er_in[i]->DIEPINTF = 0xFFU; + udev->regs.er_out[i]->DOEPINTF = 0xFFU; + } + + udev->regs.dr->DIEPINTEN = 0U; + udev->regs.dr->DOEPINTEN = 0U; + udev->regs.dr->DAEPINTEN = 0U; + udev->regs.dr->DAEPINT = 0xFFFFFFFFU; + + /* flush the FIFO */ + (void)usb_rxfifo_flush (&udev->regs); + (void)usb_txfifo_flush (&udev->regs, 0x10U); +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usb_host.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usb_host.c new file mode 100644 index 00000000..30333532 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usb_host.c @@ -0,0 +1,446 @@ +/*! + \file drv_usb_host.c + \brief USB host mode low level driver + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "drv_usb_core.h" +#include "drv_usb_host.h" + +const uint32_t PIPE_DPID[2] = { + PIPE_DPID_DATA0, + PIPE_DPID_DATA1 +}; + +/*! + \brief initializes USB core for host mode + \param[in] udev: pointer to selected USB host + \param[out] none + \retval operation status +*/ +usb_status usb_host_init (usb_core_driver *udev) +{ + uint32_t i = 0U, inten = 0U; + + uint32_t nptxfifolen = 0U; + uint32_t ptxfifolen = 0U; + + /* restart the PHY Clock */ + *udev->regs.PWRCLKCTL = 0U; + + /* configure USB clock of PHY */ + usb_phyclock_config (udev, HCTL_48MHZ); + + /* support FS/LS only */ + udev->regs.hr->HCTL &= ~HCTL_SPDFSLS; + + /* configure data FIFOs size */ +#ifdef USB_FS_CORE + if (USB_CORE_ENUM_FS == udev->bp.core_enum) { + /* set Rx FIFO size */ + udev->regs.gr->GRFLEN = USB_RX_FIFO_FS_SIZE; + + /* set non-periodic Tx FIFO size and address */ + nptxfifolen |= USB_RX_FIFO_FS_SIZE; + nptxfifolen |= USB_HTX_NPFIFO_FS_SIZE << 16U; + udev->regs.gr->DIEP0TFLEN_HNPTFLEN = nptxfifolen; + + /* set periodic Tx FIFO size and address */ + ptxfifolen |= USB_RX_FIFO_FS_SIZE + USB_HTX_NPFIFO_FS_SIZE; + ptxfifolen |= USB_HTX_PFIFO_FS_SIZE << 16U; + udev->regs.gr->HPTFLEN = ptxfifolen; + } +#endif /* USB_FS_CORE */ + +#ifdef USE_OTG_MODE + + /* clear host set HNP enable in the usb_otg control register */ + udev->regs.gr->GOTGCS &= ~GOTGCS_HHNPEN; + +#endif /* USE_OTG_MODE */ + + /* make sure the FIFOs are flushed */ + + /* flush all Tx FIFOs in device or host mode */ + usb_txfifo_flush (&udev->regs, 0x10U); + + /* flush the entire Rx FIFO */ + usb_rxfifo_flush (&udev->regs); + + /* disable all interrupts */ + udev->regs.gr->GINTEN = 0U; + + /* clear any pending USB OTG interrupts */ + udev->regs.gr->GOTGINTF = 0xFFFFFFFFU; + + /* enable the USB wakeup and suspend interrupts */ + udev->regs.gr->GINTF = 0xBFFFFFFFU; + + /* clear all pending host channel interrupts */ + for (i = 0U; i < udev->bp.num_pipe; i++) { + udev->regs.pr[i]->HCHINTF = 0xFFFFFFFFU; + udev->regs.pr[i]->HCHINTEN = 0U; + } + +#ifndef USE_OTG_MODE + usb_portvbus_switch (udev, 1U); +#endif /* USE_OTG_MODE */ + + udev->regs.gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE; + + /* enable host_mode-related interrupts */ + if (USB_USE_FIFO == udev->bp.transfer_mode) { + inten = GINTEN_RXFNEIE; + } + + inten |= GINTEN_SESIE | GINTEN_HPIE | GINTEN_HCIE | GINTEN_ISOINCIE; + + udev->regs.gr->GINTEN |= inten; + + inten = GINTEN_DISCIE | GINTEN_SOFIE; + + udev->regs.gr->GINTEN &= ~inten; + + return USB_OK; +} + +/*! + \brief control the VBUS to power + \param[in] udev: pointer to selected usb host + \param[in] state: VBUS state + \param[out] none + \retval none +*/ +void usb_portvbus_switch (usb_core_driver *udev, uint8_t state) +{ + uint32_t port = 0U; + + /* enable or disable the external charge pump */ + usb_vbus_drive (state); + + /* turn on the host port power. */ + port = usb_port_read (udev); + + if (!(port & HPCS_PP) && (1U == state)) { + port |= HPCS_PP; + } + + if ((port & HPCS_PP) && (0U == state)) { + port &= ~HPCS_PP; + } + + *udev->regs.HPCS = port; + + usb_mdelay (200U); +} + +/*! + \brief reset host port + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +uint32_t usb_port_reset (usb_core_driver *udev) +{ + __IO uint32_t port = usb_port_read (udev); + + *udev->regs.HPCS = port | HPCS_PRST; + + usb_mdelay(20U); /* see note */ + + *udev->regs.HPCS = port & ~HPCS_PRST; + + usb_mdelay(20U); + + return 1U; +} + +/*! + \brief initialize host pipe + \param[in] udev: pointer to USB device + \param[in] pipe_num: host pipe number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status usb_pipe_init (usb_core_driver *udev, uint8_t pipe_num) +{ + usb_status status = USB_OK; + + __IO uint32_t pp_ctl = 0U; + __IO uint32_t pp_inten = HCHINTEN_TFIE; + + usb_pipe *pp = &udev->host.pipe[pipe_num]; + + /* clear old interrupt conditions for this host channel */ + udev->regs.pr[pipe_num]->HCHINTF = 0xFFFFFFFFU; + + if (pp->ep.dir) { + pp_inten |= HCHINTEN_BBERIE; + } + + /* enable channel interrupts required for this transfer */ + switch (pp->ep.type) { + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + pp_inten |= HCHINTEN_STALLIE | HCHINTEN_USBERIE \ + | HCHINTEN_DTERIE | HCHINTEN_NAKIE; + + if (!pp->ep.dir) { + if (PORT_SPEED_HIGH == pp->dev_speed) { + pp_inten |= HCHINTEN_NYETIE; + pp_inten |= HCHINTEN_ACKIE; + } + } + break; + + case USB_EPTYPE_INTR: + pp_inten |= HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE \ + | HCHINTEN_NAKIE | HCHINTEN_REQOVRIE; + break; + + case USB_EPTYPE_ISOC: + pp_inten |= HCHINTEN_REQOVRIE | HCHINTEN_ACKIE; + + if (pp->ep.dir) { + pp_inten |= HCHINTEN_USBERIE; + } + break; + + default: + break; + } + + udev->regs.pr[pipe_num]->HCHINTEN = pp_inten; + + /* enable the top level host channel interrupt */ + udev->regs.hr->HACHINTEN |= 1U << pipe_num; + + /* make sure host channel interrupts are enabled */ + udev->regs.gr->GINTEN |= GINTEN_HCIE; + + /* program the host channel control register */ + pp_ctl |= PIPE_CTL_DAR(pp->dev_addr); + pp_ctl |= PIPE_CTL_EPNUM(pp->ep.num); + pp_ctl |= PIPE_CTL_EPDIR(pp->ep.dir); + pp_ctl |= PIPE_CTL_EPTYPE(pp->ep.type); + pp_ctl |= PIPE_CTL_LSD(pp->dev_speed == PORT_SPEED_LOW); + + pp_ctl |= pp->ep.mps; + pp_ctl |= ((uint32_t)(pp->ep.type == USB_EPTYPE_INTR) << 29U) & HCHCTL_ODDFRM; + + udev->regs.pr[pipe_num]->HCHCTL = pp_ctl; + + return status; +} + +/*! + \brief prepare host channel for transferring packets + \param[in] udev: pointer to USB device + \param[in] pipe_num: host pipe number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status usb_pipe_xfer (usb_core_driver *udev, uint8_t pipe_num) +{ + usb_status status = USB_OK; + + uint16_t dword_len = 0U; + uint16_t packet_count = 0U; + + __IO uint32_t pp_ctl = 0U; + + usb_pipe *pp = &udev->host.pipe[pipe_num]; + + uint16_t max_packet_len = pp->ep.mps; + + /* compute the expected number of packets associated to the transfer */ + if (pp->xfer_len > 0U) { + packet_count = (uint16_t)((pp->xfer_len + max_packet_len - 1U) / max_packet_len); + + if (packet_count > HC_MAX_PACKET_COUNT) { + packet_count = HC_MAX_PACKET_COUNT; + pp->xfer_len = (uint16_t)(packet_count * max_packet_len); + } + } else { + packet_count = 1U; + } + + if (pp->ep.dir) { + pp->xfer_len = (uint16_t)(packet_count * max_packet_len); + } + + /* initialize the host channel transfer information */ + udev->regs.pr[pipe_num]->HCHLEN = pp->xfer_len | pp->DPID | PIPE_XFER_PCNT(packet_count); + + pp_ctl = udev->regs.pr[pipe_num]->HCHCTL; + + if (usb_frame_even(udev)) { + pp_ctl |= HCHCTL_ODDFRM; + } else { + pp_ctl &= ~HCHCTL_ODDFRM; + } + + /* set host channel enabled */ + pp_ctl |= HCHCTL_CEN; + pp_ctl &= ~HCHCTL_CDIS; + + udev->regs.pr[pipe_num]->HCHCTL = pp_ctl; + + if (USB_USE_FIFO == udev->bp.transfer_mode) { + if ((0U == pp->ep.dir) && (pp->xfer_len > 0U)) { + switch (pp->ep.type) { + /* non-periodic transfer */ + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + dword_len = (uint16_t)((pp->xfer_len + 3U) / 4U); + + /* check if there is enough space in FIFO space */ + if (dword_len > (udev->regs.gr->HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { + /* need to process data in nptxfempty interrupt */ + udev->regs.gr->GINTEN |= GINTEN_NPTXFEIE; + } + break; + + /* periodic transfer */ + case USB_EPTYPE_INTR: + case USB_EPTYPE_ISOC: + dword_len = (uint16_t)((pp->xfer_len + 3U) / 4U); + + /* check if there is enough space in fifo space */ + if (dword_len > (udev->regs.hr->HPTFQSTAT & HPTFQSTAT_PTXFS)) { + /* need to process data in ptxfempty interrupt */ + udev->regs.gr->GINTEN |= GINTEN_PTXFEIE; + } + break; + + default: + break; + } + + /* write packet into the Tx fifo. */ + usb_txfifo_write (&udev->regs, pp->xfer_buf, pipe_num, (uint16_t)pp->xfer_len); + } + } + + return status; +} + +/*! + \brief halt pipe + \param[in] udev: pointer to USB device + \param[in] pipe_num: host pipe number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status usb_pipe_halt (usb_core_driver *udev, uint8_t pipe_num) +{ + __IO uint32_t pp_ctl = udev->regs.pr[pipe_num]->HCHCTL; + + uint8_t ep_type = (uint8_t)((pp_ctl & HCHCTL_EPTYPE) >> 18U); + + pp_ctl |= HCHCTL_CEN | HCHCTL_CDIS; + + switch (ep_type) { + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + if (0U == (udev->regs.gr->HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { + pp_ctl &= ~HCHCTL_CEN; + } + break; + + case USB_EPTYPE_INTR: + case USB_EPTYPE_ISOC: + if (0U == (udev->regs.hr->HPTFQSTAT & HPTFQSTAT_PTXFS)) { + pp_ctl &= ~HCHCTL_CEN; + } + break; + + default: + break; + } + + udev->regs.pr[pipe_num]->HCHCTL = pp_ctl; + + return USB_OK; +} + +/*! + \brief configure host pipe to do ping operation + \param[in] udev: pointer to USB device + \param[in] pipe_num: host pipe number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status usb_pipe_ping (usb_core_driver *udev, uint8_t pipe_num) +{ + uint32_t pp_ctl = 0U; + + udev->regs.pr[pipe_num]->HCHLEN = HCHLEN_PING | (HCHLEN_PCNT & (1U << 19U)); + + pp_ctl = udev->regs.pr[pipe_num]->HCHCTL; + + pp_ctl |= HCHCTL_CEN; + pp_ctl &= ~HCHCTL_CDIS; + + udev->regs.pr[pipe_num]->HCHCTL = pp_ctl; + + return USB_OK; +} + +/*! + \brief stop the USB host and clean up FIFO + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_host_stop (usb_core_driver *udev) +{ + uint32_t i; + __IO uint32_t pp_ctl = 0U; + + udev->regs.hr->HACHINTEN = 0x0U; + udev->regs.hr->HACHINT = 0xFFFFFFFFU; + + /* flush out any leftover queued requests. */ + for (i = 0U; i < udev->bp.num_pipe; i++) { + pp_ctl = udev->regs.pr[i]->HCHCTL; + + pp_ctl &= ~(HCHCTL_CEN | HCHCTL_EPDIR); + pp_ctl |= HCHCTL_CDIS; + + udev->regs.pr[i]->HCHCTL = pp_ctl; + } + + /* flush the FIFO */ + usb_rxfifo_flush (&udev->regs); + usb_txfifo_flush (&udev->regs, 0x10U); +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usbd_int.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usbd_int.c new file mode 100644 index 00000000..08498d97 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usbd_int.c @@ -0,0 +1,494 @@ +/*! + \file drv_usbd_int.c + \brief USB device mode interrupt routines + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_conf.h" +#include "drv_usbd_int.h" +#include "usbd_transc.h" + +/* local function prototypes ('static') */ +static uint32_t usbd_int_epout (usb_core_driver *udev); +static uint32_t usbd_int_epin (usb_core_driver *udev); +static uint32_t usbd_int_rxfifo (usb_core_driver *udev); +static uint32_t usbd_int_reset (usb_core_driver *udev); +static uint32_t usbd_int_enumfinish (usb_core_driver *udev); +static uint32_t usbd_int_suspend (usb_core_driver *udev); +static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num); + +static const uint8_t USB_SPEED[4] = { + [DSTAT_EM_HS_PHY_30MHZ_60MHZ] = (uint8_t)USB_SPEED_HIGH, + [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = (uint8_t)USB_SPEED_FULL, + [DSTAT_EM_FS_PHY_48MHZ] = (uint8_t)USB_SPEED_FULL, + [DSTAT_EM_LS_PHY_6MHZ] = (uint8_t)USB_SPEED_LOW +}; + +__IO uint8_t setupc_flag = 0U; + +/*! + \brief USB device-mode interrupts global service routine handler + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void usbd_isr (usb_core_driver *udev) +{ + if (HOST_MODE != (udev->regs.gr->GINTF & GINTF_COPM)) { + uint32_t intr = udev->regs.gr->GINTF; + intr &= udev->regs.gr->GINTEN; + + /* there are no interrupts, avoid spurious interrupt */ + if (!intr) { + return; + } + + /* OUT endpoints interrupts */ + if (intr & GINTF_OEPIF) { + (void)usbd_int_epout (udev); + } + + /* IN endpoints interrupts */ + if (intr & GINTF_IEPIF) { + (void)usbd_int_epin (udev); + } + + /* suspend interrupt */ + if (intr & GINTF_SP) { + (void)usbd_int_suspend (udev); + } + + /* wakeup interrupt */ + if (intr & GINTF_WKUPIF) { + if(USBD_SUSPENDED == udev->dev.cur_status){ + /* inform upper layer by the resume event */ + udev->dev.cur_status = udev->dev.backup_status; + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_WKUPIF; + } + + /* start of frame interrupt */ + if (intr & GINTF_SOF) { + if (udev->dev.class_core->SOF) { + (void)udev->dev.class_core->SOF(udev); + } + + if (0U != setupc_flag) { + setupc_flag++; + + if (setupc_flag >= 3U) { + usbd_setup_transc (udev); + + setupc_flag = 0U; + } + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_SOF; + } + + /* receive FIFO not empty interrupt */ + if (intr & GINTF_RXFNEIF) { + (void)usbd_int_rxfifo (udev); + } + + /* USB reset interrupt */ + if (intr & GINTF_RST) { + (void)usbd_int_reset (udev); + } + + /* enumeration has been done interrupt */ + if (intr & GINTF_ENUMFIF) { + (void)usbd_int_enumfinish (udev); + } + + /* incomplete synchronization IN transfer interrupt*/ + if (intr & GINTF_ISOINCIF) { + if (NULL != udev->dev.class_core->incomplete_isoc_in) { + (void)udev->dev.class_core->incomplete_isoc_in(udev); + } + + /* Clear interrupt */ + udev->regs.gr->GINTF = GINTF_ISOINCIF; + } + + /* incomplete synchronization OUT transfer interrupt*/ + if (intr & GINTF_ISOONCIF) { + if (NULL != udev->dev.class_core->incomplete_isoc_out) { + (void)udev->dev.class_core->incomplete_isoc_out(udev); + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_ISOONCIF; + } + +#ifdef VBUS_SENSING_ENABLED + + /* session request interrupt */ + if (intr & GINTF_SESIF) { + udev->regs.gr->GINTF = GINTF_SESIF; + } + + /* OTG mode interrupt */ + if (intr & GINTF_OTGIF) { + if(udev->regs.gr->GOTGINTF & GOTGINTF_SESEND) { + + } + + /* clear OTG interrupt */ + udev->regs.gr->GINTF = GINTF_OTGIF; + } +#endif /* VBUS_SENSING_ENABLED */ + } +} + +/*! + \brief indicates that an OUT endpoint has a pending interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_epout (usb_core_driver *udev) +{ + uint32_t epintnum = 0U; + uint8_t ep_num = 0U; + + for (epintnum = usb_oepintnum_read (udev); epintnum; epintnum >>= 1, ep_num++) { + if (epintnum & 0x01U) { + __IO uint32_t oepintr = usb_oepintr_read (udev, ep_num); + + /* transfer complete interrupt */ + if (oepintr & DOEPINTF_TF) { + /* clear the bit in DOEPINTF for this interrupt */ + udev->regs.er_out[ep_num]->DOEPINTF = DOEPINTF_TF; + + /* inform upper layer: data ready */ + (void)usbd_out_transc (udev, ep_num); + } + + /* setup phase finished interrupt (control endpoints) */ + if (oepintr & DOEPINTF_STPF) { + if((0U == ep_num) && (0U != setupc_flag)) { + /* inform the upper layer that a setup packet is available */ + (void)usbd_setup_transc (udev); + + udev->regs.er_out[ep_num]->DOEPINTF = DOEPINTF_STPF; + + setupc_flag = 0U; + } + } + } + } + + return 1U; +} + +/*! + \brief indicates that an IN endpoint has a pending interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_epin (usb_core_driver *udev) +{ + uint32_t epintnum = 0U; + uint8_t ep_num = 0U; + + for (epintnum = usb_iepintnum_read (udev); epintnum; epintnum >>= 1, ep_num++) { + if (epintnum & 0x1U) { + __IO uint32_t iepintr = usb_iepintr_read (udev, ep_num); + + if (iepintr & DIEPINTF_TF) { + udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TF; + + /* data transmission is completed */ + (void)usbd_in_transc (udev, ep_num); + } + + if (iepintr & DIEPINTF_TXFE) { + usbd_emptytxfifo_write (udev, (uint32_t)ep_num); + + udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TXFE; + } + } + } + + return 1U; +} + +/*! + \brief handle the RX status queue level interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_rxfifo (usb_core_driver *udev) +{ + usb_transc *transc = NULL; + + uint8_t data_PID = 0U; + uint32_t bcount = 0U; + + __IO uint32_t devrxstat = 0U; + + /* disable the Rx status queue non-empty interrupt */ + udev->regs.gr->GINTEN &= ~GINTEN_RXFNEIE; + + /* get the status from the top of the FIFO */ + devrxstat = udev->regs.gr->GRSTATP; + + uint8_t ep_num = (uint8_t)(devrxstat & GRSTATRP_EPNUM); + + transc = &udev->dev.transc_out[ep_num]; + + bcount = (devrxstat & GRSTATRP_BCOUNT) >> 4U; + data_PID = (uint8_t)((devrxstat & GRSTATRP_DPID) >> 15U); + + switch((devrxstat & GRSTATRP_RPCKST) >> 17U) { + case RSTAT_GOUT_NAK: + break; + + case RSTAT_DATA_UPDT: + if (bcount > 0U) { + (void)usb_rxfifo_read (&udev->regs, transc->xfer_buf, (uint16_t)bcount); + + transc->xfer_buf += bcount; + transc->xfer_count += bcount; + } + break; + + case RSTAT_XFER_COMP: + /* trigger the OUT endpoint interrupt */ + break; + + case RSTAT_SETUP_COMP: + /* trigger the OUT endpoint interrupt */ + break; + + case RSTAT_SETUP_UPDT: + if ((0U == transc->ep_addr.num) && (8U == bcount) && (DPID_DATA0 == data_PID)) { + /* copy the setup packet received in FIFO into the setup buffer in RAM */ + (void)usb_rxfifo_read (&udev->regs, (uint8_t *)&udev->dev.control.req, (uint16_t)bcount); + + transc->xfer_count += bcount; + + /* set the flag */ + setupc_flag = 1; + } + break; + + default: + break; + } + + /* enable the Rx status queue level interrupt */ + udev->regs.gr->GINTEN |= GINTEN_RXFNEIE; + + return 1U; +} + +/*! + \brief handle USB reset interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_int_reset (usb_core_driver *udev) +{ + uint32_t i; + + /* clear the remote wakeup signaling */ + udev->regs.dr->DCTL &= ~DCTL_RWKUP; + + /* flush the Tx FIFO */ + (void)usb_txfifo_flush (&udev->regs, 0U); + + for (i = 0U; i < udev->bp.num_ep; i++) { + udev->regs.er_in[i]->DIEPINTF = 0xFFU; + udev->regs.er_out[i]->DOEPINTF = 0xFFU; + } + + /* clear all pending device endpoint interrupts */ + udev->regs.dr->DAEPINT = 0xFFFFFFFFU; + + /* enable endpoint 0 interrupts */ + udev->regs.dr->DAEPINTEN = 1U | (1U << 16U); + + /* enable OUT endpoint interrupts */ + udev->regs.dr->DOEPINTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN; + + /* enable IN endpoint interrupts */ + udev->regs.dr->DIEPINTEN = DIEPINTEN_TFEN; + + /* reset device address */ + udev->regs.dr->DCFG &= ~DCFG_DAR; + + /* configure endpoint 0 to receive SETUP packets */ + usb_ctlep_startout (udev); + + /* clear USB reset interrupt */ + udev->regs.gr->GINTF = GINTF_RST; + + udev->dev.transc_out[0] = (usb_transc) { + .ep_type = USB_EPTYPE_CTRL, + .max_len = USB_FS_EP0_MAX_LEN + }; + + (void)usb_transc_active (udev, &udev->dev.transc_out[0]); + + udev->dev.transc_in[0] = (usb_transc) { + .ep_addr = { + .dir = 1U + }, + + .ep_type = USB_EPTYPE_CTRL, + .max_len = USB_FS_EP0_MAX_LEN + }; + + (void)usb_transc_active (udev, &udev->dev.transc_in[0]); + + /* upon reset call user call back */ + udev->dev.cur_status = (uint8_t)USBD_DEFAULT; + + return 1U; +} + +/*! + \brief handle USB speed enumeration finish interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_int_enumfinish (usb_core_driver *udev) +{ + uint8_t enum_speed = (uint8_t)((udev->regs.dr->DSTAT & DSTAT_ES) >> 1U); + + udev->regs.dr->DCTL &= ~DCTL_CGINAK; + udev->regs.dr->DCTL |= DCTL_CGINAK; + + udev->regs.gr->GUSBCS &= ~GUSBCS_UTT; + + /* set USB turn-around time based on device speed and PHY interface */ + if (USB_SPEED[enum_speed] == (uint8_t)USB_SPEED_HIGH) { + udev->bp.core_speed = (uint8_t)USB_SPEED_HIGH; + + udev->regs.gr->GUSBCS |= 0x09U << 10U; + } else { + udev->bp.core_speed = (uint8_t)USB_SPEED_FULL; + + udev->regs.gr->GUSBCS |= 0x05U << 10U; + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_ENUMFIF; + + return 1U; +} + +/*! + \brief USB suspend interrupt handler + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_suspend (usb_core_driver *udev) +{ + __IO uint8_t low_power = udev->bp.low_power; + __IO uint8_t suspend = (uint8_t)(udev->regs.dr->DSTAT & DSTAT_SPST); + __IO uint8_t is_configured = (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) ? 1U : 0U; + + udev->dev.backup_status = udev->dev.cur_status; + udev->dev.cur_status = (uint8_t)USBD_SUSPENDED; + + if (low_power && suspend && is_configured) { + /* switch-off the USB clocks */ + *udev->regs.PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK; + + /* enter DEEP_SLEEP mode with LDO in low power mode */ + pmu_to_deepsleepmode (PMU_LDO_LOWPOWER, WFI_CMD); + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_SP; + + return 1U; +} + +/*! + \brief check FIFO for the next packet to be loaded + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier which is in (0..3) + \param[out] none + \retval status +*/ +static uint32_t usbd_emptytxfifo_write (usb_core_driver *udev, uint32_t ep_num) +{ + uint32_t len; + uint32_t word_count; + + usb_transc *transc = &udev->dev.transc_in[ep_num]; + + len = transc->xfer_len - transc->xfer_count; + + /* get the data length to write */ + if (len > transc->max_len) { + len = transc->max_len; + } + + word_count = (len + 3U) / 4U; + + while (((udev->regs.er_in[ep_num]->DIEPTFSTAT & DIEPTFSTAT_IEPTFS) >= word_count) && \ + (transc->xfer_count < transc->xfer_len)) { + len = transc->xfer_len - transc->xfer_count; + + if (len > transc->max_len) { + len = transc->max_len; + } + + /* write FIFO in word(4bytes) */ + word_count = (len + 3U) / 4U; + + /* write the FIFO */ + (void)usb_txfifo_write (&udev->regs, transc->xfer_buf, (uint8_t)ep_num, (uint16_t)len); + + transc->xfer_buf += len; + transc->xfer_count += len; + + if (transc->xfer_count == transc->xfer_len) { + /* disable the device endpoint FIFO empty interrupt */ + udev->regs.dr->DIEPFEINTEN &= ~(0x01U << ep_num); + } + } + + return 1U; +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usbh_int.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usbh_int.c new file mode 100644 index 00000000..b096f31e --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/driver/Source/drv_usbh_int.c @@ -0,0 +1,598 @@ +/*! + \file drv_usbh_int.c + \brief USB host mode interrupt handler file + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usbh_int.h" + +#if defined (__CC_ARM) /*!< ARM compiler */ +#pragma O0 +#elif defined (__GNUC__) /*!< GNU compiler */ +#pragma GCC optimize ("O0") +#elif defined (__TASKING__) /*!< TASKING compiler */ +#pragma optimize=0 +#endif /* __CC_ARM */ + +/* local function prototypes ('static') */ +static uint32_t usbh_int_port (usb_core_driver *udev); +static uint32_t usbh_int_pipe (usb_core_driver *udev); +static uint32_t usbh_int_pipe_in (usb_core_driver *udev, uint32_t pp_num); +static uint32_t usbh_int_pipe_out (usb_core_driver *udev, uint32_t pp_num); +static uint32_t usbh_int_rxfifonoempty (usb_core_driver *udev); +static uint32_t usbh_int_txfifoempty (usb_core_driver *udev, usb_pipe_mode pp_mode); + +/*! + \brief handle global host interrupt + \param[in] udev: pointer to USB core instance + \param[out] none + \retval operation status +*/ +uint32_t usbh_isr (usb_core_driver *udev) +{ + uint32_t retval = 0U; + + __IO uint32_t intr = 0U; + + /* check if host mode */ + if (HOST_MODE == (udev->regs.gr->GINTF & GINTF_COPM)) { + intr = usb_coreintr_get(&udev->regs); + + if (!intr) { + return 0U; + } + + if (intr & GINTF_SOF) { + usbh_int_fop->SOF(udev->host.data); + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_SOF; + } + + if (intr & GINTF_RXFNEIF) { + retval |= usbh_int_rxfifonoempty (udev); + } + + if (intr & GINTF_NPTXFEIF) { + retval |= usbh_int_txfifoempty (udev, PIPE_NON_PERIOD); + } + + if (intr & GINTF_PTXFEIF) { + retval |= usbh_int_txfifoempty (udev, PIPE_PERIOD); + } + + if (intr & GINTF_HCIF) { + retval |= usbh_int_pipe (udev); + } + + if (intr & GINTF_HPIF) { + retval |= usbh_int_port (udev); + } + + if (intr & GINTF_DISCIF) { + usbh_int_fop->disconnect(udev->host.data); + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_DISCIF; + } + + if (intr & GINTF_ISOONCIF) { + udev->regs.pr[0]->HCHCTL |= HCHCTL_CEN | HCHCTL_CDIS; + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_ISOONCIF; + } + + if (intr & GINTF_SESIF) { + usb_portvbus_switch (udev, 1U); + + udev->regs.gr->GINTF = GINTF_SESIF; + } + + if (intr & GINTF_WKUPIF) { + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_WKUPIF; + } + } + + return retval; +} + +/*! + \brief handle USB pipe halt + \param[in] udev: pointer to USB core instance + \param[in] pp_num: pp_num: host channel number which is in (0..7) + \param[in] pp_int: pipe interrupt + \param[in] pp_status: pipe status + \param[out] none + \retval none +*/ +static inline void usb_pp_halt (usb_core_driver *udev, + uint8_t pp_num, + uint32_t pp_int, + usb_pipe_staus pp_status) +{ + udev->regs.pr[pp_num]->HCHINTEN |= HCHINTEN_CHIE; + + usb_pipe_halt(udev, pp_num); + + udev->regs.pr[pp_num]->HCHINTF = pp_int; + + udev->host.pipe[pp_num].pp_status = pp_status; +} + +/*! + \brief handle the host port interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +#if defined (__ICCARM__) /*!< IAR compiler */ + #pragma optimize = none +#endif /* __ICCARM */ +static uint32_t usbh_int_port (usb_core_driver *udev) +{ + uint32_t retval = 0U; + uint8_t port_reset = 0U; + __IO uint32_t port_state = *udev->regs.HPCS; + + /* clear the interrupt bits in GINTSTS */ + port_state &= ~(HPCS_PE | HPCS_PCD | HPCS_PEDC); + + /* port connect detected */ + if (*udev->regs.HPCS & HPCS_PCD) { + port_state |= HPCS_PCD; + + usbh_int_fop->connect(udev->host.data); + + retval |= 1U; + } + + /* port enable changed */ + if (*udev->regs.HPCS & HPCS_PEDC) { + port_state |= HPCS_PEDC; + + if (*udev->regs.HPCS & HPCS_PE) { + uint32_t port_speed = usb_curspeed_get(udev); + uint32_t clock_type = udev->regs.hr->HCTL & HCTL_CLKSEL; + + udev->host.connect_status = 1U; + + if (PORT_SPEED_LOW == port_speed) { + udev->regs.hr->HFT = 6000U; + + if (HCTL_6MHZ != clock_type) { + if (USB_EMBEDDED_PHY == udev->bp.phy_itf) { + usb_phyclock_config (udev, HCTL_6MHZ); + } + + port_reset = 1U; + } + } else if (PORT_SPEED_FULL == port_speed) { + udev->regs.hr->HFT = 48000U; + + if (HCTL_48MHZ != clock_type) { + usb_phyclock_config (udev, HCTL_48MHZ); + } + + port_reset = 1U; + } else { + /* for high speed device and others */ + port_reset = 1U; + } + + udev->host.port_enabled = 1; + + udev->regs.gr->GINTEN |= GINTEN_DISCIE | GINTEN_SOFIE; + } else { + udev->host.port_enabled = 0; + } + } + + if (port_reset) { + usb_port_reset(udev); + } + + /* clear port interrupts */ + *udev->regs.HPCS = port_state; + + return retval; +} + +/*! + \brief handle all host channels interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_int_pipe (usb_core_driver *udev) +{ + uint32_t pp_num = 0U; + uint32_t retval = 0U; + + for (pp_num = 0U; pp_num < udev->bp.num_pipe; pp_num++) { + if ((udev->regs.hr->HACHINT & HACHINT_HACHINT) & (1UL << pp_num)) { + if (udev->regs.pr[pp_num]->HCHCTL & HCHCTL_EPDIR) { + retval |= usbh_int_pipe_in (udev, pp_num); + } else { + retval |= usbh_int_pipe_out (udev, pp_num); + } + } + } + + return retval; +} + +/*! + \brief handle the IN channel interrupt + \param[in] udev: pointer to USB device instance + \param[in] pp_num: host channel number which is in (0..7) + \param[out] none + \retval operation status +*/ +#if defined (__ICCARM__) /*!< IAR compiler */ + #pragma optimize = none +#endif /* __ICCARM */ +static uint32_t usbh_int_pipe_in (usb_core_driver *udev, uint32_t pp_num) +{ + usb_pr *pp_reg = udev->regs.pr[pp_num]; + + usb_pipe *pp = &udev->host.pipe[pp_num]; + + uint32_t intr_pp = pp_reg->HCHINTF; + intr_pp &= pp_reg->HCHINTEN; + + uint8_t ep_type = (uint8_t)((pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U); + + if (intr_pp & HCHINTF_ACK) { + pp_reg->HCHINTF = HCHINTF_ACK; + } else if (intr_pp & HCHINTF_STALL) { + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_STALL, PIPE_STALL); + pp_reg->HCHINTF = HCHINTF_NAK; + + /* note: When there is a 'STALL', reset also NAK, + else, the udev->host.pp_status = HC_STALL + will be overwritten by 'NAK' in code below */ + intr_pp &= ~HCHINTF_NAK; + } else if (intr_pp & HCHINTF_DTER) { + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_DTER, PIPE_DTGERR); + pp_reg->HCHINTF = HCHINTF_NAK; + } else { + /* no operation */ + } + + if (intr_pp & HCHINTF_REQOVR) { + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_REQOVR, PIPE_REQOVR); + } else if (intr_pp & HCHINTF_TF) { + pp->pp_status = PIPE_XF; + pp->err_count = 0U; + + pp_reg->HCHINTF = HCHINTF_TF; + + switch (ep_type) { + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_XF); + + pp->data_toggle_in ^= 1U; + break; + + case USB_EPTYPE_INTR: + case USB_EPTYPE_ISOC: + pp_reg->HCHCTL |= HCHCTL_ODDFRM; + pp->urb_state = URB_DONE; + break; + + default: + break; + } + } else if (intr_pp & HCHINTF_CH) { + pp_reg->HCHINTEN &= ~HCHINTEN_CHIE; + + switch (pp->pp_status) { + case PIPE_XF: + pp->urb_state = URB_DONE; + break; + + case PIPE_STALL: + pp->urb_state = URB_STALL; + break; + + case PIPE_TRACERR: + case PIPE_DTGERR: + pp->err_count = 0U; + pp->urb_state = URB_ERROR; + + pp->data_toggle_in ^= 1U; + break; + + case PIPE_IDLE: + case PIPE_HALTED: + case PIPE_NAK: + case PIPE_NYET: + case PIPE_BBERR: + case PIPE_REQOVR: + default: + if((uint8_t)USB_EPTYPE_INTR == ep_type) { + pp->data_toggle_in ^= 1U; + } + break; + } + + pp_reg->HCHINTF = HCHINTF_CH; + } else if (intr_pp & HCHINTF_USBER) { + pp->err_count++; + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_USBER, PIPE_TRACERR); + } else if (intr_pp & HCHINTF_NAK) { + switch (ep_type) { + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + /* re-activate the channel */ + pp_reg->HCHCTL = (pp_reg->HCHCTL | HCHCTL_CEN) & ~HCHCTL_CDIS; + break; + + case USB_EPTYPE_INTR: + pp_reg->HCHINTEN |= HCHINTEN_CHIE; + + (void)usb_pipe_halt(udev, (uint8_t)pp_num); + break; + + default: + break; + } + + pp->pp_status = PIPE_NAK; + + pp_reg->HCHINTF = HCHINTF_NAK; + } else { + /* no operation */ + } + + return 1U; +} + +/*! + \brief handle the OUT channel interrupt + \param[in] udev: pointer to USB device instance + \param[in] pp_num: host channel number which is in (0..7) + \param[out] none + \retval operation status +*/ +#if defined (__ICCARM__) /*!< IAR compiler */ + #pragma optimize = none +#endif /* __ICCARM */ +static uint32_t usbh_int_pipe_out (usb_core_driver *udev, uint32_t pp_num) +{ + usb_pr *pp_reg = udev->regs.pr[pp_num]; + + usb_pipe *pp = &udev->host.pipe[pp_num]; + + uint32_t intr_pp = pp_reg->HCHINTF; + intr_pp &= pp_reg->HCHINTEN; + + if(intr_pp & HCHINTF_ACK) { + + pp_reg->HCHINTF = HCHINTF_ACK; + } else if(intr_pp & HCHINTF_STALL) { + usb_pp_halt(udev, (uint8_t)pp_num, HCHINTF_STALL, PIPE_STALL); + } else if(intr_pp & HCHINTF_DTER) { + usb_pp_halt(udev, (uint8_t)pp_num, HCHINTF_DTER, PIPE_DTGERR); + pp_reg->HCHINTF = HCHINTF_NAK; + } else if(intr_pp & HCHINTF_REQOVR) { + usb_pp_halt(udev, (uint8_t)pp_num, HCHINTF_REQOVR, PIPE_REQOVR); + } else if(intr_pp & HCHINTF_TF) { + pp->err_count = 0U; + usb_pp_halt(udev, (uint8_t)pp_num, HCHINTF_TF, PIPE_XF); + } else if(intr_pp & HCHINTF_NAK) { + pp->err_count = 0U; + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_NAK); + } else if (intr_pp & HCHINTF_USBER) { + pp->err_count++; + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_USBER, PIPE_TRACERR); + } else if(intr_pp & HCHINTF_NYET) { + pp->err_count = 0U; + usb_pp_halt (udev, (uint8_t)pp_num, HCHINTF_NYET, PIPE_NYET); + } else if (intr_pp & HCHINTF_CH) { + udev->regs.pr[pp_num]->HCHINTEN &= ~HCHINTEN_CHIE; + + switch (pp->pp_status) { + case PIPE_XF: + pp->urb_state = URB_DONE; + + if ((uint8_t)USB_EPTYPE_BULK == ((pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U)) { + pp->data_toggle_out ^= 1U; + } + break; + + case PIPE_NAK: + case PIPE_NYET: + pp->urb_state = URB_NOTREADY; + break; + + case PIPE_STALL: + pp->urb_state = URB_STALL; + break; + + case PIPE_TRACERR: + if (3U == pp->err_count) { + pp->urb_state = URB_ERROR; + pp->err_count = 0U; + } + break; + + case PIPE_IDLE: + case PIPE_HALTED: + case PIPE_BBERR: + case PIPE_REQOVR: + case PIPE_DTGERR: + default: + break; + } + + pp_reg->HCHINTF = HCHINTF_CH; + } else { + /* no operation */ + } + + return 1U; +} + +/*! + \brief handle the RX FIFO non-empty interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +#if defined (__ICCARM__) /*!< IAR compiler */ + #pragma optimize = none +#endif /* __ICCARM */ +static uint32_t usbh_int_rxfifonoempty (usb_core_driver *udev) +{ + uint32_t count = 0U, xfer_count = 0U; + + __IO uint8_t pp_num = 0U; + __IO uint32_t rx_stat = 0U; + + /* disable the RX status queue level interrupt */ + udev->regs.gr->GINTEN &= ~GINTEN_RXFNEIE; + + rx_stat = udev->regs.gr->GRSTATP; + pp_num = (uint8_t)(rx_stat & GRSTATRP_CNUM); + + switch ((rx_stat & GRSTATRP_RPCKST) >> 17U) { + case GRXSTS_PKTSTS_IN: + count = (rx_stat & GRSTATRP_BCOUNT) >> 4U; + + /* read the data into the host buffer. */ + if ((count > 0U) && (NULL != udev->host.pipe[pp_num].xfer_buf)) { + (void)usb_rxfifo_read (&udev->regs, udev->host.pipe[pp_num].xfer_buf, (uint16_t)count); + + /* manage multiple transfer packet */ + udev->host.pipe[pp_num].xfer_buf += count; + udev->host.pipe[pp_num].xfer_count += count; + + xfer_count = udev->host.pipe[pp_num].xfer_count; + + udev->host.backup_xfercount[pp_num] = xfer_count; + + if (udev->regs.pr[pp_num]->HCHLEN & HCHLEN_PCNT) { + /* re-activate the channel when more packets are expected */ + uint32_t pp_ctl = udev->regs.pr[pp_num]->HCHCTL; + + pp_ctl |= HCHCTL_CEN; + pp_ctl &= ~HCHCTL_CDIS; + + udev->regs.pr[pp_num]->HCHCTL = pp_ctl; + } + } + break; + + case GRXSTS_PKTSTS_IN_XFER_COMP: + break; + + case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: + count = (rx_stat & GRSTATRP_BCOUNT) >> 4U; + + while (count > 0U) { + rx_stat = udev->regs.gr->GRSTATP; + count--; + } + break; + + case GRXSTS_PKTSTS_CH_HALTED: + break; + + default: + break; + } + + /* enable the RX status queue level interrupt */ + udev->regs.gr->GINTEN |= GINTEN_RXFNEIE; + + return 1U; +} + +/*! + \brief handle the TX FIFO empty interrupt + \param[in] udev: pointer to USB device instance + \param[in] pp_mode: pipe mode + \param[out] none + \retval operation status +*/ +#if defined (__ICCARM__) /*!< IAR compiler */ + #pragma optimize = none +#endif /* __ICCARM */ +static uint32_t usbh_int_txfifoempty (usb_core_driver *udev, usb_pipe_mode pp_mode) +{ + uint8_t pp_num = 0U; + uint16_t word_count = 0U, len = 0U; + __IO uint32_t *txfiforeg = 0U, txfifostate = 0U; + + if (PIPE_NON_PERIOD == pp_mode) { + txfiforeg = &udev->regs.gr->HNPTFQSTAT; + } else if (PIPE_PERIOD == pp_mode) { + txfiforeg = &udev->regs.hr->HPTFQSTAT; + } else { + return 0U; + } + + txfifostate = *txfiforeg; + + pp_num = (uint8_t)((txfifostate & TFQSTAT_CNUM) >> 27U); + + word_count = (uint16_t)(udev->host.pipe[pp_num].xfer_len + 3U) / 4U; + + while (((txfifostate & TFQSTAT_TXFS) >= word_count) && (0U != udev->host.pipe[pp_num].xfer_len)) { + len = (uint16_t)(txfifostate & TFQSTAT_TXFS) * 4U; + + if (len > udev->host.pipe[pp_num].xfer_len) { + /* last packet */ + len = (uint16_t)udev->host.pipe[pp_num].xfer_len; + + if (PIPE_NON_PERIOD == pp_mode) { + udev->regs.gr->GINTEN &= ~GINTEN_NPTXFEIE; + } else { + udev->regs.gr->GINTEN &= ~GINTEN_PTXFEIE; + } + } + + word_count = (uint16_t)((udev->host.pipe[pp_num].xfer_len + 3U) / 4U); + usb_txfifo_write (&udev->regs, udev->host.pipe[pp_num].xfer_buf, pp_num, len); + + udev->host.pipe[pp_num].xfer_buf += len; + udev->host.pipe[pp_num].xfer_len -= len; + udev->host.pipe[pp_num].xfer_count += len; + + txfifostate = *txfiforeg; + } + + return 1U; +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/hid/Include/usbh_hid_core.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/hid/Include/usbh_hid_core.h new file mode 100644 index 00000000..69931d44 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/hid/Include/usbh_hid_core.h @@ -0,0 +1,120 @@ +/*! + \file usbh_hid_core.h + \brief header file for the usbh_hid_core.c + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_HID_CORE_H +#define __USBH_HID_CORE_H + +#include "usb_hid.h" +#include "usbh_enum.h" +#include "usbh_transc.h" + +#define HID_MIN_POLL 10U +#define HID_REPORT_SIZE 16U +#define HID_QUEUE_SIZE 10U + +#define USB_HID_DESC_SIZE 9U + +/* states for HID state machine */ +typedef enum { + HID_INIT = 0U, + HID_IDLE, + HID_SEND_DATA, + HID_BUSY, + HID_GET_DATA, + HID_SYNC, + HID_POLL, + HID_ERROR, +} hid_state; + +typedef enum { + HID_REQ_INIT = 0U, + HID_REQ_IDLE, + HID_REQ_GET_REPORT_DESC, + HID_REQ_GET_HID_DESC, + HID_REQ_SET_IDLE, + HID_REQ_SET_PROTOCOL, + HID_REQ_SET_REPORT, +} hid_ctlstate; + +typedef enum +{ + HID_MOUSE = 0x01U, + HID_KEYBOARD = 0x02U, + HID_UNKNOWN = 0xFFU, +} hid_type; + +typedef struct +{ + uint8_t *buf; + uint16_t head; + uint16_t tail; + uint16_t size; + uint8_t lock; +} data_fifo; + +/* structure for HID process */ +typedef struct _hid_process +{ + uint8_t pipe_in; + uint8_t pipe_out; + uint8_t ep_addr; + uint8_t ep_in; + uint8_t ep_out; + uint8_t *pdata; + __IO uint8_t data_ready; + uint16_t len; + uint16_t poll; + + __IO uint32_t timer; + usb_desc_hid hid_desc; + + hid_state state; + hid_ctlstate ctl_state; + + usbh_status (*init)(usb_core_driver *udev, usbh_host *uhost); + usbh_status (*decode)(uint8_t *data); +} usbh_hid_handler; + +extern usbh_class usbh_hid; + +/* function declarations */ +/* set HID report */ +usbh_status usbh_set_report (usb_core_driver *udev, + usbh_host *uhost, + uint8_t report_type, + uint8_t report_ID, + uint8_t report_len, + uint8_t *report_buf); + +#endif /* __USBH_HID_CORE_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/hid/Include/usbh_standard_hid.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/hid/Include/usbh_standard_hid.h new file mode 100644 index 00000000..2b8161b9 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/hid/Include/usbh_standard_hid.h @@ -0,0 +1,99 @@ +/*! + \file usbh_standard_hid.h + \brief header file for usbh_standard_hid.c + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_STANDARD_HID_H +#define __USBH_STANDARD_HID_H + +#include "usb_conf.h" +#include "usbh_hid_core.h" + +//#define AZERTY_KEYBOARD +#define QWERTY_KEYBOARD + +#define MOUSE_BUTTON_1 0x01U +#define MOUSE_BUTTON_2 0x02U +#define MOUSE_BUTTON_3 0x04U + +#define KBD_LEFT_CTRL 0x01U +#define KBD_LEFT_SHIFT 0x02U +#define KBD_LEFT_ALT 0x04U +#define KBD_LEFT_GUI 0x08U +#define KBD_RIGHT_CTRL 0x10U +#define KBD_RIGHT_SHIFT 0x20U +#define KBD_RIGHT_ALT 0x40U +#define KBD_RIGHT_GUI 0x80U + +#define KBD_PRESSED_MAX_NUM 6U + +typedef struct _hid_mouse_info +{ + uint8_t x; + uint8_t y; + uint8_t buttons[3]; +} hid_mouse_info; + +typedef struct +{ + uint8_t state; + uint8_t lctrl; + uint8_t lshift; + uint8_t lalt; + uint8_t lgui; + uint8_t rctrl; + uint8_t rshift; + uint8_t ralt; + uint8_t rgui; + uint8_t keys[6]; +} hid_keybd_info; + +/* function declarations */ +/* initialize mouse */ +void usr_mouse_init (void); +/* process mouse data */ +void usr_mouse_process_data (hid_mouse_info *data); +/* initialize mouse function */ +usbh_status usbh_hid_mouse_init (usb_core_driver *udev, usbh_host *uhost); +/* decode mouse information */ +usbh_status usbh_hid_mouse_decode(uint8_t *data); + +/* initialize keyboard */ +void usr_keybrd_init (void); +/* process keyboard data */ +void usr_keybrd_process_data (uint8_t pbuf); +/* initialize the keyboard function */ +usbh_status usbh_hid_keybrd_init (usb_core_driver *udev, usbh_host *uhost); +/* decode keyboard information */ +usbh_status usbh_hid_keybrd_decode (uint8_t *data); + +#endif /* __USBH_STANDARD_HID_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/hid/Source/usbh_hid_core.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/hid/Source/usbh_hid_core.c new file mode 100644 index 00000000..e93d5fb1 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/hid/Source/usbh_hid_core.c @@ -0,0 +1,581 @@ +/*! + \file usbh_hid_core.c + \brief USB host HID class driver + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include +#include "usbh_pipe.h" +#include "usbh_hid_core.h" +#include "usbh_standard_hid.h" + +/* local function prototypes ('static') */ +static void usbh_hiddesc_parse(usb_desc_hid *hid_desc, uint8_t *buf); +static void usbh_hid_itf_deinit(usbh_host *uhost); +static usbh_status usbh_hid_itf_init(usbh_host *uhost); +static usbh_status usbh_hid_class_req(usbh_host *uhost); +static usbh_status usbh_hid_handle(usbh_host *uhost); +static usbh_status usbh_hid_reportdesc_get(usbh_host *uhost, uint16_t len); +static usbh_status usbh_hid_sof(usbh_host *uhost); +static usbh_status usbh_hid_desc_get(usbh_host *uhost, uint16_t len); +static usbh_status usbh_set_idle(usbh_host *uhost, uint8_t duration, uint8_t report_ID); +static usbh_status usbh_set_protocol(usbh_host *uhost, uint8_t protocol); + +usbh_class usbh_hid = +{ + USB_HID_CLASS, + usbh_hid_itf_init, + usbh_hid_itf_deinit, + usbh_hid_class_req, + usbh_hid_handle, + usbh_hid_sof +}; + +/*! + \brief get report + \param[in] uhost: pointer to USB host + \param[in] report_type: duration for HID set idle request + \param[in] report_ID: targeted report ID for HID set idle request + \param[in] report_len: length of data report to be send + \param[in] report_buf: report buffer + \param[out] none + \retval operation status +*/ +usbh_status usbh_get_report (usbh_host *uhost, + uint8_t report_type, + uint8_t report_ID, + uint8_t report_len, + uint8_t *report_buf) +{ + usbh_status status = USBH_BUSY; + + if (CTL_IDLE == uhost->control.ctl_state) { + uhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_IN | USB_RECPTYPE_ITF | USB_REQTYPE_CLASS, + .bRequest = GET_REPORT, + .wValue = (report_type << 8U) | report_ID, + .wIndex = 0U, + .wLength = report_len + }; + + usbh_ctlstate_config (uhost, report_buf, report_len); + } + + status = usbh_ctl_handler (uhost); + + return status; +} + +/*! + \brief set report + \param[in] udev: pointer to USB core instance + \param[in] uhost: pointer to USB host + \param[in] report_type: duration for HID set idle request + \param[in] report_ID: targeted report ID for HID set idle request + \param[in] report_len: length of data report to be send + \param[in] report_buf: report buffer + \param[out] none + \retval operation status +*/ +usbh_status usbh_set_report (usb_core_driver *udev, + usbh_host *uhost, + uint8_t report_type, + uint8_t report_ID, + uint8_t report_len, + uint8_t *report_buf) +{ + usbh_status status = USBH_BUSY; + + if (CTL_IDLE == uhost->control.ctl_state) { + uhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_CLASS, + .bRequest = SET_REPORT, + .wValue = (report_type << 8U) | report_ID, + .wIndex = 0U, + .wLength = report_len + }; + + usbh_ctlstate_config (uhost, report_buf, report_len); + } + + status = usbh_ctl_handler (uhost); + + return status; +} + +/*! + \brief deinitialize the host pipes used for the HID class + \param[in] uhost: pointer to USB host + \param[out] none + \retval operation status +*/ +void usbh_hid_itf_deinit (usbh_host *uhost) +{ + usbh_hid_handler *hid = (usbh_hid_handler *)uhost->active_class->class_data; + + if (0x00U != hid->pipe_in) { + usb_pipe_halt (uhost->data, hid->pipe_in); + + usbh_pipe_free (uhost->data, hid->pipe_in); + + hid->pipe_in = 0U; /* reset the pipe as free */ + } + + if (0x00U != hid->pipe_out) { + usb_pipe_halt (uhost->data, hid->pipe_out); + + usbh_pipe_free (uhost->data, hid->pipe_out); + + hid->pipe_out = 0U; /* reset the channel as free */ + } +} + +/*! + \brief return device type + \param[in] udev: pointer to USB core instance + \param[in] uhost: pointer to USB host + \param[out] none + \retval hid_type +*/ +hid_type usbh_hid_device_type_get(usb_core_driver *udev, usbh_host *uhost) +{ + hid_type type = HID_UNKNOWN; + uint8_t interface_protocol; + + if (HOST_CLASS_HANDLER == uhost->cur_state) { + interface_protocol = uhost->dev_prop.cfg_desc_set.itf_desc_set[uhost->dev_prop.cur_itf][0].itf_desc.bInterfaceProtocol; + + if (USB_HID_PROTOCOL_KEYBOARD == interface_protocol) { + type = HID_KEYBOARD; + } else { + if (USB_HID_PROTOCOL_MOUSE == interface_protocol) { + type = HID_MOUSE; + } + } + } + + return type; +} + +/*! + \brief return HID device poll time + \param[in] udev: pointer to USB core instance + \param[in] uhost: pointer to USB host + \param[out] none + \retval poll time (ms) +*/ +uint8_t usbh_hid_poll_interval_get (usb_core_driver *udev, usbh_host *uhost) +{ + usbh_hid_handler *hid = (usbh_hid_handler *)uhost->active_class->class_data; + + if ((HOST_CLASS_ENUM == uhost->cur_state) || + (HOST_USER_INPUT == uhost->cur_state) || + (HOST_CLASS_CHECK == uhost->cur_state) || + (HOST_CLASS_HANDLER == uhost->cur_state)) { + return (uint8_t)(hid->poll); + } else { + return 0U; + } +} + +/*! + \brief initialize the hid class + \param[in] uhost: pointer to USB host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_hid_itf_init (usbh_host *uhost) +{ + uint8_t num = 0U, ep_num = 0U, interface = 0U; + usbh_status status = USBH_BUSY; + + interface = usbh_interface_find(&uhost->dev_prop, USB_HID_CLASS, USB_HID_SUBCLASS_BOOT_ITF, 0xFFU); + + if (0xFFU == interface) { + uhost->usr_cb->dev_not_supported(); + + status = USBH_FAIL; + } else { + usbh_interface_select(&uhost->dev_prop, interface); + + static usbh_hid_handler hid_handler; + + memset((void*)&hid_handler, 0, sizeof(usbh_hid_handler)); + + hid_handler.state = HID_ERROR; + + uint8_t itf_protocol = uhost->dev_prop.cfg_desc_set.itf_desc_set[uhost->dev_prop.cur_itf][0].itf_desc.bInterfaceProtocol; + if (USB_HID_PROTOCOL_KEYBOARD == itf_protocol) { + hid_handler.init = usbh_hid_keybrd_init; + hid_handler.decode = usbh_hid_keybrd_decode; + } else if (USB_HID_PROTOCOL_MOUSE == itf_protocol) { + hid_handler.init = usbh_hid_mouse_init; + hid_handler.decode = usbh_hid_mouse_decode; + } else { + status = USBH_FAIL; + } + + hid_handler.state = HID_INIT; + hid_handler.ctl_state = HID_REQ_INIT; + hid_handler.ep_addr = uhost->dev_prop.cfg_desc_set.itf_desc_set[uhost->dev_prop.cur_itf][0].ep_desc[0].bEndpointAddress; + hid_handler.len = uhost->dev_prop.cfg_desc_set.itf_desc_set[uhost->dev_prop.cur_itf][0].ep_desc[0].wMaxPacketSize; + hid_handler.poll = uhost->dev_prop.cfg_desc_set.itf_desc_set[uhost->dev_prop.cur_itf][0].ep_desc[0].bInterval; + + if (hid_handler.poll < HID_MIN_POLL) { + hid_handler.poll = HID_MIN_POLL; + } + + /* check for available number of endpoints */ + /* find the number of endpoints in the interface descriptor */ + /* choose the lower number in order not to overrun the buffer allocated */ + ep_num = USB_MIN(uhost->dev_prop.cfg_desc_set.itf_desc_set[uhost->dev_prop.cur_itf][0].itf_desc.bNumEndpoints, USBH_MAX_EP_NUM); + + /* decode endpoint IN and OUT address from interface descriptor */ + for (num = 0U; num < ep_num; num++) { + usb_desc_ep *ep_desc = &uhost->dev_prop.cfg_desc_set.itf_desc_set[uhost->dev_prop.cur_itf][0].ep_desc[num]; + + uint8_t ep_addr = ep_desc->bEndpointAddress; + + if (ep_addr & 0x80U) { + hid_handler.ep_in = ep_addr; + hid_handler.pipe_in = usbh_pipe_allocate (uhost->data, ep_addr); + + /* open channel for IN endpoint */ + usbh_pipe_create (uhost->data, + &uhost->dev_prop, + hid_handler.pipe_in, + USB_EPTYPE_INTR, + hid_handler.len); + + usbh_pipe_toggle_set(uhost->data, hid_handler.pipe_in, 0U); + } else { + hid_handler.ep_out = ep_addr; + hid_handler.pipe_out = usbh_pipe_allocate (uhost->data, ep_addr); + + /* open channel for OUT endpoint */ + usbh_pipe_create (uhost->data, + &uhost->dev_prop, + hid_handler.pipe_out, + USB_EPTYPE_INTR, + hid_handler.len); + + usbh_pipe_toggle_set(uhost->data, hid_handler.pipe_out, 0U); + } + } + + uhost->active_class->class_data = (void *)&hid_handler; + + status = USBH_OK; + } + + return status; +} + +/*! + \brief handle HID class requests for HID class + \param[in] uhost: pointer to USB host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_hid_class_req (usbh_host *uhost) +{ + usbh_status status = USBH_BUSY; + usbh_status class_req_status = USBH_BUSY; + + usbh_hid_handler *hid = (usbh_hid_handler *)uhost->active_class->class_data; + + /* handle HID control state machine */ + switch (hid->ctl_state) { + case HID_REQ_INIT: + case HID_REQ_GET_HID_DESC: + /* get HID descriptor */ + if (USBH_OK == usbh_hid_desc_get (uhost, USB_HID_DESC_SIZE)) { + usbh_hiddesc_parse(&hid->hid_desc, uhost->dev_prop.data); + + hid->ctl_state = HID_REQ_GET_REPORT_DESC; + } + break; + + case HID_REQ_GET_REPORT_DESC: + /* get report descriptor */ + if (USBH_OK == usbh_hid_reportdesc_get(uhost, hid->hid_desc.wDescriptorLength)) { + hid->ctl_state = HID_REQ_SET_IDLE; + } + break; + + case HID_REQ_SET_IDLE: + class_req_status = usbh_set_idle (uhost, 0U, 0U); + + /* set idle */ + if (USBH_OK == class_req_status) { + hid->ctl_state = HID_REQ_SET_PROTOCOL; + } else { + if(USBH_NOT_SUPPORTED == class_req_status) { + hid->ctl_state = HID_REQ_SET_PROTOCOL; + } + } + break; + + case HID_REQ_SET_PROTOCOL: + /* set protocol */ + if (USBH_OK == usbh_set_protocol (uhost, 0U)) { + hid->ctl_state = HID_REQ_IDLE; + + /* all requests performed */ + status = USBH_OK; + } + break; + + case HID_REQ_IDLE: + default: + break; + } + + return status; +} + +/*! + \brief manage state machine for HID data transfers + \param[in] uhost: pointer to USB host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_hid_handle (usbh_host *uhost) +{ + usbh_status status = USBH_OK; + usbh_hid_handler *hid = (usbh_hid_handler *)uhost->active_class->class_data; + + switch (hid->state) { + case HID_INIT: + hid->init(uhost->data, uhost); + hid->state = HID_IDLE; + break; + + case HID_IDLE: + hid->state = HID_SYNC; + status = USBH_OK; + break; + + case HID_SYNC: + /* sync with start of even frame */ + if (TRUE == usb_frame_even(uhost->data)) { + hid->state = HID_GET_DATA; + } + break; + + case HID_GET_DATA: + usbh_data_recev (uhost->data, hid->pdata, hid->pipe_in, hid->len); + + hid->state = HID_POLL; + hid->timer = usb_curframe_get (uhost->data); + hid->data_ready = 0U; + break; + + case HID_POLL: + if (URB_DONE == usbh_urbstate_get (uhost->data, hid->pipe_in)) { + if (0U == hid->data_ready) { + hid->data_ready = 1U; + + hid->decode(hid->pdata); + } + } else { + /* check IN endpoint stall status */ + if (URB_STALL == usbh_urbstate_get (uhost->data, hid->pipe_in)) { + /* issue clear feature on interrupt in endpoint */ + if (USBH_OK == (usbh_clrfeature (uhost, hid->ep_addr, hid->pipe_in))) { + /* change state to issue next in token */ + hid->state = HID_GET_DATA; + } + } + } + break; + + default: + break; + } + return status; +} + +/*! + \brief send get report descriptor command to the device + \param[in] uhost: pointer to USB host + \param[in] len: HID report descriptor length + \param[out] none + \retval operation status +*/ +static usbh_status usbh_hid_reportdesc_get (usbh_host *uhost, uint16_t len) +{ + usbh_status status = USBH_BUSY; + + if (CTL_IDLE == uhost->control.ctl_state) { + uhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_IN | USB_RECPTYPE_ITF | USB_REQTYPE_STRD, + .bRequest = USB_GET_DESCRIPTOR, + .wValue = USBH_DESC(USB_DESCTYPE_REPORT), + .wIndex = 0U, + .wLength = len + }; + + usbh_ctlstate_config (uhost, uhost->dev_prop.data, len); + } + + status = usbh_ctl_handler (uhost); + + return status; +} + +/*! + \brief managing the SOF process + \param[in] uhost: pointer to USB host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_hid_sof(usbh_host *uhost) +{ + usbh_hid_handler *hid = (usbh_hid_handler *)uhost->active_class->class_data; + + if (HID_POLL == hid->state) { + uint32_t frame_count = usb_curframe_get (uhost->data); + + if ((frame_count > hid->timer) && ((frame_count - hid->timer) >= hid->poll)) { + hid->state = HID_GET_DATA; + } else if ((frame_count < hid->timer) && ((frame_count + 0x3FFFU - hid->timer) >= hid->poll)) { + hid->state = HID_GET_DATA; + } else { + /* no operation */ + } + } + + return USBH_OK; +} + +/*! + \brief send the command of get HID descriptor to the device + \param[in] uhost: pointer to USB host + \param[in] len: HID descriptor length + \param[out] none + \retval operation status +*/ +static usbh_status usbh_hid_desc_get (usbh_host *uhost, uint16_t len) +{ + usbh_status status = USBH_BUSY; + + if (CTL_IDLE == uhost->control.ctl_state) { + uhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_IN | USB_RECPTYPE_ITF | USB_REQTYPE_STRD, + .bRequest = USB_GET_DESCRIPTOR, + .wValue = USBH_DESC(USB_DESCTYPE_HID), + .wIndex = 0U, + .wLength = len + }; + + usbh_ctlstate_config (uhost, uhost->dev_prop.data, len); + } + + status = usbh_ctl_handler (uhost); + + return status; +} + +/*! + \brief set idle state + \param[in] uhost: pointer to USB host + \param[in] duration: duration for HID set idle request + \param[in] report_ID: targeted report ID for HID set idle request + \param[out] none + \retval operation status +*/ +static usbh_status usbh_set_idle (usbh_host *uhost, uint8_t duration, uint8_t report_ID) +{ + usbh_status status = USBH_BUSY; + + if (CTL_IDLE == uhost->control.ctl_state) { + uhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_CLASS, + .bRequest = SET_IDLE, + .wValue = (duration << 8U) | report_ID, + .wIndex = 0U, + .wLength = 0U + }; + + usbh_ctlstate_config (uhost, NULL, 0U); + } + + status = usbh_ctl_handler (uhost); + + return status; +} + +/*! + \brief set protocol state + \param[in] uhost: pointer to USB host + \param[in] protocol: boot/report protocol + \param[out] none + \retval operation status +*/ +static usbh_status usbh_set_protocol (usbh_host *uhost, uint8_t protocol) +{ + usbh_status status = USBH_BUSY; + + if (CTL_IDLE == uhost->control.ctl_state) { + uhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_CLASS, + .bRequest = SET_PROTOCOL, + .wValue = !protocol, + .wIndex = 0U, + .wLength = 0U + }; + + usbh_ctlstate_config (uhost, NULL, 0U); + } + + status = usbh_ctl_handler (uhost); + + return status; +} + +/*! + \brief parse the HID descriptor + \param[in] hid_desc: pointer to HID descriptor + \param[in] buf: pointer to buffer where the source descriptor is available + \param[out] none + \retval none +*/ +static void usbh_hiddesc_parse (usb_desc_hid *hid_desc, uint8_t *buf) +{ + hid_desc->header.bLength = *(uint8_t *)(buf + 0U); + hid_desc->header.bDescriptorType = *(uint8_t *)(buf + 1U); + hid_desc->bcdHID = BYTE_SWAP(buf + 2U); + hid_desc->bCountryCode = *(uint8_t *)(buf + 4U); + hid_desc->bNumDescriptors = *(uint8_t *)(buf + 5U); + hid_desc->bDescriptorType = *(uint8_t *)(buf + 6U); + hid_desc->wDescriptorLength = BYTE_SWAP(buf + 7U); +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/hid/Source/usbh_standard_hid.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/hid/Source/usbh_standard_hid.c new file mode 100644 index 00000000..8d5c8ece --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/hid/Source/usbh_standard_hid.c @@ -0,0 +1,274 @@ +/*! + \file usbh_standard_hid.c + \brief USB host HID mouse and keyboard driver + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_standard_hid.h" +#include + +hid_mouse_info mouse_info; +hid_keybd_info keybd_info; + +uint8_t mouse_report_data[8] = {0U}; +uint32_t keybd_report_data[2]; + +/* local constants */ +static const uint8_t kbd_codes[] = +{ + 0, 0, 0, 0, 31, 50, 48, 33, + 19, 34, 35, 36, 24, 37, 38, 39, /* 0x00 - 0x0F */ + 52, 51, 25, 26, 17, 20, 32, 21, + 23, 49, 18, 47, 22, 46, 2, 3, /* 0x10 - 0x1F */ + 4, 5, 6, 7, 8, 9, 10, 11, + 43, 110, 15, 16, 61, 12, 13, 27, /* 0x20 - 0x2F */ + 28, 29, 42, 40, 41, 1, 53, 54, + 55, 30, 112, 113, 114, 115, 116, 117, /* 0x30 - 0x3F */ + 118, 119, 120, 121, 122, 123, 124, 125, + 126, 75, 80, 85, 76, 81, 86, 89, /* 0x40 - 0x4F */ + 79, 84, 83, 90, 95, 100, 105, 106, + 108, 93, 98, 103, 92, 97, 102, 91, /* 0x50 - 0x5F */ + 96, 101, 99, 104, 45, 129, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x60 - 0x6F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x70 - 0x7F */ + 0, 0, 0, 0, 0, 107, 0, 56, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x80 - 0x8F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x90 - 0x9F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xA0 - 0xAF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xB0 - 0xBF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xC0 - 0xCF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xD0 - 0xDF */ + 58, 44, 60, 127, 64, 57, 62, 128 /* 0xE0 - 0xE7 */ +}; + +#ifdef QWERTY_KEYBOARD + +static const int8_t kbd_key[] = +{ + '\0', '`', '1', '2', '3', '4', '5', '6', + '7', '8', '9', '0', '-', '=', '\0', '\r', + '\t', 'q', 'w', 'e', 'r', 't', 'y', 'u', + 'i', 'o', 'p', '[', ']', '\\', + '\0', 'a', 's', 'd', 'f', 'g', 'h', 'j', + 'k', 'l', ';', '\'', '\0', '\n', + '\0', '\0', 'z', 'x', 'c', 'v', 'b', 'n', + 'm', ',', '.', '/', '\0', '\0', + '\0', '\0', '\0', ' ', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '7', '4', '1', + '\0', '/', '8', '5', '2', + '0', '*', '9', '6', '3', + '.', '-', '+', '\0', '\n', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0' +}; + +static const int8_t kbd_key_shift[] = { + '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', + '_', '+', '\0', '\0', '\0', 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', + 'I', 'O', 'P', '{', '}', '|', '\0', 'A', 'S', 'D', 'F', 'G', + 'H', 'J', 'K', 'L', ':', '"', '\0', '\n', '\0', '\0', 'Z', 'X', + 'C', 'V', 'B', 'N', 'M', '<', '>', '?', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; + +#else + +static const int8_t kbd_key[] = { + '\0', '`', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', + '-', '=', '\0', '\r', '\t', 'a', 'z', 'e', 'r', 't', 'y', 'u', + 'i', 'o', 'p', '[', ']', '\\', '\0', 'q', 's', 'd', 'f', 'g', + 'h', 'j', 'k', 'l', 'm', '\0', '\0', '\n', '\0', '\0', 'w', 'x', + 'c', 'v', 'b', 'n', ',', ';', ':', '!', '\0', '\0', '\0', '\0', + '\0', ' ', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '7', '4', '1', '\0', '/', + '8', '5', '2', '0', '*', '9', '6', '3', '.', '-', '+', '\0', + '\n', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; + +static const int8_t kbd_key_shift[] = { + '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', + '+', '\0', '\0', '\0', 'A', 'Z', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', + 'P', '{', '}', '*', '\0', 'Q', 'S', 'D', 'F', 'G', 'H', 'J', 'K', + 'L', 'M', '%', '\0', '\n', '\0', '\0', 'W', 'X', 'C', 'V', 'B', 'N', + '?', '.', '/', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; + +#endif /* QWERTY_KEYBOARD */ + +/*! + \brief initialize the mouse function + \param[in] udev: pointer to USB core instance + \param[in] uhost: pointer to USB host + \param[out] none + \retval none +*/ +usbh_status usbh_hid_mouse_init (usb_core_driver *udev, usbh_host *uhost) +{ + usbh_hid_handler *hid = (usbh_hid_handler *)uhost->active_class->class_data; + + mouse_info.x = 0U; + mouse_info.y = 0U; + mouse_info.buttons[0] = 0U; + mouse_info.buttons[1] = 0U; + mouse_info.buttons[2] = 0U; + + if(hid->len > sizeof(mouse_report_data)) { + hid->len = sizeof(mouse_report_data); + } + + hid->pdata = (uint8_t *)(void *)mouse_report_data; + + usr_mouse_init(); + + return USBH_OK; +} + +/*! + \brief decode mouse information + \param[in] udev: pointer to USB core instance + \param[in] uhost: pointer to USB host + \param[out] none + \retval operation status +*/ +usbh_status usbh_hid_mouse_decode(uint8_t *data) +{ + mouse_info.buttons[0] = data[0] & MOUSE_BUTTON_1; + mouse_info.buttons[1] = data[0] & MOUSE_BUTTON_2; + mouse_info.buttons[2] = data[0] & MOUSE_BUTTON_3; + + mouse_info.x = data[1]; + mouse_info.y = data[2]; + + /* handle mouse data position */ + usr_mouse_process_data(&mouse_info); + + return USBH_FAIL; +} + +/*! + \brief initialize the keyboard function + \param[in] udev: pointer to USB core instance + \param[in] uhost: pointer to USB host + \param[out] none + \retval operation status +*/ +usbh_status usbh_hid_keybrd_init (usb_core_driver *udev, usbh_host *uhost) +{ + usbh_hid_handler *hid = (usbh_hid_handler *)uhost->active_class->class_data; + + keybd_info.lctrl = keybd_info.lshift = 0U; + keybd_info.lalt = keybd_info.lgui = 0U; + keybd_info.rctrl = keybd_info.rshift = 0U; + keybd_info.ralt = keybd_info.rgui = 0U; + + for (uint32_t x = 0U; x < (sizeof(keybd_report_data) / sizeof(uint32_t)); x++) { + keybd_report_data[x] = 0U; + } + + if (hid->len > (sizeof(keybd_report_data) / sizeof(uint32_t))) { + hid->len = (sizeof(keybd_report_data) / sizeof(uint32_t)); + } + + hid->pdata = (uint8_t*)(void *)keybd_report_data; + + /* call user initialization*/ + usr_keybrd_init(); + + return USBH_OK; +} + +/*! + \brief get ascii code + \param[in] info: keyboard information + \param[out] none + \retval output +*/ +uint8_t usbh_hid_ascii_code_get (hid_keybd_info *info) +{ + uint8_t output; + if ((1U == info->lshift) || (info->rshift)) { + output = kbd_key_shift[kbd_codes[info->keys[0]]]; + } else { + output = kbd_key[kbd_codes[info->keys[0]]]; + } + + return output; +} + +/*! + \brief decode keyboard information + \param[in] udev: pointer to USB core instance + \param[in] uhost: pointer to USB host + \param[out] none + \retval operation status +*/ +usbh_status usbh_hid_keybrd_decode (uint8_t *data) +{ + uint8_t output; + + keybd_info.lshift = data[0] & KBD_LEFT_SHIFT; + keybd_info.rshift = data[0] & KBD_RIGHT_SHIFT; + + keybd_info.keys[0] = data[2]; + + if (keybd_info.lshift || keybd_info.rshift) { + output = kbd_key_shift[kbd_codes[keybd_info.keys[0]]]; + } else { + output = kbd_key[kbd_codes[keybd_info.keys[0]]]; + } + + if (0U != output) { + usr_keybrd_process_data(output); + } + + return USBH_OK; +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Include/usbh_msc_bbb.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Include/usbh_msc_bbb.h new file mode 100644 index 00000000..4c82de85 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Include/usbh_msc_bbb.h @@ -0,0 +1,150 @@ +/*! + \file usbh_msc_bbb.h + \brief header file for usbh_msc_bbb.c + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_MSC_BBB_H +#define __USBH_MSC_BBB_H + +#include "usbh_enum.h" +#include "msc_bbb.h" + +typedef union { + msc_bbb_cbw field; + + uint8_t CBWArray[31]; +} usbh_cbw_pkt; + +typedef union { + msc_bbb_csw field; + + uint8_t CSWArray[13]; +} usbh_csw_pkt; + +enum usbh_msc_state { + USBH_MSC_BBB_INIT_STATE = 0U, + USBH_MSC_BBB_RESET, + USBH_MSC_GET_MAX_LUN, + USBH_MSC_TEST_UNIT_READY, + USBH_MSC_READ_CAPACITY10, + USBH_MSC_MODE_SENSE6, + USBH_MSC_REQUEST_SENSE, + USBH_MSC_BBB_USB_TRANSFERS, + USBH_MSC_DEFAULT_APPLI_STATE, + USBH_MSC_CTRL_ERROR_STATE, + USBH_MSC_UNRECOVERED_STATE +}; + +typedef enum +{ + BBB_OK = 0U, + BBB_FAIL, + BBB_PHASE_ERROR, + BBB_BUSY +} bbb_status; + +typedef enum +{ + BBB_CMD_IDLE = 0U, + BBB_CMD_SEND, + BBB_CMD_WAIT +} bbb_cmd_state; + +/* csw status definitions */ +typedef enum +{ + BBB_CSW_CMD_PASSED = 0U, + BBB_CSW_CMD_FAILED, + BBB_CSW_PHASE_ERROR +} bbb_csw_status; + +typedef enum +{ + BBB_SEND_CBW = 1U, + BBB_SEND_CBW_WAIT, + BBB_DATA_IN, + BBB_DATA_IN_WAIT, + BBB_DATA_OUT, + BBB_DATA_OUT_WAIT, + BBB_RECEIVE_CSW, + BBB_RECEIVE_CSW_WAIT, + BBB_ERROR_IN, + BBB_ERROR_OUT, + BBB_UNRECOVERED_ERROR +} bbb_state; + +typedef struct +{ + uint8_t *pbuf; + uint32_t data[16]; + bbb_state state; + bbb_state prev_state; + bbb_cmd_state cmd_state; + usbh_cbw_pkt cbw; + usbh_csw_pkt csw; +} bbb_handle; + +#define USBH_MSC_BBB_CBW_TAG 0x20304050U + +#define USBH_MSC_CSW_MAX_LENGTH 63U + +#define USBH_MSC_SEND_CSW_DISABLE 0U +#define USBH_MSC_SEND_CSW_ENABLE 1U + +#define USBH_MSC_DIR_IN 0U +#define USBH_MSC_DIR_OUT 1U +#define USBH_MSC_BOTH_DIR 2U + +#define USBH_MSC_PAGE_LENGTH 512U + +#define CBW_CB_LENGTH 16U +#define CBW_LENGTH 10U +#define CBW_LENGTH_TEST_UNIT_READY 0U + +#define MAX_BULK_STALL_COUNT_LIMIT 0x04U /*!< If STALL is seen on Bulk + Endpoint continously, this means + that device and Host has phase error + Hence a Reset is needed */ + +/* function declarations */ +/* initialize the mass storage parameters */ +void usbh_msc_bbb_init (usbh_host *uhost); +/* manage the different states of BBB transfer and updates the status to upper layer */ +usbh_status usbh_msc_bbb_process (usbh_host *uhost, uint8_t lun); +/* manages the different error handling for stall */ +usbh_status usbh_msc_bbb_abort (usbh_host *uhost, uint8_t direction); +/* reset MSC bbb request structure */ +usbh_status usbh_msc_bbb_reset (usbh_host *uhost); +/* decode the CSW received by the device and updates the same to upper layer */ +bbb_csw_status usbh_msc_csw_decode (usbh_host *uhost); + +#endif /* __USBH_MSC_BBB_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Include/usbh_msc_core.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Include/usbh_msc_core.h new file mode 100644 index 00000000..5a5f92b1 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Include/usbh_msc_core.h @@ -0,0 +1,124 @@ +/*! + \file usbh_core.h + \brief header file for the usbh_core.c + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_MSC_CORE_H +#define __USBH_MSC_CORE_H + +#include "usb_msc.h" +#include "usbh_msc_scsi.h" +#include "usbh_msc_bbb.h" + +#define MSC_MAX_SUPPORTED_LUN 2U + +typedef enum +{ + MSC_INIT = 0U, + MSC_IDLE, + MSC_TEST_UNIT_READY, + MSC_READ_CAPACITY10, + MSC_READ_INQUIRY, + MSC_REQUEST_SENSE, + MSC_READ, + MSC_WRITE, + MSC_UNRECOVERED_ERROR, + MSC_PERIODIC_CHECK, +} msc_state; + +typedef enum +{ + MSC_OK, + MSC_NOT_READY, + MSC_ERROR, +} msc_error; + +typedef enum +{ + MSC_REQ_IDLE = 0U, + MSC_REQ_RESET, + MSC_REQ_GET_MAX_LUN, + MSC_REQ_ERROR, +} msc_req_state; + +/* structure for LUN */ +typedef struct +{ + msc_state state; + msc_error error; + msc_scsi_sense sense; + scsi_capacity capacity; + scsi_std_inquiry_data inquiry; + usbh_status prev_ready_state; + uint8_t state_changed; +} msc_lun; + +/* structure for msc process */ +typedef struct _msc_process +{ + uint8_t pipe_in; + uint8_t pipe_out; + uint8_t ep_in; + uint8_t ep_out; + uint16_t ep_size_in; + uint16_t ep_size_out; + uint8_t cur_lun; + uint16_t rw_lun; + uint32_t max_lun; + msc_state state; + msc_error error; + msc_req_state req_state; + msc_req_state prev_req_state; + bbb_handle bbb; + msc_lun unit[MSC_MAX_SUPPORTED_LUN]; + uint32_t timer; +} usbh_msc_handler; + +extern usbh_class usbh_msc; + +/* function declarations */ +/* get msc logic unit information */ +usbh_status usbh_msc_lun_info_get (usbh_host *uhost, uint8_t lun, msc_lun *info); +/* msc read interface */ +usbh_status usbh_msc_read (usbh_host *uhost, + uint8_t lun, + uint32_t address, + uint8_t *pbuf, + uint32_t length); +/* msc write interface */ +usbh_status usbh_msc_write (usbh_host *uhost, + uint8_t lun, + uint32_t address, + uint8_t *pbuf, + uint32_t length); + +#endif /* __USBH_MSC_CORE_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Include/usbh_msc_scsi.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Include/usbh_msc_scsi.h new file mode 100644 index 00000000..34aeab6e --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Include/usbh_msc_scsi.h @@ -0,0 +1,100 @@ +/*! + \file usbh_msc_scsi.h + \brief header file for usbh_msc_scsi.c + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_MSC_SCSI_H +#define __USBH_MSC_SCSI_H + +#include "msc_scsi.h" +#include "usbh_enum.h" + +/* capacity data */ +typedef struct +{ + uint32_t block_nbr; + uint16_t block_size; +} scsi_capacity; + +/* inquiry data */ +typedef struct +{ + uint8_t peripheral_qualifier; + uint8_t device_type; + uint8_t removable_media; + uint8_t vendor_id[9]; + uint8_t product_id[17]; + uint8_t revision_id[5]; +} scsi_std_inquiry_data; + +typedef struct +{ + uint32_t msc_capacity; + uint32_t msc_sense_key; + uint16_t msc_page_len; + uint8_t msc_write_protect; +} usbh_msc_parameter; + +#define DESC_REQUEST_SENSE 0x00U +#define ALLOCATION_LENGTH_REQUEST_SENSE 63U +#define XFER_LEN_MODE_SENSE6 63U + +#define MASK_MODE_SENSE_WRITE_PROTECT 0x80U +#define MODE_SENSE_PAGE_CONTROL_FIELD 0x00U +#define MODE_SENSE_PAGE_CODE 0x3FU +#define DISK_WRITE_PROTECTED 0x01U + +/* function declarations */ +/* send 'Inquiry' command to the device */ +usbh_status usbh_msc_scsi_inquiry (usbh_host *uhost, uint8_t lun, scsi_std_inquiry_data *inquiry); +/* send 'Test unit ready' command to the device */ +usbh_status usbh_msc_test_unitready (usbh_host *uhost, uint8_t lun); +/* send the read capacity command to the device */ +usbh_status usbh_msc_read_capacity10 (usbh_host *uhost, uint8_t lun, scsi_capacity *capacity); +/* send the mode sense6 command to the device */ +usbh_status usbh_msc_mode_sense6 (usbh_host *uhost, uint8_t lun); +/* send the Request Sense command to the device */ +usbh_status usbh_msc_request_sense (usbh_host *uhost, uint8_t lun, msc_scsi_sense *sense_data); +/* send the write10 command to the device */ +usbh_status usbh_msc_write10 (usbh_host *uhost, + uint8_t lun, + uint8_t *data_buf, + uint32_t addr, + uint32_t byte_num); +/* send the read10 command to the device */ +usbh_status usbh_msc_read10 (usbh_host *uhost, + uint8_t lun, + uint8_t *data_buf, + uint32_t addr, + uint32_t byte_num); + +#endif /* __USBH_MSC_SCSI_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Source/usbh_msc_bbb.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Source/usbh_msc_bbb.c new file mode 100644 index 00000000..f8155b18 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Source/usbh_msc_bbb.c @@ -0,0 +1,362 @@ +/*! + \file usbh_msc_bbb.c + \brief USB MSC BBB protocol related functions + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_pipe.h" +#include "usbh_msc_core.h" +#include "usbh_msc_scsi.h" +#include "usbh_msc_bbb.h" +#include "usbh_transc.h" +#include "drv_usbh_int.h" + +/*! + \brief initialize the mass storage parameters + \param[in] uhost: pointer to USB host handler + \param[out] none + \retval none +*/ +void usbh_msc_bbb_init (usbh_host *uhost) +{ + usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; + + msc->bbb.cbw.field.dCBWSignature = BBB_CBW_SIGNATURE; + msc->bbb.cbw.field.dCBWTag = USBH_MSC_BBB_CBW_TAG; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_SEND; +} + +/*! + \brief manage the different states of BBB transfer and updates the status to upper layer + \param[in] uhost: pointer to USB host handler + \param[in] lun: logic unit number + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_bbb_process (usbh_host *uhost, uint8_t lun) +{ + bbb_csw_status csw_status = BBB_CSW_CMD_FAILED; + usbh_status status = USBH_BUSY; + usbh_status error = USBH_BUSY; + usb_urb_state urb_status = URB_IDLE; + usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; + + switch (msc->bbb.state) { + case BBB_SEND_CBW: + msc->bbb.cbw.field.bCBWLUN = lun; + msc->bbb.state = BBB_SEND_CBW_WAIT; + /* send CBW */ + usbh_data_send (uhost->data, + msc->bbb.cbw.CBWArray, + msc->pipe_out, + BBB_CBW_LENGTH); + break; + + case BBB_SEND_CBW_WAIT: + urb_status = usbh_urbstate_get(uhost->data, msc->pipe_out); + + if (URB_DONE == urb_status) { + if (0U != msc->bbb.cbw.field.dCBWDataTransferLength) { + if (USB_TRX_IN == (msc->bbb.cbw.field.bmCBWFlags & USB_TRX_MASK)) { + msc->bbb.state = BBB_DATA_IN; + } else { + msc->bbb.state = BBB_DATA_OUT; + } + } else { + msc->bbb.state = BBB_RECEIVE_CSW; + } + + } else if (URB_NOTREADY == urb_status) { + msc->bbb.state = BBB_SEND_CBW; + } else { + if (URB_STALL == urb_status) { + msc->bbb.state = BBB_ERROR_OUT; + } + } + break; + + case BBB_DATA_IN: + usbh_data_recev (uhost->data, + msc->bbb.pbuf, + msc->pipe_in, + msc->ep_size_in); + + msc->bbb.state = BBB_DATA_IN_WAIT; + break; + + case BBB_DATA_IN_WAIT: + urb_status = usbh_urbstate_get(uhost->data, msc->pipe_in); + + /* BBB DATA IN stage */ + if (URB_DONE == urb_status) { + if (msc->bbb.cbw.field.dCBWDataTransferLength > msc->ep_size_in) { + msc->bbb.pbuf += msc->ep_size_in; + msc->bbb.cbw.field.dCBWDataTransferLength -= msc->ep_size_in; + } else { + msc->bbb.cbw.field.dCBWDataTransferLength = 0U; + } + + if (msc->bbb.cbw.field.dCBWDataTransferLength > 0U) { + usbh_data_recev (uhost->data, + msc->bbb.pbuf, + msc->pipe_in, + msc->ep_size_in); + } else { + msc->bbb.state = BBB_RECEIVE_CSW; + } + } else if(URB_STALL == urb_status) { + /* this is data stage stall condition */ + msc->bbb.state = BBB_ERROR_IN; + } else { + /* no operation */ + } + break; + + case BBB_DATA_OUT: + usbh_data_send (uhost->data, + msc->bbb.pbuf, + msc->pipe_out, + msc->ep_size_out); + + msc->bbb.state = BBB_DATA_OUT_WAIT; + break; + + case BBB_DATA_OUT_WAIT: + /* BBB DATA OUT stage */ + urb_status = usbh_urbstate_get(uhost->data, msc->pipe_out); + if (URB_DONE == urb_status) { + if (msc->bbb.cbw.field.dCBWDataTransferLength > msc->ep_size_out) { + msc->bbb.pbuf += msc->ep_size_out; + msc->bbb.cbw.field.dCBWDataTransferLength -= msc->ep_size_out; + } else { + msc->bbb.cbw.field.dCBWDataTransferLength = 0; /* reset this value and keep in same state */ + } + + if (msc->bbb.cbw.field.dCBWDataTransferLength > 0) { + usbh_data_send (uhost->data, + msc->bbb.pbuf, + msc->pipe_out, + msc->ep_size_out); + } else { + msc->bbb.state = BBB_RECEIVE_CSW; + } + } else if (URB_NOTREADY == urb_status) { + msc->bbb.state = BBB_DATA_OUT; + } else if (URB_STALL == urb_status) { + msc->bbb.state = BBB_ERROR_OUT; + } else { + /* no operation */ + } + break; + + case BBB_RECEIVE_CSW: + /* BBB CSW stage */ + usbh_data_recev (uhost->data, + msc->bbb.csw.CSWArray, + msc->pipe_in, + BBB_CSW_LENGTH); + + msc->bbb.state = BBB_RECEIVE_CSW_WAIT; + break; + + case BBB_RECEIVE_CSW_WAIT: + urb_status = usbh_urbstate_get(uhost->data, msc->pipe_in); + + /* decode CSW */ + if (URB_DONE == urb_status) { + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_SEND; + + csw_status = usbh_msc_csw_decode(uhost); + if (BBB_CSW_CMD_PASSED == csw_status) { + status = USBH_OK; + } else { + status = USBH_FAIL; + } + } else if (URB_STALL == urb_status) { + msc->bbb.state = BBB_ERROR_IN; + } else { + /* no operation */ + } + break; + + case BBB_ERROR_IN: + error = usbh_msc_bbb_abort(uhost, USBH_MSC_DIR_IN); + + if (USBH_OK == error) { + msc->bbb.state = BBB_RECEIVE_CSW; + } else if (USBH_UNRECOVERED_ERROR == status) { + /* this means that there is a stall error limit, do reset recovery */ + msc->bbb.state = BBB_UNRECOVERED_ERROR; + } else { + /* no operation */ + } + break; + + case BBB_ERROR_OUT: + status = usbh_msc_bbb_abort (uhost, USBH_MSC_DIR_OUT); + + if (USBH_OK == status) { + uint8_t toggle = usbh_pipe_toggle_get(uhost->data, msc->pipe_out); + usbh_pipe_toggle_set(uhost->data, msc->pipe_out, 1U - toggle); + usbh_pipe_toggle_set(uhost->data, msc->pipe_in, 0U); + msc->bbb.state = BBB_ERROR_IN; + } else { + if (USBH_UNRECOVERED_ERROR == status) { + msc->bbb.state = BBB_UNRECOVERED_ERROR; + } + } + break; + + case BBB_UNRECOVERED_ERROR: + status = usbh_msc_bbb_reset(uhost); + if (USBH_OK == status) { + msc->bbb.state = BBB_SEND_CBW; + } + break; + + default: + break; + } + + return status; +} + +/*! + \brief manages the different error handling for stall + \param[in] uhost: pointer to USB host handler + \param[in] direction: data IN or OUT + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_bbb_abort (usbh_host *uhost, uint8_t direction) +{ + usbh_status status = USBH_BUSY; + usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; + + switch (direction) { + case USBH_MSC_DIR_IN : + /* send clrfeature command on bulk IN endpoint */ + status = usbh_clrfeature(uhost, + msc->ep_in, + msc->pipe_in); + break; + + case USBH_MSC_DIR_OUT : + /*send clrfeature command on bulk OUT endpoint */ + status = usbh_clrfeature(uhost, + msc->ep_out, + msc->pipe_out); + break; + + default: + break; + } + + return status; +} + +/*! + \brief reset msc bbb transfer + \param[in] uhost: pointer to USB host handler + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_bbb_reset (usbh_host *uhost) +{ + usbh_status status = USBH_BUSY; + + if (CTL_IDLE == uhost->control.ctl_state) { + uhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_REQTYPE_CLASS | USB_RECPTYPE_ITF, + .bRequest = BBB_RESET, + .wValue = 0U, + .wIndex = 0U, + .wLength = 0U + }; + + usbh_ctlstate_config (uhost, NULL, 0U); + } + + status = usbh_ctl_handler (uhost); + + return status; +} + +/*! + \brief decode the CSW received by the device and updates the same to upper layer + \param[in] uhost: pointer to USB host + \param[out] none + \retval on success USBH_MSC_OK, on failure USBH_MSC_FAIL + \notes + Refer to USB Mass-Storage Class: BBB (www.usb.org) + 6.3.1 Valid CSW Conditions : + The host shall consider the CSW valid when: + 1. dCSWSignature is equal to 53425355h + 2. the CSW is 13 (Dh) bytes in length, + 3. dCSWTag matches the dCBWTag from the corresponding CBW. +*/ +bbb_csw_status usbh_msc_csw_decode (usbh_host *uhost) +{ + bbb_csw_status status = BBB_CSW_CMD_FAILED; + usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; + + /* checking if the transfer length is different than 13 */ + if (BBB_CSW_LENGTH != usbh_xfercount_get (uhost->data, msc->pipe_in)) { + status = BBB_CSW_PHASE_ERROR; + } else { + /* CSW length is correct */ + + /* check validity of the CSW Signature and CSWStatus */ + if (BBB_CSW_SIGNATURE == msc->bbb.csw.field.dCSWSignature) { + /* check condition 1. dCSWSignature is equal to 53425355h */ + if (msc->bbb.csw.field.dCSWTag == msc->bbb.cbw.field.dCBWTag) { + /* check condition 3. dCSWTag matches the dCBWTag from the corresponding CBW */ + if (0U == msc->bbb.csw.field.bCSWStatus) { + status = BBB_CSW_CMD_PASSED; + } else if (1U == msc->bbb.csw.field.bCSWStatus) { + status = BBB_CSW_CMD_FAILED; + } else if (2U == msc->bbb.csw.field.bCSWStatus) { + status = BBB_CSW_PHASE_ERROR; + } else { + /* no operation */ + } + } + } else { + /* If the CSW signature is not valid, we shall return the phase error to + upper layers for reset recovery */ + status = BBB_CSW_PHASE_ERROR; + } + } + + return status; +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Source/usbh_msc_core.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Source/usbh_msc_core.c new file mode 100644 index 00000000..7c7354d0 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Source/usbh_msc_core.c @@ -0,0 +1,563 @@ +/*! + \file usbh_core.c + \brief USB MSC(mass storage device) class driver + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_msc_core.h" +#include "usbh_msc_scsi.h" +#include "usbh_msc_bbb.h" +#include "usbh_pipe.h" +#include "usbh_transc.h" +#include +#include + +/* local function prototypes ('static') */ +static void usbh_msc_itf_deinit (usbh_host *uhost); +static usbh_status usbh_msc_itf_init (usbh_host *uhost); +static usbh_status usbh_msc_req (usbh_host *uhost); +static usbh_status usbh_msc_handle (usbh_host *uhost); +static usbh_status usbh_msc_maxlun_get (usbh_host *uhost, uint8_t *maxlun); +static usbh_status usbh_msc_rdwr_process(usbh_host *uhost, uint8_t lun); + +usbh_class usbh_msc = +{ + USB_CLASS_MSC, + usbh_msc_itf_init, + usbh_msc_itf_deinit, + usbh_msc_req, + usbh_msc_handle, + NULL, + NULL +}; + +/*! + \brief interface initialization for MSC class + \param[in] uhost: pointer to USB host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_msc_itf_init (usbh_host *uhost) +{ + usbh_status status = USBH_OK; + + uint8_t interface = usbh_interface_find(&uhost->dev_prop, MSC_CLASS, USB_MSC_SUBCLASS_SCSI, MSC_PROTOCOL); + + if (0xFFU == interface) { + uhost->usr_cb->dev_not_supported(); + + status = USBH_FAIL; + } else { + static usbh_msc_handler msc_handler; + + memset((void*)&msc_handler, 0U, sizeof(usbh_msc_handler)); + + uhost->active_class->class_data = (void *)&msc_handler; + + usbh_interface_select(&uhost->dev_prop, interface); + + usb_desc_ep *ep_desc = &uhost->dev_prop.cfg_desc_set.itf_desc_set[interface][0].ep_desc[0]; + + if (ep_desc->bEndpointAddress & 0x80U) { + msc_handler.ep_in = ep_desc->bEndpointAddress; + msc_handler.ep_size_in = ep_desc->wMaxPacketSize; + } else { + msc_handler.ep_out = ep_desc->bEndpointAddress; + msc_handler.ep_size_out = ep_desc->wMaxPacketSize; + } + + ep_desc = &uhost->dev_prop.cfg_desc_set.itf_desc_set[interface][0].ep_desc[1]; + + if(ep_desc->bEndpointAddress & 0x80U) { + msc_handler.ep_in = ep_desc->bEndpointAddress; + msc_handler.ep_size_in = ep_desc->wMaxPacketSize; + } else { + msc_handler.ep_out = ep_desc->bEndpointAddress; + msc_handler.ep_size_out = ep_desc->wMaxPacketSize; + } + + msc_handler.state = MSC_INIT; + msc_handler.error = MSC_OK; + msc_handler.req_state = MSC_REQ_IDLE; + msc_handler.pipe_out = usbh_pipe_allocate(uhost->data, msc_handler.ep_out); + msc_handler.pipe_in = usbh_pipe_allocate(uhost->data, msc_handler.ep_in); + + usbh_msc_bbb_init(uhost); + + /* open the new channels */ + usbh_pipe_create (uhost->data, + &uhost->dev_prop, + msc_handler.pipe_out, + USB_EPTYPE_BULK, + msc_handler.ep_size_out); + + usbh_pipe_create (uhost->data, + &uhost->dev_prop, + msc_handler.pipe_in, + USB_EPTYPE_BULK, + msc_handler.ep_size_in); + + usbh_pipe_toggle_set (uhost->data, msc_handler.pipe_out, 0U); + usbh_pipe_toggle_set (uhost->data, msc_handler.pipe_in, 0U); + } + + return status; +} + +/*! + \brief deinitialize interface by freeing host channels allocated to interface + \param[in] uhost: pointer to USB host + \param[out] none + \retval operation status +*/ +void usbh_msc_itf_deinit (usbh_host *uhost) +{ + usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; + + if (msc->pipe_out) { + usb_pipe_halt (uhost->data, msc->pipe_out); + usbh_pipe_free (uhost->data, msc->pipe_out); + + msc->pipe_out = 0U; + } + + if (msc->pipe_in) { + usb_pipe_halt (uhost->data, msc->pipe_in); + usbh_pipe_free (uhost->data, msc->pipe_in); + + msc->pipe_in = 0U; + } +} + +/*! + \brief initialize the MSC state machine + \param[in] uhost: pointer to USB host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_msc_req (usbh_host *uhost) +{ + usbh_status status = USBH_BUSY; + usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; + + switch (msc->req_state) { + case MSC_REQ_IDLE: + case MSC_REQ_GET_MAX_LUN: + /* issue Get_MaxLun request */ + status = usbh_msc_maxlun_get (uhost, (uint8_t *)&msc->max_lun); + + if (USBH_OK == status) { + msc->max_lun = ((uint8_t)msc->max_lun > MSC_MAX_SUPPORTED_LUN) ? MSC_MAX_SUPPORTED_LUN : (uint8_t)msc->max_lun + 1U; + + for (uint8_t i = 0U; i < msc->max_lun; i++) { + msc->unit[i].prev_ready_state = USBH_FAIL; + msc->unit[i].state_changed = 0U; + } + } else { + if (USBH_NOT_SUPPORTED == status) { + msc->max_lun = 0U; + status = USBH_OK; + } + } + break; + + case MSC_REQ_ERROR: + /* issue clear feature request */ + if (USBH_OK == usbh_clrfeature(uhost, 0x00U, uhost->control.pipe_out_num)) { + msc->req_state = msc->prev_req_state; + } + break; + + default: + break; + } + + return status; +} + +/*! + \brief MSC state machine handler + \param[in] uhost: pointer to USB host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_msc_handle (usbh_host *uhost) +{ + usbh_status status = USBH_BUSY; + uint8_t scsi_status = USBH_BUSY; + uint8_t ready_status = USBH_BUSY; + usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; + + + switch (msc->state) { + case MSC_INIT: + if (msc->cur_lun < msc->max_lun) { + msc->unit[msc->cur_lun].error = MSC_NOT_READY; + + switch (msc->unit[msc->cur_lun].state) { + case MSC_INIT: + msc->unit[msc->cur_lun].state = MSC_READ_INQUIRY; + msc->timer = uhost->control.timer; + break; + + case MSC_READ_INQUIRY: + scsi_status = usbh_msc_scsi_inquiry (uhost, msc->cur_lun, &msc->unit[msc->cur_lun].inquiry); + + if (USBH_OK == scsi_status) { + msc->unit[msc->cur_lun].state = MSC_TEST_UNIT_READY; + } else if(scsi_status == USBH_FAIL) { + msc->unit[msc->cur_lun].state = MSC_REQUEST_SENSE; + } else { + if(scsi_status == USBH_UNRECOVERED_ERROR) { + msc->unit[msc->cur_lun].state = MSC_IDLE; + msc->unit[msc->cur_lun].error = MSC_ERROR; + } + } + break; + + case MSC_TEST_UNIT_READY: + /* issue SCSI command TestUnitReady */ + ready_status = usbh_msc_test_unitready (uhost, msc->cur_lun); + + if (USBH_OK == ready_status) { + if (USBH_OK != msc->unit[msc->cur_lun].prev_ready_state) { + msc->unit[msc->cur_lun].state_changed = 1U; + } else { + msc->unit[msc->cur_lun].state_changed = 0U; + } + + msc->unit[msc->cur_lun].state = MSC_READ_CAPACITY10; + msc->unit[msc->cur_lun].error = MSC_OK; + msc->unit[msc->cur_lun].prev_ready_state = USBH_OK; + } else if(USBH_FAIL == ready_status) { + if(USBH_FAIL != msc->unit[msc->cur_lun].prev_ready_state) { + msc->unit[msc->cur_lun].state_changed = 1U; + } else { + msc->unit[msc->cur_lun].state_changed = 0U; + } + + msc->unit[msc->cur_lun].state = MSC_REQUEST_SENSE; + msc->unit[msc->cur_lun].error = MSC_NOT_READY; + msc->unit[msc->cur_lun].prev_ready_state = USBH_FAIL; + } else { + if(USBH_UNRECOVERED_ERROR == ready_status) { + msc->unit[msc->cur_lun].state = MSC_IDLE; + msc->unit[msc->cur_lun].error = MSC_ERROR; + } + } + break; + + case MSC_READ_CAPACITY10: + /* issue READ_CAPACITY10 SCSI command */ + scsi_status = usbh_msc_read_capacity10 (uhost, msc->cur_lun, &msc->unit[msc->cur_lun].capacity); + + if (USBH_OK == scsi_status) { + if (1U == msc->unit[msc->cur_lun].state_changed) { + } + msc->unit[msc->cur_lun].state = MSC_IDLE; + msc->unit[msc->cur_lun].error = MSC_OK; + msc->cur_lun ++; + } else if(USBH_FAIL == scsi_status) { + msc->unit[msc->cur_lun].state = MSC_REQUEST_SENSE; + } else { + if(USBH_UNRECOVERED_ERROR == scsi_status) { + msc->unit[msc->cur_lun].state = MSC_IDLE; + msc->unit[msc->cur_lun].error = MSC_ERROR; + } + } + break; + + case MSC_REQUEST_SENSE: + /* issue RequestSense SCSI command for retrieving error code */ + scsi_status = usbh_msc_request_sense (uhost, msc->cur_lun, &msc->unit[msc->cur_lun].sense); + if (USBH_OK == scsi_status) { + if ((msc->unit[msc->cur_lun].sense.SenseKey == UNIT_ATTENTION) || (msc->unit[msc->cur_lun].sense.SenseKey == NOT_READY)) { + if (((uhost->control.timer > msc->timer) && ((uhost->control.timer - msc->timer) < 10000U)) \ + || ((uhost->control.timer < msc->timer) && ((uhost->control.timer + 0x3FFFU - msc->timer) < 10000U))) { + msc->unit[msc->cur_lun].state = MSC_TEST_UNIT_READY; + break; + } + } + + msc->unit[msc->cur_lun].state = MSC_IDLE; + msc->cur_lun++; + } else if (USBH_FAIL == scsi_status) { + msc->unit[msc->cur_lun].state = MSC_UNRECOVERED_ERROR; + } else { + if (MSC_UNRECOVERED_ERROR == scsi_status) { + msc->unit[msc->cur_lun].state = MSC_IDLE; + msc->unit[msc->cur_lun].error = MSC_ERROR; + } + } + break; + + case MSC_UNRECOVERED_ERROR: + msc->cur_lun++; + break; + + default: + break; + } + } else { + msc->cur_lun = 0U; + msc->state = MSC_IDLE; + } + break; + + case MSC_IDLE: + uhost->usr_cb->dev_user_app(); + status = USBH_OK; + break; + + default: + break; + } + + return status; +} + +/*! + \brief get max lun of the mass storage device + \param[in] uhost: pointer to USB host + \param[in] maxlun: pointer to max lun + \param[out] none + \retval operation status +*/ +static usbh_status usbh_msc_maxlun_get (usbh_host *uhost, uint8_t *maxlun) +{ + usbh_status status = USBH_BUSY; + + if (uhost->control.ctl_state == CTL_IDLE) { + uhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_IN | USB_REQTYPE_CLASS | USB_RECPTYPE_ITF, + .bRequest = BBB_GET_MAX_LUN, + .wValue = 0U, + .wIndex = 0U, + .wLength = 1U + }; + + usbh_ctlstate_config (uhost, maxlun, 1U); + } + + status = usbh_ctl_handler (uhost); + + return status; +} + +/*! + \brief get max lun of the mass storage device + \param[in] uhost: pointer to USB host + \param[in] lun: logic unit number + \param[out] none + \retval operation status +*/ +static usbh_status usbh_msc_rdwr_process(usbh_host *uhost, uint8_t lun) +{ + usbh_status error = USBH_BUSY; + usbh_status scsi_status = USBH_BUSY; + usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; + + /* switch msc req state machine */ + switch (msc->unit[lun].state) { + case MSC_READ: + scsi_status = usbh_msc_read10(uhost, lun, NULL, 0U, 0U); + + if (USBH_OK == scsi_status) { + msc->unit[lun].state = MSC_IDLE; + error = USBH_OK; + } else if (USBH_FAIL == scsi_status) { + msc->unit[lun].state = MSC_REQUEST_SENSE; + } else { + if (USBH_UNRECOVERED_ERROR == scsi_status) { + msc->unit[lun].state = MSC_UNRECOVERED_ERROR; + error = USBH_FAIL; + } + } + break; + + case MSC_WRITE: + scsi_status = usbh_msc_write10(uhost, lun, NULL, 0U, 0U); + + if (USBH_OK == scsi_status) { + msc->unit[lun].state = MSC_IDLE; + error = USBH_OK; + } else if (USBH_FAIL == scsi_status) { + msc->unit[lun].state = MSC_REQUEST_SENSE; + } else { + if (USBH_UNRECOVERED_ERROR == scsi_status) { + msc->unit[lun].state = MSC_UNRECOVERED_ERROR; + error = USBH_FAIL; + } + } + break; + + case MSC_REQUEST_SENSE: + scsi_status = usbh_msc_request_sense (uhost, lun, &msc->unit[lun].sense); + + if (USBH_OK == scsi_status) { + msc->unit[lun].state = MSC_IDLE; + msc->unit[lun].error = MSC_ERROR; + + error = USBH_FAIL; + } + + if (USBH_FAIL == scsi_status) { + } else { + if (USBH_UNRECOVERED_ERROR == scsi_status) { + msc->unit[lun].state = MSC_UNRECOVERED_ERROR; + error = USBH_FAIL; + } + } + break; + + default: + break; + } + + return error; +} + +/*! + \brief get lun information + \param[in] uhost: pointer to USB host + \param[in] lun: logic unit number + \param[in] info: pointer to lun information + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_lun_info_get (usbh_host *uhost, uint8_t lun, msc_lun *info) +{ + usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; + + if (HOST_CLASS_HANDLER == uhost->cur_state) { + memcpy(info, &msc->unit[lun], sizeof(msc_lun)); + + return USBH_OK; + } else { + return USBH_FAIL; + } +} + +/*! + \brief handle msc read operation + \param[in] uhost: pointer to USB host + \param[in] lun: logic unit number + \param[in] address: data address + \param[in] pbuf: pointer to data buffer + \param[in] length: buffer length + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_read (usbh_host *uhost, + uint8_t lun, + uint32_t address, + uint8_t *pbuf, + uint32_t length) +{ + uint32_t timeout = 0U; + usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; + usb_core_driver *udev = (usb_core_driver *)uhost->data; + + if ((0U == udev->host.connect_status) || + (HOST_CLASS_HANDLER != uhost->cur_state) || + (MSC_IDLE != msc->unit[lun].state)) { + return USBH_FAIL; + } + + msc->state = MSC_READ; + msc->unit[lun].state = MSC_READ; + msc->rw_lun = lun; + + usbh_msc_read10(uhost, lun, pbuf, address, length); + + timeout = uhost->control.timer; + + while (USBH_BUSY == usbh_msc_rdwr_process(uhost, lun)) { + if (((uhost->control.timer > timeout) && ((uhost->control.timer - timeout) > (1000U * length))) \ + || ((uhost->control.timer < timeout) && ((uhost->control.timer + 0x3FFFU - timeout) > (1000U * length))) \ + || (0U == udev->host.connect_status)){ + msc->state = MSC_IDLE; + return USBH_FAIL; + } + } + + msc->state = MSC_IDLE; + + return USBH_OK; +} + +/*! + \brief handle msc write operation + \param[in] uhost: pointer to USB host + \param[in] lun: logic unit number + \param[in] address: data address + \param[in] pbuf: pointer to data buffer + \param[in] length: buffer length + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_write (usbh_host *uhost, + uint8_t lun, + uint32_t address, + uint8_t *pbuf, + uint32_t length) +{ + uint32_t timeout = 0U; + usb_core_driver *udev = (usb_core_driver *)uhost->data; + usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; + + if ((0U == udev->host.connect_status) || + (HOST_CLASS_HANDLER != uhost->cur_state) || + (MSC_IDLE != msc->unit[lun].state)) { + return USBH_FAIL; + } + + msc->state = MSC_WRITE; + msc->unit[lun].state = MSC_WRITE; + msc->rw_lun = lun; + + usbh_msc_write10(uhost, lun, pbuf, address, length); + + timeout = uhost->control.timer; + + while (USBH_BUSY == usbh_msc_rdwr_process(uhost, lun)) { + if (((uhost->control.timer > timeout) && ((uhost->control.timer - timeout) > (1000U * length))) \ + || ((uhost->control.timer < timeout) && ((uhost->control.timer + 0x3FFFU - timeout) > (1000U * length))) \ + || (0U == udev->host.connect_status)) { + msc->state = MSC_IDLE; + return USBH_FAIL; + } + } + + msc->state = MSC_IDLE; + + return USBH_OK; +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Source/usbh_msc_fatfs.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Source/usbh_msc_fatfs.c new file mode 100644 index 00000000..74c30c13 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Source/usbh_msc_fatfs.c @@ -0,0 +1,235 @@ +/*! + \file usbh_msc_fatfs.c + \brief USB MSC host FATFS related functions + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usb_conf.h" +#include "usbh_msc_core.h" + +#include "ff.h" +#include "diskio.h" + +static volatile DSTATUS state = STA_NOINIT; /* disk status */ + +extern usbh_host usb_host; + +/*! + \brief initialize the disk drive + \param[in] drv: physical drive number (0) + \param[out] none + \retval operation status +*/ +DSTATUS disk_initialize (BYTE drv) +{ + usb_core_driver *udev = (usb_core_driver *)usb_host.data; + + if (udev->host.connect_status) { + state &= ~STA_NOINIT; + } + + return state; +} + +/*! + \brief get disk status + \param[in] drv: physical drive number (0) + \param[out] none + \retval operation status +*/ +DSTATUS disk_status (BYTE drv) +{ + if (drv) { + return STA_NOINIT; /* supports only single drive */ + } + + return state; +} + +/*! + \brief read sectors + \param[in] drv: physical drive number (0) + \param[in] buff: pointer to the data buffer to store read data + \param[in] sector: start sector number (LBA) + \param[in] count: sector count (1..255) + \param[out] none + \retval operation status +*/ +DRESULT disk_read (BYTE drv, BYTE *buff, DWORD sector, UINT count) +{ + BYTE status = USBH_OK; + usb_core_driver *udev = (usb_core_driver *)usb_host.data; + + if (drv || (!count)) { + return RES_PARERR; + } + + if (state & STA_NOINIT) { + return RES_NOTRDY; + } + + if (udev->host.connect_status) { + do { + status = usbh_msc_read (&usb_host, drv, sector, buff, count); + + if (!udev->host.connect_status) { + return RES_ERROR; + } + } while(status == USBH_BUSY); + } + + if (status == USBH_OK) { + return RES_OK; + } + + return RES_ERROR; +} + +#if _READONLY == 0U + +/*! + \brief write sectors + \param[in] drv: physical drive number (0) + \param[in] buff: pointer to the data buffer to store read data + \param[in] sector: start sector number (LBA) + \param[in] count: sector count (1..255) + \param[out] none + \retval operation status +*/ +DRESULT disk_write (BYTE drv, const BYTE *buff, DWORD sector, UINT count) +{ + BYTE status = USBH_OK; + usb_core_driver *udev = (usb_core_driver *)usb_host.data; + + if ((!count) || drv) { + return RES_PARERR; + } + + if (state & STA_NOINIT) { + return RES_NOTRDY; + } + + if (state & STA_PROTECT) { + return RES_WRPRT; + } + + if (udev->host.connect_status) { + do { + status = usbh_msc_write (&usb_host, drv, sector, (BYTE*)buff, count); + + if (!udev->host.connect_status) { + return RES_ERROR; + } + } while(status == USBH_BUSY); + } + + if (status == USBH_OK) { + return RES_OK; + } + + return RES_ERROR; +} + +#endif /* _READONLY == 0 */ + +/*! + \brief I/O control function + \param[in] drv: physical drive number (0) + \param[in] ctrl: control code + \param[in] buff: pointer to the data buffer to store read data + \param[out] none + \retval operation status +*/ +DRESULT disk_ioctl (BYTE drv, BYTE ctrl, void *buff) +{ + DRESULT res = RES_OK; + msc_lun info; + + if (drv) { + return RES_PARERR; + } + + res = RES_ERROR; + + if (state & STA_NOINIT) { + return RES_NOTRDY; + } + + switch (ctrl) { + /* make sure that no pending write process */ + case CTRL_SYNC: + res = RES_OK; + break; + + /* get number of sectors on the disk (dword) */ + case GET_SECTOR_COUNT: + if (USBH_OK == usbh_msc_lun_info_get(&usb_host, drv, &info)) { + *(DWORD*)buff = (DWORD)info.capacity.block_nbr; + res = RES_OK; + } + break; + + /* get r/w sector size (word) */ + case GET_SECTOR_SIZE: + if (USBH_OK == usbh_msc_lun_info_get(&usb_host, drv, &info)) { + *(WORD*)buff = (DWORD)info.capacity.block_size; + res = RES_OK; + } + break; + + /* get erase block size in unit of sector (dword) */ + case GET_BLOCK_SIZE: + *(DWORD *)buff = 512U; + break; + + default: + res = RES_PARERR; + break; + } + + return res; +} + +/*! + \brief get fat time + \param[in] none + \param[out] none + \retval time value +*/ +DWORD get_fattime (void) +{ + return ((DWORD)(2019U - 1980U) << 25U) /* year 2019 */ + | ((DWORD)1U << 21U) /* month 1 */ + | ((DWORD)1U << 16U) /* day 1 */ + | ((DWORD)0U << 11U) /* hour 0 */ + | ((DWORD)0U << 5U) /* min 0 */ + | ((DWORD)0U >> 1U); /* sec 0 */ +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Source/usbh_msc_scsi.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Source/usbh_msc_scsi.c new file mode 100644 index 00000000..40702cc0 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/class/msc/Source/usbh_msc_scsi.c @@ -0,0 +1,400 @@ +/*! + \file usbh_msc_scsi.c + \brief USB MSC SCSI commands implementing + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_msc_core.h" +#include "usbh_msc_scsi.h" +#include "usbh_msc_bbb.h" + +#include + +/*! + \brief send 'Inquiry' command to the device + \param[in] uhost: pointer to USB host handler + \param[in] lun: logic unit number + \param[in] inquiry: pointer to the inquiry structure + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_scsi_inquiry (usbh_host *uhost, uint8_t lun, scsi_std_inquiry_data *inquiry) +{ + usbh_status error = USBH_FAIL; + usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; + + switch (msc->bbb.cmd_state) { + case BBB_CMD_SEND: + /* prepare the cbw and relevant field*/ + msc->bbb.cbw.field.dCBWDataTransferLength = STANDARD_INQUIRY_DATA_LEN; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_IN; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; + + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_LENGTH); + + msc->bbb.cbw.field.CBWCB[0] = SCSI_INQUIRY; + msc->bbb.cbw.field.CBWCB[1] = (lun << 5U); + msc->bbb.cbw.field.CBWCB[4] = 0x24U; + + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; + msc->bbb.pbuf = (uint8_t *)(void *)msc->bbb.data; + error = USBH_BUSY; + break; + + case BBB_CMD_WAIT: + error = usbh_msc_bbb_process(uhost, lun); + + if (USBH_OK == error) { + memset(inquiry, 0U, sizeof(scsi_std_inquiry_data)); + + /* assign inquiry data */ + inquiry->device_type = msc->bbb.pbuf[0] & 0x1FU; + inquiry->peripheral_qualifier = msc->bbb.pbuf[0] >> 5U; + + if (0x80U == ((uint32_t)msc->bbb.pbuf[1] & 0x80U)) { + inquiry->removable_media = 1U; + } else { + inquiry->removable_media = 0U; + } + + memcpy (inquiry->vendor_id, &msc->bbb.pbuf[8], 8U); + memcpy (inquiry->product_id, &msc->bbb.pbuf[16], 16U); + memcpy (inquiry->revision_id, &msc->bbb.pbuf[32], 4U); + } + break; + + default: + break; + } + + return error; +} + +/*! + \brief send 'Test unit ready' command to the device + \param[in] uhost: pointer to USB host handler + \param[in] lun: logic unit number + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_test_unitready (usbh_host *uhost, uint8_t lun) +{ + usbh_status status = USBH_FAIL; + usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; + + + switch (msc->bbb.cmd_state) { + case BBB_CMD_SEND: + /* prepare the CBW and relevant field */ + msc->bbb.cbw.field.dCBWDataTransferLength = CBW_LENGTH_TEST_UNIT_READY; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_OUT; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; + + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + + msc->bbb.cbw.field.CBWCB[0] = SCSI_TEST_UNIT_READY; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; + + status = USBH_BUSY; + break; + + case BBB_CMD_WAIT: + status = usbh_msc_bbb_process(uhost, lun); + break; + + default: + break; + } + + return status; +} + +/*! + \brief send the read capacity command to the device + \param[in] uhost: pointer to USB host handler + \param[in] lun: logic unit number + \param[in] capacity: pointer to SCSI capacity + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_read_capacity10 (usbh_host *uhost, uint8_t lun, scsi_capacity *capacity) +{ + usbh_status status = USBH_FAIL; + usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; + + switch (msc->bbb.cmd_state) { + case BBB_CMD_SEND: + /* prepare the CBW and relevant field */ + msc->bbb.cbw.field.dCBWDataTransferLength = READ_CAPACITY10_DATA_LEN; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_IN; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; + + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + + msc->bbb.cbw.field.CBWCB[0] = SCSI_READ_CAPACITY10; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; + msc->bbb.pbuf = (uint8_t *)(void *)msc->bbb.data; + + status = USBH_BUSY; + break; + + case BBB_CMD_WAIT: + status = usbh_msc_bbb_process(uhost, lun); + + if (USBH_OK == status) { + capacity->block_nbr = msc->bbb.pbuf[3] | \ + ((uint32_t)msc->bbb.pbuf[2] << 8U) | \ + ((uint32_t)msc->bbb.pbuf[1] << 16U) | \ + ((uint32_t)msc->bbb.pbuf[0] << 24U); + + capacity->block_size = (uint16_t)(msc->bbb.pbuf[7] | ((uint32_t)msc->bbb.pbuf[6] << 8U)); + } + break; + + default: + break; + } + + return status; +} + +/*! + \brief send the mode sense6 command to the device + \param[in] uhost: pointer to USB host handler + \param[in] lun: logic unit number + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_mode_sense6 (usbh_host *uhost, uint8_t lun) +{ + usbh_status status = USBH_FAIL; + usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; + + + switch (msc->bbb.cmd_state) { + case BBB_CMD_SEND: + /* prepare the CBW and relevant field */ + msc->bbb.cbw.field.dCBWDataTransferLength = XFER_LEN_MODE_SENSE6; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_IN; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; + + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + + msc->bbb.cbw.field.CBWCB[0] = SCSI_MODE_SENSE6; + msc->bbb.cbw.field.CBWCB[2] = MODE_SENSE_PAGE_CONTROL_FIELD | MODE_SENSE_PAGE_CODE; + msc->bbb.cbw.field.CBWCB[4] = XFER_LEN_MODE_SENSE6; + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; + msc->bbb.pbuf = (uint8_t *)(void *)msc->bbb.data; + + status = USBH_BUSY; + break; + + case BBB_CMD_WAIT: + status = usbh_msc_bbb_process(uhost, lun); + + if (USBH_OK == status) { + if (msc->bbb.data[2] & MASK_MODE_SENSE_WRITE_PROTECT) { + + } else { + + } + } + break; + + default: + break; + } + + + return status; +} + +/*! + \brief send the Request Sense command to the device + \param[in] uhost: pointer to USB host handler + \param[in] lun: logic unit number + \param[in] sense_data: pointer to sense data + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_request_sense (usbh_host *uhost, uint8_t lun, msc_scsi_sense *sense_data) +{ + usbh_status status = USBH_FAIL; + usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; + + switch (msc->bbb.cmd_state) { + case BBB_CMD_SEND: + /* prepare the cbw and relevant field */ + msc->bbb.cbw.field.dCBWDataTransferLength = ALLOCATION_LENGTH_REQUEST_SENSE; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_IN; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; + + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + + msc->bbb.cbw.field.CBWCB[0] = SCSI_REQUEST_SENSE; + msc->bbb.cbw.field.CBWCB[1] = (lun << 5U); + msc->bbb.cbw.field.CBWCB[4] = ALLOCATION_LENGTH_REQUEST_SENSE; + + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; + msc->bbb.pbuf = (uint8_t *)(void *)msc->bbb.data; + + status = USBH_BUSY; + break; + + case BBB_CMD_WAIT: + status = usbh_msc_bbb_process(uhost, lun); + + if (status == USBH_OK) { + /* get sense data */ + sense_data->SenseKey = msc->bbb.pbuf[2] & 0x0FU; + sense_data->ASC = msc->bbb.pbuf[12]; + sense_data->ASCQ = msc->bbb.pbuf[13]; + } + break; + + default: + break; + } + + return status; +} + +/*! + \brief send the write10 command to the device + \param[in] uhost: pointer to USB host handler + \param[in] lun: logic unit number + \param[in] data_buf: data buffer contains the data to write + \param[in] addr: address to which the data will be written + \param[in] sector_num: number of sector to be written + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_write10 (usbh_host *uhost, uint8_t lun, uint8_t *data_buf, uint32_t addr, uint32_t sector_num) +{ + usbh_status status = USBH_FAIL; + usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; + + switch (msc->bbb.cmd_state) { + case BBB_CMD_SEND: + msc->bbb.cbw.field.dCBWDataTransferLength = sector_num * msc->unit[lun].capacity.block_size; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_OUT; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; + + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + + msc->bbb.cbw.field.CBWCB[0] = SCSI_WRITE10; + + /* logical block address */ + msc->bbb.cbw.field.CBWCB[2] = (((uint8_t*)&addr)[3]); + msc->bbb.cbw.field.CBWCB[3] = (((uint8_t*)&addr)[2]); + msc->bbb.cbw.field.CBWCB[4] = (((uint8_t*)&addr)[1]); + msc->bbb.cbw.field.CBWCB[5] = (((uint8_t*)&addr)[0]); + + /* transfer length */ + msc->bbb.cbw.field.CBWCB[7] = (((uint8_t *)§or_num)[1]); + msc->bbb.cbw.field.CBWCB[8] = (((uint8_t *)§or_num)[0]); + + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; + msc->bbb.pbuf = data_buf; + + status = USBH_BUSY; + break; + + case BBB_CMD_WAIT: + status = usbh_msc_bbb_process(uhost, lun); + break; + + default: + break; + } + + return status; +} + +/*! + \brief send the read10 command to the device + \param[in] uhost: pointer to USB host handler + \param[in] lun: logic unit number + \param[in] data_buf: data buffer contains the data to write + \param[in] addr: address to which the data will be read + \param[in] sector_num: number of sector to be read + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_read10 (usbh_host *uhost, uint8_t lun, uint8_t *data_buf, uint32_t addr, uint32_t sector_num) +{ + usbh_status status = USBH_FAIL; + usbh_msc_handler *msc = (usbh_msc_handler *)uhost->active_class->class_data; + + switch (msc->bbb.cmd_state) { + case BBB_CMD_SEND: + /* prepare the CBW and relevant field */ + msc->bbb.cbw.field.dCBWDataTransferLength = sector_num * msc->unit[lun].capacity.block_size; + msc->bbb.cbw.field.bmCBWFlags = USB_TRX_IN; + msc->bbb.cbw.field.bCBWCBLength = CBW_LENGTH; + + memset(msc->bbb.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + + msc->bbb.cbw.field.CBWCB[0] = SCSI_READ10; + + /* logical block address */ + msc->bbb.cbw.field.CBWCB[2] = (((uint8_t*)&addr)[3]); + msc->bbb.cbw.field.CBWCB[3] = (((uint8_t*)&addr)[2]); + msc->bbb.cbw.field.CBWCB[4] = (((uint8_t*)&addr)[1]); + msc->bbb.cbw.field.CBWCB[5] = (((uint8_t*)&addr)[0]); + + /* transfer length */ + msc->bbb.cbw.field.CBWCB[7] = (((uint8_t *)§or_num)[1]); + msc->bbb.cbw.field.CBWCB[8] = (((uint8_t *)§or_num)[0]); + + msc->bbb.state = BBB_SEND_CBW; + msc->bbb.cmd_state = BBB_CMD_WAIT; + msc->bbb.pbuf = data_buf; + + status = USBH_BUSY; + break; + + case BBB_CMD_WAIT: + status = usbh_msc_bbb_process(uhost, lun); + break; + + default: + break; + } + + return status; +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Include/usbh_core.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Include/usbh_core.h new file mode 100644 index 00000000..873b22eb --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Include/usbh_core.h @@ -0,0 +1,279 @@ +/*! + \file usbh_core.h + \brief USB host core state machine header file + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_CORE_H +#define __USBH_CORE_H + +#include "usbh_conf.h" +#include "drv_usb_host.h" + +#define MSC_CLASS 0x08U +#define HID_CLASS 0x03U +#define MSC_PROTOCOL 0x50U +#define CBI_PROTOCOL 0x01U + +#define USBH_MAX_ERROR_COUNT 3U + +#define USBH_DEV_ADDR_DEFAULT 0U +#define USBH_DEV_ADDR 1U + +typedef enum +{ + USBH_OK = 0U, + USBH_BUSY, + USBH_FAIL, + USBH_NOT_SUPPORTED, + USBH_UNRECOVERED_ERROR, + USBH_SPEED_UNKNOWN_ERROR, + USBH_APPLY_DEINIT +} usbh_status; + +/* USB host global operation state */ +typedef enum +{ + HOST_DEFAULT = 0U, + HOST_DETECT_DEV_SPEED, + HOST_DEV_CONNECT, + HOST_DEV_DETACHED, + HOST_DEV_ENUM, + HOST_PWR_FEATURE_SET, + HOST_CLASS_CHECK, + HOST_CLASS_ENUM, + HOST_CLASS_HANDLER, + HOST_USER_INPUT, + HOST_SUSPEND, + HOST_WAKEUP, + HOST_ERROR +} usb_host_state; + +/* USB host enumeration state */ +typedef enum +{ + ENUM_DEFAULT = 0U, + ENUM_GET_DEV_DESC, + ENUM_SET_ADDR, + ENUM_GET_CFG_DESC, + ENUM_GET_CFG_DESC_SET, + ENUM_GET_STR_DESC, +#ifdef USB_MTP + ENUM_GET_MTP_STR, +#endif + ENUM_SET_CONFIGURATION, + ENUM_DEV_CONFIGURED +} usbh_enum_state; + +/* USB host control transfer state */ +typedef enum +{ + CTL_IDLE = 0U, + CTL_SETUP, + CTL_SETUP_WAIT, + CTL_DATA_IN, + CTL_DATA_IN_WAIT, + CTL_DATA_OUT, + CTL_DATA_OUT_WAIT, + CTL_STATUS_IN, + CTL_STATUS_IN_WAIT, + CTL_STATUS_OUT, + CTL_STATUS_OUT_WAIT, + CTL_ERROR, + CTL_FINISH +} usbh_ctl_state; + +/* user action state */ +typedef enum +{ + USR_IN_NO_RESP = 0U, + USR_IN_RESP_OK = 1U, +} usbh_user_status; + +/* USB host wakeup mode */ +typedef enum +{ + NORMAL_WORK = 0U, + GENERAL_WAKEUP = 1U, + REMOTE_WAKEUP = 2, +} usbh_wakeup_mode; + +/* control transfer information */ +typedef struct _usbh_control +{ + uint8_t pipe_in_num; + uint8_t pipe_out_num; + uint8_t max_len; + uint8_t error_count; + + uint8_t *buf; + uint16_t ctl_len; + uint16_t timer; + + usb_setup setup; + usbh_ctl_state ctl_state; +} usbh_control; + +/* USB interface descriptor set */ +typedef struct _usb_desc_itf_set +{ + usb_desc_itf itf_desc; + usb_desc_ep ep_desc[USBH_MAX_EP_NUM]; +} usb_desc_itf_set; + +/* USB configure descriptor set */ +typedef struct _usb_desc_cfg_set +{ + usb_desc_config cfg_desc; + usb_desc_itf_set itf_desc_set[USBH_MAX_INTERFACES_NUM][USBH_MAX_ALT_SETTING]; +} usb_desc_cfg_set; + +/* USB device property */ +typedef struct +{ + uint8_t data[USBH_DATA_BUF_MAX_LEN]; + uint8_t cur_itf; + uint8_t addr; + + uint32_t speed; + + usb_desc_dev dev_desc; + usb_desc_cfg_set cfg_desc_set; + +#if (USBH_CFG_DESC_KEEP == 1U) + uint8_t cfgdesc_rawdata[USBH_CFGSET_MAX_LEN]; +#endif /* (USBH_CFG_DESC_KEEP == 1U) */ +} usb_dev_prop; + +struct _usbh_host; + +/* device class callbacks */ +typedef struct +{ + uint8_t class_code; /*!< USB class type */ + + usbh_status (*class_init) (struct _usbh_host *phost); + void (*class_deinit) (struct _usbh_host *phost); + usbh_status (*class_requests) (struct _usbh_host *phost); + usbh_status (*class_machine) (struct _usbh_host *phost); + usbh_status (*class_sof) (struct _usbh_host *uhost); + + void *class_data; +} usbh_class; + +/* user callbacks */ +typedef struct +{ + void (*dev_init) (void); + void (*dev_deinit) (void); + void (*dev_attach) (void); + void (*dev_reset) (void); + void (*dev_detach) (void); + void (*dev_over_currented) (void); + void (*dev_speed_detected) (uint32_t dev_speed); + void (*dev_devdesc_assigned) (void *dev_desc); + void (*dev_address_set) (void); + + void (*dev_cfgdesc_assigned) (usb_desc_config *cfg_desc, + usb_desc_itf *itf_desc, + usb_desc_ep *ep_desc); + + void (*dev_mfc_str) (void *mfc_str); + void (*dev_prod_str) (void *prod_str); + void (*dev_seral_str) (void *serial_str); + void (*dev_enumerated) (void); + usbh_user_status (*dev_user_input) (void); + int (*dev_user_app) (void); + void (*dev_not_supported) (void); + void (*dev_error) (void); +} usbh_user_cb; + +/* host information */ +typedef struct _usbh_host +{ + usb_host_state cur_state; /*!< host state machine value */ + usb_host_state backup_state; /*!< backup of previous state machine value */ + usbh_enum_state enum_state; /*!< enumeration state machine */ + usbh_control control; /*!< USB host control state machine */ + usb_dev_prop dev_prop; /*!< USB device property */ + + usbh_class *uclass[USBH_MAX_SUPPORTED_CLASS]; /*!< USB host supported class */ + usbh_class *active_class; /*!< USB active class */ + usbh_user_cb *usr_cb; /*!< USB user callback */ + + uint8_t class_num; /*!< USB class number */ + + void *data; /*!< used for... */ + +#if USB_LOW_POWER + uint8_t suspend_flag; /*!< host suspend flag */ + uint8_t dev_supp_remote_wkup; /*!< record device remote wakeup function */ + usbh_wakeup_mode wakeup_mode; /*!< record wakeup mode */ +#endif /* USB_LOW_POWER*/ +} usbh_host; + +/*! + \brief get USB URB state + \param[in] udev: pointer to USB core instance + \param[in] pp_num: pipe number + \param[out] none + \retval none +*/ +static inline usb_urb_state usbh_urbstate_get (usb_core_driver *udev, uint8_t pp_num) +{ + return udev->host.pipe[pp_num].urb_state; +} + +/*! + \brief get USB transfer data count + \param[in] udev: pointer to USB core instance + \param[in] pp_num: pipe number + \param[out] none + \retval none +*/ +static inline uint32_t usbh_xfercount_get (usb_core_driver *udev, uint8_t pp_num) +{ + return udev->host.backup_xfercount[pp_num]; +} + +/* function declarations */ +/* USB host stack initializations */ +void usbh_init (usbh_host *uhost, usbh_user_cb *user_cb); +/* USB host register device class */ +usbh_status usbh_class_register (usbh_host *uhost, usbh_class *puclass); +/* de-initialize USB host */ +usbh_status usbh_deinit (usbh_host *uhost); +/* USB host core main state machine process */ +void usbh_core_task (usbh_host *uhost); +/* handle the error on USB host side */ +void usbh_error_handler (usbh_host *uhost, usbh_status err_type); + +#endif /* __USBH_CORE_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Include/usbh_enum.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Include/usbh_enum.h new file mode 100644 index 00000000..e5e5c6fb --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Include/usbh_enum.h @@ -0,0 +1,70 @@ +/*! + \file usbh_enum.h + \brief USB host mode USB enumeration header file + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_ENUM_H +#define __USBH_ENUM_H + +#include "usbh_core.h" + +/* function declarations */ +/* configure USB control status parameters */ +void usbh_ctlstate_config (usbh_host *uhost, uint8_t *buf, uint16_t len); +/* get device descriptor from the USB device */ +usbh_status usbh_devdesc_get (usbh_host *uhost, uint8_t len); +/* get configuration descriptor from the USB device */ +usbh_status usbh_cfgdesc_get (usbh_host *uhost, uint16_t len); +/* get string descriptor from the USB device */ +usbh_status usbh_strdesc_get (usbh_host *uhost,uint8_t str_index, uint8_t *buf, uint16_t len); +/* set the address to the connected device */ +usbh_status usbh_setaddress (usbh_host *uhost, uint8_t dev_addr); +/* set the configuration value to the connected device */ +usbh_status usbh_setcfg (usbh_host *uhost, uint16_t config); +/* set the interface value to the connected device */ +usbh_status usbh_setinterface (usbh_host *uhost, uint8_t itf_num, uint8_t alter_setting); +/* set or enable a specific device feature */ +usbh_status usbh_setdevfeature (usbh_host *uhost, uint8_t feature_selector, uint16_t windex); +/* clear or disable a specific device feature */ +usbh_status usbh_clrdevfeature (usbh_host *uhost, uint8_t feature_selector, uint16_t windex); +/* clear or disable a specific feature */ +usbh_status usbh_clrfeature (usbh_host *uhost, uint8_t ep_addr, uint8_t pp_num); +/* get the next descriptor header */ +usb_desc_header *usbh_nextdesc_get (uint8_t *pbuf, uint16_t *ptr); +/* select an interface */ +usbh_status usbh_interface_select (usb_dev_prop *udev, uint8_t interface); +/* find the interface index for a specific class */ +uint8_t usbh_interface_find (usb_dev_prop *udev, uint8_t main_class, uint8_t sub_class, uint8_t protocol); +/* find the interface index for a specific class interface and alternate setting number */ +uint8_t usbh_interfaceindex_find (usb_dev_prop *udev, uint8_t interface_number, uint8_t alt_settings); + +#endif /* __USBH_ENUM_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Include/usbh_pipe.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Include/usbh_pipe.h new file mode 100644 index 00000000..a6f694c5 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Include/usbh_pipe.h @@ -0,0 +1,102 @@ +/*! + \file usbh_pipe.h + \brief USB host mode pipe header file + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_PIPE_H +#define __USBH_PIPE_H + +#include "usbh_core.h" + +/* host pipe maximum */ +#define HP_MAX 8U + +/* host pipe status */ +#define HP_OK 0x0000U +#define HP_USED 0x8000U +#define HP_ERROR 0xFFFFU +#define HP_USED_MASK 0x7FFFU + +/*! + \brief set toggle for a pipe + \param[in] udev: pointer to USB core instance + \param[in] pp_num: pipe number + \param[in] toggle: toggle (0/1) + \param[out] none + \retval operation status +*/ +__STATIC_INLINE void usbh_pipe_toggle_set (usb_core_driver *udev, uint8_t pp_num, uint8_t toggle) +{ + if (udev->host.pipe[pp_num].ep.dir) { + udev->host.pipe[pp_num].data_toggle_in = toggle; + } else { + udev->host.pipe[pp_num].data_toggle_out = toggle; + } +} + +/*! + \brief get toggle flag of pipe + \param[in] udev: pointer to USB core instance + \param[in] pp_num: pipe number + \param[out] none + \retval operation status +*/ +__STATIC_INLINE uint8_t usbh_pipe_toggle_get (usb_core_driver *udev, uint8_t pp_num) +{ + if (udev->host.pipe[pp_num].ep.dir) { + return udev->host.pipe[pp_num].data_toggle_in; + } else { + return udev->host.pipe[pp_num].data_toggle_out; + } +} + +/* function declarations */ +/* create a pipe */ +uint8_t usbh_pipe_create (usb_core_driver *udev, + usb_dev_prop *dev, + uint8_t pp_num, + uint8_t ep_type, + uint16_t ep_mpl); +/* modify a pipe */ +uint8_t usbh_pipe_update (usb_core_driver *udev, + uint8_t pp_num, + uint8_t dev_addr, + uint32_t dev_speed, + uint16_t ep_mpl); +/* allocate a new pipe */ +uint8_t usbh_pipe_allocate (usb_core_driver *udev, uint8_t ep_addr); +/* free a pipe */ +uint8_t usbh_pipe_free (usb_core_driver *udev, uint8_t pp_num); +/* delete all USB host pipe */ +uint8_t usbh_pipe_delete (usb_core_driver *udev); + +#endif /* __USBH_PIPE_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Include/usbh_transc.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Include/usbh_transc.h new file mode 100644 index 00000000..4bae775e --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Include/usbh_transc.h @@ -0,0 +1,50 @@ +/*! + \file usbh_transc.h + \brief USB host mode transactions header file + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_TRANSC_H +#define __USBH_TRANSC_H + +#include "usbh_core.h" + +/* function declarations */ +/* send the setup packet to the USB device */ +usbh_status usbh_ctlsetup_send (usb_core_driver *udev, uint8_t *buf, uint8_t pp_num); +/* send a data packet to the USB device */ +usbh_status usbh_data_send (usb_core_driver *udev, uint8_t *buf, uint8_t pp_num, uint16_t len); +/* receive a data packet from the USB device */ +usbh_status usbh_data_recev (usb_core_driver *udev, uint8_t *buf, uint8_t pp_num, uint16_t len); +/* USB control transfer handler */ +usbh_status usbh_ctl_handler (usbh_host *uhost); + +#endif /* __USBH_TRANSC_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Source/usbh_core.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Source/usbh_core.c new file mode 100644 index 00000000..4c2492f5 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Source/usbh_core.c @@ -0,0 +1,653 @@ +/*! + \file usbh_core.c + \brief USB host core state machine driver + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "drv_usbh_int.h" +#include "usbh_pipe.h" +#include "usbh_enum.h" + +#include + +usb_core_driver usbh_core; + +/* local function prototypes ('static') */ +static uint8_t usb_ev_sof (usbh_host *uhost); +static uint8_t usb_ev_connect (usbh_host *uhost); +static uint8_t usb_ev_disconnect (usbh_host *uhost); +static usbh_status usbh_enum_task (usbh_host *uhost); + +#if USB_LOW_POWER +static void usb_hwp_suspend (usb_core_driver *udev); +static void usb_hwp_resume (usb_core_driver *udev); +#endif /* USB_LOW_POWER */ + +usbh_ev_cb usbh_int_op = +{ + usb_ev_connect, + usb_ev_disconnect, + usb_ev_sof, +}; + +usbh_ev_cb *usbh_int_fop = &usbh_int_op; + +/*! + \brief USB host stack initializations + \param[in] uhost: pointer to USB host + \param[in] user_cb: pointer to user callback + \param[out] none + \retval none +*/ +void usbh_init (usbh_host *uhost, usbh_user_cb *user_cb) +{ + /* host deinitialization */ + usbh_deinit(uhost); + + uhost->usr_cb = user_cb; + + usbh_core.host.connect_status = 0U; + + for (uint8_t i = 0U; i < USBFS_MAX_TX_FIFOS; i++) { + usbh_core.host.pipe[i].err_count = 0U; + usbh_core.host.pipe[i].pp_status = PIPE_IDLE; + usbh_core.host.backup_xfercount[i] = 0U; + } + + usbh_core.host.pipe[0].ep.mps = 8U; + +#ifdef USE_USB_FS + usb_basic_init (&usbh_core.bp, &usbh_core.regs, USB_CORE_ENUM_FS); +#endif /* USE_USB_FS */ + +#ifndef DUAL_ROLE_MODE_ENABLED + usb_globalint_disable(&usbh_core.regs); + + usb_core_init (usbh_core.bp, &usbh_core.regs); + +#ifndef USE_OTG_MODE + usb_curmode_set (&usbh_core.regs, HOST_MODE); +#endif /* USE_OTG_MODE */ + + usb_host_init (&usbh_core); + + usb_globalint_enable(&usbh_core.regs); +#endif /* DUAL_ROLE_MODE_ENABLED */ + + /* link driver to the stack */ + usbh_core.host.data = (void *)uhost; + uhost->data = (void *)&usbh_core; + + /* upon initialize call usr call back */ + uhost->usr_cb->dev_init(); +} + +/*! + \brief USB host register device class + \param[in] uhost: pointer to USB host instance + \param[in] puclass: pointer to USB device class + \param[out] none + \retval operation status +*/ +usbh_status usbh_class_register (usbh_host *uhost, usbh_class *puclass) +{ + usbh_status status = USBH_OK; + + if (NULL != puclass) { + if (uhost->class_num < USBH_MAX_SUPPORTED_CLASS) { + uhost->uclass[uhost->class_num++] = puclass; + } else { + status = USBH_FAIL; + } + } else { + status = USBH_FAIL; + } + + return status; +} + +/*! + \brief deinitialize USB host + \param[in] uhost: pointer to USB host + \param[out] none + \retval operation status +*/ +usbh_status usbh_deinit(usbh_host *uhost) +{ + /* software initialize */ + uhost->cur_state = HOST_DEFAULT; + uhost->backup_state = HOST_DEFAULT; + uhost->enum_state = ENUM_DEFAULT; + + uhost->control.ctl_state = CTL_IDLE; + uhost->control.max_len = USB_FS_EP0_MAX_LEN; + + uhost->dev_prop.addr = USBH_DEV_ADDR_DEFAULT; + uhost->dev_prop.speed = PORT_SPEED_FULL; + uhost->dev_prop.cur_itf = 0xFFU; + + usbh_pipe_free(&usbh_core, uhost->control.pipe_in_num); + usbh_pipe_free(&usbh_core, uhost->control.pipe_out_num); + + return USBH_OK; +} + +/*! + \brief USB host core main state machine process + \param[in] uhost: pointer to USB host + \param[out] none + \retval none +*/ +void usbh_core_task (usbh_host *uhost) +{ + volatile usbh_status status = USBH_FAIL; + + /* check for host port events */ + if (((0U == usbh_core.host.connect_status) || (0U == usbh_core.host.port_enabled)) && (HOST_DEFAULT != uhost->cur_state)) { + if (uhost->cur_state != HOST_DEV_DETACHED) { + uhost->cur_state = HOST_DEV_DETACHED; + } + } + + switch (uhost->cur_state) { + case HOST_DEFAULT: + if (usbh_core.host.connect_status) { + uhost->cur_state = HOST_DETECT_DEV_SPEED; + + usb_mdelay (100U); + + usb_port_reset (&usbh_core); + + uhost->usr_cb->dev_reset(); + } + break; + + case HOST_DETECT_DEV_SPEED: + if (usbh_core.host.port_enabled) { + uhost->cur_state = HOST_DEV_CONNECT; + + uhost->dev_prop.speed = usb_curspeed_get (&usbh_core); + + uhost->usr_cb->dev_speed_detected(uhost->dev_prop.speed); + + usb_mdelay (50U); + } + break; + + case HOST_DEV_CONNECT: + uhost->usr_cb->dev_attach(); + uhost->control.pipe_out_num = usbh_pipe_allocate(&usbh_core, 0x00U); + uhost->control.pipe_in_num = usbh_pipe_allocate(&usbh_core, 0x80U); + + /* open IN control pipe */ + usbh_pipe_create (&usbh_core, + &uhost->dev_prop, + uhost->control.pipe_in_num, + USB_EPTYPE_CTRL, + (uint16_t)uhost->control.max_len); + + /* open OUT control pipe */ + usbh_pipe_create (&usbh_core, + &uhost->dev_prop, + uhost->control.pipe_out_num, + USB_EPTYPE_CTRL, + (uint16_t)uhost->control.max_len); + + uhost->cur_state = HOST_DEV_ENUM; + break; + + case HOST_DEV_ENUM: + /* check for enumeration status */ + if (USBH_OK == usbh_enum_task (uhost)) { + /* the function shall return USBH_OK when full enumeration is complete */ + + /* user callback for end of device basic enumeration */ + uhost->usr_cb->dev_enumerated(); + +#if USB_LOW_POWER + uhost->cur_state = HOST_SUSPEND; + + /* judge device remote wakeup function */ + if ((uhost->dev_prop.cfg_desc_set.cfg_desc.bmAttributes) & (1U << 5)) { + uhost->dev_supp_remote_wkup = 1; + }else{ + uhost->dev_supp_remote_wkup = 0; + } +#else + uhost->cur_state = HOST_PWR_FEATURE_SET; +#endif /* USB_LOW_POWER */ + } + break; + + case HOST_PWR_FEATURE_SET: + if ((uhost->dev_prop.cfg_desc_set.cfg_desc.bmAttributes) & (1U << 5)) { + if (usbh_setdevfeature(uhost, FEATURE_SELECTOR_REMOTEWAKEUP, 0U) == USBH_OK) { + uhost->cur_state = HOST_CLASS_CHECK; + } + } else { + uhost->cur_state = HOST_CLASS_CHECK; + } + break; + + case HOST_CLASS_CHECK: + if (0U == uhost->class_num) { + uhost->cur_state = HOST_ERROR; + } else { + uhost->active_class = NULL; + + uint8_t itf_class = uhost->dev_prop.cfg_desc_set.itf_desc_set[0][0].itf_desc.bInterfaceClass; + + for (uint8_t index = 0U; index < uhost->class_num; index++) { + if ((uhost->uclass[index]->class_code == itf_class) || (0xFFU == itf_class)) { + uhost->active_class = uhost->uclass[index]; + } + } + + if (uhost->active_class != NULL) { + uhost->cur_state = HOST_USER_INPUT; + } else { + uhost->cur_state = HOST_ERROR; + } + } + break; + + case HOST_USER_INPUT: + /* the function should return user response true to move to class state */ + if (USR_IN_RESP_OK == uhost->usr_cb->dev_user_input()) { + if ((USBH_OK == uhost->active_class->class_init(uhost))) { + uhost->cur_state = HOST_CLASS_ENUM; + } + } + break; + +#if USB_LOW_POWER + case HOST_SUSPEND: + if(uhost->dev_supp_remote_wkup){ + /* send set feature command*/ + if (USBH_OK == usbh_setdevfeature (uhost, FEATURE_SELECTOR_REMOTEWAKEUP, 0U)) { + + usb_hwp_suspend(&usbh_core); + + usb_mdelay (20U); + uhost->suspend_flag = 1; + uhost->usr_cb->dev_user_input(); + + /* MCU enter deep-sleep*/ + pmu_to_deepsleepmode (PMU_LDO_LOWPOWER, WFI_CMD); + uhost->cur_state = HOST_WAKEUP; + } + } else { + /* host suspend */ + usb_hwp_suspend(&usbh_core); + + usb_mdelay(20U); + uhost->suspend_flag = 1U; + uhost->usr_cb->dev_user_input(); + + /* MCU enter deep-sleep */ + pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); + uhost->cur_state = HOST_WAKEUP; + } + break; + + case HOST_WAKEUP: + /* judge suspend status */ + if (0U == uhost->suspend_flag) { + usb_hwp_resume(&usbh_core); + usb_mdelay(500U); + + if (uhost->dev_supp_remote_wkup) { + if (USBH_OK == usbh_clrdevfeature (uhost, FEATURE_SELECTOR_DEV, 0U)) { + /* user callback for initialization */ + uhost->usr_cb->dev_init(); + uhost->cur_state = HOST_CLASS_CHECK; + } + } else { + uhost->cur_state = HOST_CLASS_CHECK; + } + } + break; +#endif /* USB_LOW_POWER */ + + case HOST_CLASS_ENUM: + /* process class standard control requests state machine */ + status = uhost->active_class->class_requests(uhost); + + if (USBH_OK == status) { + uhost->cur_state = HOST_CLASS_HANDLER; + } else { + usbh_error_handler (uhost, status); + } + break; + + case HOST_CLASS_HANDLER: + /* process class state machine */ + status = uhost->active_class->class_machine(uhost); + + usbh_error_handler (uhost, status); + break; + + case HOST_ERROR: + /* deinitialize host for new enumeration */ + usbh_deinit (uhost); + uhost->usr_cb->dev_deinit(); + uhost->active_class->class_deinit(uhost); + break; + + case HOST_DEV_DETACHED: + /* manage user disconnect operations*/ + uhost->usr_cb->dev_detach(); + + /* re-initialize host for new enumeration */ + usbh_deinit (uhost); + uhost->usr_cb->dev_deinit(); + uhost->active_class->class_deinit(uhost); + usbh_pipe_delete(&usbh_core); + uhost->cur_state = HOST_DEFAULT; + break; + + default: + break; + } +} + +/*! + \brief handle the error on USB host side + \param[in] uhost: pointer to USB host + \param[in] err_type: type of error or busy/OK state + \param[out] none + \retval none +*/ +void usbh_error_handler (usbh_host *uhost, usbh_status err_type) +{ + /* error unrecovered or not supported device speed */ + if ((USBH_SPEED_UNKNOWN_ERROR == err_type) || (USBH_UNRECOVERED_ERROR == err_type)) { + uhost->usr_cb->dev_error(); + + uhost->cur_state = HOST_ERROR; + } else if (USBH_APPLY_DEINIT == err_type) { + uhost->cur_state = HOST_ERROR; + + /* user callback for initialization */ + uhost->usr_cb->dev_init(); + } else { + /* no operation */ + } +} + +/*! + \brief USB SOF event function from the interrupt + \param[in] uhost: pointer to USB host + \param[out] none + \retval operation status +*/ +static uint8_t usb_ev_sof (usbh_host *uhost) +{ + /* this callback could be used to implement a scheduler process */ + uhost->control.timer = (uint16_t)usb_curframe_get(&usbh_core); + + if (uhost->active_class != NULL) { + if (uhost->active_class->class_sof != NULL) { + uhost->active_class->class_sof(uhost); + } + } + + return 0U; +} + +/*! + \brief USB connect event function from the interrupt + \param[in] uhost: pointer to USB host + \param[out] none + \retval operation status +*/ +static uint8_t usb_ev_connect (usbh_host *uhost) +{ + usbh_core.host.connect_status = 1U; + + return 0U; +} + +/*! + \brief USB disconnect event function from the interrupt + \param[in] uhost: pointer to USB host + \param[out] none + \retval operation status +*/ +static uint8_t usb_ev_disconnect (usbh_host *uhost) +{ + usbh_core.host.connect_status = 0U; + + return 0U; +} + +/*! + \brief handle the USB enumeration task + \param[in] uhost: pointer to host + \param[out] none + \retval none +*/ +static usbh_status usbh_enum_task (usbh_host *uhost) +{ + uint8_t str_buf[512]; + usbh_status status = USBH_BUSY; + + static uint8_t index_mfc_str = 0U, index_prod_str = 0U, index_serial_str = 0U; + + switch (uhost->enum_state) { + case ENUM_DEFAULT: + /* get device descriptor for only 1st 8 bytes : to get ep0 max packet size */ + if (USBH_OK == usbh_devdesc_get (uhost, 8U)) { + uhost->control.max_len = uhost->dev_prop.dev_desc.bMaxPacketSize0; + + /* modify control channels configuration for maximum packet size */ + usbh_pipe_update (&usbh_core, + uhost->control.pipe_out_num, + 0U, 0U, + (uint16_t)uhost->control.max_len); + + usbh_pipe_update (&usbh_core, + uhost->control.pipe_in_num, + 0U, 0U, + (uint16_t)uhost->control.max_len); + + uhost->enum_state = ENUM_GET_DEV_DESC; + } + break; + + case ENUM_GET_DEV_DESC: + /* get full device descriptor */ + if (USBH_OK == usbh_devdesc_get (uhost, USB_DEV_DESC_LEN)) { + uhost->usr_cb->dev_devdesc_assigned(&uhost->dev_prop.dev_desc); + + index_mfc_str = uhost->dev_prop.dev_desc.iManufacturer; + index_prod_str = uhost->dev_prop.dev_desc.iProduct; + index_serial_str = uhost->dev_prop.dev_desc.iSerialNumber; + + uhost->enum_state = ENUM_SET_ADDR; + } + break; + + case ENUM_SET_ADDR: + /* set address */ + if (USBH_OK == usbh_setaddress (uhost, USBH_DEV_ADDR)) { + usb_mdelay (2U); + + uhost->dev_prop.addr = USBH_DEV_ADDR; + + /* user callback for device address assigned */ + uhost->usr_cb->dev_address_set(); + + /* modify control channels to update device address */ + usbh_pipe_update (&usbh_core, + uhost->control.pipe_in_num, + uhost->dev_prop.addr, + 0U, 0U); + + usbh_pipe_update (&usbh_core, + uhost->control.pipe_out_num, + uhost->dev_prop.addr, + 0U, 0U); + + uhost->enum_state = ENUM_GET_CFG_DESC; + } + break; + + case ENUM_GET_CFG_DESC: + /* get standard configuration descriptor */ + if (USBH_OK == usbh_cfgdesc_get (uhost, USB_CFG_DESC_LEN)) { + uhost->enum_state = ENUM_GET_CFG_DESC_SET; + } + break; + + case ENUM_GET_CFG_DESC_SET: + /* get full configure descriptor (config, interface, endpoints) */ + if (USBH_OK == usbh_cfgdesc_get (uhost, uhost->dev_prop.cfg_desc_set.cfg_desc.wTotalLength)) { + /* user callback for configuration descriptors available */ + uhost->usr_cb->dev_cfgdesc_assigned (&uhost->dev_prop.cfg_desc_set.cfg_desc, + &uhost->dev_prop.cfg_desc_set.itf_desc_set[0][0].itf_desc, + &uhost->dev_prop.cfg_desc_set.itf_desc_set[0][0].ep_desc[0]); + + uhost->enum_state = ENUM_GET_STR_DESC; + } + break; + + case ENUM_GET_STR_DESC: + if (index_mfc_str) { + if (USBH_OK == usbh_strdesc_get (uhost, + uhost->dev_prop.dev_desc.iManufacturer, + str_buf, + 0xFFU)) { + /* user callback for manufacturing string */ + uhost->usr_cb->dev_mfc_str(str_buf); + + index_mfc_str = 0U; + } + } else { + if (index_prod_str) { + /* check that product string is available */ + if (USBH_OK == usbh_strdesc_get (uhost, + uhost->dev_prop.dev_desc.iProduct, + str_buf, + 0xFFU)) { + uhost->usr_cb->dev_prod_str(str_buf); + + index_prod_str = 0U; + } + } else { + if (index_serial_str) { + if (USBH_OK == usbh_strdesc_get (uhost, + uhost->dev_prop.dev_desc.iSerialNumber, + str_buf, + 0xFFU)) { + uhost->usr_cb->dev_seral_str(str_buf); + uhost->enum_state = ENUM_SET_CONFIGURATION; + index_serial_str = 0U; + } + } else { + uhost->enum_state = ENUM_SET_CONFIGURATION; + } + } + } + break; + + case ENUM_SET_CONFIGURATION: + if (USBH_OK == usbh_setcfg (uhost, (uint16_t)uhost->dev_prop.cfg_desc_set.cfg_desc.bConfigurationValue)) { + uhost->enum_state = ENUM_DEV_CONFIGURED; + } + break; + + case ENUM_DEV_CONFIGURED: + status = USBH_OK; + break; + + default: + break; + } + + return status; +} + +#if USB_LOW_POWER + +/*! + \brief handles the USB resume from suspend mode + \param[in] udev: pointer to selected USB device + \param[out] none + \retval none +*/ +static void usb_hwp_resume(usb_core_driver *udev) +{ + __IO uint32_t hprt = 0U; + + /* switch-on the clocks */ + *udev->regs.PWRCLKCTL &= ~PWRCLKCTL_SUCLK; + + *udev->regs.PWRCLKCTL &= ~PWRCLKCTL_SHCLK; + + hprt = usb_port_read(udev); + + hprt &= ~HPCS_PSP; + hprt |= HPCS_PREM; + + *udev->regs.HPCS = hprt; + + usb_mdelay (20U); + + hprt &= ~HPCS_PREM; + + *udev->regs.HPCS = hprt; +} + +/*! + \brief handles the USB enter to suspend mode + \param[in] udev: pointer to selected USB device + \param[out] none + \retval none +*/ +static void usb_hwp_suspend(usb_core_driver *udev) +{ + __IO uint32_t hprt = 0U; + + hprt = usb_port_read(udev); + + hprt |= HPCS_PSP; + + *udev->regs.HPCS = hprt; + + /* switch-off the clocks */ + *udev->regs.PWRCLKCTL |= PWRCLKCTL_SUCLK; + + *udev->regs.PWRCLKCTL |= PWRCLKCTL_SHCLK; +} + +#endif /* USB_LOW_POWER */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Source/usbh_enum.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Source/usbh_enum.c new file mode 100644 index 00000000..a5c81014 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Source/usbh_enum.c @@ -0,0 +1,693 @@ +/*! + \file usbh_enum.c + \brief USB host mode enumeration driver + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_pipe.h" +#include "usbh_transc.h" +#include "usbh_enum.h" + +/* local function prototypes ('static') */ +static void usbh_devdesc_parse (usb_desc_dev *dev_desc, uint8_t *buf, uint16_t len); +static void usbh_cfgdesc_parse (usb_desc_config *cfg_desc, uint8_t *buf); +static void usbh_cfgset_parse (usb_dev_prop *udev, uint8_t *buf); +static void usbh_itfdesc_parse (usb_desc_itf *itf_desc, uint8_t *buf); +static void usbh_epdesc_parse (usb_desc_ep *ep_desc, uint8_t *buf); +static void usbh_strdesc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len); + +/*! + \brief configure USB control status parameters + \param[in] uhost: pointer to USB host + \param[in] buf: control transfer data buffer pointer + \param[in] len: length of the data buffer + \param[out] none + \retval none +*/ +void usbh_ctlstate_config (usbh_host *uhost, uint8_t *buf, uint16_t len) +{ + /* prepare the transactions */ + uhost->control.buf = buf; + uhost->control.ctl_len = len; + + uhost->control.ctl_state = CTL_SETUP; +} + +/*! + \brief get device descriptor from the USB device + \param[in] uhost: pointer to USB host + \param[in] len: length of the descriptor + \param[out] none + \retval operation status +*/ +usbh_status usbh_devdesc_get (usbh_host *uhost, uint8_t len) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &uhost->control; + + if (CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, + .bRequest = USB_GET_DESCRIPTOR, + .wValue = USBH_DESC(USB_DESCTYPE_DEV), + .wIndex = 0U, + .wLength = len + }; + + usbh_ctlstate_config (uhost, uhost->dev_prop.data, (uint16_t)len); + } + + status = usbh_ctl_handler (uhost); + + if (USBH_OK == status) { + /* commands successfully sent and response received */ + usbh_devdesc_parse (&uhost->dev_prop.dev_desc, uhost->dev_prop.data, (uint16_t)len); + } + + return status; +} + +/*! + \brief get configuration descriptor from the USB device + \param[in] uhost: pointer to USB host + \param[in] len: length of the descriptor + \param[out] none + \retval operation status +*/ +usbh_status usbh_cfgdesc_get (usbh_host *uhost, uint16_t len) +{ + uint8_t *pdata = NULL; + + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &uhost->control; + +#if (USBH_CFG_DESC_KEEP == 1U) + pdata = uhost->dev_prop.cfgdesc_rawdata; +#else + pdata = uhost->dev_prop.data; +#endif /* (USBH_CFG_DESC_KEEP == 1U) */ + + if (CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, + .bRequest = USB_GET_DESCRIPTOR, + .wValue = USBH_DESC(USB_DESCTYPE_CONFIG), + .wIndex = 0U, + .wLength = len + }; + + usbh_ctlstate_config (uhost, pdata, len); + } + + status = usbh_ctl_handler (uhost); + + if (USBH_OK == status) { + if (len <= USB_CFG_DESC_LEN) { + usbh_cfgdesc_parse (&uhost->dev_prop.cfg_desc_set.cfg_desc, pdata); + } else { + usbh_cfgset_parse (&uhost->dev_prop, pdata); + } + } + + return status; +} + +/*! + \brief get string descriptor from the USB device + \param[in] uhost: pointer to USB host + \param[in] str_index: index for the string descriptor + \param[in] buf: buffer pointer to the string descriptor + \param[in] len: length of the descriptor + \param[out] none + \retval operation status +*/ +usbh_status usbh_strdesc_get (usbh_host *uhost, + uint8_t str_index, + uint8_t *buf, + uint16_t len) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &uhost->control; + + if (CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, + .bRequest = USB_GET_DESCRIPTOR, + .wValue = USBH_DESC(USB_DESCTYPE_STR) | str_index, + .wIndex = 0x0409U, + .wLength = len + }; + + usbh_ctlstate_config (uhost, uhost->dev_prop.data, len); + } + + status = usbh_ctl_handler (uhost); + + if (USBH_OK == status) { + /* commands successfully sent and response received */ + usbh_strdesc_parse (uhost->dev_prop.data, buf, len); + } + + return status; +} + +/*! + \brief set the address to the connected device + \param[in] uhost: pointer to USB host + \param[in] dev_addr: device address to assign + \param[out] none + \retval operation status +*/ +usbh_status usbh_setaddress (usbh_host *uhost, uint8_t dev_addr) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &uhost->control; + + if (CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, + .bRequest = USB_SET_ADDRESS, + .wValue = (uint16_t)dev_addr, + .wIndex = 0U, + .wLength = 0U + }; + + usbh_ctlstate_config (uhost, NULL, 0U); + } + + status = usbh_ctl_handler (uhost); + + return status; +} + +/*! + \brief set the configuration value to the connected device + \param[in] uhost: pointer to USB host + \param[in] config_index: configuration value + \param[out] none + \retval operation status +*/ +usbh_status usbh_setcfg (usbh_host *uhost, uint16_t config_index) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &uhost->control; + + if (CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, + .bRequest = USB_SET_CONFIGURATION, + .wValue = config_index, + .wIndex = 0U, + .wLength = 0U + }; + + usbh_ctlstate_config (uhost, NULL, 0U); + } + + status = usbh_ctl_handler (uhost); + + return status; +} + +/*! + \brief set the interface value to the connected device + \param[in] uhost: pointer to USB host + \param[in] itf_num: interface number + \param[in] set: alternated setting value + \param[out] none + \retval operation status +*/ +usbh_status usbh_setinterface (usbh_host *uhost, uint8_t itf_num, uint8_t set) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &uhost->control; + + if (CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_STRD, + .bRequest = USB_SET_INTERFACE, + .wValue = set, + .wIndex = itf_num, + .wLength = 0U + }; + + usbh_ctlstate_config (uhost, NULL, 0U); + } + + status = usbh_ctl_handler (uhost); + + return status; +} + +/*! + \brief set the interface value to the connected device + \param[in] uhost: pointer to USB host + \param[in] feature_selector: feature selector + \param[in] windex: index value + \param[out] none + \retval operation status +*/ +usbh_status usbh_setdevfeature (usbh_host *uhost, uint8_t feature_selector, uint16_t windex) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &uhost->control; + + if (CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, + .bRequest = USB_SET_FEATURE, + .wValue = feature_selector, + .wIndex = windex, + .wLength = 0U + }; + + usbh_ctlstate_config (uhost, NULL, 0U); + } + + status = usbh_ctl_handler (uhost); + + return status; +} + +/*! + \brief clear the interface value to the connected device + \param[in] uhost: pointer to USB host + \param[in] feature_selector: feature selector + \param[in] windex: index value + \param[out] none + \retval operation status +*/ +usbh_status usbh_clrdevfeature (usbh_host *uhost, uint8_t feature_selector, uint16_t windex) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &uhost->control; + + if (CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, + .bRequest = USB_CLEAR_FEATURE, + .wValue = feature_selector, + .wIndex = windex, + .wLength = 0U + }; + + usbh_ctlstate_config (uhost, NULL, 0U); + } + + status = usbh_ctl_handler (uhost); + + return status; +} + +/*! + \brief clear or disable a specific feature + \param[in] uhost: pointer to USB host + \param[in] ep_addr: endpoint address + \param[in] pp_num: pipe number + \param[out] none + \retval operation status +*/ +usbh_status usbh_clrfeature (usbh_host *uhost, uint8_t ep_addr, uint8_t pp_num) +{ + usbh_status status = USBH_BUSY; + usbh_control *usb_ctl = &uhost->control; + usb_core_driver *udev = (usb_core_driver *)uhost->data; + + if (CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_EP | USB_REQTYPE_STRD, + .bRequest = USB_CLEAR_FEATURE, + .wValue = FEATURE_SELECTOR_EP, + .wIndex = ep_addr, + .wLength = 0U + }; + + if (EP_ID(ep_addr) == udev->host.pipe[pp_num].ep.num) { + usbh_pipe_toggle_set(udev, pp_num, 0U); + } else { + return USBH_FAIL; + } + + usbh_ctlstate_config (uhost, NULL, 0U); + } + + status = usbh_ctl_handler (uhost); + + return status; +} + +/*! + \brief get the next descriptor header + \param[in] pbuf: pointer to buffer where the configuration descriptor set is available + \param[in] ptr: data pointer inside the configuration descriptor set + \param[out] none + \retval return descriptor header +*/ +usb_desc_header *usbh_nextdesc_get (uint8_t *pbuf, uint16_t *ptr) +{ + usb_desc_header *pnext; + + *ptr += ((usb_desc_header *)pbuf)->bLength; + + pnext = (usb_desc_header *)((uint8_t *)pbuf + ((usb_desc_header *)pbuf)->bLength); + + return (pnext); +} + +/*! + \brief get the next descriptor header + \param[in] udev: pointer to device property + \param[in] interface: interface number + \param[out] none + \retval operation status +*/ +usbh_status usbh_interface_select (usb_dev_prop *udev, uint8_t interface) +{ + usbh_status status = USBH_OK; + + if (interface < udev->cfg_desc_set.cfg_desc.bNumInterfaces) { + udev->cur_itf = interface; + } else { + status = USBH_FAIL; + } + + return status; +} + +/*! + \brief find the interface index for a specific class + \param[in] udev: pointer to device property + \param[in] main_class: class code + \param[in] sub_class: subclass code + \param[in] protocol: Protocol code + \param[out] none + \retval interface index in the configuration structure + \note interface index 0xFF means interface index not found +*/ +uint8_t usbh_interface_find (usb_dev_prop *udev, uint8_t main_class, uint8_t sub_class, uint8_t protocol) +{ + usb_desc_itf *pif; + + uint8_t if_ix = 0U; + + pif = (usb_desc_itf *)0; + + while (if_ix < udev->cfg_desc_set.cfg_desc.bNumInterfaces) { + pif = &udev->cfg_desc_set.itf_desc_set[if_ix][0].itf_desc; + + if (((pif->bInterfaceClass == main_class) || (main_class == 0xFFU))&& + ((pif->bInterfaceSubClass == sub_class) || (sub_class == 0xFFU))&& + ((pif->bInterfaceProtocol == protocol) || (protocol == 0xFFU))) { + return if_ix; + } + + if_ix++; + } + + return 0xFFU; +} + +/*! + \brief find the interface index for a specific class interface and alternate setting number + \param[in] udev: pointer to device property + \param[in] interface_number: interface number + \param[in] alt_settings: alternate setting number + \param[out] none + \retval interface index in the configuration structure + \note interface index 0xFF means interface index not found +*/ +uint8_t usbh_interfaceindex_find (usb_dev_prop *udev, uint8_t interface_number, uint8_t alt_settings) +{ + usb_desc_itf *pif; + + uint8_t if_ix = 0U; + + pif = (usb_desc_itf *)0; + + while (if_ix < USBH_MAX_INTERFACES_NUM) { + pif = &udev->cfg_desc_set.itf_desc_set[if_ix][alt_settings].itf_desc; + + if ((pif->bInterfaceNumber == interface_number) && (pif->bAlternateSetting == alt_settings)) { + return if_ix; + } + + if_ix++; + } + + return 0xFFU; +} + +/*! + \brief parse the device descriptor + \param[in] dev_desc: pointer to USB device descriptor buffer + \param[in] buf: pointer to the source descriptor buffer + \param[in] len: length of the descriptor + \param[out] none + \retval none +*/ +static void usbh_devdesc_parse (usb_desc_dev *dev_desc, uint8_t *buf, uint16_t len) +{ + *dev_desc = (usb_desc_dev) { + .header = { + .bLength = *(uint8_t *)(buf + 0U), + .bDescriptorType = *(uint8_t *)(buf + 1U) + }, + + .bcdUSB = BYTE_SWAP(buf + 2U), + .bDeviceClass = *(uint8_t *)(buf + 4U), + .bDeviceSubClass = *(uint8_t *)(buf + 5U), + .bDeviceProtocol = *(uint8_t *)(buf + 6U), + .bMaxPacketSize0 = *(uint8_t *)(buf + 7U) + }; + + if (len > 8U) { + /* for 1st time after device connection, host may issue only 8 bytes for device descriptor length */ + dev_desc->idVendor = BYTE_SWAP(buf + 8U); + dev_desc->idProduct = BYTE_SWAP(buf + 10U); + dev_desc->bcdDevice = BYTE_SWAP(buf + 12U); + dev_desc->iManufacturer = *(uint8_t *)(buf + 14U); + dev_desc->iProduct = *(uint8_t *)(buf + 15U); + dev_desc->iSerialNumber = *(uint8_t *)(buf + 16U); + dev_desc->bNumberConfigurations = *(uint8_t *)(buf + 17U); + } +} + +/*! + \brief parse the configuration descriptor + \param[in] cfg_desc: pointer to USB configuration descriptor buffer + \param[in] buf: pointer to the source descriptor buffer + \param[out] none + \retval none +*/ +static void usbh_cfgdesc_parse (usb_desc_config *cfg_desc, uint8_t *buf) +{ + /* parse configuration descriptor */ + *cfg_desc = (usb_desc_config) { + .header = { + .bLength = *(uint8_t *)(buf + 0U), + .bDescriptorType = *(uint8_t *)(buf + 1U), + }, + + .wTotalLength = BYTE_SWAP(buf + 2U), + .bNumInterfaces = *(uint8_t *)(buf + 4U), + .bConfigurationValue = *(uint8_t *)(buf + 5U), + .iConfiguration = *(uint8_t *)(buf + 6U), + .bmAttributes = *(uint8_t *)(buf + 7U), + .bMaxPower = *(uint8_t *)(buf + 8U) + }; +} + +/*! + \brief parse the configuration descriptor set + \param[in] udev: pointer to device property + \param[in] buf: pointer to the source descriptor buffer + \param[out] none + \retval none +*/ +static void usbh_cfgset_parse (usb_dev_prop *udev, uint8_t *buf) +{ + usb_desc_ep *ep = NULL; + usb_desc_itf_set *itf = NULL; + usb_desc_itf itf_value; + usb_desc_config *cfg = NULL; + + usb_desc_header *pdesc = (usb_desc_header *)buf; + + uint8_t itf_index = 0U, ep_index = 0U, alt_setting = 0U; + uint8_t pre_itf_index = 0U; + uint16_t ptr; + + /* parse configuration descriptor */ + usbh_cfgdesc_parse (&udev->cfg_desc_set.cfg_desc, buf); + cfg = &udev->cfg_desc_set.cfg_desc; + ptr = USB_CFG_DESC_LEN; + + if (cfg->bNumInterfaces > USBH_MAX_INTERFACES_NUM) { + return; + } + + while (ptr < cfg->wTotalLength) { + pdesc = usbh_nextdesc_get ((uint8_t *)pdesc, &ptr); + + if (pdesc->bDescriptorType == USB_DESCTYPE_ITF) { + itf_index = *(((uint8_t *)pdesc) + 2U); + + if (pre_itf_index != itf_index) { + alt_setting = 0U; + } + + itf = &udev->cfg_desc_set.itf_desc_set[itf_index][alt_setting]; + + alt_setting++; + + if ((*((uint8_t *)pdesc + 3U)) < 3U) { + usbh_itfdesc_parse (&itf_value, (uint8_t *)pdesc); + + /* parse endpoint descriptors relative to the current interface */ + if (itf_value.bNumEndpoints > USBH_MAX_EP_NUM) { + return; + } + + usbh_itfdesc_parse (&itf->itf_desc, (uint8_t *)&itf_value); + + /* store the previous interface index */ + pre_itf_index = itf_index; + + if (0U == itf_value.bNumEndpoints) { + continue; + } + + for (ep_index = 0U; ep_index < itf_value.bNumEndpoints; ) { + pdesc = usbh_nextdesc_get ((void*)pdesc, &ptr); + + if (pdesc->bDescriptorType == USB_DESCTYPE_EP) { + ep = &itf->ep_desc[ep_index]; + + usbh_epdesc_parse (ep, (uint8_t *)pdesc); + + ep_index++; + } + } + } + } + } +} + +/*! + \brief parse the interface descriptor + \param[in] itf_desc: pointer to USB interface descriptor buffer + \param[in] buf: pointer to the source descriptor buffer + \param[out] none + \retval none +*/ +static void usbh_itfdesc_parse (usb_desc_itf *itf_desc, uint8_t *buf) +{ + *itf_desc = (usb_desc_itf) { + .header = { + .bLength = *(uint8_t *)(buf + 0U), + .bDescriptorType = *(uint8_t *)(buf + 1U), + }, + + .bInterfaceNumber = *(uint8_t *)(buf + 2U), + .bAlternateSetting = *(uint8_t *)(buf + 3U), + .bNumEndpoints = *(uint8_t *)(buf + 4U), + .bInterfaceClass = *(uint8_t *)(buf + 5U), + .bInterfaceSubClass = *(uint8_t *)(buf + 6U), + .bInterfaceProtocol = *(uint8_t *)(buf + 7U), + .iInterface = *(uint8_t *)(buf + 8U) + }; +} + +/*! + \brief parse the endpoint descriptor + \param[in] ep_desc: pointer to USB endpoint descriptor buffer + \param[in] buf: pointer to the source descriptor buffer + \param[out] none + \retval none +*/ +static void usbh_epdesc_parse (usb_desc_ep *ep_desc, uint8_t *buf) +{ + *ep_desc = (usb_desc_ep) { + .header = { + .bLength = *(uint8_t *)(buf + 0U), + .bDescriptorType = *(uint8_t *)(buf + 1U) + }, + + .bEndpointAddress = *(uint8_t *)(buf + 2U), + .bmAttributes = *(uint8_t *)(buf + 3U), + .wMaxPacketSize = BYTE_SWAP(buf + 4U), + .bInterval = *(uint8_t *)(buf + 6U) + }; +} + +/*! + \brief parse the string descriptor + \param[in] psrc: source pointer containing the descriptor data + \param[in] pdest: destination address pointer + \param[in] len: length of the descriptor + \param[out] none + \retval none +*/ +static void usbh_strdesc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len) +{ + uint16_t str_len = 0U, index = 0U; + + /* the unicode string descriptor is not NULL-terminated. The string length is + * computed by substracting two from the value of the first byte of the descriptor. + */ + + /* check which is lower size, the size of string or the length of bytes read from the device */ + if (USB_DESCTYPE_STR == psrc[1]) { + /* make sure the descriptor is string type */ + + /* psrc[0] contains size of descriptor, subtract 2 to get the length of string */ + str_len = USB_MIN((uint16_t)psrc[0] - 2U, len); + + psrc += 2U; /* adjust the offset ignoring the string length and descriptor type */ + + for(index = 0U; index < str_len; index += 2U) { + /* copy only the string and ignore the unicode id, hence add the source */ + *pdest = psrc[index]; + + pdest++; + } + + *pdest = 0U; /* mark end of string */ + } +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Source/usbh_pipe.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Source/usbh_pipe.c new file mode 100644 index 00000000..933bf806 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Source/usbh_pipe.c @@ -0,0 +1,181 @@ +/*! + \file usbh_pipe.c + \brief USB host mode pipe operation driver + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_pipe.h" + +/* local function prototypes ('static') */ +static uint16_t usbh_freepipe_get (usb_core_driver *udev); + +/*! + \brief create a pipe + \param[in] udev: pointer to USB core instance + \param[in] dev: USB device + \param[in] pp_num: pipe number + \param[in] ep_type: endpoint type + \param[in] ep_mpl: endpoint max packet length + \param[out] none + \retval operation status +*/ +uint8_t usbh_pipe_create (usb_core_driver *udev, + usb_dev_prop *dev, + uint8_t pp_num, + uint8_t ep_type, + uint16_t ep_mpl) +{ + usb_pipe *pp = &udev->host.pipe[pp_num]; + + pp->dev_addr = dev->addr; + pp->dev_speed = dev->speed; + pp->ep.type = ep_type; + pp->ep.mps = ep_mpl; + + if ((USB_EPTYPE_BULK == pp->ep.type) || (USB_EPTYPE_CTRL == pp->ep.type)) { + pp->supp_ping = (uint8_t)(pp->dev_speed == PORT_SPEED_HIGH); + } + + usb_pipe_init (udev, pp_num); + + return HP_OK; +} + +/*! + \brief modify a pipe + \param[in] udev: pointer to USB core instance + \param[in] pp_num: pipe number + \param[in] dev_addr: device address + \param[in] dev_speed: device speed + \param[in] ep_mpl: endpoint max packet length + \param[out] none + \retval operation status +*/ +uint8_t usbh_pipe_update (usb_core_driver *udev, + uint8_t pp_num, + uint8_t dev_addr, + uint32_t dev_speed, + uint16_t ep_mpl) +{ + usb_pipe *pp = &udev->host.pipe[pp_num]; + + if ((pp->dev_addr != dev_addr) && (dev_addr)) { + pp->dev_addr = dev_addr; + } + + if ((pp->dev_speed != dev_speed) && (dev_speed)) { + pp->dev_speed = dev_speed; + + if ((USB_EPTYPE_BULK == pp->ep.type) || (USB_EPTYPE_CTRL == pp->ep.type)) { + pp->supp_ping = (uint8_t)(pp->dev_speed == PORT_SPEED_HIGH); + } + } + + if ((pp->ep.mps != ep_mpl) && (ep_mpl)) { + pp->ep.mps = ep_mpl; + } + + usb_pipe_init (udev, pp_num); + + return HP_OK; +} + +/*! + \brief allocate a new pipe + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + \param[out] none + \retval operation status +*/ +uint8_t usbh_pipe_allocate (usb_core_driver *udev, uint8_t ep_addr) +{ + uint16_t pp_num = usbh_freepipe_get (udev); + + if (HP_ERROR != pp_num) { + udev->host.pipe[pp_num].in_used = 1U; + udev->host.pipe[pp_num].ep.dir = EP_DIR(ep_addr); + udev->host.pipe[pp_num].ep.num = EP_ID(ep_addr); + } + + return (uint8_t)pp_num; +} + +/*! + \brief free a pipe + \param[in] udev: pointer to USB core instance + \param[in] pp_num: pipe number + \param[out] none + \retval operation status +*/ +uint8_t usbh_pipe_free (usb_core_driver *udev, uint8_t pp_num) +{ + if (pp_num < HP_MAX) { + udev->host.pipe[pp_num].in_used = 0U; + } + + return USBH_OK; +} + +/*! + \brief delete all USB host pipe + \param[in] udev: pointer to USB core instance + \param[out] none + \retval operation status +*/ +uint8_t usbh_pipe_delete (usb_core_driver *udev) +{ + uint8_t pp_num = 0U; + + for (pp_num = 2U; pp_num < HP_MAX; pp_num++) { + udev->host.pipe[pp_num] = (usb_pipe) {0}; + } + + return USBH_OK; +} + +/*! + \brief get a free pipe number for allocation + \param[in] udev: pointer to USB core instance + \param[out] none + \retval operation status +*/ +static uint16_t usbh_freepipe_get (usb_core_driver *udev) +{ + uint8_t pp_num = 0U; + + for (pp_num = 0U; pp_num < HP_MAX; pp_num++) { + if (0U == udev->host.pipe[pp_num].in_used) { + return (uint16_t)pp_num; + } + } + + return HP_ERROR; +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Source/usbh_transc.c b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Source/usbh_transc.c new file mode 100644 index 00000000..053e6ac6 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/host/core/Source/usbh_transc.c @@ -0,0 +1,370 @@ +/*! + \file usbh_transc.c + \brief USB host mode transactions driver + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "usbh_pipe.h" +#include "usbh_transc.h" + +/* local function prototypes ('static') */ +static usb_urb_state usbh_urb_wait (usbh_host *uhost, uint8_t pp_num, uint32_t wait_time); +static void usbh_setup_transc (usbh_host *uhost); +static void usbh_data_in_transc (usbh_host *uhost); +static void usbh_data_out_transc (usbh_host *uhost); +static void usbh_status_in_transc (usbh_host *uhost); +static void usbh_status_out_transc (usbh_host *uhost); +static uint32_t usbh_request_submit (usb_core_driver *udev, uint8_t pp_num); + +/*! + \brief send the setup packet to the USB device + \param[in] udev: pointer to USB core instance + \param[in] buf: data buffer which will be sent to USB device + \param[in] pp_num: pipe number + \param[out] none + \retval operation status +*/ +usbh_status usbh_ctlsetup_send (usb_core_driver *udev, uint8_t *buf, uint8_t pp_num) +{ + usb_pipe *pp = &udev->host.pipe[pp_num]; + + pp->DPID = PIPE_DPID_SETUP; + pp->xfer_buf = buf; + pp->xfer_len = USB_SETUP_PACKET_LEN; + + return (usbh_status)usbh_request_submit (udev, pp_num); +} + +/*! + \brief send a data packet to the USB device + \param[in] udev: pointer to USB core instance + \param[in] buf: data buffer which will be sent to USB device + \param[in] pp_num: pipe number + \param[in] len: length of the data to be sent + \param[out] none + \retval operation status +*/ +usbh_status usbh_data_send (usb_core_driver *udev, uint8_t *buf, uint8_t pp_num, uint16_t len) +{ + usb_pipe *pp = &udev->host.pipe[pp_num]; + + pp->xfer_buf = buf; + pp->xfer_len = len; + + switch (pp->ep.type) { + case USB_EPTYPE_CTRL: + if (0U == len) { + pp->data_toggle_out = 1U; + } + + pp->DPID = PIPE_DPID[pp->data_toggle_out]; + break; + + case USB_EPTYPE_INTR: + pp->DPID = PIPE_DPID[pp->data_toggle_out]; + + pp->data_toggle_out ^= 1U; + break; + + case USB_EPTYPE_BULK: + pp->DPID = PIPE_DPID[pp->data_toggle_out]; + break; + + case USB_EPTYPE_ISOC: + pp->DPID = PIPE_DPID[0]; + break; + + default: + break; + } + + usbh_request_submit (udev, pp_num); + + return USBH_OK; +} + +/*! + \brief receive a data packet from the USB device + \param[in] udev: pointer to USB core instance + \param[in] buf: data buffer which will be received from USB device + \param[in] pp_num: pipe number + \param[in] len: length of the data to be received + \param[out] none + \retval operation status +*/ +usbh_status usbh_data_recev (usb_core_driver *udev, uint8_t *buf, uint8_t pp_num, uint16_t len) +{ + usb_pipe *pp = &udev->host.pipe[pp_num]; + + pp->xfer_buf = buf; + pp->xfer_len = len; + + switch (pp->ep.type) { + case USB_EPTYPE_CTRL: + pp->DPID = PIPE_DPID[1]; + break; + + case USB_EPTYPE_INTR: + pp->DPID = PIPE_DPID[pp->data_toggle_in]; + + /* toggle DATA PID */ + pp->data_toggle_in ^= 1U; + break; + + case USB_EPTYPE_BULK: + pp->DPID = PIPE_DPID[pp->data_toggle_in]; + break; + + case USB_EPTYPE_ISOC: + pp->DPID = PIPE_DPID[0]; + break; + + default: + break; + } + + usbh_request_submit (udev, pp_num); + + return USBH_OK; +} + +/*! + \brief USB control transfer handler + \param[in] uhost: pointer to USB host + \param[out] none + \retval operation status +*/ +usbh_status usbh_ctl_handler (usbh_host *uhost) +{ + usbh_status status = USBH_BUSY; + + switch (uhost->control.ctl_state) { + case CTL_SETUP: + usbh_setup_transc (uhost); + break; + + case CTL_DATA_IN: + usbh_data_in_transc (uhost); + break; + + case CTL_DATA_OUT: + usbh_data_out_transc (uhost); + break; + + case CTL_STATUS_IN: + usbh_status_in_transc (uhost); + break; + + case CTL_STATUS_OUT: + usbh_status_out_transc (uhost); + break; + + case CTL_FINISH: + uhost->control.ctl_state = CTL_IDLE; + + status = USBH_OK; + break; + + case CTL_ERROR: + if (++uhost->control.error_count <= USBH_MAX_ERROR_COUNT) { + /* do the transmission again, starting from SETUP packet */ + uhost->control.ctl_state = CTL_SETUP; + } else { + status = USBH_FAIL; + } + break; + + default: + break; + } + + return status; +} + +/*! + \brief wait for USB URB(USB request block) state + \param[in] uhost: pointer to USB host + \param[in] pp_num: pipe number + \param[in] wait_time: wait time + \param[out] none + \retval USB URB state +*/ +static usb_urb_state usbh_urb_wait (usbh_host *uhost, uint8_t pp_num, uint32_t wait_time) +{ + uint32_t timeout = 0U; + usb_urb_state urb_status = URB_IDLE; + timeout = uhost->control.timer; + + while (URB_DONE != (urb_status = usbh_urbstate_get(uhost->data, pp_num))) { + if (URB_NOTREADY == urb_status) { + break; + } else if (URB_STALL == urb_status) { + uhost->control.ctl_state = CTL_SETUP; + break; + } else if (URB_ERROR == urb_status) { + uhost->control.ctl_state = CTL_ERROR; + break; + } else if ((wait_time > 0U) && (((usb_curframe_get(uhost->data) > timeout) && ((usb_curframe_get(uhost->data) - timeout) > wait_time)) \ + || ((usb_curframe_get(uhost->data) < timeout) && ((usb_curframe_get(uhost->data) + 0x3FFFU - timeout) > wait_time)))){ + /* timeout for in transfer */ + uhost->control.ctl_state = CTL_ERROR; + break; + } else { + /* no operation, just wait */ + } + } + + return urb_status; +} + +/*! + \brief USB setup transaction + \param[in] uhost: pointer to USB host + \param[out] none + \retval none +*/ +static void usbh_setup_transc (usbh_host *uhost) +{ + /* send a SETUP packet */ + usbh_ctlsetup_send (uhost->data, + uhost->control.setup.data, + uhost->control.pipe_out_num); + + if (URB_DONE == usbh_urb_wait (uhost, uhost->control.pipe_out_num, 0U)) { + uint8_t dir = (uhost->control.setup.req.bmRequestType & USB_TRX_MASK); + + if (uhost->control.setup.req.wLength) { + if (USB_TRX_IN == dir) { + uhost->control.ctl_state = CTL_DATA_IN; + } else { + uhost->control.ctl_state = CTL_DATA_OUT; + } + } else { + if (USB_TRX_IN == dir) { + uhost->control.ctl_state = CTL_STATUS_OUT; + } else { + uhost->control.ctl_state = CTL_STATUS_IN; + } + } + + /* set the delay timer to enable timeout for data stage completion */ + uhost->control.timer = (uint16_t)usb_curframe_get(uhost->data); + } +} + +/*! + \brief USB data IN transaction + \param[in] uhost: pointer to USB host + \param[out] none + \retval none +*/ +static void usbh_data_in_transc (usbh_host *uhost) +{ + usbh_data_recev (uhost->data, + uhost->control.buf, + uhost->control.pipe_in_num, + uhost->control.ctl_len); + + if (URB_DONE == usbh_urb_wait (uhost, uhost->control.pipe_in_num, DATA_STAGE_TIMEOUT)) { + uhost->control.ctl_state = CTL_STATUS_OUT; + + } +} + +/*! + \brief USB data OUT transaction + \param[in] uhost: pointer to USB host + \param[out] none + \retval none +*/ +static void usbh_data_out_transc (usbh_host *uhost) +{ + usbh_pipe_toggle_set(uhost->data, uhost->control.pipe_out_num, 1U); + + usbh_data_send (uhost->data, + uhost->control.buf, + uhost->control.pipe_out_num, + uhost->control.ctl_len); + + if (URB_DONE == usbh_urb_wait (uhost, uhost->control.pipe_out_num, DATA_STAGE_TIMEOUT)) { + uhost->control.ctl_state = CTL_STATUS_IN; + } +} + +/*! + \brief USB status IN transaction + \param[in] uhost: pointer to USB host + \param[out] none + \retval none +*/ +static void usbh_status_in_transc (usbh_host *uhost) +{ + uint8_t pp_num = uhost->control.pipe_in_num; + + usbh_data_recev (uhost->data, NULL, pp_num, 0U); + + if (URB_DONE == usbh_urb_wait (uhost, pp_num, NODATA_STAGE_TIMEOUT)) { + uhost->control.ctl_state = CTL_FINISH; + } +} + +/*! + \brief USB status OUT transaction + \param[in] uhost: pointer to USB host + \param[out] none + \retval none +*/ +static void usbh_status_out_transc (usbh_host *uhost) +{ + uint8_t pp_num = uhost->control.pipe_out_num; + + usbh_data_send (uhost->data, NULL, pp_num, 0U); + + if (URB_DONE == usbh_urb_wait (uhost, pp_num, NODATA_STAGE_TIMEOUT)) { + uhost->control.ctl_state = CTL_FINISH; + } +} + +/*! + \brief prepare a pipe and start a transfer + \param[in] udev: pointer to USB core instance + \param[in] pp_num: pipe number + \param[out] none + \retval operation status +*/ +static uint32_t usbh_request_submit (usb_core_driver *udev, uint8_t pp_num) +{ + udev->host.pipe[pp_num].urb_state = URB_IDLE; + udev->host.pipe[pp_num].xfer_count = 0U; + + return (uint32_t)usb_pipe_xfer (udev, pp_num); +} diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/ustd/class/cdc/usb_cdc.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/ustd/class/cdc/usb_cdc.h new file mode 100644 index 00000000..c586cace --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/ustd/class/cdc/usb_cdc.h @@ -0,0 +1,180 @@ +/*! + \file usb_cdc.h + \brief the header file of communication device class standard + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_CDC_H +#define __USB_CDC_H + +#include "usb_ch9_std.h" + +/* communications device class code */ +#define USB_CLASS_CDC 0x02U + +/* communications interface class control protocol codes */ +#define USB_CDC_PROTOCOL_NONE 0x00U +#define USB_CDC_PROTOCOL_AT 0x01U +#define USB_CDC_PROTOCOL_VENDOR 0xFFU + +/* data interface class code */ +#define USB_CLASS_DATA 0x0AU + +#define USB_DESCTYPE_CDC_ACM 0x21U +#define USB_DESCTYPE_CS_INTERFACE 0x24U + +#define USB_CDC_ACM_CONFIG_DESC_SIZE 0x43U + +/* class-specific notification codes for pstn subclasses */ +#define USB_CDC_NOTIFY_SERIAL_STATE 0x20U + +/* class-specific request codes */ +#define SEND_ENCAPSULATED_COMMAND 0x00U +#define GET_ENCAPSULATED_RESPONSE 0x01U +#define SET_COMM_FEATURE 0x02U +#define GET_COMM_FEATURE 0x03U +#define CLEAR_COMM_FEATURE 0x04U + +#define SET_AUX_LINE_STATE 0x10U +#define SET_HOOK_STATE 0x11U +#define PULSE_SETUP 0x12U +#define SEND_PULSE 0x13U +#define SET_PULSE_TIME 0x14U +#define RING_AUX_JACK 0x15U + +#define SET_LINE_CODING 0x20U +#define GET_LINE_CODING 0x21U +#define SET_CONTROL_LINE_STATE 0x22U +#define SEND_BREAK 0x23U +#define NO_CMD 0xFFU + +#define SET_RINGER_PARMS 0x30U +#define GET_RINGER_PARMS 0x31U +#define SET_OPERATION_PARMS 0x32U +#define GET_OPERATION_PARMS 0x33U +#define SET_LINE_PARMS 0x34U +#define GET_LINE_PARMS 0x35U +#define DIAL_DIGITS 0x36U +#define SET_UNIT_PARAMETER 0x37U +#define GET_UNIT_PARAMETER 0x38U +#define CLEAR_UNIT_PARAMETER 0x39U +#define GET_PROFILE 0x3AU + +#define SET_ETHERNET_MULTICAST_FILTERS 0x40U +#define SET_ETHERNET_POWER_MANAGEMENT_PATTERN FILTER 0x41U +#define GET_ETHERNET_POWER_MANAGEMENT_PATTERN FILTER 0x42U +#define SET_ETHERNET_PACKET_FILTER 0x43U +#define GET_ETHERNET_STATISTIC 0x44U + +#define SET_ATM_DATA_FORMAT 0x50U +#define GET_ATM_DEVICE_STATISTICS 0x51U +#define SET_ATM_DEFAULT_VC 0x52U +#define GET_ATM_VC_STATISTICS 0x53U + +/* wValue for set control line state */ +#define CDC_ACTIVATE_CARRIER_SIGNAL_RTS 0x0002U +#define CDC_DEACTIVATE_CARRIER_SIGNAL_RTS 0x0000U +#define CDC_ACTIVATE_SIGNAL_DTR 0x0001U +#define CDC_DEACTIVATE_SIGNAL_DTR 0x0000U + +/* CDC subclass code */ +enum usb_cdc_subclass { + USB_CDC_SUBCLASS_RESERVED = 0U, /*!< reserved */ + USB_CDC_SUBCLASS_DLCM, /*!< direct line control mode */ + USB_CDC_SUBCLASS_ACM, /*!< abstract control mode */ + USB_CDC_SUBCLASS_TCM, /*!< telephone control mode */ + USB_CDC_SUBCLASS_MCM, /*!< multichannel control model */ + USB_CDC_SUBCLASS_CCM, /*!< CAPI control model */ + USB_CDC_SUBCLASS_ENCM, /*!< ethernet networking control model */ + USB_CDC_SUBCLASS_ANCM /*!< ATM networking control model */ +}; + +#pragma pack(1) + +/* cdc acm line coding structure */ +typedef struct { + uint32_t dwDTERate; /*!< data terminal rate */ + uint8_t bCharFormat; /*!< stop bits */ + uint8_t bParityType; /*!< parity */ + uint8_t bDataBits; /*!< data bits */ +} acm_line; + +/* notification structure */ +typedef struct { + uint8_t bmRequestType; /*!< type of request */ + uint8_t bNotification; /*!< communication interface class notifications */ + uint16_t wValue; /*!< value of notification */ + uint16_t wIndex; /*!< index of interface */ + uint16_t wLength; /*!< length of notification data */ +} acm_notification; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: header function descriptor */ + uint16_t bcdCDC; /*!< bcdCDC: low byte of spec release number (CDC1.10) */ +} usb_desc_header_func; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: call management function descriptor */ + uint8_t bmCapabilities; /*!< bmCapabilities: D0 is reset, D1 is ignored */ + uint8_t bDataInterface; /*!< bDataInterface: 1 interface used for call management */ +} usb_desc_call_managment_func; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: abstract control management descriptor */ + uint8_t bmCapabilities; /*!< bmCapabilities: D1 */ +} usb_desc_acm_func; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: union function descriptor */ + uint8_t bMasterInterface; /*!< bMasterInterface: communication class interface */ + uint8_t bSlaveInterface0; /*!< bSlaveInterface0: data class interface */ +} usb_desc_union_func; + +#pragma pack() + +typedef struct { + usb_desc_config config; + usb_desc_itf cmd_itf; + usb_desc_header_func cdc_header; + usb_desc_call_managment_func cdc_call_managment; + usb_desc_acm_func cdc_acm; + usb_desc_union_func cdc_union; + usb_desc_ep cdc_cmd_endpoint; + usb_desc_itf cdc_data_interface; + usb_desc_ep cdc_out_endpoint; + usb_desc_ep cdc_in_endpoint; +} usb_cdc_desc_config_set; + +#endif /* __USB_CDC_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/ustd/class/hid/usb_hid.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/ustd/class/hid/usb_hid.h new file mode 100644 index 00000000..3c8adf89 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/ustd/class/hid/usb_hid.h @@ -0,0 +1,83 @@ +/*! + \file usb_hid.h + \brief definitions for the USB HID class + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_HID_H +#define __USB_HID_H + +#include "usb_ch9_std.h" + +#define USB_HID_CLASS 0x03U + +#define USB_DESCTYPE_HID 0x21U +#define USB_DESCTYPE_REPORT 0x22U + +/* HID subclass code */ +#define USB_HID_SUBCLASS_BOOT_ITF 0x01U + +/* HID protocol codes */ +#define USB_HID_PROTOCOL_KEYBOARD 0x01U +#define USB_HID_PROTOCOL_MOUSE 0x02U + +#define GET_REPORT 0x01U +#define GET_IDLE 0x02U +#define GET_PROTOCOL 0x03U +#define SET_REPORT 0x09U +#define SET_IDLE 0x0AU +#define SET_PROTOCOL 0x0BU + +#pragma pack(1) + +typedef struct +{ + usb_desc_header header; /*!< regular descriptor header containing the descriptor's type and length */ + + uint16_t bcdHID; /*!< BCD encoded version that the HID descriptor and device complies to */ + uint8_t bCountryCode; /*!< country code of the localized device, or zero if universal */ + uint8_t bNumDescriptors; /*!< total number of HID report descriptors for the interface */ + uint8_t bDescriptorType; /*!< type of HID report */ + uint16_t wDescriptorLength; /*!< length of the associated HID report descriptor, in bytes */ +} usb_desc_hid; + +#pragma pack() + +typedef struct +{ + usb_desc_config config; + usb_desc_itf hid_itf; + usb_desc_hid hid_vendor; + usb_desc_ep hid_epin; + usb_desc_ep hid_epout; +} usb_hid_desc_config_set; + +#endif /* __USB_HID_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/ustd/class/msc/msc_bbb.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/ustd/class/msc/msc_bbb.h new file mode 100644 index 00000000..630d908e --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/ustd/class/msc/msc_bbb.h @@ -0,0 +1,69 @@ +/*! + \file msc_bbb.h + \brief definitions for the USB MSC BBB(bulk/bulk/bulk) protocol + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __MSC_BBB_H +#define __MSC_BBB_H + +#include "usb_ch9_std.h" + +#define BBB_CBW_SIGNATURE 0x43425355U +#define BBB_CSW_SIGNATURE 0x53425355U +#define BBB_CBW_LENGTH 31U +#define BBB_CSW_LENGTH 13U + +typedef struct { + uint32_t dCBWSignature; + uint32_t dCBWTag; + uint32_t dCBWDataTransferLength; + uint8_t bmCBWFlags; + uint8_t bCBWLUN; + uint8_t bCBWCBLength; + uint8_t CBWCB[16]; +} msc_bbb_cbw; + +typedef struct { + uint32_t dCSWSignature; + uint32_t dCSWTag; + uint32_t dCSWDataResidue; + uint8_t bCSWStatus; +} msc_bbb_csw; + +/* CSW command status */ +enum msc_csw_status { + CSW_CMD_PASSED = 0, + CSW_CMD_FAILED, + CSW_PHASE_ERROR +}; + +#endif /* __MSC_BBB_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/ustd/class/msc/msc_scsi.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/ustd/class/msc/msc_scsi.h new file mode 100644 index 00000000..8a178c7d --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/ustd/class/msc/msc_scsi.h @@ -0,0 +1,117 @@ +/*! + \file msc_scsi.h + \brief definitions for the USB MSC SCSI commands + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __MSC_SCSI_H +#define __MSC_SCSI_H + +#include "usb_ch9_std.h" + +/* SCSI commands */ +#define SCSI_FORMAT_UNIT 0x04U +#define SCSI_INQUIRY 0x12U +#define SCSI_MODE_SELECT6 0x15U +#define SCSI_MODE_SELECT10 0x55U +#define SCSI_MODE_SENSE6 0x1AU +#define SCSI_READ_TOC_DATA 0x43U +#define SCSI_MODE_SENSE10 0x5AU +#define SCSI_ALLOW_MEDIUM_REMOVAL 0x1EU +#define SCSI_READ6 0x08U +#define SCSI_READ10 0x28U +#define SCSI_READ12 0xA8U +#define SCSI_READ16 0x88U + +#define SCSI_READ_CAPACITY10 0x25U +#define SCSI_READ_CAPACITY16 0x9EU + +#define SCSI_REQUEST_SENSE 0x03U +#define SCSI_START_STOP_UNIT 0x1BU +#define SCSI_TEST_UNIT_READY 0x00U +#define SCSI_WRITE6 0x0AU +#define SCSI_WRITE10 0x2AU +#define SCSI_WRITE12 0xAAU +#define SCSI_WRITE16 0x8AU + +#define SCSI_VERIFY10 0x2FU +#define SCSI_VERIFY12 0xAFU +#define SCSI_VERIFY16 0x8FU + +#define SCSI_SEND_DIAGNOSTIC 0x1DU +#define SCSI_READ_FORMAT_CAPACITIES 0x23U + +#define INVALID_CDB 0x20U +#define INVALID_FIELED_IN_COMMAND 0x24U +#define PARAMETER_LIST_LENGTH_ERROR 0x1AU +#define INVALID_FIELD_IN_PARAMETER_LIST 0x26U +#define ADDRESS_OUT_OF_RANGE 0x21U +#define MEDIUM_NOT_PRESENT 0x3AU +#define MEDIUM_HAVE_CHANGED 0x28U +#define WRITE_PROTECTED 0x27U +#define UNRECOVERED_READ_ERROR 0x11U +#define WRITE_FAULT 0x03U + +#define READ_FORMAT_CAPACITY_DATA_LEN 0x0CU +#define READ_CAPACITY10_DATA_LEN 0x08U +#define MODE_SENSE10_DATA_LEN 0x08U +#define MODE_SENSE6_DATA_LEN 0x04U +#define READ_TOC_CMD_LEN 0x14U +#define REQUEST_SENSE_DATA_LEN 0x12U +#define STANDARD_INQUIRY_DATA_LEN 0x24U +#define BLKVFY 0x04U + +enum sense_state { + NO_SENSE = 0U, + RECOVERED_ERROR, + NOT_READY, + MEDIUM_ERROR, + HARDWARE_ERROR, + ILLEGAL_REQUEST, + UNIT_ATTENTION, + DATA_PROTECT, + BLANK_CHECK, + VENDOR_SPECIFIC, + COPY_ABORTED, + ABORTED_COMMAND, + RESERVED, + VOLUME_OVERFLOW, + MISCOMPARE +}; + +typedef struct { + uint8_t SenseKey; + uint32_t Information; + uint8_t ASC; + uint8_t ASCQ; +} msc_scsi_sense; + +#endif /* __MSC_SCSI_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/ustd/class/msc/usb_msc.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/ustd/class/msc/usb_msc.h new file mode 100644 index 00000000..4bdb2418 --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/ustd/class/msc/usb_msc.h @@ -0,0 +1,68 @@ +/*! + \file usb_msc.h + \brief definitions for the USB MSC class + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_MSC_H +#define __USB_MSC_H + +#include "usb_ch9_std.h" + +/* mass storage device class code */ +#define USB_CLASS_MSC 0x08U + +/* mass storage subclass code */ +#define USB_MSC_SUBCLASS_RBC 0x01U +#define USB_MSC_SUBCLASS_ATAPI 0x02U +#define USB_MSC_SUBCLASS_UFI 0x04U +#define USB_MSC_SUBCLASS_SCSI 0x06U +#define USB_MSC_SUBCLASS_LOCKABLE 0x07U +#define USB_MSC_SUBCLASS_IEEE1667 0x08U + +/* mass storage interface class control protocol codes */ +#define USB_MSC_PROTOCOL_CBI 0x00U +#define USB_MSC_PROTOCOL_CBI_ALT 0x01U +#define USB_MSC_PROTOCOL_BBB 0x50U + +/* mass storage request codes */ +#define USB_MSC_REQ_CODES_ADSC 0x00U +#define USB_MSC_REQ_CODES_GET 0xFCU +#define USB_MSC_REQ_CODES_PUT 0xFDU +#define USB_MSC_REQ_CODES_GML 0xFEU +#define USB_MSC_REQ_CODES_BOMSR 0xFFU + +#define BBB_GET_MAX_LUN 0xFEU +#define BBB_RESET 0xFFU + +#define SCSI_CMD_LENGTH 16U + +#endif /* __USB_MSC_H */ diff --git a/lib-gd32/gd32f20x/GD32F20x_usbfs_library/ustd/common/usb_ch9_std.h b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/ustd/common/usb_ch9_std.h new file mode 100644 index 00000000..ab8d275e --- /dev/null +++ b/lib-gd32/gd32f20x/GD32F20x_usbfs_library/ustd/common/usb_ch9_std.h @@ -0,0 +1,248 @@ +/*! + \file usb_ch9_std.h + \brief USB 2.0 standard defines + + \version 2023-06-30, V2.5.0, firmware for GD32F20x +*/ + +/* + Copyright (c) 2023, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_CH9_STD_H +#define __USB_CH9_STD_H + +#include "usb_conf.h" + +#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /*!< USB device qualifier descriptor length */ +#define USB_DEV_DESC_LEN 0x12U /*!< USB device descriptor length */ +#define USB_CFG_DESC_LEN 0x09U /*!< USB configuration descriptor length */ +#define USB_ITF_DESC_LEN 0x09U /*!< USB interface descriptor length */ +#define USB_EP_DESC_LEN 0x07U /*!< USB endpoint descriptor length */ +#define USB_IAD_DESC_LEN 0x08U /*!< USB IAD descriptor length */ +#define USB_OTG_DESC_LEN 0x03U /*!< USB device OTG descriptor length */ + +#define USB_SETUP_PACKET_LEN 0x08U /*!< USB setup packet length */ + +/* bit 7 of bmRequestType: data phase transfer direction */ +#define USB_TRX_MASK 0x80U /*!< USB transfer direction mask */ +#define USB_TRX_OUT 0x00U /*!< USB transfer OUT direction */ +#define USB_TRX_IN 0x80U /*!< USB transfer IN direction */ + +/* bit 6..5 of bmRequestType: request type */ +#define USB_REQTYPE_STRD 0x00U /*!< USB standard request */ +#define USB_REQTYPE_CLASS 0x20U /*!< USB class request */ +#define USB_REQTYPE_VENDOR 0x40U /*!< USB vendor request */ +#define USB_REQTYPE_MASK 0x60U /*!< USB request mask */ + +#define USBD_BUS_POWERED 0x00U /*!< USB bus power supply */ +#define USBD_SELF_POWERED 0x01U /*!< USB self power supply */ + +#define USB_STATUS_REMOTE_WAKEUP 2U /*!< USB is in remote wakeup status */ +#define USB_STATUS_SELF_POWERED 1U /*!< USB is in self powered status */ + +/* bit 4..0 of bmRequestType: recipient type */ +enum _usb_recp_type { + USB_RECPTYPE_DEV = 0x0U, /*!< USB device request type */ + USB_RECPTYPE_ITF = 0x1U, /*!< USB interface request type */ + USB_RECPTYPE_EP = 0x2U, /*!< USB endpoint request type */ + USB_RECPTYPE_MASK = 0x3U /*!< USB request type mask */ +}; + +/* bRequest value */ +enum _usb_request { + USB_GET_STATUS = 0x0U, /*!< USB get status request */ + USB_CLEAR_FEATURE = 0x1U, /*!< USB clear feature request */ + USB_RESERVED2 = 0x2U, + USB_SET_FEATURE = 0x3U, /*!< USB set feature request */ + USB_RESERVED4 = 0x4U, + USB_SET_ADDRESS = 0x5U, /*!< USB set address request */ + USB_GET_DESCRIPTOR = 0x6U, /*!< USB get descriptor request */ + USB_SET_DESCRIPTOR = 0x7U, /*!< USB set descriptor request */ + USB_GET_CONFIGURATION = 0x8U, /*!< USB get configuration request */ + USB_SET_CONFIGURATION = 0x9U, /*!< USB set configuration request */ + USB_GET_INTERFACE = 0xAU, /*!< USB get interface request */ + USB_SET_INTERFACE = 0xBU, /*!< USB set interface request */ + USB_SYNCH_FRAME = 0xCU /*!< USB synchronize frame request */ +}; + +/* descriptor types of USB specifications */ +enum _usb_desctype { + USB_DESCTYPE_DEV = 0x1U, /*!< USB device descriptor type */ + USB_DESCTYPE_CONFIG = 0x2U, /*!< USB configuration descriptor type */ + USB_DESCTYPE_STR = 0x3U, /*!< USB string descriptor type */ + USB_DESCTYPE_ITF = 0x4U, /*!< USB interface descriptor type */ + USB_DESCTYPE_EP = 0x5U, /*!< USB endpoint descriptor type */ + USB_DESCTYPE_DEV_QUALIFIER = 0x6U, /*!< USB device qualifier descriptor type */ + USB_DESCTYPE_OTHER_SPD_CONFIG = 0x7U, /*!< USB other speed configuration descriptor type */ + USB_DESCTYPE_ITF_POWER = 0x8U, /*!< USB interface power descriptor type */ + USB_DESCTYPE_IAD = 0xBU, /*!< USB interface association descriptor type */ + USB_DESCTYPE_BOS = 0xFU /*!< USB BOS descriptor type */ +}; + +/* USB Endpoint Descriptor bmAttributes bit definitions */ +/* bits 1..0 : transfer type */ +enum _usbx_type { + USB_EP_ATTR_CTL = 0x0U, /*!< USB control transfer type */ + USB_EP_ATTR_ISO = 0x1U, /*!< USB Isochronous transfer type */ + USB_EP_ATTR_BULK = 0x2U, /*!< USB Bulk transfer type */ + USB_EP_ATTR_INT = 0x3U /*!< USB Interrupt transfer type */ +}; + +/* bits 3..2 : Sync type (only if ISOCHRONOUS) */ +#define USB_EP_ATTR_NOSYNC 0x00U /*!< No Synchronization */ +#define USB_EP_ATTR_ASYNC 0x04U /*!< Asynchronous */ +#define USB_EP_ATTR_ADAPTIVE 0x08U /*!< Adaptive */ +#define USB_EP_ATTR_SYNC 0x0CU /*!< Synchronous */ +#define USB_EP_ATTR_SYNCTYPE 0x0CU /*!< Synchronous type */ + +/* bits 5..4 : usage type (only if ISOCHRONOUS) */ +#define USB_EP_ATTR_DATA 0x00U /*!< Data endpoint */ +#define USB_EP_ATTR_FEEDBACK 0x10U /*!< Feedback endpoint */ +#define USB_EP_ATTR_IMPLICIT_FEEDBACK_DATA 0x20U /*!< Implicit feedback Data endpoint */ +#define USB_EP_ATTR_USAGETYPE 0x30U /*!< Usage type */ + +/* endpoint max packet size bits12..11 */ +#define USB_EP_MPS_ADD_0 (0x00 << 11) /*!< None(1 transaction per microframe */ +#define USB_EP_MPS_ADD_1 (0x01 << 11) /*!< 1 additional(2 transaction per microframe */ +#define USB_EP_MPS_ADD_2 (0x02 << 11) /*!< 2 additional(3 transaction per microframe */ + +#define FEATURE_SELECTOR_EP 0x00U /*!< USB endpoint feature selector */ +#define FEATURE_SELECTOR_DEV 0x01U /*!< USB device feature selector */ +#define FEATURE_SELECTOR_REMOTEWAKEUP 0x01U /*!< USB feature selector remote wakeup */ + +#define BYTE_SWAP(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ + (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) + +#define BYTE_LOW(x) ((uint8_t)((x) & 0x00FFU)) +#define BYTE_HIGH(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) + +#define USB_MIN(a, b) (((a) < (b)) ? (a) : (b)) + +#define USB_DEFAULT_CONFIG 0U + +/* USB classes */ +#define USB_CLASS_HID 0x03U /*!< USB HID class */ +#define USB_CLASS_MSC 0x08U /*!< USB MSC class */ + +/* use the following values when USB host need to get descriptor */ +#define USBH_DESC(x) (((x)<< 8U) & 0xFF00U) + +/* as per USB specs 9.2.6.4 :standard request with data request timeout: 5sec + standard request with no data stage timeout : 50ms */ +#define DATA_STAGE_TIMEOUT 5000U /*!< USB data stage timeout*/ +#define NODATA_STAGE_TIMEOUT 50U /*!< USB no data stage timeout*/ + +#pragma pack(1) + +/* USB standard device request structure */ +typedef struct _usb_req { + uint8_t bmRequestType; /*!< type of request */ + uint8_t bRequest; /*!< request of setup packet */ + uint16_t wValue; /*!< value of setup packet */ + uint16_t wIndex; /*!< index of setup packet */ + uint16_t wLength; /*!< length of setup packet */ +} usb_req; + +/* USB setup packet define */ +typedef union _usb_setup { + uint8_t data[8]; + + usb_req req; +} usb_setup; + +/* USB descriptor defines */ + +typedef struct _usb_desc_header { + uint8_t bLength; /*!< size of the descriptor */ + uint8_t bDescriptorType; /*!< type of the descriptor */ +} usb_desc_header; + +typedef struct _usb_desc_dev { + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint16_t bcdUSB; /*!< BCD of the supported USB specification */ + uint8_t bDeviceClass; /*!< USB device class */ + uint8_t bDeviceSubClass; /*!< USB device subclass */ + uint8_t bDeviceProtocol; /*!< USB device protocol */ + uint8_t bMaxPacketSize0; /*!< size of the control (address 0) endpoint's bank in bytes */ + uint16_t idVendor; /*!< vendor ID for the USB product */ + uint16_t idProduct; /*!< unique product ID for the USB product */ + uint16_t bcdDevice; /*!< product release (version) number */ + uint8_t iManufacturer; /*!< string index for the manufacturer's name */ + uint8_t iProduct; /*!< string index for the product name/details */ + uint8_t iSerialNumber; /*!< string index for the product's globally unique hexadecimal serial number */ + uint8_t bNumberConfigurations; /*!< total number of configurations supported by the device */ +} usb_desc_dev; + +typedef struct _usb_desc_config { + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint16_t wTotalLength; /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */ + uint8_t bNumInterfaces; /*!< total number of interfaces in the configuration */ + uint8_t bConfigurationValue; /*!< configuration index of the current configuration */ + uint8_t iConfiguration; /*!< index of a string descriptor describing the configuration */ + uint8_t bmAttributes; /*!< configuration attributes */ + uint8_t bMaxPower; /*!< maximum power consumption of the device while in the current configuration */ +} usb_desc_config; + +typedef struct _usb_desc_itf { + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint8_t bInterfaceNumber; /*!< index of the interface in the current configuration */ + uint8_t bAlternateSetting; /*!< alternate setting for the interface number */ + uint8_t bNumEndpoints; /*!< total number of endpoints in the interface */ + uint8_t bInterfaceClass; /*!< interface class ID */ + uint8_t bInterfaceSubClass; /*!< interface subclass ID */ + uint8_t bInterfaceProtocol; /*!< interface protocol ID */ + uint8_t iInterface; /*!< index of the string descriptor describing the interface */ +} usb_desc_itf; + +typedef struct _usb_desc_ep { + usb_desc_header header; /*!< descriptor header, including type and size. */ + + uint8_t bEndpointAddress; /*!< logical address of the endpoint */ + uint8_t bmAttributes; /*!< endpoint attributes */ + uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */ + uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */ +} usb_desc_ep; + +typedef struct _usb_desc_LANGID { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint16_t wLANGID; /*!< LANGID code */ +} usb_desc_LANGID; + +typedef struct _usb_desc_str { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint16_t unicode_string[128]; /*!< unicode string data */ +} usb_desc_str; + +#pragma pack() + +/* compute string descriptor length */ +#define USB_STRING_LEN(unicode_chars) (sizeof(usb_desc_header) + ((unicode_chars) << 1U)) + +#endif /* __USB_CH9_STD_H */ diff --git a/lib-gd32/include/FreeRTOSConfig.h b/lib-gd32/include/FreeRTOSConfig.h new file mode 100644 index 00000000..28b79c84 --- /dev/null +++ b/lib-gd32/include/FreeRTOSConfig.h @@ -0,0 +1,164 @@ +/* + FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__TASKING__) || defined(__GNUC__) +#include +extern uint32_t SystemCoreClock; +#endif + + +#define configUSE_PREEMPTION 1 +#define configCPU_CLOCK_HZ ( SystemCoreClock ) +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configMAX_PRIORITIES ( 8 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 30 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_APPLICATION_TASK_TAG 0 + + +/* hook function related definitions */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 + +/* run time and task stats gathering related definitions */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 + + +/* co-routine definitions */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* software timer definitions */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( 2 ) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +/* set to 1 to include the API function, or 0 to exclude the API function */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + + + +/* Cortex-M specific definitions */ +#ifdef __NVIC_PRIO_BITS + /* __NVIC_PRIO_BITS will be specified when CMSIS is being used. */ + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 4 /* 15 priority levels */ +#endif + +/* the lowest interrupt priority that can be used in a call to a "set priority" function */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. Do not call +interrupt safe freertos api functions from any interrupt that has a higher +priority than this! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* interrupt priorities used by the kernel port layer itself */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + + + + +/* normal assert() semantics without relying on the provision of an assert.h header file */ +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* map the FreeRTOS port interrupt handlers to CMSIS standard names */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/lib-gd32/include/board/bw_opidmx4.h b/lib-gd32/include/board/bw_opidmx4.h index 2d93a0dd..999a89cc 100644 --- a/lib-gd32/include/board/bw_opidmx4.h +++ b/lib-gd32/include/board/bw_opidmx4.h @@ -2,7 +2,7 @@ * @file bw_opidmx4.h * */ -/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -38,6 +38,8 @@ # error USART0 is used for console #endif +#include + /** * LEDs */ @@ -75,30 +77,32 @@ */ #define I2C0_REMAP -#define I2C_REMAP GPIO_I2C0_REMAP -#define I2C_PERIPH I2C0_PERIPH -#define I2C_RCU_CLK I2C0_RCU_CLK -#define I2C_GPIO_SCL_PORT I2C0_SCL_GPIOx -#define I2C_GPIO_SCL_CLK I2C0_SCL_RCU_GPIOx -#define I2C_GPIO_SDA_PORT I2C0_SDA_GPIOx -#define I2C_GPIO_SDA_CLK I2C0_SDA_RCU_GPIOx -#define I2C_SCL_PIN I2C0_SCL_GPIO_PINx -#define I2C_SDA_PIN I2C0_SDA_GPIO_PINx +#define I2C_REMAP GPIO_I2C0_REMAP +#define I2C_PERIPH I2C0_PERIPH +#define I2C_RCU_I2Cx I2C0_RCU_I2C0 +#define I2C_GPIO_AFx I2C0_GPIO_AFx +#define I2C_SCL_RCU_GPIOx I2C0_SCL_RCU_GPIOx +#define I2C_SCL_GPIOx I2C0_SCL_GPIOx +#define I2C_SCL_GPIO_PINx I2C0_SCL_GPIO_PINx +#define I2C_SDA_RCU_GPIOx I2C0_SDA_RCU_GPIOx +#define I2C_SDA_GPIOx I2C0_SDA_GPIOx +#define I2C_SDA_GPIO_PINx I2C0_SDA_GPIO_PINx /** * SPI */ #define SPI_PERIPH SPI2_PERIPH +#define SPI_RCU_SPIx SPI2_RCU_SPI2 +#define SPI_RCU_GPIOx SPI2_RCU_GPIOx +#define SPI_GPIO_AFx SPI2_GPIO_AFx +#define SPI_GPIOx SPI2_GPIOx +#define SPI_SCK_GPIO_PINx SPI2_SCK_GPIO_PINx +#define SPI_MISO_GPIO_PINx SPI2_MISO_GPIO_PINx +#define SPI_MOSI_GPIO_PINx SPI2_MOSI_GPIO_PINx #define SPI_NSS_GPIOx SPI2_NSS_GPIOx #define SPI_NSS_RCU_GPIOx SPI2_NSS_RCU_GPIOx #define SPI_NSS_GPIO_PINx SPI2_NSS_GPIO_PINx -#define SPI_RCU_CLK SPI2_RCU_CLK -#define SPI_GPIOx SPI2_GPIOx -#define SPI_RCU_GPIOx SPI2_RCU_GPIOx -#define SPI_SCK_PIN SPI2_SCK_GPIO_PINx -#define SPI_MISO_PIN SPI2_MISO_GPIO_PINx -#define SPI_MOSI_PIN SPI2_MOSI_GPIO_PINx #define SPI_DMAx SPI2_DMAx #define SPI_DMA_CHx SPI2_TX_DMA_CHx #define SPI_DMA_SUBPERIx SPI2_TX_DMA_SUBPERIx @@ -113,6 +117,7 @@ /** * Panel LEDs */ + #ifdef __cplusplus namespace hal { namespace panelled { @@ -138,9 +143,9 @@ static constexpr uint32_t PORT_A_TX = 0; * SPI flash */ -#define SPI_FLASH_CS_GPIOx GPIOB -#define SPI_FLASH_CS_RCU_GPIOx RCU_GPIOB -#define SPI_FLASH_CS_GPIO_PINx GPIO_PIN_1 +#define SPI_FLASH_CS_RCU_GPIOx RCU_GPIOB +#define SPI_FLASH_CS_GPIOx GPIOB +#define SPI_FLASH_CS_GPIO_PINx GPIO_PIN_1 /** * EXT PHY @@ -171,7 +176,7 @@ static constexpr uint32_t PORT_A_TX = 0; */ #if defined (GD32F20X_CL) -# include "mcu/gd32f20x_mcu.h" +# include "mcu/gd32f207_mcu.h" # define GD32_MCU_NAME "GD32F207RG" #elif defined (GD32F407) # include "mcu/gd32f407_mcu.h" @@ -189,15 +194,21 @@ static constexpr uint32_t PORT_A_TX = 0; #define GD32_BOARD_LED3 GD32_PORT_TO_GPIO(GD32_GPIO_PORTC, 3) #define GD32_BOARD_STATUS_LED GD32_BOARD_LED1 +/** + * LCD + */ + +#define DISPLAYTIMEOUT_GPIO GD32_PORT_TO_GPIO(GD32_GPIO_PORTA, 14) // KEY2 + /** * SPI LCD */ -#define SPI_LCD_RST_PIN GPIO_EXT_7 -#define SPI_LCD_DC_PIN GPIO_EXT_26 -#define SPI_LCD_BL_PIN GPIO_EXT_22 -#if defined(SPI_LCD_HAVE_CS_PIN) -# define SPI_LCD_CS_PIN GPIO_EXT_24 +#define SPI_LCD_RST_PIN GPIO_EXT_7 +#define SPI_LCD_DC_GPIO GPIO_EXT_26 +#define SPI_LCD_BL_GPIO GPIO_EXT_22 +#if defined(SPI_LCD_HAVE_CS_GPIO) +# define SPI_LCD_CS_GPIO GPIO_EXT_24 #endif #include "gpio_header.h" diff --git a/lib-gd32/include/board/dmx3.h b/lib-gd32/include/board/dmx3.h index fe73db40..594e39a9 100644 --- a/lib-gd32/include/board/dmx3.h +++ b/lib-gd32/include/board/dmx3.h @@ -2,7 +2,7 @@ * @file dmx3.h * */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,6 +34,8 @@ # error This file should be included later #endif +#include + /** * LEDs */ @@ -71,30 +73,32 @@ */ #define I2C0_REMAP -#define I2C_REMAP GPIO_I2C0_REMAP -#define I2C_PERIPH I2C0_PERIPH -#define I2C_RCU_CLK I2C0_RCU_CLK -#define I2C_GPIO_SCL_PORT I2C0_SCL_GPIOx -#define I2C_GPIO_SCL_CLK I2C0_SCL_RCU_GPIOx -#define I2C_GPIO_SDA_PORT I2C0_SDA_GPIOx -#define I2C_GPIO_SDA_CLK I2C0_SDA_RCU_GPIOx -#define I2C_SCL_PIN I2C0_SCL_GPIO_PINx -#define I2C_SDA_PIN I2C0_SDA_GPIO_PINx +#define I2C_REMAP GPIO_I2C0_REMAP +#define I2C_PERIPH I2C0_PERIPH +#define I2C_RCU_I2Cx I2C0_RCU_I2C0 +#define I2C_GPIO_AFx I2C0_GPIO_AFx +#define I2C_SCL_RCU_GPIOx I2C0_SCL_RCU_GPIOx +#define I2C_SCL_GPIOx I2C0_SCL_GPIOx +#define I2C_SCL_GPIO_PINx I2C0_SCL_GPIO_PINx +#define I2C_SDA_RCU_GPIOx I2C0_SDA_RCU_GPIOx +#define I2C_SDA_GPIOx I2C0_SDA_GPIOx +#define I2C_SDA_GPIO_PINx I2C0_SDA_GPIO_PINx /** * SPI */ #define SPI_PERIPH SPI2_PERIPH +#define SPI_RCU_SPIx SPI2_RCU_SPI2 +#define SPI_RCU_GPIOx SPI2_RCU_GPIOx +#define SPI_GPIO_AFx SPI2_GPIO_AFx +#define SPI_GPIOx SPI2_GPIOx +#define SPI_SCK_GPIO_PINx SPI2_SCK_GPIO_PINx +#define SPI_MISO_GPIO_PINx SPI2_MISO_GPIO_PINx +#define SPI_MOSI_GPIO_PINx SPI2_MOSI_GPIO_PINx #define SPI_NSS_GPIOx SPI2_NSS_GPIOx #define SPI_NSS_RCU_GPIOx SPI2_NSS_RCU_GPIOx #define SPI_NSS_GPIO_PINx SPI2_NSS_GPIO_PINx -#define SPI_RCU_CLK SPI2_RCU_CLK -#define SPI_GPIOx SPI2_GPIOx -#define SPI_RCU_GPIOx SPI2_RCU_GPIOx -#define SPI_SCK_PIN SPI2_SCK_GPIO_PINx -#define SPI_MISO_PIN SPI2_MISO_GPIO_PINx -#define SPI_MOSI_PIN SPI2_MOSI_GPIO_PINx #define SPI_DMAx SPI2_DMAx #define SPI_DMA_CHx SPI2_TX_DMA_CHx #define SPI_DMA_SUBPERIx SPI2_TX_DMA_SUBPERIx @@ -109,6 +113,7 @@ /** * Panel LEDs */ + #ifdef __cplusplus namespace hal { namespace panelled { @@ -124,19 +129,26 @@ static constexpr uint32_t OSC_IN = 0; static constexpr uint32_t OSC_OUT = 0; static constexpr uint32_t TCNET = 0; // DMX -static constexpr uint32_t PORT_A_RX = 0; -static constexpr uint32_t PORT_A_TX = 0; +static constexpr uint32_t PORT_A_TX = (1U << 0); +static constexpr uint32_t PORT_A_RX = (1U << 8); +#define CONFIG_PANELLED_RDM_PORT +static constexpr uint32_t PORT_A_RDM = (1U << 16); } // namespace panelled } // namespace hal #endif +#define PANELLED_595_COUNT 2 +#define PANELLED_595_CS_GPIOx GPIOA +#define PANELLED_595_CS_RCU_GPIOx RCU_GPIOA +#define PANELLED_595_CS_GPIO_PINx GPIO_PIN_15 + /** * SPI flash */ -#define SPI_FLASH_CS_GPIOx GPIOB -#define SPI_FLASH_CS_RCU_GPIOx RCU_GPIOB -#define SPI_FLASH_CS_GPIO_PINx GPIO_PIN_1 +#define SPI_FLASH_CS_RCU_GPIOx RCU_GPIOB +#define SPI_FLASH_CS_GPIOx GPIOB +#define SPI_FLASH_CS_GPIO_PINx GPIO_PIN_1 /** * EXT PHY @@ -167,7 +179,7 @@ static constexpr uint32_t PORT_A_TX = 0; */ #if defined (GD32F20X_CL) -# include "mcu/gd32f20x_mcu.h" +# include "mcu/gd32f207_mcu.h" # define GD32_MCU_NAME "GD32F207RG" #elif defined (GD32F407) # include "mcu/gd32f407_mcu.h" @@ -185,15 +197,21 @@ static constexpr uint32_t PORT_A_TX = 0; #define GD32_BOARD_LED3 GD32_PORT_TO_GPIO(GD32_GPIO_PORTC, 3) #define GD32_BOARD_STATUS_LED GD32_BOARD_LED1 +/** + * LCD + */ + +#define DISPLAYTIMEOUT_GPIO GD32_PORT_TO_GPIO(GD32_GPIO_PORTA, 14) // KEY2 + /** * SPI LCD */ -#define SPI_LCD_RST_PIN GPIO_EXT_7 -#define SPI_LCD_DC_PIN GPIO_EXT_26 -#define SPI_LCD_BL_PIN GPIO_EXT_22 -#if defined(SPI_LCD_HAVE_CS_PIN) -# define SPI_LCD_CS_PIN GPIO_EXT_24 +#define SPI_LCD_RST_PIN GPIO_EXT_7 +#define SPI_LCD_DC_GPIO GPIO_EXT_26 +#define SPI_LCD_BL_GPIO GPIO_EXT_22 +#if defined(SPI_LCD_HAVE_CS_GPIO) +# define SPI_LCD_CS_GPIO GPIO_EXT_24 #endif #include "gpio_header.h" diff --git a/lib-gd32/include/board/dmx4.h b/lib-gd32/include/board/dmx4.h index 9826e5f3..8f1bdf32 100644 --- a/lib-gd32/include/board/dmx4.h +++ b/lib-gd32/include/board/dmx4.h @@ -2,7 +2,7 @@ * @file dmx4.h * */ -/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -38,6 +38,8 @@ # error USART0 is used for console #endif +#include + /** * LEDs */ @@ -75,30 +77,32 @@ */ #define I2C0_REMAP -#define I2C_REMAP GPIO_I2C0_REMAP -#define I2C_PERIPH I2C0_PERIPH -#define I2C_RCU_CLK I2C0_RCU_CLK -#define I2C_GPIO_SCL_PORT I2C0_SCL_GPIOx -#define I2C_GPIO_SCL_CLK I2C0_SCL_RCU_GPIOx -#define I2C_GPIO_SDA_PORT I2C0_SDA_GPIOx -#define I2C_GPIO_SDA_CLK I2C0_SDA_RCU_GPIOx -#define I2C_SCL_PIN I2C0_SCL_GPIO_PINx -#define I2C_SDA_PIN I2C0_SDA_GPIO_PINx +#define I2C_REMAP GPIO_I2C0_REMAP +#define I2C_PERIPH I2C0_PERIPH +#define I2C_RCU_I2Cx I2C0_RCU_I2C0 +#define I2C_GPIO_AFx I2C0_GPIO_AFx +#define I2C_SCL_RCU_GPIOx I2C0_SCL_RCU_GPIOx +#define I2C_SCL_GPIOx I2C0_SCL_GPIOx +#define I2C_SCL_GPIO_PINx I2C0_SCL_GPIO_PINx +#define I2C_SDA_RCU_GPIOx I2C0_SDA_RCU_GPIOx +#define I2C_SDA_GPIOx I2C0_SDA_GPIOx +#define I2C_SDA_GPIO_PINx I2C0_SDA_GPIO_PINx /** * SPI */ #define SPI_PERIPH SPI2_PERIPH +#define SPI_RCU_SPIx SPI2_RCU_SPI2 +#define SPI_RCU_GPIOx SPI2_RCU_GPIOx +#define SPI_GPIO_AFx SPI2_GPIO_AFx +#define SPI_GPIOx SPI2_GPIOx +#define SPI_SCK_GPIO_PINx SPI2_SCK_GPIO_PINx +#define SPI_MISO_GPIO_PINx SPI2_MISO_GPIO_PINx +#define SPI_MOSI_GPIO_PINx SPI2_MOSI_GPIO_PINx #define SPI_NSS_GPIOx SPI2_NSS_GPIOx #define SPI_NSS_RCU_GPIOx SPI2_NSS_RCU_GPIOx #define SPI_NSS_GPIO_PINx SPI2_NSS_GPIO_PINx -#define SPI_RCU_CLK SPI2_RCU_CLK -#define SPI_GPIOx SPI2_GPIOx -#define SPI_RCU_GPIOx SPI2_RCU_GPIOx -#define SPI_SCK_PIN SPI2_SCK_GPIO_PINx -#define SPI_MISO_PIN SPI2_MISO_GPIO_PINx -#define SPI_MOSI_PIN SPI2_MOSI_GPIO_PINx #define SPI_DMAx SPI2_DMAx #define SPI_DMA_CHx SPI2_TX_DMA_CHx #define SPI_DMA_SUBPERIx SPI2_TX_DMA_SUBPERIx @@ -113,6 +117,7 @@ /** * Panel LEDs */ + #ifdef __cplusplus namespace hal { namespace panelled { @@ -128,24 +133,26 @@ static constexpr uint32_t OSC_IN = 0; static constexpr uint32_t OSC_OUT = 0; static constexpr uint32_t TCNET = 0; // DMX -static constexpr uint32_t PORT_A_TX = (1U << 0); -static constexpr uint32_t PORT_A_RX = (1U << 8); +static constexpr uint32_t PORT_A_TX = (1U << 0); +static constexpr uint32_t PORT_A_RX = (1U << 8); +#define CONFIG_PANELLED_RDM_PORT +static constexpr uint32_t PORT_A_RDM = (1U << 16); } // namespace panelled } // namespace hal #endif -#define LEDPANEL_595_COUNT 2 -#define LEDPANEL_595_CS_GPIOx GPIOA -#define LEDPANEL_595_CS_RCU_GPIOx RCU_GPIOA -#define LEDPANEL_595_CS_GPIO_PINx GPIO_PIN_15 +#define PANELLED_595_COUNT 2 +#define PANELLED_595_CS_GPIOx GPIOA +#define PANELLED_595_CS_RCU_GPIOx RCU_GPIOA +#define PANELLED_595_CS_GPIO_PINx GPIO_PIN_15 /** * SPI flash */ -#define SPI_FLASH_CS_GPIOx GPIOB -#define SPI_FLASH_CS_RCU_GPIOx RCU_GPIOB -#define SPI_FLASH_CS_GPIO_PINx GPIO_PIN_1 +#define SPI_FLASH_CS_RCU_GPIOx RCU_GPIOB +#define SPI_FLASH_CS_GPIOx GPIOB +#define SPI_FLASH_CS_GPIO_PINx GPIO_PIN_1 /** * EXT PHY @@ -176,7 +183,7 @@ static constexpr uint32_t PORT_A_RX = (1U << 8); */ #if defined (GD32F20X_CL) -# include "mcu/gd32f20x_mcu.h" +# include "mcu/gd32f207_mcu.h" # define GD32_MCU_NAME "GD32F207RG" #elif defined (GD32F407) # include "mcu/gd32f407_mcu.h" @@ -194,15 +201,21 @@ static constexpr uint32_t PORT_A_RX = (1U << 8); #define GD32_BOARD_LED3 GD32_PORT_TO_GPIO(GD32_GPIO_PORTC, 3) #define GD32_BOARD_STATUS_LED GD32_BOARD_LED1 +/** + * LCD + */ + +#define DISPLAYTIMEOUT_GPIO GD32_PORT_TO_GPIO(GD32_GPIO_PORTA, 14) // KEY2 + /** * SPI LCD */ -#define SPI_LCD_RST_PIN GPIO_EXT_7 -#define SPI_LCD_DC_PIN GPIO_EXT_26 -#define SPI_LCD_BL_PIN GPIO_EXT_22 -#if defined(SPI_LCD_HAVE_CS_PIN) -# define SPI_LCD_CS_PIN GPIO_EXT_24 +#define SPI_LCD_RST_PIN GPIO_EXT_7 +#define SPI_LCD_DC_GPIO GPIO_EXT_26 +#define SPI_LCD_BL_GPIO GPIO_EXT_22 +#if defined(SPI_LCD_HAVE_CS_GPIO) +# define SPI_LCD_CS_GPIO GPIO_EXT_24 #endif #include "gpio_header.h" diff --git a/lib-gd32/include/board/gd32f207rg.h b/lib-gd32/include/board/gd32f207rg.h index 0bdb16f7..142622ed 100644 --- a/lib-gd32/include/board/gd32f207rg.h +++ b/lib-gd32/include/board/gd32f207rg.h @@ -2,7 +2,7 @@ * @file gd32f207rg.h * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,6 +34,15 @@ # error This file should be included later #endif +#include + +/** + * U(S)ART + */ + +#define USART0_REMAP +#define USART2_PARTIAL_REMAP + /** * LEDs */ @@ -77,41 +86,103 @@ #define I2C0_REMAP #define I2C_REMAP GPIO_I2C0_REMAP #define I2C_PERIPH I2C0_PERIPH -#define I2C_RCU_CLK I2C0_RCU_CLK -#define I2C_GPIO_SCL_PORT I2C0_SCL_GPIOx -#define I2C_GPIO_SCL_CLK I2C0_SCL_RCU_GPIOx -#define I2C_GPIO_SDA_PORT I2C0_SDA_GPIOx -#define I2C_GPIO_SDA_CLK I2C0_SDA_RCU_GPIOx -#define I2C_SCL_PIN I2C0_SCL_GPIO_PINx -#define I2C_SDA_PIN I2C0_SDA_GPIO_PINx +#define I2C_RCU_I2Cx I2C0_RCU_I2C0 +#define I2C_SCL_RCU_GPIOx I2C0_SCL_RCU_GPIOx +#define I2C_SCL_GPIOx I2C0_SCL_GPIOx +#define I2C_SCL_GPIO_PINx I2C0_SCL_GPIO_PINx +#define I2C_SDA_RCU_GPIOx I2C0_SDA_RCU_GPIOx +#define I2C_SDA_GPIOx I2C0_SDA_GPIOx +#define I2C_SDA_GPIO_PINx I2C0_SDA_GPIO_PINx /** * SPI */ -#define SPI_PERIPH SPI2_PERIPH -#define SPI_NSS_GPIOx SPI2_NSS_GPIOx -#define SPI_NSS_RCU_GPIOx SPI2_NSS_RCU_GPIOx -#define SPI_NSS_GPIO_PINx SPI2_NSS_GPIO_PINx -#define SPI_RCU_CLK SPI2_RCU_CLK -#define SPI_GPIOx SPI2_GPIOx -#define SPI_RCU_GPIOx SPI2_RCU_GPIOx -#define SPI_SCK_PIN SPI2_SCK_GPIO_PINx -#define SPI_MISO_PIN SPI2_MISO_GPIO_PINx -#define SPI_MOSI_PIN SPI2_MOSI_GPIO_PINx -#define SPI_DMAx SPI2_DMAx -#define SPI_DMA_CHx SPI2_TX_DMA_CHx +#if defined (CONFIG_SPI_USE_SPI2) +# define SPI2_REMAP +# define SPI_REMAP_GPIO SPI2_REMAP_GPIO +# define SPI_PERIPH SPI2_PERIPH +# define SPI_RCU_SPIx SPI2_RCU_SPI2 +# define SPI_RCU_GPIOx SPI2_RCU_GPIOx +# define SPI_GPIOx SPI2_GPIOx +# define SPI_SCK_GPIO_PINx SPI2_SCK_GPIO_PINx +# define SPI_MISO_GPIO_PINx SPI2_MISO_GPIO_PINx +# define SPI_MOSI_GPIO_PINx SPI2_MOSI_GPIO_PINx +# define SPI_NSS_RCU_GPIOx RCU_GPIOC +# define SPI_NSS_GPIOx GPIOC +# define SPI_NSS_GPIO_PINx GPIO_PIN_13 +# define SPI_DMAx SPI2_DMAx +# define SPI_DMA_CHx SPI2_TX_DMA_CHx +#else +# define SPI0_REMAP +# if defined (SPI0_REMAP) +# define SPI_REMAP_GPIO SPI0_REMAP_GPIO +# endif +# define SPI_PERIPH SPI0_PERIPH +# define SPI_RCU_SPIx SPI0_RCU_SPI0 +# define SPI_RCU_GPIOx SPI0_RCU_GPIOx +# define SPI_GPIOx SPI0_GPIOx +# define SPI_SCK_GPIO_PINx SPI0_SCK_GPIO_PINx +# define SPI_MISO_GPIO_PINx SPI0_MISO_GPIO_PINx +# define SPI_MOSI_GPIO_PINx SPI0_MOSI_GPIO_PINx +# define SPI_NSS_RCU_GPIOx SPI0_NSS_RCU_GPIOx +# define SPI_NSS_GPIOx SPI0_NSS_GPIOx +# define SPI_NSS_GPIO_PINx SPI0_NSS_GPIO_PINx +# define SPI_DMAx SPI0_DMAx +# define SPI_DMA_CHx SPI0_TX_DMA_CHx +#endif /** - * U(S)ART + * I2S */ -#define USART0_REMAP -#define USART2_PARTIAL_REMAP +#define SPI2_REMAP +#if defined (SPI2_REMAP) +# define I2S_REMAP_GPIO SPI2_REMAP_GPIO +#endif +#define I2S_PERIPH SPI2_PERIPH +#define I2S_RCU_SPIx SPI2_RCU_SPI2 +#define I2S_RCU_GPIOx SPI2_RCU_GPIOx +#define I2S_GPIOx SPI2_GPIOx +#define I2S_CK_GPIO_PINx SPI2_SCK_GPIO_PINx +#define I2S_SD_GPIO_PINx SPI2_MOSI_GPIO_PINx +#define I2S_WS_RCU_GPIOx SPI2_NSS_RCU_GPIOx +#define I2S_WS_GPIOx SPI2_NSS_GPIOx +#define I2S_WS_GPIO_PINx SPI2_NSS_GPIO_PINx +#define I2S_DMAx SPI2_DMAx +#define I2S_DMA_CHx SPI2_TX_DMA_CHx + +/** + * PWM + */ + +#define PWM_TIMERx TIMER2 +#define PWM_RCU_TIMERx RCU_TIMER2 + +#define TIMER2_FULL_REMAP +#define PWM_TIMER_REMAP TIMER2_REMAP +#define PWM_GPIO_AFx TIMER2_GPIO_AFx + +#define PWM_CH0_RCU_GPIOx TIMER2_CH0_RCU_GPIOx +#define PWM_CH0_GPIOx TIMER2_CH0_GPIOx +#define PWM_CH0_GPIO_PINx TIMER2_CH0_GPIO_PINx + +#define PWM_CH1_RCU_GPIOx TIMER2_CH1_RCU_GPIOx +#define PWM_CH1_GPIOx TIMER2_CH1_GPIOx +#define PWM_CH1_GPIO_PINx TIMER2_CH1_GPIO_PINx + +#define PWM_CH2_RCU_GPIOx TIMER2_CH2_RCU_GPIOx +#define PWM_CH2_GPIOx TIMER2_CH2_GPIOx +#define PWM_CH2_GPIO_PINx TIMER2_CH2_GPIO_PINx + +#define PWM_CH3_RCU_GPIOx TIMER2_CH3_RCU_GPIOx +#define PWM_CH3_GPIOx TIMER2_CH3_GPIOx +#define PWM_CH3_GPIO_PINx TIMER2_CH3_GPIO_PINx /** * Panel LEDs */ + #ifdef __cplusplus namespace hal { namespace panelled { @@ -137,9 +208,9 @@ static constexpr uint32_t PORT_A_TX = 0; * SPI flash */ -#define SPI_FLASH_CS_GPIOx GPIOB -#define SPI_FLASH_CS_RCU_GPIOx RCU_GPIOB -#define SPI_FLASH_CS_GPIO_PINx GPIO_PIN_1 +#define SPI_FLASH_CS_RCU_GPIOx RCU_GPIOB +#define SPI_FLASH_CS_GPIOx GPIOB +#define SPI_FLASH_CS_GPIO_PINx GPIO_PIN_1 /** * EXT PHY @@ -165,7 +236,7 @@ static constexpr uint32_t PORT_A_TX = 0; #define GD32_MCU_NAME "GD32F207RG" #define GD32_BOARD_NAME "GD32F207RG" -#include "mcu/gd32f20x_mcu.h" +#include "mcu/gd32f207_mcu.h" #include "gd32_gpio.h" #define GD32_BOARD_LED1 GD32_PORT_TO_GPIO(GD32_GPIO_PORTC, 0) @@ -173,17 +244,37 @@ static constexpr uint32_t PORT_A_TX = 0; #define GD32_BOARD_LED3 GD32_PORT_TO_GPIO(GD32_GPIO_PORTC, 3) #define GD32_BOARD_STATUS_LED GD32_BOARD_LED1 +/** + * LCD + */ + +#define DISPLAYTIMEOUT_GPIO GD32_PORT_TO_GPIO(GD32_GPIO_PORTB, 14) // KEY2 + +/** + * Pixel DMX + */ + +#define PIXELDMXSTARTSTOP_GPIO GD32_BOARD_LED2 + /** * SPI LCD */ #define SPI_LCD_RST_PIN GPIO_EXT_7 -#define SPI_LCD_DC_PIN GPIO_EXT_26 -#define SPI_LCD_BL_PIN GPIO_EXT_22 -#if defined(SPI_LCD_HAVE_CS_PIN) -# define SPI_LCD_CS_PIN GPIO_EXT_24 +#define SPI_LCD_DC_GPIO GPIO_EXT_26 +#define SPI_LCD_BL_GPIO GPIO_EXT_22 +#if defined(SPI_LCD_HAVE_CS_GPIO) +# define SPI_LCD_CS_GPIO GPIO_EXT_24 #endif +/** + * FT8xx LCD + */ + +#define FT8XX_LCD_DC_GPIO GPIO_EXT_26 +#define FT8XX_LCD_CS_GPIO GPIO_EXT_22 +#define FT8XX_LCD_INT_GPIO GPIO_EXT_12 + #include "gpio_header.h" #endif /* BOARD_GD32F207R_H_ */ diff --git a/lib-gd32/include/board/logic_analyzer.h b/lib-gd32/include/board/logic_analyzer.h index e3bc5fa1..9c2ab503 100644 --- a/lib-gd32/include/board/logic_analyzer.h +++ b/lib-gd32/include/board/logic_analyzer.h @@ -2,7 +2,7 @@ * @file logic_analyzer.h * */ -/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,60 +26,31 @@ #ifndef BOARD_LOGIC_ANALYZER_H_ #define BOARD_LOGIC_ANALYZER_H_ -#if defined (BOARD_GD32F207C_EVAL) -# define LOGIC_ANALYZER_CH0_GPIO_PINx GPIO_PIN_0 -# define LOGIC_ANALYZER_CH1_GPIO_PINx GPIO_PIN_1 -# define LOGIC_ANALYZER_CH2_GPIO_PINx GPIO_PIN_7 -//#define LOGIC_ANALYZER_CH3_GPIO_PINx -//#define LOGIC_ANALYZER_CH4_GPIO_PINx -//#define LOGIC_ANALYZER_CH5_GPIO_PINx -//#define LOGIC_ANALYZER_CH6_GPIO_PINx -//#define LOGIC_ANALYZER_CH7_GPIO_PINx - -# define LOGIC_ANALYZER_CH0_GPIOx GPIOE -# define LOGIC_ANALYZER_CH1_GPIOx GPIOE -# define LOGIC_ANALYZER_CH2_GPIOx GPIOD -# define LOGIC_ANALYZER_CH3_GPIOx -# define LOGIC_ANALYZER_CH4_GPIOx -# define LOGIC_ANALYZER_CH5_GPIOx -# define LOGIC_ANALYZER_CH6_GPIOx -# define LOGIC_ANALYZER_CH7_GPIOx - -# define LOGIC_ANALYZER_CH0_RCU_GPIOx RCU_GPIOE -# define LOGIC_ANALYZER_CH1_RCU_GPIOx RCU_GPIOE -# define LOGIC_ANALYZER_CH2_RCU_GPIOx RCU_GPIOD -# define LOGIC_ANALYZER_CH3_RCU_GPIOx -# define LOGIC_ANALYZER_CH4_RCU_GPIOx -# define LOGIC_ANALYZER_CH5_RCU_GPIOx -# define LOGIC_ANALYZER_CH6_RCU_GPIOx -# define LOGIC_ANALYZER_CH7_RCU_GPIOx -#else -# define LOGIC_ANALYZER_CH0_GPIO_PINx GPIO_PIN_8 // PC8 -# define LOGIC_ANALYZER_CH1_GPIO_PINx GPIO_PIN_9 // PC9 -# define LOGIC_ANALYZER_CH2_GPIO_PINx GPIO_PIN_13 // PC13 -# define LOGIC_ANALYZER_CH3_GPIO_PINx GPIO_PIN_4 // PA4 -# define LOGIC_ANALYZER_CH4_GPIO_PINx GPIO_PIN_5 // PA5 -# define LOGIC_ANALYZER_CH5_GPIO_PINx GPIO_PIN_13 // PA13 -//# define LOGIC_ANALYZER_CH6_GPIO_PINx GPIO_PIN_ -//# define LOGIC_ANALYZER_CH7_GPIO_PINx GPIO_PIN_ - -# define LOGIC_ANALYZER_CH0_GPIOx GPIOC -# define LOGIC_ANALYZER_CH1_GPIOx GPIOC -# define LOGIC_ANALYZER_CH2_GPIOx GPIOC -# define LOGIC_ANALYZER_CH3_GPIOx GPIOA -# define LOGIC_ANALYZER_CH4_GPIOx GPIOA -# define LOGIC_ANALYZER_CH5_GPIOx GPIOA -# define LOGIC_ANALYZER_CH6_GPIOx GPIO -# define LOGIC_ANALYZER_CH7_GPIOx GPIO - -# define LOGIC_ANALYZER_CH0_RCU_GPIOx RCU_GPIOC -# define LOGIC_ANALYZER_CH1_RCU_GPIOx RCU_GPIOC -# define LOGIC_ANALYZER_CH2_RCU_GPIOx RCU_GPIOC -# define LOGIC_ANALYZER_CH3_RCU_GPIOx RCU_GPIOA -# define LOGIC_ANALYZER_CH4_RCU_GPIOx RCU_GPIOA -# define LOGIC_ANALYZER_CH5_RCU_GPIOx RCU_GPIOA -# define LOGIC_ANALYZER_CH6_RCU_GPIOx RCU_GPIO -# define LOGIC_ANALYZER_CH7_RCU_GPIOx RCU_GPIO -#endif +#define LOGIC_ANALYZER_CH0_GPIO_PINx GPIO_PIN_3 +#define LOGIC_ANALYZER_CH1_GPIO_PINx GPIO_PIN_4 +#define LOGIC_ANALYZER_CH2_GPIO_PINx GPIO_PIN_5 +#define LOGIC_ANALYZER_CH3_GPIO_PINx GPIO_PIN_8 +#define LOGIC_ANALYZER_CH4_GPIO_PINx GPIO_PIN_9 +#define LOGIC_ANALYZER_CH5_GPIO_PINx GPIO_PIN_13 +#define LOGIC_ANALYZER_CH6_GPIO_PINx GPIO_PIN_11 +#define LOGIC_ANALYZER_CH7_GPIO_PINx GPIO_PIN_15 + +#define LOGIC_ANALYZER_CH0_GPIOx GPIOB +#define LOGIC_ANALYZER_CH1_GPIOx GPIOB +#define LOGIC_ANALYZER_CH2_GPIOx GPIOB +#define LOGIC_ANALYZER_CH3_GPIOx GPIOC +#define LOGIC_ANALYZER_CH4_GPIOx GPIOC +#define LOGIC_ANALYZER_CH5_GPIOx GPIOC +#define LOGIC_ANALYZER_CH6_GPIOx GPIOA +#define LOGIC_ANALYZER_CH7_GPIOx GPIOA + +#define LOGIC_ANALYZER_CH0_RCU_GPIOx RCU_GPIOB +#define LOGIC_ANALYZER_CH1_RCU_GPIOx RCU_GPIOB +#define LOGIC_ANALYZER_CH2_RCU_GPIOx RCU_GPIOB +#define LOGIC_ANALYZER_CH3_RCU_GPIOx RCU_GPIOC +#define LOGIC_ANALYZER_CH4_RCU_GPIOx RCU_GPIOC +#define LOGIC_ANALYZER_CH5_RCU_GPIOx RCU_GPIOC +#define LOGIC_ANALYZER_CH6_RCU_GPIOx RCU_GPIOA +#define LOGIC_ANALYZER_CH7_RCU_GPIOx RCU_GPIOA #endif /* BOARD_LOGIC_ANALYZER_H_ */ diff --git a/lib-gd32/include/gd32.h b/lib-gd32/include/gd32.h index b13f5dc1..c138dad6 100644 --- a/lib-gd32/include/gd32.h +++ b/lib-gd32/include/gd32.h @@ -2,7 +2,7 @@ * @file gd32.h * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,17 +26,22 @@ #ifndef GD32_H_ #define GD32_H_ -#include +# include -#if !defined __cplusplus - void udelay(uint32_t us); -#else -# if !defined(GD32_UDELAY) -# define GD32_UDELAY +#ifdef __cplusplus +# if !defined(UDELAY) +# define UDELAY void udelay(uint32_t us, uint32_t offset = 0); # endif #endif +struct HwTimersSeconds { +#if !defined (CONFIG_ENET_ENABLE_PTP) + volatile uint32_t nTimeval; +#endif + volatile uint32_t nUptime; +}; + /* * Needed for GD32 Firmware and CMSIS */ @@ -45,25 +50,23 @@ #ifdef __cplusplus # pragma GCC diagnostic ignored "-Wold-style-cast" # pragma GCC diagnostic ignored "-Wuseless-cast" +# if __cplusplus > 201402 +// error: compound assignment with 'volatile'-qualified left operand is deprecated +# pragma GCC diagnostic ignored "-Wvolatile" +# endif extern "C" { #endif -#if defined (GD32F10X_HD) || defined (GD32F10X_CL) -# define GD32F10X +#if defined (GD32F10X_HD) || defined (GD32F10X_CL) # include "gd32f10x.h" -# include "gd32f10x_libopt.h" #elif defined (GD32F20X_CL) -# define GD32F20X # include "gd32f20x.h" -# include "gd32f20x_libopt.h" #elif defined (GD32F30X_HD) -# define GD32F30X # include "gd32f30x.h" -# include "gd32f30x_libopt.h" -#elif defined (GD32F407) || defined (GD32F450) -# define GD32F4XX +#elif defined (GD32F407) || defined (GD32F450) || defined (GD32F470) # include "gd32f4xx.h" -# include "gd32f4xx_libopt.h" +#elif defined (GD32H759) +# include "gd32h7xx.h" #else # error MCU is not supported #endif @@ -77,7 +80,7 @@ extern "C" { # define bkp_data_read bkp_read_data #endif -#if defined(GD32F4XX) && defined(__cplusplus) +#if (defined(GD32F4XX) || defined (GD32H7XX)) && defined(__cplusplus) typedef enum { BKP_DATA_0, @@ -87,6 +90,34 @@ void bkp_data_write(bkp_data_register_enum register_number, uint16_t data); uint16_t bkp_data_read(bkp_data_register_enum register_number); #endif +#if !(defined (GD32F4XX) || defined (GD32H7XX)) +#define GPIO_INIT +#endif + +#if defined (GD32H7XX) +# define GPIO_OSPEED GPIO_OSPEED_60MHZ +#else +# define GPIO_OSPEED GPIO_OSPEED_50MHZ +#endif + +#define GD32_PORT_TO_GPIO(p,n) ((p * 16) + n) +#define GD32_GPIO_TO_PORT(g) (uint8_t)(g / 16) +#define GD32_GPIO_TO_NUMBER(g) (uint8_t)(g - (16 * GD32_GPIO_TO_PORT(g))) + +typedef enum T_GD32_Port { + GD32_GPIO_PORTA = 0, + GD32_GPIO_PORTB, + GD32_GPIO_PORTC, + GD32_GPIO_PORTD, + GD32_GPIO_PORTE, + GD32_GPIO_PORTF, + GD32_GPIO_PORTG, + GD32_GPIO_PORTH, + GD32_GPIO_PORTI, + GD32_GPIO_PORTJ, + GD32_GPIO_PORTK +} GD32_Port_TypeDef; + #include "gd32_board.h" #endif /* GD32_H_ */ diff --git a/lib-gd32/include/gd32_adc.h b/lib-gd32/include/gd32_adc.h index d637dc6f..fc66537d 100644 --- a/lib-gd32/include/gd32_adc.h +++ b/lib-gd32/include/gd32_adc.h @@ -26,10 +26,10 @@ #ifndef GD32_ADC_H_ #define GD32_ADC_H_ -float gd32_adc_gettemp(void); -float gd32_adc_getvref(void); +float gd32_adc_gettemp(); +float gd32_adc_getvref(); #if defined (GD32F4XX) -float gd32_adc_getvbat(void); +float gd32_adc_getvbat(); #endif #ifdef __cplusplus diff --git a/lib-gd32/include/gd32_board.h b/lib-gd32/include/gd32_board.h index bb1ec557..f07b59ef 100644 --- a/lib-gd32/include/gd32_board.h +++ b/lib-gd32/include/gd32_board.h @@ -2,7 +2,7 @@ * @file gd32_board.h * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -46,8 +46,14 @@ # include "board/gd32f450vi.h" #elif defined (BOARD_16X4U_PIXEL) # include "board/16x4u-pixel.h" +#elif defined (BOARD_GD32F470VG) +# include "board/gd32f470vg.h" #elif defined (BOARD_GD32F207C_EVAL) # include "board/gd32f207c_eval.h" +#elif defined (BOARD_GD32F470Z_EVAL) +# include "board/gd32f470z_eval.h" +#elif defined (BOARD_GD32H759I_EVAL) +# include "board/gd32h759i_eval.h" #elif defined (BOARD_BW_OPIDMX4) # include "board/bw_opidmx4.h" #elif defined (BOARD_DMX3) @@ -64,4 +70,22 @@ # error Configuration error #endif +#if defined (GD32H7XX) +# ifdef USE_ENET0 +# define ENETx ENET0 +# define RCU_ENET RCU_ENET0 +# define RCU_ENETTX RCU_ENET0TX +# define RCU_ENETRX RCU_ENET0RX +# elif USE_ENET1 +# define ENETx ENET1 +# define RCU_ENET RCU_ENET1 +# define RCU_ENETTX RCU_ENET1TX +# define RCU_ENETRX RCU_ENET1RX +# else +# error +# endif +#else +# define ENETx +#endif + #endif /* GD32_BOARD_H_ */ diff --git a/lib-gd32/include/gd32_dma.h b/lib-gd32/include/gd32_dma.h new file mode 100644 index 00000000..fbad893f --- /dev/null +++ b/lib-gd32/include/gd32_dma.h @@ -0,0 +1,225 @@ +/** + * @file gd32_dma.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef GD32_DMA_H_ +#define GD32_DMA_H_ + +#include +#include + +#include "gd32.h" + +#if defined (GD32F4XX) || defined (GD32H7XX) +# define DMA_PARAMETER_STRUCT dma_single_data_parameter_struct +# define DMA_CHMADDR DMA_CHM0ADDR +# define DMA_MEMORY_TO_PERIPHERAL DMA_MEMORY_TO_PERIPH +# define DMA_PERIPHERAL_WIDTH_8BIT DMA_PERIPH_WIDTH_8BIT +# define dma_init dma_single_data_mode_init +# define dma_memory_to_memory_disable(x,y) +#else +# define DMA_PARAMETER_STRUCT dma_parameter_struct +#endif + +#if defined (GD32F10X) || defined (GD32F30X) +template +bool gd32_dma_interrupt_flag_get() { + uint32_t interrupt_enable = 0, interrupt_flag = 0; + + switch (flag) { + case DMA_INT_FLAG_FTF: + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; + break; + case DMA_INT_FLAG_HTF: + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; + break; + case DMA_INT_FLAG_ERR: + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE; + break; + default: + assert(0); + } + + return interrupt_flag && interrupt_enable; +} +#elif defined (GD32F20X) +template +bool gd32_dma_interrupt_flag_get() { + uint32_t interrupt_enable = 0U, interrupt_flag = 0U; + uint32_t gif_check = 0x0FU, gif_enable = 0x0EU; + + switch (flag) { + case DMA_INT_FLAG_FTF: + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_flag = interrupt_flag >> ((channelx) * 4U); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; + break; + case DMA_INT_FLAG_HTF: + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_flag = interrupt_flag >> ((channelx) * 4U); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; + break; + case DMA_INT_FLAG_ERR: + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_flag = interrupt_flag >> ((channelx) * 4U); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE; + break; + case DMA_INT_FLAG_G: + interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(gif_check, channelx); + interrupt_flag = interrupt_flag >> ((channelx) * 4U); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & gif_enable; + break; + default: + assert(0); + } + + return (interrupt_flag && interrupt_enable); +} +#elif defined (GD32F4XX) || defined (GD32H7XX) +template +bool gd32_dma_interrupt_flag_get() { + uint32_t interrupt_enable = 0U, interrupt_flag = 0U; + + if constexpr (channelx < DMA_CH4) { + switch (flag) { + case DMA_INTF_FEEIF: + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE; + break; + case DMA_INTF_SDEIF: + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_SDEIE; + break; + case DMA_INTF_TAEIF: + interrupt_flag = DMA_INTF0( dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_TAEIE; + break; + case DMA_INTF_HTFIF: + interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; + break; + case DMA_INTF_FTFIF: + interrupt_flag = (DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag, channelx)); + interrupt_enable = (DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE); + break; + default: + assert(0); + break; + } + } else if constexpr (channelx <= DMA_CH7) { + constexpr uint32_t channel_flag_offset = static_cast(channelx) - 4; + switch (flag) { + case DMA_INTF_FEEIF: + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag, channel_flag_offset); + interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE; + break; + case DMA_INTF_SDEIF: + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag, channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_SDEIE; + break; + case DMA_INTF_TAEIF: + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag, channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_TAEIE; + break; + case DMA_INTF_HTFIF: + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag, channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; + break; + case DMA_INTF_FTFIF: + interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag, channel_flag_offset); + interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; + break; + default: + assert(0); + break; + } + } else { + assert(0); + } + + return (interrupt_flag && interrupt_enable); +} +#else +# error +#endif + +#if defined (GD32F10X) || defined (GD32F30X) || defined (GD32F20X) +template +void gd32_dma_interrupt_flag_clear() { + DMA_INTC(peripheral) |= DMA_FLAG_ADD(nFlag, channel); +} +#elif defined (GD32F4XX) || defined (GD32H7XX) +template +inline void gd32_dma_interrupt_flag_clear() { + if constexpr (channel < DMA_CH4) { + DMA_INTC0(peripheral) |= DMA_FLAG_ADD(nFlag, channel); + } else { + DMA_INTC1(peripheral) |= DMA_FLAG_ADD(nFlag, static_cast(channel) - 4U); + } +} +#else +# error +#endif + +#if defined (GD32F10X) || defined (GD32F30X) +template +void gd32_dma_interrupt_disable() { + if constexpr (DMA1 == peripheral) { + static_assert(channel <= DMA_CH4, "for DMA1, the channel is from DMA_CH0 to DMA_CH4"); + } + + DMA_CHCTL(peripheral, channel) &= static_cast(~nSource); +} +#elif defined (GD32F20X) +template +void gd32_dma_interrupt_disable() { + DMA_CHCTL(peripheral, channel) &= static_cast(~nSource); +} +#elif defined (GD32F4XX) +template +void gd32_dma_interrupt_disable() { + if constexpr (DMA_CHXFCTL_FEEIE != nSource) { + DMA_CHCTL(peripheral, channel) &= static_cast(~nSource); + } else { + DMA_CHFCTL(peripheral, channel) &= static_cast(~nSource); + } +} +#elif defined (GD32H7XX) +template +void gd32_dma_interrupt_disable() { + if constexpr (DMA_CHXFCTL_FEEIE != (DMA_CHXFCTL_FEEIE & nSource)) { + DMA_CHCTL(peripheral, channel) &= static_cast(~nSource); + } else { + DMA_CHFCTL(peripheral, channel) &= static_cast(~DMA_CHXFCTL_FEEIE); + DMA_CHCTL(peripheral, channel) &= static_cast(~(nSource & (~DMA_CHXFCTL_FEEIE))); + } +} +#else +# error +#endif + +#endif /* GD32_DMA_H_ */ diff --git a/lib-gd32/include/gd32_dma_memcpy32.h b/lib-gd32/include/gd32_dma_memcpy32.h new file mode 100644 index 00000000..c7936c14 --- /dev/null +++ b/lib-gd32/include/gd32_dma_memcpy32.h @@ -0,0 +1,56 @@ +/* + * gd32_dma_memcpy32.h + */ + +#ifndef GD32_DMA_MEMCPY32_H_ +#define GD32_DMA_MEMCPY32_H_ + +#include +#include + +#include "gd32.h" + +namespace dma { +void memcpy32_init() ; + +inline void memcpy32(const void *pDestination, const void *pSource, const uint32_t nLength) { + assert((reinterpret_cast(pSource) & 0x3) == 0); + assert((reinterpret_cast(pDestination) & 0x3) == 0); + +#if !defined (GD32F4XX) + uint32_t dmaCHCTL = DMA_CHCTL(DMA0, DMA_CH3); + dmaCHCTL &= ~DMA_CHXCTL_CHEN; + DMA_CHCTL(DMA0, DMA_CH3) = dmaCHCTL; + + DMA_CHPADDR(DMA0, DMA_CH3) = reinterpret_cast(pSource); + DMA_CHMADDR(DMA0, DMA_CH3) = reinterpret_cast(pDestination); + DMA_CHCNT(DMA0, DMA_CH3) = (nLength & DMA_CHXCNT_CNT); + + dmaCHCTL |= DMA_CHXCTL_CHEN; + DMA_CHCTL(DMA0, DMA_CH3) = dmaCHCTL; +#else + uint32_t dmaCHCTL = DMA_CHCTL(DMA1, DMA_CH0); + dmaCHCTL &= ~DMA_CHXCTL_CHEN; + DMA_CHCTL(DMA1, DMA_CH0) = dmaCHCTL; + + DMA_INTC0(DMA1) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, DMA_CH0); + + DMA_CHM0ADDR(DMA1, DMA_CH0) = reinterpret_cast(pDestination); + DMA_CHPADDR(DMA1, DMA_CH0) = reinterpret_cast(pSource); + DMA_CHCNT(DMA1, DMA_CH0) = nLength; + + dmaCHCTL |= DMA_CHXCTL_CHEN; + DMA_CHCTL(DMA1, DMA_CH0) = dmaCHCTL; +#endif +} + +inline bool memcpy32_is_active() { +#if !defined (GD32F4XX) + return DMA_CHCNT(DMA0, DMA_CH3) != 0; +#else + return DMA_CHCNT(DMA1, DMA_CH0) != 0; +#endif +} +} // namespace dma + +#endif /* GD32_DMA_MEMCPY32_H_ */ diff --git a/lib-gd32/include/gd32_gpio.h b/lib-gd32/include/gd32_gpio.h index 7591f93a..71ec42c7 100644 --- a/lib-gd32/include/gd32_gpio.h +++ b/lib-gd32/include/gd32_gpio.h @@ -2,7 +2,7 @@ * @file gd32_gpio.h * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,20 +27,7 @@ #define GD32_GPIO_H_ #include - -#define GD32_PORT_TO_GPIO(p,n) ((p * 16) + n) -#define GD32_GPIO_TO_PORT(g) (uint8_t)(g / 16) -#define GD32_GPIO_TO_NUMBER(g) (uint8_t)(g - (16 * GD32_GPIO_TO_PORT(g))) - -typedef enum T_GD32_Port { - GD32_GPIO_PORTA = 0, - GD32_GPIO_PORTB, - GD32_GPIO_PORTC, - GD32_GPIO_PORTD, - GD32_GPIO_PORTE, - GD32_GPIO_PORTF, - GD32_GPIO_PORTG, -} GD32_Port_TypeDef; +#include #include "gd32.h" @@ -52,7 +39,7 @@ typedef enum T_GD32_Port { # define GPIO_PULL_DISABLE GPIO_MODE_IN_FLOATING # define GPIO_INT_CFG_NEG_EDGE EXTI_TRIG_FALLING # define GPIO_INT_CFG_BOTH EXTI_TRIG_BOTH -#elif defined (GD32F407) || defined (GD32F450) +#elif defined (GD32F407) || defined (GD32F450) || defined (GD32F470) || defined (GD32F470) || defined (GD32H759) # define GPIO_FSEL_OUTPUT GPIO_MODE_OUTPUT # define GPIO_FSEL_INPUT GPIO_MODE_INPUT # define GPIO_PULL_UP GPIO_PUPD_PULLUP @@ -60,7 +47,8 @@ typedef enum T_GD32_Port { # define GPIO_PULL_DISABLE GPIO_PUPD_NONE #endif -inline static void gpio_fsel(const uint32_t gpio_periph, const uint32_t pin, const uint32_t fsel) { +#ifdef __cplusplus +inline void gpio_fsel(const uint32_t gpio_periph, const uint32_t pin, const uint32_t fsel) { switch (gpio_periph) { case GPIOA: rcu_periph_clock_enable(RCU_GPIOA); @@ -80,11 +68,32 @@ inline static void gpio_fsel(const uint32_t gpio_periph, const uint32_t pin, con case GPIOF: rcu_periph_clock_enable(RCU_GPIOF); break; + case GPIOG: + rcu_periph_clock_enable(RCU_GPIOG); + break; +#if !(defined (GD32F10X) || defined (GD32F30X)) + case GPIOH: + rcu_periph_clock_enable(RCU_GPIOH); + break; +# if !defined (GD32H7XX) + case GPIOI: + rcu_periph_clock_enable(RCU_GPIOI); + break; +# endif +#endif +#if defined (GD32H7XX) + case GPIOJ: + rcu_periph_clock_enable(RCU_GPIOJ); + break; + case GPIOK: + rcu_periph_clock_enable(RCU_GPIOK); + break; +#endif default: break; } -#if defined (GD32F10X) || defined (GD32F20X) || defined (GD32F30X) +#if defined (GD32F10X) || defined (GD32F20X) || defined (GD32F30X) if (gpio_periph == GPIOA) { if ((pin == GPIO_PIN_13) || (pin == GPIO_PIN_14)) { rcu_periph_clock_enable(RCU_AF); @@ -93,10 +102,10 @@ inline static void gpio_fsel(const uint32_t gpio_periph, const uint32_t pin, con } gpio_init(gpio_periph, fsel, GPIO_OSPEED_50MHZ, pin); -#elif defined (GD32F4XX) +#elif defined (GD32F4XX) || defined (GD32H7XX) if (fsel == GPIO_FSEL_OUTPUT) { gpio_mode_set(gpio_periph, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, pin); - gpio_output_options_set(gpio_periph, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, pin); + gpio_output_options_set(gpio_periph, GPIO_OTYPE_PP, GPIO_OSPEED, pin); } else { gpio_mode_set(gpio_periph, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, pin); } @@ -105,31 +114,8 @@ inline static void gpio_fsel(const uint32_t gpio_periph, const uint32_t pin, con #endif } -inline static void gd32_gpio_fsel(const uint32_t gpio, const uint32_t fsel) { - const uint32_t gpio_periph = GPIOA + (GD32_GPIO_TO_PORT(gpio) * 0x400); - const uint32_t pin = BIT(GD32_GPIO_TO_NUMBER(gpio)); - - gpio_fsel(gpio_periph, pin, fsel); -} - -inline static void gd32_gpio_pud(const uint32_t gpio, const uint32_t pud) { - const uint32_t gpio_periph = GPIOA + (GD32_GPIO_TO_PORT(gpio) * 0x400); - const uint32_t pin = BIT(GD32_GPIO_TO_NUMBER(gpio)); - -#if defined (GD32F10X) || defined (GD32F20X) || defined (GD32F30X) - gpio_init(gpio_periph, pud, GPIO_OSPEED_50MHZ, pin); -#elif defined (GD32F4XX) - if (pud == GPIO_PULL_UP) { - gpio_mode_set(gpio_periph, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, pin); - } else if (pud == GPIO_PULL_DOWN) { - gpio_mode_set(gpio_periph, GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN, pin); - } else { - gpio_mode_set(gpio_periph, GPIO_MODE_INPUT, GPIO_PUPD_NONE, pin); - } -#endif -} - -inline static void gd32_gpio_int_cfg(const uint32_t gpio, const uint32_t trig_type) { +#if !defined (GD32H7XX) +inline void gd32_gpio_int_cfg(const uint32_t gpio, const uint32_t trig_type) { const uint32_t linex = BIT(GD32_GPIO_TO_NUMBER(gpio)); switch(trig_type){ @@ -158,22 +144,66 @@ inline static void gd32_gpio_int_cfg(const uint32_t gpio, const uint32_t trig_ty syscfg_exti_line_config(output_port, output_pin); #endif } +#endif -inline static void gd32_gpio_clr(const uint32_t gpio) { - const uint32_t gpio_periph = GPIOA + (GD32_GPIO_TO_PORT(gpio) * 0x400); +inline uint32_t gd32_gpio_to_periph(const uint32_t gpio) { + switch ((GD32_Port_TypeDef) GD32_GPIO_TO_PORT(gpio)) { + case GD32_GPIO_PORTA: + case GD32_GPIO_PORTB: + case GD32_GPIO_PORTC: + case GD32_GPIO_PORTD: + case GD32_GPIO_PORTE: + case GD32_GPIO_PORTF: + case GD32_GPIO_PORTG: + return GPIOA + (GD32_GPIO_TO_PORT(gpio) * 0x400); + break; +#if !(defined (GD32F10X) || defined (GD32F30X)) + case GD32_GPIO_PORTH: + return GPIOH; + break; +# if !defined (GD32H7XX) + case GD32_GPIO_PORTI: + return GPIOI; + break; +# endif +#endif +#if defined (GD32H7XX) + case GD32_GPIO_PORTJ: + return GPIOJ; + break; + case GD32_GPIO_PORTK: + return GPIOK; + break; +#endif + default: + assert(0); + return 0; + break; + } +} + +inline void gd32_gpio_fsel(const uint32_t gpio, const uint32_t fsel) { + const uint32_t gpio_periph = gd32_gpio_to_periph(gpio); const uint32_t pin = BIT(GD32_GPIO_TO_NUMBER(gpio)); - GPIO_BC(gpio_periph) = (uint32_t) pin; + gpio_fsel(gpio_periph, pin, fsel); } -inline static void gd32_gpio_set(const uint32_t gpio) { - const uint32_t gpio_periph = GPIOA + (GD32_GPIO_TO_PORT(gpio) * 0x400); +inline void gd32_gpio_clr(const uint32_t gpio) { + const uint32_t gpio_periph = gd32_gpio_to_periph(gpio); const uint32_t pin = BIT(GD32_GPIO_TO_NUMBER(gpio)); - GPIO_BOP(gpio_periph) = (uint32_t) pin; + GPIO_BC(gpio_periph) = pin; } -inline static void gd32_gpio_write(const uint32_t gpio, const uint32_t level) { +inline void gd32_gpio_set(const uint32_t gpio) { + const uint32_t gpio_periph = gd32_gpio_to_periph(gpio); + const uint32_t pin = BIT(GD32_GPIO_TO_NUMBER(gpio)); + + GPIO_BOP(gpio_periph) = pin; +} + +inline void gd32_gpio_write(const uint32_t gpio, const uint32_t level) { if (level == 0) { gd32_gpio_clr(gpio); } else { @@ -181,10 +211,135 @@ inline static void gd32_gpio_write(const uint32_t gpio, const uint32_t level) { } } -inline static uint32_t gd32_gpio_lev(const uint32_t gpio) { - const uint32_t gpio_periph = GPIOA + (GD32_GPIO_TO_PORT(gpio) * 0x400); +inline uint32_t gd32_gpio_lev(const uint32_t gpio) { + const uint32_t gpio_periph = gd32_gpio_to_periph(gpio); const uint32_t pin = BIT(GD32_GPIO_TO_NUMBER(gpio)); - return (uint32_t) ((uint32_t) 0 != (GPIO_ISTAT(gpio_periph) & pin)); + + return (uint32_t)(0 != (GPIO_ISTAT(gpio_periph) & pin)); } +inline void gd32_gpio_set_pud(const uint32_t gpio, const uint32_t pud) { + const uint32_t gpio_periph = gd32_gpio_to_periph(gpio); + const uint32_t pin = BIT(GD32_GPIO_TO_NUMBER(gpio)); + +#if defined (GD32F10X) || defined (GD32F20X) || defined (GD32F30X) + gpio_init(gpio_periph, pud, GPIO_OSPEED_50MHZ, pin); +#elif defined (GD32F4XX) || defined (GD32H7XX) + if (pud == GPIO_PULL_UP) { + gpio_mode_set(gpio_periph, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, pin); + } else if (pud == GPIO_PULL_DOWN) { + gpio_mode_set(gpio_periph, GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN, pin); + } else { + gpio_mode_set(gpio_periph, GPIO_MODE_INPUT, GPIO_PUPD_NONE, pin); + } +#endif +} + +#if defined (GD32F4XX) || defined (GD32H7XX) +template +inline void gd32_gpio_mode_set() { + static_assert(pin != 0, "pin cannot be zero"); + static_assert(pin == (1U << __builtin_ctz(pin)), "Only single pin values are allowed"); + + uint32_t ctl = GPIO_CTL(gpio_periph); + uint32_t pupd = GPIO_PUD(gpio_periph); + + constexpr auto i = 31U - __builtin_clz(pin); + + /* clear the specified pin mode bits */ + ctl &= ~GPIO_MODE_MASK(i); + /* set the specified pin mode bits */ + ctl |= GPIO_MODE_SET(i, mode); + + /* clear the specified pin pupd bits */ + pupd &= ~GPIO_PUPD_MASK(i); + /* set the specified pin pupd bits */ + pupd |= GPIO_PUPD_SET(i, pull_up_down); + + GPIO_CTL(gpio_periph) = ctl; + GPIO_PUD(gpio_periph) = pupd; +} + +template +inline void gd32_gpio_af_set() { + static_assert(pin != 0, "pin cannot be zero"); + static_assert(pin == (1U << __builtin_ctz(pin)), "Only single pin values are allowed"); + + constexpr uint32_t i = 31U - __builtin_clz(pin); + + auto afrl = GPIO_AFSEL0(gpio_periph); + auto afrh = GPIO_AFSEL1(gpio_periph); + + if constexpr(i < 8U) { + /* clear the specified pin alternate function bits */ + afrl &= ~GPIO_AFR_MASK(i); + afrl |= GPIO_AFR_SET(i, alt_func_num); + } else if constexpr(i < 16U) { + /* clear the specified pin alternate function bits */ + afrh &= ~GPIO_AFR_MASK(i - 8U); + afrh |= GPIO_AFR_SET(i - 8U, alt_func_num); + } + + GPIO_AFSEL0(gpio_periph) = afrl; + GPIO_AFSEL1(gpio_periph) = afrh; +} +#else +template +inline void gd32_gpio_init() { + /* GPIO mode configuration */ + auto temp_mode = (mode & 0x0F); + + /* GPIO speed configuration */ + if constexpr ((0x00U) != (mode & (0x10U))) { + /* output mode max speed: 10MHz, 2MHz, 50MHz */ + temp_mode |= speed; + } + + constexpr uint32_t pin_pos = 31U - __builtin_clz(pin); + + if constexpr (pin_pos < 8U) { + uint32_t reg = GPIO_CTL0(gpio_periph); + /* clear the specified pin mode bits */ + reg &= ~GPIO_MODE_MASK(pin_pos); + /* set the specified pin mode bits */ + reg |= GPIO_MODE_SET(pin_pos, temp_mode); + + /* set IPD or IPU */ + if constexpr (GPIO_MODE_IPD == mode) { + /* reset the corresponding OCTL bit */ + GPIO_BC(gpio_periph) = (1U << pin_pos); + } else { + /* set the corresponding OCTL bit */ + if constexpr (GPIO_MODE_IPU == mode) { + GPIO_BOP(gpio_periph) = (1U << pin_pos); + } + } + /* set GPIO_CTL0 register */ + GPIO_CTL0(gpio_periph) = reg; + } else { + /* configure the eight high port pins with GPIO_CTL1 */ + constexpr uint32_t high_pin_pos = pin_pos - 8U; + uint32_t reg = GPIO_CTL1(gpio_periph); + /* clear the specified pin mode bits */ + reg &= ~GPIO_MODE_MASK(high_pin_pos); + /* set the specified pin mode bits */ + reg |= GPIO_MODE_SET(high_pin_pos, temp_mode); + + /* set IPD or IPU */ + if constexpr (GPIO_MODE_IPD == mode) { + /* reset the corresponding OCTL bit */ + GPIO_BC(gpio_periph) = (1U << pin_pos); + } else { + /* set the corresponding OCTL bit */ + if (GPIO_MODE_IPU == mode) { + GPIO_BOP(gpio_periph) = (1U << pin_pos); + } + } + /* set GPIO_CTL1 register */ + GPIO_CTL1(gpio_periph) = reg; + } +} +#endif +#endif + #endif /* GD32_GPIO_H_ */ diff --git a/lib-gd32/include/gd32_ptp.h b/lib-gd32/include/gd32_ptp.h new file mode 100644 index 00000000..c1eb623e --- /dev/null +++ b/lib-gd32/include/gd32_ptp.h @@ -0,0 +1,98 @@ +/** + * @file gd32_ptp.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef GD32_PTP_H_ +#define GD32_PTP_H_ + +#include + +#include "gd32.h" + +namespace gd32 { +namespace ptp { +#if !defined(MCU_CLOCK_FREQ) +# error MCU_CLOCK_FREQ is not defined +#endif +#if !defined(PTP_ACCARACY_NS) + static constexpr uint8_t PTP_TICK = 20; +#else + static constexpr uint8_t PTP_TICK = PTP_ACCARACY_NS; +#endif +static constexpr uint8_t ADJ_FREQ_BASE_INCREMENT = static_cast((PTP_TICK * static_cast(1ULL << 31) / 1E9) + 0.5f); +static constexpr uint32_t ADJ_FREQ_BASE_ADDEND = (static_cast(1ULL << 63) / AHB_CLOCK_FREQ) / ADJ_FREQ_BASE_INCREMENT; +static constexpr int32_t ADJ_FREQ_MAX = 5120000; + +struct time_t { + int32_t tv_sec; + int32_t tv_nsec; +}; + +struct ptptime { + uint32_t tv_sec; + uint32_t tv_nsec; +}; +} // namespace ptp + +inline uint32_t ptp_nanosecond_2_subsecond(const uint32_t nanosecond) { + uint64_t val = nanosecond * 0x80000000Ull; + val /= 1000000000U; + return static_cast(val); +} + +inline uint32_t ptp_subsecond_2_nanosecond(const uint32_t subsecond) { + uint64_t val = subsecond * 1000000000Ull; + val >>= 31U; + return (uint32_t) val; +} + +inline void normalize_time(ptp::time_t *r) { + r->tv_sec += r->tv_nsec / 1000000000; + r->tv_nsec -= r->tv_nsec / 1000000000 * 1000000000; + + if (r->tv_sec > 0 && r->tv_nsec < 0) { + r->tv_sec -= 1; + r->tv_nsec += 1000000000; + } else if (r->tv_sec < 0 && r->tv_nsec > 0) { + r->tv_sec += 1; + r->tv_nsec -= 1000000000; + } +} + +inline void sub_time(struct ptp::time_t *r, const struct ptp::time_t *x, const struct ptp::time_t *y) { + r->tv_sec = x->tv_sec - y->tv_sec; + r->tv_nsec = x->tv_nsec - y->tv_nsec; + + normalize_time(r); +} + +} // namespace gd32 + +void gd32_ptp_start(); +void gd32_ptp_get_time(gd32::ptp::ptptime *ptp_time); +void gd32_ptp_set_time(const gd32::ptp::ptptime *ptp_time); +void gd32_ptp_update_time(const gd32::ptp::time_t *ptp_time); +bool gd32_adj_frequency(const int32_t adjust_pbb); + +#endif /* GD32_PTP_H_ */ diff --git a/lib-gd32/include/gd32_pwm.h b/lib-gd32/include/gd32_pwm.h new file mode 100644 index 00000000..5e3cf8c8 --- /dev/null +++ b/lib-gd32/include/gd32_pwm.h @@ -0,0 +1,43 @@ +/** + * @file gd32_pwm.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef GD32_PWM_H_ +#define GD32_PWM_H_ + +#include + +namespace pwm { +enum class Channel { + PWM_CHANNEL_0, + PWM_CHANNEL_1, + PWM_CHANNEL_2, + PWM_CHANNEL_3 +}; +} // namespace pwm + +void gd32_pwm_begin(); +void gd32_pwm_set_duty_cycle(const pwm::Channel channel, const uint32_t nDutyCycle); + +#endif /* GD32_PWM_H_ */ diff --git a/lib-gd32/include/gd32_spi.h b/lib-gd32/include/gd32_spi.h index 9b1f8ad5..10d410f0 100644 --- a/lib-gd32/include/gd32_spi.h +++ b/lib-gd32/include/gd32_spi.h @@ -2,7 +2,7 @@ * @file gd32_spi.h * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -62,10 +62,21 @@ void gd32_spi_writenb(const char *pTxBuffer, uint32_t nDataLength); * DMA support */ +const uint8_t *gd32_spi_dma_tx_prepare(uint32_t& nLength); +void gd32_spi_dma_tx_start(const uint8_t *pTxBuffer, uint32_t nLength); +bool gd32_spi_dma_tx_is_active(); + +/** + * SPI DMA implementation using I2S. + * Limitation SPI is that you cannot set the speed exactly. + * Exact speed is needed for pixels (WS2812B, etc). + */ +namespace i2s { void gd32_spi_dma_begin(); -void gd32_spi_dma_set_speed_hz(uint32_t speed_hz); -const uint8_t *gd32_spi_dma_tx_prepare(uint32_t *data_length); -void gd32_spi_dma_tx_start(const uint8_t *tx_buffer, uint32_t length); +void gd32_spi_dma_set_speed_hz(uint32_t nSpeedHz); +const uint8_t *gd32_spi_dma_tx_prepare(uint32_t *pLength); +void gd32_spi_dma_tx_start(const uint8_t *pTxBuffer, uint32_t nLength); bool gd32_spi_dma_tx_is_active(); +} // namespace i2s #endif /* GD32_SPI_H_ */ diff --git a/lib-gd32/include/gd32_uart.h b/lib-gd32/include/gd32_uart.h index 5f3c7595..f562f6c3 100644 --- a/lib-gd32/include/gd32_uart.h +++ b/lib-gd32/include/gd32_uart.h @@ -2,7 +2,7 @@ * @file gd32_uart.h * */ -/* Copyright (C) 2021 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,6 +26,13 @@ #ifndef GD32_UART_H_ #define GD32_UART_H_ +#if !defined (GD32H7XX) +# define USART_TDATA USART_DATA +# define USART_RDATA USART_DATA +# define USART_TDATA_TDATA USART_DATA_DATA +# define USART_RDATA_TDATA USART_DATA_DATA +#endif + typedef enum GD32_UART_BITS { GD32_UART_BITS_8 = 8, GD32_UART_BITS_9 = 9 @@ -42,27 +49,75 @@ typedef enum GD32_UART_STOPBITS { GD32_UART_STOP_2BITS = 2 } gd32_uart_stopbits_t; -#include +#include #include "gd32.h" -#ifdef __cplusplus -extern "C" { -#endif - -extern void gd32_uart_begin(const uint32_t usart_periph, uint32_t baudrate, uint32_t bits, uint32_t parity, uint32_t stop_bits); -extern void gd32_uart_set_baudrate(const uint32_t usart_periph, uint32_t baudrate); -extern void gd32_uart_transmit(const uint32_t usart_periph, const uint8_t *data, uint32_t length); -extern void gd32_uart_transmit_string(const uint32_t uart_base, const char *data); +void gd32_uart_begin(const uint32_t usart_periph, uint32_t baudrate, uint32_t bits, uint32_t parity, uint32_t stop_bits); +void gd32_uart_set_baudrate(const uint32_t usart_periph, uint32_t baudrate); +void gd32_uart_transmit(const uint32_t usart_periph, const uint8_t *data, uint32_t length); +void gd32_uart_transmit_string(const uint32_t usart_periph, const char *data); -static inline uint32_t gd32_uart_get_rx_fifo_level(__attribute__((unused)) const uint32_t usart_periph) { +inline uint32_t gd32_uart_get_rx_fifo_level(__attribute__((unused)) const uint32_t usart_periph) { return 1; } -static inline uint8_t gd32_uart_get_rx_data(const uint32_t uart_base) { - return (uint8_t)(GET_BITS(USART_DATA(uart_base), 0U, 8U)); +inline uint8_t gd32_uart_get_rx_data(const uint32_t usart_periph) { + return static_cast(GET_BITS(USART_RDATA(usart_periph), 0U, 8U)); +} + +template +bool gd32_usart_flag_get(const uint32_t usart_periph) { + return (0 != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))); +} + +template +void gd32_usart_flag_clear(const uint32_t usart_periph) { +#if defined (GD32F10X) || defined (GD32F30X) || defined (GD32F20X) + USART_REG_VAL(usart_periph, flag) = ~BIT(USART_BIT_POS(flag)); +#elif defined (GD32F4XX) + USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag)); +#elif defined (GD32H7XX) + if constexpr (USART_FLAG_AM1 == flag) { + USART_INTC(usart_periph) |= USART_INTC_AMC1; + } else if constexpr (USART_FLAG_EPERR == flag) { + USART_CHC(usart_periph) &= (uint32_t) (~USART_CHC_EPERR); + } else if constexpr (USART_FLAG_TFE == flag) { + USART_FCS(usart_periph) |= USART_FCS_TFEC; + } else { + USART_INTC(usart_periph) |= BIT(USART_BIT_POS(flag)); + } +#else +# error +#endif +} + +template +void gd32_usart_interrupt_enable(const uint32_t usart_periph) { + USART_REG_VAL(usart_periph, interrupt) |= BIT(USART_BIT_POS(interrupt)); } -#ifdef __cplusplus +template +void gd32_usart_interrupt_disable(const uint32_t usart_periph) { + USART_REG_VAL(usart_periph, interrupt) &= ~BIT(USART_BIT_POS(interrupt)); } + +template +void gd32_usart_interrupt_flag_clear(const uint32_t usart_periph) { +#if defined (GD32F10X) || defined (GD32F30X) || defined (GD32F20X) + USART_REG_VAL2(usart_periph, flag) = ~BIT(USART_BIT_POS2(flag)); +#elif defined (GD32F4XX) + USART_REG_VAL2(usart_periph, flag) &= ~BIT(USART_BIT_POS2(flag)); +#elif defined (GD32H7XX) + if constexpr (USART_INT_FLAG_TFE == flag) { + USART_FCS(usart_periph) |= USART_FCS_TFEC; + } else if constexpr (USART_INT_FLAG_RFF == flag) { + USART_FCS(usart_periph) &= (~USART_FCS_RFFIF); + } else { + USART_INTC(usart_periph) |= BIT(USART_BIT_POS2(flag)); + } +#else +# error #endif +} + #endif /* GD32_UART_H_ */ diff --git a/lib-gd32/include/logic_analyzer.h b/lib-gd32/include/logic_analyzer.h index ff116a02..c70ef0b4 100644 --- a/lib-gd32/include/logic_analyzer.h +++ b/lib-gd32/include/logic_analyzer.h @@ -2,7 +2,7 @@ * @file logic_analyzer.h * */ -/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,96 +26,96 @@ #ifndef LOGIC_ANALYZER_H_ #define LOGIC_ANALYZER_H_ +#include "board/logic_analyzer.h" #include "gd32.h" namespace logic_analyzer { - -static void init() { +inline void init() { #if defined (LOGIC_ANALYZER) # if defined (LOGIC_ANALYZER_CH0_GPIO_PINx) rcu_periph_clock_enable(LOGIC_ANALYZER_CH0_RCU_GPIOx); -# if !defined (GD32F4XX) +# if defined (GPIO_INIT) gpio_init(LOGIC_ANALYZER_CH0_GPIOx, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, LOGIC_ANALYZER_CH0_GPIO_PINx); # else gpio_mode_set(LOGIC_ANALYZER_CH0_GPIOx, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LOGIC_ANALYZER_CH0_GPIO_PINx); - gpio_output_options_set(LOGIC_ANALYZER_CH0_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, LOGIC_ANALYZER_CH0_GPIO_PINx); + gpio_output_options_set(LOGIC_ANALYZER_CH0_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, LOGIC_ANALYZER_CH0_GPIO_PINx); # endif GPIO_BC(LOGIC_ANALYZER_CH0_GPIOx) = LOGIC_ANALYZER_CH0_GPIO_PINx; # endif # if defined (LOGIC_ANALYZER_CH1_GPIO_PINx) rcu_periph_clock_enable(LOGIC_ANALYZER_CH1_RCU_GPIOx); -# if !defined (GD32F4XX) +# if defined (GPIO_INIT) gpio_init(LOGIC_ANALYZER_CH1_GPIOx, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, LOGIC_ANALYZER_CH1_GPIO_PINx); # else gpio_mode_set(LOGIC_ANALYZER_CH1_GPIOx, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LOGIC_ANALYZER_CH1_GPIO_PINx); - gpio_output_options_set(LOGIC_ANALYZER_CH1_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, LOGIC_ANALYZER_CH1_GPIO_PINx); + gpio_output_options_set(LOGIC_ANALYZER_CH1_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, LOGIC_ANALYZER_CH1_GPIO_PINx); # endif GPIO_BC(LOGIC_ANALYZER_CH1_GPIOx) = LOGIC_ANALYZER_CH1_GPIO_PINx; # endif # if defined (LOGIC_ANALYZER_CH2_GPIO_PINx) rcu_periph_clock_enable(LOGIC_ANALYZER_CH2_RCU_GPIOx); -# if !defined (GD32F4XX) +# if defined (GPIO_INIT) gpio_init(LOGIC_ANALYZER_CH2_GPIOx, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, LOGIC_ANALYZER_CH2_GPIO_PINx); # else gpio_mode_set(LOGIC_ANALYZER_CH2_GPIOx, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LOGIC_ANALYZER_CH2_GPIO_PINx); - gpio_output_options_set(LOGIC_ANALYZER_CH2_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, LOGIC_ANALYZER_CH2_GPIO_PINx); + gpio_output_options_set(LOGIC_ANALYZER_CH2_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, LOGIC_ANALYZER_CH2_GPIO_PINx); # endif GPIO_BC(LOGIC_ANALYZER_CH2_GPIOx) = LOGIC_ANALYZER_CH2_GPIO_PINx; # endif # if defined (LOGIC_ANALYZER_CH3_GPIO_PINx) rcu_periph_clock_enable(LOGIC_ANALYZER_CH3_RCU_GPIOx); -# if !defined (GD32F4XX) +# if defined (GPIO_INIT) gpio_init(LOGIC_ANALYZER_CH3_GPIOx, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, LOGIC_ANALYZER_CH3_GPIO_PINx); # else gpio_mode_set(LOGIC_ANALYZER_CH3_GPIOx, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LOGIC_ANALYZER_CH3_GPIO_PINx); - gpio_output_options_set(LOGIC_ANALYZER_CH3_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, LOGIC_ANALYZER_CH3_GPIO_PINx); + gpio_output_options_set(LOGIC_ANALYZER_CH3_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, LOGIC_ANALYZER_CH3_GPIO_PINx); # endif GPIO_BC(LOGIC_ANALYZER_CH3_GPIOx) = LOGIC_ANALYZER_CH3_GPIO_PINx; # endif # if defined (LOGIC_ANALYZER_CH4_GPIO_PINx) rcu_periph_clock_enable(LOGIC_ANALYZER_CH4_RCU_GPIOx); -# if !defined (GD32F4XX) +# if defined (GPIO_INIT) gpio_init(LOGIC_ANALYZER_CH4_GPIOx, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, LOGIC_ANALYZER_CH4_GPIO_PINx); # else gpio_mode_set(LOGIC_ANALYZER_CH4_GPIOx, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LOGIC_ANALYZER_CH4_GPIO_PINx); - gpio_output_options_set(LOGIC_ANALYZER_CH4_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, LOGIC_ANALYZER_CH4_GPIO_PINx); + gpio_output_options_set(LOGIC_ANALYZER_CH4_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, LOGIC_ANALYZER_CH4_GPIO_PINx); # endif GPIO_BC(LOGIC_ANALYZER_CH4_GPIOx) = LOGIC_ANALYZER_CH4_GPIO_PINx; # endif # if defined (LOGIC_ANALYZER_CH5_GPIO_PINx) rcu_periph_clock_enable(LOGIC_ANALYZER_CH5_RCU_GPIOx); -# if !defined (GD32F4XX) +# if defined (GPIO_INIT) gpio_init(LOGIC_ANALYZER_CH5_GPIOx, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, LOGIC_ANALYZER_CH5_GPIO_PINx); # else gpio_mode_set(LOGIC_ANALYZER_CH5_GPIOx, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LOGIC_ANALYZER_CH5_GPIO_PINx); - gpio_output_options_set(LOGIC_ANALYZER_CH5_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, LOGIC_ANALYZER_CH5_GPIO_PINx); + gpio_output_options_set(LOGIC_ANALYZER_CH5_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, LOGIC_ANALYZER_CH5_GPIO_PINx); # endif GPIO_BC(LOGIC_ANALYZER_CH5_GPIOx) = LOGIC_ANALYZER_CH5_GPIO_PINx; # endif # if defined (LOGIC_ANALYZER_CH6_GPIO_PINx) rcu_periph_clock_enable(LOGIC_ANALYZER_CH6_RCU_GPIOx); -# if !defined (GD32F4XX) +# if defined (GPIO_INIT) gpio_init(LOGIC_ANALYZER_CH6_GPIOx, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, LOGIC_ANALYZER_CH6_GPIO_PINx); # else gpio_mode_set(LOGIC_ANALYZER_CH6_GPIOx, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LOGIC_ANALYZER_CH6_GPIO_PINx); - gpio_output_options_set(LOGIC_ANALYZER_CH6_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, LOGIC_ANALYZER_CH6_GPIO_PINx); + gpio_output_options_set(LOGIC_ANALYZER_CH6_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, LOGIC_ANALYZER_CH6_GPIO_PINx); # endif GPIO_BC(LOGIC_ANALYZER_CH6_GPIOx) = LOGIC_ANALYZER_CH6_GPIO_PINx; # endif # if defined (LOGIC_ANALYZER_CH7_GPIO_PINx) rcu_periph_clock_enable(LOGIC_ANALYZER_CH7_RCU_GPIOx); -# if !defined (GD32F4XX) +# if defined (GPIO_INIT) gpio_init(LOGIC_ANALYZER_CH7_GPIOx, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, LOGIC_ANALYZER_CH7_GPIO_PINx); # else gpio_mode_set(LOGIC_ANALYZER_CH7_GPIOx, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LOGIC_ANALYZER_CH7_GPIO_PINx); - gpio_output_options_set(LOGIC_ANALYZER_CH7_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, LOGIC_ANALYZER_CH7_GPIO_PINx); + gpio_output_options_set(LOGIC_ANALYZER_CH7_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, LOGIC_ANALYZER_CH7_GPIO_PINx); # endif GPIO_BC(LOGIC_ANALYZER_CH7_GPIOx) = LOGIC_ANALYZER_CH7_GPIO_PINx; # endif @@ -123,103 +123,101 @@ static void init() { #endif } -static void ch0_clear() { -#if defined (LOGIC_ANALYZER_CH0_GPIO_PINx) +inline void ch0_clear() { +#if defined (LOGIC_ANALYZER_CH0_GPIO_PINx) && defined (LOGIC_ANALYZER) GPIO_BC(LOGIC_ANALYZER_CH0_GPIOx) = LOGIC_ANALYZER_CH0_GPIO_PINx; #endif } -static void ch0_set() { -#if defined (LOGIC_ANALYZER_CH0_GPIO_PINx) +inline void ch0_set() { +#if defined (LOGIC_ANALYZER_CH0_GPIO_PINx) && defined (LOGIC_ANALYZER) GPIO_BOP(LOGIC_ANALYZER_CH0_GPIOx) = LOGIC_ANALYZER_CH0_GPIO_PINx; #endif } -static void ch1_clear() { -#if defined (LOGIC_ANALYZER_CH1_GPIO_PINx) +inline void ch1_clear() { +#if defined (LOGIC_ANALYZER_CH1_GPIO_PINx) && defined (LOGIC_ANALYZER) GPIO_BC(LOGIC_ANALYZER_CH1_GPIOx) = LOGIC_ANALYZER_CH1_GPIO_PINx; #endif } -static void ch1_set() { -#if defined (LOGIC_ANALYZER_CH1_GPIO_PINx) +inline void ch1_set() { +#if defined (LOGIC_ANALYZER_CH1_GPIO_PINx) && defined (LOGIC_ANALYZER) GPIO_BOP(LOGIC_ANALYZER_CH1_GPIOx) = LOGIC_ANALYZER_CH1_GPIO_PINx; #endif } -static void ch2_clear() { -#if defined (LOGIC_ANALYZER_CH2_GPIO_PINx) +inline void ch2_clear() { +#if defined (LOGIC_ANALYZER_CH2_GPIO_PINx) && defined (LOGIC_ANALYZER) GPIO_BC(LOGIC_ANALYZER_CH2_GPIOx) = LOGIC_ANALYZER_CH2_GPIO_PINx; #endif } -static void ch2_set() { -#if defined (LOGIC_ANALYZER_CH2_GPIO_PINx) +inline void ch2_set() { +#if defined (LOGIC_ANALYZER_CH2_GPIO_PINx) && defined (LOGIC_ANALYZER) GPIO_BOP(LOGIC_ANALYZER_CH2_GPIOx) = LOGIC_ANALYZER_CH2_GPIO_PINx; #endif } -static void ch3_clear() { -#if defined (LOGIC_ANALYZER_CH3_GPIO_PINx) +inline void ch3_clear() { +#if defined (LOGIC_ANALYZER_CH3_GPIO_PINx) && defined (LOGIC_ANALYZER) GPIO_BC(LOGIC_ANALYZER_CH3_GPIOx) = LOGIC_ANALYZER_CH3_GPIO_PINx; #endif } -static void ch3_set() { -#if defined (LOGIC_ANALYZER_CH3_GPIO_PINx) +inline void ch3_set() { +#if defined (LOGIC_ANALYZER_CH3_GPIO_PINx) && defined (LOGIC_ANALYZER) GPIO_BOP(LOGIC_ANALYZER_CH3_GPIOx) = LOGIC_ANALYZER_CH3_GPIO_PINx; #endif } -// -static void ch4_clear() { -#if defined (LOGIC_ANALYZER_CH4_GPIO_PINx) +inline void ch4_clear() { +#if defined (LOGIC_ANALYZER_CH4_GPIO_PINx) && defined (LOGIC_ANALYZER) GPIO_BC(LOGIC_ANALYZER_CH4_GPIOx) = LOGIC_ANALYZER_CH4_GPIO_PINx; #endif } -static void ch4_set() { -#if defined (LOGIC_ANALYZER_CH4_GPIO_PINx) +inline void ch4_set() { +#if defined (LOGIC_ANALYZER_CH4_GPIO_PINx) && defined (LOGIC_ANALYZER) GPIO_BOP(LOGIC_ANALYZER_CH4_GPIOx) = LOGIC_ANALYZER_CH4_GPIO_PINx; #endif } -static void ch5_clear() { -#if defined (LOGIC_ANALYZER_CH5_GPIO_PINx) +inline void ch5_clear() { +#if defined (LOGIC_ANALYZER_CH5_GPIO_PINx) && defined (LOGIC_ANALYZER) GPIO_BC(LOGIC_ANALYZER_CH5_GPIOx) = LOGIC_ANALYZER_CH5_GPIO_PINx; #endif } -static void ch5_set() { -#if defined (LOGIC_ANALYZER_CH5_GPIO_PINx) +inline void ch5_set() { +#if defined (LOGIC_ANALYZER_CH5_GPIO_PINx) && defined (LOGIC_ANALYZER) GPIO_BOP(LOGIC_ANALYZER_CH5_GPIOx) = LOGIC_ANALYZER_CH5_GPIO_PINx; #endif } -static void ch6_clear() { -#if defined (LOGIC_ANALYZER_CH6_GPIO_PINx) +inline void ch6_clear() { +#if defined (LOGIC_ANALYZER_CH6_GPIO_PINx) && defined (LOGIC_ANALYZER) GPIO_BC(LOGIC_ANALYZER_CH6_GPIOx) = LOGIC_ANALYZER_CH6_GPIO_PINx; #endif } -static void ch6_set() { -#if defined (LOGIC_ANALYZER_CH6_GPIO_PINx) +inline void ch6_set() { +#if defined (LOGIC_ANALYZER_CH6_GPIO_PINx) && defined (LOGIC_ANALYZER) GPIO_BOP(LOGIC_ANALYZER_CH6_GPIOx) = LOGIC_ANALYZER_CH6_GPIO_PINx; #endif } -static void ch7_clear() { -#if defined (LOGIC_ANALYZER_CH7_GPIO_PINx) +inline void ch7_clear() { +#if defined (LOGIC_ANALYZER_CH7_GPIO_PINx) && defined (LOGIC_ANALYZER) GPIO_BC(LOGIC_ANALYZER_CH7_GPIOx) = LOGIC_ANALYZER_CH7_GPIO_PINx; #endif } -static void ch7_set() { -#if defined (LOGIC_ANALYZER_CH7_GPIO_PINx) +inline void ch7_set() { +#if defined (LOGIC_ANALYZER_CH7_GPIO_PINx) && defined (LOGIC_ANALYZER) GPIO_BOP(LOGIC_ANALYZER_CH7_GPIOx) = LOGIC_ANALYZER_CH7_GPIO_PINx; #endif } - } // namespace logic_analyzer #endif /* LOGIC_ANALYZER_H_ */ diff --git a/lib-gd32/include/mcu/gd32f207_mcu.h b/lib-gd32/include/mcu/gd32f207_mcu.h new file mode 100644 index 00000000..ae856918 --- /dev/null +++ b/lib-gd32/include/mcu/gd32f207_mcu.h @@ -0,0 +1,44 @@ +/** + * @file gd32f207_mcu.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MCU_GD32F207_MCU_H_ +#define MCU_GD32F207_MCU_H_ + +#if !defined(GD32F20X_CL) +# error This file should not be included +#endif + +#include + +#define MCU_CLOCK_FREQ (uint32_t)(120000000) +#define AHB_CLOCK_FREQ (uint32_t)(120000000) +#define APB1_CLOCK_FREQ (uint32_t)(60000000) +#define APB2_CLOCK_FREQ (uint32_t)(120000000) +#define TIMER_PSC_1MHZ (uint16_t)(119) +#define TIMER_PSC_10KHZ (uint16_t)(11999) + +#include "gd32f20x_mcu.h" + +#endif /* MCU_GD32F207_MCU_H_ */ diff --git a/lib-gd32/include/mcu/gd32f20x_mcu.h b/lib-gd32/include/mcu/gd32f20x_mcu.h index ce26b135..1ab03b73 100644 --- a/lib-gd32/include/mcu/gd32f20x_mcu.h +++ b/lib-gd32/include/mcu/gd32f20x_mcu.h @@ -2,7 +2,7 @@ * @file gd32f20x_mcu.h * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,14 +32,6 @@ #include -#define MCU_CLOCK_FREQ (uint32_t)(120000000) -#define APB1_CLOCK_FREQ (uint32_t)(60000000) -#define APB2_CLOCK_FREQ (uint32_t)(120000000) -#define TIMER_PSC_1MHZ (uint16_t)(119) -#define TIMER_PSC_10KHZ (uint16_t)(11999) - -#include "gd32f20x_libopt.h" - /** * */ @@ -50,113 +42,113 @@ * U(S)ART */ -#define USART0_RCU_CLK RCU_USART0 +#define USART0_RCU_USART0 RCU_USART0 #if defined (USART0_REMAP) -# define USART0_GPIO_PORT GPIOB -# define USART0_GPIO_CLK RCU_GPIOB -# define USART0_TX_PIN GPIO_PIN_6 -# define USART0_RX_PIN GPIO_PIN_7 +# define USART0_RCU_GPIOx RCU_GPIOB +# define USART0_GPIOx GPIOB +# define USART0_TX_GPIO_PINx GPIO_PIN_6 +# define USART0_RX_GPIO_PINx GPIO_PIN_7 #else -# define USART0_GPIO_PORT GPIOA -# define USART0_GPIO_CLK RCU_GPIOA -# define USART0_TX_PIN GPIO_PIN_9 -# define USART0_RX_PIN GPIO_PIN_10 +# define USART0_RCU_GPIOx RCU_GPIOA +# define USART0_GPIOx GPIOA +# define USART0_TX_GPIO_PINx GPIO_PIN_9 +# define USART0_RX_GPIO_PINx GPIO_PIN_10 #endif -#define USART1_RCU_CLK RCU_USART1 +#define USART1_RCU_USART1 RCU_USART1 #if defined (USART1_REMAP) -# define USART1_GPIO_PORT GPIOD -# define USART1_GPIO_CLK RCU_GPIOD -# define USART1_TX_PIN GPIO_PIN_5 -# define USART1_RX_PIN GPIO_PIN_6 +# define USART1_RCU_GPIOx RCU_GPIOD +# define USART1_GPIOx GPIOD +# define USART1_TX_GPIO_PINx GPIO_PIN_5 +# define USART1_RX_GPIO_PINx GPIO_PIN_6 #else -# define USART1_GPIO_PORT GPIOA -# define USART1_GPIO_CLK RCU_GPIOA -# define USART1_TX_PIN GPIO_PIN_2 -# define USART1_RX_PIN GPIO_PIN_3 +# define USART1_RCU_GPIOx RCU_GPIOA +# define USART1_GPIOx GPIOA +# define USART1_TX_GPIO_PINx GPIO_PIN_2 +# define USART1_RX_GPIO_PINx GPIO_PIN_3 #endif -#define USART2_RCU_CLK RCU_USART2 +#define USART2_RCU_USART2 RCU_USART2 #if defined (USART2_FULL_REMAP) -# define USART2_GPIO_PORT GPIOD -# define USART2_GPIO_CLK RCU_GPIOD -# define USART2_TX_PIN GPIO_PIN_8 -# define USART2_RX_PIN GPIO_PIN_9 +# define USART2_RCU_GPIOx RCU_GPIOD +# define USART2_GPIOx GPIOD +# define USART2_TX_GPIO_PINx GPIO_PIN_8 +# define USART2_RX_GPIO_PINx GPIO_PIN_9 #elif defined (USART2_PARTIAL_REMAP) -# define USART2_GPIO_PORT GPIOC -# define USART2_GPIO_CLK RCU_GPIOC -# define USART2_TX_PIN GPIO_PIN_10 -# define USART2_RX_PIN GPIO_PIN_11 +# define USART2_RCU_GPIOx RCU_GPIOC +# define USART2_GPIOx GPIOC +# define USART2_TX_GPIO_PINx GPIO_PIN_10 +# define USART2_RX_GPIO_PINx GPIO_PIN_11 #else -# define USART2_GPIO_PORT GPIOB -# define USART2_GPIO_CLK RCU_GPIOB -# define USART2_TX_PIN GPIO_PIN_10 -# define USART2_RX_PIN GPIO_PIN_11 +# define USART2_RCU_GPIOx RCU_GPIOB +# define USART2_GPIOx GPIOB +# define USART2_TX_GPIO_PINx GPIO_PIN_10 +# define USART2_RX_GPIO_PINx GPIO_PIN_11 #endif -#define UART3_RCU_CLK RCU_UART3 +#define UART3_RCU_UART3 RCU_UART3 #if defined (UART3_REMAP) -# define UART3_GPIO_PORT GPIOA -# define UART3_GPIO_CLK RCU_GPIOA -# define UART3_TX_PIN GPIO_PIN_0 -# define UART3_RX_PIN GPIO_PIN_1 +# define UART3_RCU_GPIOx RCU_GPIOA +# define UART3_GPIOx GPIOA +# define UART3_TX_GPIO_PINx GPIO_PIN_0 +# define UART3_RX_GPIO_PINx GPIO_PIN_1 #else -# define UART3_GPIO_PORT GPIOC -# define UART3_GPIO_CLK RCU_GPIOC -# define UART3_TX_PIN GPIO_PIN_10 -# define UART3_RX_PIN GPIO_PIN_11 +# define UART3_RCU_GPIOx RCU_GPIOC +# define UART3_GPIOx GPIOC +# define UART3_TX_GPIO_PINx GPIO_PIN_10 +# define UART3_RX_GPIO_PINx GPIO_PIN_11 #endif -#define UART4_RCU_CLK RCU_UART4 -#define UART4_GPIO_TX_PORT GPIOC -#define UART4_GPIO_TX_CLK RCU_GPIOC -#define UART4_GPIO_RX_PORT GPIOD -#define UART4_GPIO_RX_CLK RCU_GPIOD -#define UART4_TX_PIN GPIO_PIN_12 -#define UART4_RX_PIN GPIO_PIN_2 +#define UART4_RCU_UART4 RCU_UART4 +#define UART4_TX_RCU_GPIOx RCU_GPIOC +#define UART4_TX_GPIOx GPIOC +#define UART4_TX_GPIO_PINx GPIO_PIN_12 +#define UART4_RX_RCU_GPIOx RCU_GPIOD +#define UART4_RX_GPIOx GPIOD +#define UART4_RX_GPIO_PINx GPIO_PIN_2 -#define USART5_RCU_CLK RCU_USART5 +#define USART5_RCU_USART5 RCU_USART5 #if defined (USART5_REMAP) -# define USART5_GPIO_PORT GPIOG -# define USART5_GPIO_CLK RCU_GPIOG -# define USART5_TX_PIN GPIO_PIN_14 -# define USART5_RX_PIN GPIO_PIN_9 +# define USART5_RCU_GPIOx RCU_GPIOG +# define USART5_GPIOx GPIOG +# define USART5_TX_GPIO_PINx GPIO_PIN_14 +# define USART5_RX_GPIO_PINx GPIO_PIN_9 #else -# define USART5_GPIO_PORT GPIOC -# define USART5_GPIO_CLK RCU_GPIOC -# define USART5_TX_PIN GPIO_PIN_6 -# define USART5_RX_PIN GPIO_PIN_7 +# define USART5_RCU_GPIOx RCU_GPIOC +# define USART5_GPIOx GPIOC +# define USART5_TX_GPIO_PINx GPIO_PIN_6 +# define USART5_RX_GPIO_PINx GPIO_PIN_7 #endif -#define UART6_RCU_CLK RCU_UART6 +#define UART6_RCU_UART6 RCU_UART6 #if defined (UART6_REMAP) -# define UART6_GPIO_PORT GPIOF -# define UART6_GPIO_CLK RCU_GPIOF -# define UART6_TX_PIN GPIO_PIN_7 -# define UART6_RX_PIN GPIO_PIN_6 +# define UART6_RCU_GPIOx RCU_GPIOF +# define UART6_GPIOx GPIOF +# define UART6_TX_GPIO_PINx GPIO_PIN_7 +# define UART6_RX_GPIO_PINx GPIO_PIN_6 #else -# define UART6_GPIO_PORT GPIOE -# define UART6_GPIO_CLK RCU_GPIOE -# define UART6_TX_PIN GPIO_PIN_8 -# define UART6_RX_PIN GPIO_PIN_7 +# define UART6_RCU_GPIOx RCU_GPIOE +# define UART6_GPIOx GPIOE +# define UART6_TX_GPIO_PINx GPIO_PIN_8 +# define UART6_RX_GPIO_PINx GPIO_PIN_7 #endif -#define UART7_RCU_CLK RCU_UART7 -#define UART7_GPIO_PORT GPIOE -#define UART7_GPIO_CLK RCU_GPIOE -#define UART7_TX_PIN GPIO_PIN_1 -#define UART7_RX_PIN GPIO_PIN_0 +#define UART7_RCU_UART7 RCU_UART7 +#define UART7_RCU_GPIOx RCU_GPIOE +#define UART7_GPIOx GPIOE +#define UART7_TX_GPIO_PINx GPIO_PIN_1 +#define UART7_RX_GPIO_PINx GPIO_PIN_0 /** * I2C */ #define I2C0_PERIPH I2C0 -#define I2C0_RCU_CLK RCU_I2C0 -#define I2C0_SCL_GPIOx GPIOB +#define I2C0_RCU_I2C0 RCU_I2C0 #define I2C0_SCL_RCU_GPIOx RCU_GPIOB -#define I2C0_SDA_GPIOx GPIOB +#define I2C0_SCL_GPIOx GPIOB #define I2C0_SDA_RCU_GPIOx RCU_GPIOB +#define I2C0_SDA_GPIOx GPIOB #if defined (I2C0_REMAP) # define I2C0_SCL_GPIO_PINx GPIO_PIN_8 # define I2C0_SDA_GPIO_PINx GPIO_PIN_9 @@ -166,186 +158,239 @@ #endif #define I2C1_PERIPH I2C1 -#define I2C1_RCU_CLK RCU_I2C1 +#define I2C1_RCU_I2C1 RCU_I2C1 #if defined (I2C1_REMAP10) -# define I2C1_SCL_GPIOx GPIOH # define I2C1_SCL_RCU_GPIOx RCU_GPIOH -# define I2C1_SDA_GPIOx GPIOH -# define I2C1_SDA_RCU_GPIOx RCU_GPIOH +# define I2C1_SCL_GPIOx GPIOH # define I2C1_SCL_GPIO_PINx GPIO_PIN_4 +# define I2C1_SDA_RCU_GPIOx RCU_GPIOH +# define I2C1_SDA_GPIOx GPIOH # define I2C1_SDA_GPIO_PINx GPIO_PIN_5 #elif defined (I2C1_REMAP11) -# define I2C1_SCL_GPIOx GPIOF # define I2C1_SCL_RCU_GPIOx RCU_GPIOF -# define I2C1_SDA_GPIOx GPIOF -# define I2C1_SDA_RCU_GPIOx RCU_GPIOF +# define I2C1_SCL_GPIOx GPIOF # define I2C1_SCL_GPIO_PINx GPIO_PIN_0 +# define I2C1_SDA_RCU_GPIOx RCU_GPIOF +# define I2C1_SDA_GPIOx GPIOF # define I2C1_SDA_GPIO_PINx GPIO_PIN_1 #else -# define I2C1_SCL_GPIOx GPIOB # define I2C1_SCL_RCU_GPIOx RCU_GPIOB -# define I2C1_SDA_GPIOx GPIOB -# define I2C1_SDA_RCU_GPIOx RCU_GPIOB +# define I2C1_SCL_GPIOx GPIOB # define I2C1_SCL_GPIO_PINx GPIO_PIN_10 +# define I2C1_SDA_RCU_GPIOx RCU_GPIOB +# define I2C1_SDA_GPIOx GPIOB # define I2C1_SDA_GPIO_PINx GPIO_PIN_11 #endif #define I2C2_PERIPH I2C2 -#define I2C2_RCU_CLK RCU_I2C2 +#define I2C2_RCU_I2C2 RCU_I2C2 #if defined (I2C2_REMAP) -# define I2C2_GPIO_SCL_PORT GPIOH -# define I2C2_GPIO_SCL_CLK RCU_GPIOH -# define I2C2_SCL_PIN GPIO_PIN_7 -# define I2C2_GPIO_SDA_PORT GPIOH -# define I2C2_GPIO_SDA_CLK RCU_GPIOH -# define I2C2_SDA_PIN GPIO_PIN_8 +# define I2C2_SCL_GPIOx GPIOH +# define I2C2_SCL_RCU_GPIOx RCU_GPIOH +# define I2C2_SCL_GPIO_PINx GPIO_PIN_7 +# define I2C2_SDA_GPIOx GPIOH +# define I2C2_SDA_RCU_GPIOx RCU_GPIOH +# define I2C2_SDA_GPIO_PINx GPIO_PIN_8 #else -# define I2C2_GPIO_SCL_PORT GPIOA -# define I2C2_GPIO_SCL_CLK RCU_GPIOA -# define I2C2_SCL_PIN GPIO_PIN_8 -# define I2C2_GPIO_SDA_PORT GPIOC -# define I2C2_GPIO_SDA_CLK RCU_GPIOC -# define I2C2_SDA_PIN GPIO_PIN_9 +# define I2C2_SCL_GPIOx GPIOA +# define I2C2_SCL_RCU_GPIOx RCU_GPIOA +# define I2C2_SCL_GPIO_PINx GPIO_PIN_8 +# define I2C2_SDA_GPIOx GPIOC +# define I2C2_SDA_RCU_GPIOx RCU_GPIOC +# define I2C2_SDA_GPIO_PINx GPIO_PIN_9 #endif /** * SPI */ -#define SPI0_PERiPH SPI0 -#define SPI0_RCU_CLK RCU_SPI0 +#define SPI0_PERIPH SPI0 +#define SPI0_RCU_SPI0 RCU_SPI0 #if defined (SPI0_REMAP) # define SPI0_REMAP_GPIO GPIO_SPI0_REMAP -# define SPI0_NSS_GPIOx GPIOA -# define SPI0_NSS_RCU_GPIOx RCU_GPIOA -# define SPI0_NSS_GPIO_PINx GPIO_PIN_15 # define SPI0_GPIOx GPIOB # define SPI0_RCU_GPIOx RCU_GPIOB # define SPI0_SCK_GPIO_PINx GPIO_PIN_3 # define SPI0_MISO_GPIO_PINx GPIO_PIN_4 # define SPI0_MOSI_GPIO_PINx GPIO_PIN_5 -#else -# define SPI0_NSS_GPIOx GPIOA # define SPI0_NSS_RCU_GPIOx RCU_GPIOA -# define SPI0_NSS_GPIO_PINx GPIO_PIN_4 +# define SPI0_NSS_GPIOx GPIOA +# define SPI0_NSS_GPIO_PINx GPIO_PIN_15 +#else # define SPI0_GPIOx GPIOA # define SPI0_RCU_GPIOx RCU_GPIOA # define SPI0_SCK_GPIO_PINx GPIO_PIN_5 # define SPI0_MISO_GPIO_PINx GPIO_PIN_6 # define SPI0_MOSI_GPIO_PINx GPIO_PIN_7 +# define SPI0_IO3_GPIO_PINx GPIO_PIN_2 +# define SPI0_IO4_GPIO_PINx GPIO_PIN_3 +# define SPI0_NSS_RCU_GPIOx RCU_GPIOA +# define SPI0_NSS_GPIOx GPIOA +# define SPI0_NSS_GPIO_PINx GPIO_PIN_4 #endif #define SPI1_PERIPH SPI1 -#define SPI1_RCU_CLK RCU_SPI1 +#define SPI1_RCU_SPI1 RCU_SPI1 #if defined (SPI1_REMAP10) -# define SPI1_NSS_GPIOx GPIOI -# define SPI1_NSS_RCU_GPIOx RCU_GPIOI -# define SPI1_NSS_GPIO_PINx GPIO_PIN_0 -# define SPI1_GPIOx GPIOI # define SPI1_RCU_GPIOx RCU_GPIOI +# define SPI1_GPIOx GPIOI # define SPI1_SCK_GPIO_PINx GPIO_PIN_1 # define SPI1_MISO_GPIO_PINx GPIO_PIN_2 # define SPI1_MOSI_GPIO_PINx GPIO_PIN_3 +# define SPI1_NSS_RCU_GPIOx RCU_GPIOI +# define SPI1_NSS_GPIOx GPIOI +# define SPI1_NSS_GPIO_PINx GPIO_PIN_0 #elif defined (SPI1_REMAP11) # error SPI1_REMAP11 is not defined #else -# define SPI1_NSS_GPIOx GPIOB -# define SPI1_NSS_RCU_GPIOx RCU_GPIOB -# define SPI1_NSS_GPIO_PINx GPIO_PIN_12 -# define SPI1_GPIOx GPIOB # define SPI1_RCU_GPIOx RCU_GPIOB +# define SPI1_GPIOx GPIOB # define SPI1_SCK_GPIO_PINx GPIO_PIN_13 # define SPI1_MISO_GPIO_PINx GPIO_PIN_14 # define SPI1_MOSI_GPIO_PINx GPIO_PIN_15 +# define SPI1_NSS_RCU_GPIOx RCU_GPIOB +# define SPI1_NSS_GPIOx GPIOB +# define SPI1_NSS_GPIO_PINx GPIO_PIN_12 #endif #define SPI2_PERIPH SPI2 -#define SPI2_RCU_CLK RCU_SPI2 +#define SPI2_RCU_SPI2 RCU_SPI2 #if defined (SPI2_REMAP) # define SPI2_REMAP_GPIO GPIO_SPI2_REMAP -# define SPI2_NSS_GPIOx GPIOA -# define SPI2_NSS_RCU_GPIOx RCU_GPIOA -# define SPI2_NSS_GPIO_PINx GPIO_PIN_4 -# define SPI2_GPIOx GPIOC # define SPI2_RCU_GPIOx RCU_GPIOC +# define SPI2_GPIOx GPIOC # define SPI2_SCK_GPIO_PINx GPIO_PIN_10 # define SPI2_MISO_GPIO_PINx GPIO_PIN_11 # define SPI2_MOSI_GPIO_PINx GPIO_PIN_12 -#else -# define SPI2_NSS_GPIOx GPIOA # define SPI2_NSS_RCU_GPIOx RCU_GPIOA -# define SPI2_NSS_GPIO_PINx GPIO_PIN_15 -# define SPI2_GPIOx GPIOB +# define SPI2_NSS_GPIOx GPIOA +# define SPI2_NSS_GPIO_PINx GPIO_PIN_4 +#else # define SPI2_RCU_GPIOx RCU_GPIOB +# define SPI2_GPIOx GPIOB # define SPI2_SCK_GPIO_PINx GPIO_PIN_3 # define SPI2_MISO_GPIO_PINx GPIO_PIN_4 # define SPI2_MOSI_GPIO_PINx GPIO_PIN_5 +# define SPI2_NSS_RCU_GPIOx RCU_GPIOA +# define SPI2_NSS_GPIOx GPIOA +# define SPI2_NSS_GPIO_PINx GPIO_PIN_15 #endif /** * TIMER GPIO */ -#define TIMER2CH0_RCU_GPIOx RCU_GPIOA -#define TIMER2CH0_GPIOx GPIOA -#define TIMER2CH0_GPIO_PINx GPIO_PIN_6 +#define TIMER2CH0_RCU_GPIOx RCU_GPIOA +#define TIMER2CH0_GPIOx GPIOA +#define TIMER2CH0_GPIO_PINx GPIO_PIN_6 + +#if defined(TIMER2_FULL_REMAP) +# define TIMER2_REMAP GPIO_TIMER2_FULL_REMAP +# define TIMER2_CH0_RCU_GPIOx RCU_GPIOC +# define TIMER2_CH0_GPIOx GPIOC +# define TIMER2_CH0_GPIO_PINx GPIO_PIN_6 + +# define TIMER2_CH1_RCU_GPIOx RCU_GPIOC +# define TIMER2_CH1_GPIOx GPIOC +# define TIMER2_CH1_GPIO_PINx GPIO_PIN_7 + +# define TIMER2_CH2_RCU_GPIOx RCU_GPIOC +# define TIMER2_CH2_GPIOx GPIOC +# define TIMER2_CH2_GPIO_PINx GPIO_PIN_8 + +# define TIMER2_CH3_RCU_GPIOx RCU_GPIOC +# define TIMER2_CH3_GPIOx GPIOC +# define TIMER2_CH3_GPIO_PINx GPIO_PIN_9 +#elif defined(TIMER2_PARTIAL_REMAP) +# define TIMER2_REMAP GPIO_TIMER2_PARTIAL_REMAP +# define TIMER2_CH0_RCU_GPIOx RCU_GPIOB +# define TIMER2_CH0_GPIOx GPIOB +# define TIMER2_CH0_GPIO_PINx GPIO_PIN_4 + +# define TIMER2_CH1_RCU_GPIOx RCU_GPIOB +# define TIMER2_CH1_GPIOx GPIOB +# define TIMER2_CH1_GPIO_PINx GPIO_PIN_5 + +# define TIMER2_CH2_RCU_GPIOx RCU_GPIOB +# define TIMER2_CH2_GPIOx GPIOB +# define TIMER2_CH2_GPIO_PINx GPIO_PIN_0 + +# define TIMER2_CH3_RCU_GPIOx RCU_GPIOB +# define TIMER2_CH3_GPIOx GPIOB +# define TIMER2_CH3_GPIO_PINx GPIO_PIN_1 +#else +# define TIMER2_CH0_RCU_GPIOx RCU_GPIOA +# define TIMER2_CH0_GPIOx GPIOA +# define TIMER2_CH0_GPIO_PINx GPIO_PIN_6 + +# define TIMER2_CH1_RCU_GPIOx RCU_GPIOA +# define TIMER2_CH1_GPIOx GPIOA +# define TIMER2_CH1_GPIO_PINx GPIO_PIN_7 + +# define TIMER2_CH2_RCU_GPIOx RCU_GPIOB +# define TIMER2_CH2_GPIOx GPIOB +# define TIMER2_CH2_GPIO_PINx GPIO_PIN_0 + +# define TIMER2_CH3_RCU_GPIOx RCU_GPIOB +# define TIMER2_CH3_GPIOx GPIOB +# define TIMER2_CH3_GPIO_PINx GPIO_PIN_1 +#endif /** * DMA */ -#define SPI0_DMAx DMA0 -#define SPI0_TX_DMA_CHx DMA_CH2 +#define SPI0_DMAx DMA0 +#define SPI0_TX_DMA_CHx DMA_CH2 -#define SPI1_DMAx DMA0 -#define SPI1_TX_DMA_CHx DMA_CH4 +#define SPI1_DMAx DMA0 +#define SPI1_TX_DMA_CHx DMA_CH4 -#define SPI2_DMAx DMA1 -#define SPI2_TX_DMA_CHx DMA_CH1 +#define SPI2_DMAx DMA1 +#define SPI2_TX_DMA_CHx DMA_CH1 -#define TIMER2_RCU_DMAx RCU_DMA0 -#define TIMER2_DMAx DMA0 -#define TIMER2_CH0_DMA_CHx DMA_CH5 -// #define TIMER2_CH1_DMA_CHx -#define TIMER2_CH2_DMA_CHx DMA_CH1 -#define TIMER2_CH3_DMA_CHx DMA_CH2 +#define TIMER2_RCU_DMAx RCU_DMA0 +#define TIMER2_DMAx DMA0 +#define TIMER2_CH0_DMA_CHx DMA_CH5 +#define TIMER2_CH2_DMA_CHx DMA_CH1 +#define TIMER2_CH3_DMA_CHx DMA_CH2 -#define TIMER7_RCU_DMAx RCU_DMA1 -#define TIMER7_DMAx DMA1 -#define TIMER7_CH0_DMA_CHx DMA_CH2 -#define TIMER7_CH1_DMA_CHx DMA_CH4 -#define TIMER7_CH2_DMA_CHx DMA_CH0 +#define TIMER7_RCU_DMAx RCU_DMA1 +#define TIMER7_DMAx DMA1 +#define TIMER7_CH0_DMA_CHx DMA_CH2 +#define TIMER7_CH1_DMA_CHx DMA_CH4 +#define TIMER7_CH2_DMA_CHx DMA_CH0 -#define USART0_DMA DMA0 -#define USART0_TX_DMA_CH DMA_CH3 -#define USART0_RX_DMA_CH DMA_CH4 +#define USART0_DMAx DMA0 +#define USART0_TX_DMA_CHx DMA_CH3 +#define USART0_RX_DMA_CHx DMA_CH4 -#define USART1_DMA DMA0 -#define USART1_TX_DMA_CH DMA_CH6 -#define USART1_RX_DMA_CH DMA_CH5 +#define USART1_DMAx DMA0 +#define USART1_TX_DMA_CHx DMA_CH6 +#define USART1_RX_DMA_CHx DMA_CH5 -#define USART2_DMA DMA0 -#define USART2_TX_DMA_CH DMA_CH1 -#define USART2_RX_DMA_CH DMA_CH2 +#define USART2_DMAx DMA0 +#define USART2_TX_DMA_CHx DMA_CH1 +#define USART2_RX_DMA_CHx DMA_CH2 -#define UART3_DMA DMA1 -#define UART3_TX_DMA_CH DMA_CH4 -#define UART3_RX_DMA_CH DMA_CH2 +#define UART3_DMAx DMA1 +#define UART3_TX_DMA_CHx DMA_CH4 +#define UART3_RX_DMA_CHx DMA_CH2 -#define UART4_DMA DMA1 -#define UART4_TX_DMA_CH DMA_CH3 -#define UART4_RX_DMA_CH DMA_CH1 +#define UART4_DMAx DMA1 +#define UART4_TX_DMA_CHx DMA_CH3 +#define UART4_RX_DMA_CHx DMA_CH1 -#define USART5_DMA DMA1 -#define USART5_TX_DMA_CH DMA_CH6 -#define USART5_RX_DMA_CH DMA_CH5 +#define USART5_DMAx DMA1 +#define USART5_TX_DMA_CHx DMA_CH6 +#define USART5_RX_DMA_CHx DMA_CH5 -#define UART6_DMA DMA1 -#define UART6_TX_DMA_CH DMA_CH4 -#define UART6_RX_DMA_CH DMA_CH2 +#define UART6_DMAx DMA1 +#define UART6_TX_DMA_CHx DMA_CH4 +#define UART6_RX_DMA_CHx DMA_CH2 -#define UART7_DMA DMA1 -#define UART7_TX_DMA_CH DMA_CH3 -#define UART7_RX_DMA_CH DMA_CH1 +#define UART7_DMAx DMA1 +#define UART7_TX_DMA_CHx DMA_CH3 +#define UART7_RX_DMA_CHx DMA_CH1 #endif /* MCU_GD32F20X_MCU_H_ */ diff --git a/lib-gd32/src/bkp.cpp b/lib-gd32/src/bkp.cpp index 74349c53..bd4d57d8 100644 --- a/lib-gd32/src/bkp.cpp +++ b/lib-gd32/src/bkp.cpp @@ -2,7 +2,7 @@ * @file bkp.cpp * */ -/* Copyright (C) 2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,18 +23,39 @@ * THE SOFTWARE. */ +#include + #include "gd32.h" -#if defined (GD32F4XX) +#if defined (GD32F4XX) || defined (GD32H7XX) void bkp_data_write(bkp_data_register_enum register_number, uint16_t data) { - if ((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_1)) { - REG16((BKPSRAM_BASE) + 16 + (register_number) * 2) = data; + switch (register_number) { + case BKP_DATA_0: + RTC_BKP0 = (uint32_t) data; + break; + case BKP_DATA_1: + RTC_BKP1 = (uint32_t) data; + break; + default: + assert(0); + break; } } + uint16_t bkp_data_read(bkp_data_register_enum register_number) { - if ((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_1)) { - return REG16((BKPSRAM_BASE) + 16 + (register_number) * 2); + switch (register_number) { + case BKP_DATA_0: + return RTC_BKP0; + break; + case BKP_DATA_1: + return RTC_BKP1; + break; + default: + assert(0); + break; } + + assert(0); return 0; } #endif diff --git a/lib-gd32/src/gd32_adc.cpp b/lib-gd32/src/f/gd32_adc.cpp similarity index 96% rename from lib-gd32/src/gd32_adc.cpp rename to lib-gd32/src/f/gd32_adc.cpp index 43479213..294b2951 100644 --- a/lib-gd32/src/gd32_adc.cpp +++ b/lib-gd32/src/f/gd32_adc.cpp @@ -27,7 +27,7 @@ #include "gd32.h" -void gd32_adc_init(void) { +void gd32_adc_init() { rcu_periph_clock_enable(RCU_ADC0); #if !defined (GD32F4XX) rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV12); @@ -86,21 +86,20 @@ void gd32_adc_init(void) { adc_software_trigger_enable(ADC0, ADC_INSERTED_CHANNEL); } -float gd32_adc_gettemp(void) { - /* value convert */ +float gd32_adc_gettemp() { const float temperature = (1.43f - ADC_IDATA0(ADC0) * 3.3f / 4096) * 1000 / 4.3f + 25; adc_software_trigger_enable(ADC0, ADC_INSERTED_CHANNEL); return temperature; } -float gd32_adc_getvref(void) { +float gd32_adc_getvref() { const float vref_value = (ADC_IDATA1(ADC0) * 3.3f / 4096); adc_software_trigger_enable(ADC0, ADC_INSERTED_CHANNEL); return vref_value; } #if defined (GD32F4XX) -float gd32_adc_getvbat(void) { +float gd32_adc_getvbat() { const float vref_value = (ADC_IDATA2(ADC0) * 3.3f / 4096) * 4; adc_software_trigger_enable(ADC0, ADC_INSERTED_CHANNEL); return vref_value; diff --git a/lib-gd32/src/f/gd32_dma_memcpy32.cpp b/lib-gd32/src/f/gd32_dma_memcpy32.cpp new file mode 100644 index 00000000..55625b32 --- /dev/null +++ b/lib-gd32/src/f/gd32_dma_memcpy32.cpp @@ -0,0 +1,55 @@ +/* + * gd32_dma_memcpy32.cpp + */ + +#include +#include + +#include "gd32.h" + +namespace dma { +void memcpy32_init() { +#if !defined (GD32F4XX) + rcu_periph_clock_enable(RCU_DMA0); + dma_deinit(DMA0, DMA_CH3); + + dma_parameter_struct dma_init_struct; + dma_struct_para_init(&dma_init_struct); + + dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY; +// dma_init_struct.memory_addr = destination; + dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_init_struct.memory_width = DMA_MEMORY_WIDTH_32BIT; + dma_init_struct.number = 0; // BUFFER_SIZE; +// dma_init_struct.periph_addr = source + dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_ENABLE; + dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_32BIT; + dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH; + + dma_init(DMA0, DMA_CH3, &dma_init_struct); + dma_circulation_disable(DMA0, DMA_CH3); + dma_memory_to_memory_enable(DMA0, DMA_CH3); +#else + rcu_periph_clock_enable(RCU_DMA1); + dma_deinit(DMA1, DMA_CH0); + + dma_multi_data_parameter_struct dma_init_parameter; + +// dma_init_parameter.periph_addr = source; + dma_init_parameter.periph_width = DMA_PERIPH_WIDTH_32BIT; + dma_init_parameter.periph_inc = DMA_PERIPH_INCREASE_ENABLE; +// dma_init_parameter.memory0_addr = destination; + dma_init_parameter.memory_width = DMA_MEMORY_WIDTH_32BIT; + dma_init_parameter.memory_inc = DMA_MEMORY_INCREASE_ENABLE; + dma_init_parameter.memory_burst_width = DMA_MEMORY_BURST_4_BEAT; + dma_init_parameter.periph_burst_width = DMA_PERIPH_BURST_4_BEAT; + dma_init_parameter.critical_value = DMA_FIFO_4_WORD; + dma_init_parameter.circular_mode = DMA_CIRCULAR_MODE_DISABLE; + dma_init_parameter.direction = DMA_MEMORY_TO_MEMORY; + dma_init_parameter.number = 0; // BUFFER_SIZE; + dma_init_parameter.priority = DMA_PRIORITY_ULTRA_HIGH; + + dma_multi_data_mode_init(DMA1, DMA_CH0, &dma_init_parameter); +#endif +} +} // namespace dma diff --git a/lib-gd32/src/gd32_i2c.cpp b/lib-gd32/src/f/gd32_i2c.cpp similarity index 67% rename from lib-gd32/src/gd32_i2c.cpp rename to lib-gd32/src/f/gd32_i2c.cpp index 2a233991..880f1146 100644 --- a/lib-gd32/src/gd32_i2c.cpp +++ b/lib-gd32/src/f/gd32_i2c.cpp @@ -2,7 +2,7 @@ * @file gd32_i2c.cpp * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -24,6 +24,7 @@ */ #include +#include #include "gd32_i2c.h" #include "gd32.h" @@ -32,21 +33,18 @@ static constexpr int32_t TIMEOUT = 0xfff; static uint8_t s_nAddress; -static int32_t _sendstart(void) { +static int32_t send_start() { auto nTimeout = TIMEOUT; - /* wait until I2C bus is idle */ while (i2c_flag_get(I2C_PERIPH, I2C_FLAG_I2CBSY)) { if (--nTimeout <= 0) { return -GD32_I2C_NOK_TOUT; } } - nTimeout = TIMEOUT; - - /* send a start condition to I2C bus */ i2c_start_on_bus(I2C_PERIPH); + nTimeout = TIMEOUT; /* wait until SBSEND bit is set */ while (!i2c_flag_get(I2C_PERIPH, I2C_FLAG_SBSEND)) { if (--nTimeout <= 0) { @@ -57,25 +55,22 @@ static int32_t _sendstart(void) { return GD32_I2C_OK; } -static int32_t _sendslaveaddr(void) { - auto nTimeout = TIMEOUT; - - /* send slave address to I2C bus */ +static int32_t send_slaveaddr() { i2c_master_addressing(I2C_PERIPH, s_nAddress, I2C_TRANSMITTER); - /* wait until ADDSEND bit is set */ + auto nTimeout = TIMEOUT; + while (!i2c_flag_get(I2C_PERIPH, I2C_FLAG_ADDSEND)) { if (--nTimeout <= 0) { return -GD32_I2C_NOK_TOUT; } } - /* clear the ADDSEND bit */ + i2c_flag_clear(I2C_PERIPH, I2C_FLAG_ADDSEND); nTimeout = TIMEOUT; - /* wait until the transmit data buffer is empty */ while (SET != i2c_flag_get(I2C_PERIPH, I2C_FLAG_TBE)) { if (--nTimeout <= 0) { return -GD32_I2C_NOK_TOUT; @@ -85,10 +80,9 @@ static int32_t _sendslaveaddr(void) { return GD32_I2C_OK; } -static int32_t _stop(void) { +static int32_t send_stop() { auto nTimeout = TIMEOUT; - /* send a stop condition to I2C bus */ i2c_stop_on_bus(I2C_PERIPH); /* wait until the stop condition is finished */ @@ -101,18 +95,12 @@ static int32_t _stop(void) { return GD32_I2C_OK; } -static int32_t _senddata(uint8_t *pData, uint32_t nCount) { - int32_t nTimeout; - +static int32_t send_data(const uint8_t *pData, const uint32_t nCount) { for (uint32_t i = 0; i < nCount; i++) { i2c_data_transmit(I2C_PERIPH, *pData); - - /* point to the next byte to be written */ pData++; + auto nTimeout = TIMEOUT; - nTimeout = TIMEOUT; - - /* wait until BTC bit is set */ while (!i2c_flag_get(I2C_PERIPH, I2C_FLAG_BTC)) { if (--nTimeout <= 0) { return -GD32_I2C_NOK_TOUT; @@ -123,60 +111,72 @@ static int32_t _senddata(uint8_t *pData, uint32_t nCount) { return GD32_I2C_OK; } -static int _write(char *pBuffer, int nLength) { - if (_sendstart() != GD32_I2C_OK) { - _stop(); +static int32_t write(const char *pBuffer, const int nLength) { + if (send_start() != GD32_I2C_OK) { + send_stop(); return -1; } - if (_sendslaveaddr() != GD32_I2C_OK) { - _stop(); + if (send_slaveaddr() != GD32_I2C_OK) { + send_stop(); return -1; } - if (_senddata((uint8_t*) pBuffer, (uint32_t) nLength) != GD32_I2C_OK) { - _stop(); + if (send_data((uint8_t*) pBuffer, (uint32_t) nLength) != GD32_I2C_OK) { + send_stop(); return -1; } - _stop(); + send_stop(); return 0; } -/* - * Public API's - */ - -void gd32_i2c_begin(void) { - rcu_periph_clock_enable(I2C_RCU_CLK); - rcu_periph_clock_enable(I2C_GPIO_SCL_CLK); - rcu_periph_clock_enable(I2C_GPIO_SDA_CLK); +static void rcu_config() { + rcu_periph_clock_enable(I2C_RCU_I2Cx); + rcu_periph_clock_enable(I2C_SCL_RCU_GPIOx); + rcu_periph_clock_enable(I2C_SDA_RCU_GPIOx); +} -#if !defined (GD32F4XX) - gpio_init(I2C_GPIO_SCL_PORT, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, I2C_SCL_PIN); - gpio_init(I2C_GPIO_SDA_PORT, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, I2C_SDA_PIN); +static void gpio_config() { +#if defined (GPIO_INIT) + gpio_init(I2C_SCL_GPIOx, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, I2C_SCL_GPIO_PINx); + gpio_init(I2C_SDA_GPIOx, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, I2C_SDA_GPIO_PINx); # if defined (I2C_REMAP) if (I2C_REMAP == GPIO_I2C0_REMAP) { gpio_pin_remap_config(GPIO_I2C0_REMAP, ENABLE); + } else { + assert(0); } # endif #else - gpio_af_set(I2C_GPIO_SCL_PORT, GPIO_AF_4, I2C_SCL_PIN); - gpio_af_set(I2C_GPIO_SCL_PORT, GPIO_AF_4, I2C_SDA_PIN); + gpio_af_set(I2C_SCL_GPIOx, I2C_GPIO_AFx, I2C_SCL_GPIO_PINx); + gpio_mode_set(I2C_SCL_GPIOx, GPIO_MODE_AF, GPIO_PUPD_PULLUP, I2C_SCL_GPIO_PINx); + gpio_output_options_set(I2C_SCL_GPIOx, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, I2C_SCL_GPIO_PINx); - gpio_mode_set(I2C_GPIO_SCL_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, I2C_SCL_PIN); - gpio_output_options_set(I2C_GPIO_SCL_PORT, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, I2C_SCL_PIN); - gpio_mode_set(I2C_GPIO_SDA_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, I2C_SDA_PIN); - gpio_output_options_set(I2C_GPIO_SDA_PORT, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, I2C_SDA_PIN); + gpio_af_set(I2C_SDA_GPIOx, I2C_GPIO_AFx, I2C_SDA_GPIO_PINx); + gpio_mode_set(I2C_SDA_GPIOx, GPIO_MODE_AF, GPIO_PUPD_PULLUP, I2C_SDA_GPIO_PINx); + gpio_output_options_set(I2C_SDA_GPIOx, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, I2C_SDA_GPIO_PINx); #endif +} +static void i2c_config() { i2c_clock_config(I2C_PERIPH, GD32_I2C_FULL_SPEED, I2C_DTCY_2); i2c_enable(I2C_PERIPH); i2c_ack_config(I2C_PERIPH, I2C_ACK_ENABLE); } +/* + * Public API's + */ + +void gd32_i2c_begin() { + rcu_config(); + gpio_config(); + i2c_config(); +} + void gd32_i2c_set_baudrate(uint32_t nBaudrate) { i2c_clock_config(I2C_PERIPH, nBaudrate, I2C_DTCY_2); } @@ -186,18 +186,16 @@ void gd32_i2c_set_address(uint8_t nAddress) { } uint8_t gd32_i2c_write(const char *pBuffer, uint32_t nLength) { - const auto ret = _write((char *)pBuffer, (int) nLength); - + const auto ret = write((char *)pBuffer, (int) nLength); return (uint8_t)-ret; } uint8_t gd32_i2c_read(char *pBuffer, uint32_t nLength) { auto nTimeout = TIMEOUT; - /* wait until I2C bus is idle */ while (i2c_flag_get(I2C_PERIPH, I2C_FLAG_I2CBSY)) { if (--nTimeout <= 0) { - _stop(); + send_stop(); return GD32_I2C_NOK_TOUT; } } @@ -206,79 +204,67 @@ uint8_t gd32_i2c_read(char *pBuffer, uint32_t nLength) { i2c_ackpos_config(I2C_PERIPH, I2C_ACKPOS_NEXT); } - /* send a start condition to I2C bus */ i2c_start_on_bus(I2C_PERIPH); nTimeout = TIMEOUT; - /* wait until SBSEND bit is set */ while (!i2c_flag_get(I2C_PERIPH, I2C_FLAG_SBSEND)) { if (--nTimeout <= 0) { - _stop(); + send_stop(); return GD32_I2C_NOK_TOUT; } } - /* send slave address to I2C bus */ i2c_master_addressing(I2C_PERIPH, s_nAddress, I2C_RECEIVER); if (nLength < 3) { - /* disable acknowledge */ i2c_ack_config(I2C_PERIPH, I2C_ACK_DISABLE); } nTimeout = TIMEOUT; - /* wait until ADDSEND bit is set */ while (!i2c_flag_get(I2C_PERIPH, I2C_FLAG_ADDSEND)) { if (--nTimeout <= 0) { - _stop(); + send_stop(); return GD32_I2C_NOK_TOUT; } } - /* clear the ADDSEND bit */ i2c_flag_clear(I2C_PERIPH, I2C_FLAG_ADDSEND); if (1 == nLength) { - /* send a stop condition to I2C bus */ i2c_stop_on_bus(I2C_PERIPH); } auto nTimeoutLoop = TIMEOUT; - /* while there is data to be read */ while (nLength) { if (3 == nLength) { nTimeout = TIMEOUT; - /* wait until BTC bit is set */ + while (!i2c_flag_get(I2C_PERIPH, I2C_FLAG_BTC)) { if (--nTimeout <= 0) { - _stop(); + send_stop(); return GD32_I2C_NOK_TOUT; } } - /* disable acknowledge */ i2c_ack_config(I2C_PERIPH, I2C_ACK_DISABLE); } if (2 == nLength) { nTimeout = TIMEOUT; - /* wait until BTC bit is set */ while (!i2c_flag_get(I2C_PERIPH, I2C_FLAG_BTC)) { if (--nTimeout <= 0) { - _stop(); + send_stop(); return GD32_I2C_NOK_TOUT; } } - /* send a stop condition to I2C bus */ i2c_stop_on_bus(I2C_PERIPH); } - /* wait until the RBNE bit is set and clear it */ if (i2c_flag_get(I2C_PERIPH, I2C_FLAG_RBNE)) { *pBuffer = i2c_data_receive(I2C_PERIPH); pBuffer++; @@ -287,23 +273,20 @@ uint8_t gd32_i2c_read(char *pBuffer, uint32_t nLength) { } if (--nTimeoutLoop <= 0) { - _stop(); + send_stop(); return GD32_I2C_NOK_TOUT; } } nTimeout = TIMEOUT; - /* wait until the stop condition is finished */ while (I2C_CTL0(I2C_PERIPH) & 0x0200) { if (--nTimeout <= 0) { return GD32_I2C_NOK_TOUT; } } - /* enable acknowledge */ i2c_ack_config(I2C_PERIPH, I2C_ACK_ENABLE); - i2c_ackpos_config(I2C_PERIPH, I2C_ACKPOS_CURRENT); return GD32_I2C_OK; diff --git a/lib-gd32/src/gd32_spi.cpp b/lib-gd32/src/f/gd32_spi.cpp similarity index 70% rename from lib-gd32/src/gd32_spi.cpp rename to lib-gd32/src/f/gd32_spi.cpp index 74a9828c..5e16577f 100644 --- a/lib-gd32/src/gd32_spi.cpp +++ b/lib-gd32/src/f/gd32_spi.cpp @@ -2,7 +2,7 @@ * @file gd32_spi.cpp * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,19 +32,19 @@ static uint8_t s_nChipSelect = GD32_SPI_CS0; -static inline void _cs_high() { +static void cs_high() { if (s_nChipSelect == GD32_SPI_CS0) { - GPIO_BOP(SPI_NSS_GPIOx) = static_cast(SPI_NSS_GPIO_PINx); + GPIO_BOP(SPI_NSS_GPIOx) = SPI_NSS_GPIO_PINx; } } -static inline void _cs_low() { +static void cs_low() { if (s_nChipSelect == GD32_SPI_CS0) { - GPIO_BC(SPI_NSS_GPIOx) = static_cast(SPI_NSS_GPIO_PINx); + GPIO_BC(SPI_NSS_GPIOx) = SPI_NSS_GPIO_PINx; } } -static uint8_t _send_byte(uint8_t byte) { +static uint8_t send_byte(uint8_t byte) { while (RESET == (SPI_STAT(SPI_PERIPH) & SPI_FLAG_TBE)) ; @@ -56,37 +56,44 @@ static uint8_t _send_byte(uint8_t byte) { return static_cast(static_cast(SPI_DATA(SPI_PERIPH))); } -void gd32_spi_begin() { +static void rcu_config() { + rcu_periph_clock_enable(SPI_RCU_SPIx); rcu_periph_clock_enable(SPI_RCU_GPIOx); - rcu_periph_clock_enable(SPI_RCU_CLK); + rcu_periph_clock_enable(SPI_NSS_RCU_GPIOx); -#if !defined (GD32F4XX) +#if defined (GPIO_INIT) rcu_periph_clock_enable(RCU_AF); +#endif +} - gpio_init(SPI_GPIOx, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, SPI_SCK_PIN | SPI_MISO_PIN | SPI_MOSI_PIN); - -# if defined (SPI_REMAP) - gpio_pin_remap_config(SPI_REMAP, ENABLE); +static void gpio_config() { +#if defined (GPIO_INIT) +# if defined (SPI_REMAP_GPIO) + gpio_pin_remap_config(SPI_REMAP_GPIO, ENABLE); + if (SPI_PERIPH == SPI0) { + gpio_pin_remap_config(GPIO_SWJ_DISABLE_REMAP, ENABLE); + } # else if (SPI_PERIPH == SPI2) { gpio_pin_remap_config(GPIO_SWJ_DISABLE_REMAP, ENABLE); } # endif + gpio_init(SPI_GPIOx, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, SPI_SCK_GPIO_PINx | SPI_MOSI_GPIO_PINx); + gpio_init(SPI_GPIOx, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, SPI_MISO_GPIO_PINx); + gpio_init(SPI_NSS_GPIOx, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, SPI_NSS_GPIO_PINx); #else - if (SPI_PERIPH == SPI2) { - gpio_af_set(SPI_GPIOx, GPIO_AF_6, SPI_SCK_PIN | SPI_MISO_PIN | SPI_MOSI_PIN); - } else { - gpio_af_set(SPI_GPIOx, GPIO_AF_5, SPI_SCK_PIN | SPI_MISO_PIN | SPI_MOSI_PIN); - } + gpio_af_set(SPI_GPIOx, SPI_GPIO_AFx, SPI_SCK_GPIO_PINx | SPI_MISO_GPIO_PINx | SPI_MOSI_GPIO_PINx); + gpio_mode_set(SPI_GPIOx, GPIO_MODE_AF, GPIO_PUPD_NONE, SPI_SCK_GPIO_PINx | SPI_MISO_GPIO_PINx | SPI_MOSI_GPIO_PINx); + gpio_output_options_set(SPI_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, SPI_SCK_GPIO_PINx | SPI_MOSI_GPIO_PINx); - gpio_mode_set(SPI_GPIOx, GPIO_MODE_AF, GPIO_PUPD_NONE, SPI_SCK_PIN | SPI_MISO_PIN | SPI_MOSI_PIN); - gpio_output_options_set(SPI_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, SPI_SCK_PIN | SPI_MISO_PIN | SPI_MOSI_PIN); + gpio_mode_set(SPI_NSS_GPIOx, GPIO_MODE_OUTPUT,GPIO_PUPD_NONE, SPI_NSS_GPIO_PINx); + gpio_output_options_set(SPI_NSS_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, SPI_NSS_GPIO_PINx); #endif - gpio_fsel(SPI_NSS_GPIOx, SPI_NSS_GPIO_PINx, GPIO_FSEL_OUTPUT); - - _cs_high(); + cs_high(); +} +static void spi_config() { spi_disable(SPI_PERIPH); spi_i2s_deinit(SPI_PERIPH); @@ -103,15 +110,23 @@ void gd32_spi_begin() { spi_enable(SPI_PERIPH); } +/* + * Public API's + */ + +void gd32_spi_begin() { + rcu_config(); + gpio_config(); + spi_config(); +} + void gd32_spi_end() { - spi_i2s_deinit(SPI_PERIPH); -#if !defined (GD32F4XX) - gpio_init(SPI_GPIOx, GPIO_MODE_IPD, GPIO_OSPEED_50MHZ, SPI_SCK_PIN | SPI_MISO_PIN | SPI_MOSI_PIN); + spi_disable(SPI_PERIPH); +#if defined (GPIO_INIT) + gpio_init(SPI_GPIOx, GPIO_MODE_IPD, GPIO_OSPEED_50MHZ, SPI_SCK_GPIO_PINx | SPI_MISO_GPIO_PINx | SPI_MOSI_GPIO_PINx); gpio_init(SPI_NSS_GPIOx, GPIO_MODE_IPD, GPIO_OSPEED_50MHZ, SPI_NSS_GPIO_PINx); #else - gpio_af_set(SPI_GPIOx, GPIO_AF_0, SPI_SCK_PIN | SPI_MISO_PIN | SPI_MOSI_PIN); - gpio_mode_set(SPI_GPIOx, GPIO_MODE_INPUT, GPIO_PUPD_NONE, SPI_SCK_PIN | SPI_MISO_PIN | SPI_MOSI_PIN); - + gpio_mode_set(SPI_GPIOx, GPIO_MODE_INPUT, GPIO_PUPD_NONE, SPI_SCK_GPIO_PINx | SPI_MISO_GPIO_PINx | SPI_MOSI_GPIO_PINx); gpio_mode_set(SPI_NSS_GPIOx, GPIO_MODE_INPUT, GPIO_PUPD_NONE, SPI_NSS_GPIO_PINx); #endif } @@ -165,21 +180,27 @@ void gd32_spi_setDataMode(uint8_t nMode) { void gd32_spi_chipSelect(uint8_t nChipSelect) { s_nChipSelect = nChipSelect; + + if (nChipSelect == GD32_SPI_CS0) { + spi_nss_output_enable(SPI_PERIPH); + } else { + spi_nss_output_disable(SPI_PERIPH); + } } void gd32_spi_transfernb(const char *pTxBuffer, char *pRxBuffer, uint32_t nDataLength) { assert(pTxBuffer != nullptr); assert(pRxBuffer != nullptr); - _cs_low(); + cs_low(); while (nDataLength-- > 0) { - *pRxBuffer = _send_byte(static_cast(*pTxBuffer)); + *pRxBuffer = send_byte(static_cast(*pTxBuffer)); pRxBuffer++; pTxBuffer++; } - _cs_high(); + cs_high(); } void gd32_spi_transfern(char *pTxBuffer, uint32_t nDataLength) { @@ -187,23 +208,23 @@ void gd32_spi_transfern(char *pTxBuffer, uint32_t nDataLength) { } void gd32_spi_write(const uint16_t nData) { - _cs_low(); + cs_low(); - _send_byte(static_cast(nData >> 8)); - _send_byte(static_cast(nData & 0xFF)); + send_byte(static_cast(nData >> 8)); + send_byte(static_cast(nData & 0xFF)); - _cs_high(); + cs_high(); } void gd32_spi_writenb(const char *pTxBuffer, uint32_t nDataLength) { assert(pTxBuffer != nullptr); - _cs_low(); + cs_low(); while (nDataLength-- > 0) { - _send_byte(static_cast(*pTxBuffer)); + send_byte(static_cast(*pTxBuffer)); pTxBuffer++; } - _cs_high(); + cs_high(); } diff --git a/lib-gd32/src/i2s_psc_config_dump.cpp b/lib-gd32/src/f/i2s_psc_config_dump.cpp similarity index 96% rename from lib-gd32/src/i2s_psc_config_dump.cpp rename to lib-gd32/src/f/i2s_psc_config_dump.cpp index e364ec22..e8d72356 100644 --- a/lib-gd32/src/i2s_psc_config_dump.cpp +++ b/lib-gd32/src/f/i2s_psc_config_dump.cpp @@ -45,7 +45,7 @@ #define RCU_CFG1_PREDV1_OFFSET 4U /* PREDV1 offset in RCU_CFG1 */ #define RCU_CFG1_PLL2MF_OFFSET 12U /* PLL2MF offset in RCU_CFG1 */ -void i2s_psc_config_dump(__attribute__((unused)) uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout) { +void i2s_psc_config_dump([[maybe_unused]] uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout) { uint32_t i2sdiv = 2U, i2sof = 0U; uint32_t clks = 0U; uint32_t i2sclock = 0U; diff --git a/lib-gd32/src/gd32_gpio_mode_set.cpp b/lib-gd32/src/gd32_gpio_mode_set.cpp new file mode 100644 index 00000000..bf8f4807 --- /dev/null +++ b/lib-gd32/src/gd32_gpio_mode_set.cpp @@ -0,0 +1,75 @@ +#if defined (GD32F4XX) || defined (GD32H7XX) +/** + * @file gd32_gpio_mode_set.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "gd32.h" + +void gd32_gpio_mode_set_output(const uint32_t gpio_periph, const uint32_t pin) { + assert(pin != 0); + assert(__builtin_popcount(static_cast(pin)) == 1); + + auto ctl = GPIO_CTL(gpio_periph); + auto pupd = GPIO_PUD(gpio_periph); + + const auto i = 31 - __builtin_clz(pin); + + /* clear the specified pin mode bits */ + ctl &= ~GPIO_MODE_MASK(i); + /* set the specified pin mode bits */ + ctl |= GPIO_MODE_SET(i, GPIO_MODE_OUTPUT); + /* clear the specified pin pupd bits */ + pupd &= ~GPIO_PUPD_MASK(i); + /* set the specified pin pupd bits */ + pupd |= GPIO_PUPD_SET(i, GPIO_PUPD_NONE); + + GPIO_CTL(gpio_periph) = ctl; + GPIO_PUD(gpio_periph) = pupd; +} + +void gd32_gpio_mode_set_af(const uint32_t gpio_periph, const uint32_t pin) { + assert(pin != 0); + assert(__builtin_popcount(static_cast(pin)) == 1); + + auto ctl = GPIO_CTL(gpio_periph); + auto pupd = GPIO_PUD(gpio_periph); + + const auto i = 31 - __builtin_clz(pin); + + /* clear the specified pin mode bits */ + ctl &= ~GPIO_MODE_MASK(i); + /* set the specified pin mode bits */ + ctl |= GPIO_MODE_SET(i, GPIO_MODE_AF); + /* clear the specified pin pupd bits */ + pupd &= ~GPIO_PUPD_MASK(i); + /* set the specified pin pupd bits */ + pupd |= GPIO_PUPD_SET(i, GPIO_PUPD_PULLUP); + + GPIO_CTL(gpio_periph) = ctl; + GPIO_PUD(gpio_periph) = pupd; +} +#endif diff --git a/lib-gd32/src/gd32_pwm.cpp b/lib-gd32/src/gd32_pwm.cpp new file mode 100644 index 00000000..44c8da36 --- /dev/null +++ b/lib-gd32/src/gd32_pwm.cpp @@ -0,0 +1,300 @@ +/** + * @file gd32_pwm.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#if 0 +#undef NDEBUG + +#define PWM_TIMERx TIMER2 +#define PWM_RCU_TIMERx RCU_TIMER2 + +#define TIMER2_FULL_REMAP +#define PWM_TIMER_REMAP TIMER2_REMAP +#define PWM_GPIO_AFx TIMER2_GPIO_AFx + +#define PWM_CH0_RCU_GPIOx TIMER2_CH0_RCU_GPIOx +#define PWM_CH0_GPIOx TIMER2_CH0_GPIOx +#define PWM_CH0_GPIO_PINx TIMER2_CH0_GPIO_PINx + +#define PWM_CH1_RCU_GPIOx TIMER2_CH1_RCU_GPIOx +#define PWM_CH1_GPIOx TIMER2_CH1_GPIOx +#define PWM_CH1_GPIO_PINx TIMER2_CH1_GPIO_PINx + +#define PWM_CH2_RCU_GPIOx TIMER2_CH2_RCU_GPIOx +#define PWM_CH2_GPIOx TIMER2_CH2_GPIOx +#define PWM_CH2_GPIO_PINx TIMER2_CH2_GPIO_PINx + +#define PWM_CH3_RCU_GPIOx TIMER2_CH3_RCU_GPIOx +#define PWM_CH3_GPIOx TIMER2_CH3_GPIOx +#define PWM_CH3_GPIO_PINx TIMER2_CH3_GPIO_PINx +#endif + +#include +#ifndef NDEBUG +# include +#endif + +#include "gd32_pwm.h" +#include "gd32.h" + +#include "debug.h" + +namespace pwm { +#if !defined(PWM_CHANNEL_0_DUTYCYCLE) +# define PWM_CHANNEL_0_DUTYCYCLE 50 +#endif +#if !defined(PWM_CHANNEL_1_DUTYCYCLE) +# define PWM_CHANNEL_1_DUTYCYCLE 50 +#endif +#if !defined(PWM_CHANNEL_2_DUTYCYCLE) +# define PWM_CHANNEL_2_DUTYCYCLE 50 +#endif +#if !defined(PWM_CHANNEL_3_DUTYCYCLE) +# define PWM_CHANNEL_3_DUTYCYCLE 50 +#endif +#if defined (PWM_CH0_RCU_GPIOx) +static constexpr uint32_t DEFAUL_CHANNEL_0_DUTYCYCLE = PWM_CHANNEL_0_DUTYCYCLE; +#endif +#if defined (PWM_CH1_RCU_GPIOx) +static constexpr uint32_t DEFAUL_CHANNEL_1_DUTYCYCLE = PWM_CHANNEL_1_DUTYCYCLE; +#endif +#if defined (PWM_CH2_RCU_GPIOx) +static constexpr uint32_t DEFAUL_CHANNEL_2_DUTYCYCLE = PWM_CHANNEL_2_DUTYCYCLE; +#endif +#if defined (PWM_CH3_RCU_GPIOx) +static constexpr uint32_t DEFAUL_CHANNEL_3_DUTYCYCLE = PWM_CHANNEL_3_DUTYCYCLE; +#endif +#if defined (PWM_RCU_TIMERx) && defined (PWM_TIMERx) +static constexpr uint32_t TIMER_PERIOD = 19999; // 50KHz +#endif +} // namespace pwm + +#if defined (PWM_RCU_TIMERx) && defined (PWM_TIMERx) + +static void dump() { +#if 1 + DEBUG_ENTRY +#ifndef NDEBUG + printf("PWM_TIMERx=0x%.8X\n", PWM_TIMERx - TIMER_BASE); + printf("PWM_RCU_TIMERx=0x%.8X\n", PWM_RCU_TIMERx); +# if defined (GPIO_INIT) + printf("PWM_TIMER_REMAP=0x%.8X\n", PWM_TIMER_REMAP); +# endif + puts("--------------------------------"); +# if defined (PWM_CH0_RCU_GPIOx) + printf("PWM_CH0_RCU_GPIOx=0x%.8X\n", PWM_CH0_RCU_GPIOx); + printf("PWM_CH0_GPIOx=0x%.8X\n", PWM_CH0_GPIOx); + printf("PWM_CH0_GPIO_PINx=0x%.4X\n", PWM_CH0_GPIO_PINx); + puts("--------------------------------"); +# endif +# if defined (PWM_CH1_RCU_GPIOx) + printf("PWM_CH1_RCU_GPIOx=0x%.8X\n", PWM_CH1_RCU_GPIOx); + printf("PWM_CH1_GPIOx=0x%.8X\n", PWM_CH1_GPIOx); + printf("PWM_CH1_GPIO_PINx=0x%.4X\n", PWM_CH1_GPIO_PINx); + puts("--------------------------------"); +# endif +# if defined (PWM_CH2_RCU_GPIOx) + printf("PWM_CH2_RCU_GPIOx=0x%.8X\n", PWM_CH2_RCU_GPIOx); + printf("PWM_CH2_GPIOx=0x%.8X\n", PWM_CH2_GPIOx); + printf("PWM_CH2_GPIO_PINx=0x%.4X\n", PWM_CH2_GPIO_PINx); + puts("--------------------------------"); +# endif +# if defined (PWM_CH3_RCU_GPIOx) + printf("PWM_CH3_RCU_GPIOx=0x%.8X\n", PWM_CH3_RCU_GPIOx); + printf("PWM_CH3_GPIOx=0x%.8X\n", PWM_CH3_GPIOx); + printf("PWM_CH3_GPIO_PINx=0x%.4X\n", PWM_CH3_GPIO_PINx); +# endif +#endif + DEBUG_EXIT +#endif +} + +static void gpio_config() { +#if defined (PWM_CH0_RCU_GPIOx) + rcu_periph_clock_enable(PWM_CH0_RCU_GPIOx); +#endif +#if defined (PWM_CH1_RCU_GPIOx) + rcu_periph_clock_enable(PWM_CH1_RCU_GPIOx); +#endif +#if defined (PWM_CH2_RCU_GPIOx) + rcu_periph_clock_enable(PWM_CH2_RCU_GPIOx); +#endif +#if defined (PWM_CH3_RCU_GPIOx) + rcu_periph_clock_enable(PWM_CH3_RCU_GPIOx); +#endif + +#if defined (GPIO_INIT) + rcu_periph_clock_enable(RCU_AF); +# if defined(PWM_TIMER_REMAP) + gpio_pin_remap_config(PWM_TIMER_REMAP, ENABLE); +# endif +# if defined (PWM_CH0_GPIOx) && defined (PWM_CH0_GPIO_PINx) + gpio_init(PWM_CH0_GPIOx, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, PWM_CH0_GPIO_PINx); +# endif +# if defined (PWM_CH1_GPIOx) && defined (PWM_CH1_GPIO_PINx) + gpio_init(PWM_CH1_GPIOx, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, PWM_CH1_GPIO_PINx); +# endif +# if defined (PWM_CH2_GPIOx) && defined (PWM_CH2_GPIO_PINx) + gpio_init(PWM_CH2_GPIOx, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, PWM_CH2_GPIO_PINx); +# endif +# if defined (PWM_CH3_GPIOx) && defined (PWM_CH3_GPIO_PINx) + gpio_init(PWM_CH3_GPIOx, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, PWM_CH3_GPIO_PINx); +# endif +#else +# if defined (PWM_CH0_GPIOx) && defined (PWM_CH0_GPIO_PINx) + gpio_af_set(PWM_CH0_GPIOx, PWM_GPIO_AFx, PWM_CH0_GPIO_PINx); + gpio_mode_set(PWM_CH0_GPIOx, GPIO_MODE_AF, GPIO_PUPD_NONE, PWM_CH0_GPIO_PINx); + gpio_output_options_set(PWM_CH0_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, PWM_CH0_GPIO_PINx); +# endif +# if defined (PWM_CH1_GPIOx) && defined (PWM_CH1_GPIO_PINx) + gpio_af_set(PWM_CH1_GPIOx, PWM_GPIO_AFx, PWM_CH1_GPIO_PINx); + gpio_mode_set(PWM_CH1_GPIOx, GPIO_MODE_AF, GPIO_PUPD_NONE, PWM_CH1_GPIO_PINx); + gpio_output_options_set(PWM_CH1_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, PWM_CH1_GPIO_PINx); +# endif +# if defined (PWM_CH2_GPIOx) && defined (PWM_CH2_GPIO_PINx) + gpio_af_set(PWM_CH2_GPIOx, PWM_GPIO_AFx, PWM_CH2_GPIO_PINx); + gpio_mode_set(PWM_CH2_GPIOx, GPIO_MODE_AF, GPIO_PUPD_NONE, PWM_CH2_GPIO_PINx); + gpio_output_options_set(PWM_CH2_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, PWM_CH2_GPIO_PINx); +# endif +# if defined (PWM_CH3_GPIOx) && defined (PWM_CH3_GPIO_PINx) + gpio_af_set(PWM_CH3_GPIOx, PWM_GPIO_AFx, PWM_CH3_GPIO_PINx); + gpio_mode_set(PWM_CH3_GPIOx, GPIO_MODE_AF, GPIO_PUPD_NONE, PWM_CH3_GPIO_PINx); + gpio_output_options_set(PWM_CH3_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, PWM_CH3_GPIO_PINx); +# endif +#endif +} + +static void timer_config() { +#if defined (PWM_RCU_TIMERx) && defined (PWM_TIMERx) + rcu_periph_clock_enable(PWM_RCU_TIMERx); + + timer_deinit(PWM_TIMERx); + + timer_parameter_struct timer_initpara; + timer_initpara.prescaler = TIMER_PSC_1MHZ; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = pwm::TIMER_PERIOD; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init(PWM_TIMERx, &timer_initpara); + +# if defined (PWM_CH0_RCU_GPIOx) || defined (PWM_CH1_RCU_GPIOx) || defined (PWM_CH2_RCU_GPIOx) || defined (PWM_CH3_RCU_GPIOx) + timer_oc_parameter_struct timer_ocintpara; + timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocintpara.outputstate = TIMER_CCX_ENABLE; + timer_ocintpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocintpara.outputnstate = TIMER_CCXN_DISABLE; + timer_ocintpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + timer_ocintpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; +# endif +# if defined (PWM_CH0_RCU_GPIOx) + timer_channel_output_config(PWM_TIMERx, TIMER_CH_0, &timer_ocintpara); + timer_channel_output_pulse_value_config(PWM_TIMERx, TIMER_CH_0, 1999); + timer_channel_output_mode_config(PWM_TIMERx, TIMER_CH_0, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(PWM_TIMERx, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); +# endif +# if defined (PWM_CH1_RCU_GPIOx) + timer_channel_output_config(PWM_TIMERx, TIMER_CH_1, &timer_ocintpara); + timer_channel_output_pulse_value_config(PWM_TIMERx, TIMER_CH_1, 3999); + timer_channel_output_mode_config(PWM_TIMERx, TIMER_CH_1, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(PWM_TIMERx, TIMER_CH_1, TIMER_OC_SHADOW_DISABLE); +# endif +# if defined (PWM_CH2_RCU_GPIOx) + timer_channel_output_config(PWM_TIMERx, TIMER_CH_2, &timer_ocintpara); + timer_channel_output_pulse_value_config(PWM_TIMERx, TIMER_CH_2, 7999); + timer_channel_output_mode_config(PWM_TIMERx, TIMER_CH_2, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(PWM_TIMERx, TIMER_CH_2, TIMER_OC_SHADOW_DISABLE); +# endif +# if defined (PWM_CH3_RCU_GPIOx) + timer_channel_output_config(PWM_TIMERx, TIMER_CH_3, &timer_ocintpara); + timer_channel_output_pulse_value_config(PWM_TIMERx, TIMER_CH_3, 11999); + timer_channel_output_mode_config(PWM_TIMERx, TIMER_CH_3, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(PWM_TIMERx, TIMER_CH_3, TIMER_OC_SHADOW_DISABLE); +# endif + + timer_auto_reload_shadow_enable(PWM_TIMERx); + timer_enable(PWM_TIMERx); +#endif +} + +void gd32_pwm_begin() { + DEBUG_ENTRY + + dump(); + + gpio_config(); + timer_config(); + +#if defined (PWM_CH0_RCU_GPIOx) + gd32_pwm_set_duty_cycle(pwm::Channel::PWM_CHANNEL_0, pwm::DEFAUL_CHANNEL_0_DUTYCYCLE); +#endif +#if defined (PWM_CH1_RCU_GPIOx) + gd32_pwm_set_duty_cycle(pwm::Channel::PWM_CHANNEL_1, pwm::DEFAUL_CHANNEL_1_DUTYCYCLE); +#endif +#if defined (PWM_CH2_RCU_GPIOx) + gd32_pwm_set_duty_cycle(pwm::Channel::PWM_CHANNEL_2, pwm::DEFAUL_CHANNEL_2_DUTYCYCLE); +#endif +#if defined (PWM_CH3_RCU_GPIOx) + gd32_pwm_set_duty_cycle(pwm::Channel::PWM_CHANNEL_3, pwm::DEFAUL_CHANNEL_3_DUTYCYCLE); +#endif + + DEBUG_EXIT +} + +void gd32_pwm_set_duty_cycle(const pwm::Channel channel, const uint32_t nDutyCycle) { + DEBUG_ENTRY + + const uint32_t nPulse = (nDutyCycle > 100 ? 100 : nDutyCycle) * (pwm::TIMER_PERIOD / 100U); + + DEBUG_PRINTF("Channel=%u, nDutyCycle=%u, nPulse=%u", static_cast(channel), nDutyCycle, static_cast(nPulse)); + + switch (channel) { +#if defined (PWM_CH0_RCU_GPIOx) + case pwm::Channel::PWM_CHANNEL_0: + timer_channel_output_pulse_value_config(PWM_TIMERx, TIMER_CH_0, nPulse); + break; +#endif +#if defined (PWM_CH1_RCU_GPIOx) + case pwm::Channel::PWM_CHANNEL_1: + timer_channel_output_pulse_value_config(PWM_TIMERx, TIMER_CH_1, nPulse); + break; +#endif +#if defined (PWM_CH2_RCU_GPIOx) + case pwm::Channel::PWM_CHANNEL_2: + timer_channel_output_pulse_value_config(PWM_TIMERx, TIMER_CH_2, nPulse); + break; +#endif +#if defined (PWM_CH3_RCU_GPIOx) + case pwm::Channel::PWM_CHANNEL_3: + timer_channel_output_pulse_value_config(PWM_TIMERx, TIMER_CH_3, nPulse); + break; +#endif + default: + break; + } + + DEBUG_EXIT +} +#endif diff --git a/lib-gd32/src/gd32_spi_dma_i2s.cpp b/lib-gd32/src/gd32_spi_dma_i2s.cpp index e25fedae..6ddfbd5e 100644 --- a/lib-gd32/src/gd32_spi_dma_i2s.cpp +++ b/lib-gd32/src/gd32_spi_dma_i2s.cpp @@ -2,7 +2,7 @@ * @file gd32_spi_dma_i2s.cpp * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,143 +28,156 @@ #include "gd32.h" -#if defined (GD32F4XX) -# define DMA_PARAMETER_STRUCT dma_single_data_parameter_struct -# define DMA_CHMADDR DMA_CHM0ADDR -# define DMA_MEMORY_TO_PERIPHERAL DMA_MEMORY_TO_PERIPH -# define DMA_PERIPHERAL_WIDTH_16BIT DMA_PERIPH_WIDTH_16BIT -# define dma_init dma_single_data_mode_init -# define dma_struct_para_init dma_single_data_para_struct_init -# define dma_memory_to_memory_disable(x,y) +#if defined (I2S_PERIPH) + +# if defined (GD32H7XX) + static_assert(I2S_PERIPH != SPI3); + static_assert(I2S_PERIPH != SPI4); +# else + static_assert(I2S_PERIPH != SPI0); +# endif + +# if defined (GD32F4XX) || defined (GD32H7XX) +# define DMA_PARAMETER_STRUCT dma_single_data_parameter_struct +# define DMA_CHMADDR DMA_CHM0ADDR +# define DMA_MEMORY_TO_PERIPHERAL DMA_MEMORY_TO_PERIPH +# define DMA_PERIPHERAL_WIDTH_16BIT DMA_PERIPH_WIDTH_16BIT +# define dma_init dma_single_data_mode_init +# define dma_struct_para_init dma_single_data_para_struct_init +# define dma_memory_to_memory_disable(x,y) +# else +# define DMA_PARAMETER_STRUCT dma_parameter_struct +# endif + +# ifndef NDEBUG +# if !defined (GD32H7XX) + void i2s_psc_config_dump(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout); +# endif +# endif + +# if !defined(SPI_BUFFER_SIZE) +# define SPI_BUFFER_SIZE ((24 * 1024) / 2) +# endif + +static uint16_t s_TxBuffer[SPI_BUFFER_SIZE] __attribute__ ((aligned (4))); + +static void rcu_config() { + rcu_periph_clock_enable(I2S_WS_RCU_GPIOx); + +#if defined (GPIO_INIT) + rcu_periph_clock_enable(RCU_AF); + rcu_periph_clock_enable(I2S_RCU_SPIx); + rcu_periph_clock_enable(I2S_RCU_GPIOx); #else -# define DMA_PARAMETER_STRUCT dma_parameter_struct + rcu_periph_clock_enable(I2S_CK_RCU_GPIOx); + rcu_periph_clock_enable(I2S_SD_RCU_GPIOx); #endif -#ifndef NDEBUG -void i2s_psc_config_dump(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout); -#endif + if (I2S_DMAx == DMA0) { + rcu_periph_clock_enable(RCU_DMA0); + } else { + rcu_periph_clock_enable(RCU_DMA1); + } -#if !defined(SPI_BUFFER_SIZE) -# define SPI_BUFFER_SIZE ((24 * 1024) / 2) +#if defined (GD32H7XX) + rcu_periph_clock_enable(RCU_DMAMUX); #endif +} -static uint16_t s_TxBuffer[SPI_BUFFER_SIZE] __attribute__ ((aligned (4))); +static void gpio_config() { +#if defined (GPIO_INIT) +# if defined (I2S_REMAP_GPIO) + gpio_pin_remap_config(I2S_REMAP_GPIO, ENABLE); + if (I2S_PERIPH == SPI0) { + gpio_pin_remap_config(GPIO_SWJ_DISABLE_REMAP, ENABLE); + } +# else + if (I2S_PERIPH == SPI2) { + gpio_pin_remap_config(GPIO_SWJ_DISABLE_REMAP, ENABLE); + } +# endif + gpio_init(I2S_GPIOx, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, I2S_CK_GPIO_PINx | I2S_SD_GPIO_PINx); + gpio_init(I2S_WS_GPIOx, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, I2S_WS_GPIO_PINx); +#else + gpio_af_set(I2S_CK_GPIOx, I2S_GPIO_AFx, I2S_CK_GPIO_PINx); + gpio_mode_set(I2S_CK_GPIOx, GPIO_MODE_AF, GPIO_PUPD_NONE, I2S_CK_GPIO_PINx); + gpio_output_options_set(I2S_CK_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, I2S_CK_GPIO_PINx); + + gpio_af_set(I2S_SD_GPIOx, I2S_GPIO_AFx, I2S_SD_GPIO_PINx); + gpio_mode_set(I2S_SD_GPIOx, GPIO_MODE_AF, GPIO_PUPD_NONE, I2S_SD_GPIO_PINx); + gpio_output_options_set(I2S_SD_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, I2S_SD_GPIO_PINx); -static void _spi_i2s_dma_config() { - rcu_periph_clock_enable(RCU_DMA1); + gpio_af_set(I2S_WS_GPIOx, I2S_GPIO_AFx, I2S_WS_GPIO_PINx); + gpio_mode_set(I2S_WS_GPIOx, GPIO_MODE_OUTPUT,GPIO_PUPD_NONE, I2S_WS_GPIO_PINx); + gpio_output_options_set(I2S_WS_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, I2S_WS_GPIO_PINx); +#endif +} - dma_deinit(SPI_DMAx, SPI_DMA_CHx); +static void spi_i2s_dma_config() { + dma_deinit(I2S_DMAx, I2S_DMA_CHx); DMA_PARAMETER_STRUCT dma_init_struct; dma_struct_para_init(&dma_init_struct); + +#if defined (GD32H7XX) + dma_init_struct.request = I2S_DMA_REQUEST_I2S_TX; +#endif dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL; dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE; -#if !defined (GD32F4XX) +# if defined (GD32F4XX) || defined (GD32H7XX) +# else dma_init_struct.memory_width = DMA_MEMORY_WIDTH_16BIT; #endif - dma_init_struct.periph_addr = SPI_PERIPH + 0x0CU; - dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; -#if !defined (GD32F4XX) - dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_16BIT; +#if defined (GD32H7XX) + dma_init_struct.periph_addr = (uint32_t)&SPI_TDATA(I2S_PERIPH); #else + dma_init_struct.periph_addr = I2S_PERIPH + 0x0CU; +#endif + dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE; +#if defined (GD32F4XX) || defined (GD32H7XX) dma_init_struct.periph_memory_width = DMA_PERIPHERAL_WIDTH_16BIT; +#else + dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_16BIT; #endif dma_init_struct.priority = DMA_PRIORITY_HIGH; - dma_init(SPI_DMAx, SPI_DMA_CHx, &dma_init_struct); - /* configure DMA mode */ - dma_circulation_disable(SPI_DMAx, SPI_DMA_CHx); - dma_memory_to_memory_disable(SPI_DMAx, SPI_DMA_CHx); + dma_init(I2S_DMAx, I2S_DMA_CHx, &dma_init_struct); + + dma_circulation_disable(I2S_DMAx, I2S_DMA_CHx); + dma_memory_to_memory_disable(I2S_DMAx, I2S_DMA_CHx); #if defined (GD32F4XX) - dma_channel_subperipheral_select(SPI_DMAx, SPI_DMA_CHx, SPI_DMA_SUBPERIx); + dma_channel_subperipheral_select(I2S_DMAx, I2S_DMA_CHx, I2S_DMA_SUBPERIx); #endif - DMA_CHCNT(SPI_DMAx, SPI_DMA_CHx) = 0; + DMA_CHCNT(I2S_DMAx, I2S_DMA_CHx) = 0; } - +namespace i2s { void gd32_spi_dma_begin() { - assert(SPI_PERIPH != SPI0); - - rcu_periph_clock_enable(SPI_NSS_RCU_GPIOx); - rcu_periph_clock_enable(SPI_RCU_GPIOx); - rcu_periph_clock_enable(SPI_RCU_CLK); - -#if !defined (GD32F4XX) - rcu_periph_clock_enable(RCU_AF); - - gpio_init(SPI_GPIOx, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, SPI_SCK_PIN | SPI_MISO_PIN | SPI_MOSI_PIN); - gpio_init(SPI_NSS_GPIOx, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, SPI_NSS_GPIO_PINx); - -# if defined (SPI2_REMAP) - gpio_pin_remap_config(GPIO_SPI2_REMAP, ENABLE); -# else - if (SPI_PERIPH == SPI2) { - gpio_pin_remap_config(GPIO_SWJ_DISABLE_REMAP, ENABLE); - } -# endif -#else - if (SPI_PERIPH == SPI2) { - gpio_af_set(SPI_GPIOx, GPIO_AF_6, SPI_SCK_PIN | SPI_MISO_PIN | SPI_MOSI_PIN); - } else { - gpio_af_set(SPI_GPIOx, GPIO_AF_5, SPI_SCK_PIN | SPI_MISO_PIN | SPI_MOSI_PIN); - } - gpio_mode_set(SPI_GPIOx, GPIO_MODE_AF, GPIO_PUPD_NONE, SPI_SCK_PIN | SPI_MISO_PIN | SPI_MOSI_PIN); - gpio_output_options_set(SPI_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, SPI_SCK_PIN | SPI_MISO_PIN | SPI_MOSI_PIN); - - gpio_mode_set(SPI_NSS_GPIOx, GPIO_MODE_OUTPUT,GPIO_PUPD_NONE, SPI_NSS_GPIO_PINx); - gpio_output_options_set(SPI_NSS_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, SPI_NSS_GPIO_PINx); -#endif - -#if defined (GD32F10X_CL) || defined (GD32F20X_CL) - /** - * Setup PLL2 - * - * i2sclock=160000000 - * i2sdiv=12, i2sof=256 - */ - - RCU_CTL &= ~RCU_CTL_PLL2EN; - - rcu_pll2_config(RCU_PLL2_MUL16); + rcu_config(); + gpio_config(); - RCU_CTL |= RCU_CTL_PLL2EN; + i2s_disable(I2S_PERIPH); + i2s_psc_config(I2S_PERIPH, 200000, I2S_FRAMEFORMAT_DT16B_CH16B, I2S_MCKOUT_DISABLE); + i2s_init(I2S_PERIPH, I2S_MODE_MASTERTX, I2S_STD_MSB, I2S_CKPL_LOW); + i2s_enable(I2S_PERIPH); - while ((RCU_CTL & RCU_CTL_PLL2STB) == 0U) { - } - - if (SPI_PERIPH == SPI2) { - rcu_i2s2_clock_config(RCU_I2S2SRC_CKPLL2_MUL2); - } else { - rcu_i2s1_clock_config(RCU_I2S1SRC_CKPLL2_MUL2); - } -#endif - - i2s_disable(SPI_PERIPH); - i2s_psc_config(SPI_PERIPH, 200000, I2S_FRAMEFORMAT_DT16B_CH16B, I2S_MCKOUT_DISABLE); - i2s_init(SPI_PERIPH, I2S_MODE_MASTERTX, I2S_STD_MSB, I2S_CKPL_LOW); - i2s_enable(SPI_PERIPH); - - _spi_i2s_dma_config(); + spi_i2s_dma_config(); #ifndef NDEBUG - i2s_psc_config_dump(SPI_PERIPH, 200000, I2S_FRAMEFORMAT_DT16B_CH16B, I2S_MCKOUT_DISABLE); + i2s_psc_config_dump(I2S_PERIPH, 200000, I2S_FRAMEFORMAT_DT16B_CH16B, I2S_MCKOUT_DISABLE); #endif } void gd32_spi_dma_set_speed_hz(uint32_t nSpeedHz) { - const auto audiosample = nSpeedHz / 16 / 2 ; + const auto audiosample = nSpeedHz / 16U / 2U ; - i2s_disable(SPI_PERIPH); - i2s_psc_config(SPI2, audiosample, I2S_FRAMEFORMAT_DT16B_CH16B, I2S_MCKOUT_DISABLE); - i2s_enable(SPI_PERIPH); + i2s_disable(I2S_PERIPH); + i2s_psc_config(I2S_PERIPH, audiosample, I2S_FRAMEFORMAT_DT16B_CH16B, I2S_MCKOUT_DISABLE); + i2s_enable(I2S_PERIPH); } -/** - * DMA - */ - const uint8_t *gd32_spi_dma_tx_prepare(uint32_t *nLength) { *nLength = (sizeof(s_TxBuffer) / sizeof(s_TxBuffer[0])) * 2; - return (const uint8_t*) s_TxBuffer; + return (const uint8_t *) s_TxBuffer; } void gd32_spi_dma_tx_start(const uint8_t *pTxBuffer, uint32_t nLength) { @@ -172,24 +185,27 @@ void gd32_spi_dma_tx_start(const uint8_t *pTxBuffer, uint32_t nLength) { assert((uint32_t )pTxBuffer >= (uint32_t )s_TxBuffer); assert(nLength != 0); +#if defined (GD32F4XX) || defined (GD32H7XX) + dma_flag_clear(I2S_DMAx, I2S_DMA_CHx, DMA_FLAG_FTF); +#endif + const auto dma_chcnt = (((nLength + 1) / 2) & DMA_CHXCNT_CNT); - auto nDmaChCTL = DMA_CHCTL(SPI_DMAx, SPI_DMA_CHx); + auto nDmaChCTL = DMA_CHCTL(I2S_DMAx, I2S_DMA_CHx); nDmaChCTL &= ~DMA_CHXCTL_CHEN; - DMA_CHCTL(SPI_DMAx, SPI_DMA_CHx) = nDmaChCTL; - DMA_CHMADDR(SPI_DMAx, SPI_DMA_CHx) = (uint32_t)pTxBuffer; - DMA_CHCNT(SPI_DMAx, SPI_DMA_CHx) = dma_chcnt; + DMA_CHCTL(I2S_DMAx, I2S_DMA_CHx) = nDmaChCTL; + + DMA_CHMADDR(I2S_DMAx, I2S_DMA_CHx) = (uint32_t)pTxBuffer; + DMA_CHCNT(I2S_DMAx, I2S_DMA_CHx) = dma_chcnt; + nDmaChCTL |= DMA_CHXCTL_CHEN; - DMA_CHCTL(SPI_DMAx, SPI_DMA_CHx) = nDmaChCTL; - spi_dma_enable(SPI_PERIPH, SPI_DMA_TRANSMIT); -} + DMA_CHCTL(I2S_DMAx, I2S_DMA_CHx) = nDmaChCTL; -bool gd32_spi_dma_tx_is_active(void) { - return (uint32_t) DMA_CHCNT(SPI_DMAx, SPI_DMA_CHx) != 0; + spi_dma_enable(I2S_PERIPH, SPI_DMA_TRANSMIT); } -/** - * /CS - */ - -//TODO Implement /CS +bool gd32_spi_dma_tx_is_active() { + return DMA_CHCNT(I2S_DMAx, I2S_DMA_CHx) != 0; +} +} // namespace i2s +#endif diff --git a/lib-gd32/src/gd32_uart.cpp b/lib-gd32/src/gd32_uart.cpp index 7620cddc..41ef6a83 100644 --- a/lib-gd32/src/gd32_uart.cpp +++ b/lib-gd32/src/gd32_uart.cpp @@ -2,7 +2,7 @@ * @file gd32_uart.cpp * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,51 +29,51 @@ #include "gd32_uart.h" #include "gd32.h" -static void _rcu_periph_clock_enable(const uint32_t usart_periph) { +static void rcu_config(const uint32_t usart_periph) { #ifndef NDEBUG bool isSet = false; #endif switch (usart_periph) { case USART0: - rcu_periph_clock_enable(USART0_RCU_CLK); - rcu_periph_clock_enable(USART0_GPIO_CLK); + rcu_periph_clock_enable(USART0_RCU_USART0); + rcu_periph_clock_enable(USART0_RCU_GPIOx); #ifndef NDEBUG isSet = true; #endif break; case USART1: - rcu_periph_clock_enable(USART1_RCU_CLK); - rcu_periph_clock_enable(USART1_GPIO_CLK); + rcu_periph_clock_enable(USART1_RCU_USART1); + rcu_periph_clock_enable(USART1_RCU_GPIOx); #ifndef NDEBUG isSet = true; #endif break; case USART2: - rcu_periph_clock_enable(USART2_RCU_CLK); - rcu_periph_clock_enable(USART2_GPIO_CLK); + rcu_periph_clock_enable(USART2_RCU_USART2); + rcu_periph_clock_enable(USART2_RCU_GPIOx); #ifndef NDEBUG isSet = true; #endif break; case UART3: - rcu_periph_clock_enable(UART3_RCU_CLK); - rcu_periph_clock_enable(UART3_GPIO_CLK); + rcu_periph_clock_enable(UART3_RCU_UART3); + rcu_periph_clock_enable(UART3_RCU_GPIOx); #ifndef NDEBUG isSet = true; #endif break; case UART4: - rcu_periph_clock_enable(UART4_RCU_CLK); - rcu_periph_clock_enable(UART4_GPIO_TX_CLK); - rcu_periph_clock_enable(UART4_GPIO_RX_CLK); + rcu_periph_clock_enable(UART4_RCU_UART4); + rcu_periph_clock_enable(UART4_TX_RCU_GPIOx); + rcu_periph_clock_enable(UART4_RX_RCU_GPIOx); #ifndef NDEBUG isSet = true; #endif break; #if defined (USART5) case USART5: - rcu_periph_clock_enable(USART5_RCU_CLK); - rcu_periph_clock_enable(USART5_GPIO_CLK); + rcu_periph_clock_enable(USART5_RCU_USART5); + rcu_periph_clock_enable(USART5_RCU_GPIOx); # ifndef NDEBUG isSet = true; # endif @@ -81,8 +81,8 @@ static void _rcu_periph_clock_enable(const uint32_t usart_periph) { #endif #if defined (UART6) case UART6: - rcu_periph_clock_enable(UART6_RCU_CLK); - rcu_periph_clock_enable(UART6_GPIO_CLK); + rcu_periph_clock_enable(UART6_RCU_UART6); + rcu_periph_clock_enable(UART6_RCU_GPIOx); # ifndef NDEBUG isSet = true; # endif @@ -90,8 +90,8 @@ static void _rcu_periph_clock_enable(const uint32_t usart_periph) { #endif #if defined (UART7) case UART7: - rcu_periph_clock_enable(UART7_RCU_CLK); - rcu_periph_clock_enable(UART7_GPIO_CLK); + rcu_periph_clock_enable(UART7_RCU_UART7); + rcu_periph_clock_enable(UART7_RCU_GPIOx); # ifndef NDEBUG isSet = true; # endif @@ -106,28 +106,28 @@ static void _rcu_periph_clock_enable(const uint32_t usart_periph) { assert(isSet); } -#if !defined (GD32F4XX) -static void _gpio_init(const uint32_t usart_periph) { +#if !(defined (GD32F4XX) || defined (GD32H7XX)) +static void gpio_config(const uint32_t usart_periph) { rcu_periph_clock_enable(RCU_AF); switch (usart_periph) { case USART0: - gpio_init(USART0_GPIO_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, USART0_TX_PIN); - gpio_init(USART0_GPIO_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, USART0_RX_PIN); + gpio_init(USART0_GPIOx, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, USART0_TX_GPIO_PINx); + gpio_init(USART0_GPIOx, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, USART0_RX_GPIO_PINx); #if defined (USART0_REMAP) gpio_pin_remap_config(GPIO_USART0_REMAP, ENABLE); #endif break; case USART1: - gpio_init(USART1_GPIO_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, USART1_TX_PIN); - gpio_init(USART1_GPIO_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, USART1_RX_PIN); + gpio_init(USART1_GPIOx, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, USART1_TX_GPIO_PINx); + gpio_init(USART1_GPIOx, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, USART1_RX_GPIO_PINx); #if defined (USART1_REMAP) gpio_pin_remap_config(GPIO_USART1_REMAP, ENABLE); #endif break; case USART2: - gpio_init(USART2_GPIO_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, USART2_TX_PIN); - gpio_init(USART2_GPIO_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, USART2_RX_PIN); + gpio_init(USART2_GPIOx, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, USART2_TX_GPIO_PINx); + gpio_init(USART2_GPIOx, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, USART2_RX_GPIO_PINx); #if defined (USART2_FULL_REMAP) gpio_pin_remap_config(GPIO_USART2_FULL_REMAP, ENABLE); #elif defined (USART2_PARTIAL_REMAP) @@ -135,20 +135,20 @@ static void _gpio_init(const uint32_t usart_periph) { #endif break; case UART3: - gpio_init(UART3_GPIO_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, UART3_TX_PIN); - gpio_init(UART3_GPIO_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, UART3_RX_PIN); + gpio_init(UART3_GPIOx, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, UART3_TX_GPIO_PINx); + gpio_init(UART3_GPIOx, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, UART3_RX_GPIO_PINx); #if defined (UART3_REMAP) gpio_pin_remap_config(GPIO_PCF5_UART3_REMAP, ENABLE); #endif break; case UART4: - gpio_init(UART4_GPIO_TX_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, UART4_TX_PIN); - gpio_init(UART4_GPIO_RX_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, UART4_RX_PIN); + gpio_init(UART4_TX_GPIOx, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, UART4_TX_GPIO_PINx); + gpio_init(UART4_RX_GPIOx, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, UART4_RX_GPIO_PINx); break; #if defined (USART5) case USART5: - gpio_init(USART5_GPIO_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, USART5_TX_PIN); - gpio_init(USART5_GPIO_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, USART5_RX_PIN); + gpio_init(USART5_GPIOx, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, USART5_TX_GPIO_PINx); + gpio_init(USART5_GPIOx, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, USART5_RX_GPIO_PINx); # if defined (USART5_REMAP) gpio_pin_remap_config(GPIO_PCF5_USART5_TX_PG14_REMAP, ENABLE); gpio_pin_remap_config(GPIO_PCF5_USART5_RX_PG9_REMAP, ENABLE); @@ -157,8 +157,8 @@ static void _gpio_init(const uint32_t usart_periph) { #endif #if defined (UART6) case UART6: - gpio_init(UART6_GPIO_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, UART6_TX_PIN); - gpio_init(UART6_GPIO_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, UART6_RX_PIN); + gpio_init(UART6_GPIOx, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, UART6_TX_GPIO_PINx); + gpio_init(UART6_GPIOx, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, UART6_RX_GPIO_PINx); # if defined (UART6_REMAP) gpio_pin_remap_config(GPIO_PCF5_UART6_REMAP, ENABLE); # endif @@ -166,8 +166,8 @@ static void _gpio_init(const uint32_t usart_periph) { #endif #if defined (UART7) case UART7: - gpio_init(UART7_GPIO_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, UART7_TX_PIN); - gpio_init(UART7_GPIO_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, UART7_RX_PIN); + gpio_init(UART7_GPIOx, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, UART7_TX_GPIO_PINx); + gpio_init(UART7_GPIOx, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, UART7_RX_GPIO_PINx); break; #endif default: @@ -177,77 +177,77 @@ static void _gpio_init(const uint32_t usart_periph) { } } #else -void _gpio_init(const uint32_t usart_periph) { +static void gpio_config(const uint32_t usart_periph) { switch (usart_periph) { case USART0: - gpio_af_set(USART0_GPIO_PORT, GPIO_AF_7, USART0_TX_PIN); - gpio_mode_set(USART0_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART0_TX_PIN); - gpio_output_options_set(USART0_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, USART0_TX_PIN); - gpio_af_set(USART0_GPIO_PORT, GPIO_AF_7, USART0_RX_PIN); - gpio_mode_set(USART0_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART0_RX_PIN); - gpio_output_options_set(USART0_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, USART0_RX_PIN); + gpio_af_set(USART0_GPIOx, USART0_GPIO_AFx, USART0_TX_GPIO_PINx); + gpio_mode_set(USART0_GPIOx, GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART0_TX_GPIO_PINx); + gpio_output_options_set(USART0_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, USART0_TX_GPIO_PINx); + gpio_af_set(USART0_GPIOx, USART0_GPIO_AFx, USART0_RX_GPIO_PINx); + gpio_mode_set(USART0_GPIOx, GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART0_RX_GPIO_PINx); + gpio_output_options_set(USART0_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, USART0_RX_GPIO_PINx); break; case USART1: - gpio_af_set(USART1_GPIO_PORT, GPIO_AF_7, USART1_TX_PIN); - gpio_mode_set(USART1_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART1_TX_PIN); - gpio_output_options_set(USART1_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, USART1_TX_PIN); - gpio_af_set(USART1_GPIO_PORT, GPIO_AF_7, USART1_RX_PIN); - gpio_mode_set(USART1_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART1_RX_PIN); - gpio_output_options_set(USART1_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, USART1_RX_PIN); + gpio_af_set(USART1_GPIOx, USART1_GPIO_AFx, USART1_TX_GPIO_PINx); + gpio_mode_set(USART1_GPIOx, GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART1_TX_GPIO_PINx); + gpio_output_options_set(USART1_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, USART1_TX_GPIO_PINx); + gpio_af_set(USART1_GPIOx, USART1_GPIO_AFx, USART1_RX_GPIO_PINx); + gpio_mode_set(USART1_GPIOx, GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART1_RX_GPIO_PINx); + gpio_output_options_set(USART1_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, USART1_RX_GPIO_PINx); break; case USART2: - gpio_af_set(USART2_GPIO_PORT, GPIO_AF_7, USART2_TX_PIN); - gpio_mode_set(USART2_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART2_TX_PIN); - gpio_output_options_set(USART2_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, USART2_TX_PIN); - gpio_af_set(USART2_GPIO_PORT, GPIO_AF_7, USART2_RX_PIN); - gpio_mode_set(USART2_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART2_RX_PIN); - gpio_output_options_set(USART2_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, USART2_RX_PIN); + gpio_af_set(USART2_GPIOx, USART2_GPIO_AFx, USART2_TX_GPIO_PINx); + gpio_mode_set(USART2_GPIOx, GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART2_TX_GPIO_PINx); + gpio_output_options_set(USART2_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, USART2_TX_GPIO_PINx); + gpio_af_set(USART2_GPIOx, USART2_GPIO_AFx, USART2_RX_GPIO_PINx); + gpio_mode_set(USART2_GPIOx, GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART2_RX_GPIO_PINx); + gpio_output_options_set(USART2_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, USART2_RX_GPIO_PINx); break; case UART3: - gpio_af_set(UART3_GPIO_PORT, GPIO_AF_8, UART3_TX_PIN); - gpio_mode_set(UART3_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, UART3_TX_PIN); - gpio_output_options_set(UART3_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, UART3_TX_PIN); - gpio_af_set(UART3_GPIO_PORT, GPIO_AF_8, UART3_RX_PIN); - gpio_mode_set(UART3_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, UART3_RX_PIN); - gpio_output_options_set(UART3_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, UART3_RX_PIN); + gpio_af_set(UART3_GPIOx, UART3_GPIO_AFx, UART3_TX_GPIO_PINx); + gpio_mode_set(UART3_GPIOx, GPIO_MODE_AF, GPIO_PUPD_PULLUP, UART3_TX_GPIO_PINx); + gpio_output_options_set(UART3_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, UART3_TX_GPIO_PINx); + gpio_af_set(UART3_GPIOx, UART3_GPIO_AFx, UART3_RX_GPIO_PINx); + gpio_mode_set(UART3_GPIOx, GPIO_MODE_AF, GPIO_PUPD_PULLUP, UART3_RX_GPIO_PINx); + gpio_output_options_set(UART3_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, UART3_RX_GPIO_PINx); break; case UART4: - gpio_af_set(UART4_GPIO_TX_PORT, GPIO_AF_8, UART4_TX_PIN); - gpio_mode_set(UART4_GPIO_TX_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, UART4_TX_PIN); - gpio_output_options_set(UART4_GPIO_TX_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, UART4_TX_PIN); - gpio_af_set(UART4_GPIO_RX_PORT, GPIO_AF_8, UART4_RX_PIN); - gpio_mode_set(UART4_GPIO_RX_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, UART4_RX_PIN); - gpio_output_options_set(UART4_GPIO_RX_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, UART4_RX_PIN); + gpio_af_set(UART4_TX_GPIOx, UART4_GPIO_AFx, UART4_TX_GPIO_PINx); + gpio_mode_set(UART4_TX_GPIOx, GPIO_MODE_AF, GPIO_PUPD_PULLUP, UART4_TX_GPIO_PINx); + gpio_output_options_set(UART4_TX_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, UART4_TX_GPIO_PINx); + gpio_af_set(UART4_RX_GPIOx, UART4_GPIO_AFx, UART4_RX_GPIO_PINx); + gpio_mode_set(UART4_RX_GPIOx, GPIO_MODE_AF, GPIO_PUPD_PULLUP, UART4_RX_GPIO_PINx); + gpio_output_options_set(UART4_RX_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, UART4_RX_GPIO_PINx); break; #if defined (USART5) case USART5: - gpio_af_set(USART5_GPIO_PORT, GPIO_AF_8, USART5_TX_PIN); - gpio_mode_set(USART5_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART5_TX_PIN); - gpio_output_options_set(USART5_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, USART5_TX_PIN); - gpio_af_set(USART5_GPIO_PORT, GPIO_AF_8, USART5_RX_PIN); - gpio_mode_set(USART5_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART5_RX_PIN); - gpio_output_options_set(USART5_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, USART5_RX_PIN); + gpio_af_set(USART5_GPIOx, USART5_GPIO_AFx, USART5_TX_GPIO_PINx); + gpio_mode_set(USART5_GPIOx, GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART5_TX_GPIO_PINx); + gpio_output_options_set(USART5_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, USART5_TX_GPIO_PINx); + gpio_af_set(USART5_GPIOx, USART5_GPIO_AFx, USART5_RX_GPIO_PINx); + gpio_mode_set(USART5_GPIOx, GPIO_MODE_AF, GPIO_PUPD_PULLUP, USART5_RX_GPIO_PINx); + gpio_output_options_set(USART5_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, USART5_RX_GPIO_PINx); break; #endif #if defined (UART6) case UART6: - gpio_af_set(UART6_GPIO_PORT, GPIO_AF_8, UART6_TX_PIN); - gpio_mode_set(UART6_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, UART6_TX_PIN); - gpio_output_options_set(UART6_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, UART6_TX_PIN); - gpio_af_set(UART6_GPIO_PORT, GPIO_AF_8, UART6_RX_PIN); - gpio_mode_set(UART6_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, UART6_RX_PIN); - gpio_output_options_set(UART6_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, UART6_RX_PIN); + gpio_af_set(UART6_GPIOx, UART6_GPIO_AFx, UART6_TX_GPIO_PINx); + gpio_mode_set(UART6_GPIOx, GPIO_MODE_AF, GPIO_PUPD_PULLUP, UART6_TX_GPIO_PINx); + gpio_output_options_set(UART6_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, UART6_TX_GPIO_PINx); + gpio_af_set(UART6_GPIOx, UART6_GPIO_AFx, UART6_RX_GPIO_PINx); + gpio_mode_set(UART6_GPIOx, GPIO_MODE_AF, GPIO_PUPD_PULLUP, UART6_RX_GPIO_PINx); + gpio_output_options_set(UART6_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, UART6_RX_GPIO_PINx); break; #endif #if defined (UART7) case UART7: - gpio_af_set(UART7_GPIO_PORT, GPIO_AF_8, UART7_TX_PIN); - gpio_mode_set(UART7_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, UART7_TX_PIN); - gpio_output_options_set(UART7_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, UART7_TX_PIN); - gpio_af_set(UART7_GPIO_PORT, GPIO_AF_8, UART7_RX_PIN); - gpio_mode_set(UART7_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, UART7_RX_PIN); - gpio_output_options_set(UART7_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, UART7_RX_PIN); + gpio_af_set(UART7_GPIOx, UART7_GPIO_AFx, UART7_TX_GPIO_PINx); + gpio_mode_set(UART7_GPIOx, GPIO_MODE_AF, GPIO_PUPD_PULLUP, UART7_TX_GPIO_PINx); + gpio_output_options_set(UART7_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, UART7_TX_GPIO_PINx); + gpio_af_set(UART7_GPIOx, UART7_GPIO_AFx, UART7_RX_GPIO_PINx); + gpio_mode_set(UART7_GPIOx, GPIO_MODE_AF, GPIO_PUPD_PULLUP, UART7_RX_GPIO_PINx); + gpio_output_options_set(UART7_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, UART7_RX_GPIO_PINx); break; #endif default: @@ -259,8 +259,8 @@ void _gpio_init(const uint32_t usart_periph) { #endif void gd32_uart_begin(const uint32_t usart_periph, uint32_t baudrate, uint32_t bits, uint32_t parity, uint32_t stop_bits) { - _rcu_periph_clock_enable(usart_periph); - _gpio_init(usart_periph); + rcu_config(usart_periph); + gpio_config(usart_periph); usart_deinit(usart_periph); @@ -307,7 +307,11 @@ void gd32_uart_transmit(const uint32_t usart_periph, const uint8_t *data, uint32 while (length-- != 0) { while (RESET == usart_flag_get(usart_periph, USART_FLAG_TBE)) ; - USART_DATA(usart_periph) = ((uint16_t) USART_DATA_DATA & *data++); +#if defined (GD32H7XX) + USART_TDATA(usart_periph) = USART_TDATA_TDATA & (uint32_t)*data++; +#else + USART_DATA(usart_periph) = (USART_DATA_DATA & *data++); +#endif } } @@ -318,6 +322,10 @@ void gd32_uart_transmit_string(const uint32_t usart_periph, const char *data) { while (*data != '\0') { while (RESET == usart_flag_get(USART0, USART_FLAG_TBE)) ; - USART_DATA(usart_periph) = ((uint16_t) USART_DATA_DATA & *data++); +#if defined (GD32H7XX) + USART_TDATA(usart_periph) = USART_TDATA_TDATA & (uint32_t)*data++; +#else + USART_DATA(usart_periph) = (USART_DATA_DATA & *data++); +#endif } } diff --git a/lib-gd32/src/mac_address.cpp b/lib-gd32/src/mac_address.cpp index fe9b2d40..0306485c 100644 --- a/lib-gd32/src/mac_address.cpp +++ b/lib-gd32/src/mac_address.cpp @@ -2,7 +2,7 @@ * @file mac_address.cpp * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,12 +29,15 @@ #include "debug.h" void mac_address_get(uint8_t paddr[]) { -#if !defined (GD32F4XX) - const auto mac_hi = *(volatile uint32_t *) (0x1FFFF7E8); - const auto mac_lo = *(volatile uint32_t *) (0x1FFFF7EC); -#else +#if defined (GD32H7XX) + const auto mac_hi = *(volatile uint32_t *) (0x1FF0F7E8); + const auto mac_lo = *(volatile uint32_t *) (0x1FF0F7EC); +#elif defined (GD32F4XX) const auto mac_hi = *(volatile uint32_t *) (0x1FFF7A10); const auto mac_lo = *(volatile uint32_t *) (0x1FFF7A14); +#else + const auto mac_hi = *(volatile uint32_t *) (0x1FFFF7E8); + const auto mac_lo = *(volatile uint32_t *) (0x1FFFF7EC); #endif paddr[0] = 2; diff --git a/lib-gd32/src/ptp/gd32_ptp.cpp b/lib-gd32/src/ptp/gd32_ptp.cpp new file mode 100644 index 00000000..a027d5c0 --- /dev/null +++ b/lib-gd32/src/ptp/gd32_ptp.cpp @@ -0,0 +1,183 @@ +/** + * @file gd32_ptp.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include +#include + +#include "gd32_ptp.h" +#include "gd32.h" + +#include "debug.h" + +extern "C" void console_error(const char *); + +#if defined (GD32H7XX) +# define enet_interrupt_disable(x) enet_interrupt_disable(ENETx, x) +# define enet_ptp_feature_enable(x) enet_ptp_feature_enable(ENETx, x) +# define enet_ptp_subsecond_increment_config(x) enet_ptp_subsecond_increment_config(ENETx, x) +# define enet_ptp_timestamp_function_config(x) enet_ptp_timestamp_function_config(ENETx, x) +# define enet_ptp_timestamp_addend_config(x) enet_ptp_timestamp_addend_config(ENETx, x) +# define enet_ptp_timestamp_update_config(x,y,z) enet_ptp_timestamp_update_config(ENETx, x, y, z) +# define enet_ptp_system_time_get(x) enet_ptp_system_time_get(ENETx, x) +static FlagStatus enet_ptpflagstatus_get(const uint32_t flag) { + FlagStatus bitstatus = RESET; + + if (0 != (ENET_PTP_TSCTL(ENETx) & flag)) { + bitstatus = SET; + } + + return bitstatus; +} +#else +static FlagStatus enet_ptpflagstatus_get(const uint32_t flag) { + FlagStatus bitstatus = RESET; + + if (0 != (ENET_PTP_TSCTL & flag)) { + bitstatus = SET; + } + + return bitstatus; +} +#endif + +static void ptp_start(const uint32_t init_sec, const uint32_t init_subsec, [[maybe_unused]] const uint32_t carry_cfg, const uint32_t accuracy_cfg) { + DEBUG_ENTRY + + enet_interrupt_disable(ENET_MAC_INT_TMSTIM); + +#if defined(GD32F4XX) || defined (GD32H7XX) + enet_ptp_feature_enable(ENET_ALL_RX_TIMESTAMP | ENET_RXTX_TIMESTAMP); +#else + enet_ptp_feature_enable(ENET_RXTX_TIMESTAMP); +#endif + enet_ptp_subsecond_increment_config(accuracy_cfg); + + enet_ptp_timestamp_addend_config(carry_cfg); + + enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); + while(enet_ptpflagstatus_get(ENET_PTP_ADDEND_UPDATE) == SET); + + enet_ptp_timestamp_function_config(ENET_PTP_FINEMODE); + + enet_ptp_timestamp_update_config(ENET_PTP_ADD_TO_TIME, init_sec, init_subsec); + enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT); + while(enet_ptpflagstatus_get(ENET_PTP_SYSTIME_INIT) == SET); + + DEBUG_EXIT +} + +void gd32_ptp_start() { + DEBUG_ENTRY + DEBUG_PRINTF("PTP_TICK=%u", gd32::ptp::PTP_TICK); + DEBUG_PRINTF("ADJ_FREQ_BASE_INCREMENT=%u", gd32::ptp::ADJ_FREQ_BASE_INCREMENT); + DEBUG_PRINTF("ADJ_FREQ_BASE_ADDEND=x%X", gd32::ptp::ADJ_FREQ_BASE_ADDEND); + + struct tm tmbuf; + memset(&tmbuf, 0, sizeof(struct tm)); + tmbuf.tm_mday = _TIME_STAMP_DAY_; // The day of the month, in the range 1 to 31. + tmbuf.tm_mon = _TIME_STAMP_MONTH_ - 1; // The number of months since January, in the range 0 to 11. + tmbuf.tm_year = _TIME_STAMP_YEAR_ - 1900; // The number of years since 1900. + + ptp_start(mktime(&tmbuf), 0, gd32::ptp::ADJ_FREQ_BASE_ADDEND, gd32::ptp::ADJ_FREQ_BASE_INCREMENT); + +#ifndef NDEBUG + struct timeval tv; + gettimeofday(&tv, nullptr); + auto *tm = localtime(&tv.tv_sec); + + DEBUG_PRINTF("%.2d-%.2d-%.4d %.2d:%.2d:%.2d.%.6d", tm->tm_mday, tm->tm_mon + 1, tm->tm_year + 1900, tm->tm_hour, tm->tm_min, tm->tm_sec, static_cast(tv.tv_usec)); +#endif + DEBUG_EXIT +} + +void gd32_ptp_get_time(gd32::ptp::ptptime *ptp_time) { + enet_ptp_systime_struct systime; + + enet_ptp_system_time_get(&systime); + + ptp_time->tv_sec = systime.second; +#if !defined (GD32F4XX) + ptp_time->tv_nsec = systime.nanosecond; +#else + ptp_time->tv_nsec = gd32::ptp_subsecond_2_nanosecond(systime.subsecond); +#endif +} + +void gd32_ptp_set_time(const gd32::ptp::ptptime *ptp_time) { + const auto nSign = ENET_PTP_ADD_TO_TIME; + const auto nSecond = ptp_time->tv_sec; + const auto nNanoSecond = ptp_time->tv_nsec; + const auto nSubSecond = gd32::ptp_nanosecond_2_subsecond(nNanoSecond); + + enet_ptp_timestamp_update_config(nSign, nSecond, nSubSecond); + enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT); + while(enet_ptpflagstatus_get(ENET_PTP_SYSTIME_INIT) == SET); +} + +void gd32_ptp_update_time(const gd32::ptp::time_t *pTime) { + uint32_t nSign; + uint32_t nSecond; + uint32_t nNanoSecond; + + if (pTime->tv_sec < 0 || (pTime->tv_sec == 0 && pTime->tv_nsec < 0)) { + nSign = ENET_PTP_SUBSTRACT_FROM_TIME; + nSecond = -pTime->tv_sec; + nNanoSecond = -pTime->tv_nsec; + } else { + nSign = ENET_PTP_ADD_TO_TIME; + nSecond = pTime->tv_sec; + nNanoSecond = pTime->tv_nsec; + } + + const auto nSubSecond = gd32::ptp_nanosecond_2_subsecond(nNanoSecond); +#if defined (GD32H7XX) + const auto nAddend = ENET_PTP_TSADDEND(ENETx); +#else + const auto nAddend = ENET_PTP_TSADDEND; +#endif + + enet_ptp_timestamp_update_config(nSign, nSecond, nSubSecond); + enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_UPDATE); + while(enet_ptpflagstatus_get(ENET_PTP_SYSTIME_UPDATE) == SET); + + enet_ptp_timestamp_addend_config(nAddend); + enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); +} + +bool gd32_adj_frequency(const int32_t adjust_ppb) { + const uint32_t addend = gd32::ptp::ADJ_FREQ_BASE_ADDEND + static_cast((((static_cast(gd32::ptp::ADJ_FREQ_BASE_ADDEND)) * adjust_ppb) / 1000000000ULL)); + + enet_ptp_timestamp_addend_config(addend); + + const auto reval = enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); + + if (reval == ERROR) { + console_error("enet_ptp_timestamp_addend_config\n"); + } + + return reval != ERROR; +} diff --git a/lib-gd32/src/softuart0/gd32_uart0.c b/lib-gd32/src/softuart0/gd32_uart0.c deleted file mode 100644 index 7f8dee8c..00000000 --- a/lib-gd32/src/softuart0/gd32_uart0.c +++ /dev/null @@ -1,189 +0,0 @@ -/** - * @file gd32_uart0.c - * - */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#if defined (NDEBUG) -# undef NDEBUG -#endif - -#include -#include -#include - -#include "gd32.h" - -#if !defined (SOFTUART_TX_PINx) -# define SOFTUART_TX_PINx GPIO_PIN_9 -# define SOFTUART_TX_GPIOx GPIOA -# define SOFTUART_TX_RCU_GPIOx RCU_GPIOA -#endif - -#if defined (GD32F4XX) -# define TIMER_CLOCK (APB2_CLOCK_FREQ * 2) -#else -# define TIMER_CLOCK (APB2_CLOCK_FREQ) -#endif - -#define BAUD_RATE (115200U) -#define TIMER_PERIOD ((TIMER_CLOCK / BAUD_RATE) - 1U) -#define BUFFER_SIZE (128U) - -typedef enum { - SOFTUART_IDLE, - SOFTUART_START_BIT, - SOFTUART_DATA, - SOFTUART_STOP_BIT, -} softuart_state; - -struct circular_buffer { - uint8_t buffer[BUFFER_SIZE]; - uint32_t head; - uint32_t tail; - bool full; -}; - -static volatile softuart_state s_state; -static volatile struct circular_buffer s_circular_buffer; -static volatile uint8_t s_data; -static volatile uint8_t s_shift; - -static bool is_circular_buffer_empty() { - return (!s_circular_buffer.full && (s_circular_buffer.head == s_circular_buffer.tail)); -} - -void TIMER0_UP_TIMER9_IRQHandler() { - GPIO_BOP(LED3_GPIOx) = LED3_GPIO_PINx; - - switch (s_state) { - case SOFTUART_IDLE: - break; - case SOFTUART_START_BIT: - GPIO_BC(SOFTUART_TX_GPIOx) = SOFTUART_TX_PINx; - - s_state = SOFTUART_DATA; - s_data = s_circular_buffer.buffer[s_circular_buffer.tail]; - s_circular_buffer.tail = (s_circular_buffer.tail + 1) & (BUFFER_SIZE - 1); - s_circular_buffer.full = false; - s_shift = 0; - break; - case SOFTUART_DATA: - if (s_data & (1U << s_shift)) { - GPIO_BOP(SOFTUART_TX_GPIOx) = SOFTUART_TX_PINx; - } else { - GPIO_BC(SOFTUART_TX_GPIOx) = SOFTUART_TX_PINx; - } - - s_shift++; - - if (s_shift == 8) { - s_state = SOFTUART_STOP_BIT; - } - break; - case SOFTUART_STOP_BIT: - GPIO_BOP(SOFTUART_TX_GPIOx) = SOFTUART_TX_PINx; - - if (is_circular_buffer_empty()) { - s_state = SOFTUART_IDLE; - timer_disable(TIMER9); - } else { - s_state = SOFTUART_START_BIT; - } - break; - default: - break; - } - - timer_interrupt_flag_clear(TIMER9, TIMER_INT_FLAG_UP); - - GPIO_BC(LED3_GPIOx) = LED3_GPIO_PINx; -} - -void uart0_init() { - rcu_periph_clock_enable (LED3_RCU_GPIOx); -#if !defined (GD32F4XX) - gpio_init(LED3_GPIOx, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, LED3_GPIO_PINx); -#else - gpio_mode_set(LED3_GPIOx, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLDOWN, LED3_GPIO_PINx); - gpio_output_options_set(LED3_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, LED3_GPIO_PINx); - gpio_af_set(LED3_GPIOx, GPIO_AF_0, LED3_GPIO_PINx); -#endif - - GPIO_BC(LED3_GPIOx) = LED3_GPIO_PINx; - - rcu_periph_clock_enable (SOFTUART_TX_RCU_GPIOx); - -#if !defined (GD32F4XX) - gpio_init(SOFTUART_TX_GPIOx, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, SOFTUART_TX_PINx); -#else - gpio_mode_set(SOFTUART_TX_GPIOx, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLDOWN, SOFTUART_TX_PINx); - gpio_output_options_set(SOFTUART_TX_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, SOFTUART_TX_PINx); - gpio_af_set(SOFTUART_TX_GPIOx, GPIO_AF_0, SOFTUART_TX_PINx); -#endif - - GPIO_BOP(SOFTUART_TX_GPIOx) = SOFTUART_TX_PINx; - - rcu_periph_clock_enable(RCU_TIMER9); - - timer_deinit(TIMER9); - - timer_parameter_struct timer_initpara; - timer_initpara.prescaler = 0; - timer_initpara.alignedmode = TIMER_COUNTER_EDGE; - timer_initpara.counterdirection = TIMER_COUNTER_UP; - timer_initpara.period = TIMER_PERIOD; - timer_initpara.clockdivision = TIMER_CKDIV_DIV1; - - timer_init(TIMER9, &timer_initpara); - - timer_flag_clear(TIMER9, ~0); - timer_interrupt_flag_clear(TIMER9, ~0); - - timer_interrupt_enable(TIMER9, TIMER_INT_UP); - - NVIC_SetPriority(TIMER0_UP_TIMER9_IRQn, 2); - NVIC_EnableIRQ(TIMER0_UP_TIMER9_IRQn); -} - -static void _putc(int c) { - while (s_circular_buffer.full) - ; - - s_circular_buffer.buffer[s_circular_buffer.head] = (uint8_t) c; - s_circular_buffer.head = (s_circular_buffer.head + 1) & (BUFFER_SIZE - 1); - s_circular_buffer.full = s_circular_buffer.head == s_circular_buffer.tail; - - if (s_state == SOFTUART_IDLE) { - timer_counter_value_config(TIMER9, 0); - timer_enable(TIMER9); - s_state = SOFTUART_START_BIT; - } -} - -void uart0_putc(int c) { - if (c == '\n') { - _putc('\r'); - } - - _putc(c); -} diff --git a/lib-gd32/src/softuart0/uart0.cpp b/lib-gd32/src/softuart0/uart0.cpp new file mode 100644 index 00000000..14027731 --- /dev/null +++ b/lib-gd32/src/softuart0/uart0.cpp @@ -0,0 +1,234 @@ +/** + * @file uart0.c + * + */ +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#if !defined (CONFIG_REMOTECONFIG_MINIMUM) +# pragma GCC push_options +# pragma GCC optimize ("O2") +#endif + +#include +#include + +#include "gd32.h" + +#include "debug.h" + +#if defined (GD32H7XX) +# define TIMERx TIMER15 +# define RCU_TIMERx RCU_TIMER15 +# define TIMERx_IRQHandler TIMER15_IRQHandler +# define TIMERx_IRQn TIMER15_IRQn +#else +# define TIMERx TIMER9 +# define RCU_TIMERx RCU_TIMER9 +# define TIMERx_IRQHandler TIMER0_UP_TIMER9_IRQHandler +# define TIMERx_IRQn TIMER0_UP_TIMER9_IRQn +#endif + +#if defined (GD32H7XX) +# define TIMER_CLOCK_FREQ (AHB_CLOCK_FREQ) +#elif defined (GD32F4XX) +# define TIMER_CLOCK_FREQ (APB2_CLOCK_FREQ * 2) +#else +# define TIMER_CLOCK_FREQ (APB2_CLOCK_FREQ) +#endif + +#if !defined (SOFTUART_TX_PINx) +# define SOFTUART_TX_PINx GPIO_PIN_9 +# define SOFTUART_TX_GPIOx GPIOA +# define SOFTUART_TX_RCU_GPIOx RCU_GPIOA +#endif + +#define BAUD_RATE (115200U) +#define TIMER_PERIOD ((TIMER_CLOCK_FREQ / BAUD_RATE) - 1U) +#define BUFFER_SIZE (128U) + +typedef enum { + SOFTUART_IDLE, SOFTUART_START_BIT, SOFTUART_DATA, SOFTUART_STOP_BIT, +} softuart_state; + +struct circular_buffer { + uint8_t buffer[BUFFER_SIZE]; + uint32_t head; + uint32_t tail; + bool full; +}; + +static volatile softuart_state s_state; +static volatile struct circular_buffer s_circular_buffer; +static volatile uint8_t s_data; +static volatile uint8_t s_shift; + +static bool is_circular_buffer_empty() { + return (!s_circular_buffer.full && (s_circular_buffer.head == s_circular_buffer.tail)); +} + +extern "C" { +void TIMERx_IRQHandler() { + const auto nIntFlag = TIMER_INTF(TIMERx); + + if ((nIntFlag & TIMER_INT_FLAG_UP) == TIMER_INT_FLAG_UP) { +#if defined (LED3_GPIO_PINx) + GPIO_BOP(LED3_GPIOx) = LED3_GPIO_PINx; +#endif + + switch (s_state) { + case SOFTUART_IDLE: + break; + case SOFTUART_START_BIT: + GPIO_BC(SOFTUART_TX_GPIOx) = SOFTUART_TX_PINx; + + s_state = SOFTUART_DATA; + s_data = s_circular_buffer.buffer[s_circular_buffer.tail]; + s_circular_buffer.tail = (s_circular_buffer.tail + 1) & (BUFFER_SIZE - 1); + s_circular_buffer.full = false; + s_shift = 0; + break; + case SOFTUART_DATA: + if (s_data & (1U << s_shift)) { + GPIO_BOP(SOFTUART_TX_GPIOx) = SOFTUART_TX_PINx; + } else { + GPIO_BC(SOFTUART_TX_GPIOx) = SOFTUART_TX_PINx; + } + + s_shift++; + + if (s_shift == 8) { + s_state = SOFTUART_STOP_BIT; + } + break; + case SOFTUART_STOP_BIT: + GPIO_BOP(SOFTUART_TX_GPIOx) = SOFTUART_TX_PINx; + + if (is_circular_buffer_empty()) { + s_state = SOFTUART_IDLE; + timer_disable(TIMERx); + } else { + s_state = SOFTUART_START_BIT; + } + break; + default: + break; + } + +#if defined (LED3_GPIO_PINx) + GPIO_BC(LED3_GPIOx) = LED3_GPIO_PINx; +#endif + } + + TIMER_INTF(TIMERx) = static_cast(~nIntFlag); +} + +void uart0_init() { + s_state = SOFTUART_IDLE; + s_circular_buffer.head = 0; + s_circular_buffer.tail = 0; + s_circular_buffer.full = false; + +#if defined (LED3_GPIO_PINx) + rcu_periph_clock_enable (LED3_RCU_GPIOx); +# if defined (GPIO_INIT) + gpio_init(LED3_GPIOx, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, LED3_GPIO_PINx); +# else + gpio_mode_set(LED3_GPIOx, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLDOWN, LED3_GPIO_PINx); + gpio_output_options_set(LED3_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, LED3_GPIO_PINx); +# endif + + GPIO_BC(LED3_GPIOx) = LED3_GPIO_PINx; +#endif + + rcu_periph_clock_enable (SOFTUART_TX_RCU_GPIOx); + +#if defined (GPIO_INIT) + gpio_init(SOFTUART_TX_GPIOx, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, SOFTUART_TX_PINx); +#else + gpio_mode_set(SOFTUART_TX_GPIOx, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLDOWN, SOFTUART_TX_PINx); + gpio_output_options_set(SOFTUART_TX_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, SOFTUART_TX_PINx); +#endif + + GPIO_BOP(SOFTUART_TX_GPIOx) = SOFTUART_TX_PINx; + + rcu_periph_clock_enable(RCU_TIMERx); + + timer_deinit(TIMERx); + + timer_parameter_struct timer_initpara; + timer_struct_para_init(&timer_initpara); + + timer_initpara.prescaler = 0; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = TIMER_PERIOD; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + + timer_init(TIMERx, &timer_initpara); + + timer_flag_clear(TIMERx, ~0); + timer_interrupt_flag_clear(TIMERx, ~0); + + timer_interrupt_enable(TIMERx, TIMER_INT_UP); + + NVIC_SetPriority(TIMERx_IRQn, 2); + NVIC_EnableIRQ(TIMERx_IRQn); +} + +static void _putc(const int c) { + //FIXME deadlock when timer is not running + while (s_circular_buffer.full) + ; + + s_circular_buffer.buffer[s_circular_buffer.head] = (uint8_t) c; + s_circular_buffer.head = (s_circular_buffer.head + 1) & (BUFFER_SIZE - 1); + s_circular_buffer.full = s_circular_buffer.head == s_circular_buffer.tail; + + if (s_state == SOFTUART_IDLE) { + timer_counter_value_config(TIMERx, 0); + timer_enable(TIMERx); + s_state = SOFTUART_START_BIT; + } +} + +void uart0_putc(int c) { + if (c == '\n') { + _putc('\r'); + } + + _putc(c); +} + +void uart0_puts(const char *s) { + while (*s != '\0') { + if (*s == '\n') { + uart0_putc('\r'); + } + uart0_putc(*s++); + } + + do { + __DMB(); + } while (!is_circular_buffer_empty()); +} +} diff --git a/lib-gd32/src/systick.c b/lib-gd32/src/systick/systick.cpp similarity index 77% rename from lib-gd32/src/systick.c rename to lib-gd32/src/systick/systick.cpp index 2e9e6722..f269c586 100644 --- a/lib-gd32/src/systick.c +++ b/lib-gd32/src/systick/systick.cpp @@ -2,7 +2,7 @@ * @file systick.c * */ -/* Copyright (C) 2021 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,23 +23,24 @@ * THE SOFTWARE. */ -#include +#include #include "gd32.h" -volatile uint32_t s_nSysTickMillis; +volatile uint32_t gv_nSysTickMillis; -void systick_config(void) { - /* setup systick timer for 1000Hz interrupts */ +extern "C" { +void systick_config() { + /* Setup systick timer for 1000Hz interrupts */ if (SysTick_Config(SystemCoreClock / 1000U)) { - /* capture error */ while (1) { } } - /* configure the systick handler priority */ - NVIC_SetPriority(SysTick_IRQn, 0x00U); + + NVIC_SetPriority(SysTick_IRQn, (1UL<<__NVIC_PRIO_BITS)-1UL); // Lowest priority } -void SysTick_Handler(void) { - s_nSysTickMillis++; +void SysTick_Handler() { + gv_nSysTickMillis++; +} } diff --git a/lib-gd32/src/timer6.cpp b/lib-gd32/src/timer6.cpp new file mode 100644 index 00000000..0cbf908b --- /dev/null +++ b/lib-gd32/src/timer6.cpp @@ -0,0 +1,86 @@ +/** + * @file timer6.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#pragma GCC push_options +#pragma GCC optimize ("O2") + +#include "gd32.h" + +struct HwTimersSeconds g_Seconds; + +extern "C" { +#if defined (CONFIG_TIMER6_HAVE_NO_IRQ_HANDLER) +void TIMER6_IRQHandler() { + const auto nIntFlag = TIMER_INTF(TIMER6); + + if ((nIntFlag & TIMER_INT_FLAG_UP) == TIMER_INT_FLAG_UP) { + g_Seconds.nUptime++; + } + + TIMER_INTF(TIMER6) = static_cast(~nIntFlag); +} +#endif +} + +void timer6_config() { + g_Seconds.nUptime = 0; + + rcu_periph_clock_enable(RCU_TIMER6); + timer_deinit(TIMER6); + + timer_parameter_struct timer_initpara; + timer_struct_para_init(&timer_initpara); + + timer_initpara.prescaler = TIMER_PSC_10KHZ; + timer_initpara.period = (10000 - 1); // 1 second + timer_init(TIMER6, &timer_initpara); + + timer_counter_value_config(TIMER6, 0); + + timer_interrupt_flag_clear(TIMER6, ~0); + + timer_interrupt_enable(TIMER6, TIMER_INT_UP); + + NVIC_SetPriority(TIMER6_IRQn, (1UL<<__NVIC_PRIO_BITS)-1UL); // Lowest priority + NVIC_EnableIRQ(TIMER6_IRQn); + + timer_enable(TIMER6); +} + +uint32_t timer6_get_elapsed_milliseconds() { + const auto nUptimeFirst = g_Seconds.nUptime; + auto nTimerCount = TIMER_CNT(TIMER6); + const auto nUptimeSecond = g_Seconds.nUptime; + + // Check for consistency + if (__builtin_expect((nUptimeFirst == nUptimeSecond), 1)) { + // No overflow detected, return the calculated time + return (nUptimeFirst * 1000U) + (nTimerCount / 10U); + } + + // Potential overflow detected, re-read the timer count + nTimerCount = TIMER_CNT(TIMER6); + return (nUptimeSecond * 1000U) + (nTimerCount / 10U); +} diff --git a/lib-gd32/src/gd32_uart0.c b/lib-gd32/src/uart0.cpp similarity index 81% rename from lib-gd32/src/gd32_uart0.c rename to lib-gd32/src/uart0.cpp index 17335bda..7562f3b3 100644 --- a/lib-gd32/src/gd32_uart0.c +++ b/lib-gd32/src/uart0.cpp @@ -1,8 +1,8 @@ /** - * @file gd32_uart0.c + * @file uart0.cpp * */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,23 +23,13 @@ * THE SOFTWARE. */ -#include -#include - -extern void uart0_putc(int); +#include +#include static char s_buffer[128]; -void uart0_puts(const char *s) { - while (*s != '\0') { - if (*s == '\n') { - uart0_putc('\r'); - } - uart0_putc(*s++); - } - -// uart0_putc('\n'); //TODO Add '\n' -} +extern "C" { +void uart0_putc(int); int uart0_printf(const char *fmt, ...) { va_list arp; @@ -61,3 +51,4 @@ int uart0_printf(const char *fmt, ...) { return i; } +} diff --git a/lib-gd32/src/uart0/gd32_uart0.c b/lib-gd32/src/uart0/uart0.cpp similarity index 66% rename from lib-gd32/src/uart0/gd32_uart0.c rename to lib-gd32/src/uart0/uart0.cpp index e7c531fa..4adcc136 100644 --- a/lib-gd32/src/uart0/gd32_uart0.c +++ b/lib-gd32/src/uart0/uart0.cpp @@ -1,8 +1,8 @@ /** - * @file gd32_uart0.c + * @file uart0.cpp * */ -/* Copyright (C) 2021 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,12 +23,13 @@ * THE SOFTWARE. */ -#include -#include +#include +#include #include "gd32.h" #include "gd32_uart.h" +extern "C" { void uart0_init(void) { gd32_uart_begin(USART0, 115200U, GD32_UART_BITS_8, GD32_UART_PARITY_NONE, GD32_UART_STOP_1BIT); } @@ -37,11 +38,46 @@ void uart0_putc(int c) { if (c == '\n') { while (RESET == usart_flag_get(USART0, USART_FLAG_TBE)) ; +#if defined (GD32H7XX) + USART_TDATA(USART0) = USART_TDATA_TDATA & (uint32_t)'\r'; +#else USART_DATA(USART0) = ((uint16_t) USART_DATA_DATA & (uint8_t) '\r'); +#endif } while (RESET == usart_flag_get(USART0, USART_FLAG_TBE)) ; - +#if defined (GD32H7XX) + USART_TDATA(USART0) = USART_TDATA_TDATA & (uint32_t) c; +#else USART_DATA(USART0) = ((uint16_t) USART_DATA_DATA & (uint8_t) c); +#endif +} + +void uart0_puts(const char *s) { + while (*s != '\0') { + if (*s == '\n') { + uart0_putc('\r'); + } + uart0_putc(*s++); + } +} + +int uart0_getc(void) { + if (__builtin_expect((!gd32_usart_flag_get(USART0)), 1)) { + return EOF; + } + +#if defined (GD32H7XX) + const auto c = static_cast(USART_RDATA(USART0)); +#else + const auto c = static_cast(USART_DATA(USART0)); +#endif + +#if defined (UART0_ECHO) + uart0_putc(c); +#endif + + return c; +} } diff --git a/lib-gd32/src/udelay.cpp b/lib-gd32/src/udelay.cpp index 81cb713e..737780d3 100644 --- a/lib-gd32/src/udelay.cpp +++ b/lib-gd32/src/udelay.cpp @@ -2,7 +2,7 @@ * @file udelay.cpp * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,9 +28,9 @@ #include "gd32.h" -static constexpr auto TICKS_PER_US = (MCU_CLOCK_FREQ / 1000000U); +static constexpr uint32_t TICKS_PER_US = (MCU_CLOCK_FREQ / 1000000U); -void udelay_init(void) { +void udelay_init() { assert(MCU_CLOCK_FREQ == SystemCoreClock); CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; @@ -38,21 +38,20 @@ void udelay_init(void) { DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; } -void udelay(uint32_t nUs, uint32_t nOffsetCYCCNT) { - const auto nTicks = nUs * TICKS_PER_US; +void udelay(uint32_t nMicros, uint32_t nOffsetMicros) { + const auto nTicks = nMicros * TICKS_PER_US; uint32_t nTicksCount = 0; - uint32_t nTicksNow; uint32_t nTicksPrevious; - if (nOffsetCYCCNT == 0) { + if (nOffsetMicros == 0) { nTicksPrevious = DWT->CYCCNT; } else { - nTicksPrevious = nOffsetCYCCNT; + nTicksPrevious = nOffsetMicros; } while (1) { - nTicksNow = DWT->CYCCNT; + const auto nTicksNow = DWT->CYCCNT; if (nTicksNow != nTicksPrevious) { if (nTicksNow > nTicksPrevious) { diff --git a/lib-hal/.cproject b/lib-hal/.cproject index 707bf5ad..8f1d9807 100644 --- a/lib-hal/.cproject +++ b/lib-hal/.cproject @@ -30,11 +30,9 @@ - diff --git a/lib-hal/.settings/language.settings.xml b/lib-hal/.settings/language.settings.xml index e0cd2023..f2f25c89 100644 --- a/lib-hal/.settings/language.settings.xml +++ b/lib-hal/.settings/language.settings.xml @@ -2,7 +2,10 @@ - + + + + diff --git a/lib-hal/.settings/org.eclipse.ltk.core.refactoring.prefs b/lib-hal/.settings/org.eclipse.ltk.core.refactoring.prefs new file mode 100644 index 00000000..b196c64a --- /dev/null +++ b/lib-hal/.settings/org.eclipse.ltk.core.refactoring.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.ltk.core.refactoring.enable.project.refactoring.history=false diff --git a/lib-hal/Makefile.GD32 b/lib-hal/Makefile.GD32 index a03d2caa..449d03ef 100644 --- a/lib-hal/Makefile.GD32 +++ b/lib-hal/Makefile.GD32 @@ -1,26 +1,39 @@ DEFINES=NDEBUG -ifneq ($(MAKE_FLAGS),) - ifeq ($(findstring USE_LEDBLINK_BITBANGING595,$(MAKE_FLAGS)), USE_LEDBLINK_BITBANGING595) - EXTRA_SRCDIR=src/gd32/bitbanging +EXTRA_SRCDIR= + +ifneq ($(MAKE_FLAGS),) + ifeq (,$(findstring DISABLE_RTC,$(MAKE_FLAGS))) + ifeq (,$(findstring DISABLE_INTERNAL_RTC,$(MAKE_FLAGS))) + EXTRA_SRCDIR+=rtc/gd32 + endif + endif + + ifeq ($(findstring ENABLE_USB_HOST,$(MAKE_FLAGS)), ENABLE_USB_HOST) + ifeq ($(findstring gd32h7xx,$(FAMILY)), gd32h7xx) + EXTRA_SRCDIR+=device/usb/host/gd32/h + EXTRA_INCLUDES+=device/usb/host/gd32/h + else + EXTRA_SRCDIR+=device/usb/host/gd32/f + EXTRA_INCLUDES+=device/usb/host/gd32/f + endif + EXTRA_SRCDIR+=device/usb/host/gd32 + EXTRA_INCLUDES+=device/usb/host/gd32 endif - - ifneq (,$(findstring DEBUG_EMAC,$(MAKE_FLAGS))) + + ifneq (,$(findstring DEBUG_EMAC,$(MAKE_FLAGS))) EXTRA_SRCDIR+=debug/emac/gd32 endif - - ifeq ($(findstring ENABLE_USB_HOST,$(MAKE_FLAGS)), ENABLE_USB_HOST) - EXTRA_SRCDIR+=device/usb/host/gd32 - EXTRA_INCLUDES+=device/usb/host/gd32 - endif else - EXTRA_SRCDIR+=debug/emac/gd32 - EXTRA_SRCDIR+=ff12c ff12c/option - - EXTRA_SRCDIR+=device/usb/host/gd32 - EXTRA_INCLUDES+=device/usb/host/gd32 + ifneq (, $(shell test -d '../lib-network/src/noemac' && echo -n yes)) + else + EXTRA_SRCDIR+=debug/emac/gd32 + endif + EXTRA_SRCDIR+=rtc/gd32 +# EXTRA_SRCDIR+=device/usb/host/gd32 +# EXTRA_INCLUDES+=device/usb/host/gd32 - DEFINES=ENABLE_USB_HOST CONFIG_USB_HOST_MSC +# DEFINES=ENABLE_USB_HOST CONFIG_USB_HOST_MSC endif include Rules.mk diff --git a/lib-hal/Rules.mk b/lib-hal/Rules.mk old mode 100644 new mode 100755 index cea16ff8..0ae3fcec --- a/lib-hal/Rules.mk +++ b/lib-hal/Rules.mk @@ -1,5 +1,7 @@ $(info $$MAKE_FLAGS [${MAKE_FLAGS}]) +EXTRA_SRCDIR+=debug + ifneq ($(MAKE_FLAGS),) ifneq (,$(findstring CONSOLE_I2C,$(MAKE_FLAGS))) EXTRA_SRCDIR+=console/i2c @@ -14,23 +16,43 @@ ifneq ($(MAKE_FLAGS),) endif endif endif - ifneq ($(findstring DISABLE_RTC,$(MAKE_FLAGS)), DISABLE_RTC) + + FATFS= + ifeq ($(findstring CONFIG_USB_HOST_MSC,$(MAKE_FLAGS)), CONFIG_USB_HOST_MSC) + FATFS=1 + endif + + ifeq (,$(findstring DISABLE_FS,$(MAKE_FLAGS))) + FATFS=1 + endif + + ifdef FATFS + EXTRA_SRCDIR+=ff14b/source + EXTRA_SRCDIR+=posix + endif + + ifeq (,$(findstring DISABLE_RTC,$(MAKE_FLAGS))) EXTRA_SRCDIR+=rtc - ifeq ($(findstring DISABLE_INTERNAL_RTC,$(MAKE_FLAGS)), DISABLE_INTERNAL_RTC) + ifneq (,$(findstring DISABLE_INTERNAL_RTC,$(MAKE_FLAGS))) EXTRA_SRCDIR+=rtc/i2c - else - EXTRA_SRCDIR+=rtc/gd32 endif + EXTRA_INCLUDES+=../lib-properties/include endif + ifneq (,$(findstring DEBUG_I2C,$(MAKE_FLAGS))) EXTRA_SRCDIR+=debug/i2c EXTRA_INCLUDES+=debug/i2c endif + ifneq (,$(findstring DEBUG_STACK,$(MAKE_FLAGS))) EXTRA_SRCDIR+=debug/stack endif else - DEFINES+=DEBUG_I2C DEBUG_STACK - EXTRA_INCLUDES+=debug/i2c - EXTRA_SRCDIR+=console/i2c console/null console/uart0 rtc debug/stack debug/i2c + DEFINES+=DEBUG_I2C DEBUG_STACK DEBUG_POSIX + DEFINES+=LOGIC_ANALYZER + EXTRA_INCLUDES+=debug/i2c debug/stack + EXTRA_SRCDIR+=console/i2c console/null console/uart0 + EXTRA_SRCDIR+=posix + EXTRA_SRCDIR+=rtc rtc/i2c + EXTRA_INCLUDES+=../lib-properties/include endif diff --git a/lib-hal/console/h3/console.c b/lib-hal/console/h3/console.c deleted file mode 100644 index 809a5bef..00000000 --- a/lib-hal/console/h3/console.c +++ /dev/null @@ -1,381 +0,0 @@ -/** - * @file console.c - * - */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include - -#include "console.h" - -#include "device/fb.h" - -#include "arm/arm.h" - -extern unsigned char FONT[] __attribute__((aligned(4))); - -static const uint32_t FB_CHAR_W = 8; -static const uint32_t FB_CHAR_H = 16; - -static uint32_t current_x = 0; -static uint32_t current_y = 0; -static uint32_t saved_x = 0; -static uint32_t saved_y = 0; - -static uint32_t top_row = 0; - -static uint32_t cur_fore = CONSOLE_WHITE; -static uint32_t cur_back = CONSOLE_BLACK; -static uint32_t saved_fore = CONSOLE_WHITE; -static uint32_t saved_back = CONSOLE_BLACK; - -#if defined(USE_UBOOT_HDMI) -#undef FB_WIDTH -#define FB_WIDTH fb_width - -#undef FB_HEIGHT -#define FB_HEIGHT fb_height - -#undef FB_PITCH -#define FB_PITCH fb_pitch - -#undef FB_ADDRESS -#define FB_ADDRESS fb_addr -#endif - -void __attribute__((cold)) console_init(void) { - const int r = fb_init(); - - if (r == FB_OK) { - console_clear(); - } -} - -uint32_t console_get_line_width(void) { - return FB_WIDTH / FB_CHAR_W; -} - -void console_set_top_row(uint32_t row) { - if (row > FB_HEIGHT / FB_CHAR_H) { - top_row = 0; - } else { - top_row = row; - } - - current_x = 0; - current_y = row; -} - -inline static void clear_row(uint32_t *address) { - uint32_t i; - - for (i = 0 ; i < (FB_CHAR_H * FB_WIDTH) ; i++) { - *address++ = cur_back; - } -} - -inline static void newline(void) { - uint32_t i; - uint32_t *address; - uint32_t *to; - uint32_t *from; - - current_y++; - current_x = 0; - - if (current_y == FB_HEIGHT / FB_CHAR_H) { - if (top_row == 0) { - /* Pointer to row = 0 */ - to = (uint32_t *) (FB_ADDRESS); - /* Pointer to row = 1 */ - from = to + (FB_CHAR_H * FB_WIDTH); - /* Copy block from {row = 1, rows} to {row = 0, rows - 1} */ - i = ((FB_HEIGHT - FB_CHAR_H) * FB_WIDTH); - } else { - to = (uint32_t *) (FB_ADDRESS) + ((FB_CHAR_H * FB_WIDTH) * top_row); - from = to + (FB_CHAR_H * FB_WIDTH); - i = ((FB_HEIGHT - FB_CHAR_H) * FB_WIDTH - ((FB_CHAR_H * FB_WIDTH) * top_row)); - } - - memcpy_blk(to, from, i/8); - - /* Clear last row */ - address = (uint32_t *)(FB_ADDRESS) + ((FB_HEIGHT - FB_CHAR_H) * FB_WIDTH); - clear_row(address); - - current_y--; - } -} - -inline static void draw_pixel(uint32_t x, uint32_t y, uint32_t color) { - volatile uint32_t *address = (volatile uint32_t *)(FB_ADDRESS + (x * FB_BYTES_PER_PIXEL) + (y * FB_WIDTH * FB_BYTES_PER_PIXEL)); - *address = (uint32_t) color; -} - -inline static void draw_char(int c, uint32_t x, uint32_t y, uint32_t fore, uint32_t back) { - uint32_t i, j; - uint8_t line; - unsigned char *p = FONT + (c * (int) FB_CHAR_H); - - for (i = 0; i < FB_CHAR_H; i++) { - line = (uint8_t) *p++; - for (j = x; j < (FB_CHAR_W + x); j++) { - if ((line & 0x1) != 0) { - draw_pixel(j, y, fore); - } else { - draw_pixel(j, y, back); - } - line >>= 1; - } - y++; - } -} - -int console_draw_char(int ch, uint16_t x, uint16_t y, uint32_t fore, uint32_t back) { - draw_char(ch, x * FB_CHAR_W, y * FB_CHAR_H, fore, back); - return (int)ch; -} - -void console_putc(int ch) { - if (ch == (int)'\n') { - newline(); - } else if (ch == (int)'\r') { - current_x = 0; - } else if (ch == (int)'\t') { - current_x += 4; - } else { - draw_char(ch, current_x * FB_CHAR_W, current_y * FB_CHAR_H, cur_fore, cur_back); - current_x++; - if (current_x == FB_WIDTH / FB_CHAR_W) { - newline(); - } - } -} - -void console_puts(const char *s) { - char c; - while ((c = *s++) != (char) 0) { - console_putc((int) c); - } -} - -void console_write(const char *s, unsigned int n) { - char c; - - while (((c = *s++) != (char) 0) && (n-- != 0)) { - console_putc((int) c); - } -} - -void console_error(const char *s) { - uint32_t fore_current = cur_fore; - uint32_t back_current = cur_back; - - cur_fore = CONSOLE_RED; - cur_back = CONSOLE_BLACK; - - console_puts("Error <"); - console_puts((char *) s); - console_puts(">\n"); - - cur_fore = fore_current; - cur_back = back_current; -} - -void console_status(uint32_t color, const char *s) { - const uint32_t fore_current = cur_fore; - const uint32_t back_current = cur_back; - - const uint32_t s_y = current_y; - const uint32_t s_x = current_x; - - console_clear_line(29); - - cur_fore = color; - cur_back = CONSOLE_BLACK; - - console_puts((char *)s); - - current_y = s_y; - current_x = s_x; - - cur_fore = fore_current; - cur_back = back_current; -} - -#define TO_HEX(i) ((i) < 10) ? (uint8_t)'0' + (i) : (uint8_t)'A' + ((i) - (uint8_t)10) - -void console_puthex(uint8_t data) { - console_putc((int) (TO_HEX(((data & 0xF0) >> 4)))); - console_putc((int) (TO_HEX(data & 0x0F))); -} - -void console_puthex_fg_bg(uint8_t data, uint32_t fore, uint32_t back) { - uint32_t fore_current = cur_fore; - uint32_t back_current = cur_back; - - cur_fore = fore; - cur_back = back; - - (void) console_putc((int) (TO_HEX(((data & 0xF0) >> 4)))); - (void) console_putc((int) (TO_HEX(data & 0x0F))); - - cur_fore = fore_current; - cur_back = back_current; -} - -void console_putpct_fg_bg(uint8_t data, uint32_t fore, uint32_t back) { - uint32_t fore_current = cur_fore; - uint32_t back_current = cur_back; - - cur_fore = fore; - cur_back = back; - - if (data < 100) { - console_putc((int) ((char) '0' + (char) (data / 10))); - console_putc((int) ((char) '0' + (char) (data % 10))); - } else { - console_puts("%%"); - } - - cur_fore = fore_current; - cur_back = back_current; -} - -void console_put3dec_fg_bg(uint8_t data, uint32_t fore, uint32_t back) { - uint32_t fore_current = cur_fore; - uint32_t back_current = cur_back; - - cur_fore = fore; - cur_back = back; - - const uint8_t i = data / 100; - - (void) console_putc((int) ((char) '0' + (char) i)); - - data = (uint8_t)(data - (i * 100)); - - console_putc((int) ((char) '0' + (char) (data / 10))); - console_putc((int) ((char) '0' + (char) (data % 10))); - - cur_fore = fore_current; - cur_back = back_current; -} - -void console_newline(void){ - newline(); -} - -void console_clear(void) { - uint32_t *address = (uint32_t *)(fb_addr); - uint32_t i; - - for (i = 0; i < (FB_HEIGHT * FB_WIDTH); i++) { - *address++ = (uint32_t) cur_back; - } - - current_x = 0; - current_y = 0; -} - -void console_set_cursor(uint32_t x, uint32_t y) { - if (x > FB_WIDTH / FB_CHAR_W) - current_x = 0; - else - current_x = x; - - if (y > FB_HEIGHT / FB_CHAR_H) - current_y = 0; - else - current_y = y; -} - -void console_save_cursor(void) { - saved_y = current_y; - saved_x = current_x; - saved_back = cur_back; - saved_fore = cur_fore; -} - -void console_restore_cursor(void) { - current_y = saved_y; - current_x = saved_x; - cur_back = saved_back; - cur_fore = saved_fore; -} - -void console_save_color(void) { - saved_back = cur_back; - saved_fore = cur_fore; -} - -void console_restore_color(void) { - cur_back = saved_back; - cur_fore = saved_fore; -} - -void console_set_fg_color(uint32_t fore) { - cur_fore = fore; -} - -void console_set_bg_color(uint32_t back) { - cur_back = back; -} - -void console_set_fg_bg_color(uint32_t fore, uint32_t back) { - cur_fore = fore; - cur_back = back; -} - -void console_clear_line(uint32_t line) { - uint32_t *address; - - if (line > FB_HEIGHT / FB_CHAR_H) { - return; - } else { - current_y = line; - } - - current_x = 0; - - address = (uint32_t *)(fb_addr) + (line * FB_CHAR_H * FB_WIDTH); - clear_row(address); -} - -void console_clear_top_row(void) { - uint32_t line; - uint32_t *address; - - for (line = top_row; line < (FB_HEIGHT / FB_CHAR_H) - 1; line++) { - address = (uint32_t*) (fb_addr) + (line * FB_CHAR_H * FB_WIDTH); - clear_row(address); - } - - current_x = 0; - current_y = top_row; -} - -void console_putpixel(uint32_t x, uint32_t y, uint32_t color) { - draw_pixel(x, y, color); -} - diff --git a/lib-hal/console/i2c/console.c b/lib-hal/console/i2c/console.cpp similarity index 77% rename from lib-hal/console/i2c/console.c rename to lib-hal/console/i2c/console.cpp index d33e8a75..37be38bf 100644 --- a/lib-hal/console/i2c/console.c +++ b/lib-hal/console/i2c/console.cpp @@ -1,8 +1,8 @@ /** - * @file console.c + * @file console.cpp * */ -/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,9 +23,8 @@ * THE SOFTWARE. */ -#include -#include -#include +#include +#include #include "console.h" @@ -34,57 +33,57 @@ static bool s_isConnected; #if !defined (CONSOLE_I2C_ADDRESS) -# define CONSOLE_I2C_ADDRESS ((uint8_t)0x4D) +# define CONSOLE_I2C_ADDRESS (0x4D) #endif #if !defined (CONSOLE_I2C_ONBOARD_CRYSTAL) -# define CONSOLE_I2C_ONBOARD_CRYSTAL 14745600UL +# define CONSOLE_I2C_ONBOARD_CRYSTAL (14745600UL) #endif #if !defined (CONSOLE_I2C_BAUDRATE) -# define CONSOLE_I2C_BAUDRATE 115200U +# define CONSOLE_I2C_BAUDRATE (115200U) #endif #define SC16IS7X0_REG_SHIFT 3 -#define SC16IS7X0_THR ((uint8_t)(0x00 << SC16IS7X0_REG_SHIFT)) -#define SC16IS7X0_FCR ((uint8_t)(0x02 << SC16IS7X0_REG_SHIFT)) -#define SC16IS7X0_LCR ((uint8_t)(0x03 << SC16IS7X0_REG_SHIFT)) -#define SC16IS7X0_MCR ((uint8_t)(0x04 << SC16IS7X0_REG_SHIFT)) -#define SC16IS7X0_SPR ((uint8_t)(0x07 << SC16IS7X0_REG_SHIFT)) -#define SC16IS7X0_TLR ((uint8_t)(0x07 << SC16IS7X0_REG_SHIFT)) -#define SC16IS7X0_TXLVL ((uint8_t)(0x08 << SC16IS7X0_REG_SHIFT)) +#define SC16IS7X0_THR (0x00 << SC16IS7X0_REG_SHIFT) +#define SC16IS7X0_FCR (0x02 << SC16IS7X0_REG_SHIFT) +#define SC16IS7X0_LCR (0x03 << SC16IS7X0_REG_SHIFT) +#define SC16IS7X0_MCR (0x04 << SC16IS7X0_REG_SHIFT) +#define SC16IS7X0_SPR (0x07 << SC16IS7X0_REG_SHIFT) +#define SC16IS7X0_TLR (0x07 << SC16IS7X0_REG_SHIFT) +#define SC16IS7X0_TXLVL (0x08 << SC16IS7X0_REG_SHIFT) -#define SC16IS7X0_DLL ((uint8_t)(0x00 << SC16IS7X0_REG_SHIFT)) -#define SC16IS7X0_DLH ((uint8_t)(0x01 << SC16IS7X0_REG_SHIFT)) -#define SC16IS7X0_EFR ((uint8_t)(0x02 << SC16IS7X0_REG_SHIFT)) +#define SC16IS7X0_DLL (0x00 << SC16IS7X0_REG_SHIFT) +#define SC16IS7X0_DLH (0x01 << SC16IS7X0_REG_SHIFT) +#define SC16IS7X0_EFR (0x02 << SC16IS7X0_REG_SHIFT) /** See section 8.3 of the datasheet for definitions * of bits in the FIFO Control Register (FCR) */ -#define FCR_TX_FIFO_RST ((uint8_t)(1U << 2)) -#define FCR_ENABLE_FIFO ((uint8_t)(1U << 0)) +#define FCR_TX_FIFO_RST (1U << 2) +#define FCR_ENABLE_FIFO (1U << 0) /** See section 8.4 of the datasheet for definitions * of bits in the Line Control Register (LCR) */ -#define LCR_BITS8 ((uint8_t)0x03) -#define LCR_BITS1 ((uint8_t)0x00) -#define LCR_NONE ((uint8_t)0x00) -#define LCR_ENABLE_DIV ((uint8_t)0x80) +#define LCR_BITS8 (0x03) +#define LCR_BITS1 (0x00) +#define LCR_NONE (0x00) +#define LCR_ENABLE_DIV (0x80) /** * 8.6 Modem Control Register (MCR) */ //MCR[2] only accessible when EFR[4] is set -#define MCR_ENABLE_TCR_TLR ((uint8_t)(1U << 2)) -#define MCR_PRESCALE_4 ((uint8_t)(1U << 7)) +#define MCR_ENABLE_TCR_TLR (1U << 2) +#define MCR_PRESCALE_4 (1U << 7) /** * 8.11 Enhanced Features Register (EFR) */ -#define EFR_ENABLE_ENHANCED_FUNCTIONS ((uint8_t)(1U << 4)) +#define EFR_ENABLE_ENHANCED_FUNCTIONS (1U << 4) static bool is_connected(const uint8_t address, const uint32_t baudrate) { char buf; @@ -97,7 +96,7 @@ static bool is_connected(const uint8_t address, const uint32_t baudrate) { } /* This is known to corrupt the Atmel AT24RF08 EEPROM */ - return FUNC_PREFIX(i2c_write(NULL, 0)) == 0; + return FUNC_PREFIX(i2c_write(nullptr, 0)) == 0; } static void setup() { @@ -108,8 +107,8 @@ static void setup() { static void write_register(uint8_t nRegister, uint8_t nValue) { char buffer[2]; - buffer[0] = (char)(nRegister); - buffer[1] = (char)(nValue); + buffer[0] = static_cast(nRegister); + buffer[1] = static_cast(nValue); setup(); FUNC_PREFIX(i2c_write(buffer, 2)); @@ -121,13 +120,13 @@ static uint8_t read_byte() { setup(); FUNC_PREFIX(i2c_read(buffer, 1)); - return (uint8_t) (buffer[0]); + return static_cast(buffer[0]); } static uint8_t read_register(uint8_t nRegister) { char buffer[1]; - buffer[0] = (char) (nRegister); + buffer[0] = static_cast(nRegister); setup(); FUNC_PREFIX(i2c_write(buffer, 1)); @@ -135,7 +134,7 @@ static uint8_t read_register(uint8_t nRegister) { return read_byte(); } -inline static bool is_writable() { +static bool is_writable() { return (read_register(SC16IS7X0_TXLVL) != 0); } @@ -157,7 +156,7 @@ static void set_baud(uint32_t nBaud) { write_register(SC16IS7X0_LCR, nRegisterLCR); } -void __attribute__((cold)) console_init(void) { +void __attribute__((cold)) console_init() { FUNC_PREFIX(i2c_begin()); s_isConnected = is_connected(CONSOLE_I2C_ADDRESS, 100000); @@ -198,6 +197,7 @@ void __attribute__((cold)) console_init(void) { write_register(SC16IS7X0_FCR, FCR_ENABLE_FIFO); } +extern "C" { void console_putc(int c) { if (!s_isConnected) { return; @@ -303,14 +303,15 @@ void console_set_bg_color(uint16_t bg) { } } -void console_status(uint32_t color, const char *s) { +void console_status(uint32_t nColour, const char *s) { if (!s_isConnected) { return; } - console_set_fg_color((uint16_t) color); + console_set_fg_color(static_cast(nColour)); console_set_bg_color(CONSOLE_BLACK); console_puts(s); console_putc('\n'); console_set_fg_color(CONSOLE_WHITE); } +} diff --git a/lib-hal/console/null/console.cpp b/lib-hal/console/null/console.cpp new file mode 100755 index 00000000..c0cf5ec3 --- /dev/null +++ b/lib-hal/console/null/console.cpp @@ -0,0 +1,36 @@ +/** + * @file console.cpp + * + */ +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +void console_init() {} + +extern "C" { +void console_puts([[maybe_unused]] const char *p) {} +void console_write([[maybe_unused]] const char *p, [[maybe_unused]] unsigned int i) {} +void console_status([[maybe_unused]] uint32_t i, [[maybe_unused]] const char *p) {} +void console_error([[maybe_unused]] const char *p) {} +void console_putc([[maybe_unused]] int i) {} +} diff --git a/lib-hal/console/uart0/console.c b/lib-hal/console/uart0/console.cpp similarity index 83% rename from lib-hal/console/uart0/console.c rename to lib-hal/console/uart0/console.cpp index 9fca1a3f..cbb2cdf8 100644 --- a/lib-hal/console/uart0/console.c +++ b/lib-hal/console/uart0/console.cpp @@ -1,8 +1,8 @@ /** - * @file console.c + * @file console.cpp * */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,20 +23,14 @@ * THE SOFTWARE. */ -#include +#include #include "console.h" -extern void uart0_init(void); -extern void uart0_putc(int); -extern void uart0_puts(const char *); - -void __attribute__((cold)) console_init(void) { - uart0_init(); - - console_set_fg_color(CONSOLE_WHITE); - console_set_bg_color(CONSOLE_BLACK); -} +extern "C" { +void uart0_init(); +void uart0_putc(int); +void uart0_puts(const char *); void console_putc(int c) { uart0_putc(c); @@ -46,6 +40,12 @@ void console_puts(const char *s) { uart0_puts(s); } +void console_error(const char *s) { + uart0_puts("\x1b[31m"); + uart0_puts(s); + uart0_puts("\x1b[37m"); +} + void console_set_fg_color(uint16_t fg) { switch (fg) { case CONSOLE_BLACK: @@ -89,19 +89,13 @@ void console_set_bg_color(uint16_t bg) { void console_write(const char *s, unsigned int n) { char c; - while (((c = *s++) != (char) 0) && (n-- != 0)) { - console_putc((int) c); + while (((c = *s++) != 0) && (n-- != 0)) { + console_putc(static_cast(c)); } } -void console_error(const char *s) { - uart0_puts("\x1b[31m"); - uart0_puts(s); - uart0_puts("\x1b[37m"); -} - -void console_status(uint32_t color, const char *s) { - console_set_fg_color((uint16_t) color); +void console_status(uint32_t nColour, const char *s) { + console_set_fg_color(static_cast(nColour)); console_set_bg_color(CONSOLE_BLACK); uart0_puts(s); @@ -109,3 +103,11 @@ void console_status(uint32_t color, const char *s) { console_set_fg_color(CONSOLE_WHITE); } +} + +void __attribute__((cold)) console_init() { + uart0_init(); + + console_set_fg_color(CONSOLE_WHITE); + console_set_bg_color(CONSOLE_BLACK); +} diff --git a/lib-debug/src/debug_dump.c b/lib-hal/debug/debug_dump.cpp old mode 100644 new mode 100755 similarity index 74% rename from lib-debug/src/debug_dump.c rename to lib-hal/debug/debug_dump.cpp index e2383f82..b69df49f --- a/lib-debug/src/debug_dump.c +++ b/lib-hal/debug/debug_dump.cpp @@ -1,8 +1,8 @@ /** - * @file debug_dump.c + * @file debug_dump.cpp * */ -/* Copyright (C) 2018-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,32 +23,31 @@ * THE SOFTWARE. */ +#include +#include #include -#include -#include #if defined (H3) -extern int uart0_printf(const char* fmt, ...); +extern "C" int uart0_printf(const char* fmt, ...); # define printf uart0_printf #endif -#define CHARS_PER_LINE 16 +static constexpr uint32_t CHARS_PER_LINE = 16; -void debug_dump(const void *packet, uint16_t len) { - uint16_t chars = 0; - uint16_t chars_this_line = 0; - const uint8_t *p = (const uint8_t *) packet; +void debug_dump(const void *pData, uint32_t nSize) { + uint32_t chars = 0; + const auto *p = reinterpret_cast(pData); - printf("%p:%d\n", packet, len); + printf("%p:%d\n", pData, nSize); do { - chars_this_line = 0; + uint32_t chars_this_line = 0; printf("%04x ", chars); - const uint8_t *q = p; + const auto *q = p; - while ((chars_this_line < CHARS_PER_LINE) && (chars < len)) { + while ((chars_this_line < CHARS_PER_LINE) && (chars < nSize)) { if (chars_this_line % 8 == 0) { printf(" "); } @@ -60,7 +59,7 @@ void debug_dump(const void *packet, uint16_t len) { p++; } - uint16_t chars_dot_line = chars_this_line; + auto chars_dot_line = chars_this_line; for (; chars_this_line < CHARS_PER_LINE; chars_this_line++) { if (chars_this_line % 8 == 0) { @@ -88,8 +87,8 @@ void debug_dump(const void *packet, uint16_t len) { q++; } - printf("\n"); + puts(""); - } while (chars < len); + } while (chars < nSize); } diff --git a/lib-debug/src/debug_print_bits.c b/lib-hal/debug/debug_print_bits.cpp old mode 100644 new mode 100755 similarity index 89% rename from lib-debug/src/debug_print_bits.c rename to lib-hal/debug/debug_print_bits.cpp index 48747959..07a758ab --- a/lib-debug/src/debug_print_bits.c +++ b/lib-hal/debug/debug_print_bits.cpp @@ -1,8 +1,8 @@ /** - * @file debug_print_bits.c + * @file debug_print_bits.cpp * */ -/* Copyright (C) 2018-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,7 +27,7 @@ #include #if defined (H3) -extern int uart0_printf(const char* fmt, ...); +extern "C" int uart0_printf(const char* fmt, ...); # define printf uart0_printf #endif @@ -44,5 +44,5 @@ void debug_print_bits(uint32_t u) { b = b >> 1; } - printf("\n"); + puts(""); } diff --git a/lib-hal/debug/emac/gd32/emac_debug.cpp b/lib-hal/debug/emac/gd32/emac_debug.cpp old mode 100644 new mode 100755 index b42aa6c4..ef37b876 --- a/lib-hal/debug/emac/gd32/emac_debug.cpp +++ b/lib-hal/debug/emac/gd32/emac_debug.cpp @@ -2,7 +2,7 @@ * @file emac_debug.cpp * */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,7 +32,11 @@ static uint32_t s_nCounter; void emac_debug_run() { uint32_t rxfifo_drop; uint32_t rxdma_drop; +#if defined (GD32H7XX) + enet_missed_frame_counter_get(ENETx, &rxfifo_drop, &rxdma_drop); +#else enet_missed_frame_counter_get(&rxfifo_drop, &rxdma_drop); +#endif if ((rxfifo_drop != 0) || (rxdma_drop != 0)) { printf("%u: RxFIFO: %u RxDMA: %u\n", ++s_nCounter, rxfifo_drop, rxdma_drop); diff --git a/lib-hal/debug/i2c/i2cdetect.cpp b/lib-hal/debug/i2c/i2cdetect.cpp old mode 100644 new mode 100755 index 90c0e243..90c647d7 --- a/lib-hal/debug/i2c/i2cdetect.cpp +++ b/lib-hal/debug/i2c/i2cdetect.cpp @@ -2,7 +2,7 @@ * @file i2cdetect.cpp * */ -/* Copyright (C) 2020-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,12 +23,16 @@ * THE SOFTWARE. */ +#undef NDEBUG + #include #include "i2cdetect.h" #include "hal_i2c.h" +#include "debug.h" + inline static bool i2c_is_connected(uint8_t nAddress) { uint8_t nResult; char buffer; diff --git a/lib-hal/debug/i2c/i2cdetect.h b/lib-hal/debug/i2c/i2cdetect.h old mode 100644 new mode 100755 index 68bf63e7..f7f44491 --- a/lib-hal/debug/i2c/i2cdetect.h +++ b/lib-hal/debug/i2c/i2cdetect.h @@ -2,7 +2,7 @@ * @file i2cdetect.h * */ -/* Copyright (C) 2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-hal/debug/stack/stack_debug.cpp b/lib-hal/debug/stack/stack_debug.cpp old mode 100644 new mode 100755 index 45eac749..b106c334 --- a/lib-hal/debug/stack/stack_debug.cpp +++ b/lib-hal/debug/stack/stack_debug.cpp @@ -2,7 +2,7 @@ * @file stack_debug.cpp * */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -66,6 +66,7 @@ void stack_debug_print() { if (s_nUsedBytesPrevious != nUsedBytes) { s_nUsedBytesPrevious = nUsedBytes; + if (nFreePct == 0) { printf("\x1b[31m"); } else if (nFreePct == 1) { diff --git a/lib-hal/device/usb/host/gd32/usb_host.cpp b/lib-hal/device/usb/host/gd32/f/usb_host.cpp similarity index 76% rename from lib-hal/device/usb/host/gd32/usb_host.cpp rename to lib-hal/device/usb/host/gd32/f/usb_host.cpp index c0b2ff50..254e2aac 100644 --- a/lib-hal/device/usb/host/gd32/usb_host.cpp +++ b/lib-hal/device/usb/host/gd32/f/usb_host.cpp @@ -2,7 +2,7 @@ * usb_host.cpp * */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,23 +27,28 @@ #include "gd32.h" +/** + * Needed for older GD32F firmware + */ +#if !defined(GPIO_OSPEED_MAX) +# define GPIO_OSPEED_MAX GPIO_OSPEED_200MHZ +#endif + extern "C" { #include "usbh_core.h" #include "usbh_msc_core.h" - #include "drv_usbh_int.h" +void usb_mdelay(uint32_t); } static void usb_gpio_config() { #if !defined (GD32F4XX) #else rcu_periph_clock_enable(RCU_SYSCFG); - rcu_periph_clock_enable(RCU_GPIOA); - /* USBFS_DM(PA11) and USBFS_DP(PA12) GPIO pin configuration */ gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_11 | GPIO_PIN_12); - gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_11 | GPIO_PIN_12); + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_MAX, GPIO_PIN_11 | GPIO_PIN_12); gpio_af_set(GPIOA, GPIO_AF_10, GPIO_PIN_11 | GPIO_PIN_12); #endif @@ -94,23 +99,41 @@ static void usb_intr_config() { #endif } -usbh_host usb_host_msc; +void usb_vbus_config () { +#if defined (USB_HOST_VBUS_GPIOx) + rcu_periph_clock_enable(USB_HOST_VBUS_RCU_GPIOx); + +# if defined (GPIO_INIT) + gpio_init(USB_HOST_VBUS_GPIOx, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, USB_HOST_VBUS_GPIO_PINx); +# else + gpio_mode_set(USB_HOST_VBUS_GPIOx, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, USB_HOST_VBUS_GPIO_PINx); + gpio_output_options_set(USB_HOST_VBUS_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED_MAX, USB_HOST_VBUS_GPIO_PINx); +# endif + + gpio_bit_set(USB_HOST_VBUS_GPIOx, USB_HOST_VBUS_GPIO_PINx); + + usb_mdelay (200); +#endif +} + #if !defined (GD32F4XX) extern usb_core_driver usbh_core; +usbh_host usb_host; #else usb_core_driver usbh_core; +usbh_host usb_host_msc; #endif extern usbh_user_cb usr_cb; void usb_init() { usb_gpio_config(); usb_rcu_config(); - - usbh_class_register(&usb_host_msc, &usbh_msc); - + usb_vbus_config(); #if !defined (GD32F4XX) - usbh_init (&usb_host_msc, &usr_cb); + usbh_class_register(&usb_host, &usbh_msc); + usbh_init (&usb_host, &usr_cb); #else + usbh_class_register(&usb_host_msc, &usbh_msc); usbh_init(&usb_host_msc, &usbh_core, USB_CORE_ENUM_FS, diff --git a/lib-hal/device/usb/host/gd32/usb_host_msc.cpp b/lib-hal/device/usb/host/gd32/usb_host_msc.cpp index 227d0b10..585a9e81 100644 --- a/lib-hal/device/usb/host/gd32/usb_host_msc.cpp +++ b/lib-hal/device/usb/host/gd32/usb_host_msc.cpp @@ -2,7 +2,7 @@ * usb_host_msc.cpp * */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,6 +23,10 @@ * THE SOFTWARE. */ +#ifndef NDEBUG +# undef NDEBUG +#endif + #include #include @@ -31,8 +35,20 @@ extern "C" { #include "usb_host_msc.h" #include "usbh_core.h" +void console_error(const char *); } +#include "../lib-hal/ff14b/source/ff.h" +#include "device/usb/host.h" + +#if (FF_DEFINED == 86631) // R0.14b + static FATFS fat_fs; +#else +# error Not a recognized/tested FatFs version +#endif + +#include "device/usb/host.h" + usbh_user_cb usr_cb = { usbh_user_init, usbh_user_deinit, @@ -54,51 +70,90 @@ usbh_user_cb usr_cb = { usbh_user_unrecovered_error }; -#define USBH_USR_FS_INIT 0 -#define USBH_USR_FS_READLIST 1 -#define USBH_USR_FS_WRITEFILE 2 -#define USBH_USR_FS_DRAW 3 -#define USBH_USR_FS_DEMOEND 4 +#if defined NODE_SHOWFILE +namespace showfile { + void usb_ready(); + void usb_disconnected(); +} // namespace showfile +#endif -static uint32_t usbh_usr_application_state = USBH_USR_FS_INIT; +/* state machine for the USBH_USR_ApplicationState */ +#define USBH_USR_FS_MOUNT 0 +#define USBH_USR_FS_READY 1 -void usbh_user_init() { - static uint32_t startup = 0U; +static uint8_t usbh_usr_application_state = USBH_USR_FS_MOUNT; + +static usb::host::Status s_status; +static usb::host::Speed s_speed; +static usb::host::Class s_class; + +namespace usb { +namespace host { +Status get_status() { + return s_status; +} +Speed get_speed() { + return s_speed; +} +Class get_class() { + return s_class; +} +} // namespace host +} // namespace usb - if (0U == startup) { - startup = 1U; +void usbh_user_init() { + if (s_status == usb::host::Status::NOT_AVAILABLE) { + s_status = usb::host::Status::DISCONNECTED; +#ifndef NDEBUG puts("USB host library started."); +#endif } } void usbh_user_deinit() { - usbh_usr_application_state = USBH_USR_FS_INIT; + s_status = usb::host::Status::NOT_AVAILABLE; } void usbh_user_device_connected() { + s_status = usb::host::Status::ATTACHED; puts("> Device Attached."); } void usbh_user_unrecovered_error() { + s_status = usb::host::Status::UNRECOVERABLE_ERROR; puts("> Unrecovered error state."); } void usbh_user_device_disconnected() { + s_status = usb::host::Status::DISCONNECTED; puts("> Device Disconnected."); + usbh_usr_application_state = USBH_USR_FS_MOUNT; +#if defined NODE_SHOWFILE + showfile::usb_disconnected(); +#endif } void usbh_user_device_reset() { + s_status = usb::host::Status::RESET; puts("> Reset the USB device."); } void usbh_user_device_speed_detected(uint32_t device_speed) { if (PORT_SPEED_HIGH == device_speed) { + s_speed = usb::host::Speed::HIGH; puts("> High speed device detected."); } else if (PORT_SPEED_FULL == device_speed) { + s_speed = usb::host::Speed::FULL; +#ifndef NDEBUG puts("> Full speed device detected."); +#endif } else if (PORT_SPEED_LOW == device_speed) { + s_speed = usb::host::Speed::LOW; +#ifndef NDEBUG puts("> Low speed device detected."); +#endif } else { + s_speed = usb::host::Speed::FAULT; puts("> Device Fault."); } } @@ -137,16 +192,17 @@ void usbh_user_serialnum_string(void *serial_num_string) { } void usbh_user_enumeration_finish() { + s_status = usb::host::Status::ENUMERATION_COMPLETED; puts("> Enumeration completed."); } void usbh_user_device_not_supported() { + s_status = usb::host::Status::DEVICE_NOT_SUPPORTED; puts("> Device not supported."); } usbh_user_status usbh_user_userinput() { puts("usbh_user_userinput"); - return static_cast(1); } @@ -155,5 +211,22 @@ void usbh_user_over_current_detected() { } int usbh_usr_msc_application() { + if (usbh_usr_application_state == USBH_USR_FS_MOUNT) { + const auto result = f_mount(&fat_fs, (const TCHAR *) "0:/", (BYTE) 0); + + if (result == FR_OK) { + s_status = usb::host::Status::READY; + usbh_usr_application_state = USBH_USR_FS_READY; +#if defined NODE_SHOWFILE + showfile::usb_ready(); +#endif + } else { + char buffer[32]; + snprintf(buffer, sizeof(buffer) - 1, "f_mount failed! %d\n", (int) result); + console_error(buffer); + return -1; + } + } + return 0; } diff --git a/lib-hal/ff14b/LICENSE.txt b/lib-hal/ff14b/LICENSE.txt new file mode 100755 index 00000000..25379e46 --- /dev/null +++ b/lib-hal/ff14b/LICENSE.txt @@ -0,0 +1,24 @@ +FatFs License + +FatFs has being developped as a personal project of the author, ChaN. It is free from the code anyone else wrote at current release. Following code block shows a copy of the FatFs license document that heading the source files. + +/*----------------------------------------------------------------------------/ +/ FatFs - Generic FAT Filesystem Module Rx.xx / +/-----------------------------------------------------------------------------/ +/ +/ Copyright (C) 20xx, ChaN, all right reserved. +/ +/ FatFs module is an open source software. Redistribution and use of FatFs in +/ source and binary forms, with or without modification, are permitted provided +/ that the following condition is met: +/ +/ 1. Redistributions of source code must retain the above copyright notice, +/ this condition and the following disclaimer. +/ +/ This software is provided by the copyright holder and contributors "AS IS" +/ and any warranties related to this software are DISCLAIMED. +/ The copyright owner or contributors be NOT LIABLE for any damages caused +/ by use of this software. +/----------------------------------------------------------------------------*/ + +Therefore FatFs license is one of the BSD-style licenses, but there is a significant feature. FatFs is mainly intended for embedded systems. In order to extend the usability for commercial products, the redistributions of FatFs in binary form, such as embedded code, binary library and any forms without source code, do not need to include about FatFs in the documentations. This is equivalent to the 1-clause BSD license. Of course FatFs is compatible with the most of open source software licenses include GNU GPL. When you redistribute the FatFs source code with changes or create a fork, the license can also be changed to GNU GPL, BSD-style license or any open source software license that not conflict with FatFs license. diff --git a/lib-hal/ff14b/source/00history.txt b/lib-hal/ff14b/source/00history.txt new file mode 100755 index 00000000..d3c910c1 --- /dev/null +++ b/lib-hal/ff14b/source/00history.txt @@ -0,0 +1,359 @@ +---------------------------------------------------------------------------- + Revision history of FatFs module +---------------------------------------------------------------------------- + +R0.00 (February 26, 2006) + + Prototype. + + + +R0.01 (April 29, 2006) + + The first release. + + + +R0.02 (June 01, 2006) + + Added FAT12 support. + Removed unbuffered mode. + Fixed a problem on small (<32M) partition. + + + +R0.02a (June 10, 2006) + + Added a configuration option (_FS_MINIMUM). + + + +R0.03 (September 22, 2006) + + Added f_rename(). + Changed option _FS_MINIMUM to _FS_MINIMIZE. + + + +R0.03a (December 11, 2006) + + Improved cluster scan algorithm to write files fast. + Fixed f_mkdir() creates incorrect directory on FAT32. + + + +R0.04 (February 04, 2007) + + Added f_mkfs(). + Supported multiple drive system. + Changed some interfaces for multiple drive system. + Changed f_mountdrv() to f_mount(). + + + +R0.04a (April 01, 2007) + + Supported multiple partitions on a physical drive. + Added a capability of extending file size to f_lseek(). + Added minimization level 3. + Fixed an endian sensitive code in f_mkfs(). + + + +R0.04b (May 05, 2007) + + Added a configuration option _USE_NTFLAG. + Added FSINFO support. + Fixed DBCS name can result FR_INVALID_NAME. + Fixed short seek (<= csize) collapses the file object. + + + +R0.05 (August 25, 2007) + + Changed arguments of f_read(), f_write() and f_mkfs(). + Fixed f_mkfs() on FAT32 creates incorrect FSINFO. + Fixed f_mkdir() on FAT32 creates incorrect directory. + + + +R0.05a (February 03, 2008) + + Added f_truncate() and f_utime(). + Fixed off by one error at FAT sub-type determination. + Fixed btr in f_read() can be mistruncated. + Fixed cached sector is not flushed when create and close without write. + + + +R0.06 (April 01, 2008) + + Added fputc(), fputs(), fprintf() and fgets(). + Improved performance of f_lseek() on moving to the same or following cluster. + + + +R0.07 (April 01, 2009) + + Merged Tiny-FatFs as a configuration option. (_FS_TINY) + Added long file name feature. (_USE_LFN) + Added multiple code page feature. (_CODE_PAGE) + Added re-entrancy for multitask operation. (_FS_REENTRANT) + Added auto cluster size selection to f_mkfs(). + Added rewind option to f_readdir(). + Changed result code of critical errors. + Renamed string functions to avoid name collision. + + + +R0.07a (April 14, 2009) + + Septemberarated out OS dependent code on reentrant cfg. + Added multiple sector size feature. + + + +R0.07c (June 21, 2009) + + Fixed f_unlink() can return FR_OK on error. + Fixed wrong cache control in f_lseek(). + Added relative path feature. + Added f_chdir() and f_chdrive(). + Added proper case conversion to extended character. + + + +R0.07e (November 03, 2009) + + Septemberarated out configuration options from ff.h to ffconf.h. + Fixed f_unlink() fails to remove a sub-directory on _FS_RPATH. + Fixed name matching error on the 13 character boundary. + Added a configuration option, _LFN_UNICODE. + Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. + + + +R0.08 (May 15, 2010) + + Added a memory configuration option. (_USE_LFN = 3) + Added file lock feature. (_FS_SHARE) + Added fast seek feature. (_USE_FASTSEEK) + Changed some types on the API, XCHAR->TCHAR. + Changed .fname in the FILINFO structure on Unicode cfg. + String functions support UTF-8 encoding files on Unicode cfg. + + + +R0.08a (August 16, 2010) + + Added f_getcwd(). (_FS_RPATH = 2) + Added sector erase feature. (_USE_ERASE) + Moved file lock semaphore table from fs object to the bss. + Fixed f_mkfs() creates wrong FAT32 volume. + + + +R0.08b (January 15, 2011) + + Fast seek feature is also applied to f_read() and f_write(). + f_lseek() reports required table size on creating CLMP. + Extended format syntax of f_printf(). + Ignores duplicated directory separators in given path name. + + + +R0.09 (September 06, 2011) + + f_mkfs() supports multiple partition to complete the multiple partition feature. + Added f_fdisk(). + + + +R0.09a (August 27, 2012) + + Changed f_open() and f_opendir() reject null object pointer to avoid crash. + Changed option name _FS_SHARE to _FS_LOCK. + Fixed assertion failure due to OS/2 EA on FAT12/16 volume. + + + +R0.09b (January 24, 2013) + + Added f_setlabel() and f_getlabel(). + + + +R0.10 (October 02, 2013) + + Added selection of character encoding on the file. (_STRF_ENCODE) + Added f_closedir(). + Added forced full FAT scan for f_getfree(). (_FS_NOFSINFO) + Added forced mount feature with changes of f_mount(). + Improved behavior of volume auto detection. + Improved write throughput of f_puts() and f_printf(). + Changed argument of f_chdrive(), f_mkfs(), disk_read() and disk_write(). + Fixed f_write() can be truncated when the file size is close to 4GB. + Fixed f_open(), f_mkdir() and f_setlabel() can return incorrect value on error. + + + +R0.10a (January 15, 2014) + + Added arbitrary strings as drive number in the path name. (_STR_VOLUME_ID) + Added a configuration option of minimum sector size. (_MIN_SS) + 2nd argument of f_rename() can have a drive number and it will be ignored. + Fixed f_mount() with forced mount fails when drive number is >= 1. (appeared at R0.10) + Fixed f_close() invalidates the file object without volume lock. + Fixed f_closedir() returns but the volume lock is left acquired. (appeared at R0.10) + Fixed creation of an entry with LFN fails on too many SFN collisions. (appeared at R0.07) + + + +R0.10b (May 19, 2014) + + Fixed a hard error in the disk I/O layer can collapse the directory entry. + Fixed LFN entry is not deleted when delete/rename an object with lossy converted SFN. (appeared at R0.07) + + + +R0.10c (November 09, 2014) + + Added a configuration option for the platforms without RTC. (_FS_NORTC) + Changed option name _USE_ERASE to _USE_TRIM. + Fixed volume label created by Mac OS X cannot be retrieved with f_getlabel(). (appeared at R0.09b) + Fixed a potential problem of FAT access that can appear on disk error. + Fixed null pointer dereference on attempting to delete the root direcotry. (appeared at R0.08) + + + +R0.11 (February 09, 2015) + + Added f_findfirst(), f_findnext() and f_findclose(). (_USE_FIND) + Fixed f_unlink() does not remove cluster chain of the file. (appeared at R0.10c) + Fixed _FS_NORTC option does not work properly. (appeared at R0.10c) + + + +R0.11a (September 05, 2015) + + Fixed wrong media change can lead a deadlock at thread-safe configuration. + Added code page 771, 860, 861, 863, 864, 865 and 869. (_CODE_PAGE) + Removed some code pages actually not exist on the standard systems. (_CODE_PAGE) + Fixed errors in the case conversion teble of code page 437 and 850 (ff.c). + Fixed errors in the case conversion teble of Unicode (cc*.c). + + + +R0.12 (April 12, 2016) + + Added support for exFAT file system. (_FS_EXFAT) + Added f_expand(). (_USE_EXPAND) + Changed some members in FINFO structure and behavior of f_readdir(). + Added an option _USE_CHMOD. + Removed an option _WORD_ACCESS. + Fixed errors in the case conversion table of Unicode (cc*.c). + + + +R0.12a (July 10, 2016) + + Added support for creating exFAT volume with some changes of f_mkfs(). + Added a file open method FA_OPEN_APPEND. An f_lseek() following f_open() is no longer needed. + f_forward() is available regardless of _FS_TINY. + Fixed f_mkfs() creates wrong volume. (appeared at R0.12) + Fixed wrong memory read in create_name(). (appeared at R0.12) + Fixed compilation fails at some configurations, _USE_FASTSEEK and _USE_FORWARD. + + + +R0.12b (September 04, 2016) + + Made f_rename() be able to rename objects with the same name but case. + Fixed an error in the case conversion teble of code page 866. (ff.c) + Fixed writing data is truncated at the file offset 4GiB on the exFAT volume. (appeared at R0.12) + Fixed creating a file in the root directory of exFAT volume can fail. (appeared at R0.12) + Fixed f_mkfs() creating exFAT volume with too small cluster size can collapse unallocated memory. (appeared at R0.12) + Fixed wrong object name can be returned when read directory at Unicode cfg. (appeared at R0.12) + Fixed large file allocation/removing on the exFAT volume collapses allocation bitmap. (appeared at R0.12) + Fixed some internal errors in f_expand() and f_lseek(). (appeared at R0.12) + + + +R0.12c (March 04, 2017) + + Improved write throughput at the fragmented file on the exFAT volume. + Made memory usage for exFAT be able to be reduced as decreasing _MAX_LFN. + Fixed successive f_getfree() can return wrong count on the FAT12/16 volume. (appeared at R0.12) + Fixed configuration option _VOLUMES cannot be set 10. (appeared at R0.10c) + + + +R0.13 (May 21, 2017) + + Changed heading character of configuration keywords "_" to "FF_". + Removed ASCII-only configuration, FF_CODE_PAGE = 1. Use FF_CODE_PAGE = 437 instead. + Added f_setcp(), run-time code page configuration. (FF_CODE_PAGE = 0) + Improved cluster allocation time on stretch a deep buried cluster chain. + Improved processing time of f_mkdir() with large cluster size by using FF_USE_LFN = 3. + Improved NoFatChain flag of the fragmented file to be set after it is truncated and got contiguous. + Fixed archive attribute is left not set when a file on the exFAT volume is renamed. (appeared at R0.12) + Fixed exFAT FAT entry can be collapsed when write or lseek operation to the existing file is done. (appeared at R0.12c) + Fixed creating a file can fail when a new cluster allocation to the exFAT directory occures. (appeared at R0.12c) + + + +R0.13a (October 14, 2017) + + Added support for UTF-8 encoding on the API. (FF_LFN_UNICODE = 2) + Added options for file name output buffer. (FF_LFN_BUF, FF_SFN_BUF). + Added dynamic memory allocation option for working buffer of f_mkfs() and f_fdisk(). + Fixed f_fdisk() and f_mkfs() create the partition table with wrong CHS parameters. (appeared at R0.09) + Fixed f_unlink() can cause lost clusters at fragmented file on the exFAT volume. (appeared at R0.12c) + Fixed f_setlabel() rejects some valid characters for exFAT volume. (appeared at R0.12) + + + +R0.13b (April 07, 2018) + + Added support for UTF-32 encoding on the API. (FF_LFN_UNICODE = 3) + Added support for Unix style volume ID. (FF_STR_VOLUME_ID = 2) + Fixed accesing any object on the exFAT root directory beyond the cluster boundary can fail. (appeared at R0.12c) + Fixed f_setlabel() does not reject some invalid characters. (appeared at R0.09b) + + + +R0.13c (October 14, 2018) + Supported stdint.h for C99 and later. (integer.h was included in ff.h) + Fixed reading a directory gets infinite loop when the last directory entry is not empty. (appeared at R0.12) + Fixed creating a sub-directory in the fragmented sub-directory on the exFAT volume collapses FAT chain of the parent directory. (appeared at R0.12) + Fixed f_getcwd() cause output buffer overrun when the buffer has a valid drive number. (appeared at R0.13b) + + + +R0.14 (October 14, 2019) + Added support for 64-bit LBA and GUID partition table (FF_LBA64 = 1) + Changed some API functions, f_mkfs() and f_fdisk(). + Fixed f_open() function cannot find the file with file name in length of FF_MAX_LFN characters. + Fixed f_readdir() function cannot retrieve long file names in length of FF_MAX_LFN - 1 characters. + Fixed f_readdir() function returns file names with wrong case conversion. (appeared at R0.12) + Fixed f_mkfs() function can fail to create exFAT volume in the second partition. (appeared at R0.12) + + +R0.14a (December 5, 2020) + Limited number of recursive calls in f_findnext(). + Fixed old floppy disks formatted with MS-DOS 2.x and 3.x cannot be mounted. + Fixed some compiler warnings. + + + +R0.14b (April 17, 2021) + Made FatFs uses standard library for copy, compare and search instead of built-in string functions. + Added support for long long integer and floating point to f_printf(). (FF_STRF_LLI and FF_STRF_FP) + Made path name parser ignore the terminating separator to allow "dir/". + Improved the compatibility in Unix style path name feature. + Fixed the file gets dead-locked when f_open() failed with some conditions. (appeared at R0.12a) + Fixed f_mkfs() can create wrong exFAT volume due to a timing dependent error. (appeared at R0.12) + Fixed code page 855 cannot be set by f_setcp(). + Fixed some compiler warnings. + + diff --git a/lib-hal/ff14b/source/00readme.txt b/lib-hal/ff14b/source/00readme.txt new file mode 100755 index 00000000..53e035f6 --- /dev/null +++ b/lib-hal/ff14b/source/00readme.txt @@ -0,0 +1,21 @@ +FatFs Module Source Files R0.14b + + +FILES + + 00readme.txt This file. + 00history.txt Revision history. + ff.c FatFs module. + ffconf.h Configuration file of FatFs module. + ff.h Common include file for FatFs and application module. + diskio.h Common include file for FatFs and disk I/O module. + diskio.c An example of glue function to attach existing disk I/O module to FatFs. + ffunicode.c Optional Unicode utility functions. + ffsystem.c An example of optional O/S related functions. + + + Low level disk I/O module is not included in this archive because the FatFs + module is only a generic file system layer and it does not depend on any specific + storage device. You need to provide a low level disk I/O module written to + control the storage device that attached to the target system. + diff --git a/lib-hal/ff14b/source/diskio.h b/lib-hal/ff14b/source/diskio.h new file mode 100755 index 00000000..554398e4 --- /dev/null +++ b/lib-hal/ff14b/source/diskio.h @@ -0,0 +1,79 @@ +/*-----------------------------------------------------------------------/ +/ Low level disk interface modlue include file (C)ChaN, 2019 / +/-----------------------------------------------------------------------*/ + +#ifndef _DISKIO_DEFINED +#define _DISKIO_DEFINED + +#include "ff.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Status of Disk Functions */ +typedef BYTE DSTATUS; + +/* Results of Disk Functions */ +typedef enum { + RES_OK = 0, /* 0: Successful */ + RES_ERROR, /* 1: R/W Error */ + RES_WRPRT, /* 2: Write Protected */ + RES_NOTRDY, /* 3: Not Ready */ + RES_PARERR /* 4: Invalid Parameter */ +} DRESULT; + + +/*---------------------------------------*/ +/* Prototypes for disk control functions */ + + +DSTATUS disk_initialize (BYTE pdrv); +DSTATUS disk_status (BYTE pdrv); +DRESULT disk_read (BYTE pdrv, BYTE* buff, LBA_t sector, UINT count); +DRESULT disk_write (BYTE pdrv, const BYTE* buff, LBA_t sector, UINT count); +DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff); + + +/* Disk Status Bits (DSTATUS) */ + +#define STA_NOINIT 0x01 /* Drive not initialized */ +#define STA_NODISK 0x02 /* No medium in the drive */ +#define STA_PROTECT 0x04 /* Write protected */ + + +/* Command code for disk_ioctrl fucntion */ + +/* Generic command (Used by FatFs) */ +#define CTRL_SYNC 0 /* Complete pending write process (needed at FF_FS_READONLY == 0) */ +#define GET_SECTOR_COUNT 1 /* Get media size (needed at FF_USE_MKFS == 1) */ +#define GET_SECTOR_SIZE 2 /* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */ +#define GET_BLOCK_SIZE 3 /* Get erase block size (needed at FF_USE_MKFS == 1) */ +#define CTRL_TRIM 4 /* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */ + +/* Generic command (Not used by FatFs) */ +#define CTRL_POWER 5 /* Get/Set power status */ +#define CTRL_LOCK 6 /* Lock/Unlock media removal */ +#define CTRL_EJECT 7 /* Eject media */ +#define CTRL_FORMAT 8 /* Create physical format on the media */ + +/* MMC/SDC specific ioctl command */ +#define MMC_GET_TYPE 10 /* Get card type */ +#define MMC_GET_CSD 11 /* Get CSD */ +#define MMC_GET_CID 12 /* Get CID */ +#define MMC_GET_OCR 13 /* Get OCR */ +#define MMC_GET_SDSTAT 14 /* Get SD status */ +#define ISDIO_READ 55 /* Read data form SD iSDIO register */ +#define ISDIO_WRITE 56 /* Write data to SD iSDIO register */ +#define ISDIO_MRITE 57 /* Masked write data to SD iSDIO register */ + +/* ATA/CF specific ioctl command */ +#define ATA_GET_REV 20 /* Get F/W revision */ +#define ATA_GET_MODEL 21 /* Get model name */ +#define ATA_GET_SN 22 /* Get serial number */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib-hal/ff14b/source/ff.c b/lib-hal/ff14b/source/ff.c new file mode 100755 index 00000000..da05196d --- /dev/null +++ b/lib-hal/ff14b/source/ff.c @@ -0,0 +1,6987 @@ +#pragma GCC push_options +#pragma GCC optimize ("Os") +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wsign-conversion" +/*----------------------------------------------------------------------------/ +/ FatFs - Generic FAT Filesystem Module R0.14b / +/-----------------------------------------------------------------------------/ +/ +/ Copyright (C) 2021, ChaN, all right reserved. +/ +/ FatFs module is an open source software. Redistribution and use of FatFs in +/ source and binary forms, with or without modification, are permitted provided +/ that the following condition is met: +/ +/ 1. Redistributions of source code must retain the above copyright notice, +/ this condition and the following disclaimer. +/ +/ This software is provided by the copyright holder and contributors "AS IS" +/ and any warranties related to this software are DISCLAIMED. +/ The copyright owner or contributors be NOT LIABLE for any damages caused +/ by use of this software. +/ +/----------------------------------------------------------------------------*/ + + +#include +#include "ff.h" /* Declarations of FatFs API */ +#include "diskio.h" /* Declarations of device I/O functions */ + + +/*-------------------------------------------------------------------------- + + Module Private Definitions + +---------------------------------------------------------------------------*/ + +#if FF_DEFINED != 86631 /* Revision ID */ +#error Wrong include file (ff.h). +#endif + + +/* Limits and boundaries */ +#define MAX_DIR 0x200000 /* Max size of FAT directory */ +#define MAX_DIR_EX 0x10000000 /* Max size of exFAT directory */ +#define MAX_FAT12 0xFF5 /* Max FAT12 clusters (differs from specs, but right for real DOS/Windows behavior) */ +#define MAX_FAT16 0xFFF5 /* Max FAT16 clusters (differs from specs, but right for real DOS/Windows behavior) */ +#define MAX_FAT32 0x0FFFFFF5 /* Max FAT32 clusters (not specified, practical limit) */ +#define MAX_EXFAT 0x7FFFFFFD /* Max exFAT clusters (differs from specs, implementation limit) */ + + +/* Character code support macros */ +#define IsUpper(c) ((c) >= 'A' && (c) <= 'Z') +#define IsLower(c) ((c) >= 'a' && (c) <= 'z') +#define IsDigit(c) ((c) >= '0' && (c) <= '9') +#define IsSeparator(c) ((c) == '/' || (c) == '\\') +#define IsTerminator(c) ((UINT)(c) < (FF_USE_LFN ? ' ' : '!')) +#define IsSurrogate(c) ((c) >= 0xD800 && (c) <= 0xDFFF) +#define IsSurrogateH(c) ((c) >= 0xD800 && (c) <= 0xDBFF) +#define IsSurrogateL(c) ((c) >= 0xDC00 && (c) <= 0xDFFF) + + +/* Additional file access control and file status flags for internal use */ +#define FA_SEEKEND 0x20 /* Seek to end of the file on file open */ +#define FA_MODIFIED 0x40 /* File has been modified */ +#define FA_DIRTY 0x80 /* FIL.buf[] needs to be written-back */ + + +/* Additional file attribute bits for internal use */ +#define AM_VOL 0x08 /* Volume label */ +#define AM_LFN 0x0F /* LFN entry */ +#define AM_MASK 0x3F /* Mask of defined bits in FAT */ +#define AM_MASKX 0x37 /* Mask of defined bits in exFAT */ + + +/* Name status flags in fn[11] */ +#define NSFLAG 11 /* Index of the name status byte */ +#define NS_LOSS 0x01 /* Out of 8.3 format */ +#define NS_LFN 0x02 /* Force to create LFN entry */ +#define NS_LAST 0x04 /* Last segment */ +#define NS_BODY 0x08 /* Lower case flag (body) */ +#define NS_EXT 0x10 /* Lower case flag (ext) */ +#define NS_DOT 0x20 /* Dot entry */ +#define NS_NOLFN 0x40 /* Do not find LFN */ +#define NS_NONAME 0x80 /* Not followed */ + + +/* exFAT directory entry types */ +#define ET_BITMAP 0x81 /* Allocation bitmap */ +#define ET_UPCASE 0x82 /* Up-case table */ +#define ET_VLABEL 0x83 /* Volume label */ +#define ET_FILEDIR 0x85 /* File and directory */ +#define ET_STREAM 0xC0 /* Stream extension */ +#define ET_FILENAME 0xC1 /* Name extension */ + + +/* FatFs refers the FAT structure as simple byte array instead of structure member +/ because the C structure is not binary compatible between different platforms */ + +#define BS_JmpBoot 0 /* x86 jump instruction (3-byte) */ +#define BS_OEMName 3 /* OEM name (8-byte) */ +#define BPB_BytsPerSec 11 /* Sector size [byte] (WORD) */ +#define BPB_SecPerClus 13 /* Cluster size [sector] (BYTE) */ +#define BPB_RsvdSecCnt 14 /* Size of reserved area [sector] (WORD) */ +#define BPB_NumFATs 16 /* Number of FATs (BYTE) */ +#define BPB_RootEntCnt 17 /* Size of root directory area for FAT [entry] (WORD) */ +#define BPB_TotSec16 19 /* Volume size (16-bit) [sector] (WORD) */ +#define BPB_Media 21 /* Media descriptor byte (BYTE) */ +#define BPB_FATSz16 22 /* FAT size (16-bit) [sector] (WORD) */ +#define BPB_SecPerTrk 24 /* Number of sectors per track for int13h [sector] (WORD) */ +#define BPB_NumHeads 26 /* Number of heads for int13h (WORD) */ +#define BPB_HiddSec 28 /* Volume offset from top of the drive (DWORD) */ +#define BPB_TotSec32 32 /* Volume size (32-bit) [sector] (DWORD) */ +#define BS_DrvNum 36 /* Physical drive number for int13h (BYTE) */ +#define BS_NTres 37 /* WindowsNT error flag (BYTE) */ +#define BS_BootSig 38 /* Extended boot signature (BYTE) */ +#define BS_VolID 39 /* Volume serial number (DWORD) */ +#define BS_VolLab 43 /* Volume label string (8-byte) */ +#define BS_FilSysType 54 /* Filesystem type string (8-byte) */ +#define BS_BootCode 62 /* Boot code (448-byte) */ +#define BS_55AA 510 /* Signature word (WORD) */ + +#define BPB_FATSz32 36 /* FAT32: FAT size [sector] (DWORD) */ +#define BPB_ExtFlags32 40 /* FAT32: Extended flags (WORD) */ +#define BPB_FSVer32 42 /* FAT32: Filesystem version (WORD) */ +#define BPB_RootClus32 44 /* FAT32: Root directory cluster (DWORD) */ +#define BPB_FSInfo32 48 /* FAT32: Offset of FSINFO sector (WORD) */ +#define BPB_BkBootSec32 50 /* FAT32: Offset of backup boot sector (WORD) */ +#define BS_DrvNum32 64 /* FAT32: Physical drive number for int13h (BYTE) */ +#define BS_NTres32 65 /* FAT32: Error flag (BYTE) */ +#define BS_BootSig32 66 /* FAT32: Extended boot signature (BYTE) */ +#define BS_VolID32 67 /* FAT32: Volume serial number (DWORD) */ +#define BS_VolLab32 71 /* FAT32: Volume label string (8-byte) */ +#define BS_FilSysType32 82 /* FAT32: Filesystem type string (8-byte) */ +#define BS_BootCode32 90 /* FAT32: Boot code (420-byte) */ + +#define BPB_ZeroedEx 11 /* exFAT: MBZ field (53-byte) */ +#define BPB_VolOfsEx 64 /* exFAT: Volume offset from top of the drive [sector] (QWORD) */ +#define BPB_TotSecEx 72 /* exFAT: Volume size [sector] (QWORD) */ +#define BPB_FatOfsEx 80 /* exFAT: FAT offset from top of the volume [sector] (DWORD) */ +#define BPB_FatSzEx 84 /* exFAT: FAT size [sector] (DWORD) */ +#define BPB_DataOfsEx 88 /* exFAT: Data offset from top of the volume [sector] (DWORD) */ +#define BPB_NumClusEx 92 /* exFAT: Number of clusters (DWORD) */ +#define BPB_RootClusEx 96 /* exFAT: Root directory start cluster (DWORD) */ +#define BPB_VolIDEx 100 /* exFAT: Volume serial number (DWORD) */ +#define BPB_FSVerEx 104 /* exFAT: Filesystem version (WORD) */ +#define BPB_VolFlagEx 106 /* exFAT: Volume flags (WORD) */ +#define BPB_BytsPerSecEx 108 /* exFAT: Log2 of sector size in unit of byte (BYTE) */ +#define BPB_SecPerClusEx 109 /* exFAT: Log2 of cluster size in unit of sector (BYTE) */ +#define BPB_NumFATsEx 110 /* exFAT: Number of FATs (BYTE) */ +#define BPB_DrvNumEx 111 /* exFAT: Physical drive number for int13h (BYTE) */ +#define BPB_PercInUseEx 112 /* exFAT: Percent in use (BYTE) */ +#define BPB_RsvdEx 113 /* exFAT: Reserved (7-byte) */ +#define BS_BootCodeEx 120 /* exFAT: Boot code (390-byte) */ + +#define DIR_Name 0 /* Short file name (11-byte) */ +#define DIR_Attr 11 /* Attribute (BYTE) */ +#define DIR_NTres 12 /* Lower case flag (BYTE) */ +#define DIR_CrtTime10 13 /* Created time sub-second (BYTE) */ +#define DIR_CrtTime 14 /* Created time (DWORD) */ +#define DIR_LstAccDate 18 /* Last accessed date (WORD) */ +#define DIR_FstClusHI 20 /* Higher 16-bit of first cluster (WORD) */ +#define DIR_ModTime 22 /* Modified time (DWORD) */ +#define DIR_FstClusLO 26 /* Lower 16-bit of first cluster (WORD) */ +#define DIR_FileSize 28 /* File size (DWORD) */ +#define LDIR_Ord 0 /* LFN: LFN order and LLE flag (BYTE) */ +#define LDIR_Attr 11 /* LFN: LFN attribute (BYTE) */ +#define LDIR_Type 12 /* LFN: Entry type (BYTE) */ +#define LDIR_Chksum 13 /* LFN: Checksum of the SFN (BYTE) */ +#define LDIR_FstClusLO 26 /* LFN: MBZ field (WORD) */ +#define XDIR_Type 0 /* exFAT: Type of exFAT directory entry (BYTE) */ +#define XDIR_NumLabel 1 /* exFAT: Number of volume label characters (BYTE) */ +#define XDIR_Label 2 /* exFAT: Volume label (11-WORD) */ +#define XDIR_CaseSum 4 /* exFAT: Sum of case conversion table (DWORD) */ +#define XDIR_NumSec 1 /* exFAT: Number of secondary entries (BYTE) */ +#define XDIR_SetSum 2 /* exFAT: Sum of the set of directory entries (WORD) */ +#define XDIR_Attr 4 /* exFAT: File attribute (WORD) */ +#define XDIR_CrtTime 8 /* exFAT: Created time (DWORD) */ +#define XDIR_ModTime 12 /* exFAT: Modified time (DWORD) */ +#define XDIR_AccTime 16 /* exFAT: Last accessed time (DWORD) */ +#define XDIR_CrtTime10 20 /* exFAT: Created time subsecond (BYTE) */ +#define XDIR_ModTime10 21 /* exFAT: Modified time subsecond (BYTE) */ +#define XDIR_CrtTZ 22 /* exFAT: Created timezone (BYTE) */ +#define XDIR_ModTZ 23 /* exFAT: Modified timezone (BYTE) */ +#define XDIR_AccTZ 24 /* exFAT: Last accessed timezone (BYTE) */ +#define XDIR_GenFlags 33 /* exFAT: General secondary flags (BYTE) */ +#define XDIR_NumName 35 /* exFAT: Number of file name characters (BYTE) */ +#define XDIR_NameHash 36 /* exFAT: Hash of file name (WORD) */ +#define XDIR_ValidFileSize 40 /* exFAT: Valid file size (QWORD) */ +#define XDIR_FstClus 52 /* exFAT: First cluster of the file data (DWORD) */ +#define XDIR_FileSize 56 /* exFAT: File/Directory size (QWORD) */ + +#define SZDIRE 32 /* Size of a directory entry */ +#define DDEM 0xE5 /* Deleted directory entry mark set to DIR_Name[0] */ +#define RDDEM 0x05 /* Replacement of the character collides with DDEM */ +#define LLEF 0x40 /* Last long entry flag in LDIR_Ord */ + +#define FSI_LeadSig 0 /* FAT32 FSI: Leading signature (DWORD) */ +#define FSI_StrucSig 484 /* FAT32 FSI: Structure signature (DWORD) */ +#define FSI_Free_Count 488 /* FAT32 FSI: Number of free clusters (DWORD) */ +#define FSI_Nxt_Free 492 /* FAT32 FSI: Last allocated cluster (DWORD) */ + +#define MBR_Table 446 /* MBR: Offset of partition table in the MBR */ +#define SZ_PTE 16 /* MBR: Size of a partition table entry */ +#define PTE_Boot 0 /* MBR PTE: Boot indicator */ +#define PTE_StHead 1 /* MBR PTE: Start head */ +#define PTE_StSec 2 /* MBR PTE: Start sector */ +#define PTE_StCyl 3 /* MBR PTE: Start cylinder */ +#define PTE_System 4 /* MBR PTE: System ID */ +#define PTE_EdHead 5 /* MBR PTE: End head */ +#define PTE_EdSec 6 /* MBR PTE: End sector */ +#define PTE_EdCyl 7 /* MBR PTE: End cylinder */ +#define PTE_StLba 8 /* MBR PTE: Start in LBA */ +#define PTE_SizLba 12 /* MBR PTE: Size in LBA */ + +#define GPTH_Sign 0 /* GPT: Header signature (8-byte) */ +#define GPTH_Rev 8 /* GPT: Revision (DWORD) */ +#define GPTH_Size 12 /* GPT: Header size (DWORD) */ +#define GPTH_Bcc 16 /* GPT: Header BCC (DWORD) */ +#define GPTH_CurLba 24 /* GPT: Main header LBA (QWORD) */ +#define GPTH_BakLba 32 /* GPT: Backup header LBA (QWORD) */ +#define GPTH_FstLba 40 /* GPT: First LBA for partitions (QWORD) */ +#define GPTH_LstLba 48 /* GPT: Last LBA for partitions (QWORD) */ +#define GPTH_DskGuid 56 /* GPT: Disk GUID (16-byte) */ +#define GPTH_PtOfs 72 /* GPT: Partation table LBA (QWORD) */ +#define GPTH_PtNum 80 /* GPT: Number of table entries (DWORD) */ +#define GPTH_PteSize 84 /* GPT: Size of table entry (DWORD) */ +#define GPTH_PtBcc 88 /* GPT: Partation table BCC (DWORD) */ +#define SZ_GPTE 128 /* GPT: Size of partition table entry */ +#define GPTE_PtGuid 0 /* GPT PTE: Partition type GUID (16-byte) */ +#define GPTE_UpGuid 16 /* GPT PTE: Partition unique GUID (16-byte) */ +#define GPTE_FstLba 32 /* GPT PTE: First LBA (QWORD) */ +#define GPTE_LstLba 40 /* GPT PTE: Last LBA inclusive (QWORD) */ +#define GPTE_Flags 48 /* GPT PTE: Flags (QWORD) */ +#define GPTE_Name 56 /* GPT PTE: Name */ + + +/* Post process on fatal error in the file operations */ +#define ABORT(fs, res) { fp->err = (BYTE)(res); LEAVE_FF(fs, res); } + + +/* Re-entrancy related */ +#if FF_FS_REENTRANT +#if FF_USE_LFN == 1 +#error Static LFN work area cannot be used in thread-safe configuration +#endif +#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; } +#else +#define LEAVE_FF(fs, res) return res +#endif + + +/* Definitions of logical drive - physical location conversion */ +#if FF_MULTI_PARTITION +#define LD2PD(vol) VolToPart[vol].pd /* Get physical drive number */ +#define LD2PT(vol) VolToPart[vol].pt /* Get partition number (0:auto search, 1..:forced partition number) */ +#else +#define LD2PD(vol) (BYTE)(vol) /* Each logical drive is associated with the same physical drive number */ +#define LD2PT(vol) 0 /* Auto partition search */ +#endif + + +/* Definitions of sector size */ +#if (FF_MAX_SS < FF_MIN_SS) || (FF_MAX_SS != 512 && FF_MAX_SS != 1024 && FF_MAX_SS != 2048 && FF_MAX_SS != 4096) || (FF_MIN_SS != 512 && FF_MIN_SS != 1024 && FF_MIN_SS != 2048 && FF_MIN_SS != 4096) +#error Wrong sector size configuration +#endif +#if FF_MAX_SS == FF_MIN_SS +#define SS(fs) ((UINT)FF_MAX_SS) /* Fixed sector size */ +#else +#define SS(fs) ((fs)->ssize) /* Variable sector size */ +#endif + + +/* Timestamp */ +#if FF_FS_NORTC == 1 +#if FF_NORTC_YEAR < 1980 || FF_NORTC_YEAR > 2107 || FF_NORTC_MON < 1 || FF_NORTC_MON > 12 || FF_NORTC_MDAY < 1 || FF_NORTC_MDAY > 31 +#error Invalid FF_FS_NORTC settings +#endif +#define GET_FATTIME() ((DWORD)(FF_NORTC_YEAR - 1980) << 25 | (DWORD)FF_NORTC_MON << 21 | (DWORD)FF_NORTC_MDAY << 16) +#else +#define GET_FATTIME() get_fattime() +#endif + + +/* File lock controls */ +#if FF_FS_LOCK != 0 +#if FF_FS_READONLY +#error FF_FS_LOCK must be 0 at read-only configuration +#endif +typedef struct { + FATFS *fs; /* Object ID 1, volume (NULL:blank entry) */ + DWORD clu; /* Object ID 2, containing directory (0:root) */ + DWORD ofs; /* Object ID 3, offset in the directory */ + WORD ctr; /* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */ +} FILESEM; +#endif + + +/* SBCS up-case tables (\x80-\xFF) */ +#define TBL_CT437 {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ + 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT720 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT737 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \ + 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xEF,0xF5,0xF0,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT771 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDC,0xDE,0xDE, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFE,0xFF} +#define TBL_CT775 {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F, \ + 0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT850 {0x43,0x55,0x45,0x41,0x41,0x41,0x41,0x43,0x45,0x45,0x45,0x49,0x49,0x49,0x41,0x41, \ + 0x45,0x92,0x92,0x4F,0x4F,0x4F,0x55,0x55,0x59,0x4F,0x55,0x4F,0x9C,0x4F,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0x41,0x41,0x41,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0x41,0x41,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD1,0xD1,0x45,0x45,0x45,0x49,0x49,0x49,0x49,0xD9,0xDA,0xDB,0xDC,0xDD,0x49,0xDF, \ + 0x4F,0xE1,0x4F,0x4F,0x4F,0x4F,0xE6,0xE8,0xE8,0x55,0x55,0x55,0x59,0x59,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT852 {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0xAC, \ + 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF} +#define TBL_CT855 {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F, \ + 0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \ + 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \ + 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF, \ + 0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT857 {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x49,0x8E,0x8F, \ + 0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0x49,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT860 {0x80,0x9A,0x90,0x8F,0x8E,0x91,0x86,0x80,0x89,0x89,0x92,0x8B,0x8C,0x98,0x8E,0x8F, \ + 0x90,0x91,0x92,0x8C,0x99,0xA9,0x96,0x9D,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x86,0x8B,0x9F,0x96,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT861 {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x8B,0x8B,0x8D,0x8E,0x8F, \ + 0x90,0x92,0x92,0x4F,0x99,0x8D,0x55,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xA4,0xA5,0xA6,0xA7,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT862 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT863 {0x43,0x55,0x45,0x41,0x41,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x41,0x8F, \ + 0x45,0x45,0x45,0x4F,0x45,0x49,0x55,0x55,0x98,0x4F,0x55,0x9B,0x9C,0x55,0x55,0x9F, \ + 0xA0,0xA1,0x4F,0x55,0xA4,0xA5,0xA6,0xA7,0x49,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT864 {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ + 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT865 {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ + 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT866 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} +#define TBL_CT869 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x86,0x9C,0x8D,0x8F,0x90, \ + 0x91,0x90,0x92,0x95,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xA4,0xA5,0xA6,0xD9,0xDA,0xDB,0xDC,0xA7,0xA8,0xDF, \ + 0xA9,0xAA,0xAC,0xAD,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xCF,0xCF,0xD0,0xEF, \ + 0xF0,0xF1,0xD1,0xD2,0xD3,0xF5,0xD4,0xF7,0xF8,0xF9,0xD5,0x96,0x95,0x98,0xFE,0xFF} + + +/* DBCS code range |----- 1st byte -----| |----------- 2nd byte -----------| */ +/* <------> <------> <------> <------> <------> */ +#define TBL_DC932 {0x81, 0x9F, 0xE0, 0xFC, 0x40, 0x7E, 0x80, 0xFC, 0x00, 0x00} +#define TBL_DC936 {0x81, 0xFE, 0x00, 0x00, 0x40, 0x7E, 0x80, 0xFE, 0x00, 0x00} +#define TBL_DC949 {0x81, 0xFE, 0x00, 0x00, 0x41, 0x5A, 0x61, 0x7A, 0x81, 0xFE} +#define TBL_DC950 {0x81, 0xFE, 0x00, 0x00, 0x40, 0x7E, 0xA1, 0xFE, 0x00, 0x00} + + +/* Macros for table definitions */ +#define MERGE_2STR(a, b) a ## b +#define MKCVTBL(hd, cp) MERGE_2STR(hd, cp) + + + + +/*-------------------------------------------------------------------------- + + Module Private Work Area + +---------------------------------------------------------------------------*/ +/* Remark: Variables defined here without initial value shall be guaranteed +/ zero/null at start-up. If not, the linker option or start-up routine is +/ not compliance with C standard. */ + +/*--------------------------------*/ +/* File/Volume controls */ +/*--------------------------------*/ + +#if FF_VOLUMES < 1 || FF_VOLUMES > 10 +#error Wrong FF_VOLUMES setting +#endif +static FATFS* FatFs[FF_VOLUMES]; /* Pointer to the filesystem objects (logical drives) */ +static WORD Fsid; /* Filesystem mount ID */ + +#if FF_FS_RPATH != 0 +static BYTE CurrVol; /* Current drive */ +#endif + +#if FF_FS_LOCK != 0 +static FILESEM Files[FF_FS_LOCK]; /* Open object lock semaphores */ +#endif + +#if FF_STR_VOLUME_ID +#ifdef FF_VOLUME_STRS +static const char* const VolumeStr[FF_VOLUMES] = {FF_VOLUME_STRS}; /* Pre-defined volume ID */ +#endif +#endif + +#if FF_LBA64 +#if FF_MIN_GPT > 0x100000000 +#error Wrong FF_MIN_GPT setting +#endif +static const BYTE GUID_MS_Basic[16] = {0xA2,0xA0,0xD0,0xEB,0xE5,0xB9,0x33,0x44,0x87,0xC0,0x68,0xB6,0xB7,0x26,0x99,0xC7}; +#endif + + + +/*--------------------------------*/ +/* LFN/Directory working buffer */ +/*--------------------------------*/ + +#if FF_USE_LFN == 0 /* Non-LFN configuration */ +#if FF_FS_EXFAT +#error LFN must be enabled when enable exFAT +#endif +#define DEF_NAMBUF +#define INIT_NAMBUF(fs) +#define FREE_NAMBUF() +#define LEAVE_MKFS(res) return res + +#else /* LFN configurations */ +#if FF_MAX_LFN < 12 || FF_MAX_LFN > 255 +#error Wrong setting of FF_MAX_LFN +#endif +#if FF_LFN_BUF < FF_SFN_BUF || FF_SFN_BUF < 12 +#error Wrong setting of FF_LFN_BUF or FF_SFN_BUF +#endif +#if FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3 +#error Wrong setting of FF_LFN_UNICODE +#endif +static const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* FAT: Offset of LFN characters in the directory entry */ +#define MAXDIRB(nc) ((nc + 44U) / 15 * SZDIRE) /* exFAT: Size of directory entry block scratchpad buffer needed for the name length */ + +#if FF_USE_LFN == 1 /* LFN enabled with static working buffer */ +#if FF_FS_EXFAT +static BYTE DirBuf[MAXDIRB(FF_MAX_LFN)]; /* Directory entry block scratchpad buffer */ +#endif +static WCHAR LfnBuf[FF_MAX_LFN + 1]; /* LFN working buffer */ +#define DEF_NAMBUF +#define INIT_NAMBUF(fs) +#define FREE_NAMBUF() +#define LEAVE_MKFS(res) return res + +#elif FF_USE_LFN == 2 /* LFN enabled with dynamic working buffer on the stack */ +#if FF_FS_EXFAT +#define DEF_NAMBUF WCHAR lbuf[FF_MAX_LFN+1]; BYTE dbuf[MAXDIRB(FF_MAX_LFN)]; /* LFN working buffer and directory entry block scratchpad buffer */ +#define INIT_NAMBUF(fs) { (fs)->lfnbuf = lbuf; (fs)->dirbuf = dbuf; } +#define FREE_NAMBUF() +#else +#define DEF_NAMBUF WCHAR lbuf[FF_MAX_LFN+1]; /* LFN working buffer */ +#define INIT_NAMBUF(fs) { (fs)->lfnbuf = lbuf; } +#define FREE_NAMBUF() +#endif +#define LEAVE_MKFS(res) return res + +#elif FF_USE_LFN == 3 /* LFN enabled with dynamic working buffer on the heap */ +#if FF_FS_EXFAT +#define DEF_NAMBUF WCHAR *lfn; /* Pointer to LFN working buffer and directory entry block scratchpad buffer */ +#define INIT_NAMBUF(fs) { lfn = ff_memalloc((FF_MAX_LFN+1)*2 + MAXDIRB(FF_MAX_LFN)); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; (fs)->dirbuf = (BYTE*)(lfn+FF_MAX_LFN+1); } +#define FREE_NAMBUF() ff_memfree(lfn) +#else +#define DEF_NAMBUF WCHAR *lfn; /* Pointer to LFN working buffer */ +#define INIT_NAMBUF(fs) { lfn = ff_memalloc((FF_MAX_LFN+1)*2); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; } +#define FREE_NAMBUF() ff_memfree(lfn) +#endif +#define LEAVE_MKFS(res) { if (!work) ff_memfree(buf); return res; } +#define MAX_MALLOC 0x8000 /* Must be >=FF_MAX_SS */ + +#else +#error Wrong setting of FF_USE_LFN + +#endif /* FF_USE_LFN == 1 */ +#endif /* FF_USE_LFN == 0 */ + + + +/*--------------------------------*/ +/* Code conversion tables */ +/*--------------------------------*/ + +#if FF_CODE_PAGE == 0 /* Run-time code page configuration */ +#define CODEPAGE CodePage +static WORD CodePage; /* Current code page */ +static const BYTE *ExCvt, *DbcTbl; /* Pointer to current SBCS up-case table and DBCS code range table below */ + +static const BYTE Ct437[] = TBL_CT437; +static const BYTE Ct720[] = TBL_CT720; +static const BYTE Ct737[] = TBL_CT737; +static const BYTE Ct771[] = TBL_CT771; +static const BYTE Ct775[] = TBL_CT775; +static const BYTE Ct850[] = TBL_CT850; +static const BYTE Ct852[] = TBL_CT852; +static const BYTE Ct855[] = TBL_CT855; +static const BYTE Ct857[] = TBL_CT857; +static const BYTE Ct860[] = TBL_CT860; +static const BYTE Ct861[] = TBL_CT861; +static const BYTE Ct862[] = TBL_CT862; +static const BYTE Ct863[] = TBL_CT863; +static const BYTE Ct864[] = TBL_CT864; +static const BYTE Ct865[] = TBL_CT865; +static const BYTE Ct866[] = TBL_CT866; +static const BYTE Ct869[] = TBL_CT869; +static const BYTE Dc932[] = TBL_DC932; +static const BYTE Dc936[] = TBL_DC936; +static const BYTE Dc949[] = TBL_DC949; +static const BYTE Dc950[] = TBL_DC950; + +#elif FF_CODE_PAGE < 900 /* Static code page configuration (SBCS) */ +#define CODEPAGE FF_CODE_PAGE +static const BYTE ExCvt[] = MKCVTBL(TBL_CT, FF_CODE_PAGE); + +#else /* Static code page configuration (DBCS) */ +#define CODEPAGE FF_CODE_PAGE +static const BYTE DbcTbl[] = MKCVTBL(TBL_DC, FF_CODE_PAGE); + +#endif + + + + +/*-------------------------------------------------------------------------- + + Module Private Functions + +---------------------------------------------------------------------------*/ + + +/*-----------------------------------------------------------------------*/ +/* Load/Store multi-byte word in the FAT structure */ +/*-----------------------------------------------------------------------*/ + +static WORD ld_word (const BYTE* ptr) /* Load a 2-byte little-endian word */ +{ + WORD rv; + + rv = ptr[1]; + rv = rv << 8 | ptr[0]; + return rv; +} + +static DWORD ld_dword (const BYTE* ptr) /* Load a 4-byte little-endian word */ +{ + DWORD rv; + + rv = ptr[3]; + rv = rv << 8 | ptr[2]; + rv = rv << 8 | ptr[1]; + rv = rv << 8 | ptr[0]; + return rv; +} + +#if FF_FS_EXFAT +static QWORD ld_qword (const BYTE* ptr) /* Load an 8-byte little-endian word */ +{ + QWORD rv; + + rv = ptr[7]; + rv = rv << 8 | ptr[6]; + rv = rv << 8 | ptr[5]; + rv = rv << 8 | ptr[4]; + rv = rv << 8 | ptr[3]; + rv = rv << 8 | ptr[2]; + rv = rv << 8 | ptr[1]; + rv = rv << 8 | ptr[0]; + return rv; +} +#endif + +#if !FF_FS_READONLY +static void st_word (BYTE* ptr, WORD val) /* Store a 2-byte word in little-endian */ +{ + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; +} + +static void st_dword (BYTE* ptr, DWORD val) /* Store a 4-byte word in little-endian */ +{ + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; +} + +#if FF_FS_EXFAT +static void st_qword (BYTE* ptr, QWORD val) /* Store an 8-byte word in little-endian */ +{ + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; val >>= 8; + *ptr++ = (BYTE)val; +} +#endif +#endif /* !FF_FS_READONLY */ + + + +/*-----------------------------------------------------------------------*/ +/* String functions */ +/*-----------------------------------------------------------------------*/ + +/* Test if the byte is DBC 1st byte */ +static int dbc_1st (BYTE c) +{ +#if FF_CODE_PAGE == 0 /* Variable code page */ + if (DbcTbl && c >= DbcTbl[0]) { + if (c <= DbcTbl[1]) return 1; /* 1st byte range 1 */ + if (c >= DbcTbl[2] && c <= DbcTbl[3]) return 1; /* 1st byte range 2 */ + } +#elif FF_CODE_PAGE >= 900 /* DBCS fixed code page */ + if (c >= DbcTbl[0]) { + if (c <= DbcTbl[1]) return 1; + if (c >= DbcTbl[2] && c <= DbcTbl[3]) return 1; + } +#else /* SBCS fixed code page */ + if (c != 0) return 0; /* Always false */ +#endif + return 0; +} + + +/* Test if the byte is DBC 2nd byte */ +static int dbc_2nd (BYTE c) +{ +#if FF_CODE_PAGE == 0 /* Variable code page */ + if (DbcTbl && c >= DbcTbl[4]) { + if (c <= DbcTbl[5]) return 1; /* 2nd byte range 1 */ + if (c >= DbcTbl[6] && c <= DbcTbl[7]) return 1; /* 2nd byte range 2 */ + if (c >= DbcTbl[8] && c <= DbcTbl[9]) return 1; /* 2nd byte range 3 */ + } +#elif FF_CODE_PAGE >= 900 /* DBCS fixed code page */ + if (c >= DbcTbl[4]) { + if (c <= DbcTbl[5]) return 1; + if (c >= DbcTbl[6] && c <= DbcTbl[7]) return 1; + if (c >= DbcTbl[8] && c <= DbcTbl[9]) return 1; + } +#else /* SBCS fixed code page */ + if (c != 0) return 0; /* Always false */ +#endif + return 0; +} + + +#if FF_USE_LFN + +/* Get a Unicode code point from the TCHAR string in defined API encodeing */ +static DWORD tchar2uni ( /* Returns a character in UTF-16 encoding (>=0x10000 on surrogate pair, 0xFFFFFFFF on decode error) */ + const TCHAR** str /* Pointer to pointer to TCHAR string in configured encoding */ +) +{ + DWORD uc; + const TCHAR *p = *str; + +#if FF_LFN_UNICODE == 1 /* UTF-16 input */ + WCHAR wc; + + uc = *p++; /* Get a unit */ + if (IsSurrogate(uc)) { /* Surrogate? */ + wc = *p++; /* Get low surrogate */ + if (!IsSurrogateH(uc) || !IsSurrogateL(wc)) return 0xFFFFFFFF; /* Wrong surrogate? */ + uc = uc << 16 | wc; + } + +#elif FF_LFN_UNICODE == 2 /* UTF-8 input */ + BYTE b; + int nf; + + uc = (BYTE)*p++; /* Get an encoding unit */ + if (uc & 0x80) { /* Multiple byte code? */ + if ((uc & 0xE0) == 0xC0) { /* 2-byte sequence? */ + uc &= 0x1F; nf = 1; + } else if ((uc & 0xF0) == 0xE0) { /* 3-byte sequence? */ + uc &= 0x0F; nf = 2; + } else if ((uc & 0xF8) == 0xF0) { /* 4-byte sequence? */ + uc &= 0x07; nf = 3; + } else { /* Wrong sequence */ + return 0xFFFFFFFF; + } + do { /* Get trailing bytes */ + b = (BYTE)*p++; + if ((b & 0xC0) != 0x80) return 0xFFFFFFFF; /* Wrong sequence? */ + uc = uc << 6 | (b & 0x3F); + } while (--nf != 0); + if (uc < 0x80 || IsSurrogate(uc) || uc >= 0x110000) return 0xFFFFFFFF; /* Wrong code? */ + if (uc >= 0x010000) uc = 0xD800DC00 | ((uc - 0x10000) << 6 & 0x3FF0000) | (uc & 0x3FF); /* Make a surrogate pair if needed */ + } + +#elif FF_LFN_UNICODE == 3 /* UTF-32 input */ + uc = (TCHAR)*p++; /* Get a unit */ + if (uc >= 0x110000 || IsSurrogate(uc)) return 0xFFFFFFFF; /* Wrong code? */ + if (uc >= 0x010000) uc = 0xD800DC00 | ((uc - 0x10000) << 6 & 0x3FF0000) | (uc & 0x3FF); /* Make a surrogate pair if needed */ + +#else /* ANSI/OEM input */ + BYTE b; + WCHAR wc; + + wc = (BYTE)*p++; /* Get a byte */ + if (dbc_1st((BYTE)wc)) { /* Is it a DBC 1st byte? */ + b = (BYTE)*p++; /* Get 2nd byte */ + if (!dbc_2nd(b)) return 0xFFFFFFFF; /* Invalid code? */ + wc = (wc << 8) + b; /* Make a DBC */ + } + if (wc != 0) { + wc = ff_oem2uni(wc, CODEPAGE); /* ANSI/OEM ==> Unicode */ + if (wc == 0) return 0xFFFFFFFF; /* Invalid code? */ + } + uc = wc; + +#endif + *str = p; /* Next read pointer */ + return uc; +} + + +/* Store a Unicode char in defined API encoding */ +static UINT put_utf ( /* Returns number of encoding units written (0:buffer overflow or wrong encoding) */ + DWORD chr, /* UTF-16 encoded character (Surrogate pair if >=0x10000) */ + TCHAR* buf, /* Output buffer */ + UINT szb /* Size of the buffer */ +) +{ +#if FF_LFN_UNICODE == 1 /* UTF-16 output */ + WCHAR hs, wc; + + hs = (WCHAR)(chr >> 16); + wc = (WCHAR)chr; + if (hs == 0) { /* Single encoding unit? */ + if (szb < 1 || IsSurrogate(wc)) return 0; /* Buffer overflow or wrong code? */ + *buf = wc; + return 1; + } + if (szb < 2 || !IsSurrogateH(hs) || !IsSurrogateL(wc)) return 0; /* Buffer overflow or wrong surrogate? */ + *buf++ = hs; + *buf++ = wc; + return 2; + +#elif FF_LFN_UNICODE == 2 /* UTF-8 output */ + DWORD hc; + + if (chr < 0x80) { /* Single byte code? */ + if (szb < 1) return 0; /* Buffer overflow? */ + *buf = (TCHAR)chr; + return 1; + } + if (chr < 0x800) { /* 2-byte sequence? */ + if (szb < 2) return 0; /* Buffer overflow? */ + *buf++ = (TCHAR)(0xC0 | (chr >> 6 & 0x1F)); + *buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F)); + return 2; + } + if (chr < 0x10000) { /* 3-byte sequence? */ + if (szb < 3 || IsSurrogate(chr)) return 0; /* Buffer overflow or wrong code? */ + *buf++ = (TCHAR)(0xE0 | (chr >> 12 & 0x0F)); + *buf++ = (TCHAR)(0x80 | (chr >> 6 & 0x3F)); + *buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F)); + return 3; + } + /* 4-byte sequence */ + if (szb < 4) return 0; /* Buffer overflow? */ + hc = ((chr & 0xFFFF0000) - 0xD8000000) >> 6; /* Get high 10 bits */ + chr = (chr & 0xFFFF) - 0xDC00; /* Get low 10 bits */ + if (hc >= 0x100000 || chr >= 0x400) return 0; /* Wrong surrogate? */ + chr = (hc | chr) + 0x10000; + *buf++ = (TCHAR)(0xF0 | (chr >> 18 & 0x07)); + *buf++ = (TCHAR)(0x80 | (chr >> 12 & 0x3F)); + *buf++ = (TCHAR)(0x80 | (chr >> 6 & 0x3F)); + *buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F)); + return 4; + +#elif FF_LFN_UNICODE == 3 /* UTF-32 output */ + DWORD hc; + + if (szb < 1) return 0; /* Buffer overflow? */ + if (chr >= 0x10000) { /* Out of BMP? */ + hc = ((chr & 0xFFFF0000) - 0xD8000000) >> 6; /* Get high 10 bits */ + chr = (chr & 0xFFFF) - 0xDC00; /* Get low 10 bits */ + if (hc >= 0x100000 || chr >= 0x400) return 0; /* Wrong surrogate? */ + chr = (hc | chr) + 0x10000; + } + *buf++ = (TCHAR)chr; + return 1; + +#else /* ANSI/OEM output */ + WCHAR wc; + + wc = ff_uni2oem(chr, CODEPAGE); + if (wc >= 0x100) { /* Is this a DBC? */ + if (szb < 2) return 0; + *buf++ = (char)(wc >> 8); /* Store DBC 1st byte */ + *buf++ = (TCHAR)wc; /* Store DBC 2nd byte */ + return 2; + } + if (wc == 0 || szb < 1) return 0; /* Invalid char or buffer overflow? */ + *buf++ = (TCHAR)wc; /* Store the character */ + return 1; +#endif +} +#endif /* FF_USE_LFN */ + + +#if FF_FS_REENTRANT +/*-----------------------------------------------------------------------*/ +/* Request/Release grant to access the volume */ +/*-----------------------------------------------------------------------*/ +static int lock_fs ( /* 1:Ok, 0:timeout */ + FATFS* fs /* Filesystem object */ +) +{ + return ff_req_grant(fs->sobj); +} + + +static void unlock_fs ( + FATFS* fs, /* Filesystem object */ + FRESULT res /* Result code to be returned */ +) +{ + if (fs && res != FR_NOT_ENABLED && res != FR_INVALID_DRIVE && res != FR_TIMEOUT) { + ff_rel_grant(fs->sobj); + } +} + +#endif + + + +#if FF_FS_LOCK != 0 +/*-----------------------------------------------------------------------*/ +/* File lock control functions */ +/*-----------------------------------------------------------------------*/ + +static FRESULT chk_lock ( /* Check if the file can be accessed */ + DIR* dp, /* Directory object pointing the file to be checked */ + int acc /* Desired access type (0:Read mode open, 1:Write mode open, 2:Delete or rename) */ +) +{ + UINT i, be; + + /* Search open object table for the object */ + be = 0; + for (i = 0; i < FF_FS_LOCK; i++) { + if (Files[i].fs) { /* Existing entry */ + if (Files[i].fs == dp->obj.fs && /* Check if the object matches with an open object */ + Files[i].clu == dp->obj.sclust && + Files[i].ofs == dp->dptr) break; + } else { /* Blank entry */ + be = 1; + } + } + if (i == FF_FS_LOCK) { /* The object has not been opened */ + return (!be && acc != 2) ? FR_TOO_MANY_OPEN_FILES : FR_OK; /* Is there a blank entry for new object? */ + } + + /* The object was opened. Reject any open against writing file and all write mode open */ + return (acc != 0 || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK; +} + + +static int enq_lock (void) /* Check if an entry is available for a new object */ +{ + UINT i; + + for (i = 0; i < FF_FS_LOCK && Files[i].fs; i++) ; + return (i == FF_FS_LOCK) ? 0 : 1; +} + + +static UINT inc_lock ( /* Increment object open counter and returns its index (0:Internal error) */ + DIR* dp, /* Directory object pointing the file to register or increment */ + int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ +) +{ + UINT i; + + + for (i = 0; i < FF_FS_LOCK; i++) { /* Find the object */ + if (Files[i].fs == dp->obj.fs + && Files[i].clu == dp->obj.sclust + && Files[i].ofs == dp->dptr) break; + } + + if (i == FF_FS_LOCK) { /* Not opened. Register it as new. */ + for (i = 0; i < FF_FS_LOCK && Files[i].fs; i++) ; + if (i == FF_FS_LOCK) return 0; /* No free entry to register (int err) */ + Files[i].fs = dp->obj.fs; + Files[i].clu = dp->obj.sclust; + Files[i].ofs = dp->dptr; + Files[i].ctr = 0; + } + + if (acc >= 1 && Files[i].ctr) return 0; /* Access violation (int err) */ + + Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */ + + return i + 1; /* Index number origin from 1 */ +} + + +static FRESULT dec_lock ( /* Decrement object open counter */ + UINT i /* Semaphore index (1..) */ +) +{ + WORD n; + FRESULT res; + + + if (--i < FF_FS_LOCK) { /* Index number origin from 0 */ + n = Files[i].ctr; + if (n == 0x100) n = 0; /* If write mode open, delete the entry */ + if (n > 0) n--; /* Decrement read mode open count */ + Files[i].ctr = n; + if (n == 0) Files[i].fs = 0; /* Delete the entry if open count gets zero */ + res = FR_OK; + } else { + res = FR_INT_ERR; /* Invalid index nunber */ + } + return res; +} + + +static void clear_lock ( /* Clear lock entries of the volume */ + FATFS *fs +) +{ + UINT i; + + for (i = 0; i < FF_FS_LOCK; i++) { + if (Files[i].fs == fs) Files[i].fs = 0; + } +} + +#endif /* FF_FS_LOCK != 0 */ + + + +/*-----------------------------------------------------------------------*/ +/* Move/Flush disk access window in the filesystem object */ +/*-----------------------------------------------------------------------*/ +#if !FF_FS_READONLY +static FRESULT sync_window ( /* Returns FR_OK or FR_DISK_ERR */ + FATFS* fs /* Filesystem object */ +) +{ + FRESULT res = FR_OK; + + + if (fs->wflag) { /* Is the disk access window dirty? */ + if (disk_write(fs->pdrv, fs->win, fs->winsect, 1) == RES_OK) { /* Write it back into the volume */ + fs->wflag = 0; /* Clear window dirty flag */ + if (fs->winsect - fs->fatbase < fs->fsize) { /* Is it in the 1st FAT? */ + if (fs->n_fats == 2) disk_write(fs->pdrv, fs->win, fs->winsect + fs->fsize, 1); /* Reflect it to 2nd FAT if needed */ + } + } else { + res = FR_DISK_ERR; + } + } + return res; +} +#endif + + +static FRESULT move_window ( /* Returns FR_OK or FR_DISK_ERR */ + FATFS* fs, /* Filesystem object */ + LBA_t sect /* Sector LBA to make appearance in the fs->win[] */ +) +{ + FRESULT res = FR_OK; + + + if (sect != fs->winsect) { /* Window offset changed? */ +#if !FF_FS_READONLY + res = sync_window(fs); /* Flush the window */ +#endif + if (res == FR_OK) { /* Fill sector window with new data */ + if (disk_read(fs->pdrv, fs->win, sect, 1) != RES_OK) { + sect = (LBA_t)0 - 1; /* Invalidate window if read data is not valid */ + res = FR_DISK_ERR; + } + fs->winsect = sect; + } + } + return res; +} + + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Synchronize filesystem and data on the storage */ +/*-----------------------------------------------------------------------*/ + +static FRESULT sync_fs ( /* Returns FR_OK or FR_DISK_ERR */ + FATFS* fs /* Filesystem object */ +) +{ + FRESULT res; + + + res = sync_window(fs); + if (res == FR_OK) { + if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) { /* FAT32: Update FSInfo sector if needed */ + /* Create FSInfo structure */ + memset(fs->win, 0, sizeof fs->win); + st_word(fs->win + BS_55AA, 0xAA55); /* Boot signature */ + st_dword(fs->win + FSI_LeadSig, 0x41615252); /* Leading signature */ + st_dword(fs->win + FSI_StrucSig, 0x61417272); /* Structure signature */ + st_dword(fs->win + FSI_Free_Count, fs->free_clst); /* Number of free clusters */ + st_dword(fs->win + FSI_Nxt_Free, fs->last_clst); /* Last allocated culuster */ + fs->winsect = fs->volbase + 1; /* Write it into the FSInfo sector (Next to VBR) */ + disk_write(fs->pdrv, fs->win, fs->winsect, 1); + fs->fsi_flag = 0; + } + /* Make sure that no pending write process in the lower layer */ + if (disk_ioctl(fs->pdrv, CTRL_SYNC, 0) != RES_OK) res = FR_DISK_ERR; + } + + return res; +} + +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Get physical sector number from cluster number */ +/*-----------------------------------------------------------------------*/ + +static LBA_t clst2sect ( /* !=0:Sector number, 0:Failed (invalid cluster#) */ + FATFS* fs, /* Filesystem object */ + DWORD clst /* Cluster# to be converted */ +) +{ + clst -= 2; /* Cluster number is origin from 2 */ + if (clst >= fs->n_fatent - 2) return 0; /* Is it invalid cluster number? */ + return fs->database + (LBA_t)fs->csize * clst; /* Start sector number of the cluster */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* FAT access - Read value of an FAT entry */ +/*-----------------------------------------------------------------------*/ + +static DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x7FFFFFFF:Cluster status */ + FFOBJID* obj, /* Corresponding object */ + DWORD clst /* Cluster number to get the value */ +) +{ + UINT wc, bc; + DWORD val; + FATFS *fs = obj->fs; + + + if (clst < 2 || clst >= fs->n_fatent) { /* Check if in valid range */ + val = 1; /* Internal error */ + + } else { + val = 0xFFFFFFFF; /* Default value falls on disk error */ + + switch (fs->fs_type) { + case FS_FAT12 : + bc = (UINT)clst; bc += bc / 2; + if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; + wc = fs->win[bc++ % SS(fs)]; /* Get 1st byte of the entry */ + if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; + wc |= fs->win[bc % SS(fs)] << 8; /* Merge 2nd byte of the entry */ + val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF); /* Adjust bit position */ + break; + + case FS_FAT16 : + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break; + val = ld_word(fs->win + clst * 2 % SS(fs)); /* Simple WORD array */ + break; + + case FS_FAT32 : + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break; + val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF; /* Simple DWORD array but mask out upper 4 bits */ + break; +#if FF_FS_EXFAT + case FS_EXFAT : + if ((obj->objsize != 0 && obj->sclust != 0) || obj->stat == 0) { /* Object except root dir must have valid data length */ + DWORD cofs = clst - obj->sclust; /* Offset from start cluster */ + DWORD clen = (DWORD)((LBA_t)((obj->objsize - 1) / SS(fs)) / fs->csize); /* Number of clusters - 1 */ + + if (obj->stat == 2 && cofs <= clen) { /* Is it a contiguous chain? */ + val = (cofs == clen) ? 0x7FFFFFFF : clst + 1; /* No data on the FAT, generate the value */ + break; + } + if (obj->stat == 3 && cofs < obj->n_cont) { /* Is it in the 1st fragment? */ + val = clst + 1; /* Generate the value */ + break; + } + if (obj->stat != 2) { /* Get value from FAT if FAT chain is valid */ + if (obj->n_frag != 0) { /* Is it on the growing edge? */ + val = 0x7FFFFFFF; /* Generate EOC */ + } else { + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break; + val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x7FFFFFFF; + } + break; + } + } + val = 1; /* Internal error */ + break; +#endif + default: + val = 1; /* Internal error */ + } + } + + return val; +} + + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* FAT access - Change value of an FAT entry */ +/*-----------------------------------------------------------------------*/ + +static FRESULT put_fat ( /* FR_OK(0):succeeded, !=0:error */ + FATFS* fs, /* Corresponding filesystem object */ + DWORD clst, /* FAT index number (cluster number) to be changed */ + DWORD val /* New value to be set to the entry */ +) +{ + UINT bc; + BYTE *p; + FRESULT res = FR_INT_ERR; + + + if (clst >= 2 && clst < fs->n_fatent) { /* Check if in valid range */ + switch (fs->fs_type) { + case FS_FAT12: + bc = (UINT)clst; bc += bc / 2; /* bc: byte offset of the entry */ + res = move_window(fs, fs->fatbase + (bc / SS(fs))); + if (res != FR_OK) break; + p = fs->win + bc++ % SS(fs); + *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; /* Update 1st byte */ + fs->wflag = 1; + res = move_window(fs, fs->fatbase + (bc / SS(fs))); + if (res != FR_OK) break; + p = fs->win + bc % SS(fs); + *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); /* Update 2nd byte */ + fs->wflag = 1; + break; + + case FS_FAT16: + res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))); + if (res != FR_OK) break; + st_word(fs->win + clst * 2 % SS(fs), (WORD)val); /* Simple WORD array */ + fs->wflag = 1; + break; + + case FS_FAT32: +#if FF_FS_EXFAT + case FS_EXFAT: +#endif + res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))); + if (res != FR_OK) break; + if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) { + val = (val & 0x0FFFFFFF) | (ld_dword(fs->win + clst * 4 % SS(fs)) & 0xF0000000); + } + st_dword(fs->win + clst * 4 % SS(fs), val); + fs->wflag = 1; + break; + } + } + return res; +} + +#endif /* !FF_FS_READONLY */ + + + + +#if FF_FS_EXFAT && !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* exFAT: Accessing FAT and Allocation Bitmap */ +/*-----------------------------------------------------------------------*/ + +/*--------------------------------------*/ +/* Find a contiguous free cluster block */ +/*--------------------------------------*/ + +static DWORD find_bitmap ( /* 0:Not found, 2..:Cluster block found, 0xFFFFFFFF:Disk error */ + FATFS* fs, /* Filesystem object */ + DWORD clst, /* Cluster number to scan from */ + DWORD ncl /* Number of contiguous clusters to find (1..) */ +) +{ + BYTE bm, bv; + UINT i; + DWORD val, scl, ctr; + + + clst -= 2; /* The first bit in the bitmap corresponds to cluster #2 */ + if (clst >= fs->n_fatent - 2) clst = 0; + scl = val = clst; ctr = 0; + for (;;) { + if (move_window(fs, fs->bitbase + val / 8 / SS(fs)) != FR_OK) return 0xFFFFFFFF; + i = val / 8 % SS(fs); bm = 1 << (val % 8); + do { + do { + bv = fs->win[i] & bm; bm <<= 1; /* Get bit value */ + if (++val >= fs->n_fatent - 2) { /* Next cluster (with wrap-around) */ + val = 0; bm = 0; i = SS(fs); + } + if (bv == 0) { /* Is it a free cluster? */ + if (++ctr == ncl) return scl + 2; /* Check if run length is sufficient for required */ + } else { + scl = val; ctr = 0; /* Encountered a cluster in-use, restart to scan */ + } + if (val == clst) return 0; /* All cluster scanned? */ + } while (bm != 0); + bm = 1; + } while (++i < SS(fs)); + } +} + + +/*----------------------------------------*/ +/* Set/Clear a block of allocation bitmap */ +/*----------------------------------------*/ + +static FRESULT change_bitmap ( + FATFS* fs, /* Filesystem object */ + DWORD clst, /* Cluster number to change from */ + DWORD ncl, /* Number of clusters to be changed */ + int bv /* bit value to be set (0 or 1) */ +) +{ + BYTE bm; + UINT i; + LBA_t sect; + + + clst -= 2; /* The first bit corresponds to cluster #2 */ + sect = fs->bitbase + clst / 8 / SS(fs); /* Sector address */ + i = clst / 8 % SS(fs); /* Byte offset in the sector */ + bm = 1 << (clst % 8); /* Bit mask in the byte */ + for (;;) { + if (move_window(fs, sect++) != FR_OK) return FR_DISK_ERR; + do { + do { + if (bv == (int)((fs->win[i] & bm) != 0)) return FR_INT_ERR; /* Is the bit expected value? */ + fs->win[i] ^= bm; /* Flip the bit */ + fs->wflag = 1; + if (--ncl == 0) return FR_OK; /* All bits processed? */ + } while (bm <<= 1); /* Next bit */ + bm = 1; + } while (++i < SS(fs)); /* Next byte */ + i = 0; + } +} + + +/*---------------------------------------------*/ +/* Fill the first fragment of the FAT chain */ +/*---------------------------------------------*/ + +static FRESULT fill_first_frag ( + FFOBJID* obj /* Pointer to the corresponding object */ +) +{ + FRESULT res; + DWORD cl, n; + + + if (obj->stat == 3) { /* Has the object been changed 'fragmented' in this session? */ + for (cl = obj->sclust, n = obj->n_cont; n; cl++, n--) { /* Create cluster chain on the FAT */ + res = put_fat(obj->fs, cl, cl + 1); + if (res != FR_OK) return res; + } + obj->stat = 0; /* Change status 'FAT chain is valid' */ + } + return FR_OK; +} + + +/*---------------------------------------------*/ +/* Fill the last fragment of the FAT chain */ +/*---------------------------------------------*/ + +static FRESULT fill_last_frag ( + FFOBJID* obj, /* Pointer to the corresponding object */ + DWORD lcl, /* Last cluster of the fragment */ + DWORD term /* Value to set the last FAT entry */ +) +{ + FRESULT res; + + + while (obj->n_frag > 0) { /* Create the chain of last fragment */ + res = put_fat(obj->fs, lcl - obj->n_frag + 1, (obj->n_frag > 1) ? lcl - obj->n_frag + 2 : term); + if (res != FR_OK) return res; + obj->n_frag--; + } + return FR_OK; +} + +#endif /* FF_FS_EXFAT && !FF_FS_READONLY */ + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* FAT handling - Remove a cluster chain */ +/*-----------------------------------------------------------------------*/ + +static FRESULT remove_chain ( /* FR_OK(0):succeeded, !=0:error */ + FFOBJID* obj, /* Corresponding object */ + DWORD clst, /* Cluster to remove a chain from */ + DWORD pclst /* Previous cluster of clst (0 if entire chain) */ +) +{ + FRESULT res = FR_OK; + DWORD nxt; + FATFS *fs = obj->fs; +#if FF_FS_EXFAT || FF_USE_TRIM + DWORD scl = clst, ecl = clst; +#endif +#if FF_USE_TRIM + LBA_t rt[2]; +#endif + + if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Check if in valid range */ + + /* Mark the previous cluster 'EOC' on the FAT if it exists */ + if (pclst != 0 && (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT || obj->stat != 2)) { + res = put_fat(fs, pclst, 0xFFFFFFFF); + if (res != FR_OK) return res; + } + + /* Remove the chain */ + do { + nxt = get_fat(obj, clst); /* Get cluster status */ + if (nxt == 0) break; /* Empty cluster? */ + if (nxt == 1) return FR_INT_ERR; /* Internal error? */ + if (nxt == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error? */ + if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) { + res = put_fat(fs, clst, 0); /* Mark the cluster 'free' on the FAT */ + if (res != FR_OK) return res; + } + if (fs->free_clst < fs->n_fatent - 2) { /* Update FSINFO */ + fs->free_clst++; + fs->fsi_flag |= 1; + } +#if FF_FS_EXFAT || FF_USE_TRIM + if (ecl + 1 == nxt) { /* Is next cluster contiguous? */ + ecl = nxt; + } else { /* End of contiguous cluster block */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + res = change_bitmap(fs, scl, ecl - scl + 1, 0); /* Mark the cluster block 'free' on the bitmap */ + if (res != FR_OK) return res; + } +#endif +#if FF_USE_TRIM + rt[0] = clst2sect(fs, scl); /* Start of data area to be freed */ + rt[1] = clst2sect(fs, ecl) + fs->csize - 1; /* End of data area to be freed */ + disk_ioctl(fs->pdrv, CTRL_TRIM, rt); /* Inform storage device that the data in the block may be erased */ +#endif + scl = ecl = nxt; + } +#endif + clst = nxt; /* Next cluster */ + } while (clst < fs->n_fatent); /* Repeat while not the last link */ + +#if FF_FS_EXFAT + /* Some post processes for chain status */ + if (fs->fs_type == FS_EXFAT) { + if (pclst == 0) { /* Has the entire chain been removed? */ + obj->stat = 0; /* Change the chain status 'initial' */ + } else { + if (obj->stat == 0) { /* Is it a fragmented chain from the beginning of this session? */ + clst = obj->sclust; /* Follow the chain to check if it gets contiguous */ + while (clst != pclst) { + nxt = get_fat(obj, clst); + if (nxt < 2) return FR_INT_ERR; + if (nxt == 0xFFFFFFFF) return FR_DISK_ERR; + if (nxt != clst + 1) break; /* Not contiguous? */ + clst++; + } + if (clst == pclst) { /* Has the chain got contiguous again? */ + obj->stat = 2; /* Change the chain status 'contiguous' */ + } + } else { + if (obj->stat == 3 && pclst >= obj->sclust && pclst <= obj->sclust + obj->n_cont) { /* Was the chain fragmented in this session and got contiguous again? */ + obj->stat = 2; /* Change the chain status 'contiguous' */ + } + } + } + } +#endif + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Stretch a chain or Create a new chain */ +/*-----------------------------------------------------------------------*/ + +static DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */ + FFOBJID* obj, /* Corresponding object */ + DWORD clst /* Cluster# to stretch, 0:Create a new chain */ +) +{ + DWORD cs, ncl, scl; + FRESULT res; + FATFS *fs = obj->fs; + + + if (clst == 0) { /* Create a new chain */ + scl = fs->last_clst; /* Suggested cluster to start to find */ + if (scl == 0 || scl >= fs->n_fatent) scl = 1; + } + else { /* Stretch a chain */ + cs = get_fat(obj, clst); /* Check the cluster status */ + if (cs < 2) return 1; /* Test for insanity */ + if (cs == 0xFFFFFFFF) return cs; /* Test for disk error */ + if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ + scl = clst; /* Cluster to start to find */ + } + if (fs->free_clst == 0) return 0; /* No free cluster */ + +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + ncl = find_bitmap(fs, scl, 1); /* Find a free cluster */ + if (ncl == 0 || ncl == 0xFFFFFFFF) return ncl; /* No free cluster or hard error? */ + res = change_bitmap(fs, ncl, 1, 1); /* Mark the cluster 'in use' */ + if (res == FR_INT_ERR) return 1; + if (res == FR_DISK_ERR) return 0xFFFFFFFF; + if (clst == 0) { /* Is it a new chain? */ + obj->stat = 2; /* Set status 'contiguous' */ + } else { /* It is a stretched chain */ + if (obj->stat == 2 && ncl != scl + 1) { /* Is the chain got fragmented? */ + obj->n_cont = scl - obj->sclust; /* Set size of the contiguous part */ + obj->stat = 3; /* Change status 'just fragmented' */ + } + } + if (obj->stat != 2) { /* Is the file non-contiguous? */ + if (ncl == clst + 1) { /* Is the cluster next to previous one? */ + obj->n_frag = obj->n_frag ? obj->n_frag + 1 : 2; /* Increment size of last framgent */ + } else { /* New fragment */ + if (obj->n_frag == 0) obj->n_frag = 1; + res = fill_last_frag(obj, clst, ncl); /* Fill last fragment on the FAT and link it to new one */ + if (res == FR_OK) obj->n_frag = 1; + } + } + } else +#endif + { /* On the FAT/FAT32 volume */ + ncl = 0; + if (scl == clst) { /* Stretching an existing chain? */ + ncl = scl + 1; /* Test if next cluster is free */ + if (ncl >= fs->n_fatent) ncl = 2; + cs = get_fat(obj, ncl); /* Get next cluster status */ + if (cs == 1 || cs == 0xFFFFFFFF) return cs; /* Test for error */ + if (cs != 0) { /* Not free? */ + cs = fs->last_clst; /* Start at suggested cluster if it is valid */ + if (cs >= 2 && cs < fs->n_fatent) scl = cs; + ncl = 0; + } + } + if (ncl == 0) { /* The new cluster cannot be contiguous and find another fragment */ + ncl = scl; /* Start cluster */ + for (;;) { + ncl++; /* Next cluster */ + if (ncl >= fs->n_fatent) { /* Check wrap-around */ + ncl = 2; + if (ncl > scl) return 0; /* No free cluster found? */ + } + cs = get_fat(obj, ncl); /* Get the cluster status */ + if (cs == 0) break; /* Found a free cluster? */ + if (cs == 1 || cs == 0xFFFFFFFF) return cs; /* Test for error */ + if (ncl == scl) return 0; /* No free cluster found? */ + } + } + res = put_fat(fs, ncl, 0xFFFFFFFF); /* Mark the new cluster 'EOC' */ + if (res == FR_OK && clst != 0) { + res = put_fat(fs, clst, ncl); /* Link it from the previous one if needed */ + } + } + + if (res == FR_OK) { /* Update FSINFO if function succeeded. */ + fs->last_clst = ncl; + if (fs->free_clst <= fs->n_fatent - 2) fs->free_clst--; + fs->fsi_flag |= 1; + } else { + ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; /* Failed. Generate error status */ + } + + return ncl; /* Return new cluster number or error status */ +} + +#endif /* !FF_FS_READONLY */ + + + + +#if FF_USE_FASTSEEK +/*-----------------------------------------------------------------------*/ +/* FAT handling - Convert offset into cluster with link map table */ +/*-----------------------------------------------------------------------*/ + +static DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */ + FIL* fp, /* Pointer to the file object */ + FSIZE_t ofs /* File offset to be converted to cluster# */ +) +{ + DWORD cl, ncl, *tbl; + FATFS *fs = fp->obj.fs; + + + tbl = fp->cltbl + 1; /* Top of CLMT */ + cl = (DWORD)(ofs / SS(fs) / fs->csize); /* Cluster order from top of the file */ + for (;;) { + ncl = *tbl++; /* Number of cluters in the fragment */ + if (ncl == 0) return 0; /* End of table? (error) */ + if (cl < ncl) break; /* In this fragment? */ + cl -= ncl; tbl++; /* Next fragment */ + } + return cl + *tbl; /* Return the cluster number */ +} + +#endif /* FF_USE_FASTSEEK */ + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Fill a cluster with zeros */ +/*-----------------------------------------------------------------------*/ + +#if !FF_FS_READONLY +static FRESULT dir_clear ( /* Returns FR_OK or FR_DISK_ERR */ + FATFS *fs, /* Filesystem object */ + DWORD clst /* Directory table to clear */ +) +{ + LBA_t sect; + UINT n, szb; + BYTE *ibuf; + + + if (sync_window(fs) != FR_OK) return FR_DISK_ERR; /* Flush disk access window */ + sect = clst2sect(fs, clst); /* Top of the cluster */ + fs->winsect = sect; /* Set window to top of the cluster */ + memset(fs->win, 0, sizeof fs->win); /* Clear window buffer */ +#if FF_USE_LFN == 3 /* Quick table clear by using multi-secter write */ + /* Allocate a temporary buffer */ + for (szb = ((DWORD)fs->csize * SS(fs) >= MAX_MALLOC) ? MAX_MALLOC : fs->csize * SS(fs), ibuf = 0; szb > SS(fs) && (ibuf = ff_memalloc(szb)) == 0; szb /= 2) ; + if (szb > SS(fs)) { /* Buffer allocated? */ + memset(ibuf, 0, szb); + szb /= SS(fs); /* Bytes -> Sectors */ + for (n = 0; n < fs->csize && disk_write(fs->pdrv, ibuf, sect + n, szb) == RES_OK; n += szb) ; /* Fill the cluster with 0 */ + ff_memfree(ibuf); + } else +#endif + { + ibuf = fs->win; szb = 1; /* Use window buffer (many single-sector writes may take a time) */ + for (n = 0; n < fs->csize && disk_write(fs->pdrv, ibuf, sect + n, szb) == RES_OK; n += szb) ; /* Fill the cluster with 0 */ + } + return (n == fs->csize) ? FR_OK : FR_DISK_ERR; +} +#endif /* !FF_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Set directory index */ +/*-----------------------------------------------------------------------*/ + +static FRESULT dir_sdi ( /* FR_OK(0):succeeded, !=0:error */ + DIR* dp, /* Pointer to directory object */ + DWORD ofs /* Offset of directory table */ +) +{ + DWORD csz, clst; + FATFS *fs = dp->obj.fs; + + + if (ofs >= (DWORD)((FF_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR) || ofs % SZDIRE) { /* Check range of offset and alignment */ + return FR_INT_ERR; + } + dp->dptr = ofs; /* Set current offset */ + clst = dp->obj.sclust; /* Table start cluster (0:root) */ + if (clst == 0 && fs->fs_type >= FS_FAT32) { /* Replace cluster# 0 with root cluster# */ + clst = (DWORD)fs->dirbase; + if (FF_FS_EXFAT) dp->obj.stat = 0; /* exFAT: Root dir has an FAT chain */ + } + + if (clst == 0) { /* Static table (root-directory on the FAT volume) */ + if (ofs / SZDIRE >= fs->n_rootdir) return FR_INT_ERR; /* Is index out of range? */ + dp->sect = fs->dirbase; + + } else { /* Dynamic table (sub-directory or root-directory on the FAT32/exFAT volume) */ + csz = (DWORD)fs->csize * SS(fs); /* Bytes per cluster */ + while (ofs >= csz) { /* Follow cluster chain */ + clst = get_fat(&dp->obj, clst); /* Get next cluster */ + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Reached to end of table or internal error */ + ofs -= csz; + } + dp->sect = clst2sect(fs, clst); + } + dp->clust = clst; /* Current cluster# */ + if (dp->sect == 0) return FR_INT_ERR; + dp->sect += ofs / SS(fs); /* Sector# of the directory entry */ + dp->dir = fs->win + (ofs % SS(fs)); /* Pointer to the entry in the win[] */ + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Move directory table index next */ +/*-----------------------------------------------------------------------*/ + +static FRESULT dir_next ( /* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */ + DIR* dp, /* Pointer to the directory object */ + int stretch /* 0: Do not stretch table, 1: Stretch table if needed */ +) +{ + DWORD ofs, clst; + FATFS *fs = dp->obj.fs; + + + ofs = dp->dptr + SZDIRE; /* Next entry */ + if (ofs >= (DWORD)((FF_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) dp->sect = 0; /* Disable it if the offset reached the max value */ + if (dp->sect == 0) return FR_NO_FILE; /* Report EOT if it has been disabled */ + + if (ofs % SS(fs) == 0) { /* Sector changed? */ + dp->sect++; /* Next sector */ + + if (dp->clust == 0) { /* Static table */ + if (ofs / SZDIRE >= fs->n_rootdir) { /* Report EOT if it reached end of static table */ + dp->sect = 0; return FR_NO_FILE; + } + } + else { /* Dynamic table */ + if ((ofs / SS(fs) & (fs->csize - 1)) == 0) { /* Cluster changed? */ + clst = get_fat(&dp->obj, dp->clust); /* Get next cluster */ + if (clst <= 1) return FR_INT_ERR; /* Internal error */ + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + if (clst >= fs->n_fatent) { /* It reached end of dynamic table */ +#if !FF_FS_READONLY + if (!stretch) { /* If no stretch, report EOT */ + dp->sect = 0; return FR_NO_FILE; + } + clst = create_chain(&dp->obj, dp->clust); /* Allocate a cluster */ + if (clst == 0) return FR_DENIED; /* No free cluster */ + if (clst == 1) return FR_INT_ERR; /* Internal error */ + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + if (dir_clear(fs, clst) != FR_OK) return FR_DISK_ERR; /* Clean up the stretched table */ + if (FF_FS_EXFAT) dp->obj.stat |= 4; /* exFAT: The directory has been stretched */ +#else + if (!stretch) dp->sect = 0; /* (this line is to suppress compiler warning) */ + dp->sect = 0; return FR_NO_FILE; /* Report EOT */ +#endif + } + dp->clust = clst; /* Initialize data for new cluster */ + dp->sect = clst2sect(fs, clst); + } + } + } + dp->dptr = ofs; /* Current entry */ + dp->dir = fs->win + ofs % SS(fs); /* Pointer to the entry in the win[] */ + + return FR_OK; +} + + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Directory handling - Reserve a block of directory entries */ +/*-----------------------------------------------------------------------*/ + +static FRESULT dir_alloc ( /* FR_OK(0):succeeded, !=0:error */ + DIR* dp, /* Pointer to the directory object */ + UINT n_ent /* Number of contiguous entries to allocate */ +) +{ + FRESULT res; + UINT n; + FATFS *fs = dp->obj.fs; + + + res = dir_sdi(dp, 0); + if (res == FR_OK) { + n = 0; + do { + res = move_window(fs, dp->sect); + if (res != FR_OK) break; +#if FF_FS_EXFAT + if ((fs->fs_type == FS_EXFAT) ? (int)((dp->dir[XDIR_Type] & 0x80) == 0) : (int)(dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0)) { /* Is the entry free? */ +#else + if (dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0) { /* Is the entry free? */ +#endif + if (++n == n_ent) break; /* Is a block of contiguous free entries found? */ + } else { + n = 0; /* Not a free entry, restart to search */ + } + res = dir_next(dp, 1); /* Next entry with table stretch enabled */ + } while (res == FR_OK); + } + + if (res == FR_NO_FILE) res = FR_DENIED; /* No directory entry to allocate */ + return res; +} + +#endif /* !FF_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* FAT: Directory handling - Load/Store start cluster number */ +/*-----------------------------------------------------------------------*/ + +static DWORD ld_clust ( /* Returns the top cluster value of the SFN entry */ + FATFS* fs, /* Pointer to the fs object */ + const BYTE* dir /* Pointer to the key entry */ +) +{ + DWORD cl; + + cl = ld_word(dir + DIR_FstClusLO); + if (fs->fs_type == FS_FAT32) { + cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16; + } + + return cl; +} + + +#if !FF_FS_READONLY +static void st_clust ( + FATFS* fs, /* Pointer to the fs object */ + BYTE* dir, /* Pointer to the key entry */ + DWORD cl /* Value to be set */ +) +{ + st_word(dir + DIR_FstClusLO, (WORD)cl); + if (fs->fs_type == FS_FAT32) { + st_word(dir + DIR_FstClusHI, (WORD)(cl >> 16)); + } +} +#endif + + + +#if FF_USE_LFN +/*--------------------------------------------------------*/ +/* FAT-LFN: Compare a part of file name with an LFN entry */ +/*--------------------------------------------------------*/ + +static int cmp_lfn ( /* 1:matched, 0:not matched */ + const WCHAR* lfnbuf, /* Pointer to the LFN working buffer to be compared */ + BYTE* dir /* Pointer to the directory entry containing the part of LFN */ +) +{ + UINT i, s; + WCHAR wc, uc; + + + if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO */ + + i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ + + for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */ + uc = ld_word(dir + LfnOfs[s]); /* Pick an LFN character */ + if (wc != 0) { + if (i >= FF_MAX_LFN + 1 || ff_wtoupper(uc) != ff_wtoupper(lfnbuf[i++])) { /* Compare it */ + return 0; /* Not matched */ + } + wc = uc; + } else { + if (uc != 0xFFFF) return 0; /* Check filler */ + } + } + + if ((dir[LDIR_Ord] & LLEF) && wc && lfnbuf[i]) return 0; /* Last segment matched but different length */ + + return 1; /* The part of LFN matched */ +} + + +#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 || FF_USE_LABEL || FF_FS_EXFAT +/*-----------------------------------------------------*/ +/* FAT-LFN: Pick a part of file name from an LFN entry */ +/*-----------------------------------------------------*/ + +static int pick_lfn ( /* 1:succeeded, 0:buffer overflow or invalid LFN entry */ + WCHAR* lfnbuf, /* Pointer to the LFN working buffer */ + BYTE* dir /* Pointer to the LFN entry */ +) +{ + UINT i, s; + WCHAR wc, uc; + + + if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO is 0 */ + + i = ((dir[LDIR_Ord] & ~LLEF) - 1) * 13; /* Offset in the LFN buffer */ + + for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */ + uc = ld_word(dir + LfnOfs[s]); /* Pick an LFN character */ + if (wc != 0) { + if (i >= FF_MAX_LFN + 1) return 0; /* Buffer overflow? */ + lfnbuf[i++] = wc = uc; /* Store it */ + } else { + if (uc != 0xFFFF) return 0; /* Check filler */ + } + } + + if (dir[LDIR_Ord] & LLEF && wc != 0) { /* Put terminator if it is the last LFN part and not terminated */ + if (i >= FF_MAX_LFN + 1) return 0; /* Buffer overflow? */ + lfnbuf[i] = 0; + } + + return 1; /* The part of LFN is valid */ +} +#endif + + +#if !FF_FS_READONLY +/*-----------------------------------------*/ +/* FAT-LFN: Create an entry of LFN entries */ +/*-----------------------------------------*/ + +static void put_lfn ( + const WCHAR* lfn, /* Pointer to the LFN */ + BYTE* dir, /* Pointer to the LFN entry to be created */ + BYTE ord, /* LFN order (1-20) */ + BYTE sum /* Checksum of the corresponding SFN */ +) +{ + UINT i, s; + WCHAR wc; + + + dir[LDIR_Chksum] = sum; /* Set checksum */ + dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ + dir[LDIR_Type] = 0; + st_word(dir + LDIR_FstClusLO, 0); + + i = (ord - 1) * 13; /* Get offset in the LFN working buffer */ + s = wc = 0; + do { + if (wc != 0xFFFF) wc = lfn[i++]; /* Get an effective character */ + st_word(dir + LfnOfs[s], wc); /* Put it */ + if (wc == 0) wc = 0xFFFF; /* Padding characters for following items */ + } while (++s < 13); + if (wc == 0xFFFF || !lfn[i]) ord |= LLEF; /* Last LFN part is the start of LFN sequence */ + dir[LDIR_Ord] = ord; /* Set the LFN order */ +} + +#endif /* !FF_FS_READONLY */ +#endif /* FF_USE_LFN */ + + + +#if FF_USE_LFN && !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* FAT-LFN: Create a Numbered SFN */ +/*-----------------------------------------------------------------------*/ + +static void gen_numname ( + BYTE* dst, /* Pointer to the buffer to store numbered SFN */ + const BYTE* src, /* Pointer to SFN in directory form */ + const WCHAR* lfn, /* Pointer to LFN */ + UINT seq /* Sequence number */ +) +{ + BYTE ns[8], c; + UINT i, j; + WCHAR wc; + DWORD sreg; + + + memcpy(dst, src, 11); /* Prepare the SFN to be modified */ + + if (seq > 5) { /* In case of many collisions, generate a hash number instead of sequential number */ + sreg = seq; + while (*lfn) { /* Create a CRC as hash value */ + wc = *lfn++; + for (i = 0; i < 16; i++) { + sreg = (sreg << 1) + (wc & 1); + wc >>= 1; + if (sreg & 0x10000) sreg ^= 0x11021; + } + } + seq = (UINT)sreg; + } + + /* Make suffix (~ + hexdecimal) */ + i = 7; + do { + c = (BYTE)((seq % 16) + '0'); seq /= 16; + if (c > '9') c += 7; + ns[i--] = c; + } while (i && seq); + ns[i] = '~'; + + /* Append the suffix to the SFN body */ + for (j = 0; j < i && dst[j] != ' '; j++) { /* Find the offset to append */ + if (dbc_1st(dst[j])) { /* To avoid DBC break up */ + if (j == i - 1) break; + j++; + } + } + do { /* Append the suffix */ + dst[j++] = (i < 8) ? ns[i++] : ' '; + } while (j < 8); +} +#endif /* FF_USE_LFN && !FF_FS_READONLY */ + + + +#if FF_USE_LFN +/*-----------------------------------------------------------------------*/ +/* FAT-LFN: Calculate checksum of an SFN entry */ +/*-----------------------------------------------------------------------*/ + +static BYTE sum_sfn ( + const BYTE* dir /* Pointer to the SFN entry */ +) +{ + BYTE sum = 0; + UINT n = 11; + + do { + sum = (sum >> 1) + (sum << 7) + *dir++; + } while (--n); + return sum; +} + +#endif /* FF_USE_LFN */ + + + +#if FF_FS_EXFAT +/*-----------------------------------------------------------------------*/ +/* exFAT: Checksum */ +/*-----------------------------------------------------------------------*/ + +static WORD xdir_sum ( /* Get checksum of the directoly entry block */ + const BYTE* dir /* Directory entry block to be calculated */ +) +{ + UINT i, szblk; + WORD sum; + + + szblk = (dir[XDIR_NumSec] + 1) * SZDIRE; /* Number of bytes of the entry block */ + for (i = sum = 0; i < szblk; i++) { + if (i == XDIR_SetSum) { /* Skip 2-byte sum field */ + i++; + } else { + sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + dir[i]; + } + } + return sum; +} + + + +static WORD xname_sum ( /* Get check sum (to be used as hash) of the file name */ + const WCHAR* name /* File name to be calculated */ +) +{ + WCHAR chr; + WORD sum = 0; + + + while ((chr = *name++) != 0) { + chr = (WCHAR)ff_wtoupper(chr); /* File name needs to be up-case converted */ + sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr & 0xFF); + sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr >> 8); + } + return sum; +} + + +#if !FF_FS_READONLY && FF_USE_MKFS +static DWORD xsum32 ( /* Returns 32-bit checksum */ + BYTE dat, /* Byte to be calculated (byte-by-byte processing) */ + DWORD sum /* Previous sum value */ +) +{ + sum = ((sum & 1) ? 0x80000000 : 0) + (sum >> 1) + dat; + return sum; +} +#endif + + + +/*-----------------------------------*/ +/* exFAT: Get a directry entry block */ +/*-----------------------------------*/ + +static FRESULT load_xdir ( /* FR_INT_ERR: invalid entry block */ + DIR* dp /* Reading direcotry object pointing top of the entry block to load */ +) +{ + FRESULT res; + UINT i, sz_ent; + BYTE *dirb = dp->obj.fs->dirbuf; /* Pointer to the on-memory direcotry entry block 85+C0+C1s */ + + + /* Load file directory entry */ + res = move_window(dp->obj.fs, dp->sect); + if (res != FR_OK) return res; + if (dp->dir[XDIR_Type] != ET_FILEDIR) return FR_INT_ERR; /* Invalid order */ + memcpy(dirb + 0 * SZDIRE, dp->dir, SZDIRE); + sz_ent = (dirb[XDIR_NumSec] + 1) * SZDIRE; + if (sz_ent < 3 * SZDIRE || sz_ent > 19 * SZDIRE) return FR_INT_ERR; + + /* Load stream extension entry */ + res = dir_next(dp, 0); + if (res == FR_NO_FILE) res = FR_INT_ERR; /* It cannot be */ + if (res != FR_OK) return res; + res = move_window(dp->obj.fs, dp->sect); + if (res != FR_OK) return res; + if (dp->dir[XDIR_Type] != ET_STREAM) return FR_INT_ERR; /* Invalid order */ + memcpy(dirb + 1 * SZDIRE, dp->dir, SZDIRE); + if (MAXDIRB(dirb[XDIR_NumName]) > sz_ent) return FR_INT_ERR; + + /* Load file name entries */ + i = 2 * SZDIRE; /* Name offset to load */ + do { + res = dir_next(dp, 0); + if (res == FR_NO_FILE) res = FR_INT_ERR; /* It cannot be */ + if (res != FR_OK) return res; + res = move_window(dp->obj.fs, dp->sect); + if (res != FR_OK) return res; + if (dp->dir[XDIR_Type] != ET_FILENAME) return FR_INT_ERR; /* Invalid order */ + if (i < MAXDIRB(FF_MAX_LFN)) memcpy(dirb + i, dp->dir, SZDIRE); + } while ((i += SZDIRE) < sz_ent); + + /* Sanity check (do it for only accessible object) */ + if (i <= MAXDIRB(FF_MAX_LFN)) { + if (xdir_sum(dirb) != ld_word(dirb + XDIR_SetSum)) return FR_INT_ERR; + } + return FR_OK; +} + + +/*------------------------------------------------------------------*/ +/* exFAT: Initialize object allocation info with loaded entry block */ +/*------------------------------------------------------------------*/ + +static void init_alloc_info ( + FATFS* fs, /* Filesystem object */ + FFOBJID* obj /* Object allocation information to be initialized */ +) +{ + obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus); /* Start cluster */ + obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize); /* Size */ + obj->stat = fs->dirbuf[XDIR_GenFlags] & 2; /* Allocation status */ + obj->n_frag = 0; /* No last fragment info */ +} + + + +#if !FF_FS_READONLY || FF_FS_RPATH != 0 +/*------------------------------------------------*/ +/* exFAT: Load the object's directory entry block */ +/*------------------------------------------------*/ + +static FRESULT load_obj_xdir ( + DIR* dp, /* Blank directory object to be used to access containing direcotry */ + const FFOBJID* obj /* Object with its containing directory information */ +) +{ + FRESULT res; + + /* Open object containing directory */ + dp->obj.fs = obj->fs; + dp->obj.sclust = obj->c_scl; + dp->obj.stat = (BYTE)obj->c_size; + dp->obj.objsize = obj->c_size & 0xFFFFFF00; + dp->obj.n_frag = 0; + dp->blk_ofs = obj->c_ofs; + + res = dir_sdi(dp, dp->blk_ofs); /* Goto object's entry block */ + if (res == FR_OK) { + res = load_xdir(dp); /* Load the object's entry block */ + } + return res; +} +#endif + + +#if !FF_FS_READONLY +/*----------------------------------------*/ +/* exFAT: Store the directory entry block */ +/*----------------------------------------*/ + +static FRESULT store_xdir ( + DIR* dp /* Pointer to the direcotry object */ +) +{ + FRESULT res; + UINT nent; + BYTE *dirb = dp->obj.fs->dirbuf; /* Pointer to the direcotry entry block 85+C0+C1s */ + + /* Create set sum */ + st_word(dirb + XDIR_SetSum, xdir_sum(dirb)); + nent = dirb[XDIR_NumSec] + 1; + + /* Store the direcotry entry block to the directory */ + res = dir_sdi(dp, dp->blk_ofs); + while (res == FR_OK) { + res = move_window(dp->obj.fs, dp->sect); + if (res != FR_OK) break; + memcpy(dp->dir, dirb, SZDIRE); + dp->obj.fs->wflag = 1; + if (--nent == 0) break; + dirb += SZDIRE; + res = dir_next(dp, 0); + } + return (res == FR_OK || res == FR_DISK_ERR) ? res : FR_INT_ERR; +} + + + +/*-------------------------------------------*/ +/* exFAT: Create a new directory enrty block */ +/*-------------------------------------------*/ + +static void create_xdir ( + BYTE* dirb, /* Pointer to the direcotry entry block buffer */ + const WCHAR* lfn /* Pointer to the object name */ +) +{ + UINT i; + BYTE nc1, nlen; + WCHAR wc; + + + /* Create file-directory and stream-extension entry */ + memset(dirb, 0, 2 * SZDIRE); + dirb[0 * SZDIRE + XDIR_Type] = ET_FILEDIR; + dirb[1 * SZDIRE + XDIR_Type] = ET_STREAM; + + /* Create file-name entries */ + i = SZDIRE * 2; /* Top of file_name entries */ + nlen = nc1 = 0; wc = 1; + do { + dirb[i++] = ET_FILENAME; dirb[i++] = 0; + do { /* Fill name field */ + if (wc != 0 && (wc = lfn[nlen]) != 0) nlen++; /* Get a character if exist */ + st_word(dirb + i, wc); /* Store it */ + i += 2; + } while (i % SZDIRE != 0); + nc1++; + } while (lfn[nlen]); /* Fill next entry if any char follows */ + + dirb[XDIR_NumName] = nlen; /* Set name length */ + dirb[XDIR_NumSec] = 1 + nc1; /* Set secondary count (C0 + C1s) */ + st_word(dirb + XDIR_NameHash, xname_sum(lfn)); /* Set name hash */ +} + +#endif /* !FF_FS_READONLY */ +#endif /* FF_FS_EXFAT */ + + + +#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 || FF_USE_LABEL || FF_FS_EXFAT +/*-----------------------------------------------------------------------*/ +/* Read an object from the directory */ +/*-----------------------------------------------------------------------*/ + +#define DIR_READ_FILE(dp) dir_read(dp, 0) +#define DIR_READ_LABEL(dp) dir_read(dp, 1) + +static FRESULT dir_read ( + DIR* dp, /* Pointer to the directory object */ + int vol /* Filtered by 0:file/directory or 1:volume label */ +) +{ + FRESULT res = FR_NO_FILE; + FATFS *fs = dp->obj.fs; + BYTE attr, b; +#if FF_USE_LFN + BYTE ord = 0xFF, sum = 0xFF; +#endif + + while (dp->sect) { + res = move_window(fs, dp->sect); + if (res != FR_OK) break; + b = dp->dir[DIR_Name]; /* Test for the entry type */ + if (b == 0) { + res = FR_NO_FILE; break; /* Reached to end of the directory */ + } +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + if (FF_USE_LABEL && vol) { + if (b == ET_VLABEL) break; /* Volume label entry? */ + } else { + if (b == ET_FILEDIR) { /* Start of the file entry block? */ + dp->blk_ofs = dp->dptr; /* Get location of the block */ + res = load_xdir(dp); /* Load the entry block */ + if (res == FR_OK) { + dp->obj.attr = fs->dirbuf[XDIR_Attr] & AM_MASK; /* Get attribute */ + } + break; + } + } + } else +#endif + { /* On the FAT/FAT32 volume */ + dp->obj.attr = attr = dp->dir[DIR_Attr] & AM_MASK; /* Get attribute */ +#if FF_USE_LFN /* LFN configuration */ + if (b == DDEM || b == '.' || (int)((attr & ~AM_ARC) == AM_VOL) != vol) { /* An entry without valid data */ + ord = 0xFF; + } else { + if (attr == AM_LFN) { /* An LFN entry is found */ + if (b & LLEF) { /* Is it start of an LFN sequence? */ + sum = dp->dir[LDIR_Chksum]; + b &= (BYTE)~LLEF; ord = b; + dp->blk_ofs = dp->dptr; + } + /* Check LFN validity and capture it */ + ord = (b == ord && sum == dp->dir[LDIR_Chksum] && pick_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF; + } else { /* An SFN entry is found */ + if (ord != 0 || sum != sum_sfn(dp->dir)) { /* Is there a valid LFN? */ + dp->blk_ofs = 0xFFFFFFFF; /* It has no LFN. */ + } + break; + } + } +#else /* Non LFN configuration */ + if (b != DDEM && b != '.' && attr != AM_LFN && (int)((attr & ~AM_ARC) == AM_VOL) == vol) { /* Is it a valid entry? */ + break; + } +#endif + } + res = dir_next(dp, 0); /* Next entry */ + if (res != FR_OK) break; + } + + if (res != FR_OK) dp->sect = 0; /* Terminate the read operation on error or EOT */ + return res; +} + +#endif /* FF_FS_MINIMIZE <= 1 || FF_USE_LABEL || FF_FS_RPATH >= 2 */ + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Find an object in the directory */ +/*-----------------------------------------------------------------------*/ + +static FRESULT dir_find ( /* FR_OK(0):succeeded, !=0:error */ + DIR* dp /* Pointer to the directory object with the file name */ +) +{ + FRESULT res; + FATFS *fs = dp->obj.fs; + BYTE c; +#if FF_USE_LFN + BYTE a, ord, sum; +#endif + + res = dir_sdi(dp, 0); /* Rewind directory object */ + if (res != FR_OK) return res; +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + BYTE nc; + UINT di, ni; + WORD hash = xname_sum(fs->lfnbuf); /* Hash value of the name to find */ + + while ((res = DIR_READ_FILE(dp)) == FR_OK) { /* Read an item */ +#if FF_MAX_LFN < 255 + if (fs->dirbuf[XDIR_NumName] > FF_MAX_LFN) continue; /* Skip comparison if inaccessible object name */ +#endif + if (ld_word(fs->dirbuf + XDIR_NameHash) != hash) continue; /* Skip comparison if hash mismatched */ + for (nc = fs->dirbuf[XDIR_NumName], di = SZDIRE * 2, ni = 0; nc; nc--, di += 2, ni++) { /* Compare the name */ + if ((di % SZDIRE) == 0) di += 2; + if (ff_wtoupper(ld_word(fs->dirbuf + di)) != ff_wtoupper(fs->lfnbuf[ni])) break; + } + if (nc == 0 && !fs->lfnbuf[ni]) break; /* Name matched? */ + } + return res; + } +#endif + /* On the FAT/FAT32 volume */ +#if FF_USE_LFN + ord = sum = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ +#endif + do { + res = move_window(fs, dp->sect); + if (res != FR_OK) break; + c = dp->dir[DIR_Name]; + if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ +#if FF_USE_LFN /* LFN configuration */ + dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK; + if (c == DDEM || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ + ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ + } else { + if (a == AM_LFN) { /* An LFN entry is found */ + if (!(dp->fn[NSFLAG] & NS_NOLFN)) { + if (c & LLEF) { /* Is it start of LFN sequence? */ + sum = dp->dir[LDIR_Chksum]; + c &= (BYTE)~LLEF; ord = c; /* LFN start order */ + dp->blk_ofs = dp->dptr; /* Start offset of LFN */ + } + /* Check validity of the LFN entry and compare it with given name */ + ord = (c == ord && sum == dp->dir[LDIR_Chksum] && cmp_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF; + } + } else { /* An SFN entry is found */ + if (ord == 0 && sum == sum_sfn(dp->dir)) break; /* LFN matched? */ + if (!(dp->fn[NSFLAG] & NS_LOSS) && !memcmp(dp->dir, dp->fn, 11)) break; /* SFN matched? */ + ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ + } + } +#else /* Non LFN configuration */ + dp->obj.attr = dp->dir[DIR_Attr] & AM_MASK; + if (!(dp->dir[DIR_Attr] & AM_VOL) && !memcmp(dp->dir, dp->fn, 11)) break; /* Is it a valid entry? */ +#endif + res = dir_next(dp, 0); /* Next entry */ + } while (res == FR_OK); + + return res; +} + + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Register an object to the directory */ +/*-----------------------------------------------------------------------*/ + +static FRESULT dir_register ( /* FR_OK:succeeded, FR_DENIED:no free entry or too many SFN collision, FR_DISK_ERR:disk error */ + DIR* dp /* Target directory with object name to be created */ +) +{ + FRESULT res; + FATFS *fs = dp->obj.fs; +#if FF_USE_LFN /* LFN configuration */ + UINT n, len, n_ent; + BYTE sn[12], sum; + + + if (dp->fn[NSFLAG] & (NS_DOT | NS_NONAME)) return FR_INVALID_NAME; /* Check name validity */ + for (len = 0; fs->lfnbuf[len]; len++) ; /* Get lfn length */ + +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + n_ent = (len + 14) / 15 + 2; /* Number of entries to allocate (85+C0+C1s) */ + res = dir_alloc(dp, n_ent); /* Allocate directory entries */ + if (res != FR_OK) return res; + dp->blk_ofs = dp->dptr - SZDIRE * (n_ent - 1); /* Set the allocated entry block offset */ + + if (dp->obj.stat & 4) { /* Has the directory been stretched by new allocation? */ + dp->obj.stat &= ~4; + res = fill_first_frag(&dp->obj); /* Fill the first fragment on the FAT if needed */ + if (res != FR_OK) return res; + res = fill_last_frag(&dp->obj, dp->clust, 0xFFFFFFFF); /* Fill the last fragment on the FAT if needed */ + if (res != FR_OK) return res; + if (dp->obj.sclust != 0) { /* Is it a sub-directory? */ + DIR dj; + + res = load_obj_xdir(&dj, &dp->obj); /* Load the object status */ + if (res != FR_OK) return res; + dp->obj.objsize += (DWORD)fs->csize * SS(fs); /* Increase the directory size by cluster size */ + st_qword(fs->dirbuf + XDIR_FileSize, dp->obj.objsize); + st_qword(fs->dirbuf + XDIR_ValidFileSize, dp->obj.objsize); + fs->dirbuf[XDIR_GenFlags] = dp->obj.stat | 1; /* Update the allocation status */ + res = store_xdir(&dj); /* Store the object status */ + if (res != FR_OK) return res; + } + } + + create_xdir(fs->dirbuf, fs->lfnbuf); /* Create on-memory directory block to be written later */ + return FR_OK; + } +#endif + /* On the FAT/FAT32 volume */ + memcpy(sn, dp->fn, 12); + if (sn[NSFLAG] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */ + dp->fn[NSFLAG] = NS_NOLFN; /* Find only SFN */ + for (n = 1; n < 100; n++) { + gen_numname(dp->fn, sn, fs->lfnbuf, n); /* Generate a numbered name */ + res = dir_find(dp); /* Check if the name collides with existing SFN */ + if (res != FR_OK) break; + } + if (n == 100) return FR_DENIED; /* Abort if too many collisions */ + if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ + dp->fn[NSFLAG] = sn[NSFLAG]; + } + + /* Create an SFN with/without LFNs. */ + n_ent = (sn[NSFLAG] & NS_LFN) ? (len + 12) / 13 + 1 : 1; /* Number of entries to allocate */ + res = dir_alloc(dp, n_ent); /* Allocate entries */ + if (res == FR_OK && --n_ent) { /* Set LFN entry if needed */ + res = dir_sdi(dp, dp->dptr - n_ent * SZDIRE); + if (res == FR_OK) { + sum = sum_sfn(dp->fn); /* Checksum value of the SFN tied to the LFN */ + do { /* Store LFN entries in bottom first */ + res = move_window(fs, dp->sect); + if (res != FR_OK) break; + put_lfn(fs->lfnbuf, dp->dir, (BYTE)n_ent, sum); + fs->wflag = 1; + res = dir_next(dp, 0); /* Next entry */ + } while (res == FR_OK && --n_ent); + } + } + +#else /* Non LFN configuration */ + res = dir_alloc(dp, 1); /* Allocate an entry for SFN */ + +#endif + + /* Set SFN entry */ + if (res == FR_OK) { + res = move_window(fs, dp->sect); + if (res == FR_OK) { + memset(dp->dir, 0, SZDIRE); /* Clean the entry */ + memcpy(dp->dir + DIR_Name, dp->fn, 11); /* Put SFN */ +#if FF_USE_LFN + dp->dir[DIR_NTres] = dp->fn[NSFLAG] & (NS_BODY | NS_EXT); /* Put NT flag */ +#endif + fs->wflag = 1; + } + } + + return res; +} + +#endif /* !FF_FS_READONLY */ + + + +#if !FF_FS_READONLY && FF_FS_MINIMIZE == 0 +/*-----------------------------------------------------------------------*/ +/* Remove an object from the directory */ +/*-----------------------------------------------------------------------*/ + +static FRESULT dir_remove ( /* FR_OK:Succeeded, FR_DISK_ERR:A disk error */ + DIR* dp /* Directory object pointing the entry to be removed */ +) +{ + FRESULT res; + FATFS *fs = dp->obj.fs; +#if FF_USE_LFN /* LFN configuration */ + DWORD last = dp->dptr; + + res = (dp->blk_ofs == 0xFFFFFFFF) ? FR_OK : dir_sdi(dp, dp->blk_ofs); /* Goto top of the entry block if LFN is exist */ + if (res == FR_OK) { + do { + res = move_window(fs, dp->sect); + if (res != FR_OK) break; + if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + dp->dir[XDIR_Type] &= 0x7F; /* Clear the entry InUse flag. */ + } else { /* On the FAT/FAT32 volume */ + dp->dir[DIR_Name] = DDEM; /* Mark the entry 'deleted'. */ + } + fs->wflag = 1; + if (dp->dptr >= last) break; /* If reached last entry then all entries of the object has been deleted. */ + res = dir_next(dp, 0); /* Next entry */ + } while (res == FR_OK); + if (res == FR_NO_FILE) res = FR_INT_ERR; + } +#else /* Non LFN configuration */ + + res = move_window(fs, dp->sect); + if (res == FR_OK) { + dp->dir[DIR_Name] = DDEM; /* Mark the entry 'deleted'.*/ + fs->wflag = 1; + } +#endif + + return res; +} + +#endif /* !FF_FS_READONLY && FF_FS_MINIMIZE == 0 */ + + + +#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 +/*-----------------------------------------------------------------------*/ +/* Get file information from directory entry */ +/*-----------------------------------------------------------------------*/ + +static void get_fileinfo ( + DIR* dp, /* Pointer to the directory object */ + FILINFO* fno /* Pointer to the file information to be filled */ +) +{ + UINT si, di; +#if FF_USE_LFN + BYTE lcf; + WCHAR wc, hs; + FATFS *fs = dp->obj.fs; + UINT nw; +#else + TCHAR c; +#endif + + + fno->fname[0] = 0; /* Invaidate file info */ + if (dp->sect == 0) return; /* Exit if read pointer has reached end of directory */ + +#if FF_USE_LFN /* LFN configuration */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* exFAT volume */ + UINT nc = 0; + + si = SZDIRE * 2; di = 0; /* 1st C1 entry in the entry block */ + hs = 0; + while (nc < fs->dirbuf[XDIR_NumName]) { + if (si >= MAXDIRB(FF_MAX_LFN)) { di = 0; break; } /* Truncated directory block? */ + if ((si % SZDIRE) == 0) si += 2; /* Skip entry type field */ + wc = ld_word(fs->dirbuf + si); si += 2; nc++; /* Get a character */ + if (hs == 0 && IsSurrogate(wc)) { /* Is it a surrogate? */ + hs = wc; continue; /* Get low surrogate */ + } + nw = put_utf((DWORD)hs << 16 | wc, &fno->fname[di], FF_LFN_BUF - di); /* Store it in API encoding */ + if (nw == 0) { di = 0; break; } /* Buffer overflow or wrong char? */ + di += nw; + hs = 0; + } + if (hs != 0) di = 0; /* Broken surrogate pair? */ + if (di == 0) fno->fname[di++] = '?'; /* Inaccessible object name? */ + fno->fname[di] = 0; /* Terminate the name */ + fno->altname[0] = 0; /* exFAT does not support SFN */ + + fno->fattrib = fs->dirbuf[XDIR_Attr] & AM_MASKX; /* Attribute */ + fno->fsize = (fno->fattrib & AM_DIR) ? 0 : ld_qword(fs->dirbuf + XDIR_FileSize); /* Size */ + fno->ftime = ld_word(fs->dirbuf + XDIR_ModTime + 0); /* Time */ + fno->fdate = ld_word(fs->dirbuf + XDIR_ModTime + 2); /* Date */ + return; + } else +#endif + { /* FAT/FAT32 volume */ + if (dp->blk_ofs != 0xFFFFFFFF) { /* Get LFN if available */ + si = di = 0; + hs = 0; + while (fs->lfnbuf[si] != 0) { + wc = fs->lfnbuf[si++]; /* Get an LFN character (UTF-16) */ + if (hs == 0 && IsSurrogate(wc)) { /* Is it a surrogate? */ + hs = wc; continue; /* Get low surrogate */ + } + nw = put_utf((DWORD)hs << 16 | wc, &fno->fname[di], FF_LFN_BUF - di); /* Store it in API encoding */ + if (nw == 0) { di = 0; break; } /* Buffer overflow or wrong char? */ + di += nw; + hs = 0; + } + if (hs != 0) di = 0; /* Broken surrogate pair? */ + fno->fname[di] = 0; /* Terminate the LFN (null string means LFN is invalid) */ + } + } + + si = di = 0; + while (si < 11) { /* Get SFN from SFN entry */ + wc = dp->dir[si++]; /* Get a char */ + if (wc == ' ') continue; /* Skip padding spaces */ + if (wc == RDDEM) wc = DDEM; /* Restore replaced DDEM character */ + if (si == 9 && di < FF_SFN_BUF) fno->altname[di++] = '.'; /* Insert a . if extension is exist */ +#if FF_LFN_UNICODE >= 1 /* Unicode output */ + if (dbc_1st((BYTE)wc) && si != 8 && si != 11 && dbc_2nd(dp->dir[si])) { /* Make a DBC if needed */ + wc = wc << 8 | dp->dir[si++]; + } + wc = ff_oem2uni(wc, CODEPAGE); /* ANSI/OEM -> Unicode */ + if (wc == 0) { di = 0; break; } /* Wrong char in the current code page? */ + nw = put_utf(wc, &fno->altname[di], FF_SFN_BUF - di); /* Store it in API encoding */ + if (nw == 0) { di = 0; break; } /* Buffer overflow? */ + di += nw; +#else /* ANSI/OEM output */ + fno->altname[di++] = (TCHAR)wc; /* Store it without any conversion */ +#endif + } + fno->altname[di] = 0; /* Terminate the SFN (null string means SFN is invalid) */ + + if (fno->fname[0] == 0) { /* If LFN is invalid, altname[] needs to be copied to fname[] */ + if (di == 0) { /* If LFN and SFN both are invalid, this object is inaccesible */ + fno->fname[di++] = '?'; + } else { + for (si = di = 0, lcf = NS_BODY; fno->altname[si]; si++, di++) { /* Copy altname[] to fname[] with case information */ + wc = (WCHAR)fno->altname[si]; + if (wc == '.') lcf = NS_EXT; + if (IsUpper(wc) && (dp->dir[DIR_NTres] & lcf)) wc += 0x20; + fno->fname[di] = (TCHAR)wc; + } + } + fno->fname[di] = 0; /* Terminate the LFN */ + if (!dp->dir[DIR_NTres]) fno->altname[0] = 0; /* Altname is not needed if neither LFN nor case info is exist. */ + } + +#else /* Non-LFN configuration */ + si = di = 0; + while (si < 11) { /* Copy name body and extension */ + c = (TCHAR)dp->dir[si++]; + if (c == ' ') continue; /* Skip padding spaces */ + if (c == RDDEM) c = DDEM; /* Restore replaced DDEM character */ + if (si == 9) fno->fname[di++] = '.';/* Insert a . if extension is exist */ + fno->fname[di++] = c; + } + fno->fname[di] = 0; /* Terminate the SFN */ +#endif + + fno->fattrib = dp->dir[DIR_Attr] & AM_MASK; /* Attribute */ + fno->fsize = ld_dword(dp->dir + DIR_FileSize); /* Size */ + fno->ftime = ld_word(dp->dir + DIR_ModTime + 0); /* Time */ + fno->fdate = ld_word(dp->dir + DIR_ModTime + 2); /* Date */ +} + +#endif /* FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 */ + + + +#if FF_USE_FIND && FF_FS_MINIMIZE <= 1 +/*-----------------------------------------------------------------------*/ +/* Pattern matching */ +/*-----------------------------------------------------------------------*/ + +#define FIND_RECURS 4 /* Maximum number of wildcard terms in the pattern to limit recursion */ + + +static DWORD get_achar ( /* Get a character and advance ptr */ + const TCHAR** ptr /* Pointer to pointer to the ANSI/OEM or Unicode string */ +) +{ + DWORD chr; + + +#if FF_USE_LFN && FF_LFN_UNICODE >= 1 /* Unicode input */ + chr = tchar2uni(ptr); + if (chr == 0xFFFFFFFF) chr = 0; /* Wrong UTF encoding is recognized as end of the string */ + chr = ff_wtoupper(chr); + +#else /* ANSI/OEM input */ + chr = (BYTE)*(*ptr)++; /* Get a byte */ + if (IsLower(chr)) chr -= 0x20; /* To upper ASCII char */ +#if FF_CODE_PAGE == 0 + if (ExCvt && chr >= 0x80) chr = ExCvt[chr - 0x80]; /* To upper SBCS extended char */ +#elif FF_CODE_PAGE < 900 + if (chr >= 0x80) chr = ExCvt[chr - 0x80]; /* To upper SBCS extended char */ +#endif +#if FF_CODE_PAGE == 0 || FF_CODE_PAGE >= 900 + if (dbc_1st((BYTE)chr)) { /* Get DBC 2nd byte if needed */ + chr = dbc_2nd((BYTE)**ptr) ? chr << 8 | (BYTE)*(*ptr)++ : 0; + } +#endif + +#endif + return chr; +} + + +static int pattern_match ( /* 0:mismatched, 1:matched */ + const TCHAR* pat, /* Matching pattern */ + const TCHAR* nam, /* String to be tested */ + UINT skip, /* Number of pre-skip chars (number of ?s, b8:infinite (* specified)) */ + UINT recur /* Recursion count */ +) +{ + const TCHAR *pptr, *nptr; + DWORD pchr, nchr; + UINT sk; + + + while ((skip & 0xFF) != 0) { /* Pre-skip name chars */ + if (!get_achar(&nam)) return 0; /* Branch mismatched if less name chars */ + skip--; + } + if (*pat == 0 && skip) return 1; /* Matched? (short circuit) */ + + do { + pptr = pat; nptr = nam; /* Top of pattern and name to match */ + for (;;) { + if (*pptr == '?' || *pptr == '*') { /* Wildcard term? */ + if (recur == 0) return 0; /* Too many wildcard terms? */ + sk = 0; + do { /* Analyze the wildcard term */ + if (*pptr++ == '?') sk++; else sk |= 0x100; + } while (*pptr == '?' || *pptr == '*'); + if (pattern_match(pptr, nptr, sk, recur - 1)) return 1; /* Test new branch (recursive call) */ + nchr = *nptr; break; /* Branch mismatched */ + } + pchr = get_achar(&pptr); /* Get a pattern char */ + nchr = get_achar(&nptr); /* Get a name char */ + if (pchr != nchr) break; /* Branch mismatched? */ + if (pchr == 0) return 1; /* Branch matched? (matched at end of both strings) */ + } + get_achar(&nam); /* nam++ */ + } while (skip && nchr); /* Retry until end of name if infinite search is specified */ + + return 0; +} + +#endif /* FF_USE_FIND && FF_FS_MINIMIZE <= 1 */ + + + +/*-----------------------------------------------------------------------*/ +/* Pick a top segment and create the object name in directory form */ +/*-----------------------------------------------------------------------*/ + +static FRESULT create_name ( /* FR_OK: successful, FR_INVALID_NAME: could not create */ + DIR* dp, /* Pointer to the directory object */ + const TCHAR** path /* Pointer to pointer to the segment in the path string */ +) +{ +#if FF_USE_LFN /* LFN configuration */ + BYTE b, cf; + WCHAR wc, *lfn; + DWORD uc; + UINT i, ni, si, di; + const TCHAR *p; + + + /* Create LFN into LFN working buffer */ + p = *path; lfn = dp->obj.fs->lfnbuf; di = 0; + for (;;) { + uc = tchar2uni(&p); /* Get a character */ + if (uc == 0xFFFFFFFF) return FR_INVALID_NAME; /* Invalid code or UTF decode error */ + if (uc >= 0x10000) lfn[di++] = (WCHAR)(uc >> 16); /* Store high surrogate if needed */ + wc = (WCHAR)uc; + if (wc < ' ' || IsSeparator(wc)) break; /* Break if end of the path or a separator is found */ + if (wc < 0x80 && strchr("*:<>|\"\?\x7F", (int)wc)) return FR_INVALID_NAME; /* Reject illegal characters for LFN */ + if (di >= FF_MAX_LFN) return FR_INVALID_NAME; /* Reject too long name */ + lfn[di++] = wc; /* Store the Unicode character */ + } + if (wc < ' ') { /* Stopped at end of the path? */ + cf = NS_LAST; /* Last segment */ + } else { /* Stopped at a separator */ + while (IsSeparator(*p)) p++; /* Skip duplicated separators if exist */ + cf = 0; /* Next segment may follow */ + if (IsTerminator(*p)) cf = NS_LAST; /* Ignore terminating separator */ + } + *path = p; /* Return pointer to the next segment */ + +#if FF_FS_RPATH != 0 + if ((di == 1 && lfn[di - 1] == '.') || + (di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) { /* Is this segment a dot name? */ + lfn[di] = 0; + for (i = 0; i < 11; i++) { /* Create dot name for SFN entry */ + dp->fn[i] = (i < di) ? '.' : ' '; + } + dp->fn[i] = cf | NS_DOT; /* This is a dot entry */ + return FR_OK; + } +#endif + while (di) { /* Snip off trailing spaces and dots if exist */ + wc = lfn[di - 1]; + if (wc != ' ' && wc != '.') break; + di--; + } + lfn[di] = 0; /* LFN is created into the working buffer */ + if (di == 0) return FR_INVALID_NAME; /* Reject null name */ + + /* Create SFN in directory form */ + for (si = 0; lfn[si] == ' '; si++) ; /* Remove leading spaces */ + if (si > 0 || lfn[si] == '.') cf |= NS_LOSS | NS_LFN; /* Is there any leading space or dot? */ + while (di > 0 && lfn[di - 1] != '.') di--; /* Find last dot (di<=si: no extension) */ + + memset(dp->fn, ' ', 11); + i = b = 0; ni = 8; + for (;;) { + wc = lfn[si++]; /* Get an LFN character */ + if (wc == 0) break; /* Break on end of the LFN */ + if (wc == ' ' || (wc == '.' && si != di)) { /* Remove embedded spaces and dots */ + cf |= NS_LOSS | NS_LFN; + continue; + } + + if (i >= ni || si == di) { /* End of field? */ + if (ni == 11) { /* Name extension overflow? */ + cf |= NS_LOSS | NS_LFN; + break; + } + if (si != di) cf |= NS_LOSS | NS_LFN; /* Name body overflow? */ + if (si > di) break; /* No name extension? */ + si = di; i = 8; ni = 11; b <<= 2; /* Enter name extension */ + continue; + } + + if (wc >= 0x80) { /* Is this an extended character? */ + cf |= NS_LFN; /* LFN entry needs to be created */ +#if FF_CODE_PAGE == 0 + if (ExCvt) { /* In SBCS cfg */ + wc = ff_uni2oem(wc, CODEPAGE); /* Unicode ==> ANSI/OEM code */ + if (wc & 0x80) wc = ExCvt[wc & 0x7F]; /* Convert extended character to upper (SBCS) */ + } else { /* In DBCS cfg */ + wc = ff_uni2oem(ff_wtoupper(wc), CODEPAGE); /* Unicode ==> Up-convert ==> ANSI/OEM code */ + } +#elif FF_CODE_PAGE < 900 /* In SBCS cfg */ + wc = ff_uni2oem(wc, CODEPAGE); /* Unicode ==> ANSI/OEM code */ + if (wc & 0x80) wc = ExCvt[wc & 0x7F]; /* Convert extended character to upper (SBCS) */ +#else /* In DBCS cfg */ + wc = ff_uni2oem(ff_wtoupper(wc), CODEPAGE); /* Unicode ==> Up-convert ==> ANSI/OEM code */ +#endif + } + + if (wc >= 0x100) { /* Is this a DBC? */ + if (i >= ni - 1) { /* Field overflow? */ + cf |= NS_LOSS | NS_LFN; + i = ni; continue; /* Next field */ + } + dp->fn[i++] = (BYTE)(wc >> 8); /* Put 1st byte */ + } else { /* SBC */ + if (wc == 0 || strchr("+,;=[]", (int)wc)) { /* Replace illegal characters for SFN */ + wc = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ + } else { + if (IsUpper(wc)) { /* ASCII upper case? */ + b |= 2; + } + if (IsLower(wc)) { /* ASCII lower case? */ + b |= 1; wc -= 0x20; + } + } + } + dp->fn[i++] = (BYTE)wc; + } + + if (dp->fn[0] == DDEM) dp->fn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */ + + if (ni == 8) b <<= 2; /* Shift capital flags if no extension */ + if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) cf |= NS_LFN; /* LFN entry needs to be created if composite capitals */ + if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended character, NT flags are created */ + if (b & 0x01) cf |= NS_EXT; /* NT flag (Extension has small capital letters only) */ + if (b & 0x04) cf |= NS_BODY; /* NT flag (Body has small capital letters only) */ + } + + dp->fn[NSFLAG] = cf; /* SFN is created into dp->fn[] */ + + return FR_OK; + + +#else /* FF_USE_LFN : Non-LFN configuration */ + BYTE c, d, *sfn; + UINT ni, si, i; + const char *p; + + /* Create file name in directory form */ + p = *path; sfn = dp->fn; + memset(sfn, ' ', 11); + si = i = 0; ni = 8; +#if FF_FS_RPATH != 0 + if (p[si] == '.') { /* Is this a dot entry? */ + for (;;) { + c = (BYTE)p[si++]; + if (c != '.' || si >= 3) break; + sfn[i++] = c; + } + if (!IsSeparator(c) && c > ' ') return FR_INVALID_NAME; + *path = p + si; /* Return pointer to the next segment */ + sfn[NSFLAG] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of the path */ + return FR_OK; + } +#endif + for (;;) { + c = (BYTE)p[si++]; /* Get a byte */ + if (c <= ' ') break; /* Break if end of the path name */ + if (IsSeparator(c)) { /* Break if a separator is found */ + while (IsSeparator(p[si])) si++; /* Skip duplicated separator if exist */ + break; + } + if (c == '.' || i >= ni) { /* End of body or field overflow? */ + if (ni == 11 || c != '.') return FR_INVALID_NAME; /* Field overflow or invalid dot? */ + i = 8; ni = 11; /* Enter file extension field */ + continue; + } +#if FF_CODE_PAGE == 0 + if (ExCvt && c >= 0x80) { /* Is SBC extended character? */ + c = ExCvt[c & 0x7F]; /* To upper SBC extended character */ + } +#elif FF_CODE_PAGE < 900 + if (c >= 0x80) { /* Is SBC extended character? */ + c = ExCvt[c & 0x7F]; /* To upper SBC extended character */ + } +#endif + if (dbc_1st(c)) { /* Check if it is a DBC 1st byte */ + d = (BYTE)p[si++]; /* Get 2nd byte */ + if (!dbc_2nd(d) || i >= ni - 1) return FR_INVALID_NAME; /* Reject invalid DBC */ + sfn[i++] = c; + sfn[i++] = d; + } else { /* SBC */ + if (strchr("*+,:;<=>[]|\"\?\x7F", (int)c)) return FR_INVALID_NAME; /* Reject illegal chrs for SFN */ + if (IsLower(c)) c -= 0x20; /* To upper */ + sfn[i++] = c; + } + } + *path = &p[si]; /* Return pointer to the next segment */ + if (i == 0) return FR_INVALID_NAME; /* Reject nul string */ + + if (sfn[0] == DDEM) sfn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */ + sfn[NSFLAG] = (c <= ' ' || p[si] <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of the path */ + + return FR_OK; +#endif /* FF_USE_LFN */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* Follow a file path */ +/*-----------------------------------------------------------------------*/ + +static FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ + DIR* dp, /* Directory object to return last directory and found object */ + const TCHAR* path /* Full-path string to find a file or directory */ +) +{ + FRESULT res; + BYTE ns; + FATFS *fs = dp->obj.fs; + + +#if FF_FS_RPATH != 0 + if (!IsSeparator(*path) && (FF_STR_VOLUME_ID != 2 || !IsTerminator(*path))) { /* Without heading separator */ + dp->obj.sclust = fs->cdir; /* Start at the current directory */ + } else +#endif + { /* With heading separator */ + while (IsSeparator(*path)) path++; /* Strip separators */ + dp->obj.sclust = 0; /* Start from the root directory */ + } +#if FF_FS_EXFAT + dp->obj.n_frag = 0; /* Invalidate last fragment counter of the object */ +#if FF_FS_RPATH != 0 + if (fs->fs_type == FS_EXFAT && dp->obj.sclust) { /* exFAT: Retrieve the sub-directory's status */ + DIR dj; + + dp->obj.c_scl = fs->cdc_scl; + dp->obj.c_size = fs->cdc_size; + dp->obj.c_ofs = fs->cdc_ofs; + res = load_obj_xdir(&dj, &dp->obj); + if (res != FR_OK) return res; + dp->obj.objsize = ld_dword(fs->dirbuf + XDIR_FileSize); + dp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2; + } +#endif +#endif + + if ((UINT)*path < ' ') { /* Null path name is the origin directory itself */ + dp->fn[NSFLAG] = NS_NONAME; + res = dir_sdi(dp, 0); + + } else { /* Follow path */ + for (;;) { + res = create_name(dp, &path); /* Get a segment name of the path */ + if (res != FR_OK) break; + res = dir_find(dp); /* Find an object with the segment name */ + ns = dp->fn[NSFLAG]; + if (res != FR_OK) { /* Failed to find the object */ + if (res == FR_NO_FILE) { /* Object is not found */ + if (FF_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exist, stay there */ + if (!(ns & NS_LAST)) continue; /* Continue to follow if not last segment */ + dp->fn[NSFLAG] = NS_NONAME; + res = FR_OK; + } else { /* Could not find the object */ + if (!(ns & NS_LAST)) res = FR_NO_PATH; /* Adjust error code if not last segment */ + } + } + break; + } + if (ns & NS_LAST) break; /* Last segment matched. Function completed. */ + /* Get into the sub-directory */ + if (!(dp->obj.attr & AM_DIR)) { /* It is not a sub-directory and cannot follow */ + res = FR_NO_PATH; break; + } +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* Save containing directory information for next dir */ + dp->obj.c_scl = dp->obj.sclust; + dp->obj.c_size = ((DWORD)dp->obj.objsize & 0xFFFFFF00) | dp->obj.stat; + dp->obj.c_ofs = dp->blk_ofs; + init_alloc_info(fs, &dp->obj); /* Open next directory */ + } else +#endif + { + dp->obj.sclust = ld_clust(fs, fs->win + dp->dptr % SS(fs)); /* Open next directory */ + } + } + } + + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Get logical drive number from path name */ +/*-----------------------------------------------------------------------*/ + +static int get_ldnumber ( /* Returns logical drive number (-1:invalid drive number or null pointer) */ + const TCHAR** path /* Pointer to pointer to the path name */ +) +{ + const TCHAR *tp, *tt; + TCHAR tc; + int i; + int vol = -1; +#if FF_STR_VOLUME_ID /* Find string volume ID */ + const char *sp; + char c; +#endif + + tt = tp = *path; + if (!tp) return vol; /* Invalid path name? */ + do tc = *tt++; while (!IsTerminator(tc) && tc != ':'); /* Find a colon in the path */ + + if (tc == ':') { /* DOS/Windows style volume ID? */ + i = FF_VOLUMES; + if (IsDigit(*tp) && tp + 2 == tt) { /* Is there a numeric volume ID + colon? */ + i = (int)*tp - '0'; /* Get the LD number */ + } +#if FF_STR_VOLUME_ID == 1 /* Arbitrary string is enabled */ + else { + i = 0; + do { + sp = VolumeStr[i]; tp = *path; /* This string volume ID and path name */ + do { /* Compare the volume ID with path name */ + c = *sp++; tc = *tp++; + if (IsLower(c)) c -= 0x20; + if (IsLower(tc)) tc -= 0x20; + } while (c && (TCHAR)c == tc); + } while ((c || tp != tt) && ++i < FF_VOLUMES); /* Repeat for each id until pattern match */ + } +#endif + if (i < FF_VOLUMES) { /* If a volume ID is found, get the drive number and strip it */ + vol = i; /* Drive number */ + *path = tt; /* Snip the drive prefix off */ + } + return vol; + } +#if FF_STR_VOLUME_ID == 2 /* Unix style volume ID is enabled */ + if (*tp == '/') { /* Is there a volume ID? */ + while (*(tp + 1) == '/') tp++; /* Skip duplicated separator */ + i = 0; + do { + tt = tp; sp = VolumeStr[i]; /* Path name and this string volume ID */ + do { /* Compare the volume ID with path name */ + c = *sp++; tc = *(++tt); + if (IsLower(c)) c -= 0x20; + if (IsLower(tc)) tc -= 0x20; + } while (c && (TCHAR)c == tc); + } while ((c || (tc != '/' && !IsTerminator(tc))) && ++i < FF_VOLUMES); /* Repeat for each ID until pattern match */ + if (i < FF_VOLUMES) { /* If a volume ID is found, get the drive number and strip it */ + vol = i; /* Drive number */ + *path = tt; /* Snip the drive prefix off */ + } + return vol; + } +#endif + /* No drive prefix is found */ +#if FF_FS_RPATH != 0 + vol = CurrVol; /* Default drive is current drive */ +#else + vol = 0; /* Default drive is 0 */ +#endif + return vol; /* Return the default drive */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* GPT support functions */ +/*-----------------------------------------------------------------------*/ + +#if FF_LBA64 + +/* Calculate CRC32 in byte-by-byte */ + +static DWORD crc32 ( /* Returns next CRC value */ + DWORD crc, /* Current CRC value */ + BYTE d /* A byte to be processed */ +) +{ + BYTE b; + + + for (b = 1; b; b <<= 1) { + crc ^= (d & b) ? 1 : 0; + crc = (crc & 1) ? crc >> 1 ^ 0xEDB88320 : crc >> 1; + } + return crc; +} + + +/* Check validity of GPT header */ + +static int test_gpt_header ( /* 0:Invalid, 1:Valid */ + const BYTE* gpth /* Pointer to the GPT header */ +) +{ + UINT i; + DWORD bcc; + + + if (memcmp(gpth + GPTH_Sign, "EFI PART" "\0\0\1\0" "\x5C\0\0", 16)) return 0; /* Check sign, version (1.0) and length (92) */ + for (i = 0, bcc = 0xFFFFFFFF; i < 92; i++) { /* Check header BCC */ + bcc = crc32(bcc, i - GPTH_Bcc < 4 ? 0 : gpth[i]); + } + if (~bcc != ld_dword(gpth + GPTH_Bcc)) return 0; + if (ld_dword(gpth + GPTH_PteSize) != SZ_GPTE) return 0; /* Table entry size (must be SZ_GPTE bytes) */ + if (ld_dword(gpth + GPTH_PtNum) > 128) return 0; /* Table size (must be 128 entries or less) */ + + return 1; +} + +#if !FF_FS_READONLY && FF_USE_MKFS + +/* Generate random value */ +static DWORD make_rand ( + DWORD seed, /* Seed value */ + BYTE* buff, /* Output buffer */ + UINT n /* Data length */ +) +{ + UINT r; + + + if (seed == 0) seed = 1; + do { + for (r = 0; r < 8; r++) seed = seed & 1 ? seed >> 1 ^ 0xA3000000 : seed >> 1; /* Shift 8 bits the 32-bit LFSR */ + *buff++ = (BYTE)seed; + } while (--n); + return seed; +} + +#endif +#endif + + + +/*-----------------------------------------------------------------------*/ +/* Load a sector and check if it is an FAT VBR */ +/*-----------------------------------------------------------------------*/ + +/* Check what the sector is */ + +static UINT check_fs ( /* 0:FAT/FAT32 VBR, 1:exFAT VBR, 2:Not FAT and valid BS, 3:Not FAT and invalid BS, 4:Disk error */ + FATFS* fs, /* Filesystem object */ + LBA_t sect /* Sector to load and check if it is an FAT-VBR or not */ +) +{ + WORD w, sign; + BYTE b; + + + fs->wflag = 0; fs->winsect = (LBA_t)0 - 1; /* Invaidate window */ + if (move_window(fs, sect) != FR_OK) return 4; /* Load the boot sector */ + sign = ld_word(fs->win + BS_55AA); +#if FF_FS_EXFAT + if (sign == 0xAA55 && !memcmp(fs->win + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11)) return 1; /* It is an exFAT VBR */ +#endif + b = fs->win[BS_JmpBoot]; + if (b == 0xEB || b == 0xE9 || b == 0xE8) { /* Valid JumpBoot code? (short jump, near jump or near call) */ + if (sign == 0xAA55 && !memcmp(fs->win + BS_FilSysType32, "FAT32 ", 8)) { + return 0; /* It is an FAT32 VBR */ + } + /* FAT volumes formatted with early MS-DOS lack BS_55AA and BS_FilSysType, so FAT VBR needs to be identified without them. */ + w = ld_word(fs->win + BPB_BytsPerSec); + b = fs->win[BPB_SecPerClus]; + if ((w & (w - 1)) == 0 && w >= FF_MIN_SS && w <= FF_MAX_SS /* Properness of sector size (512-4096 and 2^n) */ + && b != 0 && (b & (b - 1)) == 0 /* Properness of cluster size (2^n) */ + && ld_word(fs->win + BPB_RsvdSecCnt) != 0 /* Properness of reserved sectors (MNBZ) */ + && (UINT)fs->win[BPB_NumFATs] - 1 <= 1 /* Properness of FATs (1 or 2) */ + && ld_word(fs->win + BPB_RootEntCnt) != 0 /* Properness of root dir entries (MNBZ) */ + && (ld_word(fs->win + BPB_TotSec16) >= 128 || ld_dword(fs->win + BPB_TotSec32) >= 0x10000) /* Properness of volume sectors (>=128) */ + && ld_word(fs->win + BPB_FATSz16) != 0) { /* Properness of FAT size (MNBZ) */ + return 0; /* It can be presumed an FAT VBR */ + } + } + return sign == 0xAA55 ? 2 : 3; /* Not an FAT VBR (valid or invalid BS) */ +} + + +/* Find an FAT volume */ +/* (It supports only generic partitioning rules, MBR, GPT and SFD) */ + +static UINT find_volume ( /* Returns BS status found in the hosting drive */ + FATFS* fs, /* Filesystem object */ + UINT part /* Partition to fined = 0:auto, 1..:forced */ +) +{ + UINT fmt, i; + DWORD mbr_pt[4]; + + + fmt = check_fs(fs, 0); /* Load sector 0 and check if it is an FAT VBR as SFD format */ + if (fmt != 2 && (fmt >= 3 || part == 0)) return fmt; /* Returns if it is an FAT VBR as auto scan, not a BS or disk error */ + + /* Sector 0 is not an FAT VBR or forced partition number wants a partition */ + +#if FF_LBA64 + if (fs->win[MBR_Table + PTE_System] == 0xEE) { /* GPT protective MBR? */ + DWORD n_ent, v_ent, ofs; + QWORD pt_lba; + + if (move_window(fs, 1) != FR_OK) return 4; /* Load GPT header sector (next to MBR) */ + if (!test_gpt_header(fs->win)) return 3; /* Check if GPT header is valid */ + n_ent = ld_dword(fs->win + GPTH_PtNum); /* Number of entries */ + pt_lba = ld_qword(fs->win + GPTH_PtOfs); /* Table location */ + for (v_ent = i = 0; i < n_ent; i++) { /* Find FAT partition */ + if (move_window(fs, pt_lba + i * SZ_GPTE / SS(fs)) != FR_OK) return 4; /* PT sector */ + ofs = i * SZ_GPTE % SS(fs); /* Offset in the sector */ + if (!memcmp(fs->win + ofs + GPTE_PtGuid, GUID_MS_Basic, 16)) { /* MS basic data partition? */ + v_ent++; + fmt = check_fs(fs, ld_qword(fs->win + ofs + GPTE_FstLba)); /* Load VBR and check status */ + if (part == 0 && fmt <= 1) return fmt; /* Auto search (valid FAT volume found first) */ + if (part != 0 && v_ent == part) return fmt; /* Forced partition order (regardless of it is valid or not) */ + } + } + return 3; /* Not found */ + } +#endif + if (FF_MULTI_PARTITION && part > 4) return 3; /* MBR has 4 partitions max */ + for (i = 0; i < 4; i++) { /* Load partition offset in the MBR */ + mbr_pt[i] = ld_dword(fs->win + MBR_Table + i * SZ_PTE + PTE_StLba); + } + i = part ? part - 1 : 0; /* Table index to find first */ + do { /* Find an FAT volume */ + fmt = mbr_pt[i] ? check_fs(fs, mbr_pt[i]) : 3; /* Check if the partition is FAT */ + } while (part == 0 && fmt >= 2 && ++i < 4); + return fmt; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Determine logical drive number and mount the volume if needed */ +/*-----------------------------------------------------------------------*/ + +static FRESULT mount_volume ( /* FR_OK(0): successful, !=0: an error occurred */ + const TCHAR** path, /* Pointer to pointer to the path name (drive number) */ + FATFS** rfs, /* Pointer to pointer to the found filesystem object */ + BYTE mode /* !=0: Check write protection for write access */ +) +{ + int vol; + DSTATUS stat; + LBA_t bsect; + DWORD tsect, sysect, fasize, nclst, szbfat; + WORD nrsv; + FATFS *fs; + UINT fmt; + + + /* Get logical drive number */ + *rfs = 0; + vol = get_ldnumber(path); + if (vol < 0) return FR_INVALID_DRIVE; + + /* Check if the filesystem object is valid or not */ + fs = FatFs[vol]; /* Get pointer to the filesystem object */ + if (!fs) return FR_NOT_ENABLED; /* Is the filesystem object available? */ +#if FF_FS_REENTRANT + if (!lock_fs(fs)) return FR_TIMEOUT; /* Lock the volume */ +#endif + *rfs = fs; /* Return pointer to the filesystem object */ + + mode &= (BYTE)~FA_READ; /* Desired access mode, write access or not */ + if (fs->fs_type != 0) { /* If the volume has been mounted */ + stat = disk_status(fs->pdrv); + if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized */ + if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check write protection if needed */ + return FR_WRITE_PROTECTED; + } + return FR_OK; /* The filesystem object is already valid */ + } + } + + /* The filesystem object is not valid. */ + /* Following code attempts to mount the volume. (find an FAT volume, analyze the BPB and initialize the filesystem object) */ + + fs->fs_type = 0; /* Clear the filesystem object */ + fs->pdrv = LD2PD(vol); /* Volume hosting physical drive */ + stat = disk_initialize(fs->pdrv); /* Initialize the physical drive */ + if (stat & STA_NOINIT) { /* Check if the initialization succeeded */ + return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */ + } + if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */ + return FR_WRITE_PROTECTED; + } +#if FF_MAX_SS != FF_MIN_SS /* Get sector size (multiple sector size cfg only) */ + if (disk_ioctl(fs->pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) return FR_DISK_ERR; + if (SS(fs) > FF_MAX_SS || SS(fs) < FF_MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR; +#endif + + /* Find an FAT volume on the drive */ + fmt = find_volume(fs, LD2PT(vol)); + if (fmt == 4) return FR_DISK_ERR; /* An error occured in the disk I/O layer */ + if (fmt >= 2) return FR_NO_FILESYSTEM; /* No FAT volume is found */ + bsect = fs->winsect; /* Volume offset */ + + /* An FAT volume is found (bsect). Following code initializes the filesystem object */ + +#if FF_FS_EXFAT + if (fmt == 1) { + QWORD maxlba; + DWORD so, cv, bcl, i; + + for (i = BPB_ZeroedEx; i < BPB_ZeroedEx + 53 && fs->win[i] == 0; i++) ; /* Check zero filler */ + if (i < BPB_ZeroedEx + 53) return FR_NO_FILESYSTEM; + + if (ld_word(fs->win + BPB_FSVerEx) != 0x100) return FR_NO_FILESYSTEM; /* Check exFAT version (must be version 1.0) */ + + if (1 << fs->win[BPB_BytsPerSecEx] != SS(fs)) { /* (BPB_BytsPerSecEx must be equal to the physical sector size) */ + return FR_NO_FILESYSTEM; + } + + maxlba = ld_qword(fs->win + BPB_TotSecEx) + bsect; /* Last LBA of the volume + 1 */ + if (!FF_LBA64 && maxlba >= 0x100000000) return FR_NO_FILESYSTEM; /* (It cannot be accessed in 32-bit LBA) */ + + fs->fsize = ld_dword(fs->win + BPB_FatSzEx); /* Number of sectors per FAT */ + + fs->n_fats = fs->win[BPB_NumFATsEx]; /* Number of FATs */ + if (fs->n_fats != 1) return FR_NO_FILESYSTEM; /* (Supports only 1 FAT) */ + + fs->csize = 1 << fs->win[BPB_SecPerClusEx]; /* Cluster size */ + if (fs->csize == 0) return FR_NO_FILESYSTEM; /* (Must be 1..32768 sectors) */ + + nclst = ld_dword(fs->win + BPB_NumClusEx); /* Number of clusters */ + if (nclst > MAX_EXFAT) return FR_NO_FILESYSTEM; /* (Too many clusters) */ + fs->n_fatent = nclst + 2; + + /* Boundaries and Limits */ + fs->volbase = bsect; + fs->database = bsect + ld_dword(fs->win + BPB_DataOfsEx); + fs->fatbase = bsect + ld_dword(fs->win + BPB_FatOfsEx); + if (maxlba < (QWORD)fs->database + nclst * fs->csize) return FR_NO_FILESYSTEM; /* (Volume size must not be smaller than the size requiered) */ + fs->dirbase = ld_dword(fs->win + BPB_RootClusEx); + + /* Get bitmap location and check if it is contiguous (implementation assumption) */ + so = i = 0; + for (;;) { /* Find the bitmap entry in the root directory (in only first cluster) */ + if (i == 0) { + if (so >= fs->csize) return FR_NO_FILESYSTEM; /* Not found? */ + if (move_window(fs, clst2sect(fs, (DWORD)fs->dirbase) + so) != FR_OK) return FR_DISK_ERR; + so++; + } + if (fs->win[i] == ET_BITMAP) break; /* Is it a bitmap entry? */ + i = (i + SZDIRE) % SS(fs); /* Next entry */ + } + bcl = ld_dword(fs->win + i + 20); /* Bitmap cluster */ + if (bcl < 2 || bcl >= fs->n_fatent) return FR_NO_FILESYSTEM; /* (Wrong cluster#) */ + fs->bitbase = fs->database + fs->csize * (bcl - 2); /* Bitmap sector */ + for (;;) { /* Check if bitmap is contiguous */ + if (move_window(fs, fs->fatbase + bcl / (SS(fs) / 4)) != FR_OK) return FR_DISK_ERR; + cv = ld_dword(fs->win + bcl % (SS(fs) / 4) * 4); + if (cv == 0xFFFFFFFF) break; /* Last link? */ + if (cv != ++bcl) return FR_NO_FILESYSTEM; /* Fragmented? */ + } + +#if !FF_FS_READONLY + fs->last_clst = fs->free_clst = 0xFFFFFFFF; /* Initialize cluster allocation information */ +#endif + fmt = FS_EXFAT; /* FAT sub-type */ + } else +#endif /* FF_FS_EXFAT */ + { + if (ld_word(fs->win + BPB_BytsPerSec) != SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_BytsPerSec must be equal to the physical sector size) */ + + fasize = ld_word(fs->win + BPB_FATSz16); /* Number of sectors per FAT */ + if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32); + fs->fsize = fasize; + + fs->n_fats = fs->win[BPB_NumFATs]; /* Number of FATs */ + if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */ + fasize *= fs->n_fats; /* Number of sectors for FAT area */ + + fs->csize = fs->win[BPB_SecPerClus]; /* Cluster size */ + if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM; /* (Must be power of 2) */ + + fs->n_rootdir = ld_word(fs->win + BPB_RootEntCnt); /* Number of root directory entries */ + if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM; /* (Must be sector aligned) */ + + tsect = ld_word(fs->win + BPB_TotSec16); /* Number of sectors on the volume */ + if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32); + + nrsv = ld_word(fs->win + BPB_RsvdSecCnt); /* Number of reserved sectors */ + if (nrsv == 0) return FR_NO_FILESYSTEM; /* (Must not be 0) */ + + /* Determine the FAT sub type */ + sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZDIRE); /* RSV + FAT + DIR */ + if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ + if (nclst == 0) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + fmt = 0; + if (nclst <= MAX_FAT32) fmt = FS_FAT32; + if (nclst <= MAX_FAT16) fmt = FS_FAT16; + if (nclst <= MAX_FAT12) fmt = FS_FAT12; + if (fmt == 0) return FR_NO_FILESYSTEM; + + /* Boundaries and Limits */ + fs->n_fatent = nclst + 2; /* Number of FAT entries */ + fs->volbase = bsect; /* Volume start sector */ + fs->fatbase = bsect + nrsv; /* FAT start sector */ + fs->database = bsect + sysect; /* Data start sector */ + if (fmt == FS_FAT32) { + if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM; /* (Must be FAT32 revision 0.0) */ + if (fs->n_rootdir != 0) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ + fs->dirbase = ld_dword(fs->win + BPB_RootClus32); /* Root directory start cluster */ + szbfat = fs->n_fatent * 4; /* (Needed FAT size) */ + } else { + if (fs->n_rootdir == 0) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */ + fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ + szbfat = (fmt == FS_FAT16) ? /* (Needed FAT size) */ + fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1); + } + if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_FATSz must not be less than the size needed) */ + +#if !FF_FS_READONLY + /* Get FSInfo if available */ + fs->last_clst = fs->free_clst = 0xFFFFFFFF; /* Initialize cluster allocation information */ + fs->fsi_flag = 0x80; +#if (FF_FS_NOFSINFO & 3) != 3 + if (fmt == FS_FAT32 /* Allow to update FSInfo only if BPB_FSInfo32 == 1 */ + && ld_word(fs->win + BPB_FSInfo32) == 1 + && move_window(fs, bsect + 1) == FR_OK) + { + fs->fsi_flag = 0; + if (ld_word(fs->win + BS_55AA) == 0xAA55 /* Load FSInfo data if available */ + && ld_dword(fs->win + FSI_LeadSig) == 0x41615252 + && ld_dword(fs->win + FSI_StrucSig) == 0x61417272) + { +#if (FF_FS_NOFSINFO & 1) == 0 + fs->free_clst = ld_dword(fs->win + FSI_Free_Count); +#endif +#if (FF_FS_NOFSINFO & 2) == 0 + fs->last_clst = ld_dword(fs->win + FSI_Nxt_Free); +#endif + } + } +#endif /* (FF_FS_NOFSINFO & 3) != 3 */ +#endif /* !FF_FS_READONLY */ + } + + fs->fs_type = (BYTE)fmt;/* FAT sub-type */ + fs->id = ++Fsid; /* Volume mount ID */ +#if FF_USE_LFN == 1 + fs->lfnbuf = LfnBuf; /* Static LFN working buffer */ +#if FF_FS_EXFAT + fs->dirbuf = DirBuf; /* Static directory block scratchpad buuffer */ +#endif +#endif +#if FF_FS_RPATH != 0 + fs->cdir = 0; /* Initialize current directory */ +#endif +#if FF_FS_LOCK != 0 /* Clear file lock semaphores */ + clear_lock(fs); +#endif + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Check if the file/directory object is valid or not */ +/*-----------------------------------------------------------------------*/ + +static FRESULT validate ( /* Returns FR_OK or FR_INVALID_OBJECT */ + FFOBJID* obj, /* Pointer to the FFOBJID, the 1st member in the FIL/DIR object, to check validity */ + FATFS** rfs /* Pointer to pointer to the owner filesystem object to return */ +) +{ + FRESULT res = FR_INVALID_OBJECT; + + + if (obj && obj->fs && obj->fs->fs_type && obj->id == obj->fs->id) { /* Test if the object is valid */ +#if FF_FS_REENTRANT + if (lock_fs(obj->fs)) { /* Obtain the filesystem object */ + if (!(disk_status(obj->fs->pdrv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialized */ + res = FR_OK; + } else { + unlock_fs(obj->fs, FR_OK); + } + } else { + res = FR_TIMEOUT; + } +#else + if (!(disk_status(obj->fs->pdrv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialized */ + res = FR_OK; + } +#endif + } + *rfs = (res == FR_OK) ? obj->fs : 0; /* Corresponding filesystem object */ + return res; +} + + + + +/*--------------------------------------------------------------------------- + + Public Functions (FatFs API) + +----------------------------------------------------------------------------*/ + + + +/*-----------------------------------------------------------------------*/ +/* Mount/Unmount a Logical Drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mount ( + FATFS* fs, /* Pointer to the filesystem object to be registered (NULL:unmount)*/ + const TCHAR* path, /* Logical drive number to be mounted/unmounted */ + BYTE opt /* Mount option: 0=Do not mount (delayed mount), 1=Mount immediately */ +) +{ + FATFS *cfs; + int vol; + FRESULT res; + const TCHAR *rp = path; + + + /* Get logical drive number */ + vol = get_ldnumber(&rp); + if (vol < 0) return FR_INVALID_DRIVE; + cfs = FatFs[vol]; /* Pointer to fs object */ + + if (cfs) { +#if FF_FS_LOCK != 0 + clear_lock(cfs); +#endif +#if FF_FS_REENTRANT /* Discard sync object of the current volume */ + if (!ff_del_syncobj(cfs->sobj)) return FR_INT_ERR; +#endif + cfs->fs_type = 0; /* Clear old fs object */ + } + + if (fs) { + fs->fs_type = 0; /* Clear new fs object */ +#if FF_FS_REENTRANT /* Create sync object for the new volume */ + if (!ff_cre_syncobj((BYTE)vol, &fs->sobj)) return FR_INT_ERR; +#endif + } + FatFs[vol] = fs; /* Register new fs object */ + + if (opt == 0) return FR_OK; /* Do not mount now, it will be mounted later */ + + res = mount_volume(&path, &fs, 0); /* Force mounted the volume */ + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Open or Create a File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_open ( + FIL* fp, /* Pointer to the blank file object */ + const TCHAR* path, /* Pointer to the file name */ + BYTE mode /* Access mode and open mode flags */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; +#if !FF_FS_READONLY + DWORD cl, bcs, clst, tm; + LBA_t sc; + FSIZE_t ofs; +#endif + DEF_NAMBUF + + + if (!fp) return FR_INVALID_OBJECT; + + /* Get logical drive number */ + mode &= FF_FS_READONLY ? FA_READ : FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_CREATE_NEW | FA_OPEN_ALWAYS | FA_OPEN_APPEND; + res = mount_volume(&path, &fs, mode); + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the file path */ +#if !FF_FS_READONLY /* Read/Write configuration */ + if (res == FR_OK) { + if (dj.fn[NSFLAG] & NS_NONAME) { /* Origin directory itself? */ + res = FR_INVALID_NAME; + } +#if FF_FS_LOCK != 0 + else { + res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0); /* Check if the file can be used */ + } +#endif + } + /* Create or Open a file */ + if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) { + if (res != FR_OK) { /* No file, create new */ + if (res == FR_NO_FILE) { /* There is no file to open, create a new entry */ +#if FF_FS_LOCK != 0 + res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES; +#else + res = dir_register(&dj); +#endif + } + mode |= FA_CREATE_ALWAYS; /* File is created */ + } + else { /* Any object with the same name is already existing */ + if (dj.obj.attr & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */ + res = FR_DENIED; + } else { + if (mode & FA_CREATE_NEW) res = FR_EXIST; /* Cannot create as new file */ + } + } + if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate the file if overwrite mode */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + /* Get current allocation info */ + fp->obj.fs = fs; + init_alloc_info(fs, &fp->obj); + /* Set directory entry block initial state */ + memset(fs->dirbuf + 2, 0, 30); /* Clear 85 entry except for NumSec */ + memset(fs->dirbuf + 38, 0, 26); /* Clear C0 entry except for NumName and NameHash */ + fs->dirbuf[XDIR_Attr] = AM_ARC; + st_dword(fs->dirbuf + XDIR_CrtTime, GET_FATTIME()); + fs->dirbuf[XDIR_GenFlags] = 1; + res = store_xdir(&dj); + if (res == FR_OK && fp->obj.sclust != 0) { /* Remove the cluster chain if exist */ + res = remove_chain(&fp->obj, fp->obj.sclust, 0); + fs->last_clst = fp->obj.sclust - 1; /* Reuse the cluster hole */ + } + } else +#endif + { + /* Set directory entry initial state */ + tm = GET_FATTIME(); /* Set created time */ + st_dword(dj.dir + DIR_CrtTime, tm); + st_dword(dj.dir + DIR_ModTime, tm); + cl = ld_clust(fs, dj.dir); /* Get current cluster chain */ + dj.dir[DIR_Attr] = AM_ARC; /* Reset attribute */ + st_clust(fs, dj.dir, 0); /* Reset file allocation info */ + st_dword(dj.dir + DIR_FileSize, 0); + fs->wflag = 1; + if (cl != 0) { /* Remove the cluster chain if exist */ + sc = fs->winsect; + res = remove_chain(&dj.obj, cl, 0); + if (res == FR_OK) { + res = move_window(fs, sc); + fs->last_clst = cl - 1; /* Reuse the cluster hole */ + } + } + } + } + } + else { /* Open an existing file */ + if (res == FR_OK) { /* Is the object exsiting? */ + if (dj.obj.attr & AM_DIR) { /* File open against a directory */ + res = FR_NO_FILE; + } else { + if ((mode & FA_WRITE) && (dj.obj.attr & AM_RDO)) { /* Write mode open against R/O file */ + res = FR_DENIED; + } + } + } + } + if (res == FR_OK) { + if (mode & FA_CREATE_ALWAYS) mode |= FA_MODIFIED; /* Set file change flag if created or overwritten */ + fp->dir_sect = fs->winsect; /* Pointer to the directory entry */ + fp->dir_ptr = dj.dir; +#if FF_FS_LOCK != 0 + fp->obj.lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0); /* Lock the file for this session */ + if (fp->obj.lockid == 0) res = FR_INT_ERR; +#endif + } +#else /* R/O configuration */ + if (res == FR_OK) { + if (dj.fn[NSFLAG] & NS_NONAME) { /* Is it origin directory itself? */ + res = FR_INVALID_NAME; + } else { + if (dj.obj.attr & AM_DIR) { /* Is it a directory? */ + res = FR_NO_FILE; + } + } + } +#endif + + if (res == FR_OK) { +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + fp->obj.c_scl = dj.obj.sclust; /* Get containing directory info */ + fp->obj.c_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat; + fp->obj.c_ofs = dj.blk_ofs; + init_alloc_info(fs, &fp->obj); + } else +#endif + { + fp->obj.sclust = ld_clust(fs, dj.dir); /* Get object allocation info */ + fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize); + } +#if FF_USE_FASTSEEK + fp->cltbl = 0; /* Disable fast seek mode */ +#endif + fp->obj.fs = fs; /* Validate the file object */ + fp->obj.id = fs->id; + fp->flag = mode; /* Set file access mode */ + fp->err = 0; /* Clear error flag */ + fp->sect = 0; /* Invalidate current data sector */ + fp->fptr = 0; /* Set file pointer top of the file */ +#if !FF_FS_READONLY +#if !FF_FS_TINY + memset(fp->buf, 0, sizeof fp->buf); /* Clear sector buffer */ +#endif + if ((mode & FA_SEEKEND) && fp->obj.objsize > 0) { /* Seek to end of file if FA_OPEN_APPEND is specified */ + fp->fptr = fp->obj.objsize; /* Offset to seek */ + bcs = (DWORD)fs->csize * SS(fs); /* Cluster size in byte */ + clst = fp->obj.sclust; /* Follow the cluster chain */ + for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) { + clst = get_fat(&fp->obj, clst); + if (clst <= 1) res = FR_INT_ERR; + if (clst == 0xFFFFFFFF) res = FR_DISK_ERR; + } + fp->clust = clst; + if (res == FR_OK && ofs % SS(fs)) { /* Fill sector buffer if not on the sector boundary */ + sc = clst2sect(fs, clst); + if (sc == 0) { + res = FR_INT_ERR; + } else { + fp->sect = sc + (DWORD)(ofs / SS(fs)); +#if !FF_FS_TINY + if (disk_read(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) res = FR_DISK_ERR; +#endif + } + } +#if FF_FS_LOCK != 0 + if (res != FR_OK) dec_lock(fp->obj.lockid); /* Decrement file open counter if seek failed */ +#endif + } +#endif + } + + FREE_NAMBUF(); + } + + if (res != FR_OK) fp->obj.fs = 0; /* Invalidate file object on error */ + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_read ( + FIL* fp, /* Open file to be read */ + void* buff, /* Data buffer to store the read data */ + UINT btr, /* Number of bytes to read */ + UINT* br /* Number of bytes read */ +) +{ + FRESULT res; + FATFS *fs; + DWORD clst; + LBA_t sect; + FSIZE_t remain; + UINT rcnt, cc, csect; + BYTE *rbuff = (BYTE*)buff; + + + *br = 0; /* Clear read byte counter */ + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ + if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + remain = fp->obj.objsize - fp->fptr; + if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + + for ( ; btr > 0; btr -= rcnt, *br += rcnt, rbuff += rcnt, fp->fptr += rcnt) { /* Repeat until btr bytes read */ + if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */ + if (csect == 0) { /* On the cluster boundary? */ + if (fp->fptr == 0) { /* On the top of the file? */ + clst = fp->obj.sclust; /* Follow cluster chain from the origin */ + } else { /* Middle or end of the file */ +#if FF_USE_FASTSEEK + if (fp->cltbl) { + clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ + } else +#endif + { + clst = get_fat(&fp->obj, fp->clust); /* Follow cluster chain on the FAT */ + } + } + if (clst < 2) ABORT(fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + } + sect = clst2sect(fs, fp->clust); /* Get current sector */ + if (sect == 0) ABORT(fs, FR_INT_ERR); + sect += csect; + cc = btr / SS(fs); /* When remaining bytes >= sector size, */ + if (cc > 0) { /* Read maximum contiguous sectors directly */ + if (csect + cc > fs->csize) { /* Clip at cluster boundary */ + cc = fs->csize - csect; + } + if (disk_read(fs->pdrv, rbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR); +#if !FF_FS_READONLY && FF_FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */ +#if FF_FS_TINY + if (fs->wflag && fs->winsect - sect < cc) { + memcpy(rbuff + ((fs->winsect - sect) * SS(fs)), fs->win, SS(fs)); + } +#else + if ((fp->flag & FA_DIRTY) && fp->sect - sect < cc) { + memcpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs)); + } +#endif +#endif + rcnt = SS(fs) * cc; /* Number of bytes transferred */ + continue; + } +#if !FF_FS_TINY + if (fp->sect != sect) { /* Load data sector if not in cache */ +#if !FF_FS_READONLY + if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Fill sector cache */ + } +#endif + fp->sect = sect; + } + rcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes remains in the sector */ + if (rcnt > btr) rcnt = btr; /* Clip it by btr if needed */ +#if FF_FS_TINY + if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */ + memcpy(rbuff, fs->win + fp->fptr % SS(fs), rcnt); /* Extract partial sector */ +#else + memcpy(rbuff, fp->buf + fp->fptr % SS(fs), rcnt); /* Extract partial sector */ +#endif + } + + LEAVE_FF(fs, FR_OK); +} + + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Write File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_write ( + FIL* fp, /* Open file to be written */ + const void* buff, /* Data to be written */ + UINT btw, /* Number of bytes to write */ + UINT* bw /* Number of bytes written */ +) +{ + FRESULT res; + FATFS *fs; + DWORD clst; + LBA_t sect; + UINT wcnt, cc, csect; + const BYTE *wbuff = (const BYTE*)buff; + + + *bw = 0; /* Clear write byte counter */ + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ + if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + + /* Check fptr wrap-around (file size cannot reach 4 GiB at FAT volume) */ + if ((!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) && (DWORD)(fp->fptr + btw) < (DWORD)fp->fptr) { + btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr); + } + + for ( ; btw > 0; btw -= wcnt, *bw += wcnt, wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp->obj.objsize) { /* Repeat until all data written */ + if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1); /* Sector offset in the cluster */ + if (csect == 0) { /* On the cluster boundary? */ + if (fp->fptr == 0) { /* On the top of the file? */ + clst = fp->obj.sclust; /* Follow from the origin */ + if (clst == 0) { /* If no cluster is allocated, */ + clst = create_chain(&fp->obj, 0); /* create a new cluster chain */ + } + } else { /* On the middle or end of the file */ +#if FF_USE_FASTSEEK + if (fp->cltbl) { + clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ + } else +#endif + { + clst = create_chain(&fp->obj, fp->clust); /* Follow or stretch cluster chain on the FAT */ + } + } + if (clst == 0) break; /* Could not allocate a new cluster (disk full) */ + if (clst == 1) ABORT(fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + if (fp->obj.sclust == 0) fp->obj.sclust = clst; /* Set start cluster if the first write */ + } +#if FF_FS_TINY + if (fs->winsect == fp->sect && sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Write-back sector cache */ +#else + if (fp->flag & FA_DIRTY) { /* Write-back sector cache */ + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + sect = clst2sect(fs, fp->clust); /* Get current sector */ + if (sect == 0) ABORT(fs, FR_INT_ERR); + sect += csect; + cc = btw / SS(fs); /* When remaining bytes >= sector size, */ + if (cc > 0) { /* Write maximum contiguous sectors directly */ + if (csect + cc > fs->csize) { /* Clip at cluster boundary */ + cc = fs->csize - csect; + } + if (disk_write(fs->pdrv, wbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR); +#if FF_FS_MINIMIZE <= 2 +#if FF_FS_TINY + if (fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ + memcpy(fs->win, wbuff + ((fs->winsect - sect) * SS(fs)), SS(fs)); + fs->wflag = 0; + } +#else + if (fp->sect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ + memcpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs)); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif +#endif + wcnt = SS(fs) * cc; /* Number of bytes transferred */ + continue; + } +#if FF_FS_TINY + if (fp->fptr >= fp->obj.objsize) { /* Avoid silly cache filling on the growing edge */ + if (sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR); + fs->winsect = sect; + } +#else + if (fp->sect != sect && /* Fill sector cache with file data */ + fp->fptr < fp->obj.objsize && + disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) { + ABORT(fs, FR_DISK_ERR); + } +#endif + fp->sect = sect; + } + wcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes remains in the sector */ + if (wcnt > btw) wcnt = btw; /* Clip it by btw if needed */ +#if FF_FS_TINY + if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */ + memcpy(fs->win + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */ + fs->wflag = 1; +#else + memcpy(fp->buf + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */ + fp->flag |= FA_DIRTY; +#endif + } + + fp->flag |= FA_MODIFIED; /* Set file change flag */ + + LEAVE_FF(fs, FR_OK); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Synchronize the File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_sync ( + FIL* fp /* Open file to be synced */ +) +{ + FRESULT res; + FATFS *fs; + DWORD tm; + BYTE *dir; + + + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res == FR_OK) { + if (fp->flag & FA_MODIFIED) { /* Is there any change to the file? */ +#if !FF_FS_TINY + if (fp->flag & FA_DIRTY) { /* Write-back cached data if needed */ + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + /* Update the directory entry */ + tm = GET_FATTIME(); /* Modified time */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + res = fill_first_frag(&fp->obj); /* Fill first fragment on the FAT if needed */ + if (res == FR_OK) { + res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF); /* Fill last fragment on the FAT if needed */ + } + if (res == FR_OK) { + DIR dj; + DEF_NAMBUF + + INIT_NAMBUF(fs); + res = load_obj_xdir(&dj, &fp->obj); /* Load directory entry block */ + if (res == FR_OK) { + fs->dirbuf[XDIR_Attr] |= AM_ARC; /* Set archive attribute to indicate that the file has been changed */ + fs->dirbuf[XDIR_GenFlags] = fp->obj.stat | 1; /* Update file allocation information */ + st_dword(fs->dirbuf + XDIR_FstClus, fp->obj.sclust); /* Update start cluster */ + st_qword(fs->dirbuf + XDIR_FileSize, fp->obj.objsize); /* Update file size */ + st_qword(fs->dirbuf + XDIR_ValidFileSize, fp->obj.objsize); /* (FatFs does not support Valid File Size feature) */ + st_dword(fs->dirbuf + XDIR_ModTime, tm); /* Update modified time */ + fs->dirbuf[XDIR_ModTime10] = 0; + st_dword(fs->dirbuf + XDIR_AccTime, 0); + res = store_xdir(&dj); /* Restore it to the directory */ + if (res == FR_OK) { + res = sync_fs(fs); + fp->flag &= (BYTE)~FA_MODIFIED; + } + } + FREE_NAMBUF(); + } + } else +#endif + { + res = move_window(fs, fp->dir_sect); + if (res == FR_OK) { + dir = fp->dir_ptr; + dir[DIR_Attr] |= AM_ARC; /* Set archive attribute to indicate that the file has been changed */ + st_clust(fp->obj.fs, dir, fp->obj.sclust); /* Update file allocation information */ + st_dword(dir + DIR_FileSize, (DWORD)fp->obj.objsize); /* Update file size */ + st_dword(dir + DIR_ModTime, tm); /* Update modified time */ + st_word(dir + DIR_LstAccDate, 0); + fs->wflag = 1; + res = sync_fs(fs); /* Restore it to the directory */ + fp->flag &= (BYTE)~FA_MODIFIED; + } + } + } + } + + LEAVE_FF(fs, res); +} + +#endif /* !FF_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Close File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_close ( + FIL* fp /* Open file to be closed */ +) +{ + FRESULT res; + FATFS *fs; + +#if !FF_FS_READONLY + res = f_sync(fp); /* Flush cached data */ + if (res == FR_OK) +#endif + { + res = validate(&fp->obj, &fs); /* Lock volume */ + if (res == FR_OK) { +#if FF_FS_LOCK != 0 + res = dec_lock(fp->obj.lockid); /* Decrement file open counter */ + if (res == FR_OK) fp->obj.fs = 0; /* Invalidate file object */ +#else + fp->obj.fs = 0; /* Invalidate file object */ +#endif +#if FF_FS_REENTRANT + unlock_fs(fs, FR_OK); /* Unlock volume */ +#endif + } + } + return res; +} + + + + +#if FF_FS_RPATH >= 1 +/*-----------------------------------------------------------------------*/ +/* Change Current Directory or Current Drive, Get Current Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_chdrive ( + const TCHAR* path /* Drive number to set */ +) +{ + int vol; + + + /* Get logical drive number */ + vol = get_ldnumber(&path); + if (vol < 0) return FR_INVALID_DRIVE; + CurrVol = (BYTE)vol; /* Set it as current volume */ + + return FR_OK; +} + + + +FRESULT f_chdir ( + const TCHAR* path /* Pointer to the directory path */ +) +{ +#if FF_STR_VOLUME_ID == 2 + UINT i; +#endif + FRESULT res; + DIR dj; + FATFS *fs; + DEF_NAMBUF + + + /* Get logical drive */ + res = mount_volume(&path, &fs, 0); + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the path */ + if (res == FR_OK) { /* Follow completed */ + if (dj.fn[NSFLAG] & NS_NONAME) { /* Is it the start directory itself? */ + fs->cdir = dj.obj.sclust; +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + fs->cdc_scl = dj.obj.c_scl; + fs->cdc_size = dj.obj.c_size; + fs->cdc_ofs = dj.obj.c_ofs; + } +#endif + } else { + if (dj.obj.attr & AM_DIR) { /* It is a sub-directory */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + fs->cdir = ld_dword(fs->dirbuf + XDIR_FstClus); /* Sub-directory cluster */ + fs->cdc_scl = dj.obj.sclust; /* Save containing directory information */ + fs->cdc_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat; + fs->cdc_ofs = dj.blk_ofs; + } else +#endif + { + fs->cdir = ld_clust(fs, dj.dir); /* Sub-directory cluster */ + } + } else { + res = FR_NO_PATH; /* Reached but a file */ + } + } + } + FREE_NAMBUF(); + if (res == FR_NO_FILE) res = FR_NO_PATH; +#if FF_STR_VOLUME_ID == 2 /* Also current drive is changed if in Unix style volume ID */ + if (res == FR_OK) { + for (i = FF_VOLUMES - 1; i && fs != FatFs[i]; i--) ; /* Set current drive */ + CurrVol = (BYTE)i; + } +#endif + } + + LEAVE_FF(fs, res); +} + + +#if FF_FS_RPATH >= 2 +FRESULT f_getcwd ( + TCHAR* buff, /* Pointer to the directory path */ + UINT len /* Size of buff in unit of TCHAR */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; + UINT i, n; + DWORD ccl; + TCHAR *tp = buff; +#if FF_VOLUMES >= 2 + UINT vl; +#if FF_STR_VOLUME_ID + const char *vp; +#endif +#endif + FILINFO fno; + DEF_NAMBUF + + + /* Get logical drive */ + buff[0] = 0; /* Set null string to get current volume */ + res = mount_volume((const TCHAR**)&buff, &fs, 0); /* Get current volume */ + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + + /* Follow parent directories and create the path */ + i = len; /* Bottom of buffer (directory stack base) */ + if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) { /* (Cannot do getcwd on exFAT and returns root path) */ + dj.obj.sclust = fs->cdir; /* Start to follow upper directory from current directory */ + while ((ccl = dj.obj.sclust) != 0) { /* Repeat while current directory is a sub-directory */ + res = dir_sdi(&dj, 1 * SZDIRE); /* Get parent directory */ + if (res != FR_OK) break; + res = move_window(fs, dj.sect); + if (res != FR_OK) break; + dj.obj.sclust = ld_clust(fs, dj.dir); /* Goto parent directory */ + res = dir_sdi(&dj, 0); + if (res != FR_OK) break; + do { /* Find the entry links to the child directory */ + res = DIR_READ_FILE(&dj); + if (res != FR_OK) break; + if (ccl == ld_clust(fs, dj.dir)) break; /* Found the entry */ + res = dir_next(&dj, 0); + } while (res == FR_OK); + if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */ + if (res != FR_OK) break; + get_fileinfo(&dj, &fno); /* Get the directory name and push it to the buffer */ + for (n = 0; fno.fname[n]; n++) ; /* Name length */ + if (i < n + 1) { /* Insufficient space to store the path name? */ + res = FR_NOT_ENOUGH_CORE; break; + } + while (n) buff[--i] = fno.fname[--n]; /* Stack the name */ + buff[--i] = '/'; + } + } + if (res == FR_OK) { + if (i == len) buff[--i] = '/'; /* Is it the root-directory? */ +#if FF_VOLUMES >= 2 /* Put drive prefix */ + vl = 0; +#if FF_STR_VOLUME_ID >= 1 /* String volume ID */ + for (n = 0, vp = (const char*)VolumeStr[CurrVol]; vp[n]; n++) ; + if (i >= n + 2) { + if (FF_STR_VOLUME_ID == 2) *tp++ = (TCHAR)'/'; + for (vl = 0; vl < n; *tp++ = (TCHAR)vp[vl], vl++) ; + if (FF_STR_VOLUME_ID == 1) *tp++ = (TCHAR)':'; + vl++; + } +#else /* Numeric volume ID */ + if (i >= 3) { + *tp++ = (TCHAR)'0' + CurrVol; + *tp++ = (TCHAR)':'; + vl = 2; + } +#endif + if (vl == 0) res = FR_NOT_ENOUGH_CORE; +#endif + /* Add current directory path */ + if (res == FR_OK) { + do *tp++ = buff[i++]; while (i < len); /* Copy stacked path string */ + } + } + FREE_NAMBUF(); + } + + *tp = 0; + LEAVE_FF(fs, res); +} + +#endif /* FF_FS_RPATH >= 2 */ +#endif /* FF_FS_RPATH >= 1 */ + + + +#if FF_FS_MINIMIZE <= 2 +/*-----------------------------------------------------------------------*/ +/* Seek File Read/Write Pointer */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_lseek ( + FIL* fp, /* Pointer to the file object */ + FSIZE_t ofs /* File pointer from top of file */ +) +{ + FRESULT res; + FATFS *fs; + DWORD clst, bcs; + LBA_t nsect; + FSIZE_t ifptr; +#if FF_USE_FASTSEEK + DWORD cl, pcl, ncl, tcl, tlen, ulen; + DWORD *tbl; + LBA_t dsc; +#endif + + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res == FR_OK) res = (FRESULT)fp->err; +#if FF_FS_EXFAT && !FF_FS_READONLY + if (res == FR_OK && fs->fs_type == FS_EXFAT) { + res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF); /* Fill last fragment on the FAT if needed */ + } +#endif + if (res != FR_OK) LEAVE_FF(fs, res); + +#if FF_USE_FASTSEEK + if (fp->cltbl) { /* Fast seek */ + if (ofs == CREATE_LINKMAP) { /* Create CLMT */ + tbl = fp->cltbl; + tlen = *tbl++; ulen = 2; /* Given table size and required table size */ + cl = fp->obj.sclust; /* Origin of the chain */ + if (cl != 0) { + do { + /* Get a fragment */ + tcl = cl; ncl = 0; ulen += 2; /* Top, length and used items */ + do { + pcl = cl; ncl++; + cl = get_fat(&fp->obj, cl); + if (cl <= 1) ABORT(fs, FR_INT_ERR); + if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + } while (cl == pcl + 1); + if (ulen <= tlen) { /* Store the length and top of the fragment */ + *tbl++ = ncl; *tbl++ = tcl; + } + } while (cl < fs->n_fatent); /* Repeat until end of chain */ + } + *fp->cltbl = ulen; /* Number of items used */ + if (ulen <= tlen) { + *tbl = 0; /* Terminate table */ + } else { + res = FR_NOT_ENOUGH_CORE; /* Given table size is smaller than required */ + } + } else { /* Fast seek */ + if (ofs > fp->obj.objsize) ofs = fp->obj.objsize; /* Clip offset at the file size */ + fp->fptr = ofs; /* Set file pointer */ + if (ofs > 0) { + fp->clust = clmt_clust(fp, ofs - 1); + dsc = clst2sect(fs, fp->clust); + if (dsc == 0) ABORT(fs, FR_INT_ERR); + dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1); + if (fp->fptr % SS(fs) && dsc != fp->sect) { /* Refill sector cache if needed */ +#if !FF_FS_TINY +#if !FF_FS_READONLY + if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + if (disk_read(fs->pdrv, fp->buf, dsc, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Load current sector */ +#endif + fp->sect = dsc; + } + } + } + } else +#endif + + /* Normal Seek */ + { +#if FF_FS_EXFAT + if (fs->fs_type != FS_EXFAT && ofs >= 0x100000000) ofs = 0xFFFFFFFF; /* Clip at 4 GiB - 1 if at FATxx */ +#endif + if (ofs > fp->obj.objsize && (FF_FS_READONLY || !(fp->flag & FA_WRITE))) { /* In read-only mode, clip offset with the file size */ + ofs = fp->obj.objsize; + } + ifptr = fp->fptr; + fp->fptr = nsect = 0; + if (ofs > 0) { + bcs = (DWORD)fs->csize * SS(fs); /* Cluster size (byte) */ + if (ifptr > 0 && + (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ + fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1); /* start from the current cluster */ + ofs -= fp->fptr; + clst = fp->clust; + } else { /* When seek to back cluster, */ + clst = fp->obj.sclust; /* start from the first cluster */ +#if !FF_FS_READONLY + if (clst == 0) { /* If no cluster chain, create a new chain */ + clst = create_chain(&fp->obj, 0); + if (clst == 1) ABORT(fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + fp->obj.sclust = clst; + } +#endif + fp->clust = clst; + } + if (clst != 0) { + while (ofs > bcs) { /* Cluster following loop */ + ofs -= bcs; fp->fptr += bcs; +#if !FF_FS_READONLY + if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ + if (FF_FS_EXFAT && fp->fptr > fp->obj.objsize) { /* No FAT chain object needs correct objsize to generate FAT value */ + fp->obj.objsize = fp->fptr; + fp->flag |= FA_MODIFIED; + } + clst = create_chain(&fp->obj, clst); /* Follow chain with forceed stretch */ + if (clst == 0) { /* Clip file size in case of disk full */ + ofs = 0; break; + } + } else +#endif + { + clst = get_fat(&fp->obj, clst); /* Follow cluster chain if not in write mode */ + } + if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR); + fp->clust = clst; + } + fp->fptr += ofs; + if (ofs % SS(fs)) { + nsect = clst2sect(fs, clst); /* Current sector */ + if (nsect == 0) ABORT(fs, FR_INT_ERR); + nsect += (DWORD)(ofs / SS(fs)); + } + } + } + if (!FF_FS_READONLY && fp->fptr > fp->obj.objsize) { /* Set file change flag if the file size is extended */ + fp->obj.objsize = fp->fptr; + fp->flag |= FA_MODIFIED; + } + if (fp->fptr % SS(fs) && nsect != fp->sect) { /* Fill sector cache if needed */ +#if !FF_FS_TINY +#if !FF_FS_READONLY + if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + if (disk_read(fs->pdrv, fp->buf, nsect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Fill sector cache */ +#endif + fp->sect = nsect; + } + } + + LEAVE_FF(fs, res); +} + + + +#if FF_FS_MINIMIZE <= 1 +/*-----------------------------------------------------------------------*/ +/* Create a Directory Object */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_opendir ( + DIR* dp, /* Pointer to directory object to create */ + const TCHAR* path /* Pointer to the directory path */ +) +{ + FRESULT res; + FATFS *fs; + DEF_NAMBUF + + + if (!dp) return FR_INVALID_OBJECT; + + /* Get logical drive */ + res = mount_volume(&path, &fs, 0); + if (res == FR_OK) { + dp->obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(dp, path); /* Follow the path to the directory */ + if (res == FR_OK) { /* Follow completed */ + if (!(dp->fn[NSFLAG] & NS_NONAME)) { /* It is not the origin directory itself */ + if (dp->obj.attr & AM_DIR) { /* This object is a sub-directory */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + dp->obj.c_scl = dp->obj.sclust; /* Get containing directory inforamation */ + dp->obj.c_size = ((DWORD)dp->obj.objsize & 0xFFFFFF00) | dp->obj.stat; + dp->obj.c_ofs = dp->blk_ofs; + init_alloc_info(fs, &dp->obj); /* Get object allocation info */ + } else +#endif + { + dp->obj.sclust = ld_clust(fs, dp->dir); /* Get object allocation info */ + } + } else { /* This object is a file */ + res = FR_NO_PATH; + } + } + if (res == FR_OK) { + dp->obj.id = fs->id; + res = dir_sdi(dp, 0); /* Rewind directory */ +#if FF_FS_LOCK != 0 + if (res == FR_OK) { + if (dp->obj.sclust != 0) { + dp->obj.lockid = inc_lock(dp, 0); /* Lock the sub directory */ + if (!dp->obj.lockid) res = FR_TOO_MANY_OPEN_FILES; + } else { + dp->obj.lockid = 0; /* Root directory need not to be locked */ + } + } +#endif + } + } + FREE_NAMBUF(); + if (res == FR_NO_FILE) res = FR_NO_PATH; + } + if (res != FR_OK) dp->obj.fs = 0; /* Invalidate the directory object if function faild */ + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Close Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_closedir ( + DIR *dp /* Pointer to the directory object to be closed */ +) +{ + FRESULT res; + FATFS *fs; + + + res = validate(&dp->obj, &fs); /* Check validity of the file object */ + if (res == FR_OK) { +#if FF_FS_LOCK != 0 + if (dp->obj.lockid) res = dec_lock(dp->obj.lockid); /* Decrement sub-directory open counter */ + if (res == FR_OK) dp->obj.fs = 0; /* Invalidate directory object */ +#else + dp->obj.fs = 0; /* Invalidate directory object */ +#endif +#if FF_FS_REENTRANT + unlock_fs(fs, FR_OK); /* Unlock volume */ +#endif + } + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read Directory Entries in Sequence */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_readdir ( + DIR* dp, /* Pointer to the open directory object */ + FILINFO* fno /* Pointer to file information to return */ +) +{ + FRESULT res; + FATFS *fs; + DEF_NAMBUF + + + res = validate(&dp->obj, &fs); /* Check validity of the directory object */ + if (res == FR_OK) { + if (!fno) { + res = dir_sdi(dp, 0); /* Rewind the directory object */ + } else { + INIT_NAMBUF(fs); + res = DIR_READ_FILE(dp); /* Read an item */ + if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory */ + if (res == FR_OK) { /* A valid entry is found */ + get_fileinfo(dp, fno); /* Get the object information */ + res = dir_next(dp, 0); /* Increment index for next */ + if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory now */ + } + FREE_NAMBUF(); + } + } + LEAVE_FF(fs, res); +} + + + +#if FF_USE_FIND +/*-----------------------------------------------------------------------*/ +/* Find Next File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_findnext ( + DIR* dp, /* Pointer to the open directory object */ + FILINFO* fno /* Pointer to the file information structure */ +) +{ + FRESULT res; + + + for (;;) { + res = f_readdir(dp, fno); /* Get a directory item */ + if (res != FR_OK || !fno || !fno->fname[0]) break; /* Terminate if any error or end of directory */ + if (pattern_match(dp->pat, fno->fname, 0, FIND_RECURS)) break; /* Test for the file name */ +#if FF_USE_LFN && FF_USE_FIND == 2 + if (pattern_match(dp->pat, fno->altname, 0, FIND_RECURS)) break; /* Test for alternative name if exist */ +#endif + } + return res; +} + + + +/*-----------------------------------------------------------------------*/ +/* Find First File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_findfirst ( + DIR* dp, /* Pointer to the blank directory object */ + FILINFO* fno, /* Pointer to the file information structure */ + const TCHAR* path, /* Pointer to the directory to open */ + const TCHAR* pattern /* Pointer to the matching pattern */ +) +{ + FRESULT res; + + + dp->pat = pattern; /* Save pointer to pattern string */ + res = f_opendir(dp, path); /* Open the target directory */ + if (res == FR_OK) { + res = f_findnext(dp, fno); /* Find the first item */ + } + return res; +} + +#endif /* FF_USE_FIND */ + + + +#if FF_FS_MINIMIZE == 0 +/*-----------------------------------------------------------------------*/ +/* Get File Status */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_stat ( + const TCHAR* path, /* Pointer to the file path */ + FILINFO* fno /* Pointer to file information to return */ +) +{ + FRESULT res; + DIR dj; + DEF_NAMBUF + + + /* Get logical drive */ + res = mount_volume(&path, &dj.obj.fs, 0); + if (res == FR_OK) { + INIT_NAMBUF(dj.obj.fs); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) { /* Follow completed */ + if (dj.fn[NSFLAG] & NS_NONAME) { /* It is origin directory */ + res = FR_INVALID_NAME; + } else { /* Found an object */ + if (fno) get_fileinfo(&dj, fno); + } + } + FREE_NAMBUF(); + } + + LEAVE_FF(dj.obj.fs, res); +} + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Get Number of Free Clusters */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_getfree ( + const TCHAR* path, /* Logical drive number */ + DWORD* nclst, /* Pointer to a variable to return number of free clusters */ + FATFS** fatfs /* Pointer to return pointer to corresponding filesystem object */ +) +{ + FRESULT res; + FATFS *fs; + DWORD nfree, clst, stat; + LBA_t sect; + UINT i; + FFOBJID obj; + + + /* Get logical drive */ + res = mount_volume(&path, &fs, 0); + if (res == FR_OK) { + *fatfs = fs; /* Return ptr to the fs object */ + /* If free_clst is valid, return it without full FAT scan */ + if (fs->free_clst <= fs->n_fatent - 2) { + *nclst = fs->free_clst; + } else { + /* Scan FAT to obtain number of free clusters */ + nfree = 0; + if (fs->fs_type == FS_FAT12) { /* FAT12: Scan bit field FAT entries */ + clst = 2; obj.fs = fs; + do { + stat = get_fat(&obj, clst); + if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } + if (stat == 1) { res = FR_INT_ERR; break; } + if (stat == 0) nfree++; + } while (++clst < fs->n_fatent); + } else { +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* exFAT: Scan allocation bitmap */ + BYTE bm; + UINT b; + + clst = fs->n_fatent - 2; /* Number of clusters */ + sect = fs->bitbase; /* Bitmap sector */ + i = 0; /* Offset in the sector */ + do { /* Counts numbuer of bits with zero in the bitmap */ + if (i == 0) { + res = move_window(fs, sect++); + if (res != FR_OK) break; + } + for (b = 8, bm = fs->win[i]; b && clst; b--, clst--) { + if (!(bm & 1)) nfree++; + bm >>= 1; + } + i = (i + 1) % SS(fs); + } while (clst); + } else +#endif + { /* FAT16/32: Scan WORD/DWORD FAT entries */ + clst = fs->n_fatent; /* Number of entries */ + sect = fs->fatbase; /* Top of the FAT */ + i = 0; /* Offset in the sector */ + do { /* Counts numbuer of entries with zero in the FAT */ + if (i == 0) { + res = move_window(fs, sect++); + if (res != FR_OK) break; + } + if (fs->fs_type == FS_FAT16) { + if (ld_word(fs->win + i) == 0) nfree++; + i += 2; + } else { + if ((ld_dword(fs->win + i) & 0x0FFFFFFF) == 0) nfree++; + i += 4; + } + i %= SS(fs); + } while (--clst); + } + } + if (res == FR_OK) { /* Update parameters if succeeded */ + *nclst = nfree; /* Return the free clusters */ + fs->free_clst = nfree; /* Now free_clst is valid */ + fs->fsi_flag |= 1; /* FAT32: FSInfo is to be updated */ + } + } + } + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Truncate File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_truncate ( + FIL* fp /* Pointer to the file object */ +) +{ + FRESULT res; + FATFS *fs; + DWORD ncl; + + + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); + if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + + if (fp->fptr < fp->obj.objsize) { /* Process when fptr is not on the eof */ + if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ + res = remove_chain(&fp->obj, fp->obj.sclust, 0); + fp->obj.sclust = 0; + } else { /* When truncate a part of the file, remove remaining clusters */ + ncl = get_fat(&fp->obj, fp->clust); + res = FR_OK; + if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (ncl == 1) res = FR_INT_ERR; + if (res == FR_OK && ncl < fs->n_fatent) { + res = remove_chain(&fp->obj, ncl, fp->clust); + } + } + fp->obj.objsize = fp->fptr; /* Set file size to current read/write point */ + fp->flag |= FA_MODIFIED; +#if !FF_FS_TINY + if (res == FR_OK && (fp->flag & FA_DIRTY)) { + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) { + res = FR_DISK_ERR; + } else { + fp->flag &= (BYTE)~FA_DIRTY; + } + } +#endif + if (res != FR_OK) ABORT(fs, res); + } + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Delete a File/Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_unlink ( + const TCHAR* path /* Pointer to the file or directory path */ +) +{ + FRESULT res; + DIR dj, sdj; + DWORD dclst = 0; + FATFS *fs; +#if FF_FS_EXFAT + FFOBJID obj; +#endif + DEF_NAMBUF + + + /* Get logical drive */ + res = mount_volume(&path, &fs, FA_WRITE); + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the file path */ + if (FF_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) { + res = FR_INVALID_NAME; /* Cannot remove dot entry */ + } +#if FF_FS_LOCK != 0 + if (res == FR_OK) res = chk_lock(&dj, 2); /* Check if it is an open object */ +#endif + if (res == FR_OK) { /* The object is accessible */ + if (dj.fn[NSFLAG] & NS_NONAME) { + res = FR_INVALID_NAME; /* Cannot remove the origin directory */ + } else { + if (dj.obj.attr & AM_RDO) { + res = FR_DENIED; /* Cannot remove R/O object */ + } + } + if (res == FR_OK) { +#if FF_FS_EXFAT + obj.fs = fs; + if (fs->fs_type == FS_EXFAT) { + init_alloc_info(fs, &obj); + dclst = obj.sclust; + } else +#endif + { + dclst = ld_clust(fs, dj.dir); + } + if (dj.obj.attr & AM_DIR) { /* Is it a sub-directory? */ +#if FF_FS_RPATH != 0 + if (dclst == fs->cdir) { /* Is it the current directory? */ + res = FR_DENIED; + } else +#endif + { + sdj.obj.fs = fs; /* Open the sub-directory */ + sdj.obj.sclust = dclst; +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + sdj.obj.objsize = obj.objsize; + sdj.obj.stat = obj.stat; + } +#endif + res = dir_sdi(&sdj, 0); + if (res == FR_OK) { + res = DIR_READ_FILE(&sdj); /* Test if the directory is empty */ + if (res == FR_OK) res = FR_DENIED; /* Not empty? */ + if (res == FR_NO_FILE) res = FR_OK; /* Empty? */ + } + } + } + } + if (res == FR_OK) { + res = dir_remove(&dj); /* Remove the directory entry */ + if (res == FR_OK && dclst != 0) { /* Remove the cluster chain if exist */ +#if FF_FS_EXFAT + res = remove_chain(&obj, dclst, 0); +#else + res = remove_chain(&dj.obj, dclst, 0); +#endif + } + if (res == FR_OK) res = sync_fs(fs); + } + } + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Create a Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mkdir ( + const TCHAR* path /* Pointer to the directory path */ +) +{ + FRESULT res; + DIR dj; + FFOBJID sobj; + FATFS *fs; + DWORD dcl, pcl, tm; + DEF_NAMBUF + + + res = mount_volume(&path, &fs, FA_WRITE); /* Get logical drive */ + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) res = FR_EXIST; /* Name collision? */ + if (FF_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) { /* Invalid name? */ + res = FR_INVALID_NAME; + } + if (res == FR_NO_FILE) { /* It is clear to create a new directory */ + sobj.fs = fs; /* New object id to create a new chain */ + dcl = create_chain(&sobj, 0); /* Allocate a cluster for the new directory */ + res = FR_OK; + if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster? */ + if (dcl == 1) res = FR_INT_ERR; /* Any insanity? */ + if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; /* Disk error? */ + tm = GET_FATTIME(); + if (res == FR_OK) { + res = dir_clear(fs, dcl); /* Clean up the new table */ + if (res == FR_OK) { + if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) { /* Create dot entries (FAT only) */ + memset(fs->win + DIR_Name, ' ', 11); /* Create "." entry */ + fs->win[DIR_Name] = '.'; + fs->win[DIR_Attr] = AM_DIR; + st_dword(fs->win + DIR_ModTime, tm); + st_clust(fs, fs->win, dcl); + memcpy(fs->win + SZDIRE, fs->win, SZDIRE); /* Create ".." entry */ + fs->win[SZDIRE + 1] = '.'; pcl = dj.obj.sclust; + st_clust(fs, fs->win + SZDIRE, pcl); + fs->wflag = 1; + } + res = dir_register(&dj); /* Register the object to the parent directoy */ + } + } + if (res == FR_OK) { +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* Initialize directory entry block */ + st_dword(fs->dirbuf + XDIR_ModTime, tm); /* Created time */ + st_dword(fs->dirbuf + XDIR_FstClus, dcl); /* Table start cluster */ + st_dword(fs->dirbuf + XDIR_FileSize, (DWORD)fs->csize * SS(fs)); /* Directory size needs to be valid */ + st_dword(fs->dirbuf + XDIR_ValidFileSize, (DWORD)fs->csize * SS(fs)); + fs->dirbuf[XDIR_GenFlags] = 3; /* Initialize the object flag */ + fs->dirbuf[XDIR_Attr] = AM_DIR; /* Attribute */ + res = store_xdir(&dj); + } else +#endif + { + st_dword(dj.dir + DIR_ModTime, tm); /* Created time */ + st_clust(fs, dj.dir, dcl); /* Table start cluster */ + dj.dir[DIR_Attr] = AM_DIR; /* Attribute */ + fs->wflag = 1; + } + if (res == FR_OK) { + res = sync_fs(fs); + } + } else { + remove_chain(&sobj, dcl, 0); /* Could not register, remove the allocated cluster */ + } + } + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Rename a File/Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_rename ( + const TCHAR* path_old, /* Pointer to the object name to be renamed */ + const TCHAR* path_new /* Pointer to the new name */ +) +{ + FRESULT res; + DIR djo, djn; + FATFS *fs; + BYTE buf[FF_FS_EXFAT ? SZDIRE * 2 : SZDIRE], *dir; + LBA_t sect; + DEF_NAMBUF + + + get_ldnumber(&path_new); /* Snip the drive number of new name off */ + res = mount_volume(&path_old, &fs, FA_WRITE); /* Get logical drive of the old object */ + if (res == FR_OK) { + djo.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&djo, path_old); /* Check old object */ + if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check validity of name */ +#if FF_FS_LOCK != 0 + if (res == FR_OK) { + res = chk_lock(&djo, 2); + } +#endif + if (res == FR_OK) { /* Object to be renamed is found */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* At exFAT volume */ + BYTE nf, nn; + WORD nh; + + memcpy(buf, fs->dirbuf, SZDIRE * 2); /* Save 85+C0 entry of old object */ + memcpy(&djn, &djo, sizeof djo); + res = follow_path(&djn, path_new); /* Make sure if new object name is not in use */ + if (res == FR_OK) { /* Is new name already in use by any other object? */ + res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST; + } + if (res == FR_NO_FILE) { /* It is a valid path and no name collision */ + res = dir_register(&djn); /* Register the new entry */ + if (res == FR_OK) { + nf = fs->dirbuf[XDIR_NumSec]; nn = fs->dirbuf[XDIR_NumName]; + nh = ld_word(fs->dirbuf + XDIR_NameHash); + memcpy(fs->dirbuf, buf, SZDIRE * 2); /* Restore 85+C0 entry */ + fs->dirbuf[XDIR_NumSec] = nf; fs->dirbuf[XDIR_NumName] = nn; + st_word(fs->dirbuf + XDIR_NameHash, nh); + if (!(fs->dirbuf[XDIR_Attr] & AM_DIR)) fs->dirbuf[XDIR_Attr] |= AM_ARC; /* Set archive attribute if it is a file */ +/* Start of critical section where an interruption can cause a cross-link */ + res = store_xdir(&djn); + } + } + } else +#endif + { /* At FAT/FAT32 volume */ + memcpy(buf, djo.dir, SZDIRE); /* Save directory entry of the object */ + memcpy(&djn, &djo, sizeof (DIR)); /* Duplicate the directory object */ + res = follow_path(&djn, path_new); /* Make sure if new object name is not in use */ + if (res == FR_OK) { /* Is new name already in use by any other object? */ + res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST; + } + if (res == FR_NO_FILE) { /* It is a valid path and no name collision */ + res = dir_register(&djn); /* Register the new entry */ + if (res == FR_OK) { + dir = djn.dir; /* Copy directory entry of the object except name */ + memcpy(dir + 13, buf + 13, SZDIRE - 13); + dir[DIR_Attr] = buf[DIR_Attr]; + if (!(dir[DIR_Attr] & AM_DIR)) dir[DIR_Attr] |= AM_ARC; /* Set archive attribute if it is a file */ + fs->wflag = 1; + if ((dir[DIR_Attr] & AM_DIR) && djo.obj.sclust != djn.obj.sclust) { /* Update .. entry in the sub-directory if needed */ + sect = clst2sect(fs, ld_clust(fs, dir)); + if (sect == 0) { + res = FR_INT_ERR; + } else { +/* Start of critical section where an interruption can cause a cross-link */ + res = move_window(fs, sect); + dir = fs->win + SZDIRE * 1; /* Ptr to .. entry */ + if (res == FR_OK && dir[1] == '.') { + st_clust(fs, dir, djn.obj.sclust); + fs->wflag = 1; + } + } + } + } + } + } + if (res == FR_OK) { + res = dir_remove(&djo); /* Remove old entry */ + if (res == FR_OK) { + res = sync_fs(fs); + } + } +/* End of the critical section */ + } + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + +#endif /* !FF_FS_READONLY */ +#endif /* FF_FS_MINIMIZE == 0 */ +#endif /* FF_FS_MINIMIZE <= 1 */ +#endif /* FF_FS_MINIMIZE <= 2 */ + + + +#if FF_USE_CHMOD && !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Change Attribute */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_chmod ( + const TCHAR* path, /* Pointer to the file path */ + BYTE attr, /* Attribute bits */ + BYTE mask /* Attribute mask to change */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; + DEF_NAMBUF + + + res = mount_volume(&path, &fs, FA_WRITE); /* Get logical drive */ + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check object validity */ + if (res == FR_OK) { + mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + fs->dirbuf[XDIR_Attr] = (attr & mask) | (fs->dirbuf[XDIR_Attr] & (BYTE)~mask); /* Apply attribute change */ + res = store_xdir(&dj); + } else +#endif + { + dj.dir[DIR_Attr] = (attr & mask) | (dj.dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ + fs->wflag = 1; + } + if (res == FR_OK) { + res = sync_fs(fs); + } + } + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Timestamp */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_utime ( + const TCHAR* path, /* Pointer to the file/directory name */ + const FILINFO* fno /* Pointer to the timestamp to be set */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; + DEF_NAMBUF + + + res = mount_volume(&path, &fs, FA_WRITE); /* Get logical drive */ + if (res == FR_OK) { + dj.obj.fs = fs; + INIT_NAMBUF(fs); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check object validity */ + if (res == FR_OK) { +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + st_dword(fs->dirbuf + XDIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime); + res = store_xdir(&dj); + } else +#endif + { + st_dword(dj.dir + DIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime); + fs->wflag = 1; + } + if (res == FR_OK) { + res = sync_fs(fs); + } + } + FREE_NAMBUF(); + } + + LEAVE_FF(fs, res); +} + +#endif /* FF_USE_CHMOD && !FF_FS_READONLY */ + + + +#if FF_USE_LABEL +/*-----------------------------------------------------------------------*/ +/* Get Volume Label */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_getlabel ( + const TCHAR* path, /* Logical drive number */ + TCHAR* label, /* Buffer to store the volume label */ + DWORD* vsn /* Variable to store the volume serial number */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; + UINT si, di; + WCHAR wc; + + /* Get logical drive */ + res = mount_volume(&path, &fs, 0); + + /* Get volume label */ + if (res == FR_OK && label) { + dj.obj.fs = fs; dj.obj.sclust = 0; /* Open root directory */ + res = dir_sdi(&dj, 0); + if (res == FR_OK) { + res = DIR_READ_LABEL(&dj); /* Find a volume label entry */ + if (res == FR_OK) { +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + WCHAR hs; + UINT nw; + + for (si = di = hs = 0; si < dj.dir[XDIR_NumLabel]; si++) { /* Extract volume label from 83 entry */ + wc = ld_word(dj.dir + XDIR_Label + si * 2); + if (hs == 0 && IsSurrogate(wc)) { /* Is the code a surrogate? */ + hs = wc; continue; + } + nw = put_utf((DWORD)hs << 16 | wc, &label[di], 4); /* Store it in API encoding */ + if (nw == 0) { di = 0; break; } /* Encode error? */ + di += nw; + hs = 0; + } + if (hs != 0) di = 0; /* Broken surrogate pair? */ + label[di] = 0; + } else +#endif + { + si = di = 0; /* Extract volume label from AM_VOL entry */ + while (si < 11) { + wc = dj.dir[si++]; +#if FF_USE_LFN && FF_LFN_UNICODE >= 1 /* Unicode output */ + if (dbc_1st((BYTE)wc) && si < 11) wc = wc << 8 | dj.dir[si++]; /* Is it a DBC? */ + wc = ff_oem2uni(wc, CODEPAGE); /* Convert it into Unicode */ + if (wc == 0) { di = 0; break; } /* Invalid char in current code page? */ + di += put_utf(wc, &label[di], 4); /* Store it in Unicode */ +#else /* ANSI/OEM output */ + label[di++] = (TCHAR)wc; +#endif + } + do { /* Truncate trailing spaces */ + label[di] = 0; + if (di == 0) break; + } while (label[--di] == ' '); + } + } + } + if (res == FR_NO_FILE) { /* No label entry and return nul string */ + label[0] = 0; + res = FR_OK; + } + } + + /* Get volume serial number */ + if (res == FR_OK && vsn) { + res = move_window(fs, fs->volbase); + if (res == FR_OK) { + switch (fs->fs_type) { + case FS_EXFAT: + di = BPB_VolIDEx; + break; + + case FS_FAT32: + di = BS_VolID32; + break; + + default: + di = BS_VolID; + } + *vsn = ld_dword(fs->win + di); + } + } + + LEAVE_FF(fs, res); +} + + + +#if !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Set Volume Label */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_setlabel ( + const TCHAR* label /* Volume label to set with heading logical drive number */ +) +{ + FRESULT res; + DIR dj; + FATFS *fs; + BYTE dirvn[22]; + UINT di; + WCHAR wc; + static const char badchr[18] = "+.,;=[]" "/*:<>|\\\"\?\x7F"; /* [0..16] for FAT, [7..16] for exFAT */ +#if FF_USE_LFN + DWORD dc; +#endif + + /* Get logical drive */ + res = mount_volume(&label, &fs, FA_WRITE); + if (res != FR_OK) LEAVE_FF(fs, res); + +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ + memset(dirvn, 0, 22); + di = 0; + while ((UINT)*label >= ' ') { /* Create volume label */ + dc = tchar2uni(&label); /* Get a Unicode character */ + if (dc >= 0x10000) { + if (dc == 0xFFFFFFFF || di >= 10) { /* Wrong surrogate or buffer overflow */ + dc = 0; + } else { + st_word(dirvn + di * 2, (WCHAR)(dc >> 16)); di++; + } + } + if (dc == 0 || strchr(&badchr[7], (int)dc) || di >= 11) { /* Check validity of the volume label */ + LEAVE_FF(fs, FR_INVALID_NAME); + } + st_word(dirvn + di * 2, (WCHAR)dc); di++; + } + } else +#endif + { /* On the FAT/FAT32 volume */ + memset(dirvn, ' ', 11); + di = 0; + while ((UINT)*label >= ' ') { /* Create volume label */ +#if FF_USE_LFN + dc = tchar2uni(&label); + wc = (dc < 0x10000) ? ff_uni2oem(ff_wtoupper(dc), CODEPAGE) : 0; +#else /* ANSI/OEM input */ + wc = (BYTE)*label++; + if (dbc_1st((BYTE)wc)) wc = dbc_2nd((BYTE)*label) ? wc << 8 | (BYTE)*label++ : 0; + if (IsLower(wc)) wc -= 0x20; /* To upper ASCII characters */ +#if FF_CODE_PAGE == 0 + if (ExCvt && wc >= 0x80) wc = ExCvt[wc - 0x80]; /* To upper extended characters (SBCS cfg) */ +#elif FF_CODE_PAGE < 900 + if (wc >= 0x80) wc = ExCvt[wc - 0x80]; /* To upper extended characters (SBCS cfg) */ +#endif +#endif + if (wc == 0 || strchr(&badchr[0], (int)wc) || di >= (UINT)((wc >= 0x100) ? 10 : 11)) { /* Reject invalid characters for volume label */ + LEAVE_FF(fs, FR_INVALID_NAME); + } + if (wc >= 0x100) dirvn[di++] = (BYTE)(wc >> 8); + dirvn[di++] = (BYTE)wc; + } + if (dirvn[0] == DDEM) LEAVE_FF(fs, FR_INVALID_NAME); /* Reject illegal name (heading DDEM) */ + while (di && dirvn[di - 1] == ' ') di--; /* Snip trailing spaces */ + } + + /* Set volume label */ + dj.obj.fs = fs; dj.obj.sclust = 0; /* Open root directory */ + res = dir_sdi(&dj, 0); + if (res == FR_OK) { + res = DIR_READ_LABEL(&dj); /* Get volume label entry */ + if (res == FR_OK) { + if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) { + dj.dir[XDIR_NumLabel] = (BYTE)di; /* Change the volume label */ + memcpy(dj.dir + XDIR_Label, dirvn, 22); + } else { + if (di != 0) { + memcpy(dj.dir, dirvn, 11); /* Change the volume label */ + } else { + dj.dir[DIR_Name] = DDEM; /* Remove the volume label */ + } + } + fs->wflag = 1; + res = sync_fs(fs); + } else { /* No volume label entry or an error */ + if (res == FR_NO_FILE) { + res = FR_OK; + if (di != 0) { /* Create a volume label entry */ + res = dir_alloc(&dj, 1); /* Allocate an entry */ + if (res == FR_OK) { + memset(dj.dir, 0, SZDIRE); /* Clean the entry */ + if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) { + dj.dir[XDIR_Type] = ET_VLABEL; /* Create volume label entry */ + dj.dir[XDIR_NumLabel] = (BYTE)di; + memcpy(dj.dir + XDIR_Label, dirvn, 22); + } else { + dj.dir[DIR_Attr] = AM_VOL; /* Create volume label entry */ + memcpy(dj.dir, dirvn, 11); + } + fs->wflag = 1; + res = sync_fs(fs); + } + } + } + } + } + + LEAVE_FF(fs, res); +} + +#endif /* !FF_FS_READONLY */ +#endif /* FF_USE_LABEL */ + + + +#if FF_USE_EXPAND && !FF_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Allocate a Contiguous Blocks to the File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_expand ( + FIL* fp, /* Pointer to the file object */ + FSIZE_t fsz, /* File size to be expanded to */ + BYTE opt /* Operation mode 0:Find and prepare or 1:Find and allocate */ +) +{ + FRESULT res; + FATFS *fs; + DWORD n, clst, stcl, scl, ncl, tcl, lclst; + + + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); + if (fsz == 0 || fp->obj.objsize != 0 || !(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); +#if FF_FS_EXFAT + if (fs->fs_type != FS_EXFAT && fsz >= 0x100000000) LEAVE_FF(fs, FR_DENIED); /* Check if in size limit */ +#endif + n = (DWORD)fs->csize * SS(fs); /* Cluster size */ + tcl = (DWORD)(fsz / n) + ((fsz & (n - 1)) ? 1 : 0); /* Number of clusters required */ + stcl = fs->last_clst; lclst = 0; + if (stcl < 2 || stcl >= fs->n_fatent) stcl = 2; + +#if FF_FS_EXFAT + if (fs->fs_type == FS_EXFAT) { + scl = find_bitmap(fs, stcl, tcl); /* Find a contiguous cluster block */ + if (scl == 0) res = FR_DENIED; /* No contiguous cluster block was found */ + if (scl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (res == FR_OK) { /* A contiguous free area is found */ + if (opt) { /* Allocate it now */ + res = change_bitmap(fs, scl, tcl, 1); /* Mark the cluster block 'in use' */ + lclst = scl + tcl - 1; + } else { /* Set it as suggested point for next allocation */ + lclst = scl - 1; + } + } + } else +#endif + { + scl = clst = stcl; ncl = 0; + for (;;) { /* Find a contiguous cluster block */ + n = get_fat(&fp->obj, clst); + if (++clst >= fs->n_fatent) clst = 2; + if (n == 1) { res = FR_INT_ERR; break; } + if (n == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } + if (n == 0) { /* Is it a free cluster? */ + if (++ncl == tcl) break; /* Break if a contiguous cluster block is found */ + } else { + scl = clst; ncl = 0; /* Not a free cluster */ + } + if (clst == stcl) { res = FR_DENIED; break; } /* No contiguous cluster? */ + } + if (res == FR_OK) { /* A contiguous free area is found */ + if (opt) { /* Allocate it now */ + for (clst = scl, n = tcl; n; clst++, n--) { /* Create a cluster chain on the FAT */ + res = put_fat(fs, clst, (n == 1) ? 0xFFFFFFFF : clst + 1); + if (res != FR_OK) break; + lclst = clst; + } + } else { /* Set it as suggested point for next allocation */ + lclst = scl - 1; + } + } + } + + if (res == FR_OK) { + fs->last_clst = lclst; /* Set suggested start cluster to start next */ + if (opt) { /* Is it allocated now? */ + fp->obj.sclust = scl; /* Update object allocation information */ + fp->obj.objsize = fsz; + if (FF_FS_EXFAT) fp->obj.stat = 2; /* Set status 'contiguous chain' */ + fp->flag |= FA_MODIFIED; + if (fs->free_clst <= fs->n_fatent - 2) { /* Update FSINFO */ + fs->free_clst -= tcl; + fs->fsi_flag |= 1; + } + } + } + + LEAVE_FF(fs, res); +} + +#endif /* FF_USE_EXPAND && !FF_FS_READONLY */ + + + +#if FF_USE_FORWARD +/*-----------------------------------------------------------------------*/ +/* Forward Data to the Stream Directly */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_forward ( + FIL* fp, /* Pointer to the file object */ + UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */ + UINT btf, /* Number of bytes to forward */ + UINT* bf /* Pointer to number of bytes forwarded */ +) +{ + FRESULT res; + FATFS *fs; + DWORD clst; + LBA_t sect; + FSIZE_t remain; + UINT rcnt, csect; + BYTE *dbuf; + + + *bf = 0; /* Clear transfer byte counter */ + res = validate(&fp->obj, &fs); /* Check validity of the file object */ + if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); + if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + + remain = fp->obj.objsize - fp->fptr; + if (btf > remain) btf = (UINT)remain; /* Truncate btf by remaining bytes */ + + for ( ; btf > 0 && (*func)(0, 0); fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) { /* Repeat until all data transferred or stream goes busy */ + csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */ + if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + if (csect == 0) { /* On the cluster boundary? */ + clst = (fp->fptr == 0) ? /* On the top of the file? */ + fp->obj.sclust : get_fat(&fp->obj, fp->clust); + if (clst <= 1) ABORT(fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + } + } + sect = clst2sect(fs, fp->clust); /* Get current data sector */ + if (sect == 0) ABORT(fs, FR_INT_ERR); + sect += csect; +#if FF_FS_TINY + if (move_window(fs, sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window to the file data */ + dbuf = fs->win; +#else + if (fp->sect != sect) { /* Fill sector cache with file data */ +#if !FF_FS_READONLY + if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + fp->flag &= (BYTE)~FA_DIRTY; + } +#endif + if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + } + dbuf = fp->buf; +#endif + fp->sect = sect; + rcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes remains in the sector */ + if (rcnt > btf) rcnt = btf; /* Clip it by btr if needed */ + rcnt = (*func)(dbuf + ((UINT)fp->fptr % SS(fs)), rcnt); /* Forward the file data */ + if (rcnt == 0) ABORT(fs, FR_INT_ERR); + } + + LEAVE_FF(fs, FR_OK); +} +#endif /* FF_USE_FORWARD */ + + + +#if !FF_FS_READONLY && FF_USE_MKFS +/*-----------------------------------------------------------------------*/ +/* Create FAT/exFAT volume (with sub-functions) */ +/*-----------------------------------------------------------------------*/ + +#define N_SEC_TRACK 63 /* Sectors per track for determination of drive CHS */ +#define GPT_ALIGN 0x100000 /* Alignment of partitions in GPT [byte] (>=128KB) */ +#define GPT_ITEMS 128 /* Number of GPT table size (>=128, sector aligned) */ + + +/* Create partitions on the physical drive in format of MBR or GPT */ + +static FRESULT create_partition ( + BYTE drv, /* Physical drive number */ + const LBA_t plst[], /* Partition list */ + BYTE sys, /* System ID (for only MBR, temp setting) */ + BYTE* buf /* Working buffer for a sector */ +) +{ + UINT i, cy; + LBA_t sz_drv; + DWORD sz_drv32, nxt_alloc32, sz_part32; + BYTE *pte; + BYTE hd, n_hd, sc, n_sc; + + /* Get physical drive size */ + if (disk_ioctl(drv, GET_SECTOR_COUNT, &sz_drv) != RES_OK) return FR_DISK_ERR; + +#if FF_LBA64 + if (sz_drv >= FF_MIN_GPT) { /* Create partitions in GPT format */ + WORD ss; + UINT sz_ptbl, pi, si, ofs; + DWORD bcc, rnd, align; + QWORD nxt_alloc, sz_part, sz_pool, top_bpt; + static const BYTE gpt_mbr[16] = {0x00, 0x00, 0x02, 0x00, 0xEE, 0xFE, 0xFF, 0x00, 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF}; + +#if FF_MAX_SS != FF_MIN_SS + if (disk_ioctl(drv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR; /* Get sector size */ + if (ss > FF_MAX_SS || ss < FF_MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR; +#else + ss = FF_MAX_SS; +#endif + rnd = (DWORD)sz_drv + GET_FATTIME(); /* Random seed */ + align = GPT_ALIGN / ss; /* Partition alignment for GPT [sector] */ + sz_ptbl = GPT_ITEMS * SZ_GPTE / ss; /* Size of partition table [sector] */ + top_bpt = sz_drv - sz_ptbl - 1; /* Backup partiiton table start sector */ + nxt_alloc = 2 + sz_ptbl; /* First allocatable sector */ + sz_pool = top_bpt - nxt_alloc; /* Size of allocatable area */ + bcc = 0xFFFFFFFF; sz_part = 1; + pi = si = 0; /* partition table index, size table index */ + do { + if (pi * SZ_GPTE % ss == 0) memset(buf, 0, ss); /* Clean the buffer if needed */ + if (sz_part != 0) { /* Is the size table not termintated? */ + nxt_alloc = (nxt_alloc + align - 1) & ((QWORD)0 - align); /* Align partition start */ + sz_part = plst[si++]; /* Get a partition size */ + if (sz_part <= 100) { /* Is the size in percentage? */ + sz_part = sz_pool * sz_part / 100; + sz_part = (sz_part + align - 1) & ((QWORD)0 - align); /* Align partition end (only if in percentage) */ + } + if (nxt_alloc + sz_part > top_bpt) { /* Clip the size at end of the pool */ + sz_part = (nxt_alloc < top_bpt) ? top_bpt - nxt_alloc : 0; + } + } + if (sz_part != 0) { /* Add a partition? */ + ofs = pi * SZ_GPTE % ss; + memcpy(buf + ofs + GPTE_PtGuid, GUID_MS_Basic, 16); /* Set partition GUID (Microsoft Basic Data) */ + rnd = make_rand(rnd, buf + ofs + GPTE_UpGuid, 16); /* Set unique partition GUID */ + st_qword(buf + ofs + GPTE_FstLba, nxt_alloc); /* Set partition start sector */ + st_qword(buf + ofs + GPTE_LstLba, nxt_alloc + sz_part - 1); /* Set partition end sector */ + nxt_alloc += sz_part; /* Next allocatable sector */ + } + if ((pi + 1) * SZ_GPTE % ss == 0) { /* Write the buffer if it is filled up */ + for (i = 0; i < ss; bcc = crc32(bcc, buf[i++])) ; /* Calculate table check sum */ + if (disk_write(drv, buf, 2 + pi * SZ_GPTE / ss, 1) != RES_OK) return FR_DISK_ERR; /* Write to primary table */ + if (disk_write(drv, buf, top_bpt + pi * SZ_GPTE / ss, 1) != RES_OK) return FR_DISK_ERR; /* Write to secondary table */ + } + } while (++pi < GPT_ITEMS); + + /* Create primary GPT header */ + memset(buf, 0, ss); + memcpy(buf + GPTH_Sign, "EFI PART" "\0\0\1\0" "\x5C\0\0", 16); /* Signature, version (1.0) and size (92) */ + st_dword(buf + GPTH_PtBcc, ~bcc); /* Table check sum */ + st_qword(buf + GPTH_CurLba, 1); /* LBA of this header */ + st_qword(buf + GPTH_BakLba, sz_drv - 1); /* LBA of secondary header */ + st_qword(buf + GPTH_FstLba, 2 + sz_ptbl); /* LBA of first allocatable sector */ + st_qword(buf + GPTH_LstLba, top_bpt - 1); /* LBA of last allocatable sector */ + st_dword(buf + GPTH_PteSize, SZ_GPTE); /* Size of a table entry */ + st_dword(buf + GPTH_PtNum, GPT_ITEMS); /* Number of table entries */ + st_dword(buf + GPTH_PtOfs, 2); /* LBA of this table */ + rnd = make_rand(rnd, buf + GPTH_DskGuid, 16); /* Disk GUID */ + for (i = 0, bcc= 0xFFFFFFFF; i < 92; bcc = crc32(bcc, buf[i++])) ; /* Calculate header check sum */ + st_dword(buf + GPTH_Bcc, ~bcc); /* Header check sum */ + if (disk_write(drv, buf, 1, 1) != RES_OK) return FR_DISK_ERR; + + /* Create secondary GPT header */ + st_qword(buf + GPTH_CurLba, sz_drv - 1); /* LBA of this header */ + st_qword(buf + GPTH_BakLba, 1); /* LBA of primary header */ + st_qword(buf + GPTH_PtOfs, top_bpt); /* LBA of this table */ + st_dword(buf + GPTH_Bcc, 0); + for (i = 0, bcc= 0xFFFFFFFF; i < 92; bcc = crc32(bcc, buf[i++])) ; /* Calculate header check sum */ + st_dword(buf + GPTH_Bcc, ~bcc); /* Header check sum */ + if (disk_write(drv, buf, sz_drv - 1, 1) != RES_OK) return FR_DISK_ERR; + + /* Create protective MBR */ + memset(buf, 0, ss); + memcpy(buf + MBR_Table, gpt_mbr, 16); /* Create a GPT partition */ + st_word(buf + BS_55AA, 0xAA55); + if (disk_write(drv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; + + } else +#endif + { /* Create partitions in MBR format */ + sz_drv32 = (DWORD)sz_drv; + n_sc = N_SEC_TRACK; /* Determine drive CHS without any consideration of the drive geometry */ + for (n_hd = 8; n_hd != 0 && sz_drv32 / n_hd / n_sc > 1024; n_hd *= 2) ; + if (n_hd == 0) n_hd = 255; /* Number of heads needs to be <256 */ + + memset(buf, 0, FF_MAX_SS); /* Clear MBR */ + pte = buf + MBR_Table; /* Partition table in the MBR */ + for (i = 0, nxt_alloc32 = n_sc; i < 4 && nxt_alloc32 != 0 && nxt_alloc32 < sz_drv32; i++, nxt_alloc32 += sz_part32) { + sz_part32 = (DWORD)plst[i]; /* Get partition size */ + if (sz_part32 <= 100) sz_part32 = (sz_part32 == 100) ? sz_drv32 : sz_drv32 / 100 * sz_part32; /* Size in percentage? */ + if (nxt_alloc32 + sz_part32 > sz_drv32 || nxt_alloc32 + sz_part32 < nxt_alloc32) sz_part32 = sz_drv32 - nxt_alloc32; /* Clip at drive size */ + if (sz_part32 == 0) break; /* End of table or no sector to allocate? */ + + st_dword(pte + PTE_StLba, nxt_alloc32); /* Start LBA */ + st_dword(pte + PTE_SizLba, sz_part32); /* Number of sectors */ + pte[PTE_System] = sys; /* System type */ + + cy = (UINT)(nxt_alloc32 / n_sc / n_hd); /* Start cylinder */ + hd = (BYTE)(nxt_alloc32 / n_sc % n_hd); /* Start head */ + sc = (BYTE)(nxt_alloc32 % n_sc + 1); /* Start sector */ + pte[PTE_StHead] = hd; + pte[PTE_StSec] = (BYTE)((cy >> 2 & 0xC0) | sc); + pte[PTE_StCyl] = (BYTE)cy; + + cy = (UINT)((nxt_alloc32 + sz_part32 - 1) / n_sc / n_hd); /* End cylinder */ + hd = (BYTE)((nxt_alloc32 + sz_part32 - 1) / n_sc % n_hd); /* End head */ + sc = (BYTE)((nxt_alloc32 + sz_part32 - 1) % n_sc + 1); /* End sector */ + pte[PTE_EdHead] = hd; + pte[PTE_EdSec] = (BYTE)((cy >> 2 & 0xC0) | sc); + pte[PTE_EdCyl] = (BYTE)cy; + + pte += SZ_PTE; /* Next entry */ + } + + st_word(buf + BS_55AA, 0xAA55); /* MBR signature */ + if (disk_write(drv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; /* Write it to the MBR */ + } + + return FR_OK; +} + + + +FRESULT f_mkfs ( + const TCHAR* path, /* Logical drive number */ + const MKFS_PARM* opt, /* Format options */ + void* work, /* Pointer to working buffer (null: use heap memory) */ + UINT len /* Size of working buffer [byte] */ +) +{ + static const WORD cst[] = {1, 4, 16, 64, 256, 512, 0}; /* Cluster size boundary for FAT volume (4Ks unit) */ + static const WORD cst32[] = {1, 2, 4, 8, 16, 32, 0}; /* Cluster size boundary for FAT32 volume (128Ks unit) */ + static const MKFS_PARM defopt = {FM_ANY, 0, 0, 0, 0}; /* Default parameter */ + BYTE fsopt, fsty, sys, *buf, *pte, pdrv, ipart; + WORD ss; /* Sector size */ + DWORD sz_buf, sz_blk, n_clst, pau, nsect, n, vsn; + LBA_t sz_vol, b_vol, b_fat, b_data; /* Size of volume, Base LBA of volume, fat, data */ + LBA_t sect, lba[2]; + DWORD sz_rsv, sz_fat, sz_dir, sz_au; /* Size of reserved, fat, dir, data, cluster */ + UINT n_fat, n_root, i; /* Index, Number of FATs and Number of roor dir entries */ + int vol; + DSTATUS ds; + FRESULT fr; + + + /* Check mounted drive and clear work area */ + vol = get_ldnumber(&path); /* Get target logical drive */ + if (vol < 0) return FR_INVALID_DRIVE; + if (FatFs[vol]) FatFs[vol]->fs_type = 0; /* Clear the fs object if mounted */ + pdrv = LD2PD(vol); /* Physical drive */ + ipart = LD2PT(vol); /* Partition (0:create as new, 1..:get from partition table) */ + if (!opt) opt = &defopt; /* Use default parameter if it is not given */ + + /* Get physical drive status (sz_drv, sz_blk, ss) */ + ds = disk_initialize(pdrv); + if (ds & STA_NOINIT) return FR_NOT_READY; + if (ds & STA_PROTECT) return FR_WRITE_PROTECTED; + sz_blk = opt->align; + if (sz_blk == 0 && disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK) sz_blk = 1; + if (sz_blk == 0 || sz_blk > 0x8000 || (sz_blk & (sz_blk - 1))) sz_blk = 1; +#if FF_MAX_SS != FF_MIN_SS + if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR; + if (ss > FF_MAX_SS || ss < FF_MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR; +#else + ss = FF_MAX_SS; +#endif + /* Options for FAT sub-type and FAT parameters */ + fsopt = opt->fmt & (FM_ANY | FM_SFD); + n_fat = (opt->n_fat >= 1 && opt->n_fat <= 2) ? opt->n_fat : 1; + n_root = (opt->n_root >= 1 && opt->n_root <= 32768 && (opt->n_root % (ss / SZDIRE)) == 0) ? opt->n_root : 512; + sz_au = (opt->au_size <= 0x1000000 && (opt->au_size & (opt->au_size - 1)) == 0) ? opt->au_size : 0; + sz_au /= ss; /* Byte --> Sector */ + + /* Get working buffer */ + sz_buf = len / ss; /* Size of working buffer [sector] */ + if (sz_buf == 0) return FR_NOT_ENOUGH_CORE; + buf = (BYTE*)work; /* Working buffer */ +#if FF_USE_LFN == 3 + if (!buf) buf = ff_memalloc(sz_buf * ss); /* Use heap memory for working buffer */ +#endif + if (!buf) return FR_NOT_ENOUGH_CORE; + + /* Determine where the volume to be located (b_vol, sz_vol) */ + b_vol = sz_vol = 0; + if (FF_MULTI_PARTITION && ipart != 0) { /* Is the volume associated with any specific partition? */ + /* Get partition location from the existing partition table */ + if (disk_read(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Load MBR */ + if (ld_word(buf + BS_55AA) != 0xAA55) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if MBR is valid */ +#if FF_LBA64 + if (buf[MBR_Table + PTE_System] == 0xEE) { /* GPT protective MBR? */ + DWORD n_ent, ofs; + QWORD pt_lba; + + /* Get the partition location from GPT */ + if (disk_read(pdrv, buf, 1, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Load GPT header sector (next to MBR) */ + if (!test_gpt_header(buf)) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if GPT header is valid */ + n_ent = ld_dword(buf + GPTH_PtNum); /* Number of entries */ + pt_lba = ld_qword(buf + GPTH_PtOfs); /* Table start sector */ + ofs = i = 0; + while (n_ent) { /* Find MS Basic partition with order of ipart */ + if (ofs == 0 && disk_read(pdrv, buf, pt_lba++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Get PT sector */ + if (!memcmp(buf + ofs + GPTE_PtGuid, GUID_MS_Basic, 16) && ++i == ipart) { /* MS basic data partition? */ + b_vol = ld_qword(buf + ofs + GPTE_FstLba); + sz_vol = ld_qword(buf + ofs + GPTE_LstLba) - b_vol + 1; + break; + } + n_ent--; ofs = (ofs + SZ_GPTE) % ss; /* Next entry */ + } + if (n_ent == 0) LEAVE_MKFS(FR_MKFS_ABORTED); /* Partition not found */ + fsopt |= 0x80; /* Partitioning is in GPT */ + } else +#endif + { /* Get the partition location from MBR partition table */ + pte = buf + (MBR_Table + (ipart - 1) * SZ_PTE); + if (ipart > 4 || pte[PTE_System] == 0) LEAVE_MKFS(FR_MKFS_ABORTED); /* No partition? */ + b_vol = ld_dword(pte + PTE_StLba); /* Get volume start sector */ + sz_vol = ld_dword(pte + PTE_SizLba); /* Get volume size */ + } + } else { /* The volume is associated with a physical drive */ + if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + if (!(fsopt & FM_SFD)) { /* To be partitioned? */ + /* Create a single-partition on the drive in this function */ +#if FF_LBA64 + if (sz_vol >= FF_MIN_GPT) { /* Which partition type to create, MBR or GPT? */ + fsopt |= 0x80; /* Partitioning is in GPT */ + b_vol = GPT_ALIGN / ss; sz_vol -= b_vol + GPT_ITEMS * SZ_GPTE / ss + 1; /* Estimated partition offset and size */ + } else +#endif + { /* Partitioning is in MBR */ + if (sz_vol > N_SEC_TRACK) { + b_vol = N_SEC_TRACK; sz_vol -= b_vol; /* Estimated partition offset and size */ + } + } + } + } + if (sz_vol < 128) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if volume size is >=128s */ + + /* Now start to create an FAT volume at b_vol and sz_vol */ + + do { /* Pre-determine the FAT type */ + if (FF_FS_EXFAT && (fsopt & FM_EXFAT)) { /* exFAT possible? */ + if ((fsopt & FM_ANY) == FM_EXFAT || sz_vol >= 0x4000000 || sz_au > 128) { /* exFAT only, vol >= 64MS or sz_au > 128S ? */ + fsty = FS_EXFAT; break; + } + } +#if FF_LBA64 + if (sz_vol >= 0x100000000) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too large volume for FAT/FAT32 */ +#endif + if (sz_au > 128) sz_au = 128; /* Invalid AU for FAT/FAT32? */ + if (fsopt & FM_FAT32) { /* FAT32 possible? */ + if (!(fsopt & FM_FAT)) { /* no-FAT? */ + fsty = FS_FAT32; break; + } + } + if (!(fsopt & FM_FAT)) LEAVE_MKFS(FR_INVALID_PARAMETER); /* no-FAT? */ + fsty = FS_FAT16; + } while (0); + + vsn = (DWORD)sz_vol + GET_FATTIME(); /* VSN generated from current time and partitiion size */ + +#if FF_FS_EXFAT + if (fsty == FS_EXFAT) { /* Create an exFAT volume */ + DWORD szb_bit, szb_case, sum, nbit, clu, clen[3]; + WCHAR ch, si; + UINT j, st; + + if (sz_vol < 0x1000) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume for exFAT? */ +#if FF_USE_TRIM + lba[0] = b_vol; lba[1] = b_vol + sz_vol - 1; /* Inform storage device that the volume area may be erased */ + disk_ioctl(pdrv, CTRL_TRIM, lba); +#endif + /* Determine FAT location, data location and number of clusters */ + if (sz_au == 0) { /* AU auto-selection */ + sz_au = 8; + if (sz_vol >= 0x80000) sz_au = 64; /* >= 512Ks */ + if (sz_vol >= 0x4000000) sz_au = 256; /* >= 64Ms */ + } + b_fat = b_vol + 32; /* FAT start at offset 32 */ + sz_fat = (DWORD)((sz_vol / sz_au + 2) * 4 + ss - 1) / ss; /* Number of FAT sectors */ + b_data = (b_fat + sz_fat + sz_blk - 1) & ~((LBA_t)sz_blk - 1); /* Align data area to the erase block boundary */ + if (b_data - b_vol >= sz_vol / 2) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume? */ + n_clst = (DWORD)(sz_vol - (b_data - b_vol)) / sz_au; /* Number of clusters */ + if (n_clst <16) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too few clusters? */ + if (n_clst > MAX_EXFAT) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too many clusters? */ + + szb_bit = (n_clst + 7) / 8; /* Size of allocation bitmap */ + clen[0] = (szb_bit + sz_au * ss - 1) / (sz_au * ss); /* Number of allocation bitmap clusters */ + + /* Create a compressed up-case table */ + sect = b_data + sz_au * clen[0]; /* Table start sector */ + sum = 0; /* Table checksum to be stored in the 82 entry */ + st = 0; si = 0; i = 0; j = 0; szb_case = 0; + do { + switch (st) { + case 0: + ch = (WCHAR)ff_wtoupper(si); /* Get an up-case char */ + if (ch != si) { + si++; break; /* Store the up-case char if exist */ + } + for (j = 1; (WCHAR)(si + j) && (WCHAR)(si + j) == ff_wtoupper((WCHAR)(si + j)); j++) ; /* Get run length of no-case block */ + if (j >= 128) { + ch = 0xFFFF; st = 2; break; /* Compress the no-case block if run is >= 128 chars */ + } + st = 1; /* Do not compress short run */ + /* FALLTHROUGH */ + case 1: + ch = si++; /* Fill the short run */ + if (--j == 0) st = 0; + break; + + default: + ch = (WCHAR)j; si += (WCHAR)j; /* Number of chars to skip */ + st = 0; + } + sum = xsum32(buf[i + 0] = (BYTE)ch, sum); /* Put it into the write buffer */ + sum = xsum32(buf[i + 1] = (BYTE)(ch >> 8), sum); + i += 2; szb_case += 2; + if (si == 0 || i == sz_buf * ss) { /* Write buffered data when buffer full or end of process */ + n = (i + ss - 1) / ss; + if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + sect += n; i = 0; + } + } while (si); + clen[1] = (szb_case + sz_au * ss - 1) / (sz_au * ss); /* Number of up-case table clusters */ + clen[2] = 1; /* Number of root dir clusters */ + + /* Initialize the allocation bitmap */ + sect = b_data; nsect = (szb_bit + ss - 1) / ss; /* Start of bitmap and number of bitmap sectors */ + nbit = clen[0] + clen[1] + clen[2]; /* Number of clusters in-use by system (bitmap, up-case and root-dir) */ + do { + memset(buf, 0, sz_buf * ss); /* Initialize bitmap buffer */ + for (i = 0; nbit != 0 && i / 8 < sz_buf * ss; buf[i / 8] |= 1 << (i % 8), i++, nbit--) ; /* Mark used clusters */ + n = (nsect > sz_buf) ? sz_buf : nsect; /* Write the buffered data */ + if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + sect += n; nsect -= n; + } while (nsect); + + /* Initialize the FAT */ + sect = b_fat; nsect = sz_fat; /* Start of FAT and number of FAT sectors */ + j = nbit = clu = 0; + do { + memset(buf, 0, sz_buf * ss); i = 0; /* Clear work area and reset write offset */ + if (clu == 0) { /* Initialize FAT [0] and FAT[1] */ + st_dword(buf + i, 0xFFFFFFF8); i += 4; clu++; + st_dword(buf + i, 0xFFFFFFFF); i += 4; clu++; + } + do { /* Create chains of bitmap, up-case and root dir */ + while (nbit != 0 && i < sz_buf * ss) { /* Create a chain */ + st_dword(buf + i, (nbit > 1) ? clu + 1 : 0xFFFFFFFF); + i += 4; clu++; nbit--; + } + if (nbit == 0 && j < 3) nbit = clen[j++]; /* Get next chain length */ + } while (nbit != 0 && i < sz_buf * ss); + n = (nsect > sz_buf) ? sz_buf : nsect; /* Write the buffered data */ + if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + sect += n; nsect -= n; + } while (nsect); + + /* Initialize the root directory */ + memset(buf, 0, sz_buf * ss); + buf[SZDIRE * 0 + 0] = ET_VLABEL; /* Volume label entry (no label) */ + buf[SZDIRE * 1 + 0] = ET_BITMAP; /* Bitmap entry */ + st_dword(buf + SZDIRE * 1 + 20, 2); /* cluster */ + st_dword(buf + SZDIRE * 1 + 24, szb_bit); /* size */ + buf[SZDIRE * 2 + 0] = ET_UPCASE; /* Up-case table entry */ + st_dword(buf + SZDIRE * 2 + 4, sum); /* sum */ + st_dword(buf + SZDIRE * 2 + 20, 2 + clen[0]); /* cluster */ + st_dword(buf + SZDIRE * 2 + 24, szb_case); /* size */ + sect = b_data + sz_au * (clen[0] + clen[1]); nsect = sz_au; /* Start of the root directory and number of sectors */ + do { /* Fill root directory sectors */ + n = (nsect > sz_buf) ? sz_buf : nsect; + if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + memset(buf, 0, ss); /* Rest of entries are filled with zero */ + sect += n; nsect -= n; + } while (nsect); + + /* Create two set of the exFAT VBR blocks */ + sect = b_vol; + for (n = 0; n < 2; n++) { + /* Main record (+0) */ + memset(buf, 0, ss); + memcpy(buf + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11); /* Boot jump code (x86), OEM name */ + st_qword(buf + BPB_VolOfsEx, b_vol); /* Volume offset in the physical drive [sector] */ + st_qword(buf + BPB_TotSecEx, sz_vol); /* Volume size [sector] */ + st_dword(buf + BPB_FatOfsEx, (DWORD)(b_fat - b_vol)); /* FAT offset [sector] */ + st_dword(buf + BPB_FatSzEx, sz_fat); /* FAT size [sector] */ + st_dword(buf + BPB_DataOfsEx, (DWORD)(b_data - b_vol)); /* Data offset [sector] */ + st_dword(buf + BPB_NumClusEx, n_clst); /* Number of clusters */ + st_dword(buf + BPB_RootClusEx, 2 + clen[0] + clen[1]); /* Root dir cluster # */ + st_dword(buf + BPB_VolIDEx, vsn); /* VSN */ + st_word(buf + BPB_FSVerEx, 0x100); /* Filesystem version (1.00) */ + for (buf[BPB_BytsPerSecEx] = 0, i = ss; i >>= 1; buf[BPB_BytsPerSecEx]++) ; /* Log2 of sector size [byte] */ + for (buf[BPB_SecPerClusEx] = 0, i = sz_au; i >>= 1; buf[BPB_SecPerClusEx]++) ; /* Log2 of cluster size [sector] */ + buf[BPB_NumFATsEx] = 1; /* Number of FATs */ + buf[BPB_DrvNumEx] = 0x80; /* Drive number (for int13) */ + st_word(buf + BS_BootCodeEx, 0xFEEB); /* Boot code (x86) */ + st_word(buf + BS_55AA, 0xAA55); /* Signature (placed here regardless of sector size) */ + for (i = sum = 0; i < ss; i++) { /* VBR checksum */ + if (i != BPB_VolFlagEx && i != BPB_VolFlagEx + 1 && i != BPB_PercInUseEx) sum = xsum32(buf[i], sum); + } + if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + /* Extended bootstrap record (+1..+8) */ + memset(buf, 0, ss); + st_word(buf + ss - 2, 0xAA55); /* Signature (placed at end of sector) */ + for (j = 1; j < 9; j++) { + for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ; /* VBR checksum */ + if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + } + /* OEM/Reserved record (+9..+10) */ + memset(buf, 0, ss); + for ( ; j < 11; j++) { + for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ; /* VBR checksum */ + if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + } + /* Sum record (+11) */ + for (i = 0; i < ss; i += 4) st_dword(buf + i, sum); /* Fill with checksum value */ + if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + } + + } else +#endif /* FF_FS_EXFAT */ + { /* Create an FAT/FAT32 volume */ + do { + pau = sz_au; + /* Pre-determine number of clusters and FAT sub-type */ + if (fsty == FS_FAT32) { /* FAT32 volume */ + if (pau == 0) { /* AU auto-selection */ + n = (DWORD)sz_vol / 0x20000; /* Volume size in unit of 128KS */ + for (i = 0, pau = 1; cst32[i] && cst32[i] <= n; i++, pau <<= 1) ; /* Get from table */ + } + n_clst = (DWORD)sz_vol / pau; /* Number of clusters */ + sz_fat = (n_clst * 4 + 8 + ss - 1) / ss; /* FAT size [sector] */ + sz_rsv = 32; /* Number of reserved sectors */ + sz_dir = 0; /* No static directory */ + if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) LEAVE_MKFS(FR_MKFS_ABORTED); + } else { /* FAT volume */ + if (pau == 0) { /* au auto-selection */ + n = (DWORD)sz_vol / 0x1000; /* Volume size in unit of 4KS */ + for (i = 0, pau = 1; cst[i] && cst[i] <= n; i++, pau <<= 1) ; /* Get from table */ + } + n_clst = (DWORD)sz_vol / pau; + if (n_clst > MAX_FAT12) { + n = n_clst * 2 + 4; /* FAT size [byte] */ + } else { + fsty = FS_FAT12; + n = (n_clst * 3 + 1) / 2 + 3; /* FAT size [byte] */ + } + sz_fat = (n + ss - 1) / ss; /* FAT size [sector] */ + sz_rsv = 1; /* Number of reserved sectors */ + sz_dir = (DWORD)n_root * SZDIRE / ss; /* Root dir size [sector] */ + } + b_fat = b_vol + sz_rsv; /* FAT base */ + b_data = b_fat + sz_fat * n_fat + sz_dir; /* Data base */ + + /* Align data area to erase block boundary (for flash memory media) */ + n = (DWORD)(((b_data + sz_blk - 1) & ~(sz_blk - 1)) - b_data); /* Sectors to next nearest from current data base */ + if (fsty == FS_FAT32) { /* FAT32: Move FAT */ + sz_rsv += n; b_fat += n; + } else { /* FAT: Expand FAT */ + if (n % n_fat) { /* Adjust fractional error if needed */ + n--; sz_rsv++; b_fat++; + } + sz_fat += n / n_fat; + } + + /* Determine number of clusters and final check of validity of the FAT sub-type */ + if (sz_vol < b_data + pau * 16 - b_vol) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume? */ + n_clst = ((DWORD)sz_vol - sz_rsv - sz_fat * n_fat - sz_dir) / pau; + if (fsty == FS_FAT32) { + if (n_clst <= MAX_FAT16) { /* Too few clusters for FAT32? */ + if (sz_au == 0 && (sz_au = pau / 2) != 0) continue; /* Adjust cluster size and retry */ + LEAVE_MKFS(FR_MKFS_ABORTED); + } + } + if (fsty == FS_FAT16) { + if (n_clst > MAX_FAT16) { /* Too many clusters for FAT16 */ + if (sz_au == 0 && (pau * 2) <= 64) { + sz_au = pau * 2; continue; /* Adjust cluster size and retry */ + } + if ((fsopt & FM_FAT32)) { + fsty = FS_FAT32; continue; /* Switch type to FAT32 and retry */ + } + if (sz_au == 0 && (sz_au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */ + LEAVE_MKFS(FR_MKFS_ABORTED); + } + if (n_clst <= MAX_FAT12) { /* Too few clusters for FAT16 */ + if (sz_au == 0 && (sz_au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */ + LEAVE_MKFS(FR_MKFS_ABORTED); + } + } + if (fsty == FS_FAT12 && n_clst > MAX_FAT12) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too many clusters for FAT12 */ + + /* Ok, it is the valid cluster configuration */ + break; + } while (1); + +#if FF_USE_TRIM + lba[0] = b_vol; lba[1] = b_vol + sz_vol - 1; /* Inform storage device that the volume area may be erased */ + disk_ioctl(pdrv, CTRL_TRIM, lba); +#endif + /* Create FAT VBR */ + memset(buf, 0, ss); + memcpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11); /* Boot jump code (x86), OEM name */ + st_word(buf + BPB_BytsPerSec, ss); /* Sector size [byte] */ + buf[BPB_SecPerClus] = (BYTE)pau; /* Cluster size [sector] */ + st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv); /* Size of reserved area */ + buf[BPB_NumFATs] = (BYTE)n_fat; /* Number of FATs */ + st_word(buf + BPB_RootEntCnt, (WORD)((fsty == FS_FAT32) ? 0 : n_root)); /* Number of root directory entries */ + if (sz_vol < 0x10000) { + st_word(buf + BPB_TotSec16, (WORD)sz_vol); /* Volume size in 16-bit LBA */ + } else { + st_dword(buf + BPB_TotSec32, (DWORD)sz_vol); /* Volume size in 32-bit LBA */ + } + buf[BPB_Media] = 0xF8; /* Media descriptor byte */ + st_word(buf + BPB_SecPerTrk, 63); /* Number of sectors per track (for int13) */ + st_word(buf + BPB_NumHeads, 255); /* Number of heads (for int13) */ + st_dword(buf + BPB_HiddSec, (DWORD)b_vol); /* Volume offset in the physical drive [sector] */ + if (fsty == FS_FAT32) { + st_dword(buf + BS_VolID32, vsn); /* VSN */ + st_dword(buf + BPB_FATSz32, sz_fat); /* FAT size [sector] */ + st_dword(buf + BPB_RootClus32, 2); /* Root directory cluster # (2) */ + st_word(buf + BPB_FSInfo32, 1); /* Offset of FSINFO sector (VBR + 1) */ + st_word(buf + BPB_BkBootSec32, 6); /* Offset of backup VBR (VBR + 6) */ + buf[BS_DrvNum32] = 0x80; /* Drive number (for int13) */ + buf[BS_BootSig32] = 0x29; /* Extended boot signature */ + memcpy(buf + BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */ + } else { + st_dword(buf + BS_VolID, vsn); /* VSN */ + st_word(buf + BPB_FATSz16, (WORD)sz_fat); /* FAT size [sector] */ + buf[BS_DrvNum] = 0x80; /* Drive number (for int13) */ + buf[BS_BootSig] = 0x29; /* Extended boot signature */ + memcpy(buf + BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */ + } + st_word(buf + BS_55AA, 0xAA55); /* Signature (offset is fixed here regardless of sector size) */ + if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Write it to the VBR sector */ + + /* Create FSINFO record if needed */ + if (fsty == FS_FAT32) { + disk_write(pdrv, buf, b_vol + 6, 1); /* Write backup VBR (VBR + 6) */ + memset(buf, 0, ss); + st_dword(buf + FSI_LeadSig, 0x41615252); + st_dword(buf + FSI_StrucSig, 0x61417272); + st_dword(buf + FSI_Free_Count, n_clst - 1); /* Number of free clusters */ + st_dword(buf + FSI_Nxt_Free, 2); /* Last allocated cluster# */ + st_word(buf + BS_55AA, 0xAA55); + disk_write(pdrv, buf, b_vol + 7, 1); /* Write backup FSINFO (VBR + 7) */ + disk_write(pdrv, buf, b_vol + 1, 1); /* Write original FSINFO (VBR + 1) */ + } + + /* Initialize FAT area */ + memset(buf, 0, sz_buf * ss); + sect = b_fat; /* FAT start sector */ + for (i = 0; i < n_fat; i++) { /* Initialize FATs each */ + if (fsty == FS_FAT32) { + st_dword(buf + 0, 0xFFFFFFF8); /* FAT[0] */ + st_dword(buf + 4, 0xFFFFFFFF); /* FAT[1] */ + st_dword(buf + 8, 0x0FFFFFFF); /* FAT[2] (root directory) */ + } else { + st_dword(buf + 0, (fsty == FS_FAT12) ? 0xFFFFF8 : 0xFFFFFFF8); /* FAT[0] and FAT[1] */ + } + nsect = sz_fat; /* Number of FAT sectors */ + do { /* Fill FAT sectors */ + n = (nsect > sz_buf) ? sz_buf : nsect; + if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + memset(buf, 0, ss); /* Rest of FAT all are cleared */ + sect += n; nsect -= n; + } while (nsect); + } + + /* Initialize root directory (fill with zero) */ + nsect = (fsty == FS_FAT32) ? pau : sz_dir; /* Number of root directory sectors */ + do { + n = (nsect > sz_buf) ? sz_buf : nsect; + if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + sect += n; nsect -= n; + } while (nsect); + } + + /* A FAT volume has been created here */ + + /* Determine system ID in the MBR partition table */ + if (FF_FS_EXFAT && fsty == FS_EXFAT) { + sys = 0x07; /* exFAT */ + } else { + if (fsty == FS_FAT32) { + sys = 0x0C; /* FAT32X */ + } else { + if (sz_vol >= 0x10000) { + sys = 0x06; /* FAT12/16 (large) */ + } else { + sys = (fsty == FS_FAT16) ? 0x04 : 0x01; /* FAT16 : FAT12 */ + } + } + } + + /* Update partition information */ + if (FF_MULTI_PARTITION && ipart != 0) { /* Volume is in the existing partition */ + if (!FF_LBA64 || !(fsopt & 0x80)) { + /* Update system ID in the partition table */ + if (disk_read(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Read the MBR */ + buf[MBR_Table + (ipart - 1) * SZ_PTE + PTE_System] = sys; /* Set system ID */ + if (disk_write(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Write it back to the MBR */ + } + } else { /* Volume as a new single partition */ + if (!(fsopt & FM_SFD)) { /* Create partition table if not in SFD */ + lba[0] = sz_vol; lba[1] = 0; + fr = create_partition(pdrv, lba, sys, buf); + if (fr != FR_OK) LEAVE_MKFS(fr); + } + } + + if (disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); + + LEAVE_MKFS(FR_OK); +} + + + + +#if FF_MULTI_PARTITION +/*-----------------------------------------------------------------------*/ +/* Create Partition Table on the Physical Drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_fdisk ( + BYTE pdrv, /* Physical drive number */ + const LBA_t ptbl[], /* Pointer to the size table for each partitions */ + void* work /* Pointer to the working buffer (null: use heap memory) */ +) +{ + BYTE *buf = (BYTE*)work; + DSTATUS stat; + + + stat = disk_initialize(pdrv); + if (stat & STA_NOINIT) return FR_NOT_READY; + if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; +#if FF_USE_LFN == 3 + if (!buf) buf = ff_memalloc(FF_MAX_SS); /* Use heap memory for working buffer */ +#endif + if (!buf) return FR_NOT_ENOUGH_CORE; + + LEAVE_MKFS(create_partition(pdrv, ptbl, 0x07, buf)); +} + +#endif /* FF_MULTI_PARTITION */ +#endif /* !FF_FS_READONLY && FF_USE_MKFS */ + + + + +#if FF_USE_STRFUNC +#if FF_USE_LFN && FF_LFN_UNICODE && (FF_STRF_ENCODE < 0 || FF_STRF_ENCODE > 3) +#error Wrong FF_STRF_ENCODE setting +#endif +/*-----------------------------------------------------------------------*/ +/* Get a String from the File */ +/*-----------------------------------------------------------------------*/ + +TCHAR* f_gets ( + TCHAR* buff, /* Pointer to the buffer to store read string */ + int len, /* Size of string buffer (items) */ + FIL* fp /* Pointer to the file object */ +) +{ + int nc = 0; + TCHAR *p = buff; + BYTE s[4]; + UINT rc; + DWORD dc; +#if FF_USE_LFN && FF_LFN_UNICODE && FF_STRF_ENCODE <= 2 + WCHAR wc; +#endif +#if FF_USE_LFN && FF_LFN_UNICODE && FF_STRF_ENCODE == 3 + UINT ct; +#endif + +#if FF_USE_LFN && FF_LFN_UNICODE /* With code conversion (Unicode API) */ + /* Make a room for the character and terminator */ + if (FF_LFN_UNICODE == 1) len -= (FF_STRF_ENCODE == 0) ? 1 : 2; + if (FF_LFN_UNICODE == 2) len -= (FF_STRF_ENCODE == 0) ? 3 : 4; + if (FF_LFN_UNICODE == 3) len -= 1; + while (nc < len) { +#if FF_STRF_ENCODE == 0 /* Read a character in ANSI/OEM */ + f_read(fp, s, 1, &rc); /* Get a code unit */ + if (rc != 1) break; /* EOF? */ + wc = s[0]; + if (dbc_1st((BYTE)wc)) { /* DBC 1st byte? */ + f_read(fp, s, 1, &rc); /* Get 2nd byte */ + if (rc != 1 || !dbc_2nd(s[0])) continue; /* Wrong code? */ + wc = wc << 8 | s[0]; + } + dc = ff_oem2uni(wc, CODEPAGE); /* Convert ANSI/OEM into Unicode */ + if (dc == 0) continue; /* Conversion error? */ +#elif FF_STRF_ENCODE == 1 || FF_STRF_ENCODE == 2 /* Read a character in UTF-16LE/BE */ + f_read(fp, s, 2, &rc); /* Get a code unit */ + if (rc != 2) break; /* EOF? */ + dc = (FF_STRF_ENCODE == 1) ? ld_word(s) : s[0] << 8 | s[1]; + if (IsSurrogateL(dc)) continue; /* Broken surrogate pair? */ + if (IsSurrogateH(dc)) { /* High surrogate? */ + f_read(fp, s, 2, &rc); /* Get low surrogate */ + if (rc != 2) break; /* EOF? */ + wc = (FF_STRF_ENCODE == 1) ? ld_word(s) : s[0] << 8 | s[1]; + if (!IsSurrogateL(wc)) continue; /* Broken surrogate pair? */ + dc = ((dc & 0x3FF) + 0x40) << 10 | (wc & 0x3FF); /* Merge surrogate pair */ + } +#else /* Read a character in UTF-8 */ + f_read(fp, s, 1, &rc); /* Get a code unit */ + if (rc != 1) break; /* EOF? */ + dc = s[0]; + if (dc >= 0x80) { /* Multi-byte sequence? */ + ct = 0; + if ((dc & 0xE0) == 0xC0) { dc &= 0x1F; ct = 1; } /* 2-byte sequence? */ + if ((dc & 0xF0) == 0xE0) { dc &= 0x0F; ct = 2; } /* 3-byte sequence? */ + if ((dc & 0xF8) == 0xF0) { dc &= 0x07; ct = 3; } /* 4-byte sequence? */ + if (ct == 0) continue; + f_read(fp, s, ct, &rc); /* Get trailing bytes */ + if (rc != ct) break; + rc = 0; + do { /* Merge the byte sequence */ + if ((s[rc] & 0xC0) != 0x80) break; + dc = dc << 6 | (s[rc] & 0x3F); + } while (++rc < ct); + if (rc != ct || dc < 0x80 || IsSurrogate(dc) || dc >= 0x110000) continue; /* Wrong encoding? */ + } +#endif + /* A code point is avaialble in dc to be output */ + + if (FF_USE_STRFUNC == 2 && dc == '\r') continue; /* Strip \r off if needed */ +#if FF_LFN_UNICODE == 1 || FF_LFN_UNICODE == 3 /* Output it in UTF-16/32 encoding */ + if (FF_LFN_UNICODE == 1 && dc >= 0x10000) { /* Out of BMP at UTF-16? */ + *p++ = (TCHAR)(0xD800 | ((dc >> 10) - 0x40)); nc++; /* Make and output high surrogate */ + dc = 0xDC00 | (dc & 0x3FF); /* Make low surrogate */ + } + *p++ = (TCHAR)dc; nc++; + if (dc == '\n') break; /* End of line? */ +#elif FF_LFN_UNICODE == 2 /* Output it in UTF-8 encoding */ + if (dc < 0x80) { /* Single byte? */ + *p++ = (TCHAR)dc; + nc++; + if (dc == '\n') break; /* End of line? */ + } else { + if (dc < 0x800) { /* 2-byte sequence? */ + *p++ = (TCHAR)(0xC0 | (dc >> 6 & 0x1F)); + *p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F)); + nc += 2; + } else { + if (dc < 0x10000) { /* 3-byte sequence? */ + *p++ = (TCHAR)(0xE0 | (dc >> 12 & 0x0F)); + *p++ = (TCHAR)(0x80 | (dc >> 6 & 0x3F)); + *p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F)); + nc += 3; + } else { /* 4-byte sequence? */ + *p++ = (TCHAR)(0xF0 | (dc >> 18 & 0x07)); + *p++ = (TCHAR)(0x80 | (dc >> 12 & 0x3F)); + *p++ = (TCHAR)(0x80 | (dc >> 6 & 0x3F)); + *p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F)); + nc += 4; + } + } + } +#endif + } + +#else /* Byte-by-byte read without any conversion (ANSI/OEM API) */ + len -= 1; /* Make a room for the terminator */ + while (nc < len) { + f_read(fp, s, 1, &rc); /* Get a byte */ + if (rc != 1) break; /* EOF? */ + dc = s[0]; + if (FF_USE_STRFUNC == 2 && dc == '\r') continue; + *p++ = (TCHAR)dc; nc++; + if (dc == '\n') break; + } +#endif + + *p = 0; /* Terminate the string */ + return nc ? buff : 0; /* When no data read due to EOF or error, return with error. */ +} + + + + +#if !FF_FS_READONLY +#include +#define SZ_PUTC_BUF 64 +#define SZ_NUM_BUF 32 + +/*-----------------------------------------------------------------------*/ +/* Put a Character to the File (with sub-functions) */ +/*-----------------------------------------------------------------------*/ + +/* Output buffer and work area */ + +typedef struct { + FIL *fp; /* Ptr to the writing file */ + int idx, nchr; /* Write index of buf[] (-1:error), number of encoding units written */ +#if FF_USE_LFN && FF_LFN_UNICODE == 1 + WCHAR hs; +#elif FF_USE_LFN && FF_LFN_UNICODE == 2 + BYTE bs[4]; + UINT wi, ct; +#endif + BYTE buf[SZ_PUTC_BUF]; /* Write buffer */ +} putbuff; + + +/* Buffered file write with code conversion */ + +static void putc_bfd (putbuff* pb, TCHAR c) +{ + UINT n; + int i, nc; +#if FF_USE_LFN && FF_LFN_UNICODE + WCHAR hs, wc; +#if FF_LFN_UNICODE == 2 + DWORD dc; + const TCHAR *tp; +#endif +#endif + + if (FF_USE_STRFUNC == 2 && c == '\n') { /* LF -> CRLF conversion */ + putc_bfd(pb, '\r'); + } + + i = pb->idx; /* Write index of pb->buf[] */ + if (i < 0) return; /* In write error? */ + nc = pb->nchr; /* Write unit counter */ + +#if FF_USE_LFN && FF_LFN_UNICODE +#if FF_LFN_UNICODE == 1 /* UTF-16 input */ + if (IsSurrogateH(c)) { /* High surrogate? */ + pb->hs = c; return; /* Save it for next */ + } + hs = pb->hs; pb->hs = 0; + if (hs != 0) { /* There is a leading high surrogate */ + if (!IsSurrogateL(c)) hs = 0; /* Discard high surrogate if not a surrogate pair */ + } else { + if (IsSurrogateL(c)) return; /* Discard stray low surrogate */ + } + wc = c; +#elif FF_LFN_UNICODE == 2 /* UTF-8 input */ + for (;;) { + if (pb->ct == 0) { /* Out of multi-byte sequence? */ + pb->bs[pb->wi = 0] = (BYTE)c; /* Save 1st byte */ + if ((BYTE)c < 0x80) break; /* Single byte? */ + if (((BYTE)c & 0xE0) == 0xC0) pb->ct = 1; /* 2-byte sequence? */ + if (((BYTE)c & 0xF0) == 0xE0) pb->ct = 2; /* 3-byte sequence? */ + if (((BYTE)c & 0xF1) == 0xF0) pb->ct = 3; /* 4-byte sequence? */ + return; + } else { /* In the multi-byte sequence */ + if (((BYTE)c & 0xC0) != 0x80) { /* Broken sequence? */ + pb->ct = 0; continue; + } + pb->bs[++pb->wi] = (BYTE)c; /* Save the trailing byte */ + if (--pb->ct == 0) break; /* End of multi-byte sequence? */ + return; + } + } + tp = (const TCHAR*)pb->bs; + dc = tchar2uni(&tp); /* UTF-8 ==> UTF-16 */ + if (dc == 0xFFFFFFFF) return; /* Wrong code? */ + wc = (WCHAR)dc; + hs = (WCHAR)(dc >> 16); +#elif FF_LFN_UNICODE == 3 /* UTF-32 input */ + if (IsSurrogate(c) || c >= 0x110000) return; /* Discard invalid code */ + if (c >= 0x10000) { /* Out of BMP? */ + hs = (WCHAR)(0xD800 | ((c >> 10) - 0x40)); /* Make high surrogate */ + wc = 0xDC00 | (c & 0x3FF); /* Make low surrogate */ + } else { + hs = 0; + wc = (WCHAR)c; + } +#endif + /* A code point in UTF-16 is available in hs and wc */ + +#if FF_STRF_ENCODE == 1 /* Write a code point in UTF-16LE */ + if (hs != 0) { /* Surrogate pair? */ + st_word(&pb->buf[i], hs); + i += 2; + nc++; + } + st_word(&pb->buf[i], wc); + i += 2; +#elif FF_STRF_ENCODE == 2 /* Write a code point in UTF-16BE */ + if (hs != 0) { /* Surrogate pair? */ + pb->buf[i++] = (BYTE)(hs >> 8); + pb->buf[i++] = (BYTE)hs; + nc++; + } + pb->buf[i++] = (BYTE)(wc >> 8); + pb->buf[i++] = (BYTE)wc; +#elif FF_STRF_ENCODE == 3 /* Write a code point in UTF-8 */ + if (hs != 0) { /* 4-byte sequence? */ + nc += 3; + hs = (hs & 0x3FF) + 0x40; + pb->buf[i++] = (BYTE)(0xF0 | hs >> 8); + pb->buf[i++] = (BYTE)(0x80 | (hs >> 2 & 0x3F)); + pb->buf[i++] = (BYTE)(0x80 | (hs & 3) << 4 | (wc >> 6 & 0x0F)); + pb->buf[i++] = (BYTE)(0x80 | (wc & 0x3F)); + } else { + if (wc < 0x80) { /* Single byte? */ + pb->buf[i++] = (BYTE)wc; + } else { + if (wc < 0x800) { /* 2-byte sequence? */ + nc += 1; + pb->buf[i++] = (BYTE)(0xC0 | wc >> 6); + } else { /* 3-byte sequence */ + nc += 2; + pb->buf[i++] = (BYTE)(0xE0 | wc >> 12); + pb->buf[i++] = (BYTE)(0x80 | (wc >> 6 & 0x3F)); + } + pb->buf[i++] = (BYTE)(0x80 | (wc & 0x3F)); + } + } +#else /* Write a code point in ANSI/OEM */ + if (hs != 0) return; + wc = ff_uni2oem(wc, CODEPAGE); /* UTF-16 ==> ANSI/OEM */ + if (wc == 0) return; + if (wc >= 0x100) { + pb->buf[i++] = (BYTE)(wc >> 8); nc++; + } + pb->buf[i++] = (BYTE)wc; +#endif + +#else /* ANSI/OEM input (without re-encoding) */ + pb->buf[i++] = (BYTE)c; +#endif + + if (i >= (int)(sizeof pb->buf) - 4) { /* Write buffered characters to the file */ + f_write(pb->fp, pb->buf, (UINT)i, &n); + i = (n == (UINT)i) ? 0 : -1; + } + pb->idx = i; + pb->nchr = nc + 1; +} + + +/* Flush remaining characters in the buffer */ + +static int putc_flush (putbuff* pb) +{ + UINT nw; + + if ( pb->idx >= 0 /* Flush buffered characters to the file */ + && f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK + && (UINT)pb->idx == nw) return pb->nchr; + return -1; +} + + +/* Initialize write buffer */ + +static void putc_init (putbuff* pb, FIL* fp) +{ + memset(pb, 0, sizeof (putbuff)); + pb->fp = fp; +} + + + +int f_putc ( + TCHAR c, /* A character to be output */ + FIL* fp /* Pointer to the file object */ +) +{ + putbuff pb; + + + putc_init(&pb, fp); + putc_bfd(&pb, c); /* Put the character */ + return putc_flush(&pb); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a String to the File */ +/*-----------------------------------------------------------------------*/ + +int f_puts ( + const TCHAR* str, /* Pointer to the string to be output */ + FIL* fp /* Pointer to the file object */ +) +{ + putbuff pb; + + + putc_init(&pb, fp); + while (*str) putc_bfd(&pb, *str++); /* Put the string */ + return putc_flush(&pb); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a Formatted String to the File (with sub-functions) */ +/*-----------------------------------------------------------------------*/ +#if FF_PRINT_FLOAT && FF_INTDEF == 2 +#include + +static int ilog10 (double n) /* Calculate log10(n) in integer output */ +{ + int rv = 0; + + while (n >= 10) { /* Decimate digit in right shift */ + if (n >= 100000) { + n /= 100000; rv += 5; + } else { + n /= 10; rv++; + } + } + while (n < 1) { /* Decimate digit in left shift */ + if (n < 0.00001) { + n *= 100000; rv -= 5; + } else { + n *= 10; rv--; + } + } + return rv; +} + + +static double i10x (int n) /* Calculate 10^n in integer input */ +{ + double rv = 1; + + while (n > 0) { /* Left shift */ + if (n >= 5) { + rv *= 100000; n -= 5; + } else { + rv *= 10; n--; + } + } + while (n < 0) { /* Right shift */ + if (n <= -5) { + rv /= 100000; n += 5; + } else { + rv /= 10; n++; + } + } + return rv; +} + + +static void ftoa ( + char* buf, /* Buffer to output the floating point string */ + double val, /* Value to output */ + int prec, /* Number of fractional digits */ + TCHAR fmt /* Notation */ +) +{ + int d; + int e = 0, m = 0; + char sign = 0; + double w; + const char *er = 0; + const char ds = FF_PRINT_FLOAT == 2 ? ',' : '.'; + + + if (isnan(val)) { /* Not a number? */ + er = "NaN"; + } else { + if (prec < 0) prec = 6; /* Default precision? (6 fractional digits) */ + if (val < 0) { /* Nagative? */ + val = 0 - val; sign = '-'; + } else { + sign = '+'; + } + if (isinf(val)) { /* Infinite? */ + er = "INF"; + } else { + if (fmt == 'f') { /* Decimal notation? */ + val += i10x(0 - prec) / 2; /* Round (nearest) */ + m = ilog10(val); + if (m < 0) m = 0; + if (m + prec + 3 >= SZ_NUM_BUF) er = "OV"; /* Buffer overflow? */ + } else { /* E notation */ + if (val != 0) { /* Not a true zero? */ + val += i10x(ilog10(val) - prec) / 2; /* Round (nearest) */ + e = ilog10(val); + if (e > 99 || prec + 7 >= SZ_NUM_BUF) { /* Buffer overflow or E > +99? */ + er = "OV"; + } else { + if (e < -99) e = -99; + val /= i10x(e); /* Normalize */ + } + } + } + } + if (!er) { /* Not error condition */ + if (sign == '-') *buf++ = sign; /* Add a - if negative value */ + do { /* Put decimal number */ + if (m == -1) *buf++ = ds; /* Insert a decimal separator when get into fractional part */ + w = i10x(m); /* Snip the highest digit d */ + d = (int)(val / w); val -= d * w; + *buf++ = (char)('0' + d); /* Put the digit */ + } while (--m >= -prec); /* Output all digits specified by prec */ + if (fmt != 'f') { /* Put exponent if needed */ + *buf++ = (char)fmt; + if (e < 0) { + e = 0 - e; *buf++ = '-'; + } else { + *buf++ = '+'; + } + *buf++ = (char)('0' + e / 10); + *buf++ = (char)('0' + e % 10); + } + } + } + if (er) { /* Error condition */ + if (sign) *buf++ = sign; /* Add sign if needed */ + do *buf++ = *er++; while (*er); /* Put error symbol */ + } + *buf = 0; /* Term */ +} +#endif /* FF_PRINT_FLOAT && FF_INTDEF == 2 */ + + + +int f_printf ( + FIL* fp, /* Pointer to the file object */ + const TCHAR* fmt, /* Pointer to the format string */ + ... /* Optional arguments... */ +) +{ + va_list arp; + putbuff pb; + UINT i, j, w, f, r; + int prec; +#if FF_PRINT_LLI && FF_INTDEF == 2 + QWORD v; +#else + DWORD v; +#endif + TCHAR tc, pad, *tp; + TCHAR nul = 0; + char d, str[SZ_NUM_BUF]; + + + putc_init(&pb, fp); + + va_start(arp, fmt); + + for (;;) { + tc = *fmt++; + if (tc == 0) break; /* End of format string */ + if (tc != '%') { /* Not an escape character (pass-through) */ + putc_bfd(&pb, tc); + continue; + } + f = w = 0; pad = ' '; prec = -1; /* Initialize parms */ + tc = *fmt++; + if (tc == '0') { /* Flag: '0' padded */ + pad = '0'; tc = *fmt++; + } else if (tc == '-') { /* Flag: Left aligned */ + f = 2; tc = *fmt++; + } + if (tc == '*') { /* Minimum width from an argument */ + w = va_arg(arp, int); + tc = *fmt++; + } else { + while (IsDigit(tc)) { /* Minimum width */ + w = w * 10 + tc - '0'; + tc = *fmt++; + } + } + if (tc == '.') { /* Precision */ + tc = *fmt++; + if (tc == '*') { /* Precision from an argument */ + prec = va_arg(arp, int); + tc = *fmt++; + } else { + prec = 0; + while (IsDigit(tc)) { /* Precision */ + prec = prec * 10 + tc - '0'; + tc = *fmt++; + } + } + } + if (tc == 'l') { /* Size: long int */ + f |= 4; tc = *fmt++; +#if FF_PRINT_LLI && FF_INTDEF == 2 + if (tc == 'l') { /* Size: long long int */ + f |= 8; tc = *fmt++; + } +#endif + } + if (tc == 0) break; /* End of format string */ + switch (tc) { /* Atgument type is... */ + case 'b': /* Unsigned binary */ + r = 2; break; + case 'o': /* Unsigned octal */ + r = 8; break; + case 'd': /* Signed decimal */ + case 'u': /* Unsigned decimal */ + r = 10; break; + case 'x': /* Unsigned hexdecimal (lower case) */ + case 'X': /* Unsigned hexdecimal (upper case) */ + r = 16; break; + case 'c': /* Character */ + putc_bfd(&pb, (TCHAR)va_arg(arp, int)); + continue; + case 's': /* String */ + tp = va_arg(arp, TCHAR*); /* Get a pointer argument */ + if (!tp) tp = &nul; /* Null ptr generates a null string */ + for (j = 0; tp[j]; j++) ; /* j = tcslen(tp) */ + if (prec >= 0 && j > (UINT)prec) j = prec; /* Limited length of string body */ + for ( ; !(f & 2) && j < w; j++) putc_bfd(&pb, pad); /* Left pads */ + while (*tp && prec--) putc_bfd(&pb, *tp++); /* Body */ + while (j++ < w) putc_bfd(&pb, ' '); /* Right pads */ + continue; +#if FF_PRINT_FLOAT && FF_INTDEF == 2 + case 'f': /* Floating point (decimal) */ + case 'e': /* Floating point (e) */ + case 'E': /* Floating point (E) */ + ftoa(str, va_arg(arp, double), prec, tc); /* Make a flaoting point string */ + for (j = strlen(str); !(f & 2) && j < w; j++) putc_bfd(&pb, pad); /* Left pads */ + for (i = 0; str[i]; putc_bfd(&pb, str[i++])) ; /* Body */ + while (j++ < w) putc_bfd(&pb, ' '); /* Right pads */ + continue; +#endif + default: /* Unknown type (pass-through) */ + putc_bfd(&pb, tc); continue; + } + + /* Get an integer argument and put it in numeral */ +#if FF_PRINT_LLI && FF_INTDEF == 2 + if (f & 8) { /* long long argument? */ + v = (QWORD)va_arg(arp, LONGLONG); + } else { + if (f & 4) { /* long argument? */ + v = (tc == 'd') ? (QWORD)(LONGLONG)va_arg(arp, long) : (QWORD)va_arg(arp, unsigned long); + } else { /* int/short/char argument */ + v = (tc == 'd') ? (QWORD)(LONGLONG)va_arg(arp, int) : (QWORD)va_arg(arp, unsigned int); + } + } + if (tc == 'd' && (v & 0x8000000000000000)) { /* Negative value? */ + v = 0 - v; f |= 1; + } +#else + if (f & 4) { /* long argument? */ + v = (DWORD)va_arg(arp, long); + } else { /* int/short/char argument */ + v = (tc == 'd') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int); + } + if (tc == 'd' && (v & 0x80000000)) { /* Negative value? */ + v = 0 - v; f |= 1; + } +#endif + i = 0; + do { /* Make an integer number string */ + d = (char)(v % r); v /= r; + if (d > 9) d += (tc == 'x') ? 0x27 : 0x07; + str[i++] = d + '0'; + } while (v && i < SZ_NUM_BUF); + if (f & 1) str[i++] = '-'; /* Sign */ + /* Write it */ + for (j = i; !(f & 2) && j < w; j++) putc_bfd(&pb, pad); /* Left pads */ + do putc_bfd(&pb, (TCHAR)str[--i]); while (i); /* Body */ + while (j++ < w) putc_bfd(&pb, ' '); /* Right pads */ + } + + va_end(arp); + + return putc_flush(&pb); +} + +#endif /* !FF_FS_READONLY */ +#endif /* FF_USE_STRFUNC */ + + + +#if FF_CODE_PAGE == 0 +/*-----------------------------------------------------------------------*/ +/* Set Active Codepage for the Path Name */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_setcp ( + WORD cp /* Value to be set as active code page */ +) +{ + static const WORD validcp[22] = { 437, 720, 737, 771, 775, 850, 852, 855, 857, 860, 861, 862, 863, 864, 865, 866, 869, 932, 936, 949, 950, 0}; + static const BYTE* const tables[22] = {Ct437, Ct720, Ct737, Ct771, Ct775, Ct850, Ct852, Ct855, Ct857, Ct860, Ct861, Ct862, Ct863, Ct864, Ct865, Ct866, Ct869, Dc932, Dc936, Dc949, Dc950, 0}; + UINT i; + + + for (i = 0; validcp[i] != 0 && validcp[i] != cp; i++) ; /* Find the code page */ + if (validcp[i] != cp) return FR_INVALID_PARAMETER; /* Not found? */ + + CodePage = cp; + if (cp >= 900) { /* DBCS */ + ExCvt = 0; + DbcTbl = tables[i]; + } else { /* SBCS */ + ExCvt = tables[i]; + DbcTbl = 0; + } + return FR_OK; +} +#endif /* FF_CODE_PAGE == 0 */ + diff --git a/lib-hal/ff14b/source/ff.h b/lib-hal/ff14b/source/ff.h new file mode 100755 index 00000000..64bf79db --- /dev/null +++ b/lib-hal/ff14b/source/ff.h @@ -0,0 +1,422 @@ +/*----------------------------------------------------------------------------/ +/ FatFs - Generic FAT Filesystem module R0.14b / +/-----------------------------------------------------------------------------/ +/ +/ Copyright (C) 2021, ChaN, all right reserved. +/ +/ FatFs module is an open source software. Redistribution and use of FatFs in +/ source and binary forms, with or without modification, are permitted provided +/ that the following condition is met: + +/ 1. Redistributions of source code must retain the above copyright notice, +/ this condition and the following disclaimer. +/ +/ This software is provided by the copyright holder and contributors "AS IS" +/ and any warranties related to this software are DISCLAIMED. +/ The copyright owner or contributors be NOT LIABLE for any damages caused +/ by use of this software. +/ +/----------------------------------------------------------------------------*/ + + +#ifndef FF_DEFINED +#define FF_DEFINED 86631 /* Revision ID */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ffconf.h" /* FatFs configuration options */ + +#if FF_DEFINED != FFCONF_DEF +#error Wrong configuration file (ffconf.h). +#endif + + +/* Integer types used for FatFs API */ + +#if defined(_WIN32) /* Windows VC++ (for development only) */ +#define FF_INTDEF 2 +#include +typedef unsigned __int64 QWORD; +#include +#define isnan(v) _isnan(v) +#define isinf(v) (!_finite(v)) + +#elif (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || defined(__cplusplus) /* C99 or later */ +#define FF_INTDEF 2 +#include +typedef unsigned int UINT; /* int must be 16-bit or 32-bit */ +typedef unsigned char BYTE; /* char must be 8-bit */ +typedef uint16_t WORD; /* 16-bit unsigned integer */ +typedef uint32_t DWORD; /* 32-bit unsigned integer */ +typedef uint64_t QWORD; /* 64-bit unsigned integer */ +typedef WORD WCHAR; /* UTF-16 character type */ + +#else /* Earlier than C99 */ +#define FF_INTDEF 1 +typedef unsigned int UINT; /* int must be 16-bit or 32-bit */ +typedef unsigned char BYTE; /* char must be 8-bit */ +typedef unsigned short WORD; /* 16-bit unsigned integer */ +typedef unsigned long DWORD; /* 32-bit unsigned integer */ +typedef WORD WCHAR; /* UTF-16 character type */ +#endif + + +/* Type of file size and LBA variables */ + +#if FF_FS_EXFAT +#if FF_INTDEF != 2 +#error exFAT feature wants C99 or later +#endif +typedef QWORD FSIZE_t; +#if FF_LBA64 +typedef QWORD LBA_t; +#else +typedef DWORD LBA_t; +#endif +#else +#if FF_LBA64 +#error exFAT needs to be enabled when enable 64-bit LBA +#endif +typedef DWORD FSIZE_t; +typedef DWORD LBA_t; +#endif + + + +/* Type of path name strings on FatFs API (TCHAR) */ + +#if FF_USE_LFN && FF_LFN_UNICODE == 1 /* Unicode in UTF-16 encoding */ +typedef WCHAR TCHAR; +#define _T(x) L ## x +#define _TEXT(x) L ## x +#elif FF_USE_LFN && FF_LFN_UNICODE == 2 /* Unicode in UTF-8 encoding */ +typedef char TCHAR; +#define _T(x) u8 ## x +#define _TEXT(x) u8 ## x +#elif FF_USE_LFN && FF_LFN_UNICODE == 3 /* Unicode in UTF-32 encoding */ +typedef DWORD TCHAR; +#define _T(x) U ## x +#define _TEXT(x) U ## x +#elif FF_USE_LFN && (FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3) +#error Wrong FF_LFN_UNICODE setting +#else /* ANSI/OEM code in SBCS/DBCS */ +typedef char TCHAR; +#define _T(x) x +#define _TEXT(x) x +#endif + + + +/* Definitions of volume management */ + +#if FF_MULTI_PARTITION /* Multiple partition configuration */ +typedef struct { + BYTE pd; /* Physical drive number */ + BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */ +} PARTITION; +extern PARTITION VolToPart[]; /* Volume - Partition mapping table */ +#endif + +#if FF_STR_VOLUME_ID +#ifndef FF_VOLUME_STRS +extern const char* VolumeStr[FF_VOLUMES]; /* User defied volume ID */ +#endif +#endif + + + +/* Filesystem object structure (FATFS) */ + +typedef struct { + BYTE fs_type; /* Filesystem type (0:not mounted) */ + BYTE pdrv; /* Associated physical drive */ + BYTE n_fats; /* Number of FATs (1 or 2) */ + BYTE wflag; /* win[] flag (b0:dirty) */ + BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */ + WORD id; /* Volume mount ID */ + WORD n_rootdir; /* Number of root directory entries (FAT12/16) */ + WORD csize; /* Cluster size [sectors] */ +#if FF_MAX_SS != FF_MIN_SS + WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */ +#endif +#if FF_USE_LFN + WCHAR* lfnbuf; /* LFN working buffer */ +#endif +#if FF_FS_EXFAT + BYTE* dirbuf; /* Directory entry block scratchpad buffer for exFAT */ +#endif +#if FF_FS_REENTRANT + FF_SYNC_t sobj; /* Identifier of sync object */ +#endif +#if !FF_FS_READONLY + DWORD last_clst; /* Last allocated cluster */ + DWORD free_clst; /* Number of free clusters */ +#endif +#if FF_FS_RPATH + DWORD cdir; /* Current directory start cluster (0:root) */ +#if FF_FS_EXFAT + DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */ + DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */ + DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */ +#endif +#endif + DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */ + DWORD fsize; /* Size of an FAT [sectors] */ + LBA_t volbase; /* Volume base sector */ + LBA_t fatbase; /* FAT base sector */ + LBA_t dirbase; /* Root directory base sector/cluster */ + LBA_t database; /* Data base sector */ +#if FF_FS_EXFAT + LBA_t bitbase; /* Allocation bitmap base sector */ +#endif + LBA_t winsect; /* Current sector appearing in the win[] */ + BYTE win[FF_MAX_SS]; /* Disk access window for Directory, FAT (and file data at tiny cfg) */ +} FATFS; + + + +/* Object ID and allocation information (FFOBJID) */ + +typedef struct { + FATFS* fs; /* Pointer to the hosting volume of this object */ + WORD id; /* Hosting volume mount ID */ + BYTE attr; /* Object attribute */ + BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:fragmented in this session, b2:sub-directory stretched) */ + DWORD sclust; /* Object data start cluster (0:no cluster or root directory) */ + FSIZE_t objsize; /* Object size (valid when sclust != 0) */ +#if FF_FS_EXFAT + DWORD n_cont; /* Size of first fragment - 1 (valid when stat == 3) */ + DWORD n_frag; /* Size of last fragment needs to be written to FAT (valid when not zero) */ + DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */ + DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */ + DWORD c_ofs; /* Offset in the containing directory (valid when file object and sclust != 0) */ +#endif +#if FF_FS_LOCK + UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */ +#endif +} FFOBJID; + + + +/* File object structure (FIL) */ + +typedef struct { + FFOBJID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */ + BYTE flag; /* File status flags */ + BYTE err; /* Abort flag (error code) */ + FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */ + DWORD clust; /* Current cluster of fpter (invalid when fptr is 0) */ + LBA_t sect; /* Sector number appearing in buf[] (0:invalid) */ +#if !FF_FS_READONLY + LBA_t dir_sect; /* Sector number containing the directory entry (not used at exFAT) */ + BYTE* dir_ptr; /* Pointer to the directory entry in the win[] (not used at exFAT) */ +#endif +#if FF_USE_FASTSEEK + DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */ +#endif +#if !FF_FS_TINY + BYTE buf[FF_MAX_SS]; /* File private data read/write window */ +#endif +} FIL; + + + +/* Directory object structure (DIR) */ + +typedef struct { + FFOBJID obj; /* Object identifier */ + DWORD dptr; /* Current read/write offset */ + DWORD clust; /* Current cluster */ + LBA_t sect; /* Current sector (0:Read operation has terminated) */ + BYTE* dir; /* Pointer to the directory item in the win[] */ + BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */ +#if FF_USE_LFN + DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */ +#endif +#if FF_USE_FIND + const TCHAR* pat; /* Pointer to the name matching pattern */ +#endif +} DIR; + + + +/* File information structure (FILINFO) */ + +typedef struct { + FSIZE_t fsize; /* File size */ + WORD fdate; /* Modified date */ + WORD ftime; /* Modified time */ + BYTE fattrib; /* File attribute */ +#if FF_USE_LFN + TCHAR altname[FF_SFN_BUF + 1];/* Altenative file name */ + TCHAR fname[FF_LFN_BUF + 1]; /* Primary file name */ +#else + TCHAR fname[12 + 1]; /* File name */ +#endif +} FILINFO; + + + +/* Format parameter structure (MKFS_PARM) */ + +typedef struct { + BYTE fmt; /* Format option (FM_FAT, FM_FAT32, FM_EXFAT and FM_SFD) */ + BYTE n_fat; /* Number of FATs */ + UINT align; /* Data area alignment (sector) */ + UINT n_root; /* Number of root directory entries */ + DWORD au_size; /* Cluster size (byte) */ +} MKFS_PARM; + + + +/* File function return code (FRESULT) */ + +typedef enum { + FR_OK = 0, /* (0) Succeeded */ + FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */ + FR_INT_ERR, /* (2) Assertion failed */ + FR_NOT_READY, /* (3) The physical drive cannot work */ + FR_NO_FILE, /* (4) Could not find the file */ + FR_NO_PATH, /* (5) Could not find the path */ + FR_INVALID_NAME, /* (6) The path name format is invalid */ + FR_DENIED, /* (7) Access denied due to prohibited access or directory full */ + FR_EXIST, /* (8) Access denied due to prohibited access */ + FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */ + FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */ + FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */ + FR_NOT_ENABLED, /* (12) The volume has no work area */ + FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */ + FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */ + FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */ + FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */ + FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */ + FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > FF_FS_LOCK */ + FR_INVALID_PARAMETER /* (19) Given parameter is invalid */ +} FRESULT; + + + +/*--------------------------------------------------------------*/ +/* FatFs module application interface */ + +FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */ +FRESULT f_close (FIL* fp); /* Close an open file object */ +FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */ +FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */ +FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */ +FRESULT f_truncate (FIL* fp); /* Truncate the file */ +FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */ +FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */ +FRESULT f_closedir (DIR* dp); /* Close an open directory */ +FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */ +FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */ +FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */ +FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */ +FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */ +FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */ +FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */ +FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */ +FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */ +FRESULT f_chdir (const TCHAR* path); /* Change current directory */ +FRESULT f_chdrive (const TCHAR* path); /* Change current drive */ +FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */ +FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */ +FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */ +FRESULT f_setlabel (const TCHAR* label); /* Set volume label */ +FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */ +FRESULT f_expand (FIL* fp, FSIZE_t fsz, BYTE opt); /* Allocate a contiguous block to the file */ +FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */ +FRESULT f_mkfs (const TCHAR* path, const MKFS_PARM* opt, void* work, UINT len); /* Create a FAT volume */ +FRESULT f_fdisk (BYTE pdrv, const LBA_t ptbl[], void* work); /* Divide a physical drive into some partitions */ +FRESULT f_setcp (WORD cp); /* Set current code page */ +int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */ +int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */ +int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */ +TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */ + +#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize)) +#define f_error(fp) ((fp)->err) +#define f_tell(fp) ((fp)->fptr) +#define f_size(fp) ((fp)->obj.objsize) +#define f_rewind(fp) f_lseek((fp), 0) +#define f_rewinddir(dp) f_readdir((dp), 0) +#define f_rmdir(path) f_unlink(path) +#define f_unmount(path) f_mount(0, path, 0) + + + + +/*--------------------------------------------------------------*/ +/* Additional user defined functions */ + +/* RTC function */ +#if !FF_FS_READONLY && !FF_FS_NORTC +DWORD get_fattime (void); +#endif + +/* LFN support functions */ +#if FF_USE_LFN >= 1 /* Code conversion (defined in unicode.c) */ +WCHAR ff_oem2uni (WCHAR oem, WORD cp); /* OEM code to Unicode conversion */ +WCHAR ff_uni2oem (DWORD uni, WORD cp); /* Unicode to OEM code conversion */ +DWORD ff_wtoupper (DWORD uni); /* Unicode upper-case conversion */ +#endif +#if FF_USE_LFN == 3 /* Dynamic memory allocation */ +void* ff_memalloc (UINT msize); /* Allocate memory block */ +void ff_memfree (void* mblock); /* Free memory block */ +#endif + +/* Sync functions */ +#if FF_FS_REENTRANT +int ff_cre_syncobj (BYTE vol, FF_SYNC_t* sobj); /* Create a sync object */ +int ff_req_grant (FF_SYNC_t sobj); /* Lock sync object */ +void ff_rel_grant (FF_SYNC_t sobj); /* Unlock sync object */ +int ff_del_syncobj (FF_SYNC_t sobj); /* Delete a sync object */ +#endif + + + + +/*--------------------------------------------------------------*/ +/* Flags and offset address */ + + +/* File access mode and open method flags (3rd argument of f_open) */ +#define FA_READ 0x01 +#define FA_WRITE 0x02 +#define FA_OPEN_EXISTING 0x00 +#define FA_CREATE_NEW 0x04 +#define FA_CREATE_ALWAYS 0x08 +#define FA_OPEN_ALWAYS 0x10 +#define FA_OPEN_APPEND 0x30 + +/* Fast seek controls (2nd argument of f_lseek) */ +#define CREATE_LINKMAP ((FSIZE_t)0 - 1) + +/* Format options (2nd argument of f_mkfs) */ +#define FM_FAT 0x01 +#define FM_FAT32 0x02 +#define FM_EXFAT 0x04 +#define FM_ANY 0x07 +#define FM_SFD 0x08 + +/* Filesystem type (FATFS.fs_type) */ +#define FS_FAT12 1 +#define FS_FAT16 2 +#define FS_FAT32 3 +#define FS_EXFAT 4 + +/* File attribute bits for directory entry (FILINFO.fattrib) */ +#define AM_RDO 0x01 /* Read only */ +#define AM_HID 0x02 /* Hidden */ +#define AM_SYS 0x04 /* System */ +#define AM_DIR 0x10 /* Directory */ +#define AM_ARC 0x20 /* Archive */ + + +#ifdef __cplusplus +} +#endif + +#endif /* FF_DEFINED */ diff --git a/lib-hal/ff14b/source/ffconf.h b/lib-hal/ff14b/source/ffconf.h new file mode 100755 index 00000000..4104abf2 --- /dev/null +++ b/lib-hal/ff14b/source/ffconf.h @@ -0,0 +1,308 @@ +/*---------------------------------------------------------------------------/ +/ FatFs Functional Configurations +/---------------------------------------------------------------------------*/ + +#define FFCONF_DEF 86631 /* Revision ID */ + +/*---------------------------------------------------------------------------/ +/ Function Configurations +/---------------------------------------------------------------------------*/ + +#if defined (CONFIG_FS_ENABLE_WRITE) +# define FF_FS_READONLY 0 +#else +# define FF_FS_READONLY 1 +#endif +/* This option switches read-only configuration. (0:Read/Write or 1:Read-only) +/ Read-only configuration removes writing API functions, f_write(), f_sync(), +/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree() +/ and optional writing functions as well. */ + + +#define FF_FS_MINIMIZE 0 +/* This option defines minimization level to remove some basic API functions. +/ +/ 0: Basic functions are fully enabled. +/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename() +/ are removed. +/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. +/ 3: f_lseek() function is removed in addition to 2. */ + + +#define FF_USE_FIND 0 +/* This option switches filtered directory read functions, f_findfirst() and +/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */ + + +#define FF_USE_MKFS 0 +/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */ + + +#define FF_USE_FASTSEEK 0 +/* This option switches fast seek function. (0:Disable or 1:Enable) */ + + +#define FF_USE_EXPAND 0 +/* This option switches f_expand function. (0:Disable or 1:Enable) */ + + +#define FF_USE_CHMOD 0 +/* This option switches attribute manipulation functions, f_chmod() and f_utime(). +/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */ + + +#define FF_USE_LABEL 0 +/* This option switches volume label functions, f_getlabel() and f_setlabel(). +/ (0:Disable or 1:Enable) */ + + +#define FF_USE_FORWARD 0 +/* This option switches f_forward() function. (0:Disable or 1:Enable) */ + + +#define FF_USE_STRFUNC 2 +#define FF_PRINT_LLI 0 +#define FF_PRINT_FLOAT 0 +#define FF_STRF_ENCODE 0 +/* FF_USE_STRFUNC switches string functions, f_gets(), f_putc(), f_puts() and +/ f_printf(). +/ +/ 0: Disable. FF_PRINT_LLI, FF_PRINT_FLOAT and FF_STRF_ENCODE have no effect. +/ 1: Enable without LF-CRLF conversion. +/ 2: Enable with LF-CRLF conversion. +/ +/ FF_PRINT_LLI = 1 makes f_printf() support long long argument and FF_PRINT_FLOAT = 1/2 + makes f_printf() support floating point argument. These features want C99 or later. +/ When FF_LFN_UNICODE >= 1 with LFN enabled, string functions convert the character +/ encoding in it. FF_STRF_ENCODE selects assumption of character encoding ON THE FILE +/ to be read/written via those functions. +/ +/ 0: ANSI/OEM in current CP +/ 1: Unicode in UTF-16LE +/ 2: Unicode in UTF-16BE +/ 3: Unicode in UTF-8 +*/ + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/---------------------------------------------------------------------------*/ + +#define FF_CODE_PAGE 850 +/* This option specifies the OEM code page to be used on the target system. +/ Incorrect code page setting can cause a file open failure. +/ +/ 437 - U.S. +/ 720 - Arabic +/ 737 - Greek +/ 771 - KBL +/ 775 - Baltic +/ 850 - Latin 1 +/ 852 - Latin 2 +/ 855 - Cyrillic +/ 857 - Turkish +/ 860 - Portuguese +/ 861 - Icelandic +/ 862 - Hebrew +/ 863 - Canadian French +/ 864 - Arabic +/ 865 - Nordic +/ 866 - Russian +/ 869 - Greek 2 +/ 932 - Japanese (DBCS) +/ 936 - Simplified Chinese (DBCS) +/ 949 - Korean (DBCS) +/ 950 - Traditional Chinese (DBCS) +/ 0 - Include all code pages above and configured by f_setcp() +*/ + + +#define FF_USE_LFN 1 +#define FF_MAX_LFN 255 +/* The FF_USE_LFN switches the support for LFN (long file name). +/ +/ 0: Disable LFN. FF_MAX_LFN has no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ To enable the LFN, ffunicode.c needs to be added to the project. The LFN function +/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and +/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled. +/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can +/ be in range of 12 to 255. It is recommended to be set it 255 to fully support LFN +/ specification. +/ When use stack for the working buffer, take care on stack overflow. When use heap +/ memory for the working buffer, memory management functions, ff_memalloc() and +/ ff_memfree() exemplified in ffsystem.c, need to be added to the project. */ + + +#define FF_LFN_UNICODE 0 +/* This option switches the character encoding on the API when LFN is enabled. +/ +/ 0: ANSI/OEM in current CP (TCHAR = char) +/ 1: Unicode in UTF-16 (TCHAR = WCHAR) +/ 2: Unicode in UTF-8 (TCHAR = char) +/ 3: Unicode in UTF-32 (TCHAR = DWORD) +/ +/ Also behavior of string I/O functions will be affected by this option. +/ When LFN is not enabled, this option has no effect. */ + + +#define FF_LFN_BUF 255 +#define FF_SFN_BUF 12 +/* This set of options defines size of file name members in the FILINFO structure +/ which is used to read out directory items. These values should be suffcient for +/ the file names to read. The maximum possible length of the read file name depends +/ on character encoding. When LFN is not enabled, these options have no effect. */ + + +#define FF_FS_RPATH 0 +/* This option configures support for relative path. +/ +/ 0: Disable relative path and remove related functions. +/ 1: Enable relative path. f_chdir() and f_chdrive() are available. +/ 2: f_getcwd() function is available in addition to 1. +*/ + + +/*---------------------------------------------------------------------------/ +/ Drive/Volume Configurations +/---------------------------------------------------------------------------*/ + +#define FF_VOLUMES 1 +/* Number of volumes (logical drives) to be used. (1-10) */ + + +#define FF_STR_VOLUME_ID 0 +#define FF_VOLUME_STRS "RAM","NAND","CF","SD","SD2","USB","USB2","USB3" +/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings. +/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive +/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each +/ logical drives. Number of items must not be less than FF_VOLUMES. Valid +/ characters for the volume ID strings are A-Z, a-z and 0-9, however, they are +/ compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is +/ not defined, a user defined volume string table needs to be defined as: +/ +/ const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",... +*/ + + +#define FF_MULTI_PARTITION 0 +/* This option switches support for multiple volumes on the physical drive. +/ By default (0), each logical drive number is bound to the same physical drive +/ number and only an FAT volume found on the physical drive will be mounted. +/ When this function is enabled (1), each logical drive number can be bound to +/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk() +/ funciton will be available. */ + + +#define FF_MIN_SS 512 +#define FF_MAX_SS 512 +/* This set of options configures the range of sector size to be supported. (512, +/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and +/ harddisk, but a larger value may be required for on-board flash memory and some +/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured +/ for variable sector size mode and disk_ioctl() function needs to implement +/ GET_SECTOR_SIZE command. */ + + +#define FF_LBA64 0 +/* This option switches support for 64-bit LBA. (0:Disable or 1:Enable) +/ To enable the 64-bit LBA, also exFAT needs to be enabled. (FF_FS_EXFAT == 1) */ + + +#define FF_MIN_GPT 0x10000000 +/* Minimum number of sectors to switch GPT as partitioning format in f_mkfs and +/ f_fdisk function. 0x100000000 max. This option has no effect when FF_LBA64 == 0. */ + + +#define FF_USE_TRIM 0 +/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable) +/ To enable Trim function, also CTRL_TRIM command should be implemented to the +/ disk_ioctl() function. */ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/---------------------------------------------------------------------------*/ + +#define FF_FS_TINY 0 +/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny) +/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes. +/ Instead of private sector buffer eliminated from the file object, common sector +/ buffer in the filesystem object (FATFS) is used for the file data transfer. */ + +#if defined (SD_EXFAT_SUPPORT) +# define FF_FS_EXFAT 1 +#else +# define FF_FS_EXFAT 0 +#endif +/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable) +/ To enable exFAT, also LFN needs to be enabled. (FF_USE_LFN >= 1) +/ Note that enabling exFAT discards ANSI C (C89) compatibility. */ + + +#define FF_FS_NORTC 0 +#define FF_NORTC_MON _TIME_STAMP_MONTH_ +#define FF_NORTC_MDAY _TIME_STAMP_DAY_ +#define FF_NORTC_YEAR _TIME_STAMP_YEAR_ +/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have +/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable +/ the timestamp function. Every object modified by FatFs will have a fixed timestamp +/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time. +/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be +/ added to the project to read current time form real-time clock. FF_NORTC_MON, +/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect. +/ These options have no effect in read-only configuration (FF_FS_READONLY = 1). */ + + +#define FF_FS_NOFSINFO 0 +/* If you need to know correct free space on the FAT32 volume, set bit 0 of this +/ option, and f_getfree() function at first time after volume mount will force +/ a full FAT scan. Bit 1 controls the use of last allocated cluster number. +/ +/ bit0=0: Use free cluster count in the FSINFO if available. +/ bit0=1: Do not trust free cluster count in the FSINFO. +/ bit1=0: Use last allocated cluster number in the FSINFO if available. +/ bit1=1: Do not trust last allocated cluster number in the FSINFO. +*/ + + +#define FF_FS_LOCK 0 +/* The option FF_FS_LOCK switches file lock function to control duplicated file open +/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY +/ is 1. +/ +/ 0: Disable file lock function. To avoid volume corruption, application program +/ should avoid illegal open, remove and rename to the open objects. +/ >0: Enable file lock function. The value defines how many files/sub-directories +/ can be opened simultaneously under file lock control. Note that the file +/ lock control is independent of re-entrancy. */ + + +/* #include // O/S definitions */ +#define FF_FS_REENTRANT 0 +#define FF_FS_TIMEOUT 1000 +#define FF_SYNC_t HANDLE +/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs +/ module itself. Note that regardless of this option, file access to different +/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs() +/ and f_fdisk() function, are always not re-entrant. Only file/directory access +/ to the same volume is under control of this function. +/ +/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect. +/ 1: Enable re-entrancy. Also user provided synchronization handlers, +/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj() +/ function, must be added to the project. Samples are available in +/ option/syscall.c. +/ +/ The FF_FS_TIMEOUT defines timeout period in unit of time tick. +/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*, +/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be +/ included somewhere in the scope of ff.h. */ + + + +/*--- End of configuration options ---*/ diff --git a/lib-hal/ff14b/source/ffsystem.c b/lib-hal/ff14b/source/ffsystem.c new file mode 100755 index 00000000..ad5d7377 --- /dev/null +++ b/lib-hal/ff14b/source/ffsystem.c @@ -0,0 +1,170 @@ +/*------------------------------------------------------------------------*/ +/* Sample Code of OS Dependent Functions for FatFs */ +/* (C)ChaN, 2018 */ +/*------------------------------------------------------------------------*/ + + +#include "ff.h" + + +#if FF_USE_LFN == 3 /* Dynamic memory allocation */ + +/*------------------------------------------------------------------------*/ +/* Allocate a memory block */ +/*------------------------------------------------------------------------*/ + +void* ff_memalloc ( /* Returns pointer to the allocated memory block (null if not enough core) */ + UINT msize /* Number of bytes to allocate */ +) +{ + return malloc(msize); /* Allocate a new memory block with POSIX API */ +} + + +/*------------------------------------------------------------------------*/ +/* Free a memory block */ +/*------------------------------------------------------------------------*/ + +void ff_memfree ( + void* mblock /* Pointer to the memory block to free (nothing to do if null) */ +) +{ + free(mblock); /* Free the memory block with POSIX API */ +} + +#endif + + + +#if FF_FS_REENTRANT /* Mutal exclusion */ + +/*------------------------------------------------------------------------*/ +/* Create a Synchronization Object */ +/*------------------------------------------------------------------------*/ +/* This function is called in f_mount() function to create a new +/ synchronization object for the volume, such as semaphore and mutex. +/ When a 0 is returned, the f_mount() function fails with FR_INT_ERR. +*/ + +//const osMutexDef_t Mutex[FF_VOLUMES]; /* Table of CMSIS-RTOS mutex */ + + +int ff_cre_syncobj ( /* 1:Function succeeded, 0:Could not create the sync object */ + BYTE vol, /* Corresponding volume (logical drive number) */ + FF_SYNC_t* sobj /* Pointer to return the created sync object */ +) +{ + /* Win32 */ + *sobj = CreateMutex(NULL, FALSE, NULL); + return (int)(*sobj != INVALID_HANDLE_VALUE); + + /* uITRON */ +// T_CSEM csem = {TA_TPRI,1,1}; +// *sobj = acre_sem(&csem); +// return (int)(*sobj > 0); + + /* uC/OS-II */ +// OS_ERR err; +// *sobj = OSMutexCreate(0, &err); +// return (int)(err == OS_NO_ERR); + + /* FreeRTOS */ +// *sobj = xSemaphoreCreateMutex(); +// return (int)(*sobj != NULL); + + /* CMSIS-RTOS */ +// *sobj = osMutexCreate(&Mutex[vol]); +// return (int)(*sobj != NULL); +} + + +/*------------------------------------------------------------------------*/ +/* Delete a Synchronization Object */ +/*------------------------------------------------------------------------*/ +/* This function is called in f_mount() function to delete a synchronization +/ object that created with ff_cre_syncobj() function. When a 0 is returned, +/ the f_mount() function fails with FR_INT_ERR. +*/ + +int ff_del_syncobj ( /* 1:Function succeeded, 0:Could not delete due to an error */ + FF_SYNC_t sobj /* Sync object tied to the logical drive to be deleted */ +) +{ + /* Win32 */ + return (int)CloseHandle(sobj); + + /* uITRON */ +// return (int)(del_sem(sobj) == E_OK); + + /* uC/OS-II */ +// OS_ERR err; +// OSMutexDel(sobj, OS_DEL_ALWAYS, &err); +// return (int)(err == OS_NO_ERR); + + /* FreeRTOS */ +// vSemaphoreDelete(sobj); +// return 1; + + /* CMSIS-RTOS */ +// return (int)(osMutexDelete(sobj) == osOK); +} + + +/*------------------------------------------------------------------------*/ +/* Request Grant to Access the Volume */ +/*------------------------------------------------------------------------*/ +/* This function is called on entering file functions to lock the volume. +/ When a 0 is returned, the file function fails with FR_TIMEOUT. +*/ + +int ff_req_grant ( /* 1:Got a grant to access the volume, 0:Could not get a grant */ + FF_SYNC_t sobj /* Sync object to wait */ +) +{ + /* Win32 */ + return (int)(WaitForSingleObject(sobj, FF_FS_TIMEOUT) == WAIT_OBJECT_0); + + /* uITRON */ +// return (int)(wai_sem(sobj) == E_OK); + + /* uC/OS-II */ +// OS_ERR err; +// OSMutexPend(sobj, FF_FS_TIMEOUT, &err)); +// return (int)(err == OS_NO_ERR); + + /* FreeRTOS */ +// return (int)(xSemaphoreTake(sobj, FF_FS_TIMEOUT) == pdTRUE); + + /* CMSIS-RTOS */ +// return (int)(osMutexWait(sobj, FF_FS_TIMEOUT) == osOK); +} + + +/*------------------------------------------------------------------------*/ +/* Release Grant to Access the Volume */ +/*------------------------------------------------------------------------*/ +/* This function is called on leaving file functions to unlock the volume. +*/ + +void ff_rel_grant ( + FF_SYNC_t sobj /* Sync object to be signaled */ +) +{ + /* Win32 */ + ReleaseMutex(sobj); + + /* uITRON */ +// sig_sem(sobj); + + /* uC/OS-II */ +// OSMutexPost(sobj); + + /* FreeRTOS */ +// xSemaphoreGive(sobj); + + /* CMSIS-RTOS */ +// osMutexRelease(sobj); +} + +#endif + diff --git a/lib-hal/ff14b/source/ffunicode.c b/lib-hal/ff14b/source/ffunicode.c new file mode 100755 index 00000000..784a10e5 --- /dev/null +++ b/lib-hal/ff14b/source/ffunicode.c @@ -0,0 +1,15593 @@ +/*------------------------------------------------------------------------*/ +/* Unicode handling functions for FatFs R0.13+ */ +/*------------------------------------------------------------------------*/ +/* This module will occupy a huge memory in the .const section when the / +/ FatFs is configured for LFN with DBCS. If the system has any Unicode / +/ utilitiy for the code conversion, this module should be modified to use / +/ that function to avoid silly memory consumption. / +/-------------------------------------------------------------------------*/ +/* +/ Copyright (C) 2014, ChaN, all right reserved. +/ +/ FatFs module is an open source software. Redistribution and use of FatFs in +/ source and binary forms, with or without modification, are permitted provided +/ that the following condition is met: +/ +/ 1. Redistributions of source code must retain the above copyright notice, +/ this condition and the following disclaimer. +/ +/ This software is provided by the copyright holder and contributors "AS IS" +/ and any warranties related to this software are DISCLAIMED. +/ The copyright owner or contributors be NOT LIABLE for any damages caused +/ by use of this software. +*/ + + +#include "ff.h" + +#if FF_USE_LFN /* This module will be blanked if non-LFN configuration */ + +#define MERGE2(a, b) a ## b +#define CVTBL(tbl, cp) MERGE2(tbl, cp) + + +/*------------------------------------------------------------------------*/ +/* Code Conversion Tables */ +/*------------------------------------------------------------------------*/ + +#if FF_CODE_PAGE == 932 || FF_CODE_PAGE == 0 /* Japanese */ +static const WCHAR uni2oem932[] = { /* Unicode --> Shift_JIS pairs */ + 0x00A7, 0x8198, 0x00A8, 0x814E, 0x00B0, 0x818B, 0x00B1, 0x817D, 0x00B4, 0x814C, 0x00B6, 0x81F7, 0x00D7, 0x817E, 0x00F7, 0x8180, + 0x0391, 0x839F, 0x0392, 0x83A0, 0x0393, 0x83A1, 0x0394, 0x83A2, 0x0395, 0x83A3, 0x0396, 0x83A4, 0x0397, 0x83A5, 0x0398, 0x83A6, + 0x0399, 0x83A7, 0x039A, 0x83A8, 0x039B, 0x83A9, 0x039C, 0x83AA, 0x039D, 0x83AB, 0x039E, 0x83AC, 0x039F, 0x83AD, 0x03A0, 0x83AE, + 0x03A1, 0x83AF, 0x03A3, 0x83B0, 0x03A4, 0x83B1, 0x03A5, 0x83B2, 0x03A6, 0x83B3, 0x03A7, 0x83B4, 0x03A8, 0x83B5, 0x03A9, 0x83B6, + 0x03B1, 0x83BF, 0x03B2, 0x83C0, 0x03B3, 0x83C1, 0x03B4, 0x83C2, 0x03B5, 0x83C3, 0x03B6, 0x83C4, 0x03B7, 0x83C5, 0x03B8, 0x83C6, + 0x03B9, 0x83C7, 0x03BA, 0x83C8, 0x03BB, 0x83C9, 0x03BC, 0x83CA, 0x03BD, 0x83CB, 0x03BE, 0x83CC, 0x03BF, 0x83CD, 0x03C0, 0x83CE, + 0x03C1, 0x83CF, 0x03C3, 0x83D0, 0x03C4, 0x83D1, 0x03C5, 0x83D2, 0x03C6, 0x83D3, 0x03C7, 0x83D4, 0x03C8, 0x83D5, 0x03C9, 0x83D6, + 0x0401, 0x8446, 0x0410, 0x8440, 0x0411, 0x8441, 0x0412, 0x8442, 0x0413, 0x8443, 0x0414, 0x8444, 0x0415, 0x8445, 0x0416, 0x8447, + 0x0417, 0x8448, 0x0418, 0x8449, 0x0419, 0x844A, 0x041A, 0x844B, 0x041B, 0x844C, 0x041C, 0x844D, 0x041D, 0x844E, 0x041E, 0x844F, + 0x041F, 0x8450, 0x0420, 0x8451, 0x0421, 0x8452, 0x0422, 0x8453, 0x0423, 0x8454, 0x0424, 0x8455, 0x0425, 0x8456, 0x0426, 0x8457, + 0x0427, 0x8458, 0x0428, 0x8459, 0x0429, 0x845A, 0x042A, 0x845B, 0x042B, 0x845C, 0x042C, 0x845D, 0x042D, 0x845E, 0x042E, 0x845F, + 0x042F, 0x8460, 0x0430, 0x8470, 0x0431, 0x8471, 0x0432, 0x8472, 0x0433, 0x8473, 0x0434, 0x8474, 0x0435, 0x8475, 0x0436, 0x8477, + 0x0437, 0x8478, 0x0438, 0x8479, 0x0439, 0x847A, 0x043A, 0x847B, 0x043B, 0x847C, 0x043C, 0x847D, 0x043D, 0x847E, 0x043E, 0x8480, + 0x043F, 0x8481, 0x0440, 0x8482, 0x0441, 0x8483, 0x0442, 0x8484, 0x0443, 0x8485, 0x0444, 0x8486, 0x0445, 0x8487, 0x0446, 0x8488, + 0x0447, 0x8489, 0x0448, 0x848A, 0x0449, 0x848B, 0x044A, 0x848C, 0x044B, 0x848D, 0x044C, 0x848E, 0x044D, 0x848F, 0x044E, 0x8490, + 0x044F, 0x8491, 0x0451, 0x8476, 0x2010, 0x815D, 0x2015, 0x815C, 0x2018, 0x8165, 0x2019, 0x8166, 0x201C, 0x8167, 0x201D, 0x8168, + 0x2020, 0x81F5, 0x2021, 0x81F6, 0x2025, 0x8164, 0x2026, 0x8163, 0x2030, 0x81F1, 0x2032, 0x818C, 0x2033, 0x818D, 0x203B, 0x81A6, + 0x2103, 0x818E, 0x2116, 0x8782, 0x2121, 0x8784, 0x212B, 0x81F0, 0x2160, 0x8754, 0x2161, 0x8755, 0x2162, 0x8756, 0x2163, 0x8757, + 0x2164, 0x8758, 0x2165, 0x8759, 0x2166, 0x875A, 0x2167, 0x875B, 0x2168, 0x875C, 0x2169, 0x875D, 0x2170, 0xFA40, 0x2171, 0xFA41, + 0x2172, 0xFA42, 0x2173, 0xFA43, 0x2174, 0xFA44, 0x2175, 0xFA45, 0x2176, 0xFA46, 0x2177, 0xFA47, 0x2178, 0xFA48, 0x2179, 0xFA49, + 0x2190, 0x81A9, 0x2191, 0x81AA, 0x2192, 0x81A8, 0x2193, 0x81AB, 0x21D2, 0x81CB, 0x21D4, 0x81CC, 0x2200, 0x81CD, 0x2202, 0x81DD, + 0x2203, 0x81CE, 0x2207, 0x81DE, 0x2208, 0x81B8, 0x220B, 0x81B9, 0x2211, 0x8794, 0x221A, 0x81E3, 0x221D, 0x81E5, 0x221E, 0x8187, + 0x221F, 0x8798, 0x2220, 0x81DA, 0x2225, 0x8161, 0x2227, 0x81C8, 0x2228, 0x81C9, 0x2229, 0x81BF, 0x222A, 0x81BE, 0x222B, 0x81E7, + 0x222C, 0x81E8, 0x222E, 0x8793, 0x2234, 0x8188, 0x2235, 0x81E6, 0x223D, 0x81E4, 0x2252, 0x81E0, 0x2260, 0x8182, 0x2261, 0x81DF, + 0x2266, 0x8185, 0x2267, 0x8186, 0x226A, 0x81E1, 0x226B, 0x81E2, 0x2282, 0x81BC, 0x2283, 0x81BD, 0x2286, 0x81BA, 0x2287, 0x81BB, + 0x22A5, 0x81DB, 0x22BF, 0x8799, 0x2312, 0x81DC, 0x2460, 0x8740, 0x2461, 0x8741, 0x2462, 0x8742, 0x2463, 0x8743, 0x2464, 0x8744, + 0x2465, 0x8745, 0x2466, 0x8746, 0x2467, 0x8747, 0x2468, 0x8748, 0x2469, 0x8749, 0x246A, 0x874A, 0x246B, 0x874B, 0x246C, 0x874C, + 0x246D, 0x874D, 0x246E, 0x874E, 0x246F, 0x874F, 0x2470, 0x8750, 0x2471, 0x8751, 0x2472, 0x8752, 0x2473, 0x8753, 0x2500, 0x849F, + 0x2501, 0x84AA, 0x2502, 0x84A0, 0x2503, 0x84AB, 0x250C, 0x84A1, 0x250F, 0x84AC, 0x2510, 0x84A2, 0x2513, 0x84AD, 0x2514, 0x84A4, + 0x2517, 0x84AF, 0x2518, 0x84A3, 0x251B, 0x84AE, 0x251C, 0x84A5, 0x251D, 0x84BA, 0x2520, 0x84B5, 0x2523, 0x84B0, 0x2524, 0x84A7, + 0x2525, 0x84BC, 0x2528, 0x84B7, 0x252B, 0x84B2, 0x252C, 0x84A6, 0x252F, 0x84B6, 0x2530, 0x84BB, 0x2533, 0x84B1, 0x2534, 0x84A8, + 0x2537, 0x84B8, 0x2538, 0x84BD, 0x253B, 0x84B3, 0x253C, 0x84A9, 0x253F, 0x84B9, 0x2542, 0x84BE, 0x254B, 0x84B4, 0x25A0, 0x81A1, + 0x25A1, 0x81A0, 0x25B2, 0x81A3, 0x25B3, 0x81A2, 0x25BC, 0x81A5, 0x25BD, 0x81A4, 0x25C6, 0x819F, 0x25C7, 0x819E, 0x25CB, 0x819B, + 0x25CE, 0x819D, 0x25CF, 0x819C, 0x25EF, 0x81FC, 0x2605, 0x819A, 0x2606, 0x8199, 0x2640, 0x818A, 0x2642, 0x8189, 0x266A, 0x81F4, + 0x266D, 0x81F3, 0x266F, 0x81F2, 0x3000, 0x8140, 0x3001, 0x8141, 0x3002, 0x8142, 0x3003, 0x8156, 0x3005, 0x8158, 0x3006, 0x8159, + 0x3007, 0x815A, 0x3008, 0x8171, 0x3009, 0x8172, 0x300A, 0x8173, 0x300B, 0x8174, 0x300C, 0x8175, 0x300D, 0x8176, 0x300E, 0x8177, + 0x300F, 0x8178, 0x3010, 0x8179, 0x3011, 0x817A, 0x3012, 0x81A7, 0x3013, 0x81AC, 0x3014, 0x816B, 0x3015, 0x816C, 0x301D, 0x8780, + 0x301F, 0x8781, 0x3041, 0x829F, 0x3042, 0x82A0, 0x3043, 0x82A1, 0x3044, 0x82A2, 0x3045, 0x82A3, 0x3046, 0x82A4, 0x3047, 0x82A5, + 0x3048, 0x82A6, 0x3049, 0x82A7, 0x304A, 0x82A8, 0x304B, 0x82A9, 0x304C, 0x82AA, 0x304D, 0x82AB, 0x304E, 0x82AC, 0x304F, 0x82AD, + 0x3050, 0x82AE, 0x3051, 0x82AF, 0x3052, 0x82B0, 0x3053, 0x82B1, 0x3054, 0x82B2, 0x3055, 0x82B3, 0x3056, 0x82B4, 0x3057, 0x82B5, + 0x3058, 0x82B6, 0x3059, 0x82B7, 0x305A, 0x82B8, 0x305B, 0x82B9, 0x305C, 0x82BA, 0x305D, 0x82BB, 0x305E, 0x82BC, 0x305F, 0x82BD, + 0x3060, 0x82BE, 0x3061, 0x82BF, 0x3062, 0x82C0, 0x3063, 0x82C1, 0x3064, 0x82C2, 0x3065, 0x82C3, 0x3066, 0x82C4, 0x3067, 0x82C5, + 0x3068, 0x82C6, 0x3069, 0x82C7, 0x306A, 0x82C8, 0x306B, 0x82C9, 0x306C, 0x82CA, 0x306D, 0x82CB, 0x306E, 0x82CC, 0x306F, 0x82CD, + 0x3070, 0x82CE, 0x3071, 0x82CF, 0x3072, 0x82D0, 0x3073, 0x82D1, 0x3074, 0x82D2, 0x3075, 0x82D3, 0x3076, 0x82D4, 0x3077, 0x82D5, + 0x3078, 0x82D6, 0x3079, 0x82D7, 0x307A, 0x82D8, 0x307B, 0x82D9, 0x307C, 0x82DA, 0x307D, 0x82DB, 0x307E, 0x82DC, 0x307F, 0x82DD, + 0x3080, 0x82DE, 0x3081, 0x82DF, 0x3082, 0x82E0, 0x3083, 0x82E1, 0x3084, 0x82E2, 0x3085, 0x82E3, 0x3086, 0x82E4, 0x3087, 0x82E5, + 0x3088, 0x82E6, 0x3089, 0x82E7, 0x308A, 0x82E8, 0x308B, 0x82E9, 0x308C, 0x82EA, 0x308D, 0x82EB, 0x308E, 0x82EC, 0x308F, 0x82ED, + 0x3090, 0x82EE, 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0xFFE5, 0x818F, 0, 0 +}; + +static const WCHAR oem2uni932[] = { /* Shift_JIS --> Unicode pairs */ + 0x00A1, 0xFF61, 0x00A2, 0xFF62, 0x00A3, 0xFF63, 0x00A4, 0xFF64, 0x00A5, 0xFF65, 0x00A6, 0xFF66, 0x00A7, 0xFF67, 0x00A8, 0xFF68, + 0x00A9, 0xFF69, 0x00AA, 0xFF6A, 0x00AB, 0xFF6B, 0x00AC, 0xFF6C, 0x00AD, 0xFF6D, 0x00AE, 0xFF6E, 0x00AF, 0xFF6F, 0x00B0, 0xFF70, + 0x00B1, 0xFF71, 0x00B2, 0xFF72, 0x00B3, 0xFF73, 0x00B4, 0xFF74, 0x00B5, 0xFF75, 0x00B6, 0xFF76, 0x00B7, 0xFF77, 0x00B8, 0xFF78, + 0x00B9, 0xFF79, 0x00BA, 0xFF7A, 0x00BB, 0xFF7B, 0x00BC, 0xFF7C, 0x00BD, 0xFF7D, 0x00BE, 0xFF7E, 0x00BF, 0xFF7F, 0x00C0, 0xFF80, + 0x00C1, 0xFF81, 0x00C2, 0xFF82, 0x00C3, 0xFF83, 0x00C4, 0xFF84, 0x00C5, 0xFF85, 0x00C6, 0xFF86, 0x00C7, 0xFF87, 0x00C8, 0xFF88, + 0x00C9, 0xFF89, 0x00CA, 0xFF8A, 0x00CB, 0xFF8B, 0x00CC, 0xFF8C, 0x00CD, 0xFF8D, 0x00CE, 0xFF8E, 0x00CF, 0xFF8F, 0x00D0, 0xFF90, + 0x00D1, 0xFF91, 0x00D2, 0xFF92, 0x00D3, 0xFF93, 0x00D4, 0xFF94, 0x00D5, 0xFF95, 0x00D6, 0xFF96, 0x00D7, 0xFF97, 0x00D8, 0xFF98, + 0x00D9, 0xFF99, 0x00DA, 0xFF9A, 0x00DB, 0xFF9B, 0x00DC, 0xFF9C, 0x00DD, 0xFF9D, 0x00DE, 0xFF9E, 0x00DF, 0xFF9F, 0x8140, 0x3000, + 0x8141, 0x3001, 0x8142, 0x3002, 0x8143, 0xFF0C, 0x8144, 0xFF0E, 0x8145, 0x30FB, 0x8146, 0xFF1A, 0x8147, 0xFF1B, 0x8148, 0xFF1F, + 0x8149, 0xFF01, 0x814A, 0x309B, 0x814B, 0x309C, 0x814C, 0x00B4, 0x814D, 0xFF40, 0x814E, 0x00A8, 0x814F, 0xFF3E, 0x8150, 0xFFE3, + 0x8151, 0xFF3F, 0x8152, 0x30FD, 0x8153, 0x30FE, 0x8154, 0x309D, 0x8155, 0x309E, 0x8156, 0x3003, 0x8157, 0x4EDD, 0x8158, 0x3005, + 0x8159, 0x3006, 0x815A, 0x3007, 0x815B, 0x30FC, 0x815C, 0x2015, 0x815D, 0x2010, 0x815E, 0xFF0F, 0x815F, 0xFF3C, 0x8160, 0xFF5E, + 0x8161, 0x2225, 0x8162, 0xFF5C, 0x8163, 0x2026, 0x8164, 0x2025, 0x8165, 0x2018, 0x8166, 0x2019, 0x8167, 0x201C, 0x8168, 0x201D, + 0x8169, 0xFF08, 0x816A, 0xFF09, 0x816B, 0x3014, 0x816C, 0x3015, 0x816D, 0xFF3B, 0x816E, 0xFF3D, 0x816F, 0xFF5B, 0x8170, 0xFF5D, + 0x8171, 0x3008, 0x8172, 0x3009, 0x8173, 0x300A, 0x8174, 0x300B, 0x8175, 0x300C, 0x8176, 0x300D, 0x8177, 0x300E, 0x8178, 0x300F, + 0x8179, 0x3010, 0x817A, 0x3011, 0x817B, 0xFF0B, 0x817C, 0xFF0D, 0x817D, 0x00B1, 0x817E, 0x00D7, 0x8180, 0x00F7, 0x8181, 0xFF1D, + 0x8182, 0x2260, 0x8183, 0xFF1C, 0x8184, 0xFF1E, 0x8185, 0x2266, 0x8186, 0x2267, 0x8187, 0x221E, 0x8188, 0x2234, 0x8189, 0x2642, + 0x818A, 0x2640, 0x818B, 0x00B0, 0x818C, 0x2032, 0x818D, 0x2033, 0x818E, 0x2103, 0x818F, 0xFFE5, 0x8190, 0xFF04, 0x8191, 0xFFE0, + 0x8192, 0xFFE1, 0x8193, 0xFF05, 0x8194, 0xFF03, 0x8195, 0xFF06, 0x8196, 0xFF0A, 0x8197, 0xFF20, 0x8198, 0x00A7, 0x8199, 0x2606, + 0x819A, 0x2605, 0x819B, 0x25CB, 0x819C, 0x25CF, 0x819D, 0x25CE, 0x819E, 0x25C7, 0x819F, 0x25C6, 0x81A0, 0x25A1, 0x81A1, 0x25A0, + 0x81A2, 0x25B3, 0x81A3, 0x25B2, 0x81A4, 0x25BD, 0x81A5, 0x25BC, 0x81A6, 0x203B, 0x81A7, 0x3012, 0x81A8, 0x2192, 0x81A9, 0x2190, + 0x81AA, 0x2191, 0x81AB, 0x2193, 0x81AC, 0x3013, 0x81B8, 0x2208, 0x81B9, 0x220B, 0x81BA, 0x2286, 0x81BB, 0x2287, 0x81BC, 0x2282, + 0x81BD, 0x2283, 0x81BE, 0x222A, 0x81BF, 0x2229, 0x81C8, 0x2227, 0x81C9, 0x2228, 0x81CA, 0xFFE2, 0x81CB, 0x21D2, 0x81CC, 0x21D4, + 0x81CD, 0x2200, 0x81CE, 0x2203, 0x81DA, 0x2220, 0x81DB, 0x22A5, 0x81DC, 0x2312, 0x81DD, 0x2202, 0x81DE, 0x2207, 0x81DF, 0x2261, + 0x81E0, 0x2252, 0x81E1, 0x226A, 0x81E2, 0x226B, 0x81E3, 0x221A, 0x81E4, 0x223D, 0x81E5, 0x221D, 0x81E6, 0x2235, 0x81E7, 0x222B, + 0x81E8, 0x222C, 0x81F0, 0x212B, 0x81F1, 0x2030, 0x81F2, 0x266F, 0x81F3, 0x266D, 0x81F4, 0x266A, 0x81F5, 0x2020, 0x81F6, 0x2021, + 0x81F7, 0x00B6, 0x81FC, 0x25EF, 0x824F, 0xFF10, 0x8250, 0xFF11, 0x8251, 0xFF12, 0x8252, 0xFF13, 0x8253, 0xFF14, 0x8254, 0xFF15, + 0x8255, 0xFF16, 0x8256, 0xFF17, 0x8257, 0xFF18, 0x8258, 0xFF19, 0x8260, 0xFF21, 0x8261, 0xFF22, 0x8262, 0xFF23, 0x8263, 0xFF24, + 0x8264, 0xFF25, 0x8265, 0xFF26, 0x8266, 0xFF27, 0x8267, 0xFF28, 0x8268, 0xFF29, 0x8269, 0xFF2A, 0x826A, 0xFF2B, 0x826B, 0xFF2C, + 0x826C, 0xFF2D, 0x826D, 0xFF2E, 0x826E, 0xFF2F, 0x826F, 0xFF30, 0x8270, 0xFF31, 0x8271, 0xFF32, 0x8272, 0xFF33, 0x8273, 0xFF34, + 0x8274, 0xFF35, 0x8275, 0xFF36, 0x8276, 0xFF37, 0x8277, 0xFF38, 0x8278, 0xFF39, 0x8279, 0xFF3A, 0x8281, 0xFF41, 0x8282, 0xFF42, + 0x8283, 0xFF43, 0x8284, 0xFF44, 0x8285, 0xFF45, 0x8286, 0xFF46, 0x8287, 0xFF47, 0x8288, 0xFF48, 0x8289, 0xFF49, 0x828A, 0xFF4A, + 0x828B, 0xFF4B, 0x828C, 0xFF4C, 0x828D, 0xFF4D, 0x828E, 0xFF4E, 0x828F, 0xFF4F, 0x8290, 0xFF50, 0x8291, 0xFF51, 0x8292, 0xFF52, + 0x8293, 0xFF53, 0x8294, 0xFF54, 0x8295, 0xFF55, 0x8296, 0xFF56, 0x8297, 0xFF57, 0x8298, 0xFF58, 0x8299, 0xFF59, 0x829A, 0xFF5A, + 0x829F, 0x3041, 0x82A0, 0x3042, 0x82A1, 0x3043, 0x82A2, 0x3044, 0x82A3, 0x3045, 0x82A4, 0x3046, 0x82A5, 0x3047, 0x82A6, 0x3048, + 0x82A7, 0x3049, 0x82A8, 0x304A, 0x82A9, 0x304B, 0x82AA, 0x304C, 0x82AB, 0x304D, 0x82AC, 0x304E, 0x82AD, 0x304F, 0x82AE, 0x3050, + 0x82AF, 0x3051, 0x82B0, 0x3052, 0x82B1, 0x3053, 0x82B2, 0x3054, 0x82B3, 0x3055, 0x82B4, 0x3056, 0x82B5, 0x3057, 0x82B6, 0x3058, + 0x82B7, 0x3059, 0x82B8, 0x305A, 0x82B9, 0x305B, 0x82BA, 0x305C, 0x82BB, 0x305D, 0x82BC, 0x305E, 0x82BD, 0x305F, 0x82BE, 0x3060, + 0x82BF, 0x3061, 0x82C0, 0x3062, 0x82C1, 0x3063, 0x82C2, 0x3064, 0x82C3, 0x3065, 0x82C4, 0x3066, 0x82C5, 0x3067, 0x82C6, 0x3068, + 0x82C7, 0x3069, 0x82C8, 0x306A, 0x82C9, 0x306B, 0x82CA, 0x306C, 0x82CB, 0x306D, 0x82CC, 0x306E, 0x82CD, 0x306F, 0x82CE, 0x3070, + 0x82CF, 0x3071, 0x82D0, 0x3072, 0x82D1, 0x3073, 0x82D2, 0x3074, 0x82D3, 0x3075, 0x82D4, 0x3076, 0x82D5, 0x3077, 0x82D6, 0x3078, + 0x82D7, 0x3079, 0x82D8, 0x307A, 0x82D9, 0x307B, 0x82DA, 0x307C, 0x82DB, 0x307D, 0x82DC, 0x307E, 0x82DD, 0x307F, 0x82DE, 0x3080, + 0x82DF, 0x3081, 0x82E0, 0x3082, 0x82E1, 0x3083, 0x82E2, 0x3084, 0x82E3, 0x3085, 0x82E4, 0x3086, 0x82E5, 0x3087, 0x82E6, 0x3088, + 0x82E7, 0x3089, 0x82E8, 0x308A, 0x82E9, 0x308B, 0x82EA, 0x308C, 0x82EB, 0x308D, 0x82EC, 0x308E, 0x82ED, 0x308F, 0x82EE, 0x3090, + 0x82EF, 0x3091, 0x82F0, 0x3092, 0x82F1, 0x3093, 0x8340, 0x30A1, 0x8341, 0x30A2, 0x8342, 0x30A3, 0x8343, 0x30A4, 0x8344, 0x30A5, + 0x8345, 0x30A6, 0x8346, 0x30A7, 0x8347, 0x30A8, 0x8348, 0x30A9, 0x8349, 0x30AA, 0x834A, 0x30AB, 0x834B, 0x30AC, 0x834C, 0x30AD, + 0x834D, 0x30AE, 0x834E, 0x30AF, 0x834F, 0x30B0, 0x8350, 0x30B1, 0x8351, 0x30B2, 0x8352, 0x30B3, 0x8353, 0x30B4, 0x8354, 0x30B5, + 0x8355, 0x30B6, 0x8356, 0x30B7, 0x8357, 0x30B8, 0x8358, 0x30B9, 0x8359, 0x30BA, 0x835A, 0x30BB, 0x835B, 0x30BC, 0x835C, 0x30BD, + 0x835D, 0x30BE, 0x835E, 0x30BF, 0x835F, 0x30C0, 0x8360, 0x30C1, 0x8361, 0x30C2, 0x8362, 0x30C3, 0x8363, 0x30C4, 0x8364, 0x30C5, + 0x8365, 0x30C6, 0x8366, 0x30C7, 0x8367, 0x30C8, 0x8368, 0x30C9, 0x8369, 0x30CA, 0x836A, 0x30CB, 0x836B, 0x30CC, 0x836C, 0x30CD, + 0x836D, 0x30CE, 0x836E, 0x30CF, 0x836F, 0x30D0, 0x8370, 0x30D1, 0x8371, 0x30D2, 0x8372, 0x30D3, 0x8373, 0x30D4, 0x8374, 0x30D5, + 0x8375, 0x30D6, 0x8376, 0x30D7, 0x8377, 0x30D8, 0x8378, 0x30D9, 0x8379, 0x30DA, 0x837A, 0x30DB, 0x837B, 0x30DC, 0x837C, 0x30DD, + 0x837D, 0x30DE, 0x837E, 0x30DF, 0x8380, 0x30E0, 0x8381, 0x30E1, 0x8382, 0x30E2, 0x8383, 0x30E3, 0x8384, 0x30E4, 0x8385, 0x30E5, + 0x8386, 0x30E6, 0x8387, 0x30E7, 0x8388, 0x30E8, 0x8389, 0x30E9, 0x838A, 0x30EA, 0x838B, 0x30EB, 0x838C, 0x30EC, 0x838D, 0x30ED, + 0x838E, 0x30EE, 0x838F, 0x30EF, 0x8390, 0x30F0, 0x8391, 0x30F1, 0x8392, 0x30F2, 0x8393, 0x30F3, 0x8394, 0x30F4, 0x8395, 0x30F5, + 0x8396, 0x30F6, 0x839F, 0x0391, 0x83A0, 0x0392, 0x83A1, 0x0393, 0x83A2, 0x0394, 0x83A3, 0x0395, 0x83A4, 0x0396, 0x83A5, 0x0397, + 0x83A6, 0x0398, 0x83A7, 0x0399, 0x83A8, 0x039A, 0x83A9, 0x039B, 0x83AA, 0x039C, 0x83AB, 0x039D, 0x83AC, 0x039E, 0x83AD, 0x039F, + 0x83AE, 0x03A0, 0x83AF, 0x03A1, 0x83B0, 0x03A3, 0x83B1, 0x03A4, 0x83B2, 0x03A5, 0x83B3, 0x03A6, 0x83B4, 0x03A7, 0x83B5, 0x03A8, + 0x83B6, 0x03A9, 0x83BF, 0x03B1, 0x83C0, 0x03B2, 0x83C1, 0x03B3, 0x83C2, 0x03B4, 0x83C3, 0x03B5, 0x83C4, 0x03B6, 0x83C5, 0x03B7, + 0x83C6, 0x03B8, 0x83C7, 0x03B9, 0x83C8, 0x03BA, 0x83C9, 0x03BB, 0x83CA, 0x03BC, 0x83CB, 0x03BD, 0x83CC, 0x03BE, 0x83CD, 0x03BF, + 0x83CE, 0x03C0, 0x83CF, 0x03C1, 0x83D0, 0x03C3, 0x83D1, 0x03C4, 0x83D2, 0x03C5, 0x83D3, 0x03C6, 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0x91DE, 0xFBBD, 0x91ED, 0xFBBE, 0x91EE, 0xFBBF, 0x91E4, 0xFBC0, 0x91E5, 0xFBC1, 0x9206, 0xFBC2, 0x9210, 0xFBC3, 0x920A, + 0xFBC4, 0x923A, 0xFBC5, 0x9240, 0xFBC6, 0x923C, 0xFBC7, 0x924E, 0xFBC8, 0x9259, 0xFBC9, 0x9251, 0xFBCA, 0x9239, 0xFBCB, 0x9267, + 0xFBCC, 0x92A7, 0xFBCD, 0x9277, 0xFBCE, 0x9278, 0xFBCF, 0x92E7, 0xFBD0, 0x92D7, 0xFBD1, 0x92D9, 0xFBD2, 0x92D0, 0xFBD3, 0xFA27, + 0xFBD4, 0x92D5, 0xFBD5, 0x92E0, 0xFBD6, 0x92D3, 0xFBD7, 0x9325, 0xFBD8, 0x9321, 0xFBD9, 0x92FB, 0xFBDA, 0xFA28, 0xFBDB, 0x931E, + 0xFBDC, 0x92FF, 0xFBDD, 0x931D, 0xFBDE, 0x9302, 0xFBDF, 0x9370, 0xFBE0, 0x9357, 0xFBE1, 0x93A4, 0xFBE2, 0x93C6, 0xFBE3, 0x93DE, + 0xFBE4, 0x93F8, 0xFBE5, 0x9431, 0xFBE6, 0x9445, 0xFBE7, 0x9448, 0xFBE8, 0x9592, 0xFBE9, 0xF9DC, 0xFBEA, 0xFA29, 0xFBEB, 0x969D, + 0xFBEC, 0x96AF, 0xFBED, 0x9733, 0xFBEE, 0x973B, 0xFBEF, 0x9743, 0xFBF0, 0x974D, 0xFBF1, 0x974F, 0xFBF2, 0x9751, 0xFBF3, 0x9755, + 0xFBF4, 0x9857, 0xFBF5, 0x9865, 0xFBF6, 0xFA2A, 0xFBF7, 0xFA2B, 0xFBF8, 0x9927, 0xFBF9, 0xFA2C, 0xFBFA, 0x999E, 0xFBFB, 0x9A4E, + 0xFBFC, 0x9AD9, 0xFC40, 0x9ADC, 0xFC41, 0x9B75, 0xFC42, 0x9B72, 0xFC43, 0x9B8F, 0xFC44, 0x9BB1, 0xFC45, 0x9BBB, 0xFC46, 0x9C00, + 0xFC47, 0x9D70, 0xFC48, 0x9D6B, 0xFC49, 0xFA2D, 0xFC4A, 0x9E19, 0xFC4B, 0x9ED1, 0, 0 +}; +#endif + +#if FF_CODE_PAGE == 936 || FF_CODE_PAGE == 0 /* Simplified Chinese */ +static const WCHAR uni2oem936[] = { /* Unicode --> GBK pairs */ + 0x00A4, 0xA1E8, 0x00A7, 0xA1EC, 0x00A8, 0xA1A7, 0x00B0, 0xA1E3, 0x00B1, 0xA1C0, 0x00B7, 0xA1A4, 0x00D7, 0xA1C1, 0x00E0, 0xA8A4, + 0x00E1, 0xA8A2, 0x00E8, 0xA8A8, 0x00E9, 0xA8A6, 0x00EA, 0xA8BA, 0x00EC, 0xA8AC, 0x00ED, 0xA8AA, 0x00F2, 0xA8B0, 0x00F3, 0xA8AE, + 0x00F7, 0xA1C2, 0x00F9, 0xA8B4, 0x00FA, 0xA8B2, 0x00FC, 0xA8B9, 0x0101, 0xA8A1, 0x0113, 0xA8A5, 0x011B, 0xA8A7, 0x012B, 0xA8A9, + 0x0144, 0xA8BD, 0x0148, 0xA8BE, 0x014D, 0xA8AD, 0x016B, 0xA8B1, 0x01CE, 0xA8A3, 0x01D0, 0xA8AB, 0x01D2, 0xA8AF, 0x01D4, 0xA8B3, + 0x01D6, 0xA8B5, 0x01D8, 0xA8B6, 0x01DA, 0xA8B7, 0x01DC, 0xA8B8, 0x0251, 0xA8BB, 0x0261, 0xA8C0, 0x02C7, 0xA1A6, 0x02C9, 0xA1A5, + 0x02CA, 0xA840, 0x02CB, 0xA841, 0x02D9, 0xA842, 0x0391, 0xA6A1, 0x0392, 0xA6A2, 0x0393, 0xA6A3, 0x0394, 0xA6A4, 0x0395, 0xA6A5, + 0x0396, 0xA6A6, 0x0397, 0xA6A7, 0x0398, 0xA6A8, 0x0399, 0xA6A9, 0x039A, 0xA6AA, 0x039B, 0xA6AB, 0x039C, 0xA6AC, 0x039D, 0xA6AD, + 0x039E, 0xA6AE, 0x039F, 0xA6AF, 0x03A0, 0xA6B0, 0x03A1, 0xA6B1, 0x03A3, 0xA6B2, 0x03A4, 0xA6B3, 0x03A5, 0xA6B4, 0x03A6, 0xA6B5, + 0x03A7, 0xA6B6, 0x03A8, 0xA6B7, 0x03A9, 0xA6B8, 0x03B1, 0xA6C1, 0x03B2, 0xA6C2, 0x03B3, 0xA6C3, 0x03B4, 0xA6C4, 0x03B5, 0xA6C5, + 0x03B6, 0xA6C6, 0x03B7, 0xA6C7, 0x03B8, 0xA6C8, 0x03B9, 0xA6C9, 0x03BA, 0xA6CA, 0x03BB, 0xA6CB, 0x03BC, 0xA6CC, 0x03BD, 0xA6CD, + 0x03BE, 0xA6CE, 0x03BF, 0xA6CF, 0x03C0, 0xA6D0, 0x03C1, 0xA6D1, 0x03C3, 0xA6D2, 0x03C4, 0xA6D3, 0x03C5, 0xA6D4, 0x03C6, 0xA6D5, + 0x03C7, 0xA6D6, 0x03C8, 0xA6D7, 0x03C9, 0xA6D8, 0x0401, 0xA7A7, 0x0410, 0xA7A1, 0x0411, 0xA7A2, 0x0412, 0xA7A3, 0x0413, 0xA7A4, + 0x0414, 0xA7A5, 0x0415, 0xA7A6, 0x0416, 0xA7A8, 0x0417, 0xA7A9, 0x0418, 0xA7AA, 0x0419, 0xA7AB, 0x041A, 0xA7AC, 0x041B, 0xA7AD, + 0x041C, 0xA7AE, 0x041D, 0xA7AF, 0x041E, 0xA7B0, 0x041F, 0xA7B1, 0x0420, 0xA7B2, 0x0421, 0xA7B3, 0x0422, 0xA7B4, 0x0423, 0xA7B5, + 0x0424, 0xA7B6, 0x0425, 0xA7B7, 0x0426, 0xA7B8, 0x0427, 0xA7B9, 0x0428, 0xA7BA, 0x0429, 0xA7BB, 0x042A, 0xA7BC, 0x042B, 0xA7BD, + 0x042C, 0xA7BE, 0x042D, 0xA7BF, 0x042E, 0xA7C0, 0x042F, 0xA7C1, 0x0430, 0xA7D1, 0x0431, 0xA7D2, 0x0432, 0xA7D3, 0x0433, 0xA7D4, + 0x0434, 0xA7D5, 0x0435, 0xA7D6, 0x0436, 0xA7D8, 0x0437, 0xA7D9, 0x0438, 0xA7DA, 0x0439, 0xA7DB, 0x043A, 0xA7DC, 0x043B, 0xA7DD, + 0x043C, 0xA7DE, 0x043D, 0xA7DF, 0x043E, 0xA7E0, 0x043F, 0xA7E1, 0x0440, 0xA7E2, 0x0441, 0xA7E3, 0x0442, 0xA7E4, 0x0443, 0xA7E5, + 0x0444, 0xA7E6, 0x0445, 0xA7E7, 0x0446, 0xA7E8, 0x0447, 0xA7E9, 0x0448, 0xA7EA, 0x0449, 0xA7EB, 0x044A, 0xA7EC, 0x044B, 0xA7ED, + 0x044C, 0xA7EE, 0x044D, 0xA7EF, 0x044E, 0xA7F0, 0x044F, 0xA7F1, 0x0451, 0xA7D7, 0x2010, 0xA95C, 0x2013, 0xA843, 0x2014, 0xA1AA, + 0x2015, 0xA844, 0x2016, 0xA1AC, 0x2018, 0xA1AE, 0x2019, 0xA1AF, 0x201C, 0xA1B0, 0x201D, 0xA1B1, 0x2025, 0xA845, 0x2026, 0xA1AD, + 0x2030, 0xA1EB, 0x2032, 0xA1E4, 0x2033, 0xA1E5, 0x2035, 0xA846, 0x203B, 0xA1F9, 0x20AC, 0x0080, 0x2103, 0xA1E6, 0x2105, 0xA847, + 0x2109, 0xA848, 0x2116, 0xA1ED, 0x2121, 0xA959, 0x2160, 0xA2F1, 0x2161, 0xA2F2, 0x2162, 0xA2F3, 0x2163, 0xA2F4, 0x2164, 0xA2F5, + 0x2165, 0xA2F6, 0x2166, 0xA2F7, 0x2167, 0xA2F8, 0x2168, 0xA2F9, 0x2169, 0xA2FA, 0x216A, 0xA2FB, 0x216B, 0xA2FC, 0x2170, 0xA2A1, + 0x2171, 0xA2A2, 0x2172, 0xA2A3, 0x2173, 0xA2A4, 0x2174, 0xA2A5, 0x2175, 0xA2A6, 0x2176, 0xA2A7, 0x2177, 0xA2A8, 0x2178, 0xA2A9, + 0x2179, 0xA2AA, 0x2190, 0xA1FB, 0x2191, 0xA1FC, 0x2192, 0xA1FA, 0x2193, 0xA1FD, 0x2196, 0xA849, 0x2197, 0xA84A, 0x2198, 0xA84B, + 0x2199, 0xA84C, 0x2208, 0xA1CA, 0x220F, 0xA1C7, 0x2211, 0xA1C6, 0x2215, 0xA84D, 0x221A, 0xA1CC, 0x221D, 0xA1D8, 0x221E, 0xA1DE, + 0x221F, 0xA84E, 0x2220, 0xA1CF, 0x2223, 0xA84F, 0x2225, 0xA1CE, 0x2227, 0xA1C4, 0x2228, 0xA1C5, 0x2229, 0xA1C9, 0x222A, 0xA1C8, + 0x222B, 0xA1D2, 0x222E, 0xA1D3, 0x2234, 0xA1E0, 0x2235, 0xA1DF, 0x2236, 0xA1C3, 0x2237, 0xA1CB, 0x223D, 0xA1D7, 0x2248, 0xA1D6, + 0x224C, 0xA1D5, 0x2252, 0xA850, 0x2260, 0xA1D9, 0x2261, 0xA1D4, 0x2264, 0xA1DC, 0x2265, 0xA1DD, 0x2266, 0xA851, 0x2267, 0xA852, + 0x226E, 0xA1DA, 0x226F, 0xA1DB, 0x2295, 0xA892, 0x2299, 0xA1D1, 0x22A5, 0xA1CD, 0x22BF, 0xA853, 0x2312, 0xA1D0, 0x2460, 0xA2D9, + 0x2461, 0xA2DA, 0x2462, 0xA2DB, 0x2463, 0xA2DC, 0x2464, 0xA2DD, 0x2465, 0xA2DE, 0x2466, 0xA2DF, 0x2467, 0xA2E0, 0x2468, 0xA2E1, + 0x2469, 0xA2E2, 0x2474, 0xA2C5, 0x2475, 0xA2C6, 0x2476, 0xA2C7, 0x2477, 0xA2C8, 0x2478, 0xA2C9, 0x2479, 0xA2CA, 0x247A, 0xA2CB, + 0x247B, 0xA2CC, 0x247C, 0xA2CD, 0x247D, 0xA2CE, 0x247E, 0xA2CF, 0x247F, 0xA2D0, 0x2480, 0xA2D1, 0x2481, 0xA2D2, 0x2482, 0xA2D3, + 0x2483, 0xA2D4, 0x2484, 0xA2D5, 0x2485, 0xA2D6, 0x2486, 0xA2D7, 0x2487, 0xA2D8, 0x2488, 0xA2B1, 0x2489, 0xA2B2, 0x248A, 0xA2B3, + 0x248B, 0xA2B4, 0x248C, 0xA2B5, 0x248D, 0xA2B6, 0x248E, 0xA2B7, 0x248F, 0xA2B8, 0x2490, 0xA2B9, 0x2491, 0xA2BA, 0x2492, 0xA2BB, + 0x2493, 0xA2BC, 0x2494, 0xA2BD, 0x2495, 0xA2BE, 0x2496, 0xA2BF, 0x2497, 0xA2C0, 0x2498, 0xA2C1, 0x2499, 0xA2C2, 0x249A, 0xA2C3, + 0x249B, 0xA2C4, 0x2500, 0xA9A4, 0x2501, 0xA9A5, 0x2502, 0xA9A6, 0x2503, 0xA9A7, 0x2504, 0xA9A8, 0x2505, 0xA9A9, 0x2506, 0xA9AA, + 0x2507, 0xA9AB, 0x2508, 0xA9AC, 0x2509, 0xA9AD, 0x250A, 0xA9AE, 0x250B, 0xA9AF, 0x250C, 0xA9B0, 0x250D, 0xA9B1, 0x250E, 0xA9B2, + 0x250F, 0xA9B3, 0x2510, 0xA9B4, 0x2511, 0xA9B5, 0x2512, 0xA9B6, 0x2513, 0xA9B7, 0x2514, 0xA9B8, 0x2515, 0xA9B9, 0x2516, 0xA9BA, + 0x2517, 0xA9BB, 0x2518, 0xA9BC, 0x2519, 0xA9BD, 0x251A, 0xA9BE, 0x251B, 0xA9BF, 0x251C, 0xA9C0, 0x251D, 0xA9C1, 0x251E, 0xA9C2, + 0x251F, 0xA9C3, 0x2520, 0xA9C4, 0x2521, 0xA9C5, 0x2522, 0xA9C6, 0x2523, 0xA9C7, 0x2524, 0xA9C8, 0x2525, 0xA9C9, 0x2526, 0xA9CA, + 0x2527, 0xA9CB, 0x2528, 0xA9CC, 0x2529, 0xA9CD, 0x252A, 0xA9CE, 0x252B, 0xA9CF, 0x252C, 0xA9D0, 0x252D, 0xA9D1, 0x252E, 0xA9D2, + 0x252F, 0xA9D3, 0x2530, 0xA9D4, 0x2531, 0xA9D5, 0x2532, 0xA9D6, 0x2533, 0xA9D7, 0x2534, 0xA9D8, 0x2535, 0xA9D9, 0x2536, 0xA9DA, + 0x2537, 0xA9DB, 0x2538, 0xA9DC, 0x2539, 0xA9DD, 0x253A, 0xA9DE, 0x253B, 0xA9DF, 0x253C, 0xA9E0, 0x253D, 0xA9E1, 0x253E, 0xA9E2, + 0x253F, 0xA9E3, 0x2540, 0xA9E4, 0x2541, 0xA9E5, 0x2542, 0xA9E6, 0x2543, 0xA9E7, 0x2544, 0xA9E8, 0x2545, 0xA9E9, 0x2546, 0xA9EA, + 0x2547, 0xA9EB, 0x2548, 0xA9EC, 0x2549, 0xA9ED, 0x254A, 0xA9EE, 0x254B, 0xA9EF, 0x2550, 0xA854, 0x2551, 0xA855, 0x2552, 0xA856, + 0x2553, 0xA857, 0x2554, 0xA858, 0x2555, 0xA859, 0x2556, 0xA85A, 0x2557, 0xA85B, 0x2558, 0xA85C, 0x2559, 0xA85D, 0x255A, 0xA85E, + 0x255B, 0xA85F, 0x255C, 0xA860, 0x255D, 0xA861, 0x255E, 0xA862, 0x255F, 0xA863, 0x2560, 0xA864, 0x2561, 0xA865, 0x2562, 0xA866, + 0x2563, 0xA867, 0x2564, 0xA868, 0x2565, 0xA869, 0x2566, 0xA86A, 0x2567, 0xA86B, 0x2568, 0xA86C, 0x2569, 0xA86D, 0x256A, 0xA86E, + 0x256B, 0xA86F, 0x256C, 0xA870, 0x256D, 0xA871, 0x256E, 0xA872, 0x256F, 0xA873, 0x2570, 0xA874, 0x2571, 0xA875, 0x2572, 0xA876, + 0x2573, 0xA877, 0x2581, 0xA878, 0x2582, 0xA879, 0x2583, 0xA87A, 0x2584, 0xA87B, 0x2585, 0xA87C, 0x2586, 0xA87D, 0x2587, 0xA87E, + 0x2588, 0xA880, 0x2589, 0xA881, 0x258A, 0xA882, 0x258B, 0xA883, 0x258C, 0xA884, 0x258D, 0xA885, 0x258E, 0xA886, 0x258F, 0xA887, + 0x2593, 0xA888, 0x2594, 0xA889, 0x2595, 0xA88A, 0x25A0, 0xA1F6, 0x25A1, 0xA1F5, 0x25B2, 0xA1F8, 0x25B3, 0xA1F7, 0x25BC, 0xA88B, + 0x25BD, 0xA88C, 0x25C6, 0xA1F4, 0x25C7, 0xA1F3, 0x25CB, 0xA1F0, 0x25CE, 0xA1F2, 0x25CF, 0xA1F1, 0x25E2, 0xA88D, 0x25E3, 0xA88E, + 0x25E4, 0xA88F, 0x25E5, 0xA890, 0x2605, 0xA1EF, 0x2606, 0xA1EE, 0x2609, 0xA891, 0x2640, 0xA1E2, 0x2642, 0xA1E1, 0x3000, 0xA1A1, + 0x3001, 0xA1A2, 0x3002, 0xA1A3, 0x3003, 0xA1A8, 0x3005, 0xA1A9, 0x3006, 0xA965, 0x3007, 0xA996, 0x3008, 0xA1B4, 0x3009, 0xA1B5, + 0x300A, 0xA1B6, 0x300B, 0xA1B7, 0x300C, 0xA1B8, 0x300D, 0xA1B9, 0x300E, 0xA1BA, 0x300F, 0xA1BB, 0x3010, 0xA1BE, 0x3011, 0xA1BF, + 0x3012, 0xA893, 0x3013, 0xA1FE, 0x3014, 0xA1B2, 0x3015, 0xA1B3, 0x3016, 0xA1BC, 0x3017, 0xA1BD, 0x301D, 0xA894, 0x301E, 0xA895, + 0x3021, 0xA940, 0x3022, 0xA941, 0x3023, 0xA942, 0x3024, 0xA943, 0x3025, 0xA944, 0x3026, 0xA945, 0x3027, 0xA946, 0x3028, 0xA947, + 0x3029, 0xA948, 0x3041, 0xA4A1, 0x3042, 0xA4A2, 0x3043, 0xA4A3, 0x3044, 0xA4A4, 0x3045, 0xA4A5, 0x3046, 0xA4A6, 0x3047, 0xA4A7, + 0x3048, 0xA4A8, 0x3049, 0xA4A9, 0x304A, 0xA4AA, 0x304B, 0xA4AB, 0x304C, 0xA4AC, 0x304D, 0xA4AD, 0x304E, 0xA4AE, 0x304F, 0xA4AF, + 0x3050, 0xA4B0, 0x3051, 0xA4B1, 0x3052, 0xA4B2, 0x3053, 0xA4B3, 0x3054, 0xA4B4, 0x3055, 0xA4B5, 0x3056, 0xA4B6, 0x3057, 0xA4B7, + 0x3058, 0xA4B8, 0x3059, 0xA4B9, 0x305A, 0xA4BA, 0x305B, 0xA4BB, 0x305C, 0xA4BC, 0x305D, 0xA4BD, 0x305E, 0xA4BE, 0x305F, 0xA4BF, + 0x3060, 0xA4C0, 0x3061, 0xA4C1, 0x3062, 0xA4C2, 0x3063, 0xA4C3, 0x3064, 0xA4C4, 0x3065, 0xA4C5, 0x3066, 0xA4C6, 0x3067, 0xA4C7, + 0x3068, 0xA4C8, 0x3069, 0xA4C9, 0x306A, 0xA4CA, 0x306B, 0xA4CB, 0x306C, 0xA4CC, 0x306D, 0xA4CD, 0x306E, 0xA4CE, 0x306F, 0xA4CF, + 0x3070, 0xA4D0, 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0xFE64, 0xA982, 0xFE65, 0xA983, 0xFE66, 0xA984, + 0xFE68, 0xA985, 0xFE69, 0xA986, 0xFE6A, 0xA987, 0xFE6B, 0xA988, 0xFF01, 0xA3A1, 0xFF02, 0xA3A2, 0xFF03, 0xA3A3, 0xFF04, 0xA1E7, + 0xFF05, 0xA3A5, 0xFF06, 0xA3A6, 0xFF07, 0xA3A7, 0xFF08, 0xA3A8, 0xFF09, 0xA3A9, 0xFF0A, 0xA3AA, 0xFF0B, 0xA3AB, 0xFF0C, 0xA3AC, + 0xFF0D, 0xA3AD, 0xFF0E, 0xA3AE, 0xFF0F, 0xA3AF, 0xFF10, 0xA3B0, 0xFF11, 0xA3B1, 0xFF12, 0xA3B2, 0xFF13, 0xA3B3, 0xFF14, 0xA3B4, + 0xFF15, 0xA3B5, 0xFF16, 0xA3B6, 0xFF17, 0xA3B7, 0xFF18, 0xA3B8, 0xFF19, 0xA3B9, 0xFF1A, 0xA3BA, 0xFF1B, 0xA3BB, 0xFF1C, 0xA3BC, + 0xFF1D, 0xA3BD, 0xFF1E, 0xA3BE, 0xFF1F, 0xA3BF, 0xFF20, 0xA3C0, 0xFF21, 0xA3C1, 0xFF22, 0xA3C2, 0xFF23, 0xA3C3, 0xFF24, 0xA3C4, + 0xFF25, 0xA3C5, 0xFF26, 0xA3C6, 0xFF27, 0xA3C7, 0xFF28, 0xA3C8, 0xFF29, 0xA3C9, 0xFF2A, 0xA3CA, 0xFF2B, 0xA3CB, 0xFF2C, 0xA3CC, + 0xFF2D, 0xA3CD, 0xFF2E, 0xA3CE, 0xFF2F, 0xA3CF, 0xFF30, 0xA3D0, 0xFF31, 0xA3D1, 0xFF32, 0xA3D2, 0xFF33, 0xA3D3, 0xFF34, 0xA3D4, + 0xFF35, 0xA3D5, 0xFF36, 0xA3D6, 0xFF37, 0xA3D7, 0xFF38, 0xA3D8, 0xFF39, 0xA3D9, 0xFF3A, 0xA3DA, 0xFF3B, 0xA3DB, 0xFF3C, 0xA3DC, + 0xFF3D, 0xA3DD, 0xFF3E, 0xA3DE, 0xFF3F, 0xA3DF, 0xFF40, 0xA3E0, 0xFF41, 0xA3E1, 0xFF42, 0xA3E2, 0xFF43, 0xA3E3, 0xFF44, 0xA3E4, + 0xFF45, 0xA3E5, 0xFF46, 0xA3E6, 0xFF47, 0xA3E7, 0xFF48, 0xA3E8, 0xFF49, 0xA3E9, 0xFF4A, 0xA3EA, 0xFF4B, 0xA3EB, 0xFF4C, 0xA3EC, + 0xFF4D, 0xA3ED, 0xFF4E, 0xA3EE, 0xFF4F, 0xA3EF, 0xFF50, 0xA3F0, 0xFF51, 0xA3F1, 0xFF52, 0xA3F2, 0xFF53, 0xA3F3, 0xFF54, 0xA3F4, + 0xFF55, 0xA3F5, 0xFF56, 0xA3F6, 0xFF57, 0xA3F7, 0xFF58, 0xA3F8, 0xFF59, 0xA3F9, 0xFF5A, 0xA3FA, 0xFF5B, 0xA3FB, 0xFF5C, 0xA3FC, + 0xFF5D, 0xA3FD, 0xFF5E, 0xA1AB, 0xFFE0, 0xA1E9, 0xFFE1, 0xA1EA, 0xFFE2, 0xA956, 0xFFE3, 0xA3FE, 0xFFE4, 0xA957, 0xFFE5, 0xA3A4, + 0, 0 +}; + +static const WCHAR oem2uni936[] = { /* GBK --> Unicode pairs */ + 0x0080, 0x20AC, 0x8140, 0x4E02, 0x8141, 0x4E04, 0x8142, 0x4E05, 0x8143, 0x4E06, 0x8144, 0x4E0F, 0x8145, 0x4E12, 0x8146, 0x4E17, + 0x8147, 0x4E1F, 0x8148, 0x4E20, 0x8149, 0x4E21, 0x814A, 0x4E23, 0x814B, 0x4E26, 0x814C, 0x4E29, 0x814D, 0x4E2E, 0x814E, 0x4E2F, + 0x814F, 0x4E31, 0x8150, 0x4E33, 0x8151, 0x4E35, 0x8152, 0x4E37, 0x8153, 0x4E3C, 0x8154, 0x4E40, 0x8155, 0x4E41, 0x8156, 0x4E42, + 0x8157, 0x4E44, 0x8158, 0x4E46, 0x8159, 0x4E4A, 0x815A, 0x4E51, 0x815B, 0x4E55, 0x815C, 0x4E57, 0x815D, 0x4E5A, 0x815E, 0x4E5B, + 0x815F, 0x4E62, 0x8160, 0x4E63, 0x8161, 0x4E64, 0x8162, 0x4E65, 0x8163, 0x4E67, 0x8164, 0x4E68, 0x8165, 0x4E6A, 0x8166, 0x4E6B, + 0x8167, 0x4E6C, 0x8168, 0x4E6D, 0x8169, 0x4E6E, 0x816A, 0x4E6F, 0x816B, 0x4E72, 0x816C, 0x4E74, 0x816D, 0x4E75, 0x816E, 0x4E76, + 0x816F, 0x4E77, 0x8170, 0x4E78, 0x8171, 0x4E79, 0x8172, 0x4E7A, 0x8173, 0x4E7B, 0x8174, 0x4E7C, 0x8175, 0x4E7D, 0x8176, 0x4E7F, + 0x8177, 0x4E80, 0x8178, 0x4E81, 0x8179, 0x4E82, 0x817A, 0x4E83, 0x817B, 0x4E84, 0x817C, 0x4E85, 0x817D, 0x4E87, 0x817E, 0x4E8A, + 0x8180, 0x4E90, 0x8181, 0x4E96, 0x8182, 0x4E97, 0x8183, 0x4E99, 0x8184, 0x4E9C, 0x8185, 0x4E9D, 0x8186, 0x4E9E, 0x8187, 0x4EA3, + 0x8188, 0x4EAA, 0x8189, 0x4EAF, 0x818A, 0x4EB0, 0x818B, 0x4EB1, 0x818C, 0x4EB4, 0x818D, 0x4EB6, 0x818E, 0x4EB7, 0x818F, 0x4EB8, + 0x8190, 0x4EB9, 0x8191, 0x4EBC, 0x8192, 0x4EBD, 0x8193, 0x4EBE, 0x8194, 0x4EC8, 0x8195, 0x4ECC, 0x8196, 0x4ECF, 0x8197, 0x4ED0, + 0x8198, 0x4ED2, 0x8199, 0x4EDA, 0x819A, 0x4EDB, 0x819B, 0x4EDC, 0x819C, 0x4EE0, 0x819D, 0x4EE2, 0x819E, 0x4EE6, 0x819F, 0x4EE7, + 0x81A0, 0x4EE9, 0x81A1, 0x4EED, 0x81A2, 0x4EEE, 0x81A3, 0x4EEF, 0x81A4, 0x4EF1, 0x81A5, 0x4EF4, 0x81A6, 0x4EF8, 0x81A7, 0x4EF9, + 0x81A8, 0x4EFA, 0x81A9, 0x4EFC, 0x81AA, 0x4EFE, 0x81AB, 0x4F00, 0x81AC, 0x4F02, 0x81AD, 0x4F03, 0x81AE, 0x4F04, 0x81AF, 0x4F05, + 0x81B0, 0x4F06, 0x81B1, 0x4F07, 0x81B2, 0x4F08, 0x81B3, 0x4F0B, 0x81B4, 0x4F0C, 0x81B5, 0x4F12, 0x81B6, 0x4F13, 0x81B7, 0x4F14, + 0x81B8, 0x4F15, 0x81B9, 0x4F16, 0x81BA, 0x4F1C, 0x81BB, 0x4F1D, 0x81BC, 0x4F21, 0x81BD, 0x4F23, 0x81BE, 0x4F28, 0x81BF, 0x4F29, + 0x81C0, 0x4F2C, 0x81C1, 0x4F2D, 0x81C2, 0x4F2E, 0x81C3, 0x4F31, 0x81C4, 0x4F33, 0x81C5, 0x4F35, 0x81C6, 0x4F37, 0x81C7, 0x4F39, + 0x81C8, 0x4F3B, 0x81C9, 0x4F3E, 0x81CA, 0x4F3F, 0x81CB, 0x4F40, 0x81CC, 0x4F41, 0x81CD, 0x4F42, 0x81CE, 0x4F44, 0x81CF, 0x4F45, + 0x81D0, 0x4F47, 0x81D1, 0x4F48, 0x81D2, 0x4F49, 0x81D3, 0x4F4A, 0x81D4, 0x4F4B, 0x81D5, 0x4F4C, 0x81D6, 0x4F52, 0x81D7, 0x4F54, + 0x81D8, 0x4F56, 0x81D9, 0x4F61, 0x81DA, 0x4F62, 0x81DB, 0x4F66, 0x81DC, 0x4F68, 0x81DD, 0x4F6A, 0x81DE, 0x4F6B, 0x81DF, 0x4F6D, + 0x81E0, 0x4F6E, 0x81E1, 0x4F71, 0x81E2, 0x4F72, 0x81E3, 0x4F75, 0x81E4, 0x4F77, 0x81E5, 0x4F78, 0x81E6, 0x4F79, 0x81E7, 0x4F7A, + 0x81E8, 0x4F7D, 0x81E9, 0x4F80, 0x81EA, 0x4F81, 0x81EB, 0x4F82, 0x81EC, 0x4F85, 0x81ED, 0x4F86, 0x81EE, 0x4F87, 0x81EF, 0x4F8A, + 0x81F0, 0x4F8C, 0x81F1, 0x4F8E, 0x81F2, 0x4F90, 0x81F3, 0x4F92, 0x81F4, 0x4F93, 0x81F5, 0x4F95, 0x81F6, 0x4F96, 0x81F7, 0x4F98, + 0x81F8, 0x4F99, 0x81F9, 0x4F9A, 0x81FA, 0x4F9C, 0x81FB, 0x4F9E, 0x81FC, 0x4F9F, 0x81FD, 0x4FA1, 0x81FE, 0x4FA2, 0x8240, 0x4FA4, + 0x8241, 0x4FAB, 0x8242, 0x4FAD, 0x8243, 0x4FB0, 0x8244, 0x4FB1, 0x8245, 0x4FB2, 0x8246, 0x4FB3, 0x8247, 0x4FB4, 0x8248, 0x4FB6, + 0x8249, 0x4FB7, 0x824A, 0x4FB8, 0x824B, 0x4FB9, 0x824C, 0x4FBA, 0x824D, 0x4FBB, 0x824E, 0x4FBC, 0x824F, 0x4FBD, 0x8250, 0x4FBE, + 0x8251, 0x4FC0, 0x8252, 0x4FC1, 0x8253, 0x4FC2, 0x8254, 0x4FC6, 0x8255, 0x4FC7, 0x8256, 0x4FC8, 0x8257, 0x4FC9, 0x8258, 0x4FCB, + 0x8259, 0x4FCC, 0x825A, 0x4FCD, 0x825B, 0x4FD2, 0x825C, 0x4FD3, 0x825D, 0x4FD4, 0x825E, 0x4FD5, 0x825F, 0x4FD6, 0x8260, 0x4FD9, + 0x8261, 0x4FDB, 0x8262, 0x4FE0, 0x8263, 0x4FE2, 0x8264, 0x4FE4, 0x8265, 0x4FE5, 0x8266, 0x4FE7, 0x8267, 0x4FEB, 0x8268, 0x4FEC, + 0x8269, 0x4FF0, 0x826A, 0x4FF2, 0x826B, 0x4FF4, 0x826C, 0x4FF5, 0x826D, 0x4FF6, 0x826E, 0x4FF7, 0x826F, 0x4FF9, 0x8270, 0x4FFB, + 0x8271, 0x4FFC, 0x8272, 0x4FFD, 0x8273, 0x4FFF, 0x8274, 0x5000, 0x8275, 0x5001, 0x8276, 0x5002, 0x8277, 0x5003, 0x8278, 0x5004, + 0x8279, 0x5005, 0x827A, 0x5006, 0x827B, 0x5007, 0x827C, 0x5008, 0x827D, 0x5009, 0x827E, 0x500A, 0x8280, 0x500B, 0x8281, 0x500E, + 0x8282, 0x5010, 0x8283, 0x5011, 0x8284, 0x5013, 0x8285, 0x5015, 0x8286, 0x5016, 0x8287, 0x5017, 0x8288, 0x501B, 0x8289, 0x501D, + 0x828A, 0x501E, 0x828B, 0x5020, 0x828C, 0x5022, 0x828D, 0x5023, 0x828E, 0x5024, 0x828F, 0x5027, 0x8290, 0x502B, 0x8291, 0x502F, + 0x8292, 0x5030, 0x8293, 0x5031, 0x8294, 0x5032, 0x8295, 0x5033, 0x8296, 0x5034, 0x8297, 0x5035, 0x8298, 0x5036, 0x8299, 0x5037, + 0x829A, 0x5038, 0x829B, 0x5039, 0x829C, 0x503B, 0x829D, 0x503D, 0x829E, 0x503F, 0x829F, 0x5040, 0x82A0, 0x5041, 0x82A1, 0x5042, + 0x82A2, 0x5044, 0x82A3, 0x5045, 0x82A4, 0x5046, 0x82A5, 0x5049, 0x82A6, 0x504A, 0x82A7, 0x504B, 0x82A8, 0x504D, 0x82A9, 0x5050, + 0x82AA, 0x5051, 0x82AB, 0x5052, 0x82AC, 0x5053, 0x82AD, 0x5054, 0x82AE, 0x5056, 0x82AF, 0x5057, 0x82B0, 0x5058, 0x82B1, 0x5059, + 0x82B2, 0x505B, 0x82B3, 0x505D, 0x82B4, 0x505E, 0x82B5, 0x505F, 0x82B6, 0x5060, 0x82B7, 0x5061, 0x82B8, 0x5062, 0x82B9, 0x5063, + 0x82BA, 0x5064, 0x82BB, 0x5066, 0x82BC, 0x5067, 0x82BD, 0x5068, 0x82BE, 0x5069, 0x82BF, 0x506A, 0x82C0, 0x506B, 0x82C1, 0x506D, + 0x82C2, 0x506E, 0x82C3, 0x506F, 0x82C4, 0x5070, 0x82C5, 0x5071, 0x82C6, 0x5072, 0x82C7, 0x5073, 0x82C8, 0x5074, 0x82C9, 0x5075, + 0x82CA, 0x5078, 0x82CB, 0x5079, 0x82CC, 0x507A, 0x82CD, 0x507C, 0x82CE, 0x507D, 0x82CF, 0x5081, 0x82D0, 0x5082, 0x82D1, 0x5083, + 0x82D2, 0x5084, 0x82D3, 0x5086, 0x82D4, 0x5087, 0x82D5, 0x5089, 0x82D6, 0x508A, 0x82D7, 0x508B, 0x82D8, 0x508C, 0x82D9, 0x508E, + 0x82DA, 0x508F, 0x82DB, 0x5090, 0x82DC, 0x5091, 0x82DD, 0x5092, 0x82DE, 0x5093, 0x82DF, 0x5094, 0x82E0, 0x5095, 0x82E1, 0x5096, + 0x82E2, 0x5097, 0x82E3, 0x5098, 0x82E4, 0x5099, 0x82E5, 0x509A, 0x82E6, 0x509B, 0x82E7, 0x509C, 0x82E8, 0x509D, 0x82E9, 0x509E, + 0x82EA, 0x509F, 0x82EB, 0x50A0, 0x82EC, 0x50A1, 0x82ED, 0x50A2, 0x82EE, 0x50A4, 0x82EF, 0x50A6, 0x82F0, 0x50AA, 0x82F1, 0x50AB, + 0x82F2, 0x50AD, 0x82F3, 0x50AE, 0x82F4, 0x50AF, 0x82F5, 0x50B0, 0x82F6, 0x50B1, 0x82F7, 0x50B3, 0x82F8, 0x50B4, 0x82F9, 0x50B5, + 0x82FA, 0x50B6, 0x82FB, 0x50B7, 0x82FC, 0x50B8, 0x82FD, 0x50B9, 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0x9EBA, 0xFC4E, 0x9EBC, 0xFC4F, 0x9EBF, + 0xFC50, 0x9EC0, 0xFC51, 0x9EC1, 0xFC52, 0x9EC2, 0xFC53, 0x9EC3, 0xFC54, 0x9EC5, 0xFC55, 0x9EC6, 0xFC56, 0x9EC7, 0xFC57, 0x9EC8, + 0xFC58, 0x9ECA, 0xFC59, 0x9ECB, 0xFC5A, 0x9ECC, 0xFC5B, 0x9ED0, 0xFC5C, 0x9ED2, 0xFC5D, 0x9ED3, 0xFC5E, 0x9ED5, 0xFC5F, 0x9ED6, + 0xFC60, 0x9ED7, 0xFC61, 0x9ED9, 0xFC62, 0x9EDA, 0xFC63, 0x9EDE, 0xFC64, 0x9EE1, 0xFC65, 0x9EE3, 0xFC66, 0x9EE4, 0xFC67, 0x9EE6, + 0xFC68, 0x9EE8, 0xFC69, 0x9EEB, 0xFC6A, 0x9EEC, 0xFC6B, 0x9EED, 0xFC6C, 0x9EEE, 0xFC6D, 0x9EF0, 0xFC6E, 0x9EF1, 0xFC6F, 0x9EF2, + 0xFC70, 0x9EF3, 0xFC71, 0x9EF4, 0xFC72, 0x9EF5, 0xFC73, 0x9EF6, 0xFC74, 0x9EF7, 0xFC75, 0x9EF8, 0xFC76, 0x9EFA, 0xFC77, 0x9EFD, + 0xFC78, 0x9EFF, 0xFC79, 0x9F00, 0xFC7A, 0x9F01, 0xFC7B, 0x9F02, 0xFC7C, 0x9F03, 0xFC7D, 0x9F04, 0xFC7E, 0x9F05, 0xFC80, 0x9F06, + 0xFC81, 0x9F07, 0xFC82, 0x9F08, 0xFC83, 0x9F09, 0xFC84, 0x9F0A, 0xFC85, 0x9F0C, 0xFC86, 0x9F0F, 0xFC87, 0x9F11, 0xFC88, 0x9F12, + 0xFC89, 0x9F14, 0xFC8A, 0x9F15, 0xFC8B, 0x9F16, 0xFC8C, 0x9F18, 0xFC8D, 0x9F1A, 0xFC8E, 0x9F1B, 0xFC8F, 0x9F1C, 0xFC90, 0x9F1D, + 0xFC91, 0x9F1E, 0xFC92, 0x9F1F, 0xFC93, 0x9F21, 0xFC94, 0x9F23, 0xFC95, 0x9F24, 0xFC96, 0x9F25, 0xFC97, 0x9F26, 0xFC98, 0x9F27, + 0xFC99, 0x9F28, 0xFC9A, 0x9F29, 0xFC9B, 0x9F2A, 0xFC9C, 0x9F2B, 0xFC9D, 0x9F2D, 0xFC9E, 0x9F2E, 0xFC9F, 0x9F30, 0xFCA0, 0x9F31, + 0xFD40, 0x9F32, 0xFD41, 0x9F33, 0xFD42, 0x9F34, 0xFD43, 0x9F35, 0xFD44, 0x9F36, 0xFD45, 0x9F38, 0xFD46, 0x9F3A, 0xFD47, 0x9F3C, + 0xFD48, 0x9F3F, 0xFD49, 0x9F40, 0xFD4A, 0x9F41, 0xFD4B, 0x9F42, 0xFD4C, 0x9F43, 0xFD4D, 0x9F45, 0xFD4E, 0x9F46, 0xFD4F, 0x9F47, + 0xFD50, 0x9F48, 0xFD51, 0x9F49, 0xFD52, 0x9F4A, 0xFD53, 0x9F4B, 0xFD54, 0x9F4C, 0xFD55, 0x9F4D, 0xFD56, 0x9F4E, 0xFD57, 0x9F4F, + 0xFD58, 0x9F52, 0xFD59, 0x9F53, 0xFD5A, 0x9F54, 0xFD5B, 0x9F55, 0xFD5C, 0x9F56, 0xFD5D, 0x9F57, 0xFD5E, 0x9F58, 0xFD5F, 0x9F59, + 0xFD60, 0x9F5A, 0xFD61, 0x9F5B, 0xFD62, 0x9F5C, 0xFD63, 0x9F5D, 0xFD64, 0x9F5E, 0xFD65, 0x9F5F, 0xFD66, 0x9F60, 0xFD67, 0x9F61, + 0xFD68, 0x9F62, 0xFD69, 0x9F63, 0xFD6A, 0x9F64, 0xFD6B, 0x9F65, 0xFD6C, 0x9F66, 0xFD6D, 0x9F67, 0xFD6E, 0x9F68, 0xFD6F, 0x9F69, + 0xFD70, 0x9F6A, 0xFD71, 0x9F6B, 0xFD72, 0x9F6C, 0xFD73, 0x9F6D, 0xFD74, 0x9F6E, 0xFD75, 0x9F6F, 0xFD76, 0x9F70, 0xFD77, 0x9F71, + 0xFD78, 0x9F72, 0xFD79, 0x9F73, 0xFD7A, 0x9F74, 0xFD7B, 0x9F75, 0xFD7C, 0x9F76, 0xFD7D, 0x9F77, 0xFD7E, 0x9F78, 0xFD80, 0x9F79, + 0xFD81, 0x9F7A, 0xFD82, 0x9F7B, 0xFD83, 0x9F7C, 0xFD84, 0x9F7D, 0xFD85, 0x9F7E, 0xFD86, 0x9F81, 0xFD87, 0x9F82, 0xFD88, 0x9F8D, + 0xFD89, 0x9F8E, 0xFD8A, 0x9F8F, 0xFD8B, 0x9F90, 0xFD8C, 0x9F91, 0xFD8D, 0x9F92, 0xFD8E, 0x9F93, 0xFD8F, 0x9F94, 0xFD90, 0x9F95, + 0xFD91, 0x9F96, 0xFD92, 0x9F97, 0xFD93, 0x9F98, 0xFD94, 0x9F9C, 0xFD95, 0x9F9D, 0xFD96, 0x9F9E, 0xFD97, 0x9FA1, 0xFD98, 0x9FA2, + 0xFD99, 0x9FA3, 0xFD9A, 0x9FA4, 0xFD9B, 0x9FA5, 0xFD9C, 0xF92C, 0xFD9D, 0xF979, 0xFD9E, 0xF995, 0xFD9F, 0xF9E7, 0xFDA0, 0xF9F1, + 0xFE40, 0xFA0C, 0xFE41, 0xFA0D, 0xFE42, 0xFA0E, 0xFE43, 0xFA0F, 0xFE44, 0xFA11, 0xFE45, 0xFA13, 0xFE46, 0xFA14, 0xFE47, 0xFA18, + 0xFE48, 0xFA1F, 0xFE49, 0xFA20, 0xFE4A, 0xFA21, 0xFE4B, 0xFA23, 0xFE4C, 0xFA24, 0xFE4D, 0xFA27, 0xFE4E, 0xFA28, 0xFE4F, 0xFA29, + 0, 0 +}; +#endif + +#if FF_CODE_PAGE == 949 || FF_CODE_PAGE == 0 /* Korean */ +static const WCHAR uni2oem949[] = { /* Unicode --> Korean pairs */ + 0x00A1, 0xA2AE, 0x00A4, 0xA2B4, 0x00A7, 0xA1D7, 0x00A8, 0xA1A7, 0x00AA, 0xA8A3, 0x00AD, 0xA1A9, 0x00AE, 0xA2E7, 0x00B0, 0xA1C6, + 0x00B1, 0xA1BE, 0x00B2, 0xA9F7, 0x00B3, 0xA9F8, 0x00B4, 0xA2A5, 0x00B6, 0xA2D2, 0x00B7, 0xA1A4, 0x00B8, 0xA2AC, 0x00B9, 0xA9F6, + 0x00BA, 0xA8AC, 0x00BC, 0xA8F9, 0x00BD, 0xA8F6, 0x00BE, 0xA8FA, 0x00BF, 0xA2AF, 0x00C6, 0xA8A1, 0x00D0, 0xA8A2, 0x00D7, 0xA1BF, + 0x00D8, 0xA8AA, 0x00DE, 0xA8AD, 0x00DF, 0xA9AC, 0x00E6, 0xA9A1, 0x00F0, 0xA9A3, 0x00F7, 0xA1C0, 0x00F8, 0xA9AA, 0x00FE, 0xA9AD, + 0x0111, 0xA9A2, 0x0126, 0xA8A4, 0x0127, 0xA9A4, 0x0131, 0xA9A5, 0x0132, 0xA8A6, 0x0133, 0xA9A6, 0x0138, 0xA9A7, 0x013F, 0xA8A8, + 0x0140, 0xA9A8, 0x0141, 0xA8A9, 0x0142, 0xA9A9, 0x0149, 0xA9B0, 0x014A, 0xA8AF, 0x014B, 0xA9AF, 0x0152, 0xA8AB, 0x0153, 0xA9AB, + 0x0166, 0xA8AE, 0x0167, 0xA9AE, 0x02C7, 0xA2A7, 0x02D0, 0xA2B0, 0x02D8, 0xA2A8, 0x02D9, 0xA2AB, 0x02DA, 0xA2AA, 0x02DB, 0xA2AD, + 0x02DD, 0xA2A9, 0x0391, 0xA5C1, 0x0392, 0xA5C2, 0x0393, 0xA5C3, 0x0394, 0xA5C4, 0x0395, 0xA5C5, 0x0396, 0xA5C6, 0x0397, 0xA5C7, + 0x0398, 0xA5C8, 0x0399, 0xA5C9, 0x039A, 0xA5CA, 0x039B, 0xA5CB, 0x039C, 0xA5CC, 0x039D, 0xA5CD, 0x039E, 0xA5CE, 0x039F, 0xA5CF, + 0x03A0, 0xA5D0, 0x03A1, 0xA5D1, 0x03A3, 0xA5D2, 0x03A4, 0xA5D3, 0x03A5, 0xA5D4, 0x03A6, 0xA5D5, 0x03A7, 0xA5D6, 0x03A8, 0xA5D7, + 0x03A9, 0xA5D8, 0x03B1, 0xA5E1, 0x03B2, 0xA5E2, 0x03B3, 0xA5E3, 0x03B4, 0xA5E4, 0x03B5, 0xA5E5, 0x03B6, 0xA5E6, 0x03B7, 0xA5E7, + 0x03B8, 0xA5E8, 0x03B9, 0xA5E9, 0x03BA, 0xA5EA, 0x03BB, 0xA5EB, 0x03BC, 0xA5EC, 0x03BD, 0xA5ED, 0x03BE, 0xA5EE, 0x03BF, 0xA5EF, + 0x03C0, 0xA5F0, 0x03C1, 0xA5F1, 0x03C3, 0xA5F2, 0x03C4, 0xA5F3, 0x03C5, 0xA5F4, 0x03C6, 0xA5F5, 0x03C7, 0xA5F6, 0x03C8, 0xA5F7, + 0x03C9, 0xA5F8, 0x0401, 0xACA7, 0x0410, 0xACA1, 0x0411, 0xACA2, 0x0412, 0xACA3, 0x0413, 0xACA4, 0x0414, 0xACA5, 0x0415, 0xACA6, + 0x0416, 0xACA8, 0x0417, 0xACA9, 0x0418, 0xACAA, 0x0419, 0xACAB, 0x041A, 0xACAC, 0x041B, 0xACAD, 0x041C, 0xACAE, 0x041D, 0xACAF, + 0x041E, 0xACB0, 0x041F, 0xACB1, 0x0420, 0xACB2, 0x0421, 0xACB3, 0x0422, 0xACB4, 0x0423, 0xACB5, 0x0424, 0xACB6, 0x0425, 0xACB7, + 0x0426, 0xACB8, 0x0427, 0xACB9, 0x0428, 0xACBA, 0x0429, 0xACBB, 0x042A, 0xACBC, 0x042B, 0xACBD, 0x042C, 0xACBE, 0x042D, 0xACBF, + 0x042E, 0xACC0, 0x042F, 0xACC1, 0x0430, 0xACD1, 0x0431, 0xACD2, 0x0432, 0xACD3, 0x0433, 0xACD4, 0x0434, 0xACD5, 0x0435, 0xACD6, + 0x0436, 0xACD8, 0x0437, 0xACD9, 0x0438, 0xACDA, 0x0439, 0xACDB, 0x043A, 0xACDC, 0x043B, 0xACDD, 0x043C, 0xACDE, 0x043D, 0xACDF, + 0x043E, 0xACE0, 0x043F, 0xACE1, 0x0440, 0xACE2, 0x0441, 0xACE3, 0x0442, 0xACE4, 0x0443, 0xACE5, 0x0444, 0xACE6, 0x0445, 0xACE7, + 0x0446, 0xACE8, 0x0447, 0xACE9, 0x0448, 0xACEA, 0x0449, 0xACEB, 0x044A, 0xACEC, 0x044B, 0xACED, 0x044C, 0xACEE, 0x044D, 0xACEF, + 0x044E, 0xACF0, 0x044F, 0xACF1, 0x0451, 0xACD7, 0x2015, 0xA1AA, 0x2018, 0xA1AE, 0x2019, 0xA1AF, 0x201C, 0xA1B0, 0x201D, 0xA1B1, + 0x2020, 0xA2D3, 0x2021, 0xA2D4, 0x2025, 0xA1A5, 0x2026, 0xA1A6, 0x2030, 0xA2B6, 0x2032, 0xA1C7, 0x2033, 0xA1C8, 0x203B, 0xA1D8, + 0x2074, 0xA9F9, 0x207F, 0xA9FA, 0x2081, 0xA9FB, 0x2082, 0xA9FC, 0x2083, 0xA9FD, 0x2084, 0xA9FE, 0x20AC, 0xA2E6, 0x2103, 0xA1C9, + 0x2109, 0xA2B5, 0x2113, 0xA7A4, 0x2116, 0xA2E0, 0x2121, 0xA2E5, 0x2122, 0xA2E2, 0x2126, 0xA7D9, 0x212B, 0xA1CA, 0x2153, 0xA8F7, + 0x2154, 0xA8F8, 0x215B, 0xA8FB, 0x215C, 0xA8FC, 0x215D, 0xA8FD, 0x215E, 0xA8FE, 0x2160, 0xA5B0, 0x2161, 0xA5B1, 0x2162, 0xA5B2, + 0x2163, 0xA5B3, 0x2164, 0xA5B4, 0x2165, 0xA5B5, 0x2166, 0xA5B6, 0x2167, 0xA5B7, 0x2168, 0xA5B8, 0x2169, 0xA5B9, 0x2170, 0xA5A1, + 0x2171, 0xA5A2, 0x2172, 0xA5A3, 0x2173, 0xA5A4, 0x2174, 0xA5A5, 0x2175, 0xA5A6, 0x2176, 0xA5A7, 0x2177, 0xA5A8, 0x2178, 0xA5A9, + 0x2179, 0xA5AA, 0x2190, 0xA1E7, 0x2191, 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0xD783, 0xC59A, + 0xD784, 0xC59B, 0xD785, 0xC59C, 0xD786, 0xC59D, 0xD787, 0xC59E, 0xD788, 0xC8F7, 0xD789, 0xC8F8, 0xD78A, 0xC59F, 0xD78B, 0xC5A0, + 0xD78C, 0xC8F9, 0xD78D, 0xC641, 0xD78E, 0xC642, 0xD78F, 0xC643, 0xD790, 0xC8FA, 0xD791, 0xC644, 0xD792, 0xC645, 0xD793, 0xC646, + 0xD794, 0xC647, 0xD795, 0xC648, 0xD796, 0xC649, 0xD797, 0xC64A, 0xD798, 0xC8FB, 0xD799, 0xC8FC, 0xD79A, 0xC64B, 0xD79B, 0xC8FD, + 0xD79C, 0xC64C, 0xD79D, 0xC8FE, 0xD79E, 0xC64D, 0xD79F, 0xC64E, 0xD7A0, 0xC64F, 0xD7A1, 0xC650, 0xD7A2, 0xC651, 0xD7A3, 0xC652, + 0xF900, 0xCBD0, 0xF901, 0xCBD6, 0xF902, 0xCBE7, 0xF903, 0xCDCF, 0xF904, 0xCDE8, 0xF905, 0xCEAD, 0xF906, 0xCFFB, 0xF907, 0xD0A2, + 0xF908, 0xD0B8, 0xF909, 0xD0D0, 0xF90A, 0xD0DD, 0xF90B, 0xD1D4, 0xF90C, 0xD1D5, 0xF90D, 0xD1D8, 0xF90E, 0xD1DB, 0xF90F, 0xD1DC, + 0xF910, 0xD1DD, 0xF911, 0xD1DE, 0xF912, 0xD1DF, 0xF913, 0xD1E0, 0xF914, 0xD1E2, 0xF915, 0xD1E3, 0xF916, 0xD1E4, 0xF917, 0xD1E5, + 0xF918, 0xD1E6, 0xF919, 0xD1E8, 0xF91A, 0xD1E9, 0xF91B, 0xD1EA, 0xF91C, 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0xF95A, 0xD4E6, 0xF95B, 0xD4FC, 0xF95C, 0xD5A5, 0xF95D, 0xD5AB, 0xF95E, 0xD5AE, 0xF95F, 0xD6B8, + 0xF960, 0xD6CD, 0xF961, 0xD7CB, 0xF962, 0xD7E4, 0xF963, 0xDBC5, 0xF964, 0xDBE4, 0xF965, 0xDCA5, 0xF966, 0xDDA5, 0xF967, 0xDDD5, + 0xF968, 0xDDF4, 0xF969, 0xDEFC, 0xF96A, 0xDEFE, 0xF96B, 0xDFB3, 0xF96C, 0xDFE1, 0xF96D, 0xDFE8, 0xF96E, 0xE0F1, 0xF96F, 0xE1AD, + 0xF970, 0xE1ED, 0xF971, 0xE3F5, 0xF972, 0xE4A1, 0xF973, 0xE4A9, 0xF974, 0xE5AE, 0xF975, 0xE5B1, 0xF976, 0xE5B2, 0xF977, 0xE5B9, + 0xF978, 0xE5BB, 0xF979, 0xE5BC, 0xF97A, 0xE5C4, 0xF97B, 0xE5CE, 0xF97C, 0xE5D0, 0xF97D, 0xE5D2, 0xF97E, 0xE5D6, 0xF97F, 0xE5FA, + 0xF980, 0xE5FB, 0xF981, 0xE5FC, 0xF982, 0xE5FE, 0xF983, 0xE6A1, 0xF984, 0xE6A4, 0xF985, 0xE6A7, 0xF986, 0xE6AD, 0xF987, 0xE6AF, + 0xF988, 0xE6B0, 0xF989, 0xE6B1, 0xF98A, 0xE6B3, 0xF98B, 0xE6B7, 0xF98C, 0xE6B8, 0xF98D, 0xE6BC, 0xF98E, 0xE6C4, 0xF98F, 0xE6C6, + 0xF990, 0xE6C7, 0xF991, 0xE6CA, 0xF992, 0xE6D2, 0xF993, 0xE6D6, 0xF994, 0xE6D9, 0xF995, 0xE6DC, 0xF996, 0xE6DF, 0xF997, 0xE6E1, + 0xF998, 0xE6E4, 0xF999, 0xE6E5, 0xF99A, 0xE6E6, 0xF99B, 0xE6E8, 0xF99C, 0xE6EA, 0xF99D, 0xE6EB, 0xF99E, 0xE6EC, 0xF99F, 0xE6EF, + 0xF9A0, 0xE6F1, 0xF9A1, 0xE6F2, 0xF9A2, 0xE6F5, 0xF9A3, 0xE6F6, 0xF9A4, 0xE6F7, 0xF9A5, 0xE6F9, 0xF9A6, 0xE7A1, 0xF9A7, 0xE7A6, + 0xF9A8, 0xE7A9, 0xF9A9, 0xE7AA, 0xF9AA, 0xE7AC, 0xF9AB, 0xE7AD, 0xF9AC, 0xE7B0, 0xF9AD, 0xE7BF, 0xF9AE, 0xE7C1, 0xF9AF, 0xE7C6, + 0xF9B0, 0xE7C7, 0xF9B1, 0xE7CB, 0xF9B2, 0xE7CD, 0xF9B3, 0xE7CF, 0xF9B4, 0xE7D0, 0xF9B5, 0xE7D3, 0xF9B6, 0xE7DF, 0xF9B7, 0xE7E4, + 0xF9B8, 0xE7E6, 0xF9B9, 0xE7F7, 0xF9BA, 0xE8E7, 0xF9BB, 0xE8E8, 0xF9BC, 0xE8F0, 0xF9BD, 0xE8F1, 0xF9BE, 0xE8F7, 0xF9BF, 0xE8F9, + 0xF9C0, 0xE8FB, 0xF9C1, 0xE8FE, 0xF9C2, 0xE9A7, 0xF9C3, 0xE9AC, 0xF9C4, 0xE9CC, 0xF9C5, 0xE9F7, 0xF9C6, 0xEAC1, 0xF9C7, 0xEAE5, + 0xF9C8, 0xEAF4, 0xF9C9, 0xEAF7, 0xF9CA, 0xEAFC, 0xF9CB, 0xEAFE, 0xF9CC, 0xEBA4, 0xF9CD, 0xEBA7, 0xF9CE, 0xEBA9, 0xF9CF, 0xEBAA, + 0xF9D0, 0xEBBA, 0xF9D1, 0xEBBB, 0xF9D2, 0xEBBD, 0xF9D3, 0xEBC1, 0xF9D4, 0xEBC2, 0xF9D5, 0xEBC6, 0xF9D6, 0xEBC7, 0xF9D7, 0xEBCC, + 0xF9D8, 0xEBCF, 0xF9D9, 0xEBD0, 0xF9DA, 0xEBD1, 0xF9DB, 0xEBD2, 0xF9DC, 0xEBD8, 0xF9DD, 0xECA6, 0xF9DE, 0xECA7, 0xF9DF, 0xECAA, + 0xF9E0, 0xECAF, 0xF9E1, 0xECB0, 0xF9E2, 0xECB1, 0xF9E3, 0xECB2, 0xF9E4, 0xECB5, 0xF9E5, 0xECB8, 0xF9E6, 0xECBA, 0xF9E7, 0xECC0, + 0xF9E8, 0xECC1, 0xF9E9, 0xECC5, 0xF9EA, 0xECC6, 0xF9EB, 0xECC9, 0xF9EC, 0xECCA, 0xF9ED, 0xECD5, 0xF9EE, 0xECDD, 0xF9EF, 0xECDE, + 0xF9F0, 0xECE1, 0xF9F1, 0xECE4, 0xF9F2, 0xECE7, 0xF9F3, 0xECE8, 0xF9F4, 0xECF7, 0xF9F5, 0xECF8, 0xF9F6, 0xECFA, 0xF9F7, 0xEDA1, + 0xF9F8, 0xEDA2, 0xF9F9, 0xEDA3, 0xF9FA, 0xEDEE, 0xF9FB, 0xEEDB, 0xF9FC, 0xF2BD, 0xF9FD, 0xF2FA, 0xF9FE, 0xF3B1, 0xF9FF, 0xF4A7, + 0xFA00, 0xF4EE, 0xFA01, 0xF6F4, 0xFA02, 0xF6F6, 0xFA03, 0xF7B8, 0xFA04, 0xF7C8, 0xFA05, 0xF7D3, 0xFA06, 0xF8DB, 0xFA07, 0xF8F0, + 0xFA08, 0xFAA1, 0xFA09, 0xFAA2, 0xFA0A, 0xFAE6, 0xFA0B, 0xFCA9, 0xFF01, 0xA3A1, 0xFF02, 0xA3A2, 0xFF03, 0xA3A3, 0xFF04, 0xA3A4, + 0xFF05, 0xA3A5, 0xFF06, 0xA3A6, 0xFF07, 0xA3A7, 0xFF08, 0xA3A8, 0xFF09, 0xA3A9, 0xFF0A, 0xA3AA, 0xFF0B, 0xA3AB, 0xFF0C, 0xA3AC, + 0xFF0D, 0xA3AD, 0xFF0E, 0xA3AE, 0xFF0F, 0xA3AF, 0xFF10, 0xA3B0, 0xFF11, 0xA3B1, 0xFF12, 0xA3B2, 0xFF13, 0xA3B3, 0xFF14, 0xA3B4, + 0xFF15, 0xA3B5, 0xFF16, 0xA3B6, 0xFF17, 0xA3B7, 0xFF18, 0xA3B8, 0xFF19, 0xA3B9, 0xFF1A, 0xA3BA, 0xFF1B, 0xA3BB, 0xFF1C, 0xA3BC, + 0xFF1D, 0xA3BD, 0xFF1E, 0xA3BE, 0xFF1F, 0xA3BF, 0xFF20, 0xA3C0, 0xFF21, 0xA3C1, 0xFF22, 0xA3C2, 0xFF23, 0xA3C3, 0xFF24, 0xA3C4, + 0xFF25, 0xA3C5, 0xFF26, 0xA3C6, 0xFF27, 0xA3C7, 0xFF28, 0xA3C8, 0xFF29, 0xA3C9, 0xFF2A, 0xA3CA, 0xFF2B, 0xA3CB, 0xFF2C, 0xA3CC, + 0xFF2D, 0xA3CD, 0xFF2E, 0xA3CE, 0xFF2F, 0xA3CF, 0xFF30, 0xA3D0, 0xFF31, 0xA3D1, 0xFF32, 0xA3D2, 0xFF33, 0xA3D3, 0xFF34, 0xA3D4, + 0xFF35, 0xA3D5, 0xFF36, 0xA3D6, 0xFF37, 0xA3D7, 0xFF38, 0xA3D8, 0xFF39, 0xA3D9, 0xFF3A, 0xA3DA, 0xFF3B, 0xA3DB, 0xFF3C, 0xA1AC, + 0xFF3D, 0xA3DD, 0xFF3E, 0xA3DE, 0xFF3F, 0xA3DF, 0xFF40, 0xA3E0, 0xFF41, 0xA3E1, 0xFF42, 0xA3E2, 0xFF43, 0xA3E3, 0xFF44, 0xA3E4, + 0xFF45, 0xA3E5, 0xFF46, 0xA3E6, 0xFF47, 0xA3E7, 0xFF48, 0xA3E8, 0xFF49, 0xA3E9, 0xFF4A, 0xA3EA, 0xFF4B, 0xA3EB, 0xFF4C, 0xA3EC, + 0xFF4D, 0xA3ED, 0xFF4E, 0xA3EE, 0xFF4F, 0xA3EF, 0xFF50, 0xA3F0, 0xFF51, 0xA3F1, 0xFF52, 0xA3F2, 0xFF53, 0xA3F3, 0xFF54, 0xA3F4, + 0xFF55, 0xA3F5, 0xFF56, 0xA3F6, 0xFF57, 0xA3F7, 0xFF58, 0xA3F8, 0xFF59, 0xA3F9, 0xFF5A, 0xA3FA, 0xFF5B, 0xA3FB, 0xFF5C, 0xA3FC, + 0xFF5D, 0xA3FD, 0xFF5E, 0xA2A6, 0xFFE0, 0xA1CB, 0xFFE1, 0xA1CC, 0xFFE2, 0xA1FE, 0xFFE3, 0xA3FE, 0xFFE5, 0xA1CD, 0xFFE6, 0xA3DC, + 0, 0 +}; + +static const WCHAR oem2uni949[] = { /* Korean --> Unicode pairs */ + 0x8141, 0xAC02, 0x8142, 0xAC03, 0x8143, 0xAC05, 0x8144, 0xAC06, 0x8145, 0xAC0B, 0x8146, 0xAC0C, 0x8147, 0xAC0D, 0x8148, 0xAC0E, + 0x8149, 0xAC0F, 0x814A, 0xAC18, 0x814B, 0xAC1E, 0x814C, 0xAC1F, 0x814D, 0xAC21, 0x814E, 0xAC22, 0x814F, 0xAC23, 0x8150, 0xAC25, + 0x8151, 0xAC26, 0x8152, 0xAC27, 0x8153, 0xAC28, 0x8154, 0xAC29, 0x8155, 0xAC2A, 0x8156, 0xAC2B, 0x8157, 0xAC2E, 0x8158, 0xAC32, + 0x8159, 0xAC33, 0x815A, 0xAC34, 0x8161, 0xAC35, 0x8162, 0xAC36, 0x8163, 0xAC37, 0x8164, 0xAC3A, 0x8165, 0xAC3B, 0x8166, 0xAC3D, + 0x8167, 0xAC3E, 0x8168, 0xAC3F, 0x8169, 0xAC41, 0x816A, 0xAC42, 0x816B, 0xAC43, 0x816C, 0xAC44, 0x816D, 0xAC45, 0x816E, 0xAC46, + 0x816F, 0xAC47, 0x8170, 0xAC48, 0x8171, 0xAC49, 0x8172, 0xAC4A, 0x8173, 0xAC4C, 0x8174, 0xAC4E, 0x8175, 0xAC4F, 0x8176, 0xAC50, + 0x8177, 0xAC51, 0x8178, 0xAC52, 0x8179, 0xAC53, 0x817A, 0xAC55, 0x8181, 0xAC56, 0x8182, 0xAC57, 0x8183, 0xAC59, 0x8184, 0xAC5A, + 0x8185, 0xAC5B, 0x8186, 0xAC5D, 0x8187, 0xAC5E, 0x8188, 0xAC5F, 0x8189, 0xAC60, 0x818A, 0xAC61, 0x818B, 0xAC62, 0x818C, 0xAC63, + 0x818D, 0xAC64, 0x818E, 0xAC65, 0x818F, 0xAC66, 0x8190, 0xAC67, 0x8191, 0xAC68, 0x8192, 0xAC69, 0x8193, 0xAC6A, 0x8194, 0xAC6B, + 0x8195, 0xAC6C, 0x8196, 0xAC6D, 0x8197, 0xAC6E, 0x8198, 0xAC6F, 0x8199, 0xAC72, 0x819A, 0xAC73, 0x819B, 0xAC75, 0x819C, 0xAC76, + 0x819D, 0xAC79, 0x819E, 0xAC7B, 0x819F, 0xAC7C, 0x81A0, 0xAC7D, 0x81A1, 0xAC7E, 0x81A2, 0xAC7F, 0x81A3, 0xAC82, 0x81A4, 0xAC87, + 0x81A5, 0xAC88, 0x81A6, 0xAC8D, 0x81A7, 0xAC8E, 0x81A8, 0xAC8F, 0x81A9, 0xAC91, 0x81AA, 0xAC92, 0x81AB, 0xAC93, 0x81AC, 0xAC95, + 0x81AD, 0xAC96, 0x81AE, 0xAC97, 0x81AF, 0xAC98, 0x81B0, 0xAC99, 0x81B1, 0xAC9A, 0x81B2, 0xAC9B, 0x81B3, 0xAC9E, 0x81B4, 0xACA2, + 0x81B5, 0xACA3, 0x81B6, 0xACA4, 0x81B7, 0xACA5, 0x81B8, 0xACA6, 0x81B9, 0xACA7, 0x81BA, 0xACAB, 0x81BB, 0xACAD, 0x81BC, 0xACAE, + 0x81BD, 0xACB1, 0x81BE, 0xACB2, 0x81BF, 0xACB3, 0x81C0, 0xACB4, 0x81C1, 0xACB5, 0x81C2, 0xACB6, 0x81C3, 0xACB7, 0x81C4, 0xACBA, + 0x81C5, 0xACBE, 0x81C6, 0xACBF, 0x81C7, 0xACC0, 0x81C8, 0xACC2, 0x81C9, 0xACC3, 0x81CA, 0xACC5, 0x81CB, 0xACC6, 0x81CC, 0xACC7, + 0x81CD, 0xACC9, 0x81CE, 0xACCA, 0x81CF, 0xACCB, 0x81D0, 0xACCD, 0x81D1, 0xACCE, 0x81D2, 0xACCF, 0x81D3, 0xACD0, 0x81D4, 0xACD1, + 0x81D5, 0xACD2, 0x81D6, 0xACD3, 0x81D7, 0xACD4, 0x81D8, 0xACD6, 0x81D9, 0xACD8, 0x81DA, 0xACD9, 0x81DB, 0xACDA, 0x81DC, 0xACDB, + 0x81DD, 0xACDC, 0x81DE, 0xACDD, 0x81DF, 0xACDE, 0x81E0, 0xACDF, 0x81E1, 0xACE2, 0x81E2, 0xACE3, 0x81E3, 0xACE5, 0x81E4, 0xACE6, + 0x81E5, 0xACE9, 0x81E6, 0xACEB, 0x81E7, 0xACED, 0x81E8, 0xACEE, 0x81E9, 0xACF2, 0x81EA, 0xACF4, 0x81EB, 0xACF7, 0x81EC, 0xACF8, + 0x81ED, 0xACF9, 0x81EE, 0xACFA, 0x81EF, 0xACFB, 0x81F0, 0xACFE, 0x81F1, 0xACFF, 0x81F2, 0xAD01, 0x81F3, 0xAD02, 0x81F4, 0xAD03, + 0x81F5, 0xAD05, 0x81F6, 0xAD07, 0x81F7, 0xAD08, 0x81F8, 0xAD09, 0x81F9, 0xAD0A, 0x81FA, 0xAD0B, 0x81FB, 0xAD0E, 0x81FC, 0xAD10, + 0x81FD, 0xAD12, 0x81FE, 0xAD13, 0x8241, 0xAD14, 0x8242, 0xAD15, 0x8243, 0xAD16, 0x8244, 0xAD17, 0x8245, 0xAD19, 0x8246, 0xAD1A, + 0x8247, 0xAD1B, 0x8248, 0xAD1D, 0x8249, 0xAD1E, 0x824A, 0xAD1F, 0x824B, 0xAD21, 0x824C, 0xAD22, 0x824D, 0xAD23, 0x824E, 0xAD24, + 0x824F, 0xAD25, 0x8250, 0xAD26, 0x8251, 0xAD27, 0x8252, 0xAD28, 0x8253, 0xAD2A, 0x8254, 0xAD2B, 0x8255, 0xAD2E, 0x8256, 0xAD2F, + 0x8257, 0xAD30, 0x8258, 0xAD31, 0x8259, 0xAD32, 0x825A, 0xAD33, 0x8261, 0xAD36, 0x8262, 0xAD37, 0x8263, 0xAD39, 0x8264, 0xAD3A, + 0x8265, 0xAD3B, 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0xFAB4, 0x99ED, 0xFAB5, 0x9AB8, 0xFAB6, 0x52BE, 0xFAB7, 0x6838, 0xFAB8, 0x5016, + 0xFAB9, 0x5E78, 0xFABA, 0x674F, 0xFABB, 0x8347, 0xFABC, 0x884C, 0xFABD, 0x4EAB, 0xFABE, 0x5411, 0xFABF, 0x56AE, 0xFAC0, 0x73E6, + 0xFAC1, 0x9115, 0xFAC2, 0x97FF, 0xFAC3, 0x9909, 0xFAC4, 0x9957, 0xFAC5, 0x9999, 0xFAC6, 0x5653, 0xFAC7, 0x589F, 0xFAC8, 0x865B, + 0xFAC9, 0x8A31, 0xFACA, 0x61B2, 0xFACB, 0x6AF6, 0xFACC, 0x737B, 0xFACD, 0x8ED2, 0xFACE, 0x6B47, 0xFACF, 0x96AA, 0xFAD0, 0x9A57, + 0xFAD1, 0x5955, 0xFAD2, 0x7200, 0xFAD3, 0x8D6B, 0xFAD4, 0x9769, 0xFAD5, 0x4FD4, 0xFAD6, 0x5CF4, 0xFAD7, 0x5F26, 0xFAD8, 0x61F8, + 0xFAD9, 0x665B, 0xFADA, 0x6CEB, 0xFADB, 0x70AB, 0xFADC, 0x7384, 0xFADD, 0x73B9, 0xFADE, 0x73FE, 0xFADF, 0x7729, 0xFAE0, 0x774D, + 0xFAE1, 0x7D43, 0xFAE2, 0x7D62, 0xFAE3, 0x7E23, 0xFAE4, 0x8237, 0xFAE5, 0x8852, 0xFAE6, 0xFA0A, 0xFAE7, 0x8CE2, 0xFAE8, 0x9249, + 0xFAE9, 0x986F, 0xFAEA, 0x5B51, 0xFAEB, 0x7A74, 0xFAEC, 0x8840, 0xFAED, 0x9801, 0xFAEE, 0x5ACC, 0xFAEF, 0x4FE0, 0xFAF0, 0x5354, + 0xFAF1, 0x593E, 0xFAF2, 0x5CFD, 0xFAF3, 0x633E, 0xFAF4, 0x6D79, 0xFAF5, 0x72F9, 0xFAF6, 0x8105, 0xFAF7, 0x8107, 0xFAF8, 0x83A2, + 0xFAF9, 0x92CF, 0xFAFA, 0x9830, 0xFAFB, 0x4EA8, 0xFAFC, 0x5144, 0xFAFD, 0x5211, 0xFAFE, 0x578B, 0xFBA1, 0x5F62, 0xFBA2, 0x6CC2, + 0xFBA3, 0x6ECE, 0xFBA4, 0x7005, 0xFBA5, 0x7050, 0xFBA6, 0x70AF, 0xFBA7, 0x7192, 0xFBA8, 0x73E9, 0xFBA9, 0x7469, 0xFBAA, 0x834A, + 0xFBAB, 0x87A2, 0xFBAC, 0x8861, 0xFBAD, 0x9008, 0xFBAE, 0x90A2, 0xFBAF, 0x93A3, 0xFBB0, 0x99A8, 0xFBB1, 0x516E, 0xFBB2, 0x5F57, + 0xFBB3, 0x60E0, 0xFBB4, 0x6167, 0xFBB5, 0x66B3, 0xFBB6, 0x8559, 0xFBB7, 0x8E4A, 0xFBB8, 0x91AF, 0xFBB9, 0x978B, 0xFBBA, 0x4E4E, + 0xFBBB, 0x4E92, 0xFBBC, 0x547C, 0xFBBD, 0x58D5, 0xFBBE, 0x58FA, 0xFBBF, 0x597D, 0xFBC0, 0x5CB5, 0xFBC1, 0x5F27, 0xFBC2, 0x6236, + 0xFBC3, 0x6248, 0xFBC4, 0x660A, 0xFBC5, 0x6667, 0xFBC6, 0x6BEB, 0xFBC7, 0x6D69, 0xFBC8, 0x6DCF, 0xFBC9, 0x6E56, 0xFBCA, 0x6EF8, + 0xFBCB, 0x6F94, 0xFBCC, 0x6FE0, 0xFBCD, 0x6FE9, 0xFBCE, 0x705D, 0xFBCF, 0x72D0, 0xFBD0, 0x7425, 0xFBD1, 0x745A, 0xFBD2, 0x74E0, + 0xFBD3, 0x7693, 0xFBD4, 0x795C, 0xFBD5, 0x7CCA, 0xFBD6, 0x7E1E, 0xFBD7, 0x80E1, 0xFBD8, 0x82A6, 0xFBD9, 0x846B, 0xFBDA, 0x84BF, + 0xFBDB, 0x864E, 0xFBDC, 0x865F, 0xFBDD, 0x8774, 0xFBDE, 0x8B77, 0xFBDF, 0x8C6A, 0xFBE0, 0x93AC, 0xFBE1, 0x9800, 0xFBE2, 0x9865, + 0xFBE3, 0x60D1, 0xFBE4, 0x6216, 0xFBE5, 0x9177, 0xFBE6, 0x5A5A, 0xFBE7, 0x660F, 0xFBE8, 0x6DF7, 0xFBE9, 0x6E3E, 0xFBEA, 0x743F, + 0xFBEB, 0x9B42, 0xFBEC, 0x5FFD, 0xFBED, 0x60DA, 0xFBEE, 0x7B0F, 0xFBEF, 0x54C4, 0xFBF0, 0x5F18, 0xFBF1, 0x6C5E, 0xFBF2, 0x6CD3, + 0xFBF3, 0x6D2A, 0xFBF4, 0x70D8, 0xFBF5, 0x7D05, 0xFBF6, 0x8679, 0xFBF7, 0x8A0C, 0xFBF8, 0x9D3B, 0xFBF9, 0x5316, 0xFBFA, 0x548C, + 0xFBFB, 0x5B05, 0xFBFC, 0x6A3A, 0xFBFD, 0x706B, 0xFBFE, 0x7575, 0xFCA1, 0x798D, 0xFCA2, 0x79BE, 0xFCA3, 0x82B1, 0xFCA4, 0x83EF, + 0xFCA5, 0x8A71, 0xFCA6, 0x8B41, 0xFCA7, 0x8CA8, 0xFCA8, 0x9774, 0xFCA9, 0xFA0B, 0xFCAA, 0x64F4, 0xFCAB, 0x652B, 0xFCAC, 0x78BA, + 0xFCAD, 0x78BB, 0xFCAE, 0x7A6B, 0xFCAF, 0x4E38, 0xFCB0, 0x559A, 0xFCB1, 0x5950, 0xFCB2, 0x5BA6, 0xFCB3, 0x5E7B, 0xFCB4, 0x60A3, + 0xFCB5, 0x63DB, 0xFCB6, 0x6B61, 0xFCB7, 0x6665, 0xFCB8, 0x6853, 0xFCB9, 0x6E19, 0xFCBA, 0x7165, 0xFCBB, 0x74B0, 0xFCBC, 0x7D08, + 0xFCBD, 0x9084, 0xFCBE, 0x9A69, 0xFCBF, 0x9C25, 0xFCC0, 0x6D3B, 0xFCC1, 0x6ED1, 0xFCC2, 0x733E, 0xFCC3, 0x8C41, 0xFCC4, 0x95CA, + 0xFCC5, 0x51F0, 0xFCC6, 0x5E4C, 0xFCC7, 0x5FA8, 0xFCC8, 0x604D, 0xFCC9, 0x60F6, 0xFCCA, 0x6130, 0xFCCB, 0x614C, 0xFCCC, 0x6643, + 0xFCCD, 0x6644, 0xFCCE, 0x69A5, 0xFCCF, 0x6CC1, 0xFCD0, 0x6E5F, 0xFCD1, 0x6EC9, 0xFCD2, 0x6F62, 0xFCD3, 0x714C, 0xFCD4, 0x749C, + 0xFCD5, 0x7687, 0xFCD6, 0x7BC1, 0xFCD7, 0x7C27, 0xFCD8, 0x8352, 0xFCD9, 0x8757, 0xFCDA, 0x9051, 0xFCDB, 0x968D, 0xFCDC, 0x9EC3, + 0xFCDD, 0x532F, 0xFCDE, 0x56DE, 0xFCDF, 0x5EFB, 0xFCE0, 0x5F8A, 0xFCE1, 0x6062, 0xFCE2, 0x6094, 0xFCE3, 0x61F7, 0xFCE4, 0x6666, + 0xFCE5, 0x6703, 0xFCE6, 0x6A9C, 0xFCE7, 0x6DEE, 0xFCE8, 0x6FAE, 0xFCE9, 0x7070, 0xFCEA, 0x736A, 0xFCEB, 0x7E6A, 0xFCEC, 0x81BE, + 0xFCED, 0x8334, 0xFCEE, 0x86D4, 0xFCEF, 0x8AA8, 0xFCF0, 0x8CC4, 0xFCF1, 0x5283, 0xFCF2, 0x7372, 0xFCF3, 0x5B96, 0xFCF4, 0x6A6B, + 0xFCF5, 0x9404, 0xFCF6, 0x54EE, 0xFCF7, 0x5686, 0xFCF8, 0x5B5D, 0xFCF9, 0x6548, 0xFCFA, 0x6585, 0xFCFB, 0x66C9, 0xFCFC, 0x689F, + 0xFCFD, 0x6D8D, 0xFCFE, 0x6DC6, 0xFDA1, 0x723B, 0xFDA2, 0x80B4, 0xFDA3, 0x9175, 0xFDA4, 0x9A4D, 0xFDA5, 0x4FAF, 0xFDA6, 0x5019, + 0xFDA7, 0x539A, 0xFDA8, 0x540E, 0xFDA9, 0x543C, 0xFDAA, 0x5589, 0xFDAB, 0x55C5, 0xFDAC, 0x5E3F, 0xFDAD, 0x5F8C, 0xFDAE, 0x673D, + 0xFDAF, 0x7166, 0xFDB0, 0x73DD, 0xFDB1, 0x9005, 0xFDB2, 0x52DB, 0xFDB3, 0x52F3, 0xFDB4, 0x5864, 0xFDB5, 0x58CE, 0xFDB6, 0x7104, + 0xFDB7, 0x718F, 0xFDB8, 0x71FB, 0xFDB9, 0x85B0, 0xFDBA, 0x8A13, 0xFDBB, 0x6688, 0xFDBC, 0x85A8, 0xFDBD, 0x55A7, 0xFDBE, 0x6684, + 0xFDBF, 0x714A, 0xFDC0, 0x8431, 0xFDC1, 0x5349, 0xFDC2, 0x5599, 0xFDC3, 0x6BC1, 0xFDC4, 0x5F59, 0xFDC5, 0x5FBD, 0xFDC6, 0x63EE, + 0xFDC7, 0x6689, 0xFDC8, 0x7147, 0xFDC9, 0x8AF1, 0xFDCA, 0x8F1D, 0xFDCB, 0x9EBE, 0xFDCC, 0x4F11, 0xFDCD, 0x643A, 0xFDCE, 0x70CB, + 0xFDCF, 0x7566, 0xFDD0, 0x8667, 0xFDD1, 0x6064, 0xFDD2, 0x8B4E, 0xFDD3, 0x9DF8, 0xFDD4, 0x5147, 0xFDD5, 0x51F6, 0xFDD6, 0x5308, + 0xFDD7, 0x6D36, 0xFDD8, 0x80F8, 0xFDD9, 0x9ED1, 0xFDDA, 0x6615, 0xFDDB, 0x6B23, 0xFDDC, 0x7098, 0xFDDD, 0x75D5, 0xFDDE, 0x5403, + 0xFDDF, 0x5C79, 0xFDE0, 0x7D07, 0xFDE1, 0x8A16, 0xFDE2, 0x6B20, 0xFDE3, 0x6B3D, 0xFDE4, 0x6B46, 0xFDE5, 0x5438, 0xFDE6, 0x6070, + 0xFDE7, 0x6D3D, 0xFDE8, 0x7FD5, 0xFDE9, 0x8208, 0xFDEA, 0x50D6, 0xFDEB, 0x51DE, 0xFDEC, 0x559C, 0xFDED, 0x566B, 0xFDEE, 0x56CD, + 0xFDEF, 0x59EC, 0xFDF0, 0x5B09, 0xFDF1, 0x5E0C, 0xFDF2, 0x6199, 0xFDF3, 0x6198, 0xFDF4, 0x6231, 0xFDF5, 0x665E, 0xFDF6, 0x66E6, + 0xFDF7, 0x7199, 0xFDF8, 0x71B9, 0xFDF9, 0x71BA, 0xFDFA, 0x72A7, 0xFDFB, 0x79A7, 0xFDFC, 0x7A00, 0xFDFD, 0x7FB2, 0xFDFE, 0x8A70, + 0, 0 +}; +#endif + +#if FF_CODE_PAGE == 950 || FF_CODE_PAGE == 0 /* Traditional Chinese */ +static const WCHAR uni2oem950[] = { /* Unicode --> Big5 pairs */ + 0x00A7, 0xA1B1, 0x00AF, 0xA1C2, 0x00B0, 0xA258, 0x00B1, 0xA1D3, 0x00B7, 0xA150, 0x00D7, 0xA1D1, 0x00F7, 0xA1D2, 0x02C7, 0xA3BE, + 0x02C9, 0xA3BC, 0x02CA, 0xA3BD, 0x02CB, 0xA3BF, 0x02CD, 0xA1C5, 0x02D9, 0xA3BB, 0x0391, 0xA344, 0x0392, 0xA345, 0x0393, 0xA346, + 0x0394, 0xA347, 0x0395, 0xA348, 0x0396, 0xA349, 0x0397, 0xA34A, 0x0398, 0xA34B, 0x0399, 0xA34C, 0x039A, 0xA34D, 0x039B, 0xA34E, + 0x039C, 0xA34F, 0x039D, 0xA350, 0x039E, 0xA351, 0x039F, 0xA352, 0x03A0, 0xA353, 0x03A1, 0xA354, 0x03A3, 0xA355, 0x03A4, 0xA356, + 0x03A5, 0xA357, 0x03A6, 0xA358, 0x03A7, 0xA359, 0x03A8, 0xA35A, 0x03A9, 0xA35B, 0x03B1, 0xA35C, 0x03B2, 0xA35D, 0x03B3, 0xA35E, + 0x03B4, 0xA35F, 0x03B5, 0xA360, 0x03B6, 0xA361, 0x03B7, 0xA362, 0x03B8, 0xA363, 0x03B9, 0xA364, 0x03BA, 0xA365, 0x03BB, 0xA366, + 0x03BC, 0xA367, 0x03BD, 0xA368, 0x03BE, 0xA369, 0x03BF, 0xA36A, 0x03C0, 0xA36B, 0x03C1, 0xA36C, 0x03C3, 0xA36D, 0x03C4, 0xA36E, + 0x03C5, 0xA36F, 0x03C6, 0xA370, 0x03C7, 0xA371, 0x03C8, 0xA372, 0x03C9, 0xA373, 0x2013, 0xA156, 0x2014, 0xA158, 0x2018, 0xA1A5, + 0x2019, 0xA1A6, 0x201C, 0xA1A7, 0x201D, 0xA1A8, 0x2025, 0xA14C, 0x2026, 0xA14B, 0x2027, 0xA145, 0x2032, 0xA1AC, 0x2035, 0xA1AB, + 0x203B, 0xA1B0, 0x20AC, 0xA3E1, 0x2103, 0xA24A, 0x2105, 0xA1C1, 0x2109, 0xA24B, 0x2160, 0xA2B9, 0x2161, 0xA2BA, 0x2162, 0xA2BB, + 0x2163, 0xA2BC, 0x2164, 0xA2BD, 0x2165, 0xA2BE, 0x2166, 0xA2BF, 0x2167, 0xA2C0, 0x2168, 0xA2C1, 0x2169, 0xA2C2, 0x2190, 0xA1F6, + 0x2191, 0xA1F4, 0x2192, 0xA1F7, 0x2193, 0xA1F5, 0x2196, 0xA1F8, 0x2197, 0xA1F9, 0x2198, 0xA1FB, 0x2199, 0xA1FA, 0x2215, 0xA241, + 0x221A, 0xA1D4, 0x221E, 0xA1DB, 0x221F, 0xA1E8, 0x2220, 0xA1E7, 0x2223, 0xA1FD, 0x2225, 0xA1FC, 0x2229, 0xA1E4, 0x222A, 0xA1E5, + 0x222B, 0xA1EC, 0x222E, 0xA1ED, 0x2234, 0xA1EF, 0x2235, 0xA1EE, 0x2252, 0xA1DC, 0x2260, 0xA1DA, 0x2261, 0xA1DD, 0x2266, 0xA1D8, + 0x2267, 0xA1D9, 0x2295, 0xA1F2, 0x2299, 0xA1F3, 0x22A5, 0xA1E6, 0x22BF, 0xA1E9, 0x2500, 0xA277, 0x2502, 0xA278, 0x250C, 0xA27A, + 0x2510, 0xA27B, 0x2514, 0xA27C, 0x2518, 0xA27D, 0x251C, 0xA275, 0x2524, 0xA274, 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0xC24C, 0x9EDC, 0xC24A, 0x9EDD, 0xC24B, 0x9EDE, 0xC249, 0x9EDF, 0xF1E0, 0x9EE0, 0xC35C, 0x9EE4, 0xF5B5, 0x9EE5, 0xF5B4, + 0x9EE6, 0xF5B7, 0x9EE7, 0xF5B6, 0x9EE8, 0xC4D2, 0x9EEB, 0xF6CB, 0x9EED, 0xF6CD, 0x9EEE, 0xF6CC, 0x9EEF, 0xC566, 0x9EF0, 0xF7C8, + 0x9EF2, 0xF876, 0x9EF3, 0xF877, 0x9EF4, 0xC5F0, 0x9EF5, 0xF964, 0x9EF6, 0xF97D, 0x9EF7, 0xC675, 0x9EF9, 0xDCB0, 0x9EFA, 0xECB6, + 0x9EFB, 0xEFB0, 0x9EFC, 0xF3F5, 0x9EFD, 0xE0EF, 0x9EFF, 0xEFB1, 0x9F00, 0xF1E2, 0x9F01, 0xF1E1, 0x9F06, 0xF878, 0x9F07, 0xC652, + 0x9F09, 0xF965, 0x9F0A, 0xF97E, 0x9F0E, 0xB9A9, 0x9F0F, 0xE8F2, 0x9F10, 0xE8F3, 0x9F12, 0xECB7, 0x9F13, 0xB9AA, 0x9F15, 0xC35D, + 0x9F16, 0xF1E3, 0x9F18, 0xF6CF, 0x9F19, 0xC567, 0x9F1A, 0xF6D0, 0x9F1B, 0xF6CE, 0x9F1C, 0xF879, 0x9F1E, 0xF8E9, 0x9F20, 0xB9AB, + 0x9F22, 0xEFB4, 0x9F23, 0xEFB3, 0x9F24, 0xEFB2, 0x9F25, 0xF1E4, 0x9F28, 0xF1E8, 0x9F29, 0xF1E7, 0x9F2A, 0xF1E6, 0x9F2B, 0xF1E5, + 0x9F2C, 0xC35E, 0x9F2D, 0xF3F6, 0x9F2E, 0xF5B9, 0x9F2F, 0xC4D3, 0x9F30, 0xF5B8, 0x9F31, 0xF6D1, 0x9F32, 0xF7CB, 0x9F33, 0xF7CA, + 0x9F34, 0xC5C4, 0x9F35, 0xF7C9, 0x9F36, 0xF87C, 0x9F37, 0xF87B, 0x9F38, 0xF87A, 0x9F3B, 0xBBF3, 0x9F3D, 0xECB8, 0x9F3E, 0xC24D, + 0x9F40, 0xF3F7, 0x9F41, 0xF3F8, 0x9F42, 0xF7CC, 0x9F43, 0xF87D, 0x9F46, 0xF8EA, 0x9F47, 0xF966, 0x9F48, 0xF9B9, 0x9F49, 0xF9D4, + 0x9F4A, 0xBBF4, 0x9F4B, 0xC24E, 0x9F4C, 0xF1E9, 0x9F4D, 0xF3F9, 0x9F4E, 0xF6D2, 0x9F4F, 0xF87E, 0x9F52, 0xBEA6, 0x9F54, 0xEFB5, + 0x9F55, 0xF1EA, 0x9F56, 0xF3FA, 0x9F57, 0xF3FB, 0x9F58, 0xF3FC, 0x9F59, 0xF5BE, 0x9F5B, 0xF5BA, 0x9F5C, 0xC568, 0x9F5D, 0xF5BD, + 0x9F5E, 0xF5BC, 0x9F5F, 0xC4D4, 0x9F60, 0xF5BB, 0x9F61, 0xC4D6, 0x9F63, 0xC4D5, 0x9F64, 0xF6D4, 0x9F65, 0xF6D3, 0x9F66, 0xC569, + 0x9F67, 0xC56A, 0x9F6A, 0xC5C6, 0x9F6B, 0xF7CD, 0x9F6C, 0xC5C5, 0x9F6E, 0xF8A3, 0x9F6F, 0xF8A4, 0x9F70, 0xF8A2, 0x9F71, 0xF8A1, + 0x9F72, 0xC654, 0x9F74, 0xF8EB, 0x9F75, 0xF8EC, 0x9F76, 0xF8ED, 0x9F77, 0xC653, 0x9F78, 0xF967, 0x9F79, 0xF96A, 0x9F7A, 0xF969, + 0x9F7B, 0xF968, 0x9F7E, 0xF9D3, 0x9F8D, 0xC073, 0x9F90, 0xC365, 0x9F91, 0xF5BF, 0x9F92, 0xF6D5, 0x9F94, 0xC5C7, 0x9F95, 0xF7CE, + 0x9F98, 0xF9D5, 0x9F9C, 0xC074, 0x9FA0, 0xEFB6, 0x9FA2, 0xF7CF, 0x9FA4, 0xF9A1, 0xFA0C, 0xC94A, 0xFA0D, 0xDDFC, 0xFE30, 0xA14A, + 0xFE31, 0xA157, 0xFE33, 0xA159, 0xFE34, 0xA15B, 0xFE35, 0xA15F, 0xFE36, 0xA160, 0xFE37, 0xA163, 0xFE38, 0xA164, 0xFE39, 0xA167, + 0xFE3A, 0xA168, 0xFE3B, 0xA16B, 0xFE3C, 0xA16C, 0xFE3D, 0xA16F, 0xFE3E, 0xA170, 0xFE3F, 0xA173, 0xFE40, 0xA174, 0xFE41, 0xA177, + 0xFE42, 0xA178, 0xFE43, 0xA17B, 0xFE44, 0xA17C, 0xFE49, 0xA1C6, 0xFE4A, 0xA1C7, 0xFE4B, 0xA1CA, 0xFE4C, 0xA1CB, 0xFE4D, 0xA1C8, + 0xFE4E, 0xA1C9, 0xFE4F, 0xA15C, 0xFE50, 0xA14D, 0xFE51, 0xA14E, 0xFE52, 0xA14F, 0xFE54, 0xA151, 0xFE55, 0xA152, 0xFE56, 0xA153, + 0xFE57, 0xA154, 0xFE59, 0xA17D, 0xFE5A, 0xA17E, 0xFE5B, 0xA1A1, 0xFE5C, 0xA1A2, 0xFE5D, 0xA1A3, 0xFE5E, 0xA1A4, 0xFE5F, 0xA1CC, + 0xFE60, 0xA1CD, 0xFE61, 0xA1CE, 0xFE62, 0xA1DE, 0xFE63, 0xA1DF, 0xFE64, 0xA1E0, 0xFE65, 0xA1E1, 0xFE66, 0xA1E2, 0xFE68, 0xA242, + 0xFE69, 0xA24C, 0xFE6A, 0xA24D, 0xFE6B, 0xA24E, 0xFF01, 0xA149, 0xFF03, 0xA1AD, 0xFF04, 0xA243, 0xFF05, 0xA248, 0xFF06, 0xA1AE, + 0xFF08, 0xA15D, 0xFF09, 0xA15E, 0xFF0A, 0xA1AF, 0xFF0B, 0xA1CF, 0xFF0C, 0xA141, 0xFF0D, 0xA1D0, 0xFF0E, 0xA144, 0xFF0F, 0xA1FE, + 0xFF10, 0xA2AF, 0xFF11, 0xA2B0, 0xFF12, 0xA2B1, 0xFF13, 0xA2B2, 0xFF14, 0xA2B3, 0xFF15, 0xA2B4, 0xFF16, 0xA2B5, 0xFF17, 0xA2B6, + 0xFF18, 0xA2B7, 0xFF19, 0xA2B8, 0xFF1A, 0xA147, 0xFF1B, 0xA146, 0xFF1C, 0xA1D5, 0xFF1D, 0xA1D7, 0xFF1E, 0xA1D6, 0xFF1F, 0xA148, + 0xFF20, 0xA249, 0xFF21, 0xA2CF, 0xFF22, 0xA2D0, 0xFF23, 0xA2D1, 0xFF24, 0xA2D2, 0xFF25, 0xA2D3, 0xFF26, 0xA2D4, 0xFF27, 0xA2D5, + 0xFF28, 0xA2D6, 0xFF29, 0xA2D7, 0xFF2A, 0xA2D8, 0xFF2B, 0xA2D9, 0xFF2C, 0xA2DA, 0xFF2D, 0xA2DB, 0xFF2E, 0xA2DC, 0xFF2F, 0xA2DD, + 0xFF30, 0xA2DE, 0xFF31, 0xA2DF, 0xFF32, 0xA2E0, 0xFF33, 0xA2E1, 0xFF34, 0xA2E2, 0xFF35, 0xA2E3, 0xFF36, 0xA2E4, 0xFF37, 0xA2E5, + 0xFF38, 0xA2E6, 0xFF39, 0xA2E7, 0xFF3A, 0xA2E8, 0xFF3C, 0xA240, 0xFF3F, 0xA1C4, 0xFF41, 0xA2E9, 0xFF42, 0xA2EA, 0xFF43, 0xA2EB, + 0xFF44, 0xA2EC, 0xFF45, 0xA2ED, 0xFF46, 0xA2EE, 0xFF47, 0xA2EF, 0xFF48, 0xA2F0, 0xFF49, 0xA2F1, 0xFF4A, 0xA2F2, 0xFF4B, 0xA2F3, + 0xFF4C, 0xA2F4, 0xFF4D, 0xA2F5, 0xFF4E, 0xA2F6, 0xFF4F, 0xA2F7, 0xFF50, 0xA2F8, 0xFF51, 0xA2F9, 0xFF52, 0xA2FA, 0xFF53, 0xA2FB, + 0xFF54, 0xA2FC, 0xFF55, 0xA2FD, 0xFF56, 0xA2FE, 0xFF57, 0xA340, 0xFF58, 0xA341, 0xFF59, 0xA342, 0xFF5A, 0xA343, 0xFF5B, 0xA161, + 0xFF5C, 0xA155, 0xFF5D, 0xA162, 0xFF5E, 0xA1E3, 0xFFE0, 0xA246, 0xFFE1, 0xA247, 0xFFE3, 0xA1C3, 0xFFE5, 0xA244, 0, 0 +}; + +static const WCHAR oem2uni950[] = { /* Big5 --> Unicode pairs */ + 0xA140, 0x3000, 0xA141, 0xFF0C, 0xA142, 0x3001, 0xA143, 0x3002, 0xA144, 0xFF0E, 0xA145, 0x2027, 0xA146, 0xFF1B, 0xA147, 0xFF1A, + 0xA148, 0xFF1F, 0xA149, 0xFF01, 0xA14A, 0xFE30, 0xA14B, 0x2026, 0xA14C, 0x2025, 0xA14D, 0xFE50, 0xA14E, 0xFE51, 0xA14F, 0xFE52, + 0xA150, 0x00B7, 0xA151, 0xFE54, 0xA152, 0xFE55, 0xA153, 0xFE56, 0xA154, 0xFE57, 0xA155, 0xFF5C, 0xA156, 0x2013, 0xA157, 0xFE31, + 0xA158, 0x2014, 0xA159, 0xFE33, 0xA15A, 0x2574, 0xA15B, 0xFE34, 0xA15C, 0xFE4F, 0xA15D, 0xFF08, 0xA15E, 0xFF09, 0xA15F, 0xFE35, + 0xA160, 0xFE36, 0xA161, 0xFF5B, 0xA162, 0xFF5D, 0xA163, 0xFE37, 0xA164, 0xFE38, 0xA165, 0x3014, 0xA166, 0x3015, 0xA167, 0xFE39, + 0xA168, 0xFE3A, 0xA169, 0x3010, 0xA16A, 0x3011, 0xA16B, 0xFE3B, 0xA16C, 0xFE3C, 0xA16D, 0x300A, 0xA16E, 0x300B, 0xA16F, 0xFE3D, + 0xA170, 0xFE3E, 0xA171, 0x3008, 0xA172, 0x3009, 0xA173, 0xFE3F, 0xA174, 0xFE40, 0xA175, 0x300C, 0xA176, 0x300D, 0xA177, 0xFE41, + 0xA178, 0xFE42, 0xA179, 0x300E, 0xA17A, 0x300F, 0xA17B, 0xFE43, 0xA17C, 0xFE44, 0xA17D, 0xFE59, 0xA17E, 0xFE5A, 0xA1A1, 0xFE5B, + 0xA1A2, 0xFE5C, 0xA1A3, 0xFE5D, 0xA1A4, 0xFE5E, 0xA1A5, 0x2018, 0xA1A6, 0x2019, 0xA1A7, 0x201C, 0xA1A8, 0x201D, 0xA1A9, 0x301D, + 0xA1AA, 0x301E, 0xA1AB, 0x2035, 0xA1AC, 0x2032, 0xA1AD, 0xFF03, 0xA1AE, 0xFF06, 0xA1AF, 0xFF0A, 0xA1B0, 0x203B, 0xA1B1, 0x00A7, + 0xA1B2, 0x3003, 0xA1B3, 0x25CB, 0xA1B4, 0x25CF, 0xA1B5, 0x25B3, 0xA1B6, 0x25B2, 0xA1B7, 0x25CE, 0xA1B8, 0x2606, 0xA1B9, 0x2605, + 0xA1BA, 0x25C7, 0xA1BB, 0x25C6, 0xA1BC, 0x25A1, 0xA1BD, 0x25A0, 0xA1BE, 0x25BD, 0xA1BF, 0x25BC, 0xA1C0, 0x32A3, 0xA1C1, 0x2105, + 0xA1C2, 0x00AF, 0xA1C3, 0xFFE3, 0xA1C4, 0xFF3F, 0xA1C5, 0x02CD, 0xA1C6, 0xFE49, 0xA1C7, 0xFE4A, 0xA1C8, 0xFE4D, 0xA1C9, 0xFE4E, + 0xA1CA, 0xFE4B, 0xA1CB, 0xFE4C, 0xA1CC, 0xFE5F, 0xA1CD, 0xFE60, 0xA1CE, 0xFE61, 0xA1CF, 0xFF0B, 0xA1D0, 0xFF0D, 0xA1D1, 0x00D7, + 0xA1D2, 0x00F7, 0xA1D3, 0x00B1, 0xA1D4, 0x221A, 0xA1D5, 0xFF1C, 0xA1D6, 0xFF1E, 0xA1D7, 0xFF1D, 0xA1D8, 0x2266, 0xA1D9, 0x2267, + 0xA1DA, 0x2260, 0xA1DB, 0x221E, 0xA1DC, 0x2252, 0xA1DD, 0x2261, 0xA1DE, 0xFE62, 0xA1DF, 0xFE63, 0xA1E0, 0xFE64, 0xA1E1, 0xFE65, + 0xA1E2, 0xFE66, 0xA1E3, 0xFF5E, 0xA1E4, 0x2229, 0xA1E5, 0x222A, 0xA1E6, 0x22A5, 0xA1E7, 0x2220, 0xA1E8, 0x221F, 0xA1E9, 0x22BF, + 0xA1EA, 0x33D2, 0xA1EB, 0x33D1, 0xA1EC, 0x222B, 0xA1ED, 0x222E, 0xA1EE, 0x2235, 0xA1EF, 0x2234, 0xA1F0, 0x2640, 0xA1F1, 0x2642, + 0xA1F2, 0x2295, 0xA1F3, 0x2299, 0xA1F4, 0x2191, 0xA1F5, 0x2193, 0xA1F6, 0x2190, 0xA1F7, 0x2192, 0xA1F8, 0x2196, 0xA1F9, 0x2197, + 0xA1FA, 0x2199, 0xA1FB, 0x2198, 0xA1FC, 0x2225, 0xA1FD, 0x2223, 0xA1FE, 0xFF0F, 0xA240, 0xFF3C, 0xA241, 0x2215, 0xA242, 0xFE68, + 0xA243, 0xFF04, 0xA244, 0xFFE5, 0xA245, 0x3012, 0xA246, 0xFFE0, 0xA247, 0xFFE1, 0xA248, 0xFF05, 0xA249, 0xFF20, 0xA24A, 0x2103, + 0xA24B, 0x2109, 0xA24C, 0xFE69, 0xA24D, 0xFE6A, 0xA24E, 0xFE6B, 0xA24F, 0x33D5, 0xA250, 0x339C, 0xA251, 0x339D, 0xA252, 0x339E, + 0xA253, 0x33CE, 0xA254, 0x33A1, 0xA255, 0x338E, 0xA256, 0x338F, 0xA257, 0x33C4, 0xA258, 0x00B0, 0xA259, 0x5159, 0xA25A, 0x515B, + 0xA25B, 0x515E, 0xA25C, 0x515D, 0xA25D, 0x5161, 0xA25E, 0x5163, 0xA25F, 0x55E7, 0xA260, 0x74E9, 0xA261, 0x7CCE, 0xA262, 0x2581, + 0xA263, 0x2582, 0xA264, 0x2583, 0xA265, 0x2584, 0xA266, 0x2585, 0xA267, 0x2586, 0xA268, 0x2587, 0xA269, 0x2588, 0xA26A, 0x258F, + 0xA26B, 0x258E, 0xA26C, 0x258D, 0xA26D, 0x258C, 0xA26E, 0x258B, 0xA26F, 0x258A, 0xA270, 0x2589, 0xA271, 0x253C, 0xA272, 0x2534, + 0xA273, 0x252C, 0xA274, 0x2524, 0xA275, 0x251C, 0xA276, 0x2594, 0xA277, 0x2500, 0xA278, 0x2502, 0xA279, 0x2595, 0xA27A, 0x250C, + 0xA27B, 0x2510, 0xA27C, 0x2514, 0xA27D, 0x2518, 0xA27E, 0x256D, 0xA2A1, 0x256E, 0xA2A2, 0x2570, 0xA2A3, 0x256F, 0xA2A4, 0x2550, + 0xA2A5, 0x255E, 0xA2A6, 0x256A, 0xA2A7, 0x2561, 0xA2A8, 0x25E2, 0xA2A9, 0x25E3, 0xA2AA, 0x25E5, 0xA2AB, 0x25E4, 0xA2AC, 0x2571, + 0xA2AD, 0x2572, 0xA2AE, 0x2573, 0xA2AF, 0xFF10, 0xA2B0, 0xFF11, 0xA2B1, 0xFF12, 0xA2B2, 0xFF13, 0xA2B3, 0xFF14, 0xA2B4, 0xFF15, + 0xA2B5, 0xFF16, 0xA2B6, 0xFF17, 0xA2B7, 0xFF18, 0xA2B8, 0xFF19, 0xA2B9, 0x2160, 0xA2BA, 0x2161, 0xA2BB, 0x2162, 0xA2BC, 0x2163, + 0xA2BD, 0x2164, 0xA2BE, 0x2165, 0xA2BF, 0x2166, 0xA2C0, 0x2167, 0xA2C1, 0x2168, 0xA2C2, 0x2169, 0xA2C3, 0x3021, 0xA2C4, 0x3022, + 0xA2C5, 0x3023, 0xA2C6, 0x3024, 0xA2C7, 0x3025, 0xA2C8, 0x3026, 0xA2C9, 0x3027, 0xA2CA, 0x3028, 0xA2CB, 0x3029, 0xA2CC, 0x5341, + 0xA2CD, 0x5344, 0xA2CE, 0x5345, 0xA2CF, 0xFF21, 0xA2D0, 0xFF22, 0xA2D1, 0xFF23, 0xA2D2, 0xFF24, 0xA2D3, 0xFF25, 0xA2D4, 0xFF26, + 0xA2D5, 0xFF27, 0xA2D6, 0xFF28, 0xA2D7, 0xFF29, 0xA2D8, 0xFF2A, 0xA2D9, 0xFF2B, 0xA2DA, 0xFF2C, 0xA2DB, 0xFF2D, 0xA2DC, 0xFF2E, + 0xA2DD, 0xFF2F, 0xA2DE, 0xFF30, 0xA2DF, 0xFF31, 0xA2E0, 0xFF32, 0xA2E1, 0xFF33, 0xA2E2, 0xFF34, 0xA2E3, 0xFF35, 0xA2E4, 0xFF36, + 0xA2E5, 0xFF37, 0xA2E6, 0xFF38, 0xA2E7, 0xFF39, 0xA2E8, 0xFF3A, 0xA2E9, 0xFF41, 0xA2EA, 0xFF42, 0xA2EB, 0xFF43, 0xA2EC, 0xFF44, + 0xA2ED, 0xFF45, 0xA2EE, 0xFF46, 0xA2EF, 0xFF47, 0xA2F0, 0xFF48, 0xA2F1, 0xFF49, 0xA2F2, 0xFF4A, 0xA2F3, 0xFF4B, 0xA2F4, 0xFF4C, + 0xA2F5, 0xFF4D, 0xA2F6, 0xFF4E, 0xA2F7, 0xFF4F, 0xA2F8, 0xFF50, 0xA2F9, 0xFF51, 0xA2FA, 0xFF52, 0xA2FB, 0xFF53, 0xA2FC, 0xFF54, + 0xA2FD, 0xFF55, 0xA2FE, 0xFF56, 0xA340, 0xFF57, 0xA341, 0xFF58, 0xA342, 0xFF59, 0xA343, 0xFF5A, 0xA344, 0x0391, 0xA345, 0x0392, + 0xA346, 0x0393, 0xA347, 0x0394, 0xA348, 0x0395, 0xA349, 0x0396, 0xA34A, 0x0397, 0xA34B, 0x0398, 0xA34C, 0x0399, 0xA34D, 0x039A, + 0xA34E, 0x039B, 0xA34F, 0x039C, 0xA350, 0x039D, 0xA351, 0x039E, 0xA352, 0x039F, 0xA353, 0x03A0, 0xA354, 0x03A1, 0xA355, 0x03A3, + 0xA356, 0x03A4, 0xA357, 0x03A5, 0xA358, 0x03A6, 0xA359, 0x03A7, 0xA35A, 0x03A8, 0xA35B, 0x03A9, 0xA35C, 0x03B1, 0xA35D, 0x03B2, + 0xA35E, 0x03B3, 0xA35F, 0x03B4, 0xA360, 0x03B5, 0xA361, 0x03B6, 0xA362, 0x03B7, 0xA363, 0x03B8, 0xA364, 0x03B9, 0xA365, 0x03BA, + 0xA366, 0x03BB, 0xA367, 0x03BC, 0xA368, 0x03BD, 0xA369, 0x03BE, 0xA36A, 0x03BF, 0xA36B, 0x03C0, 0xA36C, 0x03C1, 0xA36D, 0x03C3, + 0xA36E, 0x03C4, 0xA36F, 0x03C5, 0xA370, 0x03C6, 0xA371, 0x03C7, 0xA372, 0x03C8, 0xA373, 0x03C9, 0xA374, 0x3105, 0xA375, 0x3106, + 0xA376, 0x3107, 0xA377, 0x3108, 0xA378, 0x3109, 0xA379, 0x310A, 0xA37A, 0x310B, 0xA37B, 0x310C, 0xA37C, 0x310D, 0xA37D, 0x310E, + 0xA37E, 0x310F, 0xA3A1, 0x3110, 0xA3A2, 0x3111, 0xA3A3, 0x3112, 0xA3A4, 0x3113, 0xA3A5, 0x3114, 0xA3A6, 0x3115, 0xA3A7, 0x3116, + 0xA3A8, 0x3117, 0xA3A9, 0x3118, 0xA3AA, 0x3119, 0xA3AB, 0x311A, 0xA3AC, 0x311B, 0xA3AD, 0x311C, 0xA3AE, 0x311D, 0xA3AF, 0x311E, + 0xA3B0, 0x311F, 0xA3B1, 0x3120, 0xA3B2, 0x3121, 0xA3B3, 0x3122, 0xA3B4, 0x3123, 0xA3B5, 0x3124, 0xA3B6, 0x3125, 0xA3B7, 0x3126, + 0xA3B8, 0x3127, 0xA3B9, 0x3128, 0xA3BA, 0x3129, 0xA3BB, 0x02D9, 0xA3BC, 0x02C9, 0xA3BD, 0x02CA, 0xA3BE, 0x02C7, 0xA3BF, 0x02CB, + 0xA3E1, 0x20AC, 0xA440, 0x4E00, 0xA441, 0x4E59, 0xA442, 0x4E01, 0xA443, 0x4E03, 0xA444, 0x4E43, 0xA445, 0x4E5D, 0xA446, 0x4E86, + 0xA447, 0x4E8C, 0xA448, 0x4EBA, 0xA449, 0x513F, 0xA44A, 0x5165, 0xA44B, 0x516B, 0xA44C, 0x51E0, 0xA44D, 0x5200, 0xA44E, 0x5201, + 0xA44F, 0x529B, 0xA450, 0x5315, 0xA451, 0x5341, 0xA452, 0x535C, 0xA453, 0x53C8, 0xA454, 0x4E09, 0xA455, 0x4E0B, 0xA456, 0x4E08, + 0xA457, 0x4E0A, 0xA458, 0x4E2B, 0xA459, 0x4E38, 0xA45A, 0x51E1, 0xA45B, 0x4E45, 0xA45C, 0x4E48, 0xA45D, 0x4E5F, 0xA45E, 0x4E5E, + 0xA45F, 0x4E8E, 0xA460, 0x4EA1, 0xA461, 0x5140, 0xA462, 0x5203, 0xA463, 0x52FA, 0xA464, 0x5343, 0xA465, 0x53C9, 0xA466, 0x53E3, + 0xA467, 0x571F, 0xA468, 0x58EB, 0xA469, 0x5915, 0xA46A, 0x5927, 0xA46B, 0x5973, 0xA46C, 0x5B50, 0xA46D, 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0x9DDC, 0xF7BE, 0x9DD1, 0xF7BF, 0x9DDF, 0xF7C0, 0x9DE9, 0xF7C1, 0x9DD9, + 0xF7C2, 0x9DD8, 0xF7C3, 0x9DD6, 0xF7C4, 0x9DF5, 0xF7C5, 0x9DD5, 0xF7C6, 0x9DDD, 0xF7C7, 0x9EB6, 0xF7C8, 0x9EF0, 0xF7C9, 0x9F35, + 0xF7CA, 0x9F33, 0xF7CB, 0x9F32, 0xF7CC, 0x9F42, 0xF7CD, 0x9F6B, 0xF7CE, 0x9F95, 0xF7CF, 0x9FA2, 0xF7D0, 0x513D, 0xF7D1, 0x5299, + 0xF7D2, 0x58E8, 0xF7D3, 0x58E7, 0xF7D4, 0x5972, 0xF7D5, 0x5B4D, 0xF7D6, 0x5DD8, 0xF7D7, 0x882F, 0xF7D8, 0x5F4F, 0xF7D9, 0x6201, + 0xF7DA, 0x6203, 0xF7DB, 0x6204, 0xF7DC, 0x6529, 0xF7DD, 0x6525, 0xF7DE, 0x6596, 0xF7DF, 0x66EB, 0xF7E0, 0x6B11, 0xF7E1, 0x6B12, + 0xF7E2, 0x6B0F, 0xF7E3, 0x6BCA, 0xF7E4, 0x705B, 0xF7E5, 0x705A, 0xF7E6, 0x7222, 0xF7E7, 0x7382, 0xF7E8, 0x7381, 0xF7E9, 0x7383, + 0xF7EA, 0x7670, 0xF7EB, 0x77D4, 0xF7EC, 0x7C67, 0xF7ED, 0x7C66, 0xF7EE, 0x7E95, 0xF7EF, 0x826C, 0xF7F0, 0x863A, 0xF7F1, 0x8640, + 0xF7F2, 0x8639, 0xF7F3, 0x863C, 0xF7F4, 0x8631, 0xF7F5, 0x863B, 0xF7F6, 0x863E, 0xF7F7, 0x8830, 0xF7F8, 0x8832, 0xF7F9, 0x882E, + 0xF7FA, 0x8833, 0xF7FB, 0x8976, 0xF7FC, 0x8974, 0xF7FD, 0x8973, 0xF7FE, 0x89FE, 0xF840, 0x8B8C, 0xF841, 0x8B8E, 0xF842, 0x8B8B, + 0xF843, 0x8B88, 0xF844, 0x8C45, 0xF845, 0x8D19, 0xF846, 0x8E98, 0xF847, 0x8F64, 0xF848, 0x8F63, 0xF849, 0x91BC, 0xF84A, 0x9462, + 0xF84B, 0x9455, 0xF84C, 0x945D, 0xF84D, 0x9457, 0xF84E, 0x945E, 0xF84F, 0x97C4, 0xF850, 0x97C5, 0xF851, 0x9800, 0xF852, 0x9A56, + 0xF853, 0x9A59, 0xF854, 0x9B1E, 0xF855, 0x9B1F, 0xF856, 0x9B20, 0xF857, 0x9C52, 0xF858, 0x9C58, 0xF859, 0x9C50, 0xF85A, 0x9C4A, + 0xF85B, 0x9C4D, 0xF85C, 0x9C4B, 0xF85D, 0x9C55, 0xF85E, 0x9C59, 0xF85F, 0x9C4C, 0xF860, 0x9C4E, 0xF861, 0x9DFB, 0xF862, 0x9DF7, + 0xF863, 0x9DEF, 0xF864, 0x9DE3, 0xF865, 0x9DEB, 0xF866, 0x9DF8, 0xF867, 0x9DE4, 0xF868, 0x9DF6, 0xF869, 0x9DE1, 0xF86A, 0x9DEE, + 0xF86B, 0x9DE6, 0xF86C, 0x9DF2, 0xF86D, 0x9DF0, 0xF86E, 0x9DE2, 0xF86F, 0x9DEC, 0xF870, 0x9DF4, 0xF871, 0x9DF3, 0xF872, 0x9DE8, + 0xF873, 0x9DED, 0xF874, 0x9EC2, 0xF875, 0x9ED0, 0xF876, 0x9EF2, 0xF877, 0x9EF3, 0xF878, 0x9F06, 0xF879, 0x9F1C, 0xF87A, 0x9F38, + 0xF87B, 0x9F37, 0xF87C, 0x9F36, 0xF87D, 0x9F43, 0xF87E, 0x9F4F, 0xF8A1, 0x9F71, 0xF8A2, 0x9F70, 0xF8A3, 0x9F6E, 0xF8A4, 0x9F6F, + 0xF8A5, 0x56D3, 0xF8A6, 0x56CD, 0xF8A7, 0x5B4E, 0xF8A8, 0x5C6D, 0xF8A9, 0x652D, 0xF8AA, 0x66ED, 0xF8AB, 0x66EE, 0xF8AC, 0x6B13, + 0xF8AD, 0x705F, 0xF8AE, 0x7061, 0xF8AF, 0x705D, 0xF8B0, 0x7060, 0xF8B1, 0x7223, 0xF8B2, 0x74DB, 0xF8B3, 0x74E5, 0xF8B4, 0x77D5, + 0xF8B5, 0x7938, 0xF8B6, 0x79B7, 0xF8B7, 0x79B6, 0xF8B8, 0x7C6A, 0xF8B9, 0x7E97, 0xF8BA, 0x7F89, 0xF8BB, 0x826D, 0xF8BC, 0x8643, + 0xF8BD, 0x8838, 0xF8BE, 0x8837, 0xF8BF, 0x8835, 0xF8C0, 0x884B, 0xF8C1, 0x8B94, 0xF8C2, 0x8B95, 0xF8C3, 0x8E9E, 0xF8C4, 0x8E9F, + 0xF8C5, 0x8EA0, 0xF8C6, 0x8E9D, 0xF8C7, 0x91BE, 0xF8C8, 0x91BD, 0xF8C9, 0x91C2, 0xF8CA, 0x946B, 0xF8CB, 0x9468, 0xF8CC, 0x9469, + 0xF8CD, 0x96E5, 0xF8CE, 0x9746, 0xF8CF, 0x9743, 0xF8D0, 0x9747, 0xF8D1, 0x97C7, 0xF8D2, 0x97E5, 0xF8D3, 0x9A5E, 0xF8D4, 0x9AD5, + 0xF8D5, 0x9B59, 0xF8D6, 0x9C63, 0xF8D7, 0x9C67, 0xF8D8, 0x9C66, 0xF8D9, 0x9C62, 0xF8DA, 0x9C5E, 0xF8DB, 0x9C60, 0xF8DC, 0x9E02, + 0xF8DD, 0x9DFE, 0xF8DE, 0x9E07, 0xF8DF, 0x9E03, 0xF8E0, 0x9E06, 0xF8E1, 0x9E05, 0xF8E2, 0x9E00, 0xF8E3, 0x9E01, 0xF8E4, 0x9E09, + 0xF8E5, 0x9DFF, 0xF8E6, 0x9DFD, 0xF8E7, 0x9E04, 0xF8E8, 0x9EA0, 0xF8E9, 0x9F1E, 0xF8EA, 0x9F46, 0xF8EB, 0x9F74, 0xF8EC, 0x9F75, + 0xF8ED, 0x9F76, 0xF8EE, 0x56D4, 0xF8EF, 0x652E, 0xF8F0, 0x65B8, 0xF8F1, 0x6B18, 0xF8F2, 0x6B19, 0xF8F3, 0x6B17, 0xF8F4, 0x6B1A, + 0xF8F5, 0x7062, 0xF8F6, 0x7226, 0xF8F7, 0x72AA, 0xF8F8, 0x77D8, 0xF8F9, 0x77D9, 0xF8FA, 0x7939, 0xF8FB, 0x7C69, 0xF8FC, 0x7C6B, + 0xF8FD, 0x7CF6, 0xF8FE, 0x7E9A, 0xF940, 0x7E98, 0xF941, 0x7E9B, 0xF942, 0x7E99, 0xF943, 0x81E0, 0xF944, 0x81E1, 0xF945, 0x8646, + 0xF946, 0x8647, 0xF947, 0x8648, 0xF948, 0x8979, 0xF949, 0x897A, 0xF94A, 0x897C, 0xF94B, 0x897B, 0xF94C, 0x89FF, 0xF94D, 0x8B98, + 0xF94E, 0x8B99, 0xF94F, 0x8EA5, 0xF950, 0x8EA4, 0xF951, 0x8EA3, 0xF952, 0x946E, 0xF953, 0x946D, 0xF954, 0x946F, 0xF955, 0x9471, + 0xF956, 0x9473, 0xF957, 0x9749, 0xF958, 0x9872, 0xF959, 0x995F, 0xF95A, 0x9C68, 0xF95B, 0x9C6E, 0xF95C, 0x9C6D, 0xF95D, 0x9E0B, + 0xF95E, 0x9E0D, 0xF95F, 0x9E10, 0xF960, 0x9E0F, 0xF961, 0x9E12, 0xF962, 0x9E11, 0xF963, 0x9EA1, 0xF964, 0x9EF5, 0xF965, 0x9F09, + 0xF966, 0x9F47, 0xF967, 0x9F78, 0xF968, 0x9F7B, 0xF969, 0x9F7A, 0xF96A, 0x9F79, 0xF96B, 0x571E, 0xF96C, 0x7066, 0xF96D, 0x7C6F, + 0xF96E, 0x883C, 0xF96F, 0x8DB2, 0xF970, 0x8EA6, 0xF971, 0x91C3, 0xF972, 0x9474, 0xF973, 0x9478, 0xF974, 0x9476, 0xF975, 0x9475, + 0xF976, 0x9A60, 0xF977, 0x9C74, 0xF978, 0x9C73, 0xF979, 0x9C71, 0xF97A, 0x9C75, 0xF97B, 0x9E14, 0xF97C, 0x9E13, 0xF97D, 0x9EF6, + 0xF97E, 0x9F0A, 0xF9A1, 0x9FA4, 0xF9A2, 0x7068, 0xF9A3, 0x7065, 0xF9A4, 0x7CF7, 0xF9A5, 0x866A, 0xF9A6, 0x883E, 0xF9A7, 0x883D, + 0xF9A8, 0x883F, 0xF9A9, 0x8B9E, 0xF9AA, 0x8C9C, 0xF9AB, 0x8EA9, 0xF9AC, 0x8EC9, 0xF9AD, 0x974B, 0xF9AE, 0x9873, 0xF9AF, 0x9874, + 0xF9B0, 0x98CC, 0xF9B1, 0x9961, 0xF9B2, 0x99AB, 0xF9B3, 0x9A64, 0xF9B4, 0x9A66, 0xF9B5, 0x9A67, 0xF9B6, 0x9B24, 0xF9B7, 0x9E15, + 0xF9B8, 0x9E17, 0xF9B9, 0x9F48, 0xF9BA, 0x6207, 0xF9BB, 0x6B1E, 0xF9BC, 0x7227, 0xF9BD, 0x864C, 0xF9BE, 0x8EA8, 0xF9BF, 0x9482, + 0xF9C0, 0x9480, 0xF9C1, 0x9481, 0xF9C2, 0x9A69, 0xF9C3, 0x9A68, 0xF9C4, 0x9B2E, 0xF9C5, 0x9E19, 0xF9C6, 0x7229, 0xF9C7, 0x864B, + 0xF9C8, 0x8B9F, 0xF9C9, 0x9483, 0xF9CA, 0x9C79, 0xF9CB, 0x9EB7, 0xF9CC, 0x7675, 0xF9CD, 0x9A6B, 0xF9CE, 0x9C7A, 0xF9CF, 0x9E1D, + 0xF9D0, 0x7069, 0xF9D1, 0x706A, 0xF9D2, 0x9EA4, 0xF9D3, 0x9F7E, 0xF9D4, 0x9F49, 0xF9D5, 0x9F98, 0xF9D6, 0x7881, 0xF9D7, 0x92B9, + 0xF9D8, 0x88CF, 0xF9D9, 0x58BB, 0xF9DA, 0x6052, 0xF9DB, 0x7CA7, 0xF9DC, 0x5AFA, 0xF9DD, 0x2554, 0xF9DE, 0x2566, 0xF9DF, 0x2557, + 0xF9E0, 0x2560, 0xF9E1, 0x256C, 0xF9E2, 0x2563, 0xF9E3, 0x255A, 0xF9E4, 0x2569, 0xF9E5, 0x255D, 0xF9E6, 0x2552, 0xF9E7, 0x2564, + 0xF9E8, 0x2555, 0xF9E9, 0x255E, 0xF9EA, 0x256A, 0xF9EB, 0x2561, 0xF9EC, 0x2558, 0xF9ED, 0x2567, 0xF9EE, 0x255B, 0xF9EF, 0x2553, + 0xF9F0, 0x2565, 0xF9F1, 0x2556, 0xF9F2, 0x255F, 0xF9F3, 0x256B, 0xF9F4, 0x2562, 0xF9F5, 0x2559, 0xF9F6, 0x2568, 0xF9F7, 0x255C, + 0xF9F8, 0x2551, 0xF9F9, 0x2550, 0xF9FA, 0x256D, 0xF9FB, 0x256E, 0xF9FC, 0x2570, 0xF9FD, 0x256F, 0xF9FE, 0x2593, 0, 0 +}; +#endif + +#if FF_CODE_PAGE == 437 || FF_CODE_PAGE == 0 +static const WCHAR uc437[] = { /* CP437(U.S.) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 720 || FF_CODE_PAGE == 0 +static const WCHAR uc720[] = { /* CP720(Arabic) to Unicode conversion table */ + 0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627, + 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A, + 0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0x0650, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 737 || FF_CODE_PAGE == 0 +static const WCHAR uc737[] = { /* CP737(Greek) to Unicode conversion table */ + 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0, + 0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8, + 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E, + 0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 771 || FF_CODE_PAGE == 0 +static const WCHAR uc771[] = { /* CP771(KBL) to Unicode conversion table */ + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, + 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x0104, 0x0105, 0x010C, 0x010D, + 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, + 0x0118, 0x0119, 0x0116, 0x0117, 0x012E, 0x012F, 0x0160, 0x0161, 0x0172, 0x0173, 0x016A, 0x016B, 0x017D, 0x017E, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 775 || FF_CODE_PAGE == 0 +static const WCHAR uc775[] = { /* CP775(Baltic) to Unicode conversion table */ + 0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4, + 0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D, + 0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019, + 0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 850 || FF_CODE_PAGE == 0 +static const WCHAR uc850[] = { /* CP850(Latin 1) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 852 || FF_CODE_PAGE == 0 +static const WCHAR uc852[] = { /* CP852(Latin 2) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106, + 0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4, + 0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 855 || FF_CODE_PAGE == 0 +static const WCHAR uc855[] = { /* CP855(Cyrillic) to Unicode conversion table */ + 0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408, + 0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A, + 0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580, + 0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116, + 0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 857 || FF_CODE_PAGE == 0 +static const WCHAR uc857[] = { /* CP857(Turkish) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 860 || FF_CODE_PAGE == 0 +static const WCHAR uc860[] = { /* CP860(Portuguese) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E3, 0x00E0, 0x00C1, 0x00E7, 0x00EA, 0x00CA, 0x00E8, 0x00CD, 0x00D4, 0x00EC, 0x00C3, 0x00C2, + 0x00C9, 0x00C0, 0x00C8, 0x00F4, 0x00F5, 0x00F2, 0x00DA, 0x00F9, 0x00CC, 0x00D5, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x20A7, 0x00D3, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00D2, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 861 || FF_CODE_PAGE == 0 +static const WCHAR uc861[] = { /* CP861(Icelandic) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00D0, 0x00F0, 0x00DE, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00FE, 0x00FB, 0x00DD, 0x00FD, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00C1, 0x00CD, 0x00D3, 0x00DA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 862 || FF_CODE_PAGE == 0 +static const WCHAR uc862[] = { /* CP862(Hebrew) to Unicode conversion table */ + 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, + 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 863 || FF_CODE_PAGE == 0 +static const WCHAR uc863[] = { /* CP863(Canadian French) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00C2, 0x00E0, 0x00B6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x2017, 0x00C0, + 0x00C9, 0x00C8, 0x00CA, 0x00F4, 0x00CB, 0x00CF, 0x00FB, 0x00F9, 0x00A4, 0x00D4, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x00DB, 0x0192, + 0x00A6, 0x00B4, 0x00F3, 0x00FA, 0x00A8, 0x00BB, 0x00B3, 0x00AF, 0x00CE, 0x3210, 0x00AC, 0x00BD, 0x00BC, 0x00BE, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2219, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 864 || FF_CODE_PAGE == 0 +static const WCHAR uc864[] = { /* CP864(Arabic) to Unicode conversion table */ + 0x00B0, 0x00B7, 0x2219, 0x221A, 0x2592, 0x2500, 0x2502, 0x253C, 0x2524, 0x252C, 0x251C, 0x2534, 0x2510, 0x250C, 0x2514, 0x2518, + 0x03B2, 0x221E, 0x03C6, 0x00B1, 0x00BD, 0x00BC, 0x2248, 0x00AB, 0x00BB, 0xFEF7, 0xFEF8, 0x0000, 0x0000, 0xFEFB, 0xFEFC, 0x0000, + 0x00A0, 0x00AD, 0xFE82, 0x00A3, 0x00A4, 0xFE84, 0x0000, 0x20AC, 0xFE8E, 0xFE8F, 0xFE95, 0xFE99, 0x060C, 0xFE9D, 0xFEA1, 0xFEA5, + 0x0660, 0x0661, 0x0662, 0x0663, 0x0664, 0x0665, 0x0666, 0x0667, 0x0668, 0x0669, 0xFED1, 0x061B, 0xFEB1, 0xFEB5, 0xFEB9, 0x061F, + 0x00A2, 0xFE80, 0xFE81, 0xFE83, 0xFE85, 0xFECA, 0xFE8B, 0xFE8D, 0xFE91, 0xFE93, 0xFE97, 0xFE9B, 0xFE9F, 0xFEA3, 0xFEA7, 0xFEA9, + 0xFEAB, 0xFEAD, 0xFEAF, 0xFEB3, 0xFEB7, 0xFEBB, 0xFEBF, 0xFEC1, 0xFEC5, 0xFECB, 0xFECF, 0x00A6, 0x00AC, 0x00F7, 0x00D7, 0xFEC9, + 0x0640, 0xFED3, 0xFED7, 0xFEDB, 0xFEDF, 0xFEE3, 0xFEE7, 0xFEEB, 0xFEED, 0xFEEF, 0xFEF3, 0xFEBD, 0xFECC, 0xFECE, 0xFECD, 0xFEE1, + 0xFE7D, 0x0651, 0xFEE5, 0xFEE9, 0xFEEC, 0xFEF0, 0xFEF2, 0xFED0, 0xFED5, 0xFEF5, 0xFEF6, 0xFEDD, 0xFED9, 0xFEF1, 0x25A0, 0x0000 +}; +#endif +#if FF_CODE_PAGE == 865 || FF_CODE_PAGE == 0 +static const WCHAR uc865[] = { /* CP865(Nordic) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C5, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00A4, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 866 || FF_CODE_PAGE == 0 +static const WCHAR uc866[] = { /* CP866(Russian) to Unicode conversion table */ + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, + 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, + 0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0 +}; +#endif +#if FF_CODE_PAGE == 869 || FF_CODE_PAGE == 0 +static const WCHAR uc869[] = { /* CP869(Greek 2) to Unicode conversion table */ + 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x0386, 0x00B7, 0x00B7, 0x00AC, 0x00A6, 0x2018, 0x2019, 0x0388, 0x2015, 0x0389, + 0x038A, 0x03AA, 0x038C, 0x00B7, 0x00B7, 0x038E, 0x03AB, 0x00A9, 0x038F, 0x00B2, 0x00B3, 0x03AC, 0x00A3, 0x03AD, 0x03AE, 0x03AF, + 0x03CA, 0x0390, 0x03CC, 0x03CD, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x00BD, 0x0398, 0x0399, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x039A, 0x039B, 0x039C, 0x039D, 0x2563, 0x2551, 0x2557, 0x255D, 0x039E, 0x039F, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0A30, 0x03A1, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x03A3, + 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x2518, 0x250C, 0x2588, 0x2584, 0x03B4, 0x03B5, 0x2580, + 0x03B6, 0x03B7, 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x0384, + 0x00AD, 0x00B1, 0x03C5, 0x03C6, 0x03C7, 0x00A7, 0x03C8, 0x0385, 0x00B0, 0x00A8, 0x03C9, 0x03CB, 0x03B0, 0x03CE, 0x25A0, 0x00A0 +}; +#endif + + + + +/*------------------------------------------------------------------------*/ +/* OEM <==> Unicode conversions for static code page configuration */ +/* SBCS fixed code page */ +/*------------------------------------------------------------------------*/ + +#if FF_CODE_PAGE != 0 && FF_CODE_PAGE < 900 +WCHAR ff_uni2oem ( /* Returns OEM code character, zero on error */ + DWORD uni, /* UTF-16 encoded character to be converted */ + WORD cp /* Code page for the conversion */ +) +{ + WCHAR c = 0; + const WCHAR *p = CVTBL(uc, FF_CODE_PAGE); + + + if (uni < 0x80) { /* ASCII? */ + c = (WCHAR)uni; + + } else { /* Non-ASCII */ + if (uni < 0x10000 && cp == FF_CODE_PAGE) { /* Is it in BMP and valid code page? */ + for (c = 0; c < 0x80 && uni != p[c]; c++) ; + c = (c + 0x80) & 0xFF; + } + } + + return c; +} + +WCHAR ff_oem2uni ( /* Returns Unicode character in UTF-16, zero on error */ + WCHAR oem, /* OEM code to be converted */ + WORD cp /* Code page for the conversion */ +) +{ + WCHAR c = 0; + const WCHAR *p = CVTBL(uc, FF_CODE_PAGE); + + + if (oem < 0x80) { /* ASCII? */ + c = oem; + + } else { /* Extended char */ + if (cp == FF_CODE_PAGE) { /* Is it a valid code page? */ + if (oem < 0x100) c = p[oem - 0x80]; + } + } + + return c; +} + +#endif + + + +/*------------------------------------------------------------------------*/ +/* OEM <==> Unicode conversions for static code page configuration */ +/* DBCS fixed code page */ +/*------------------------------------------------------------------------*/ + +#if FF_CODE_PAGE >= 900 +WCHAR ff_uni2oem ( /* Returns OEM code character, zero on error */ + DWORD uni, /* UTF-16 encoded character to be converted */ + WORD cp /* Code page for the conversion */ +) +{ + const WCHAR *p; + WCHAR c = 0, uc; + UINT i = 0, n, li, hi; + + + if (uni < 0x80) { /* ASCII? */ + c = (WCHAR)uni; + + } else { /* Non-ASCII */ + if (uni < 0x10000 && cp == FF_CODE_PAGE) { /* Is it in BMP and valid code page? */ + uc = (WCHAR)uni; + p = CVTBL(uni2oem, FF_CODE_PAGE); + hi = sizeof CVTBL(uni2oem, FF_CODE_PAGE) / 4 - 1; + li = 0; + for (n = 16; n; n--) { + i = li + (hi - li) / 2; + if (uc == p[i * 2]) break; + if (uc > p[i * 2]) { + li = i; + } else { + hi = i; + } + } + if (n != 0) c = p[i * 2 + 1]; + } + } + + return c; +} + + +WCHAR ff_oem2uni ( /* Returns Unicode character in UTF-16, zero on error */ + WCHAR oem, /* OEM code to be converted */ + WORD cp /* Code page for the conversion */ +) +{ + const WCHAR *p; + WCHAR c = 0; + UINT i = 0, n, li, hi; + + + if (oem < 0x80) { /* ASCII? */ + c = oem; + + } else { /* Extended char */ + if (cp == FF_CODE_PAGE) { /* Is it valid code page? */ + p = CVTBL(oem2uni, FF_CODE_PAGE); + hi = sizeof CVTBL(oem2uni, FF_CODE_PAGE) / 4 - 1; + li = 0; + for (n = 16; n; n--) { + i = li + (hi - li) / 2; + if (oem == p[i * 2]) break; + if (oem > p[i * 2]) { + li = i; + } else { + hi = i; + } + } + if (n != 0) c = p[i * 2 + 1]; + } + } + + return c; +} +#endif + + + +/*------------------------------------------------------------------------*/ +/* OEM <==> Unicode conversions for dynamic code page configuration */ +/*------------------------------------------------------------------------*/ + +#if FF_CODE_PAGE == 0 + +static const WORD cp_code[] = { 437, 720, 737, 771, 775, 850, 852, 855, 857, 860, 861, 862, 863, 864, 865, 866, 869, 0}; +static const WCHAR* const cp_table[] = {uc437, uc720, uc737, uc771, uc775, uc850, uc852, uc855, uc857, uc860, uc861, uc862, uc863, uc864, uc865, uc866, uc869, 0}; + + +WCHAR ff_uni2oem ( /* Returns OEM code character, zero on error */ + DWORD uni, /* UTF-16 encoded character to be converted */ + WORD cp /* Code page for the conversion */ +) +{ + const WCHAR *p; + WCHAR c = 0, uc; + UINT i, n, li, hi; + + + if (uni < 0x80) { /* ASCII? */ + c = (WCHAR)uni; + + } else { /* Non-ASCII */ + if (uni < 0x10000) { /* Is it in BMP? */ + uc = (WCHAR)uni; + p = 0; + if (cp < 900) { /* SBCS */ + for (i = 0; cp_code[i] != 0 && cp_code[i] != cp; i++) ; /* Get conversion table */ + p = cp_table[i]; + if (p) { /* Is it valid code page ? */ + for (c = 0; c < 0x80 && uc != p[c]; c++) ; /* Find OEM code in the table */ + c = (c + 0x80) & 0xFF; + } + } else { /* DBCS */ + switch (cp) { /* Get conversion table */ + case 932 : p = uni2oem932; hi = sizeof uni2oem932 / 4 - 1; break; + case 936 : p = uni2oem936; hi = sizeof uni2oem936 / 4 - 1; break; + case 949 : p = uni2oem949; hi = sizeof uni2oem949 / 4 - 1; break; + case 950 : p = uni2oem950; hi = sizeof uni2oem950 / 4 - 1; break; + } + if (p) { /* Is it valid code page? */ + li = 0; + for (n = 16; n; n--) { /* Find OEM code */ + i = li + (hi - li) / 2; + if (uc == p[i * 2]) break; + if (uc > p[i * 2]) { + li = i; + } else { + hi = i; + } + } + if (n != 0) c = p[i * 2 + 1]; + } + } + } + } + + return c; +} + + +WCHAR ff_oem2uni ( /* Returns Unicode character in UTF-16, zero on error */ + WCHAR oem, /* OEM code to be converted (DBC if >=0x100) */ + WORD cp /* Code page for the conversion */ +) +{ + const WCHAR *p; + WCHAR c = 0; + UINT i, n, li, hi; + + + if (oem < 0x80) { /* ASCII? */ + c = oem; + + } else { /* Extended char */ + p = 0; + if (cp < 900) { /* SBCS */ + for (i = 0; cp_code[i] != 0 && cp_code[i] != cp; i++) ; /* Get table */ + p = cp_table[i]; + if (p) { /* Is it a valid CP ? */ + if (oem < 0x100) c = p[oem - 0x80]; + } + } else { /* DBCS */ + switch (cp) { + case 932 : p = oem2uni932; hi = sizeof oem2uni932 / 4 - 1; break; + case 936 : p = oem2uni936; hi = sizeof oem2uni936 / 4 - 1; break; + case 949 : p = oem2uni949; hi = sizeof oem2uni949 / 4 - 1; break; + case 950 : p = oem2uni950; hi = sizeof oem2uni950 / 4 - 1; break; + } + if (p) { + li = 0; + for (n = 16; n; n--) { + i = li + (hi - li) / 2; + if (oem == p[i * 2]) break; + if (oem > p[i * 2]) { + li = i; + } else { + hi = i; + } + } + if (n != 0) c = p[i * 2 + 1]; + } + } + } + + return c; +} +#endif + + + +/*------------------------------------------------------------------------*/ +/* Unicode up-case conversion */ +/*------------------------------------------------------------------------*/ + +DWORD ff_wtoupper ( /* Returns up-converted code point */ + DWORD uni /* Unicode code point to be up-converted */ +) +{ + const WORD *p; + WORD uc, bc, nc, cmd; + static const WORD cvt1[] = { /* Compressed up conversion table for U+0000 - U+0FFF */ + /* Basic Latin */ + 0x0061,0x031A, + /* Latin-1 Supplement */ + 0x00E0,0x0317, + 0x00F8,0x0307, + 0x00FF,0x0001,0x0178, + /* Latin Extended-A */ + 0x0100,0x0130, + 0x0132,0x0106, + 0x0139,0x0110, + 0x014A,0x012E, + 0x0179,0x0106, + /* Latin Extended-B */ + 0x0180,0x004D,0x0243,0x0181,0x0182,0x0182,0x0184,0x0184,0x0186,0x0187,0x0187,0x0189,0x018A,0x018B,0x018B,0x018D,0x018E,0x018F,0x0190,0x0191,0x0191,0x0193,0x0194,0x01F6,0x0196,0x0197,0x0198,0x0198,0x023D,0x019B,0x019C,0x019D,0x0220,0x019F,0x01A0,0x01A0,0x01A2,0x01A2,0x01A4,0x01A4,0x01A6,0x01A7,0x01A7,0x01A9,0x01AA,0x01AB,0x01AC,0x01AC,0x01AE,0x01AF,0x01AF,0x01B1,0x01B2,0x01B3,0x01B3,0x01B5,0x01B5,0x01B7,0x01B8,0x01B8,0x01BA,0x01BB,0x01BC,0x01BC,0x01BE,0x01F7,0x01C0,0x01C1,0x01C2,0x01C3,0x01C4,0x01C5,0x01C4,0x01C7,0x01C8,0x01C7,0x01CA,0x01CB,0x01CA, + 0x01CD,0x0110, + 0x01DD,0x0001,0x018E, + 0x01DE,0x0112, + 0x01F3,0x0003,0x01F1,0x01F4,0x01F4, + 0x01F8,0x0128, + 0x0222,0x0112, + 0x023A,0x0009,0x2C65,0x023B,0x023B,0x023D,0x2C66,0x023F,0x0240,0x0241,0x0241, + 0x0246,0x010A, + /* IPA Extensions */ + 0x0253,0x0040,0x0181,0x0186,0x0255,0x0189,0x018A,0x0258,0x018F,0x025A,0x0190,0x025C,0x025D,0x025E,0x025F,0x0193,0x0261,0x0262,0x0194,0x0264,0x0265,0x0266,0x0267,0x0197,0x0196,0x026A,0x2C62,0x026C,0x026D,0x026E,0x019C,0x0270,0x0271,0x019D,0x0273,0x0274,0x019F,0x0276,0x0277,0x0278,0x0279,0x027A,0x027B,0x027C,0x2C64,0x027E,0x027F,0x01A6,0x0281,0x0282,0x01A9,0x0284,0x0285,0x0286,0x0287,0x01AE,0x0244,0x01B1,0x01B2,0x0245,0x028D,0x028E,0x028F,0x0290,0x0291,0x01B7, + /* Greek, Coptic */ + 0x037B,0x0003,0x03FD,0x03FE,0x03FF, + 0x03AC,0x0004,0x0386,0x0388,0x0389,0x038A, + 0x03B1,0x0311, + 0x03C2,0x0002,0x03A3,0x03A3, + 0x03C4,0x0308, + 0x03CC,0x0003,0x038C,0x038E,0x038F, + 0x03D8,0x0118, + 0x03F2,0x000A,0x03F9,0x03F3,0x03F4,0x03F5,0x03F6,0x03F7,0x03F7,0x03F9,0x03FA,0x03FA, + /* Cyrillic */ + 0x0430,0x0320, + 0x0450,0x0710, + 0x0460,0x0122, + 0x048A,0x0136, + 0x04C1,0x010E, + 0x04CF,0x0001,0x04C0, + 0x04D0,0x0144, + /* Armenian */ + 0x0561,0x0426, + + 0x0000 /* EOT */ + }; + static const WORD cvt2[] = { /* Compressed up conversion table for U+1000 - U+FFFF */ + /* Phonetic Extensions */ + 0x1D7D,0x0001,0x2C63, + /* Latin Extended Additional */ + 0x1E00,0x0196, + 0x1EA0,0x015A, + /* Greek Extended */ + 0x1F00,0x0608, + 0x1F10,0x0606, + 0x1F20,0x0608, + 0x1F30,0x0608, + 0x1F40,0x0606, + 0x1F51,0x0007,0x1F59,0x1F52,0x1F5B,0x1F54,0x1F5D,0x1F56,0x1F5F, + 0x1F60,0x0608, + 0x1F70,0x000E,0x1FBA,0x1FBB,0x1FC8,0x1FC9,0x1FCA,0x1FCB,0x1FDA,0x1FDB,0x1FF8,0x1FF9,0x1FEA,0x1FEB,0x1FFA,0x1FFB, + 0x1F80,0x0608, + 0x1F90,0x0608, + 0x1FA0,0x0608, + 0x1FB0,0x0004,0x1FB8,0x1FB9,0x1FB2,0x1FBC, + 0x1FCC,0x0001,0x1FC3, + 0x1FD0,0x0602, + 0x1FE0,0x0602, + 0x1FE5,0x0001,0x1FEC, + 0x1FF3,0x0001,0x1FFC, + /* Letterlike Symbols */ + 0x214E,0x0001,0x2132, + /* Number forms */ + 0x2170,0x0210, + 0x2184,0x0001,0x2183, + /* Enclosed Alphanumerics */ + 0x24D0,0x051A, + 0x2C30,0x042F, + /* Latin Extended-C */ + 0x2C60,0x0102, + 0x2C67,0x0106, 0x2C75,0x0102, + /* Coptic */ + 0x2C80,0x0164, + /* Georgian Supplement */ + 0x2D00,0x0826, + /* Full-width */ + 0xFF41,0x031A, + + 0x0000 /* EOT */ + }; + + + if (uni < 0x10000) { /* Is it in BMP? */ + uc = (WORD)uni; + p = uc < 0x1000 ? cvt1 : cvt2; + for (;;) { + bc = *p++; /* Get the block base */ + if (bc == 0 || uc < bc) break; /* Not matched? */ + nc = *p++; cmd = nc >> 8; nc &= 0xFF; /* Get processing command and block size */ + if (uc < bc + nc) { /* In the block? */ + switch (cmd) { + case 0: uc = p[uc - bc]; break; /* Table conversion */ + case 1: uc -= (uc - bc) & 1; break; /* Case pairs */ + case 2: uc -= 16; break; /* Shift -16 */ + case 3: uc -= 32; break; /* Shift -32 */ + case 4: uc -= 48; break; /* Shift -48 */ + case 5: uc -= 26; break; /* Shift -26 */ + case 6: uc += 8; break; /* Shift +8 */ + case 7: uc -= 80; break; /* Shift -80 */ + case 8: uc -= 0x1C60; break; /* Shift -0x1C60 */ + } + break; + } + if (cmd == 0) p += nc; /* Skip table if needed */ + } + uni = uc; + } + + return uni; +} + + +#endif /* #if FF_USE_LFN */ diff --git a/lib-hal/include/console.h b/lib-hal/include/console.h index 38aab859..5c010711 100644 --- a/lib-hal/include/console.h +++ b/lib-hal/include/console.h @@ -2,7 +2,7 @@ * @file console.h * */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -56,11 +56,11 @@ typedef enum { # endif #elif defined (CONSOLE_NULL) inline void console_init(void) {} -inline void console_putc(__attribute__((unused)) int i) {} -inline void console_puts(__attribute__((unused)) const char *p) {} -inline void console_write(__attribute__((unused)) const char *p, __attribute__((unused)) unsigned int i) {} -inline void console_status(__attribute__((unused)) uint32_t i, __attribute__((unused)) const char *p) {} -inline void console_error(__attribute__((unused)) const char *p) {} +inline void console_putc([[maybe_unused]] int i) {} +inline void console_puts([[maybe_unused]] const char *p) {} +inline void console_write([[maybe_unused]] const char *p, [[maybe_unused]] unsigned int i) {} +inline void console_status([[maybe_unused]] uint32_t i, [[maybe_unused]] const char *p) {} +extern "C" inline void console_error([[maybe_unused]] const char *p) {} #else #ifdef __cplusplus extern "C" { @@ -74,21 +74,19 @@ extern void console_set_bg_color(uint16_t); #endif #endif +#if !defined (CONSOLE_NULL) +extern void console_init(); #ifdef __cplusplus extern "C" { #endif - -#if !defined (CONSOLE_NULL) -extern void console_init(void); extern void console_putc(int); extern void console_puts(const char*); extern void console_write(const char*, unsigned int); extern void console_status(uint32_t, const char *); extern void console_error(const char*); -#endif - #ifdef __cplusplus } #endif +#endif #endif /* CONSOLE_H_ */ diff --git a/lib-debug/include/debug.h b/lib-hal/include/debug.h old mode 100644 new mode 100755 similarity index 74% rename from lib-debug/include/debug.h rename to lib-hal/include/debug.h index e98f90d6..ef8e29d5 --- a/lib-debug/include/debug.h +++ b/lib-hal/include/debug.h @@ -2,7 +2,7 @@ * @file debug.h * */ -/* Copyright (C) 2018-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -30,17 +30,9 @@ #include #define DEBUG_ENTRY printf("--> %s:%s:%d\n", __FILE__, __func__, __LINE__); #define DEBUG_EXIT printf("<-- %s:%s:%d\n", __FILE__, __func__, __LINE__); - #define DEBUG1_ENTRY printf("\t--> %s:%s:%d\n", __FILE__, __func__, __LINE__); - #define DEBUG1_EXIT printf("\t<-- %s:%s:%d\n", __FILE__, __func__, __LINE__); - #define DEBUG2_ENTRY printf("\t\t--> %s:%s:%d\n", __FILE__, __func__, __LINE__); - #define DEBUG2_EXIT printf("\t\t<-- %s:%s:%d\n", __FILE__, __func__, __LINE__); #else #define DEBUG_ENTRY ((void)0); #define DEBUG_EXIT ((void)0); - #define DEBUG1_ENTRY ((void)0); - #define DEBUG1_EXIT ((void)0); - #define DEBUG2_ENTRY ((void)0); - #define DEBUG2_EXIT ((void)0); #endif #ifdef NDEBUG @@ -50,14 +42,8 @@ #define debug_print_bits(x) ((void)0) #else #include - #ifdef __cplusplus - extern "C" { - #endif - extern void debug_dump(const void *, uint16_t); - extern void debug_print_bits(uint32_t); - #ifdef __cplusplus - } - #endif + void debug_dump(const void *, uint32_t); + void debug_print_bits(uint32_t); #if defined (__linux__) || defined (__CYGWIN__) #define DEBUG_PRINTF(FORMAT, ...) \ fprintf(stderr, "%s() %s, line %i: " FORMAT "\n", __func__, __FILE__, __LINE__, __VA_ARGS__) diff --git a/lib-hal/include/device/usb/host.h b/lib-hal/include/device/usb/host.h new file mode 100644 index 00000000..fbce6622 --- /dev/null +++ b/lib-hal/include/device/usb/host.h @@ -0,0 +1,43 @@ +/* + * host.h + */ + +#ifndef DEVICE_USB_HOSTMSC_H_ +#define DEVICE_USB_HOSTMSC_H_ + +namespace usb { +namespace host { + +enum class Status { + NOT_AVAILABLE, + DISCONNECTED, + RESET, + SPEED_AVAILALBE, + ATTACHED, + CONNECTED, + ENUMERATION_COMPLETED, + READY, + DEVICE_NOT_SUPPORTED, + UNRECOVERABLE_ERROR +}; + +enum class Speed { + FAULT, + LOW, + FULL, + HIGH +}; + +enum class Class { + NOT_SUPPORTED, + MSC, + HID +}; + +Status get_status(); +Speed get_speed(); +Class get_class(); +} // namespace host +} // namespace usb + +#endif /* DEVICE_USB_HOSTMSC_H_ */ diff --git a/lib-hal/include/gd32/hal_api.h b/lib-hal/include/gd32/hal_api.h index a41381ed..cf6f7045 100644 --- a/lib-hal/include/gd32/hal_api.h +++ b/lib-hal/include/gd32/hal_api.h @@ -28,20 +28,4 @@ #define FUNC_PREFIX(x) gd32_##x -#if defined __cplusplus -# include -# if !defined(GD32_UDELAY) -# define GD32_UDELAY - void udelay(uint32_t us, uint32_t offset = 0); -# endif -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - #endif /* GD32_HAL_API_H_ */ diff --git a/lib-hal/include/gd32/hal_i2c.h b/lib-hal/include/gd32/hal_i2c.h index f6e7b057..925eb224 100644 --- a/lib-hal/include/gd32/hal_i2c.h +++ b/lib-hal/include/gd32/hal_i2c.h @@ -26,6 +26,7 @@ #ifndef GD32_HAL_I2C_H_ #define GD32_HAL_I2C_H_ +#include "gd32.h" #include "gd32_i2c.h" #endif /* GD32_HAL_I2C_H_ */ diff --git a/lib-hal/include/gd32/hal_spi.h b/lib-hal/include/gd32/hal_spi.h index 348bb332..6e8cf335 100644 --- a/lib-hal/include/gd32/hal_spi.h +++ b/lib-hal/include/gd32/hal_spi.h @@ -2,7 +2,7 @@ * @file hal_spi.h * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,12 +28,6 @@ #include "gd32_spi.h" -namespace hal { -namespace spi { - -} // namespace spi -} // namespace hal - #define SPI_MODE0 GD32_SPI_MODE0 #define SPI_MODE1 GD32_SPI_MODE1 #define SPI_MODE2 GD32_SPI_MODE2 diff --git a/lib-hal/include/gd32/hal_uart.h b/lib-hal/include/gd32/hal_uart.h index 665807a7..205e38a6 100644 --- a/lib-hal/include/gd32/hal_uart.h +++ b/lib-hal/include/gd32/hal_uart.h @@ -2,7 +2,7 @@ * @file hal_uart.h * */ -/* Copyright (C) 2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-hal/include/gd32/hardware.h b/lib-hal/include/gd32/hardware.h index bda7f289..98254b61 100644 --- a/lib-hal/include/gd32/hardware.h +++ b/lib-hal/include/gd32/hardware.h @@ -2,7 +2,7 @@ * @file hardware.h * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,6 +27,7 @@ #define GD32_HARDWARE_H_ #include +#include #include #include @@ -34,12 +35,19 @@ #include "gd32.h" #include "gd32_adc.h" -#include "gd32_micros.h" + +#if !defined (CONFIG_LEDBLINK_USE_PANELLED) && (defined (GD32F4XX) || defined(GD32H7XX)) +# define HAL_HAVE_PORT_BIT_TOGGLE +#endif #if defined (ENABLE_USB_HOST) && defined (CONFIG_USB_HOST_MSC) extern "C" { #include "usbh_core.h" -extern usbh_host usb_host_msc; +#if defined (GD32H7XX) || defined (GD32F4XX) + extern usbh_host usb_host_msc; +#else + extern usbh_host usb_host; +#endif } #endif @@ -50,12 +58,13 @@ extern usbh_host usb_host_msc; void emac_debug_run(); #endif -#if defined (USE_LEDBLINK_BITBANGING595) -# include "gd32_bitbanging595.h" -# include "panel_led.h" +#ifdef NDEBUG + extern "C" void console_error(const char *); #endif -extern volatile uint32_t s_nSysTickMillis; +#include "panel_led.h" + +#include "debug.h" class Hardware { public: @@ -65,40 +74,77 @@ class Hardware { return 0; // FIXME GetReleaseId } - void GetUuid(uuid_t out); + void GetUuid(uuid_t out) { + memcpy(out, m_uuid, sizeof(uuid_t)); + } uint32_t Millis() { - extern volatile uint32_t s_nSysTickMillis; - return s_nSysTickMillis; +#if defined (CONFIG_HAL_USE_SYSTICK) + extern volatile uint32_t gv_nSysTickMillis; + return gv_nSysTickMillis; +#else + extern uint32_t timer6_get_elapsed_milliseconds(); + return timer6_get_elapsed_milliseconds(); +#endif } uint32_t Micros() { - return micros(); + static uint32_t nMicrosPrevious; + static uint32_t nResult; + const auto nMicros = DWT->CYCCNT / (MCU_CLOCK_FREQ / 1000000U); + + if (nMicros > nMicrosPrevious) { + nResult += (nMicros - nMicrosPrevious); + } else { + nResult += ((UINT32_MAX / (MCU_CLOCK_FREQ / 1000000U)) - nMicrosPrevious + nMicros); + } + + nMicrosPrevious = nMicros; + + return nResult; } - uint32_t GetUpTime() { - return Millis() / 1000U; + uint32_t GetUpTime() const { + extern struct HwTimersSeconds g_Seconds; + return g_Seconds.nUptime; } - bool SetTime(const struct tm *pTime); - void GetTime(struct tm *pTime); + bool SetTime(__attribute__((unused)) const struct tm *pTime) { +#if !defined(DISABLE_RTC) + m_HwClock.Set(pTime); + return true; +#else + return false; +#endif + } - const char *GetBoardName(uint8_t &nLength) { +#if !defined(DISABLE_RTC) + bool SetAlarm(const struct tm *pTime) { + const auto b = m_HwClock.AlarmSet(pTime); + return b; + } + + void GetAlarm(struct tm *pTime) { + m_HwClock.AlarmGet(pTime); + } +#endif + + const char *GetBoardName(uint8_t& nLength) { nLength = sizeof(GD32_BOARD_NAME) - 1U; return GD32_BOARD_NAME; } - const char *GetSysName(uint8_t &nLength) { + const char* GetSysName(uint8_t& nLength) { nLength = 8; return "Embedded"; } - const char *GetSocName(uint8_t &nLength) { - nLength = 5; - return "GD32F"; + const char* GetSocName(uint8_t& nLength) { + nLength = 4; + return "GD32"; } - const char *GetCpuName(uint8_t &nLength) { + const char *GetCpuName(uint8_t& nLength) { nLength = sizeof(GD32_MCU_NAME) - 1U; return GD32_MCU_NAME; } @@ -112,8 +158,8 @@ class Hardware { } void WatchdogInit() { - const auto status = fwdgt_config(0xFFFF, FWDGT_PSC_DIV16); - m_bIsWatchdog = (SUCCESS == status); + m_bIsWatchdog = (SUCCESS == fwdgt_config(0xFFFF, FWDGT_PSC_DIV16)); + if (m_bIsWatchdog) { fwdgt_enable(); } @@ -138,11 +184,11 @@ class Hardware { return gd32_adc_gettemp(); } - float GetCoreTemperatureMin() { + float GetCoreTemperatureMin() const { return -40.0f; } - float GetCoreTemperatureMax() { + float GetCoreTemperatureMax() const { return 85.0f; } @@ -152,35 +198,85 @@ class Hardware { return m_Mode; } - void Run() { -#if defined (ENABLE_USB_HOST) && defined (CONFIG_USB_HOST_MSC) - usbh_core_task(&usb_host_msc); + struct Timer { + uint32_t nExpireTime; + uint32_t nIntervalMillis; + int32_t nId; + hal::TimerCallback callback; + }; + + int32_t SoftwareTimerAdd(const uint32_t nIntervalMillis, const hal::TimerCallback callback) { + if (m_nTimersCount >= hal::SOFTWARE_TIMERS_MAX) { +#ifdef NDEBUG + console_error("SoftwareTimerAdd\n"); #endif - if (__builtin_expect (m_nTicksPerSecond != 0, 1)) { - if (__builtin_expect (!(s_nSysTickMillis - m_nMillisPrevious < m_nTicksPerSecond), 1)) { - m_nMillisPrevious = s_nSysTickMillis; + return -1; + } - m_nToggleLed ^= 0x1; + const auto nCurrentTime = Hardware::Millis(); - if (m_nToggleLed != 0) { -#if defined (USE_LEDBLINK_BITBANGING595) - hal::panel_led_on(hal::panelled::ACTIVITY); -#else - GPIO_BOP(LED_BLINK_GPIO_PORT) = LED_BLINK_PIN; -#endif - } else { -#if defined (USE_LEDBLINK_BITBANGING595) - hal::panel_led_off(hal::panelled::ACTIVITY); -#else - GPIO_BC(LED_BLINK_GPIO_PORT) = LED_BLINK_PIN; -#endif + Timer newTimer = { + .nExpireTime = nCurrentTime + nIntervalMillis, + .nIntervalMillis = nIntervalMillis, + .nId = m_nNextId++, + .callback = callback, + }; + + m_Timers[m_nTimersCount++] = newTimer; + + return newTimer.nId; + } + + bool SoftwareTimerDelete(int32_t& nId) { + if (nId >= 0) { + for (uint32_t i = 0; i < m_nTimersCount; ++i) { + if (m_Timers[i].nId == nId) { + for (uint32_t j = i; j < m_nTimersCount - 1; ++j) { + m_Timers[j] = m_Timers[j + 1]; + } + --m_nTimersCount; + nId = -1; + return true; } } } -#if defined (USE_LEDBLINK_BITBANGING595) - bitBanging595.Run(); + return false; + } + + bool SoftwareTimerChange(const int32_t nId, const uint32_t nIntervalMillis) { + if (nId >= 0) { + for (uint32_t i = 0; i < m_nTimersCount; ++i) { + if (m_Timers[i].nId == nId) { + m_Timers[i].nExpireTime = Hardware::Millis() + nIntervalMillis; + m_Timers[i].nIntervalMillis = nIntervalMillis; + + return true; + } + } + } + + return false; + } + + void Run() { +#if defined (ENABLE_USB_HOST) && defined (CONFIG_USB_HOST_MSC) +# if defined (GD32H7XX) || defined (GD32F4XX) + usbh_core_task(&usb_host_msc); +# else + usbh_core_task(&usb_host); +# endif #endif + const auto nCurrentTime = Hardware::Get()->Millis(); + + for (uint32_t i = 0; i < m_nTimersCount; i++) { + if (m_Timers[i].nExpireTime <= nCurrentTime) { + m_Timers[i].callback(); + m_Timers[i].nExpireTime = nCurrentTime + m_Timers[i].nIntervalMillis; + } + } + + hal::panel_led_run(); #if defined (DEBUG_STACK) stack_debug_run(); @@ -198,54 +294,94 @@ class Hardware { private: void RebootHandler(); + static void ledblink() { +#if defined(HAL_HAVE_PORT_BIT_TOGGLE) + GPIO_TG(LED_BLINK_GPIO_PORT) = LED_BLINK_PIN; +#else + m_nToggleLed = -m_nToggleLed; + + if (m_nToggleLed > 0) { +# if defined (CONFIG_LEDBLINK_USE_PANELLED) + hal::panel_led_on(hal::panelled::ACTIVITY); +# else + GPIO_BOP(LED_BLINK_GPIO_PORT) = LED_BLINK_PIN; +# endif + } else { +# if defined (CONFIG_LEDBLINK_USE_PANELLED) + hal::panel_led_off(hal::panelled::ACTIVITY); +# else + GPIO_BC(LED_BLINK_GPIO_PORT) = LED_BLINK_PIN; +# endif + } +#endif + } + void SetFrequency(const uint32_t nFreqHz) { + DEBUG_ENTRY + DEBUG_PRINTF("m_nTimerId=%d, nFreqHz=%u", m_nTimerId, nFreqHz); + + if (m_nTimerId < 0) { + m_nTimerId = SoftwareTimerAdd((1000U / nFreqHz), ledblink); + DEBUG_EXIT + return; + } + switch (nFreqHz) { case 0: - m_nTicksPerSecond = 0; -#if defined (USE_LEDBLINK_BITBANGING595) + SoftwareTimerDelete(m_nTimerId); +#if defined (CONFIG_LEDBLINK_USE_PANELLED) hal::panel_led_off(hal::panelled::ACTIVITY); #else GPIO_BC(LED_BLINK_GPIO_PORT) = LED_BLINK_PIN; #endif break; +# if !defined (CONFIG_HAL_USE_MINIMUM) case 1: - m_nTicksPerSecond = (1000 / 1); + SoftwareTimerChange(m_nTimerId, (1000U / 1)); break; case 3: - m_nTicksPerSecond = (1000 / 3); + SoftwareTimerChange(m_nTimerId, (1000U / 3)); break; case 5: - m_nTicksPerSecond = (1000 / 5); + SoftwareTimerChange(m_nTimerId, (1000U / 5)); break; + case 8: + SoftwareTimerChange(m_nTimerId, (1000U / 8)); + break; +# endif case 255: - m_nTicksPerSecond = 0; -#if defined (USE_LEDBLINK_BITBANGING595) + SoftwareTimerDelete(m_nTimerId); +#if defined (CONFIG_LEDBLINK_USE_PANELLED) hal::panel_led_on(hal::panelled::ACTIVITY); #else GPIO_BOP(LED_BLINK_GPIO_PORT) = LED_BLINK_PIN; #endif break; default: - m_nTicksPerSecond = (1000 / nFreqHz); + SoftwareTimerChange(m_nTimerId, (1000U / nFreqHz)); break; } + + DEBUG_EXIT } private: #if !defined(DISABLE_RTC) HwClock m_HwClock; #endif + uuid_t m_uuid; bool m_bIsWatchdog { false }; - -#if defined (USE_LEDBLINK_BITBANGING595) - BitBanging595 bitBanging595; -#endif hardware::ledblink::Mode m_Mode { hardware::ledblink::Mode::UNKNOWN }; bool m_doLock { false }; - uint32_t m_nTicksPerSecond { 1000 / 2 }; - int32_t m_nToggleLed { 0 }; - uint32_t m_nMillisPrevious { 0 }; + int32_t m_nTimerId { -1 }; + Timer m_Timers[hal::SOFTWARE_TIMERS_MAX]; + uint32_t m_nTimersCount { 0 }; + int32_t m_nNextId { 0 }; + +#if !defined(HAL_HAVE_PORT_BIT_TOGGLE) + static inline int32_t m_nToggleLed { 1 }; +#endif static Hardware *s_pThis; }; diff --git a/lib-hal/include/gd32/panel_led.h b/lib-hal/include/gd32/panel_led.h index 8b6f3236..fbda082b 100644 --- a/lib-hal/include/gd32/panel_led.h +++ b/lib-hal/include/gd32/panel_led.h @@ -30,7 +30,7 @@ #include "gd32.h" -#if !defined (LEDPANEL_595_COUNT) +#if !defined (PANELLED_595_COUNT) # if !defined (UNUSED) # define UNUSED __attribute__((unused)) # endif @@ -45,11 +45,11 @@ namespace panelled { extern uint32_t g_nData; } // namespace panelled -inline static void panel_led_spi(const UNUSED uint32_t nData) { -#if defined(LEDPANEL_595_COUNT) - GPIO_BC(LEDPANEL_595_CS_GPIOx) = LEDPANEL_595_CS_GPIO_PINx; +inline void panel_led_spi(const UNUSED uint32_t nData) { +#if defined(PANELLED_595_COUNT) + GPIO_BC(PANELLED_595_CS_GPIOx) = PANELLED_595_CS_GPIO_PINx; -#if (LEDPANEL_595_COUNT >= 1) +#if (PANELLED_595_COUNT >= 1) while (RESET == (SPI_STAT(SPI_PERIPH) & SPI_FLAG_TBE)) ; @@ -60,7 +60,7 @@ inline static void panel_led_spi(const UNUSED uint32_t nData) { static_cast(SPI_DATA(SPI_PERIPH)); #endif -#if (LEDPANEL_595_COUNT >= 2) +#if (PANELLED_595_COUNT >= 2) while (RESET == (SPI_STAT(SPI_PERIPH) & SPI_FLAG_TBE)) ; @@ -71,7 +71,7 @@ inline static void panel_led_spi(const UNUSED uint32_t nData) { static_cast(SPI_DATA(SPI_PERIPH)); #endif -#if (LEDPANEL_595_COUNT >= 3) +#if (PANELLED_595_COUNT >= 3) while (RESET == (SPI_STAT(SPI_PERIPH) & SPI_FLAG_TBE)) ; @@ -82,7 +82,7 @@ inline static void panel_led_spi(const UNUSED uint32_t nData) { static_cast(SPI_DATA(SPI_PERIPH)); #endif -#if (LEDPANEL_595_COUNT == 4) +#if (PANELLED_595_COUNT == 4) while (RESET == (SPI_STAT(SPI_PERIPH) & SPI_FLAG_TBE)) ; @@ -94,12 +94,18 @@ inline static void panel_led_spi(const UNUSED uint32_t nData) { static_cast(SPI_DATA(SPI_PERIPH)); #endif - GPIO_BOP(LEDPANEL_595_CS_GPIOx) = LEDPANEL_595_CS_GPIO_PINx; + GPIO_BOP(PANELLED_595_CS_GPIOx) = PANELLED_595_CS_GPIO_PINx; #endif } -inline static void panel_led_on(uint32_t UNUSED on) { -#if defined(LEDPANEL_595_COUNT) +inline void panel_led_init() { +#if defined(PANELLED_595_COUNT) + +#endif +} + +inline void panel_led_on(uint32_t UNUSED on) { +#if defined(PANELLED_595_COUNT) if (panelled::g_nData == (panelled::g_nData | on)) { return; } @@ -110,8 +116,8 @@ inline static void panel_led_on(uint32_t UNUSED on) { #endif } -inline static void panel_led_off(uint32_t UNUSED off) { -#if defined(LEDPANEL_595_COUNT) +inline void panel_led_off(uint32_t UNUSED off) { +#if defined(PANELLED_595_COUNT) if (panelled::g_nData == (panelled::g_nData & ~off)) { return; } @@ -121,6 +127,13 @@ inline static void panel_led_off(uint32_t UNUSED off) { panel_led_spi(panelled::g_nData); #endif } + +inline void panel_led_run() { +#if defined(PANELLED_595_COUNT) + +#endif +} + } // namespace hal #endif /* GD32_PANEL_LED_H_ */ diff --git a/gd32_emac_ddp_pixel_multi/include/display_timeout.h b/lib-hal/include/hal_api.h old mode 100644 new mode 100755 similarity index 69% rename from gd32_emac_ddp_pixel_multi/include/display_timeout.h rename to lib-hal/include/hal_api.h index a8556629..71d7f29a --- a/gd32_emac_ddp_pixel_multi/include/display_timeout.h +++ b/lib-hal/include/hal_api.h @@ -1,8 +1,8 @@ /** - * @file display_timeout.h + * @file hal_api.h * */ -/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,23 +23,25 @@ * THE SOFTWARE. */ -#ifndef DISPLAY_TIMEOUT_H_ -#define DISPLAY_TIMEOUT_H_ - -#include "gd32.h" - -namespace display { -namespace timeout { - -void gpio_init() { - gpio_fsel(KEY2_GPIOx, KEY2_PINx, GPIO_FSEL_INPUT); -} - -bool gpio_renew() { - return (GPIO_ISTAT(KEY2_GPIOx) & KEY2_PINx) == 0; -} - -} // namespace timeout -} // namespace display - -#endif /* DISPLAY_TIMEOUT_H_ */ +#ifndef HAL_API_H_ +#define HAL_API_H_ + +#if defined(__linux__) || defined (__APPLE__) +# include "linux/hal_api.h" +#elif defined(H3) +# include "h3/hal_api.h" +#elif defined(GD32) +# include "gd32/hal_api.h" +#else +# include "rpi/hal_api.h" +#endif + +#ifdef __cplusplus +# if !defined(UDELAY) +# define UDELAY +# include + void udelay(uint32_t us, uint32_t offset = 0); +# endif +#endif + +#endif /* HAL_API_H_ */ diff --git a/lib-hal/include/hal_gpio.h b/lib-hal/include/hal_gpio.h index da3fdb20..8066e944 100644 --- a/lib-hal/include/hal_gpio.h +++ b/lib-hal/include/hal_gpio.h @@ -2,7 +2,7 @@ * @file hal_gpio.h * */ -/* Copyright (C) 2020-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-hal/include/hal_i2c.h b/lib-hal/include/hal_i2c.h index f3664083..150c7bdd 100644 --- a/lib-hal/include/hal_i2c.h +++ b/lib-hal/include/hal_i2c.h @@ -26,6 +26,8 @@ #ifndef HAL_I2C_H_ #define HAL_I2C_H_ +#include "hal_api.h" + #if defined(__linux__) || defined (__APPLE__) # include "linux/hal_api.h" # include "linux/hal_i2c.h" diff --git a/lib-hal/include/hal_spi.h b/lib-hal/include/hal_spi.h index ef7e22c1..ded9f3f7 100644 --- a/lib-hal/include/hal_spi.h +++ b/lib-hal/include/hal_spi.h @@ -26,6 +26,8 @@ #ifndef HAL_SPI_H_ #define HAL_SPI_H_ +#include "hal_api.h" + #if defined(__linux__) || defined (__APPLE__) # include "linux/hal_api.h" # include "linux/hal_spi.h" @@ -40,7 +42,8 @@ # include "rpi/hal_spi.h" #endif -#include +#ifdef __cplusplus +# include class HAL_SPI { void Setup() { @@ -80,5 +83,6 @@ class HAL_SPI { uint8_t m_nChipSelect; uint8_t m_nMode; }; +#endif #endif /* HAL_SPI_H_ */ diff --git a/lib-hal/include/hardware.h b/lib-hal/include/hardware.h index 6d8f9e07..e7a2d94d 100644 --- a/lib-hal/include/hardware.h +++ b/lib-hal/include/hardware.h @@ -2,7 +2,7 @@ * @file hardware.h * */ -/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,6 +27,8 @@ #define HARDWARE_H_ #include +#include +#include namespace hardware { enum class BootDevice { @@ -42,12 +44,26 @@ namespace ledblink { enum class Mode { OFF_OFF, OFF_ON, NORMAL, DATA, FAST, REBOOT, UNKNOWN }; - -void display(const uint32_t nState); } // namespace ledblink } // namespace hardware -#if defined (BARE_METAL) +namespace hal { +#if !defined (CONFIG_HAL_TIMERS_COUNT) +# define CONFIG_HAL_TIMERS_COUNT 8 +#endif + +static constexpr uint32_t SOFTWARE_TIMERS_MAX = CONFIG_HAL_TIMERS_COUNT; + +typedef void (*TimerCallback)(); +} // namespace hal + +#if defined(__linux__) || defined (__APPLE__) +# if defined (CONFIG_HAL_USE_MINIMUM) +# include "linux/minimum/hardware.h" +# else +# include "linux/hardware.h" +# endif +#else # if defined (H3) # include "h3/hardware.h" # elif defined (GD32) @@ -55,8 +71,6 @@ void display(const uint32_t nState); # else # include "rpi/hardware.h" # endif -#else -# include "linux/hardware.h" #endif #endif /* HARDWARE_H_ */ diff --git a/lib-hal/include/hwclock.h b/lib-hal/include/hwclock.h index 579949eb..331d293a 100644 --- a/lib-hal/include/hwclock.h +++ b/lib-hal/include/hwclock.h @@ -3,7 +3,7 @@ * @file hwclock.h * */ -/* Copyright (C) 2020-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,6 +28,7 @@ #define HWCLOCK_H_ #include +#include #include namespace rtc { @@ -36,18 +37,6 @@ enum class Type : uint8_t { }; } // namespace rtc -struct rtc_time { - int tm_sec; - int tm_min; - int tm_hour; - int tm_mday; - int tm_mon; - int tm_year; - int tm_wday; /* unused */ - int tm_yday; /* unused */ - int tm_isdst; /* unused */ -}; - class HwClock { public: HwClock(); @@ -56,16 +45,34 @@ class HwClock { void HcToSys(); // Set the System Clock from the Hardware Clock void SysToHc(); // Set the Hardware Clock from the System Clock - bool Set(const struct rtc_time *pRtcTime); - bool Get(struct rtc_time *pRtcTime) { - return RtcGet(pRtcTime); + bool Set(const struct tm *pTime); + bool Get(struct tm *pTime) { + return RtcGet(pTime); + } + + bool AlarmSet(const struct tm *pTime) { + return RtcSetAlarm(pTime); + } + bool AlarmGet(struct tm *pTime) { + return RtcGetAlarm(pTime); + } + void AlarmEnable(const bool bEnable) { + m_bRtcAlarmEnabled = bEnable; + } + bool AlarmIsEnabled() const { + return m_bRtcAlarmEnabled; } bool IsConnected() const { return m_bIsConnected; } - void Run(bool bDoRun); + void Run(const bool bDoRun) { + if (!bDoRun || !m_bIsConnected) { + return; + } + Process(); + } void Print(); @@ -74,8 +81,14 @@ class HwClock { } private: - bool RtcSet(const struct rtc_time *pRtcTime); - bool RtcGet(struct rtc_time *pRtcTime); + void Process(); + bool RtcSet(const struct tm *pime); + bool RtcGet(struct tm *pTime); + bool RtcSetAlarm(const struct tm *pTime); + bool RtcGetAlarm(struct tm *pTime); + int MCP794xxAlarmWeekday(struct tm *pTime); + void PCF8563GetAlarmMode(); + void PCF8563SetAlarmMode(); private: uint32_t m_nSetDelayMicros { 0 }; @@ -83,6 +96,8 @@ class HwClock { uint8_t m_nAddress { 0 }; rtc::Type m_Type { rtc::Type::UNKNOWN }; bool m_bIsConnected { false }; + bool m_bRtcAlarmEnabled { false }; + bool m_bRtcAlarmPending { false }; static HwClock *s_pThis; }; diff --git a/lib-hal/include/panel_led.h b/lib-hal/include/panel_led.h index 1ff5843d..89563f88 100644 --- a/lib-hal/include/panel_led.h +++ b/lib-hal/include/panel_led.h @@ -2,7 +2,7 @@ * @file panel_led.h * */ -/* Copyright (C) 2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -56,7 +56,9 @@ * } // namespace hal */ -#if defined (BARE_METAL) +#if defined(__linux__) || defined (__APPLE__) +# include "linux/panel_led.h" +#else # if defined (H3) # include "h3/panel_led.h" # elif defined (GD32) @@ -64,8 +66,6 @@ # else # include "rpi/panel_led.h" # endif -#else -# include "linux/panel_led.h" #endif #endif /* PANEL_LED_H_ */ diff --git a/lib-hal/include/uart0_debug.h b/lib-hal/include/uart0_debug.h index 81469d3d..58f17412 100644 --- a/lib-hal/include/uart0_debug.h +++ b/lib-hal/include/uart0_debug.h @@ -2,7 +2,7 @@ * @file uart0_debug.h * */ -/* Copyright (C) 2018-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2021 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-hal/include/utc.h b/lib-hal/include/utc.h index 3fda86b7..a2c714a3 100644 --- a/lib-hal/include/utc.h +++ b/lib-hal/include/utc.h @@ -2,7 +2,7 @@ * @file utc.h * */ -/* Copyright (C) 2019-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,14 +26,70 @@ #include -enum TUtcOffset { +#include "debug.h" + +// https://en.wikipedia.org/wiki/List_of_UTC_time_offsets + +namespace hal { +enum class UtcOffset { UTC_OFFSET_MIN = -12, UTC_OFFSET_MAX = 14 }; -class Utc { -public: - static int32_t Validate(float fOffset); -}; +inline int32_t utc_validate(const float fOffset) { + static constexpr float s_ValidOffets[] = { -9.5, -3.5, 3.5, 4.5, 5.5, 5.75, 6.5, 8.75, 9.5, 10.5, 12.75 }; + auto nInt = static_cast(fOffset); + + if ((nInt >= -12) && (nInt <= 14)) { + if (fOffset == static_cast(nInt)) { + return (nInt * 3600); + } else { + for (uint32_t i = 0; i < sizeof(s_ValidOffets) / sizeof(s_ValidOffets[0]); i++) { + if (fOffset == s_ValidOffets[i]) { + return static_cast(fOffset * 3600.0f); + } + } + } + } + + return 0; +} + +inline bool utc_validate(const int8_t nHours, const uint8_t nMinutes, int32_t& nUtcOffset) { + struct Offset { + int8_t nHours; + uint8_t nMinutes; + }; + // https://en.wikipedia.org/wiki/List_of_UTC_time_offsets + static constexpr Offset s_ValidOffsets[] = { {-9, 30}, {-3, 30}, + {3, 30}, {4, 30}, {5, 30}, {5, 45}, {6, 30}, {8, 45}, {9, 30}, {10, 30}, {12, 45} }; + constexpr int8_t UTC_OFFSET_MIN = -12; + constexpr int8_t UTC_OFFSET_MAX = 14; + + // Check if nHours is within valid range + if (nHours >= UTC_OFFSET_MIN && nHours <= UTC_OFFSET_MAX) { + // Check if minutes are 0, meaning a whole hour offset + if (nMinutes == 0) { + nUtcOffset = nHours * 3600; + return true; + } else { + for (const auto& offset : s_ValidOffsets) { + if (nHours == offset.nHours && nMinutes == offset.nMinutes) { + nUtcOffset = (nHours * 3600); + if (nHours > 0) { + nUtcOffset = nUtcOffset + (nMinutes * 60); + } else { + nUtcOffset = nUtcOffset - (nMinutes * 60); + } + return true; + } + } + } + } + + // Return false if validation fails + return false; +} +} // namespace hal #endif /* UTC_H_ */ diff --git a/lib-hal/posix/file.cpp b/lib-hal/posix/file.cpp new file mode 100644 index 00000000..26a5438a --- /dev/null +++ b/lib-hal/posix/file.cpp @@ -0,0 +1,486 @@ +/** + * @file file.c + * + */ +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#if defined (DEBUG_POSIX) +# if defined (NDEBUG) +# undef NDEBUG +# endif +#endif + +#include +#include +#include +#include +#include + +#include "../ff14b/source/ff.h" +#include /* DO NOT MOVE -> DIR is defined in ff.h */ + +#include "debug.h" + +#if !defined (CONFIG_POSIX_OPEN_FILES_MAX) || (CONFIG_POSIX_OPEN_FILES_MAX < 1) +# define CONFIG_POSIX_OPEN_FILES_MAX 2 +#endif + +namespace posix { +static constexpr int OPEN_FILES_MAX = CONFIG_POSIX_OPEN_FILES_MAX; +} // namespace posix + +#if defined(CONFIG_POSIX_ENABLE_STDIN) +static FILE s_file[3 + posix::OPEN_FILES_MAX]; +FILE *stdin = &s_file[0]; +FILE *stdout = &s_file[1]; +FILE *stderr = &s_file[2]; +#else +static FILE s_file[posix::OPEN_FILES_MAX]; +#endif +static FIL s_ff_file[posix::OPEN_FILES_MAX]; + +static FRESULT s_fresult; + +static int get_file_descriptor() { + for (int nFile = 0; nFile < posix::OPEN_FILES_MAX; nFile++) { +#if defined(CONFIG_POSIX_ENABLE_STDIN) + if (isatty(nFile)) { + continue; + } +#endif + if (s_file[nFile].udata == nullptr) { +#if defined(CONFIG_POSIX_ENABLE_STDIN) + s_file[nFile].udata = &s_ff_file[nFile - 3]; +#else + s_file[nFile].udata = &s_ff_file[nFile]; +#endif + return nFile; + } + } + + errno = ENFILE; + return -1; +} + +static int fatfs_to_errno(const BYTE err) { + switch (static_cast(err)) { + case FR_OK: /* FatFS (0) Succeeded */ + return (0); /* POSIX OK */ + case FR_DISK_ERR: /* FatFS (1) A hard error occurred in the low level disk I/O layer */ + return (EIO); /* POSIX Input/output error (POSIX.1) */ + case FR_INT_ERR: /* FatFS (2) Assertion failed */ + return (EPERM); /* POSIX Operation not permitted (POSIX.1) */ + case FR_NOT_READY: /* FatFS (3) The physical drive cannot work */ + return (EBUSY); /* POSIX Device or resource busy (POSIX.1) */ + case FR_NO_FILE: /* FatFS (4) Could not find the file */ + return (ENOENT); /* POSIX No such file or directory (POSIX.1) */ + case FR_NO_PATH: /* FatFS (5) Could not find the path */ + return (ENOENT); /* POSIX No such file or directory (POSIX.1) */ + case FR_INVALID_NAME: /* FatFS (6) The path name format is invalid */ + return (EINVAL); /* POSIX Invalid argument (POSIX.1) */ + case FR_DENIED: /* FatFS (7) Access denied due to prohibited access or directory full */ + return (EACCES); /* POSIX Permission denied (POSIX.1) */ + case FR_EXIST: /* FatFS (8) Access denied due to prohibited access */ + return (EACCES); /* POSIX Permission denied (POSIX.1) */ + case FR_INVALID_OBJECT: /* FatFS (9) The file/directory object is invalid */ + return (EINVAL); /* POSIX Invalid argument (POSIX.1) */ + case FR_WRITE_PROTECTED: /* FatFS (10) The physical drive is write protected */ + return (EROFS); /* POSIX Read-only filesystem (POSIX.1) */ + case FR_INVALID_DRIVE: /* FatFS (11) The logical drive number is invalid */ + return (ENXIO); /* POSIX No such device or address (POSIX.1) */ + case FR_NOT_ENABLED: /* FatFS (12) The volume has no work area */ + return (ENOSPC); /* POSIX No space left on device (POSIX.1) */ + case FR_NO_FILESYSTEM: /* FatFS (13) There is no valid FAT volume */ + return (ENXIO); /* POSIX No such device or address (POSIX.1) */ + case FR_MKFS_ABORTED: /* FatFS (14) The f_mkfs() aborted due to any parameter error */ + return (EINVAL); /* POSIX Invalid argument (POSIX.1) */ + case FR_TIMEOUT: /* FatFS (15) Could not get a grant to access the volume within defined period */ + return (EBUSY); /* POSIX Device or resource busy (POSIX.1) */ + case FR_LOCKED: /* FatFS (16) The operation is rejected according to the file sharing policy */ + return (EBUSY); /* POSIX Device or resource busy (POSIX.1) */ + case FR_NOT_ENOUGH_CORE: /* FatFS (17) LFN working buffer could not be allocated */ + return (ENOMEM); /* POSIX Not enough space (POSIX.1) */ + case FR_TOO_MANY_OPEN_FILES:/* FatFS (18) Number of open files > _FS_SHARE */ + return (EMFILE); /* POSIX Too many open files (POSIX.1) */ + case FR_INVALID_PARAMETER:/* FatFS (19) Given parameter is invalid */ + return (EINVAL); /* POSIX Invalid argument (POSIX.1) */ + } + + return (EBADMSG); /* POSIX Bad message (POSIX.1) */ +} + +extern "C" { +int fileno(FILE *stream) { + if (stream == nullptr) { + errno = EBADF; + return -1; + } + + for (int nFile = 0; nFile < posix::OPEN_FILES_MAX; nFile++) { + if (&s_file[nFile] == stream) { + return nFile; + } + } + + return EOF; +} + +// http://elm-chan.org/fsw/ff/doc/open.html +FILE *fopen(const char *path, const char *mode) { + assert(path != nullptr); + assert(mode != nullptr); + + DEBUG_PRINTF("%s %s", path, mode); + + errno = 0; + BYTE fm, fo; + + switch (mode[0]) { + case 'r': + fm = (BYTE) FA_READ; + fo = 0; + break; + case 'w': + fm = (BYTE) FA_WRITE; + fo = (BYTE) FA_CREATE_ALWAYS; + break; + case 'a': + fm = (BYTE) FA_WRITE; + fo = (BYTE) FA_OPEN_APPEND; + break; + default: + return nullptr; + break; + } + + while (*++mode != '\0') { + switch (*mode) { + case '+': + fm = (BYTE) (FA_READ | FA_WRITE); + break; + case 'x': + fo = (BYTE) FA_CREATE_NEW; + break; + default: + return nullptr; + break; + } + } + + const auto fd = get_file_descriptor(); + DEBUG_PRINTF("fd=%d", fd); + + if (fd < 0) { + errno = EBADF; + return nullptr; + } + + s_fresult = f_open(&s_ff_file[fd], (TCHAR *) path, (BYTE) (fm | fo)); + errno = fatfs_to_errno(s_fresult); + + DEBUG_PRINTF("errno=%d", errno); + + if (s_fresult == FR_OK) { + return &s_file[fd]; + } else { + s_file[fd].udata = nullptr; + return nullptr; + } +} + +int fclose(FILE *stream) { + errno = 0; + + if (stream == nullptr) { + return 0; + } + + const auto fd = fileno(stream); + DEBUG_PRINTF("fd=%d", fd); + + if (fd < 0) { + errno = EBADF; + return EOF; + } + + s_fresult = f_close((FIL *)stream->udata); + errno = fatfs_to_errno(s_fresult); + + DEBUG_PRINTF("errno=%d", errno); + + stream->udata = nullptr; + + if (s_fresult == FR_OK) { + return 0; + } + + return EOF; +} + +int fgetc(FILE *stream) { + char c; + UINT bytes_read; + errno = 0; + + if (stream == nullptr) { + return EOF; + } + + if ((s_fresult = f_read((FIL *)stream->udata, &c, (UINT) 1, &bytes_read)) == FR_OK) { + if (bytes_read > 0) { + return c; + } + + if (bytes_read < 1) { + errno = fatfs_to_errno(s_fresult); + stream->flags |= __SEOF; + return EOF; + } + } + + errno = fatfs_to_errno(s_fresult); + return EOF; +} + +size_t fread(void *ptr, size_t size, size_t nmemb, FILE *stream) { + UINT bytes_read; + + s_fresult = f_read((FIL *)stream->udata, ptr, (size * nmemb), &bytes_read); + errno = fatfs_to_errno(s_fresult); + + if (s_fresult == FR_OK) { + return bytes_read; + } + + return 0; +} + +int fseek(FILE *stream, long offset, int whence) { + if (whence == SEEK_SET) { + s_fresult = f_lseek((FIL *)stream->udata, (FSIZE_t) offset); + } else if (whence == SEEK_END) { + s_fresult = f_lseek((FIL *)stream->udata, f_size((FIL *)stream->udata)); + } + + errno = fatfs_to_errno(s_fresult); + + if (s_fresult == FR_OK) { + return 0; + } + + return -1; +} + +long ftell(FILE *stream) { + return (long) f_tell((FIL *)stream->udata); +} + +char *fgets(char *s, int size, FILE *stream) { + assert(s != nullptr); + errno = 0; + + if (stream == nullptr) { + *s = '\0'; + return nullptr; + } + + if (f_gets(s, size, (FIL *)stream->udata) != s) { + *s = '\0'; + errno = fatfs_to_errno(f_error((FIL *)stream->udata)); + return nullptr; + } + + return s; +} + +void clearerr(FILE *stream) { + stream->flags &= static_cast(~__SEOF); + stream->flags &= static_cast(~__SERR); +} + +int ferror(FILE *stream) { + return (stream->flags & __SERR) ? 1 : 0; +} + +int feof(FILE *stream) { + return (stream->flags & __SEOF) ? 1 : 0; +} + +/* + * The following API´s are implemented when CONFIG_FS_ENABLE_WRITE is defined + */ + +int fputs([[maybe_unused]] const char *s, [[maybe_unused]] FILE *stream) { +#if !defined (CONFIG_FS_ENABLE_WRITE) + errno = ENOSYS; + return -1; +#else + assert(s != nullptr); + assert(stream != nullptr); + errno = 0; + + return f_puts(s, (FIL *)stream->udata); +#endif +} + +size_t fwrite([[maybe_unused]] const void *ptr, [[maybe_unused]] size_t size, [[maybe_unused]] size_t nmemb, [[maybe_unused]] FILE *stream) { +#if !defined (CONFIG_FS_ENABLE_WRITE) + errno = ENOSYS; + return 0; +#else + assert(stream != nullptr); + UINT bytes_write; + + s_fresult = f_write((FIL *)stream->udata, ptr, (size * nmemb), &bytes_write); + errno = fatfs_to_errno(s_fresult); + + if (s_fresult == FR_OK) { + return bytes_write; + } + + return 0; +#endif +} + +int fputc([[maybe_unused]] int c, [[maybe_unused]] FILE *stream) { +#if !defined (CONFIG_FS_ENABLE_WRITE) + errno = ENOSYS; + return 0; +#else + assert(stream != nullptr); + + UINT bytes_write; + + s_fresult = f_write((FIL *)stream->udata, &c, 1, &bytes_write); + errno = fatfs_to_errno(s_fresult); + + if (s_fresult == FR_OK) { + return 1; + } + + return 0; +#endif +} + +int unlink([[maybe_unused]] const char *pathname) { +#if !defined (CONFIG_FS_ENABLE_WRITE) + errno = ENOSYS; + return -1; +#else + s_fresult = f_unlink(pathname); + errno = fatfs_to_errno(s_fresult); + + if (s_fresult == FR_OK) { + return 0; + } + + return -1; +#endif +} + +#if !defined (CONFIG_FS_ENABLE_WRITE) +#else +static DIR s_dir; +static dirent_t s_dirent; +#endif + +DIR *opendir([[maybe_unused]] const char *dirname) { +#if !defined (CONFIG_FS_ENABLE_WRITE) + errno = ENOSYS; + return nullptr; +#else + const auto len = strlen(dirname); + + if ((len > 0) && (dirname[len - 1] == '.')) { + char *pathdir = (char *) dirname; + pathdir[len - 1] = '\0'; + s_fresult = f_opendir(&s_dir, pathdir); + } else { + s_fresult = f_opendir(&s_dir, dirname); + } + + errno = fatfs_to_errno(s_fresult); + + if (s_fresult != FR_OK) { + return nullptr; + } + + return &s_dir; +#endif +} + +/** + * On success, readdir() returns a pointer to a dirent structure. + * If the end of the directory stream is reached, nullptr is returned and errno is not changed. + * If an error occurs, nullptr is returned and errno is set appropriately. + */ + +struct dirent *readdir([[maybe_unused]] DIR *dirp) { +#if !defined (CONFIG_FS_ENABLE_WRITE) + errno = ENOSYS; + return nullptr; +#else + FILINFO fno; + + fno.fname[0] = '\0'; + + s_fresult = f_readdir(&s_dir, &fno); + + if (s_fresult != FR_OK) { + errno = fatfs_to_errno(s_fresult); + return nullptr; + } + + if (fno.fname[0] == '\0') { + return nullptr; + } + + errno = 0; + + strncpy(s_dirent.d_name, fno.fname, sizeof(s_dirent.d_name) - 1); + + if (fno.fattrib == AM_DIR) { + s_dirent.d_type = DT_DIR; + } else { + s_dirent.d_type = DT_REG; + } + + return &s_dirent; +#endif +} + +int closedir([[maybe_unused]] DIR *dirp) { +#if !defined (CONFIG_FS_ENABLE_WRITE) + errno = ENOSYS; + return -1; +#else + s_fresult = f_closedir(&s_dir); + errno = fatfs_to_errno(s_fresult); + + if (s_fresult == FR_OK) { + return 0; + } + + return -1; +#endif +} +} diff --git a/lib-hal/rtc/gd32/hwclockrtc.cpp b/lib-hal/rtc/gd32/hwclockrtc.cpp index fbe9f5d8..708e6920 100644 --- a/lib-hal/rtc/gd32/hwclockrtc.cpp +++ b/lib-hal/rtc/gd32/hwclockrtc.cpp @@ -2,7 +2,7 @@ * @file hwclockrtc.cpp * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,20 +27,68 @@ #include #include +#include "hwclock.h" + #include "hardware.h" #include "gd32.h" #include "debug.h" -bool rtc_configuration(void) { - rcu_osci_on (RCU_LXTAL); +#define BCD2DEC(val) ( ((val) & 0x0f) + ((val) >> 4) * 10 ) +#define DEC2BCD(val) static_cast( (((val) / 10) << 4) + (val) % 10 ) + +#if defined (GD32F4XX) || defined (GD32H7XX) +# define RTC_CLOCK_SOURCE_LXTAL +static rtc_parameter_struct rtc_initpara; +#endif + +#if defined (GD32F4XX) || defined (GD32H7XX) +bool rtc_configuration() { +# if defined (RTC_CLOCK_SOURCE_IRC32K) + rcu_osci_on (RCU_IRC32K); + if (SUCCESS != rcu_osci_stab_wait(RCU_IRC32K)) { + return false; + } + rcu_rtc_clock_config (RCU_RTCSRC_IRC32K); +# elif defined (RTC_CLOCK_SOURCE_LXTAL) + rcu_osci_on(RCU_LXTAL); + + if (SUCCESS != rcu_osci_stab_wait(RCU_LXTAL)) { + return false; + } + + rcu_rtc_clock_config(RCU_RTCSRC_LXTAL); +# else +# error RTC clock source should be defined. +# endif + rcu_periph_clock_enable(RCU_RTC); + + if (SUCCESS != rtc_register_sync_wait()) { + return false; + } + + rtc_initpara.date = DEC2BCD(_TIME_STAMP_DAY_); + rtc_initpara.month = DEC2BCD(_TIME_STAMP_MONTH_ - 1); + rtc_initpara.year = DEC2BCD(_TIME_STAMP_YEAR_ - 1900); + + if (SUCCESS != rtc_init(&rtc_initpara)) { + DEBUG_PUTS("RTC time configuration failed!"); + return false; + } + + DEBUG_PUTS("RTC time configuration success!"); + return true; +} +#else +bool rtc_configuration() { + rcu_osci_on(RCU_LXTAL); if (SUCCESS != rcu_osci_stab_wait(RCU_LXTAL)) { return false; } - rcu_rtc_clock_config (RCU_RTCSRC_LXTAL); - rcu_periph_clock_enable (RCU_RTC); + rcu_rtc_clock_config(RCU_RTCSRC_LXTAL); + rcu_periph_clock_enable(RCU_RTC); rtc_register_sync_wait(); rtc_lwoff_wait(); rtc_prescaler_set(32767); @@ -48,12 +96,26 @@ bool rtc_configuration(void) { return true; } +#endif using namespace rtc; void HwClock::RtcProbe() { DEBUG_ENTRY +#if defined (GD32F4XX) || defined (GD32H7XX) +# if defined (RTC_CLOCK_SOURCE_IRC32K) + rtc_initpara.factor_syn = 0x13F; + rtc_initpara.factor_asyn = = 0x63; +# elif defined (RTC_CLOCK_SOURCE_LXTAL) + rtc_initpara.factor_syn = 0xFF; + rtc_initpara.factor_asyn = 0x7F; +# else +# error RTC clock source should be defined. +# endif + rtc_initpara.display_format = RTC_24HOUR; +#endif + if (bkp_data_read(BKP_DATA_0) != 0xA5A5) { DEBUG_PUTS("RTC not yet configured"); @@ -64,14 +126,25 @@ void HwClock::RtcProbe() { return; } - rtc_lwoff_wait(); - rtc_counter_set(time(nullptr)); - rtc_lwoff_wait(); bkp_data_write(BKP_DATA_0, 0xA5A5); + + struct tm RtcTime; + + RtcTime.tm_hour = 0; + RtcTime.tm_min = 0; + RtcTime.tm_sec = 0; + RtcTime.tm_mday = _TIME_STAMP_DAY_; + RtcTime.tm_mon = _TIME_STAMP_MONTH_ - 1; + RtcTime.tm_year = _TIME_STAMP_YEAR_ - 1900; + + RtcSet(&RtcTime); } else { DEBUG_PUTS("No need to configure RTC"); rtc_register_sync_wait(); - rtc_lwoff_wait(); +#if defined (GD32F4XX) || defined (GD32H7XX) +#else + rtc_lwoff_wait(); +#endif } m_Type = rtc::Type::SOC_INTERNAL; @@ -81,24 +154,141 @@ void HwClock::RtcProbe() { DEBUG_EXIT } -bool HwClock::RtcSet(const struct rtc_time *pRtcTime) { +bool HwClock::RtcSet(const struct tm *pTime) { + assert(pTime != nullptr); + + DEBUG_PRINTF("sec=%d, min=%d, hour=%d, mday=%d, mon=%d, year=%d, wday=%d", + pTime->tm_sec, + pTime->tm_min, + pTime->tm_hour, + pTime->tm_mday, + pTime->tm_mon, + pTime->tm_year, + pTime->tm_wday); + +#if defined (GD32F4XX) || defined (GD32H7XX) + rtc_initpara.year = DEC2BCD(pTime->tm_year); + rtc_initpara.month = DEC2BCD(pTime->tm_mon); + rtc_initpara.date = DEC2BCD(pTime->tm_mday); + rtc_initpara.day_of_week = DEC2BCD(pTime->tm_wday); + rtc_initpara.hour = DEC2BCD(pTime->tm_hour); + rtc_initpara.minute = DEC2BCD(pTime->tm_min); + rtc_initpara.second = DEC2BCD(pTime->tm_sec); + + return (SUCCESS == rtc_init(&rtc_initpara)); +#else + rtc_counter_set(mktime(const_cast(pTime))); +#endif + return true; +} + +bool HwClock::RtcGet(struct tm *pTime) { + assert(pTime != nullptr); + +#if defined (GD32F4XX) || defined (GD32H7XX) + const auto tr = reinterpret_cast(RTC_TIME); + const auto dr = reinterpret_cast(RTC_DATE); + + pTime->tm_year = BCD2DEC(GET_DATE_YR(dr)); + pTime->tm_mon = BCD2DEC(GET_DATE_MON(dr)); + pTime->tm_mday = BCD2DEC(GET_DATE_DAY(dr)); + pTime->tm_wday = BCD2DEC(GET_DATE_DOW(dr)); + pTime->tm_hour = BCD2DEC(GET_TIME_HR(tr)); + pTime->tm_min = BCD2DEC(GET_TIME_MN(tr)); + pTime->tm_sec = BCD2DEC(GET_TIME_SC(tr)); +#else + const auto nSeconds = static_cast(rtc_counter_get()); + const auto *pTm = gmtime(&nSeconds); + memcpy(pTime, pTm, sizeof(struct tm)); +#endif + + DEBUG_PRINTF("sec=%d, min=%d, hour=%d, mday=%d, mon=%d, year=%d, wday=%d", + pTime->tm_sec, + pTime->tm_min, + pTime->tm_hour, + pTime->tm_mday, + pTime->tm_mon, + pTime->tm_year, + pTime->tm_wday); + + return true; +} + +bool HwClock::RtcSetAlarm(const struct tm *pTime) { DEBUG_ENTRY - assert(pRtcTime != nullptr); + assert(pTime != nullptr); + + DEBUG_PRINTF("secs=%d, mins=%d, hours=%d, mday=%d, mon=%d, year=%d, wday=%d, enabled=%d", + pTime->tm_sec, + pTime->tm_min, + pTime->tm_hour, + pTime->tm_mday, + pTime->tm_mon, + pTime->tm_year, + pTime->tm_wday, + m_bRtcAlarmEnabled); + +#if defined (GD32F4XX) || defined (GD32H7XX) + rtc_alarm_disable (RTC_ALARM0); + rtc_alarm_struct rtc_alarm; - rtc_counter_set(mktime(const_cast(reinterpret_cast(pRtcTime)))); -// rtc_lwoff_wait(); + rtc_alarm.alarm_mask = RTC_ALARM_ALL_MASK; + rtc_alarm.weekday_or_date = RTC_ALARM_DATE_SELECTED; + rtc_alarm.am_pm = 0; + rtc_alarm.alarm_day = DEC2BCD(pTime->tm_mday); + rtc_alarm.alarm_hour = DEC2BCD(pTime->tm_hour); + rtc_alarm.alarm_minute = DEC2BCD(pTime->tm_min); + rtc_alarm.alarm_second = DEC2BCD(pTime->tm_sec); + + rtc_alarm_config(RTC_ALARM0, &rtc_alarm); + + if (m_bRtcAlarmEnabled) { + rtc_interrupt_enable (RTC_INT_ALARM0); + rtc_alarm_enable(RTC_ALARM0); + } else { + rtc_alarm_disable(RTC_ALARM0); + rtc_interrupt_disable(RTC_INT_ALARM0); + } +#else + rtc_alarm_config(mktime(const_cast(pTime))); +#endif DEBUG_EXIT return true; } -bool HwClock::RtcGet(struct rtc_time *pRtcTime) { +bool HwClock::RtcGetAlarm(struct tm *pTime) { DEBUG_ENTRY - assert(pRtcTime != nullptr); + assert(pTime != nullptr); + +#if defined (GD32F4XX) || defined (GD32H7XX) + if (!RtcGet(pTime)) { + DEBUG_EXIT + return false; + } + + rtc_alarm_struct rtc_alarm; + rtc_alarm_get(RTC_ALARM0, &rtc_alarm); - const auto nSeconds = static_cast(rtc_counter_get()); + pTime->tm_sec= BCD2DEC(rtc_alarm.alarm_second); + pTime->tm_min = BCD2DEC(rtc_alarm.alarm_minute); + pTime->tm_hour = BCD2DEC(rtc_alarm.alarm_hour); + pTime->tm_mday = BCD2DEC(rtc_alarm.alarm_day); +#else + const auto nSeconds = static_cast((RTC_ALRMH << 16U) | RTC_ALRML); const auto *pTm = localtime(&nSeconds); - memcpy(pRtcTime, pTm, sizeof(struct rtc_time)); + memcpy(pTime, pTm, sizeof(struct tm)); +#endif + + DEBUG_PRINTF("secs=%d, mins=%d, hours=%d, mday=%d, mon=%d, year=%d, wday=%d, enabled=%d", + pTime->tm_sec, + pTime->tm_min, + pTime->tm_hour, + pTime->tm_mday, + pTime->tm_mon, + pTime->tm_year, + pTime->tm_wday, + m_bRtcAlarmEnabled); DEBUG_EXIT return true; diff --git a/lib-hal/rtc/hwclock.cpp b/lib-hal/rtc/hwclock.cpp old mode 100644 new mode 100755 index 43d73a79..e065f5ca --- a/lib-hal/rtc/hwclock.cpp +++ b/lib-hal/rtc/hwclock.cpp @@ -2,7 +2,7 @@ * @file hwclock.cpp * */ -/* Copyright (C) 2020-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,9 +34,7 @@ #include "debug.h" -using namespace rtc; - -HwClock *HwClock::s_pThis = nullptr; +HwClock *HwClock::s_pThis; HwClock::HwClock() { assert(s_pThis == nullptr); @@ -52,27 +50,25 @@ void HwClock::Print() { const char *pType = "Unknown"; switch (m_Type) { - case Type::MCP7941X: + case rtc::Type::MCP7941X: pType = "MCP7941X"; break; - case Type::DS3231: + case rtc::Type::DS3231: pType = "DS3231"; break; - case Type::PCF8563: + case rtc::Type::PCF8563: pType = "PCF8563"; break; - case Type::SOC_INTERNAL: + case rtc::Type::SOC_INTERNAL: pType = "SOC_INTERNAL"; break; default: break; } - printf("%s\n", pType); - - struct rtc_time tm; + struct tm tm; RtcGet(&tm); - printf("%.4d/%.2d/%.2d %.2d:%.2d:%.2d\n", 1900 + tm.tm_year, 1 + tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); + printf("%s %.4d/%.2d/%.2d %.2d:%.2d:%.2d\n", pType, 1900 + tm.tm_year, 1 + tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); } /* @@ -85,39 +81,28 @@ void HwClock::HcToSys() { return; } - assert(Hardware::Get() != nullptr); - const bool bIsWatchdog = Hardware::Get()->IsWatchdog(); + const auto bIsWatchdog = Hardware::Get()->IsWatchdog(); if (bIsWatchdog) { Hardware::Get()->WatchdogStop(); } - struct rtc_time rtcT1; - struct rtc_time rtcT2; - + struct tm rtcT1; struct timeval tvT1; - struct timeval tvT2; RtcGet(&rtcT1); gettimeofday(&tvT1, nullptr); - const int32_t nSecondsT1 = rtcT1.tm_sec + rtcT1.tm_min * 60; - - struct tm tm; - - tm.tm_sec = rtcT1.tm_sec; - tm.tm_min = rtcT1.tm_min; - tm.tm_hour = rtcT1.tm_hour; - tm.tm_mday = rtcT1.tm_mday; - tm.tm_mon = rtcT1.tm_mon; - tm.tm_year = rtcT1.tm_year; + const auto nSecondsT1 = rtcT1.tm_sec + rtcT1.tm_min * 60; + const auto nSeconds = mktime(&rtcT1); - const time_t nSeconds = mktime(&tm); + struct tm rtcT2; + struct timeval tvT2; while(true) { RtcGet(&rtcT2); - const int32_t nSeconds2 = rtcT2.tm_sec + rtcT2.tm_min * 60; + const auto nSeconds2 = rtcT2.tm_sec + rtcT2.tm_min * 60; if (nSecondsT1 != nSeconds2) { gettimeofday(&tvT2, nullptr); @@ -159,8 +144,7 @@ void HwClock::SysToHc() { return; } - assert(Hardware::Get() != nullptr); - const bool bIsWatchdog = Hardware::Get()->IsWatchdog(); + const auto bIsWatchdog = Hardware::Get()->IsWatchdog(); if (bIsWatchdog) { Hardware::Get()->WatchdogStop(); @@ -174,18 +158,8 @@ void HwClock::SysToHc() { gettimeofday(&tv2, nullptr); if (tv2.tv_sec >= (tv1.tv_sec + 1)) { - const struct tm *tm = localtime(&tv2.tv_sec); - - struct rtc_time rtc; - - rtc.tm_sec = tm->tm_sec; - rtc.tm_min = tm->tm_min; - rtc.tm_hour = tm->tm_hour; - rtc.tm_mday = tm->tm_mday; - rtc.tm_mon = tm->tm_mon; - rtc.tm_year = tm->tm_year; - - RtcSet(&rtc); + const auto *tm = gmtime(&tv2.tv_sec); + RtcSet(tm); break; } } diff --git a/lib-hal/rtc/hwclockrun.cpp b/lib-hal/rtc/hwclockrun.cpp index 839f8290..dae0bea9 100644 --- a/lib-hal/rtc/hwclockrun.cpp +++ b/lib-hal/rtc/hwclockrun.cpp @@ -2,7 +2,7 @@ * @file hwclockrun.cpp * */ -/* Copyright (C) 2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,23 +34,18 @@ #include "debug.h" enum class Status { - WAITING, - SAMPLING + WAITING, SAMPLING }; static Status Status = Status::WAITING; static time_t nSeconds; static int32_t nSecondsT1; -static struct rtc_time rtcT1; +static struct tm rtcT1; static struct timeval tvT1; -static struct rtc_time rtcT2; +static struct tm rtcT2; static struct timeval tvT2; -void HwClock::Run(bool bDoRun) { - if (!bDoRun || !m_bIsConnected) { - return; - } - +void HwClock::Process() { if (Status == Status::WAITING) { if (__builtin_expect(((Hardware::Get()->Millis() - m_nLastHcToSysMillis) > 7200 * 1000), 0)) { Status = Status::SAMPLING; @@ -59,17 +54,7 @@ void HwClock::Run(bool bDoRun) { gettimeofday(&tvT1, nullptr); nSecondsT1 = rtcT1.tm_sec + rtcT1.tm_min * 60; - - struct tm tm; - - tm.tm_sec = rtcT1.tm_sec; - tm.tm_min = rtcT1.tm_min; - tm.tm_hour = rtcT1.tm_hour; - tm.tm_mday = rtcT1.tm_mday; - tm.tm_mon = rtcT1.tm_mon; - tm.tm_year = rtcT1.tm_year; - - nSeconds = mktime(&tm); + nSeconds = mktime(&rtcT1); } return; @@ -78,7 +63,7 @@ void HwClock::Run(bool bDoRun) { if (Status == Status::SAMPLING) { RtcGet(&rtcT2); - const int32_t nSeconds2 = rtcT2.tm_sec + rtcT2.tm_min * 60; + const auto nSeconds2 = rtcT2.tm_sec + rtcT2.tm_min * 60; if (nSecondsT1 != nSeconds2) { gettimeofday(&tvT2, nullptr); @@ -101,7 +86,7 @@ void HwClock::Run(bool bDoRun) { m_nLastHcToSysMillis = Hardware::Get()->Millis(); Status = Status::WAITING; - DEBUG_PRINTF("%d:%d (%ld %u) (%ld %u) -> %u", nSecondsT1, nSeconds2, tvT1.tv_sec, tvT1.tv_usec, tvT2.tv_sec, tvT2.tv_usec, tv.tv_usec); + DEBUG_PRINTF("%d:%d (%d %d) (%d %d) -> %d", nSecondsT1, nSeconds2, static_cast(tvT1.tv_sec), static_cast(tvT1.tv_usec), static_cast(tvT2.tv_sec), static_cast(tvT2.tv_usec), static_cast(tv.tv_usec)); } return; diff --git a/lib-hal/rtc/hwclockset.cpp b/lib-hal/rtc/hwclockset.cpp index 622bdfed..6a2cd383 100644 --- a/lib-hal/rtc/hwclockset.cpp +++ b/lib-hal/rtc/hwclockset.cpp @@ -2,7 +2,7 @@ * @file hwclockset.cpp * */ -/* Copyright (C) 2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -31,7 +31,7 @@ #include "debug.h" -bool HwClock::Set(const rtc_time *pRtcTime) { +bool HwClock::Set(const tm *pTime) { if (!m_bIsConnected) { return false; } @@ -39,19 +39,10 @@ bool HwClock::Set(const rtc_time *pRtcTime) { struct timeval tvT1; gettimeofday(&tvT1, nullptr); - RtcSet(pRtcTime); - - struct tm tm; - tm.tm_sec = pRtcTime->tm_sec; - tm.tm_min = pRtcTime->tm_min; - tm.tm_hour = pRtcTime->tm_hour; - tm.tm_mday = pRtcTime->tm_mday; - tm.tm_mon = pRtcTime->tm_mon; - tm.tm_year = pRtcTime->tm_year; - tm.tm_isdst = 0; + RtcSet(pTime); struct timeval tv; - tv.tv_sec = mktime(&tm); + tv.tv_sec = mktime(const_cast(pTime)); struct timeval tvT2; gettimeofday(&tvT2, nullptr); diff --git a/lib-hal/rtc/i2c/hwclockrtc.cpp b/lib-hal/rtc/i2c/hwclockrtc.cpp index 2bc00b7f..892d2c20 100644 --- a/lib-hal/rtc/i2c/hwclockrtc.cpp +++ b/lib-hal/rtc/i2c/hwclockrtc.cpp @@ -2,7 +2,7 @@ * @file hwclockrtc.cpp * */ -/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -24,6 +24,7 @@ */ #include +#include #include "hwclock.h" #include "hardware.h" @@ -38,38 +39,67 @@ namespace rtc { namespace reg { static constexpr uint8_t SECONDS = 0x00; static constexpr uint8_t MINUTES = 0x01; -static constexpr uint8_t HOURS = 0x02; -static constexpr uint8_t DAY = 0x03; -static constexpr uint8_t DATE = 0x04; -static constexpr uint8_t MONTH = 0x05; -static constexpr uint8_t YEAR = 0x06; +static constexpr uint8_t HOURS = 0x02; +static constexpr uint8_t DAY = 0x03; +static constexpr uint8_t DATE = 0x04; +static constexpr uint8_t MONTH = 0x05; +static constexpr uint8_t YEAR = 0x06; } // namespace reg namespace mcp7941x { +namespace reg { +static constexpr uint8_t CONTROL = 0x07; +} // namespace reg namespace bit { -static constexpr uint8_t ST = 0x80; -static constexpr uint8_t VBATEN = 0x08; +static constexpr uint8_t ST = 0x80; +static constexpr uint8_t VBATEN = 0x08; +static constexpr uint8_t ALM0_EN = 0x10; +static constexpr uint8_t ALMX_IF = (1U << 3); +static constexpr uint8_t ALMX_C0 = (1U << 4); +static constexpr uint8_t ALMX_C1 = (1U << 5); +static constexpr uint8_t ALMX_C2 = (1U << 6); +#ifndef NDEBUG +static constexpr uint8_t ALMX_POL = (1U << 7); +#endif +static constexpr uint8_t MSK_ALMX_MATCH = (ALMX_C0 | ALMX_C1 | ALMX_C2); } // namespace bit } // namespace mcp7941x +namespace ds3231 { +namespace reg { +static constexpr uint8_t ALARM1_SECONDS = 0x07; +static constexpr uint8_t CONTROL = 0x0e; +//static constexpr uint8_t STATUS = 0x0f; +} // namespace reg +namespace bit { +static constexpr uint8_t A1IE = (1U << 0); +static constexpr uint8_t A2IE = (1U << 1); +static constexpr uint8_t A1F = (1U << 0); +static constexpr uint8_t A2F = (1U << 1); +} // namespace bit +} // namespace ds3231 namespace pcf8563 { namespace reg { static constexpr uint8_t CONTROL_STATUS1 = 0x00; static constexpr uint8_t CONTROL_STATUS2 = 0x01; -static constexpr uint8_t SECONDS = 0x02; -static constexpr uint8_t MINUTES = 0x03; -static constexpr uint8_t HOURS = 0x04; -static constexpr uint8_t DAY = 0x05; -static constexpr uint8_t WEEKDAY = 0x06; -static constexpr uint8_t MONTH = 0x07; -static constexpr uint8_t YEAR = 0x08; +static constexpr uint8_t SECONDS = 0x02; +//static constexpr uint8_t MINUTES = 0x03; +//static constexpr uint8_t HOURS = 0x04; +//static constexpr uint8_t DAY = 0x05; +//static constexpr uint8_t WEEKDAY = 0x06; +//static constexpr uint8_t MONTH = 0x07; +static constexpr uint8_t YEAR = 0x08; +static constexpr uint8_t ALARM = 0x09; } // namespace reg namespace bit { -static constexpr uint8_t SEC_VL = (1U << 7); +static constexpr uint8_t SEC_VL = (1U << 7); +static constexpr uint8_t AIE = (1U << 1); +static constexpr uint8_t AF = (1U << 3); +static constexpr uint8_t ST2_N = (7U << 5); } // namespace bit } // namespace pcf8563 namespace i2caddress { -static constexpr uint8_t PCF8563 = 0x51; +static constexpr uint8_t PCF8563 = 0x51; static constexpr uint8_t MCP7941X = 0x6F; -static constexpr uint8_t DS3231 = 0x68; +static constexpr uint8_t DS3231 = 0x68; } // namespace i2caddress } // namespace rtc @@ -94,10 +124,6 @@ void HwClock::RtcProbe() { char registers[1]; #if !defined (CONFIG_RTC_DISABLE_MCP7941X) - /** - * MCP7941X - */ - FUNC_PREFIX(i2c_set_address(i2caddress::MCP7941X)); registers[0] = reg::YEAR; @@ -122,7 +148,7 @@ void HwClock::RtcProbe() { if ((registers[0] & mcp7941x::bit::ST) == 0) { DEBUG_PUTS("Start the on-board oscillator"); - struct rtc_time RtcTime; + struct tm RtcTime; RtcTime.tm_hour = 0; RtcTime.tm_min = 0; @@ -140,10 +166,6 @@ void HwClock::RtcProbe() { #endif #if !defined (CONFIG_RTC_DISABLE_DS3231) - /** - * DS3231 - */ - FUNC_PREFIX(i2c_set_address(i2caddress::DS3231)); registers[0] = reg::YEAR; @@ -158,7 +180,7 @@ void HwClock::RtcProbe() { m_Type = Type::DS3231; m_nAddress = i2caddress::DS3231; - struct rtc_time tm; + struct tm tm; RtcGet(&tm); if ((tm.tm_hour > 24) || (tm.tm_year > _TIME_STAMP_YEAR_ - 1900)) { @@ -178,10 +200,6 @@ void HwClock::RtcProbe() { #endif #if !defined (CONFIG_RTC_DISABLE_PCF8563) - /** - * PCF8563 - */ - FUNC_PREFIX(i2c_set_address(i2caddress::PCF8563)); registers[0] = pcf8563::reg::YEAR; @@ -207,7 +225,7 @@ void HwClock::RtcProbe() { if (registers[0] & pcf8563::bit::SEC_VL) { DEBUG_PUTS("Integrity of the clock information is not guaranteed"); - struct rtc_time RtcTime; + struct tm RtcTime; RtcTime.tm_hour = 0; RtcTime.tm_min = 0; @@ -237,54 +255,53 @@ void HwClock::RtcProbe() { DEBUG_EXIT } -bool HwClock::RtcSet(const struct rtc_time *pRtcTime) { - assert(pRtcTime != nullptr); +bool HwClock::RtcSet(const struct tm *pTime) { + assert(pTime != nullptr); if (!m_bIsConnected) { return false; } - char registers[7]; + DEBUG_PRINTF("secs=%d, mins=%d, hours=%d, mday=%d, mon=%d, year=%d, wday=%d", + pTime->tm_sec, + pTime->tm_min, + pTime->tm_hour, + pTime->tm_mday, + pTime->tm_mon, + pTime->tm_year, + pTime->tm_wday); - registers[reg::SECONDS] = DEC2BCD(pRtcTime->tm_sec & 0x7f); - registers[reg::MINUTES] = DEC2BCD(pRtcTime->tm_min & 0x7f); - registers[reg::HOURS] = DEC2BCD(pRtcTime->tm_hour & 0x1f); - registers[reg::DAY] = DEC2BCD(pRtcTime->tm_wday & 0x07); - registers[reg::DATE] = DEC2BCD(pRtcTime->tm_mday & 0x3f); - registers[reg::MONTH] = DEC2BCD((pRtcTime->tm_mon + 1) & 0x1f); - registers[reg::YEAR] = DEC2BCD((pRtcTime->tm_year - 100) & 0xff); + char data[8]; + auto registers = &data[1]; + + registers[reg::SECONDS] = DEC2BCD(pTime->tm_sec & 0x7f); + registers[reg::MINUTES] = DEC2BCD(pTime->tm_min & 0x7f); + registers[reg::HOURS] = DEC2BCD(pTime->tm_hour & 0x1f); + registers[reg::DAY] = DEC2BCD(pTime->tm_wday & 0x07); + registers[reg::DATE] = DEC2BCD(pTime->tm_mday & 0x3f); + registers[reg::MONTH] = DEC2BCD((pTime->tm_mon + 1) & 0x1f); + registers[reg::YEAR] = DEC2BCD((pTime->tm_year - 100) & 0xff); if (m_Type == Type::MCP7941X) { registers[reg::SECONDS] |= mcp7941x::bit::ST; registers[reg::DAY] |= mcp7941x::bit::VBATEN; } - char data[8]; - if (m_Type == Type::PCF8563) { data[0] = pcf8563::reg::SECONDS; } else { data[0] = reg::SECONDS; } - data[1] = registers[0]; - data[2] = registers[1]; - data[3] = registers[2]; - data[4] = registers[3]; - data[5] = registers[4]; - data[6] = registers[5]; - data[7] = registers[6]; - FUNC_PREFIX(i2c_set_address(m_nAddress)); FUNC_PREFIX(i2c_set_baudrate(hal::i2c::FULL_SPEED)); - FUNC_PREFIX(i2c_write(data, sizeof(data) / sizeof(data[0]))); return true; } -bool HwClock::RtcGet(struct rtc_time *pRtcTime) { - assert(pRtcTime != nullptr); +bool HwClock::RtcGet(struct tm *pTime) { + assert(pTime != nullptr); if (!m_bIsConnected) { return false; @@ -300,17 +317,328 @@ bool HwClock::RtcGet(struct rtc_time *pRtcTime) { FUNC_PREFIX(i2c_set_address(m_nAddress)); FUNC_PREFIX(i2c_set_baudrate(hal::i2c::FULL_SPEED)); - FUNC_PREFIX(i2c_write(registers, 1)); FUNC_PREFIX(i2c_read(registers, sizeof(registers) / sizeof(registers[0]))); - pRtcTime->tm_sec = BCD2DEC(registers[reg::SECONDS] & 0x7f); - pRtcTime->tm_min = BCD2DEC(registers[reg::MINUTES] & 0x7f); - pRtcTime->tm_hour = BCD2DEC(registers[reg::HOURS] & 0x3f); - pRtcTime->tm_wday = BCD2DEC(registers[reg::DAY] & 0x07); - pRtcTime->tm_mday = BCD2DEC(registers[reg::DATE] & 0x3f); - pRtcTime->tm_mon = BCD2DEC(registers[reg::MONTH] & 0x1f) - 1; - pRtcTime->tm_year = BCD2DEC(registers[reg::YEAR]) + 100; + pTime->tm_sec = BCD2DEC(registers[reg::SECONDS] & 0x7f); + pTime->tm_min = BCD2DEC(registers[reg::MINUTES] & 0x7f); + pTime->tm_hour = BCD2DEC(registers[reg::HOURS] & 0x3f); + pTime->tm_wday = BCD2DEC(registers[reg::DAY] & 0x07); + pTime->tm_mday = BCD2DEC(registers[reg::DATE] & 0x3f); + pTime->tm_mon = BCD2DEC(registers[reg::MONTH] & 0x1f) - 1; + pTime->tm_year = BCD2DEC(registers[reg::YEAR]) + 100; + + DEBUG_PRINTF("secs=%d, mins=%d, hours=%d, mday=%d, mon=%d, year=%d, wday=%d", + pTime->tm_sec, + pTime->tm_min, + pTime->tm_hour, + pTime->tm_mday, + pTime->tm_mon, + pTime->tm_year, + pTime->tm_wday); return true; } + +bool HwClock::RtcSetAlarm(const struct tm *pTime) { + DEBUG_ENTRY + assert(pTime != nullptr); + + DEBUG_PRINTF("secs=%d, mins=%d, hours=%d, mday=%d, mon=%d, year=%d, wday=%d", + pTime->tm_sec, + pTime->tm_min, + pTime->tm_hour, + pTime->tm_mday, + pTime->tm_mon, + pTime->tm_year, + pTime->tm_wday); + + switch (m_Type) { +#if !defined (CONFIG_RTC_DISABLE_MCP7941X) + case Type::MCP7941X: { + const auto wday = static_cast(MCP794xxAlarmWeekday(const_cast(pTime))); + + // Read control and alarm 0 registers. + char registers[11]; + auto data = ®isters[1]; + data[0] = mcp7941x::reg::CONTROL; + + FUNC_PREFIX(i2c_write(data, 1)); + FUNC_PREFIX(i2c_read(data, 10)); + + // Set alarm 0, using 24-hour and day-of-month modes. + data[3] = DEC2BCD(pTime->tm_sec); + data[4] = DEC2BCD(pTime->tm_min); + data[5] = DEC2BCD(pTime->tm_hour); + data[6] = wday; + data[7] = DEC2BCD(pTime->tm_mday); + data[8] = DEC2BCD(pTime->tm_mon + 1); + // Clear the alarm 0 interrupt flag. + data[6] &= static_cast(~mcp7941x::bit::ALMX_IF); + // Set alarm match: second, minute, hour, day, date, month. + data[6] |= mcp7941x::bit::MSK_ALMX_MATCH; + // Disable interrupt. We will not enable until completely programmed. + data[0] &= static_cast(~mcp7941x::bit::ALM0_EN); + + registers[0] = mcp7941x::reg::CONTROL; + FUNC_PREFIX(i2c_write(registers, sizeof(registers) / sizeof(registers[0]))); + + if (m_bRtcAlarmEnabled) { + registers[0] = mcp7941x::reg::CONTROL; + registers[1] |= mcp7941x::bit::ALM0_EN; + FUNC_PREFIX(i2c_write(registers, 2)); + } + + DEBUG_EXIT + return true; + } + break; +#endif +#if !defined (CONFIG_RTC_DISABLE_DS3231) + case Type::DS3231: { + char registers[10]; + auto data = ®isters[1]; + data[0] = ds3231::reg::ALARM1_SECONDS; + + FUNC_PREFIX(i2c_set_address(m_nAddress)); + FUNC_PREFIX(i2c_set_baudrate(hal::i2c::FULL_SPEED)); + FUNC_PREFIX(i2c_write(data, 1)); + FUNC_PREFIX(i2c_read(data, 9)); + + const auto control = data[7]; + const auto status = data[8]; + + // set ALARM1, using 24 hour and day-of-month modes + data[0] = DEC2BCD(pTime->tm_sec); + data[1] = DEC2BCD(pTime->tm_min); + data[2] = DEC2BCD(pTime->tm_hour); + data[3] = DEC2BCD(pTime->tm_mday); + // set ALARM2 to non-garbage + data[4] = 0; + data[5] = 0; + data[6] = 0; + // disable alarms + data[7] = control & static_cast(~(ds3231::bit::A1IE | ds3231::bit::A2IE)); + data[8] = status & static_cast(~(ds3231::bit::A1F | ds3231::bit::A2F)); + + registers[0] = ds3231::reg::ALARM1_SECONDS; + FUNC_PREFIX(i2c_write(registers, sizeof(registers) / sizeof(registers[0]))); + + if (m_bRtcAlarmEnabled) { + registers[0] = ds3231::reg::CONTROL; + registers[1] |= ds3231::bit::A1IE; + FUNC_PREFIX(i2c_write(registers, 2)); + } + + DEBUG_EXIT + return true; + } + break; +#endif +#if !defined (CONFIG_RTC_DISABLE_PCF8563) + case Type::PCF8563: { + char data[5]; + + data[0] = pcf8563::reg::ALARM; + data[1] = DEC2BCD(pTime->tm_min); + data[2] = DEC2BCD(pTime->tm_hour); + data[3] = DEC2BCD(pTime->tm_mday); + data[4] = pTime->tm_wday & 0x07; + + FUNC_PREFIX(i2c_set_address(m_nAddress)); + FUNC_PREFIX(i2c_set_baudrate(hal::i2c::FULL_SPEED)); + FUNC_PREFIX(i2c_write(data, sizeof(data) / sizeof(data[0]))); + + PCF8563SetAlarmMode(); + + DEBUG_EXIT + return true; + } + break; +#endif + default: + break; + } + + DEBUG_EXIT + return false; +} + +bool HwClock::RtcGetAlarm(struct tm *pTime) { + DEBUG_ENTRY + assert(pTime != nullptr); + + if (!RtcGet(pTime)) { + DEBUG_EXIT + return false; + } + + switch (m_Type) { +#if !defined (CONFIG_RTC_DISABLE_MCP7941X) + case Type::MCP7941X: { + char registers[10]; + + registers[0] = mcp7941x::reg::CONTROL; + + FUNC_PREFIX(i2c_set_address(m_nAddress)); + FUNC_PREFIX(i2c_set_baudrate(hal::i2c::FULL_SPEED)); + FUNC_PREFIX(i2c_write(registers, 1)); + FUNC_PREFIX(i2c_read(registers, sizeof(registers) / sizeof(registers[0]))); + + pTime->tm_sec = BCD2DEC(registers[3] & 0x7f); + pTime->tm_min = BCD2DEC(registers[4] & 0x7f); + pTime->tm_hour = BCD2DEC(registers[5] & 0x3f); + pTime->tm_wday = BCD2DEC(registers[6] & 0x7) - 1; + pTime->tm_mday = BCD2DEC(registers[7] & 0x3f); + pTime->tm_mon = BCD2DEC(registers[8] & 0x1f) - 1; + + m_bRtcAlarmEnabled = registers[0] & mcp7941x::bit::ALM0_EN; + + DEBUG_PRINTF("sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d polarity=%d irq=%d match=%u", + pTime->tm_sec, + pTime->tm_min, + pTime->tm_hour, + pTime->tm_wday, + pTime->tm_mday, + pTime->tm_mon, + m_bRtcAlarmEnabled, + (registers[6] & mcp7941x::bit::ALMX_POL), + (registers[6] & mcp7941x::bit::ALMX_IF), + (registers[6] & mcp7941x::bit::MSK_ALMX_MATCH) >> 4); + + DEBUG_EXIT + return true; + } + break; +#endif +#if !defined (CONFIG_RTC_DISABLE_DS3231) + case Type::DS3231: { + char registers[10]; + + registers[0] = ds3231::reg::ALARM1_SECONDS; + + FUNC_PREFIX(i2c_set_address(m_nAddress)); + FUNC_PREFIX(i2c_set_baudrate(hal::i2c::FULL_SPEED)); + FUNC_PREFIX(i2c_write(registers, 1)); + FUNC_PREFIX(i2c_read(registers, sizeof(registers) / sizeof(registers[0]))); + + pTime->tm_sec = BCD2DEC(registers[0] & 0x7f); + pTime->tm_min = BCD2DEC(registers[1] & 0x7f); + pTime->tm_hour = BCD2DEC(registers[2] & 0x3f); + pTime->tm_mday = BCD2DEC(registers[3] & 0x3f); + + m_bRtcAlarmEnabled = (registers[7] & ds3231::bit::A1IE); + m_bRtcAlarmPending = (registers[8] &ds3231::bit::A1F); + + DEBUG_PRINTF("tm is sec=%d, min=%d, hour=%d, mday=%d, enabled=%d, pending=%d", + pTime->tm_sec, + pTime->tm_min, + pTime->tm_hour, + pTime->tm_mday, + m_bRtcAlarmEnabled, + m_bRtcAlarmPending); + + DEBUG_EXIT + return true; + } + + break; +#endif +#if !defined (CONFIG_RTC_DISABLE_PCF8563) + case Type::PCF8563: { + char registers[4]; + + registers[0] = pcf8563::reg::ALARM; + + FUNC_PREFIX(i2c_set_address(m_nAddress)); + FUNC_PREFIX(i2c_set_baudrate(hal::i2c::FULL_SPEED)); + FUNC_PREFIX(i2c_write(registers, 1)); + FUNC_PREFIX(i2c_read(registers, sizeof(registers) / sizeof(registers[0]))); + + DEBUG_PRINTF("raw data is min=%02x, hr=%02x, mday=%02x, wday=%02x", + registers[0], + registers[1], + registers[2], + registers[3]); + + pTime->tm_sec = 0; + pTime->tm_min = BCD2DEC(registers[0] & 0x7F); + pTime->tm_hour = BCD2DEC(registers[1] & 0x3F); + pTime->tm_mday = BCD2DEC(registers[2] & 0x3F); + pTime->tm_wday = BCD2DEC(registers[3] & 0x7); + + PCF8563GetAlarmMode(); + + DEBUG_PRINTF("tm is mins=%d, hours=%d, mday=%d, wday=%d, enabled=%d, pending=%d", + pTime->tm_min, + pTime->tm_hour, + pTime->tm_mday, + pTime->tm_wday, + m_bRtcAlarmEnabled, + m_bRtcAlarmPending); + + DEBUG_EXIT + return true; + } + break; +#endif + default: + break; + } + + DEBUG_EXIT + return false; +} + +int HwClock::MCP794xxAlarmWeekday(struct tm *pTime) { + DEBUG_ENTRY + assert(pTime != nullptr); + assert(m_Type == rtc::Type::MCP7941X); + + struct tm tm_now; + RtcGet(&tm_now); + + const auto days_now = mktime(&tm_now) / (24 * 60 * 60); + const auto days_alarm = mktime(pTime) / (24 * 60 * 60); + const auto i = (tm_now.tm_wday + days_alarm - days_now) % 7 + 1; + + DEBUG_EXIT + return i; +} + +void HwClock::PCF8563GetAlarmMode() { + assert(m_Type == rtc::Type::PCF8563); + + char data[1]; + + data[0] = pcf8563::reg::CONTROL_STATUS2; + + FUNC_PREFIX(i2c_write(data, 1)); + FUNC_PREFIX(i2c_read(data, sizeof(data) / sizeof(data[0]))); + + m_bRtcAlarmEnabled = data[0] & pcf8563::bit::AIE; + m_bRtcAlarmPending = data[0] & pcf8563::bit::AF; +} + +void HwClock::PCF8563SetAlarmMode() { + assert(m_Type == rtc::Type::PCF8563); + + char data[2]; + + data[1] = pcf8563::reg::CONTROL_STATUS2; + + FUNC_PREFIX(i2c_write(&data[1], 1)); + FUNC_PREFIX(i2c_read(&data[1], 1)); + + if (m_bRtcAlarmEnabled) { + data[1] |= pcf8563::bit::AIE; + } else { + data[1] &= static_cast(~pcf8563::bit::AIE); + } + + data[1] &= static_cast(~pcf8563::bit::AF | pcf8563::bit::ST2_N); + + data[0] = pcf8563::reg::CONTROL_STATUS2; + + FUNC_PREFIX(i2c_write(data, 2)); +} diff --git a/lib-hal/rtc/json_rtc.cpp b/lib-hal/rtc/json_rtc.cpp new file mode 100755 index 00000000..443dd51a --- /dev/null +++ b/lib-hal/rtc/json_rtc.cpp @@ -0,0 +1,155 @@ +/** + * @file json_rtc.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include +#include + +#include "hwclock.h" + +#include "debug.h" + +// ISO 8601 format (YYYY-MM-DDTHH:MM:SS) + +#include "readconfigfile.h" +#include "sscan.h" + +static constexpr auto iso8601FormatSize = sizeof("YYYY-MM-DDTHH:MM:SS"); +static char iso8601Format[iso8601FormatSize]; + +static void staticCallbackFunction([[maybe_unused]] void *p, const char *s) { + assert(p == nullptr); + assert(s != nullptr); + + uint32_t nLength = iso8601FormatSize; + + if (Sscan::Char(s, "alarm" , iso8601Format, nLength) == Sscan::OK) { + DEBUG_PUTS("alarm"); + return; + } + + char action[8]; + nLength = sizeof(action) - 1; + + if (Sscan::Char(s, "action" , action, nLength) == Sscan::OK) { + if (strncmp(action, "hctosys", nLength) == 0) { + HwClock::Get()->HcToSys(); + return; + } + + if (strncmp(action, "systohc", nLength) == 0) { + HwClock::Get()->SysToHc(); + return; + } + + return; + } + + uint8_t nValue8; + + if (Sscan::Uint8(s, "enable", nValue8) == Sscan::OK) { + HwClock::Get()->AlarmEnable(nValue8 != 0); + return; + } +} + +namespace remoteconfig { +namespace rtc { +static int atoi(const char *pBuffer, uint32_t nSize) { + assert(pBuffer != nullptr); + assert(nSize <= 4); + + const char *p = pBuffer; + int32_t res = 0; + + for (; (nSize > 0) && (*p >= '0' && *p <= '9'); nSize--) { + res = res * 10 + *p - '0'; + p++; + } + + return res; +} + +uint32_t json_get_rtc(char *pOutBuffer, const uint32_t nOutBufferSize) { + DEBUG_ENTRY + + struct tm tm; + + if (HwClock::Get()->Get(&tm)) { + auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, + "{\"rtc\":\"%d-%.2d-%.2dT%.2d:%.2d:%.2d\",", + 1900 + tm.tm_year, 1 + tm.tm_mon, tm.tm_mday, + tm.tm_hour, tm.tm_min, tm.tm_sec)); + + if (HwClock::Get()->AlarmGet(&tm)) { + nLength += static_cast(snprintf(&pOutBuffer[nLength], nOutBufferSize, + "\"alarm\":\"%d-%.2d-%.2dT%.2d:%.2d:%.2d\",", + 1900 + tm.tm_year, 1 + tm.tm_mon, tm.tm_mday, + tm.tm_hour, tm.tm_min, tm.tm_sec)); + + nLength += static_cast(snprintf(&pOutBuffer[nLength], nOutBufferSize, + "\"enabled\":\"%d\"}", HwClock::Get()->AlarmIsEnabled())); + + DEBUG_EXIT + return nLength; + } else { + pOutBuffer[nLength++] = '}'; + } + } + + DEBUG_EXIT + return 0; +} + +void json_set_rtc(const char *pBuffer, const uint32_t nBufferSize) { + DEBUG_ENTRY + debug_dump(pBuffer, static_cast(nBufferSize)); + + iso8601Format[0] = 0; + + ReadConfigFile config(staticCallbackFunction, nullptr); + config.Read(pBuffer, nBufferSize); + + debug_dump(iso8601Format, static_cast(sizeof(iso8601Format))); + + if (iso8601Format[0] != 0) { + struct tm tm; + tm.tm_year = atoi(&iso8601Format[0], 4) - 1900; + tm.tm_mon = atoi(&iso8601Format[5], 2) - 1; + tm.tm_mday = atoi(&iso8601Format[8], 2); + tm.tm_hour = atoi(&iso8601Format[11], 2); + tm.tm_min = atoi(&iso8601Format[14], 2); + tm.tm_sec = atoi(&iso8601Format[17], 2); + HwClock::Get()->AlarmSet(&tm); + + DEBUG_EXIT + return; + } + + DEBUG_EXIT +} +} // namespace rtc +} // namespace remoteconfig diff --git a/lib-hal/src/gd32/hardware.cpp b/lib-hal/src/gd32/hardware.cpp index 57a96564..2795b715 100644 --- a/lib-hal/src/gd32/hardware.cpp +++ b/lib-hal/src/gd32/hardware.cpp @@ -2,7 +2,7 @@ * @file hardware.cpp * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -25,14 +25,18 @@ #include #include +#include #include #include "hardware.h" +#include "panel_led.h" #include "gd32.h" #include "gd32_i2c.h" #include "gd32_adc.h" -#include "gd32_board.h" +#if defined (CONFIG_ENET_ENABLE_PTP) +# include "gd32_ptp.h" +#endif #if defined (DEBUG_I2C) # include "../debug/i2c/i2cdetect.h" @@ -42,44 +46,92 @@ void usb_init(); #endif +#include "logic_analyzer.h" + #include "debug.h" +#if (defined (GD32F4XX) || defined (GD32H7XX)) && defined(GPIO_INIT) +# error +#endif + extern "C" { -void console_init(void); -void __libc_init_array(void); void systick_config(void); } +void console_init(); void udelay_init(); void gd32_adc_init(); -Hardware *Hardware::s_pThis = nullptr; +#if defined (GD32H7XX) +void cache_enable(); +void mpu_config(); +#endif + +namespace hal { +void uuid_init(uuid_t out); +} // namespace hardware + +namespace net { +void net_shutdown(); +} // namespace net + +void timer6_config(); +#if !defined (CONFIG_ENET_ENABLE_PTP) +# if defined (CONFIG_TIME_USE_TIMER) +# if defined(GD32H7XX) +void timer16_config(); +# else +void timer7_config(); +# endif +# endif +#endif + +Hardware *Hardware::s_pThis; Hardware::Hardware() { - DEBUG_ENTRY assert(s_pThis == nullptr); s_pThis = this; - console_init(); -#if !defined (ENABLE_TFTP_SERVER) - __libc_init_array(); +#if defined (GD32H7XX) + cache_enable(); + mpu_config(); #endif + + console_init(); + timer6_config(); +#if defined (CONFIG_HAL_USE_SYSTICK) systick_config(); +#endif +#if !defined (CONFIG_ENET_ENABLE_PTP) +# if defined (CONFIG_TIME_USE_TIMER) +# if defined(GD32H7XX) + timer16_config(); +# else + timer7_config(); +# endif +# endif +#endif udelay_init(); + hal::uuid_init(m_uuid); gd32_adc_init(); gd32_i2c_begin(); rcu_periph_clock_enable(RCU_TIMER5); + timer_deinit(TIMER5); + timer_parameter_struct timer_initpara; + timer_struct_para_init(&timer_initpara); + timer_initpara.prescaler = TIMER_PSC_1MHZ; timer_initpara.period = static_cast(~0); timer_init(TIMER5, &timer_initpara); timer_enable(TIMER5); -#if !defined (GD32F4XX) -#else +#if defined (GD32H7XX) +#elif defined (GD32F4XX) rcu_timer_clock_prescaler_config(RCU_TIMER_PSC_MUL4); +#else #endif #ifndef NDEBUG @@ -89,30 +141,45 @@ Hardware::Hardware() { const auto nAPB2 = rcu_clock_freq_get(CK_APB2); printf("CK_SYS=%u\nCK_AHB=%u\nCK_APB1=%u\nCK_APB2=%u\n", nSYS, nAHB, nAPB1, nAPB2); assert(nSYS == MCU_CLOCK_FREQ); + assert(nAHB == AHB_CLOCK_FREQ); assert(nAPB1 == APB1_CLOCK_FREQ); assert(nAPB2 == APB2_CLOCK_FREQ); +# if defined (GD32H7XX) + const auto nAPB3 = rcu_clock_freq_get(CK_APB3); + const auto nAPB4 = rcu_clock_freq_get(CK_APB4); + printf("nCK_APB3=%u\nCK_APB4=%u\n", nAPB3, nAPB4); + assert(nAPB3 == APB3_CLOCK_FREQ); + assert(nAPB4 == APB4_CLOCK_FREQ); +# endif #endif -#if !defined (GD32F4XX) - rcu_periph_clock_enable (RCU_BKPI); - rcu_periph_clock_enable (RCU_PMU); - pmu_backup_write_enable(); -#else +#if defined (GD32H7XX) + rcu_periph_clock_enable(RCU_PMU); + rcu_periph_clock_enable(RCU_BKPSRAM); + pmu_backup_write_enable(); +#elif defined (GD32F4XX) + rcu_periph_clock_enable(RCU_RTC); rcu_periph_clock_enable(RCU_PMU); pmu_backup_ldo_config(PMU_BLDOON_ON); rcu_periph_clock_enable(RCU_BKPSRAM); pmu_backup_write_enable(); +#else + rcu_periph_clock_enable (RCU_BKPI); + rcu_periph_clock_enable (RCU_PMU); + pmu_backup_write_enable(); #endif bkp_data_write(BKP_DATA_1, 0x0); #if !defined (ENABLE_TFTP_SERVER) -# if defined (GD32F207RG) || defined (GD32F4XX) +# if defined (GD32F207RG) || defined (GD32F4XX) || defined (GD32H7XX) +# if !defined (GD32H7XX) // clear section .dmx extern unsigned char _sdmx; extern unsigned char _edmx; DEBUG_PRINTF("clearing .dmx at %p, size %u", &_sdmx, &_edmx - &_sdmx); memset(&_sdmx, 0, &_edmx - &_sdmx); -# if defined (GD32F450VI) +# endif +# if defined (GD32F450VI) || defined (GD32H7XX) // clear section .lightset extern unsigned char _slightset; extern unsigned char _elightset; @@ -124,7 +191,7 @@ Hardware::Hardware() { extern unsigned char _enetwork; DEBUG_PRINTF("clearing .network at %p, size %u", &_snetwork, &_enetwork - &_snetwork); memset(&_snetwork, 0, &_enetwork - &_snetwork); -# if !defined (GD32F450VE) +# if !defined (GD32F450VE) && !defined (GD32H7XX) // clear section .pixel extern unsigned char _spixel; extern unsigned char _epixel; @@ -133,7 +200,7 @@ Hardware::Hardware() { # endif # endif #else -# if defined (GD32F207RG) || defined (GD32F4XX) +# if defined (GD32F20X) || defined (GD32F4XX) || defined (GD32H7XX) // clear section .network extern unsigned char _snetwork; extern unsigned char _enetwork; @@ -142,131 +209,81 @@ Hardware::Hardware() { # endif #endif +#if !defined (CONFIG_ENET_ENABLE_PTP) struct tm tmbuf; - - tmbuf.tm_hour = 0; - tmbuf.tm_min = 0; - tmbuf.tm_sec = 0; + memset(&tmbuf, 0, sizeof(struct tm)); tmbuf.tm_mday = _TIME_STAMP_DAY_; // The day of the month, in the range 1 to 31. tmbuf.tm_mon = _TIME_STAMP_MONTH_ - 1; // The number of months since January, in the range 0 to 11. tmbuf.tm_year = _TIME_STAMP_YEAR_ - 1900; // The number of years since 1900. - tmbuf.tm_isdst = 0; // 0 (DST not in effect, just take RTC time) const auto seconds = mktime(&tmbuf); const struct timeval tv = { seconds, 0 }; settimeofday(&tv, nullptr); - -#if defined (DEBUG_I2C) - I2cDetect i2cdetect; #endif #if !defined(DISABLE_RTC) m_HwClock.RtcProbe(); m_HwClock.Print(); +# if !defined (CONFIG_ENET_ENABLE_PTP) + // Set the System Clock from the Hardware Clock m_HwClock.HcToSys(); +# endif #endif -#if !defined(USE_LEDBLINK_BITBANGING595) +#if !defined(CONFIG_LEDBLINK_USE_PANELLED) rcu_periph_clock_enable(LED_BLINK_GPIO_CLK); -# if !defined (GD32F4XX) +# if defined (GPIO_INIT) gpio_init(LED_BLINK_GPIO_PORT, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, LED_BLINK_PIN); # else gpio_mode_set(LED_BLINK_GPIO_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LED_BLINK_PIN); - gpio_output_options_set(LED_BLINK_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, LED_BLINK_PIN); + gpio_output_options_set(LED_BLINK_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED, LED_BLINK_PIN); # endif - GPIO_BC(LED_BLINK_GPIO_PORT) = LED_BLINK_PIN; + GPIO_BOP(LED_BLINK_GPIO_PORT) = LED_BLINK_PIN; #endif -#if defined (LEDPANEL_595_CS_GPIOx) - rcu_periph_clock_enable(LEDPANEL_595_CS_RCU_GPIOx); -# if !defined (GD32F4XX) - gpio_init(LEDPANEL_595_CS_GPIOx, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, LEDPANEL_595_CS_GPIO_PINx); +#if defined (PANELLED_595_CS_GPIOx) + rcu_periph_clock_enable(PANELLED_595_CS_RCU_GPIOx); +# if defined (GPIO_INIT) + gpio_init(PANELLED_595_CS_GPIOx, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, PANELLED_595_CS_GPIO_PINx); # else - gpio_mode_set(LEDPANEL_595_CS_GPIOx, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LEDPANEL_595_CS_GPIO_PINx); - gpio_output_options_set(LEDPANEL_595_CS_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, LEDPANEL_595_CS_GPIO_PINx); + gpio_mode_set(PANELLED_595_CS_GPIOx, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, PANELLED_595_CS_GPIO_PINx); + gpio_output_options_set(PANELLED_595_CS_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED, PANELLED_595_CS_GPIO_PINx); # endif - GPIO_BOP(LEDPANEL_595_CS_GPIOx) = LEDPANEL_595_CS_GPIO_PINx; + GPIO_BOP(PANELLED_595_CS_GPIOx) = PANELLED_595_CS_GPIO_PINx; #endif + hal::panel_led_init(); + #if defined ENABLE_USB_HOST usb_init(); #endif - DEBUG_EXIT -} - -typedef union pcast32 { - uuid_t uuid; - uint32_t u32[4]; -} _pcast32; - -void Hardware::GetUuid(uuid_t out) { - _pcast32 cast; + logic_analyzer::init(); -#if !defined (GD32F4XX) - cast.u32[0] = *(volatile uint32_t*) (0x1FFFF7E8); - cast.u32[1] = *(volatile uint32_t*) (0x1FFFF7EC); - cast.u32[2] = *(volatile uint32_t*) (0x1FFFF7F0); -#else - cast.u32[0] = *(volatile uint32_t*) (0x1FFF7A10); - cast.u32[1] = *(volatile uint32_t*) (0x1FFF7A14); - cast.u32[2] = *(volatile uint32_t*) (0x1FFF7A18); +#if defined (DEBUG_I2C) + I2cDetect i2cdetect; #endif - cast.u32[3] = cast.u32[0] + cast.u32[1] + cast.u32[2]; - memcpy(out, cast.uuid, sizeof(uuid_t)); + SetFrequency(1U); } -bool Hardware::SetTime(__attribute__((unused)) const struct tm *pTime) { - DEBUG_ENTRY +bool Hardware::Reboot() { + puts("Rebooting ..."); + #if !defined(DISABLE_RTC) - rtc_time rtc_time; - - rtc_time.tm_sec = pTime->tm_sec; - rtc_time.tm_min = pTime->tm_min; - rtc_time.tm_hour = pTime->tm_hour; - rtc_time.tm_mday = pTime->tm_mday; - rtc_time.tm_mon = pTime->tm_mon; - rtc_time.tm_year = pTime->tm_year; - - m_HwClock.Set(&rtc_time); - - DEBUG_EXIT - return true; -#else - DEBUG_EXIT - return false; + m_HwClock.SysToHc(); #endif -} - -void Hardware::GetTime(struct tm *pTime) { - auto ltime = time(nullptr); - const auto *local_time = localtime(<ime); - pTime->tm_year = local_time->tm_year; - pTime->tm_mon = local_time->tm_mon; - pTime->tm_mday = local_time->tm_mday; - pTime->tm_hour = local_time->tm_hour; - pTime->tm_min = local_time->tm_min; - pTime->tm_sec = local_time->tm_sec; -} - -#include - -bool Hardware::Reboot() { - printf("Rebooting ...\n"); WatchdogStop(); - + RebootHandler(); - WatchdogInit(); + net::net_shutdown(); - SetMode(hardware::ledblink::Mode::REBOOT); + SetMode(hardware::ledblink::Mode::OFF_OFF); - for (;;) { - Run(); - } + NVIC_SystemReset(); __builtin_unreachable(); return true; diff --git a/lib-hal/src/hardware.cpp b/lib-hal/src/hardware.cpp index c25347ad..706f1853 100755 --- a/lib-hal/src/hardware.cpp +++ b/lib-hal/src/hardware.cpp @@ -2,7 +2,7 @@ * @file hardware.cpp * */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,16 +28,15 @@ #include "hardware.h" #include "debug.h" -namespace hardware { -namespace ledblink { -void __attribute__((weak)) display(__attribute__((unused)) const uint32_t nState) {} -} // namespace ledblink -} // namespace hardware +namespace hardware::ledblink { +void __attribute__((weak)) display([[maybe_unused]] const uint32_t nState) {} +} // namespace hardware::ledblink enum class FreqMode { OFF_OFF = 0, NORMAL = 1, DATA = 3, FAST = 5, REBOOT = 8, OFF_ON = 255 }; +#if !defined (CONFIG_HAL_USE_MINIMUM) void Hardware::SetModeWithLock(hardware::ledblink::Mode mode, bool doLock) { m_doLock = false; SetMode(mode); @@ -79,3 +78,4 @@ void Hardware::SetMode(hardware::ledblink::Mode mode) { DEBUG_PRINTF("Mode=%d", static_cast(m_Mode)); } +#endif diff --git a/lib-hal/src/json_datetime.cpp b/lib-hal/src/json_datetime.cpp new file mode 100755 index 00000000..6b07ae64 --- /dev/null +++ b/lib-hal/src/json_datetime.cpp @@ -0,0 +1,125 @@ +/** + * @file json_datetime.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include +#include +#include + +#include "configstore.h" + +#include "debug.h" + +namespace remoteconfig { +namespace timedate { +static int atoi(const char *pBuffer, uint32_t nSize) { + assert(pBuffer != nullptr); + assert(nSize <= 4); + + const char *p = pBuffer; + int32_t res = 0; + + for (; (nSize > 0) && (*p >= '0' && *p <= '9'); nSize--) { + res = res * 10 + *p - '0'; + p++; + } + + return res; +} + +uint32_t json_get_timeofday(char *pOutBuffer, const uint32_t nOutBufferSize) { + DEBUG_ENTRY + + struct timeval tv; + if (gettimeofday(&tv, nullptr) >= 0) { + auto *tm = localtime(&tv.tv_sec); + + int8_t nHours; + uint8_t nMinutes; + ConfigStore::Get()->GetEnvUtcOffset(nHours, nMinutes); + + if ((nHours == 0) && (nMinutes == 0)) { + const auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, + "{\"date\":\"%d-%.2d-%.2dT%.2d:%.2d:%.2dZ\"}\n", + 1900 + tm->tm_year, 1 + tm->tm_mon, tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec)); + + DEBUG_EXIT + return nLength; + } else { + const auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, + "{\"date\":\"%d-%.2d-%.2dT%.2d:%.2d:%.2d%s%.2d:%.2u\"}\n", + 1900 + tm->tm_year, 1 + tm->tm_mon, tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec, + nHours > 0 ? "+" : "", nHours, nMinutes)); + + DEBUG_EXIT + return nLength; + } + } + + DEBUG_EXIT + return 0; +} + +void json_set_timeofday(const char *pBuffer, const uint32_t nBufferSize) { + DEBUG_ENTRY + debug_dump(pBuffer, nBufferSize); + + if ((nBufferSize == 26) || (nBufferSize == 31)) { + struct tm tm; + tm.tm_year = atoi(&pBuffer[5], 4) - 1900; + tm.tm_mon = atoi(&pBuffer[10], 2) - 1; + tm.tm_mday = atoi(&pBuffer[13], 2); + tm.tm_hour = atoi(&pBuffer[16], 2); + tm.tm_min = atoi(&pBuffer[19], 2); + tm.tm_sec = atoi(&pBuffer[22], 2); + + struct timeval tv; + tv.tv_sec = mktime(&tm); + tv.tv_usec = 0; + + if (nBufferSize == 26) { + assert(pBuffer[23] == 'Z'); + } else { + const int8_t nSign = pBuffer[24] == '-' ? -1 : 1; + const auto nHours = static_cast(atoi(&pBuffer[25], 2) * nSign); + const auto nMinutes = static_cast(atoi(&pBuffer[28], 2)); + + ConfigStore::Get()->SetEnvUtcOffset(nHours, nMinutes); + + tv.tv_sec = tv.tv_sec - ConfigStore::Get()->GetEnvUtcOffset(); + } + + settimeofday(&tv, nullptr); + + DEBUG_PRINTF("%.4d/%.2d/%.2d %.2d:%.2d:%.2d", 1900 + tm.tm_year, 1 + tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); + DEBUG_EXIT + return; + } + + DEBUG_EXIT +} +} // namespace timedate +} // namespace remoteconfig diff --git a/lib-hal/src/json_get_directory.cpp b/lib-hal/src/json_get_directory.cpp new file mode 100755 index 00000000..67ae9b88 --- /dev/null +++ b/lib-hal/src/json_get_directory.cpp @@ -0,0 +1,96 @@ +/** + * @file json_get_directory.cpp + * + */ +/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include +#include +#ifndef NDEBUG +# include +#endif + +namespace remoteconfig { +namespace storage { +static bool filter(const char *pName) { + return *pName == '.'; +} + +uint32_t json_get_directory(char *pOutBuffer, const uint32_t nOutBufferSize) { + const auto nBufferSize = nOutBufferSize - 2U; +#if defined (__linux__) || defined (__APPLE__) + auto *dirp = opendir("storage"); +#elif defined (CONFIG_USB_HOST_MSC) + auto *dirp = opendir("0:/"); +#else + auto *dirp = opendir("."); +#endif +#ifndef NDEBUG + perror("opendir"); +#endif + + auto nLength = static_cast(snprintf(pOutBuffer, nBufferSize, "{\"label\":\"%s\",\"files\":[", (dirp != nullptr) ? "storage" : "No storage")); + + if (dirp != nullptr) { + struct dirent *dp; + do { + if ((dp = readdir(dirp)) != nullptr) { + if (dp->d_type == DT_DIR) { + continue; + } + + if (filter(dp->d_name)) { + continue; + } + + const auto nSize = nBufferSize - nLength; + const auto nCharacters = static_cast(snprintf(&pOutBuffer[nLength], nSize, "\"%s\",", dp->d_name)); + + if (nCharacters > nSize) { + break; + } + + nLength+=nCharacters; + + if (nLength >= nBufferSize) { + break; + } + } + } while (dp != nullptr); + + closedir(dirp); + + if (pOutBuffer[nLength - 1] == ',') { + nLength--; + } + } + + pOutBuffer[nLength++] = ']'; + pOutBuffer[nLength++] = '}'; + + assert(nLength <= nOutBufferSize); + return nLength; +} +} // namespace storage +} // namespace remoteconfig diff --git a/lib-lightset/.cproject b/lib-lightset/.cproject index 7710fa78..0eb196bf 100644 --- a/lib-lightset/.cproject +++ b/lib-lightset/.cproject @@ -30,12 +30,10 @@ - diff --git a/lib-lightset/Rules.mk b/lib-lightset/Rules.mk index a36ce7e5..5922504e 100644 --- a/lib-lightset/Rules.mk +++ b/lib-lightset/Rules.mk @@ -1,10 +1,4 @@ ifneq ($(MAKE_FLAGS),) - ifeq ($(findstring ESP8266,$(MAKE_FLAGS)), ESP8266) - EXTRA_SRCDIR+=src/esp8266 - endif else DEFINES+=OUTPUT_HAVE_STYLESWITCH - DEFINES+=LIGHTSET_HAVE_RUN - DEFINES+=ESP8266 - EXTRA_SRCDIR+=src/esp8266 endif \ No newline at end of file diff --git a/lib-lightset/include/lightset.h b/lib-lightset/include/lightset.h index 04f7598c..28a72272 100755 --- a/lib-lightset/include/lightset.h +++ b/lib-lightset/include/lightset.h @@ -2,7 +2,7 @@ * @file lightset.h * */ -/* Copyright (C) 2016-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2016-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -43,7 +43,7 @@ namespace node { static constexpr uint32_t LABEL_NAME_LENGTH = 18; inline void get_short_name_default(const uint32_t nPortIndex, char *pShortName) { - snprintf(pShortName, node::LABEL_NAME_LENGTH - 1, "Port %u", 1U + nPortIndex); + snprintf(pShortName, node::LABEL_NAME_LENGTH - 1, "Port %u", static_cast(1 + nPortIndex)); } } // namespace node @@ -68,12 +68,6 @@ struct SlotInfo { uint8_t nType; }; -#if defined (ESP8266) -enum class OutputType { - DMX, SPI, MONITOR, UNDEFINED -}; -#endif - inline MergeMode get_merge_mode(const char *pMergeMode) { if (pMergeMode != nullptr) { if (((pMergeMode[0] | 0x20) == 'l') @@ -85,14 +79,14 @@ inline MergeMode get_merge_mode(const char *pMergeMode) { return MergeMode::HTP; } -inline const char* get_merge_mode(const MergeMode mergeMode, const bool bToUpper = false) { +inline const char *get_merge_mode(const MergeMode mergeMode, const bool bToUpper = false) { if (bToUpper) { return (mergeMode == MergeMode::HTP) ? "HTP" : "LTP"; } return (mergeMode == MergeMode::HTP) ? "htp" : "ltp"; } -inline const char* get_merge_mode(const unsigned m, const bool bToUpper = false) { +inline const char *get_merge_mode(const unsigned m, const bool bToUpper = false) { return get_merge_mode(static_cast(m), bToUpper); } @@ -151,27 +145,15 @@ inline FailSafe get_failsafe(const char *pFailSafe) { } inline const char* get_failsafe(const FailSafe failsafe) { - switch (failsafe) { - case FailSafe::HOLD: - return "hold"; - break; - case FailSafe::OFF: + if (failsafe == FailSafe::OFF) { return "off"; - break; - case FailSafe::ON: + } else if (failsafe == FailSafe::ON) { return "on"; - break; - case FailSafe::PLAYBACK: + } else if (failsafe == FailSafe::PLAYBACK) { return "playback"; - break; - default: - assert(0); - __builtin_unreachable(); - break; } - __builtin_unreachable(); - return ""; + return "hold"; } inline OutputStyle get_output_style(const char *pOutputStyle) { @@ -203,38 +185,38 @@ class LightSet { virtual void Start(const uint32_t nPortIndex)= 0; virtual void Stop(const uint32_t nPortIndex)= 0; - virtual void SetData(uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength, const bool doUpdate = true)= 0; + virtual void SetData(const uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength, const bool doUpdate = true)= 0; /** * This is used for preparing the lightset output for a SYNC * Typically used with DMX512 output * @param [IN] PortIndex */ virtual void Sync(const uint32_t PortIndex)= 0; - /** - * - * @param [IN] doForce This parameter is used with Art-Net ArtSync only. - */ - virtual void Sync(const bool doForce = false)= 0; + virtual void Sync()= 0; #if defined (OUTPUT_HAVE_STYLESWITCH) virtual void SetOutputStyle(const uint32_t nPortIndex, const lightset::OutputStyle outputStyle)=0; virtual lightset::OutputStyle GetOutputStyle(const uint32_t nPortIndex) const=0; #endif // Optional - virtual void Blackout(__attribute__((unused)) bool bBlackout) {} + virtual uint32_t GetRefreshRate() { return 0; } + virtual void Blackout([[maybe_unused]] bool bBlackout) {} virtual void FullOn() {} virtual void Print() {} // RDM Optional - virtual bool SetDmxStartAddress(uint16_t nDmxStartAddress); - virtual uint16_t GetDmxStartAddress(); - virtual uint16_t GetDmxFootprint(); - virtual bool GetSlotInfo(uint16_t nSlotOffset, lightset::SlotInfo &tSlotInfo); -#if defined (LIGHTSET_HAVE_RUN) - virtual void Run()= 0; -#endif -#if defined (ESP8266) - static const char *GetOutputType(lightset::OutputType type); - static lightset::OutputType GetOutputType(const char *sType); -#endif + virtual bool SetDmxStartAddress([[maybe_unused]] const uint16_t nDmxStartAddress) { + return false; + } + virtual uint16_t GetDmxStartAddress() { + return lightset::dmx::START_ADDRESS_DEFAULT; + } + virtual uint16_t GetDmxFootprint() { + return lightset::dmx::UNIVERSE_SIZE; + } + virtual bool GetSlotInfo([[maybe_unused]] const uint16_t nSlotOffset, lightset::SlotInfo &slotInfo) { + slotInfo.nType = 0x00; // ST_PRIMARY + slotInfo.nCategory = 0x0001; // SD_INTENSITY + return true; + } }; #endif /* LIGHTSET_H_ */ diff --git a/lib-lightset/include/lightsetdata.h b/lib-lightset/include/lightsetdata.h old mode 100644 new mode 100755 index 95f74647..b55a29da --- a/lib-lightset/include/lightsetdata.h +++ b/lib-lightset/include/lightsetdata.h @@ -2,7 +2,7 @@ * @file lightsetdata.h * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -38,7 +38,7 @@ * https://www.gd32-dmx.org/memory.html */ # include "gd32.h" -# if defined (GD32F450VI) +# if defined (GD32F450VI) || defined (GD32H7XX) # define SECTION_LIGHTSET __attribute__ ((section (".lightset"))) # else # define SECTION_LIGHTSET @@ -50,7 +50,7 @@ namespace lightset { class Data { public: - Data(const Data&) = delete; +// Data(const Data&) = delete; static Data& Get() { static Data instance SECTION_LIGHTSET; @@ -89,6 +89,10 @@ class Data { Get().IClearLength(nPortIndex); } + static uint32_t GetLength(const uint32_t nPortIndex) { + return Get().IGetLength(nPortIndex); + } + static const uint8_t *Backup(const uint32_t nPortIndex) { return Get().IBackup(nPortIndex); } @@ -98,7 +102,7 @@ class Data { } private: - Data() {} +// Data() {} void IMergeSourceA(const uint32_t nPortIndex, const uint8_t *pData, const uint32_t nLength, const MergeMode mergeMode) { assert(nPortIndex < PORTS); @@ -169,6 +173,10 @@ class Data { m_OutputPort[nPortIndex].nLength = 0; } + uint32_t IGetLength(const uint32_t nPortIndex) const { + return m_OutputPort[nPortIndex].nLength; + } + const uint8_t *IBackup(const uint32_t nPortIndex) { assert(nPortIndex < PORTS); return const_cast(m_OutputPort[nPortIndex].data); @@ -193,13 +201,13 @@ class Data { #endif struct Source { - uint8_t data[dmx::UNIVERSE_SIZE]; + uint8_t data[dmx::UNIVERSE_SIZE] __attribute__ ((aligned (4))); }; struct OutputPort { Source sourceA; Source sourceB; - uint8_t data[dmx::UNIVERSE_SIZE]; + uint8_t data[dmx::UNIVERSE_SIZE] __attribute__ ((aligned (4))); uint32_t nLength; }; diff --git a/lib-lightset/src/dmxslotinfo.cpp b/lib-lightset/src/dmxslotinfo.cpp index c5dc365a..b12e1a20 100644 --- a/lib-lightset/src/dmxslotinfo.cpp +++ b/lib-lightset/src/dmxslotinfo.cpp @@ -2,7 +2,7 @@ * @file dmxslotinfo.h * */ -/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -140,7 +140,7 @@ const char *DmxSlotInfo::ToString(uint32_t nMask) { void DmxSlotInfo::Dump() { for (uint32_t i = 0; i < m_nSize; i++) { - printf(" Slot:%d %.2X:%.4X\n", i, m_pSlotInfo[i].nType, m_pSlotInfo[i].nCategory); + printf(" Slot:%u %.2X:%.4X\n", static_cast(i), m_pSlotInfo[i].nType, m_pSlotInfo[i].nCategory); } } diff --git a/lib-network/.cproject b/lib-network/.cproject index 5e671f68..43ab5ac3 100644 --- a/lib-network/.cproject +++ b/lib-network/.cproject @@ -30,11 +30,9 @@ - diff --git a/lib-network/Makefile.GD32 b/lib-network/Makefile.GD32 index aaed2317..161f1c6b 100644 --- a/lib-network/Makefile.GD32 +++ b/lib-network/Makefile.GD32 @@ -1,15 +1,41 @@ -DEFINES =DISABLE_FS +$(info "lib-network/Makefile.GD32") + +DEFINES =DISABLE_FS DEFINES+=NDEBUG -EXTRA_INCLUDES=../lib-properties/include +EXTRA_INCLUDES=../lib-properties/include ../lib-display/include EXTRA_SRCDIR=src/emac/gd32 -ifeq ($(findstring RTL8201F,$(PHY_TYPE)), RTL8201F) - EXTRA_SRCDIR+=src/emac/gd32/rtl8201f - DEFINES+=RTL8201F_LED1_LINK_ALL - DEFINES+=ENET_LINK_CHECK_USE_INT +ifneq ($(MAKE_FLAGS),) + ifeq ($(findstring gd32f10x,$(FAMILY)), gd32f10x) + EXTRA_SRCDIR+=src/emac/gd32/f + endif + ifeq ($(findstring gd32f20x,$(FAMILY)), gd32f20x) + EXTRA_SRCDIR+=src/emac/gd32/f + endif + ifeq ($(findstring gd32f4xx,$(FAMILY)), gd32f4xx) + EXTRA_SRCDIR+=src/emac/gd32/f + endif + ifeq ($(findstring gd32h7xx,$(FAMILY)), gd32h7xx) + EXTRA_SRCDIR+=src/emac/gd32/h + endif + + ifeq ($(findstring RTL8201F,$(MAKE_FLAGS)), RTL8201F) + EXTRA_SRCDIR+=src/emac/gd32/rtl8201f + endif + + ifeq ($(findstring ENABLE_PHY_SWITCH,$(MAKE_FLAGS)), ENABLE_PHY_SWITCH) + EXTRA_SRCDIR+=src/emac/gd32/dsa/88e6161 + endif + + ifeq ($(findstring CONFIG_ENET_ENABLE_PTP,$(MAKE_FLAGS)), CONFIG_ENET_ENABLE_PTP) + ifeq ($(findstring ENABLE_NTP_PTP_CLIENT,$(MAKE_FLAGS)), ENABLE_NTP_PTP_CLIENT) + EXTRA_SRCDIR+=src/net/apps/ntp/gd32/ptp + endif + endif else - #DEFINES+=ENET_LINK_CHECK_REG_POLL + EXTRA_SRCDIR+=src/emac/gd32/f + ENET_PHY=RTL8201F endif include Rules.mk diff --git a/lib-network/Rules.mk b/lib-network/Rules.mk index 069b63b0..15e929df 100644 --- a/lib-network/Rules.mk +++ b/lib-network/Rules.mk @@ -15,9 +15,9 @@ ifneq ($(MAKE_FLAGS),) endif endif ifndef COND - EXTRA_SRCDIR+=src/apps/mdns src/apps/ntp src/apps/tftp - EXTRA_SRCDIR+=src/emac src/params src/net - EXTRA_SRCDIR+=src/emac/phy + EXTRA_SRCDIR+=src/net/apps/mdns src/net/apps/ntp src/net/apps/tftp + EXTRA_SRCDIR+=src/emac src/net src/emac/phy + EXTRA_SRCDIR+=src/params ifeq ($(findstring ENABLE_PHY_SWITCH,$(MAKE_FLAGS)), ENABLE_PHY_SWITCH) EXTRA_SRCDIR+=src/emac/dsa endif @@ -39,9 +39,10 @@ ifneq ($(MAKE_FLAGS),) endif endif else - EXTRA_SRCDIR+=src/apps/mdns src/apps/ntp src/apps/tftp + EXTRA_SRCDIR+=src/net/apps/mdns src/net/apps/ntp src/net/apps/tftp EXTRA_SRCDIR+=src/emac src/net EXTRA_SRCDIR+=src/emac/phy EXTRA_SRCDIR+=src/emac/phy/dp83848 src/emac/phy/lan8700 src/emac/phy/phygen src/emac/phy/rtl8201f + EXTRA_SRCDIR+=src/params DEFINES+=RTL8201F_LED1_LINK_ALL endif diff --git a/lib-network/config/apps_config.h b/lib-network/config/apps_config.h index d2bc3a38..3e82f26e 100644 --- a/lib-network/config/apps_config.h +++ b/lib-network/config/apps_config.h @@ -2,7 +2,7 @@ * @file apps_config * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,7 +26,9 @@ #ifndef APPS_CONFIG_H_ #define APPS_CONFIG_H_ -#if defined (BARE_METAL) +#if defined(__linux__) || defined (__APPLE__) +# define MDNS_SERVICE_RECORDS_MAX 8 +#else # if defined (H3) # define MDNS_SERVICE_RECORDS_MAX 8 # elif defined (GD32) @@ -36,8 +38,6 @@ # else # error # endif -#else -# define MDNS_SERVICE_RECORDS_MAX 8 #endif #if !defined (MDNS_SERVICE_RECORDS_MAX) diff --git a/lib-network/config/net_config.h b/lib-network/config/net_config.h index 550dd2df..96ce794a 100644 --- a/lib-network/config/net_config.h +++ b/lib-network/config/net_config.h @@ -2,7 +2,7 @@ * @file net_config * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,26 +26,40 @@ #ifndef NET_CONFIG_H_ #define NET_CONFIG_H_ -#if defined (BARE_METAL) -# define TCP_MAX_PORTS_ALLOWED 1 +#if defined(__linux__) || defined (__APPLE__) +# define UDP_MAX_PORTS_ALLOWED 16 +# define IGMP_MAX_JOINS_ALLOWED (4 + (8 * 4)) /* 8 outputs x 4 Universes */ +# define TCP_MAX_TCBS_ALLOWED 16 +# define TCP_MAX_PORTS_ALLOWED 2 +#else +# define TCP_MAX_PORTS_ALLOWED 1 # if defined (H3) -# define HOST_NAME_PREFIX "allwinner_" +# if !defined(HOST_NAME_PREFIX) +# define HOST_NAME_PREFIX "allwinner_" +# endif # define UDP_MAX_PORTS_ALLOWED 16 # define IGMP_MAX_JOINS_ALLOWED (4 + (8 * 4)) /* 8 outputs x 4 Universes */ +# define TCP_MAX_TCBS_ALLOWED 16 # elif defined (GD32) +/* + * Supports checking IPv4 header checksum and TCP, UDP, or ICMP checksum encapsulated in IPv4 or IPv6 datagram. + */ # define CHECKSUM_BY_HARDWARE -# define HOST_NAME_PREFIX "gigadevice_" +# if !defined(HOST_NAME_PREFIX) +# define HOST_NAME_PREFIX "gigadevice_" +# endif # if !defined (UDP_MAX_PORTS_ALLOWED) # define UDP_MAX_PORTS_ALLOWED 8 # endif # if !defined (IGMP_MAX_JOINS_ALLOWED) # define IGMP_MAX_JOINS_ALLOWED (4 + (8 * 4)) /* 8 outputs x 4 Universes */ # endif +# if !defined (TCP_MAX_TCBS_ALLOWED) +# define TCP_MAX_TCBS_ALLOWED 6 +# endif # else # error # endif -#else -# error #endif #if !defined (UDP_MAX_PORTS_ALLOWED) @@ -60,4 +74,8 @@ # error #endif +#if !defined (TCP_MAX_TCBS_ALLOWED) +# error +#endif + #endif /* NET_CONFIG_H_ */ diff --git a/lib-network/include/emac/emac.h b/lib-network/include/emac/emac.h index dbb8597a..61eb20e7 100755 --- a/lib-network/include/emac/emac.h +++ b/lib-network/include/emac/emac.h @@ -1,5 +1,26 @@ -/* - * emac.h +/** + * @file emac.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. */ #ifndef EMAC_EMAC_H_ diff --git a/lib-network/include/emac/network.h b/lib-network/include/emac/network.h index 0e946b21..ffd368ae 100755 --- a/lib-network/include/emac/network.h +++ b/lib-network/include/emac/network.h @@ -2,7 +2,7 @@ * @file network.h * */ -/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -30,6 +30,17 @@ # error This file should not be included #endif +#if !defined (HAVE_NET_HANDLE) +# define HAVE_NET_HANDLE +#endif + +namespace net { +void dhcp_run(); +#if defined (CONFIG_ENET_ENABLE_PTP) +void ptp_run(); +#endif +} // namespace net + #include #include #include @@ -37,7 +48,10 @@ #include "networkparams.h" -#include "../src/net/net.h" +#include "net.h" +#include "netif.h" +#include "ip4_address.h" +#include "net/dhcp.h" #include "emac/net_link_check.h" @@ -45,42 +59,36 @@ class Network { public: - Network(NetworkParamsStore *pNetworkParamsStore); - ~Network() {} + Network(); + ~Network() = default; void Print(); - void Shutdown() { - network::display_emac_shutdown(); - network::mdns_shutdown(); - net_shutdown(); - } - void MacAddressCopyTo(uint8_t *pMacAddress) { - memcpy(pMacAddress, m_aNetMacaddr, network::MAC_SIZE); + memcpy(pMacAddress, net::netif_hwaddr(), NETIF_MAX_HWADDR_LEN); } - uint32_t GetSecondaryIp() const { - return m_IpInfo.secondary_ip.addr; + uint32_t GetSecondaryIp() { + return net::netif_secondary_ipaddr(); } void SetIp(uint32_t nIp); - uint32_t GetIp() const { - return m_IpInfo.ip.addr; + uint32_t GetIp() { + return net::netif_ipaddr(); } void SetNetmask(uint32_t nNetmask); - uint32_t GetNetmask() const { - return m_IpInfo.netmask.addr; + uint32_t GetNetmask() { + return net::netif_netmask(); } void SetGatewayIp(uint32_t nGatewayIp); - uint32_t GetGatewayIp() const { - return m_IpInfo.gw.addr; + uint32_t GetGatewayIp() { + return net::netif_gw(); } - uint32_t GetBroadcastIp() const { - return m_IpInfo.broadcast_ip.addr; + uint32_t GetBroadcastIp() { + return net::netif_broadcast_ipaddr(); } /* @@ -91,18 +99,19 @@ class Network { return m_IsDhcpCapable; } - bool EnableDhcp(); + void EnableDhcp(); - bool IsDhcpUsed() const { - return m_IsDhcpUsed; + bool IsDhcpUsed() { + const auto b = net::netif_dhcp(); + return b; } bool IsDhcpKnown() const { return true; } - network::dhcp::Mode GetDhcpMode() const { - if (m_IsDhcpUsed) { + network::dhcp::Mode GetDhcpMode() { + if (IsDhcpUsed()) { return network::dhcp::Mode::ACTIVE; } @@ -110,22 +119,31 @@ class Network { } /* - * Zeroconf + * Zeroconf / autoip */ + void SetZeroconf(); + bool IsZeroconfUsed() const { + return net::netif_autoip(); + } + bool IsZeroconfCapable() const { return m_IsZeroconfCapable; } - bool SetZeroconf(); - bool IsZeroconfUsed() const { - return m_IsZeroconfUsed; - } + + /* + * Host name + */ void SetHostName(const char *pHostName); const char *GetHostName() const { return m_aHostName; } + /* + * Domain name + */ + void SetDomainName(const char *pDomainName) { strncpy(m_aDomainName, pDomainName, network::DOMAINNAME_SIZE - 1); m_aDomainName[network::DOMAINNAME_SIZE - 1] = '\0'; @@ -134,32 +152,62 @@ class Network { return m_aDomainName; } + /* + * Name servers + */ + + uint32_t GetNameServer(const uint32_t nIndex) const { + if (nIndex < network::NAMESERVERS_COUNT) { + return m_nNameservers[nIndex]; + } + + return 0; + } + + uint32_t GetNameServers() const { + return network::NAMESERVERS_COUNT; + } + + const char *GetIfName() const { + return m_aIfName; + } + + uint32_t GetIfIndex() const { + return 1; + } + /* * UDP/IP */ int32_t Begin(uint16_t nPort) { - const auto nIndex = udp_begin(nPort); + const auto nIndex = net::udp_begin(nPort); assert(nIndex != -1); return nIndex; } int32_t End(uint16_t nPort) { - const auto nIndex = udp_end(nPort); + const auto nIndex = net::udp_end(nPort); assert(nIndex == 0); return nIndex; } - uint16_t RecvFrom(int32_t nHandle, void *pBuffer, uint16_t nLength, uint32_t *from_ip, uint16_t *from_port) { - return udp_recv1(nHandle, reinterpret_cast(pBuffer), nLength, from_ip, from_port); + uint32_t RecvFrom(int32_t nHandle, void *pBuffer, uint32_t nLength, uint32_t *from_ip, uint16_t *from_port) { + return net::udp_recv1(nHandle, reinterpret_cast(pBuffer), nLength, from_ip, from_port); } - uint16_t RecvFrom(int32_t nHandle, const void **ppBuffer, uint32_t *pFromIp, uint16_t *pFromPort) { - return udp_recv2(nHandle, reinterpret_cast(ppBuffer), pFromIp, pFromPort); + uint32_t RecvFrom(int32_t nHandle, const void **ppBuffer, uint32_t *pFromIp, uint16_t *pFromPort) { + return net::udp_recv2(nHandle, reinterpret_cast(ppBuffer), pFromIp, pFromPort); } - void SendTo(int32_t nHandle, const void *pBuffer, uint16_t nLength, uint32_t to_ip, uint16_t remote_port) { - udp_send(nHandle, reinterpret_cast(pBuffer), nLength, to_ip, remote_port); + void SendTo(int32_t nHandle, const void *pBuffer, uint32_t nLength, uint32_t to_ip, uint16_t remote_port) { + if (__builtin_expect((GetIp() != 0), 1)) { + net::udp_send(nHandle, reinterpret_cast(pBuffer), nLength, to_ip, remote_port); + } + } + + void SendToTimestamp(int32_t nHandle, const void *pBuffer, uint32_t nLength, uint32_t to_ip, uint16_t remote_port) { + net::udp_send_timestamp(nHandle, reinterpret_cast(pBuffer), nLength, to_ip, remote_port); } /* @@ -167,33 +215,35 @@ class Network { */ int32_t TcpBegin(const uint16_t nLocalPort) { - return tcp_begin(nLocalPort); + return net::tcp_begin(nLocalPort); } int32_t TcpEnd(const int32_t nHandle); uint16_t TcpRead(const int32_t nHandleListen, const uint8_t **ppBuffer, uint32_t &HandleConnection) { - return tcp_read(nHandleListen, ppBuffer, HandleConnection); + return net::tcp_read(nHandleListen, ppBuffer, HandleConnection); } - void TcpWrite(const int32_t nHandleListen, const uint8_t *pBuffer, uint16_t nLength, const uint32_t HandleConnection) { - tcp_write(nHandleListen, pBuffer, nLength, HandleConnection); + void TcpWrite(const int32_t nHandleListen, const uint8_t *pBuffer, uint32_t nLength, const uint32_t HandleConnection) { + net::tcp_write(nHandleListen, pBuffer, nLength, HandleConnection); } /* * IGMP */ - void JoinGroup(__attribute__((unused)) int32_t nHandle, uint32_t nIp) { - igmp_join(nIp); + void JoinGroup([[maybe_unused]] int32_t nHandle, uint32_t nIp) { + net::igmp_join(nIp); } - void LeaveGroup(__attribute__((unused)) int32_t nHandle, uint32_t nIp) { - igmp_leave(nIp); + void LeaveGroup([[maybe_unused]] int32_t nHandle, uint32_t nIp) { + net::igmp_leave(nIp); } - void SetQueuedStaticIp(uint32_t nLocalIp = 0, uint32_t nNetmask = 0); - void SetQueuedDhcp() { + void SetQueuedStaticIp(const uint32_t nStaticIp, const uint32_t nNetmask); + void SetQueuedDefaultRoute(const uint32_t nGatewayIp); + void SetQueuedDhcp(const network::dhcp::Mode mode) { + m_QueuedConfig.mode = mode; m_QueuedConfig.nMask |= QueuedConfig::DHCP; } void SetQueuedZeroconf() { @@ -202,15 +252,15 @@ class Network { bool ApplyQueuedConfig(); - uint32_t GetNetmaskCIDR() const { - return static_cast(__builtin_popcount(m_IpInfo.netmask.addr)); + uint32_t GetNetmaskCIDR() { + return static_cast(__builtin_popcount(GetNetmask())); } char GetAddressingMode() { - if (Network::Get()->IsZeroconfUsed()) { + if (IsZeroconfUsed()) { return 'Z'; - } else if (Network::Get()->IsDhcpKnown()) { - if (Network::Get()->IsDhcpUsed()) { + } else if (IsDhcpKnown()) { + if (IsDhcpUsed()) { return 'D'; } else { return 'S'; @@ -220,28 +270,15 @@ class Network { return 'U'; } - const char *GetIfName() const { - return m_aIfName; - } - - uint32_t GetIfIndex() const { - return m_nIfIndex; - } - - uint32_t GetNtpServerIp() const { - return m_nNtpServerIp; - } - - float GetNtpUtcOffset() const { - return m_fNtpUtcOffset; - } - - bool IsValidIp(uint32_t nIp) { - return (m_IpInfo.ip.addr & m_IpInfo.netmask.addr) == (nIp & m_IpInfo.netmask.addr); + bool IsValidIp(const uint32_t nIp) { + return (GetIp() & GetNetmask()) == (nIp & GetNetmask()); } void Run() { - net_handle(); + net::net_handle(); +#if defined (CONFIG_ENET_ENABLE_PTP) + net::ptp_run(); +#endif #if defined (ENET_LINK_CHECK_USE_PIN_POLL) net::link_pin_poll(); #elif defined (ENET_LINK_CHECK_REG_POLL) @@ -252,6 +289,7 @@ class Network { net::link_handle_change(link_state); } #endif + net::dhcp_run(); } static Network *Get() { @@ -261,31 +299,25 @@ class Network { private: net::Link s_lastState { net::Link::STATE_DOWN }; bool m_IsDhcpCapable { true }; - bool m_IsDhcpUsed { false }; bool m_IsZeroconfCapable { true }; - bool m_IsZeroconfUsed { false }; - uint32_t m_nIfIndex { 1 }; - uint32_t m_nNtpServerIp { 0 }; - float m_fNtpUtcOffset { 0 }; - - struct IpInfo m_IpInfo; + char m_aIfName[IFNAMSIZ]; char m_aHostName[network::HOSTNAME_SIZE]; char m_aDomainName[network::DOMAINNAME_SIZE]; - uint8_t m_aNetMacaddr[network::MAC_SIZE]; - char m_aIfName[IFNAMSIZ]; - - NetworkStore *m_pNetworkStore { nullptr }; + uint32_t m_nNameservers[network::NAMESERVERS_COUNT]; struct QueuedConfig { static constexpr uint32_t NONE = 0; static constexpr uint32_t STATIC_IP = (1U << 0); - static constexpr uint32_t NET_MASK = (1U << 1); - static constexpr uint32_t DHCP = (1U << 2); - static constexpr uint32_t ZEROCONF = (1U << 3); + static constexpr uint32_t NETMASK = (1U << 1); + static constexpr uint32_t GW = (1U << 2); + static constexpr uint32_t DHCP = (1U << 3); + static constexpr uint32_t ZEROCONF = (1U << 4); uint32_t nMask = QueuedConfig::NONE; - uint32_t nLocalIp = 0; - uint32_t nNetmask = 0; + uint32_t nStaticIp; + uint32_t nNetmask; + uint32_t nGateway; + network::dhcp::Mode mode; }; QueuedConfig m_QueuedConfig; diff --git a/lib-network/include/emac/phy.h b/lib-network/include/emac/phy.h index ddae0832..63a8351c 100755 --- a/lib-network/include/emac/phy.h +++ b/lib-network/include/emac/phy.h @@ -2,7 +2,7 @@ * @file phy.h * */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -30,7 +30,7 @@ namespace net { enum class Link { - STATE_UP, STATE_DOWN + STATE_DOWN, STATE_UP }; enum class Duplex { @@ -59,6 +59,7 @@ struct PhyIdentifier { */ bool phy_get_id(const uint32_t nAddress, PhyIdentifier& phyIdentifier); +Link phy_get_link(const uint32_t nAddress); /** * diff --git a/lib-lightset/src/lightsetdmx.cpp b/lib-network/include/emac/phy/rtl8201f.h old mode 100644 new mode 100755 similarity index 73% rename from lib-lightset/src/lightsetdmx.cpp rename to lib-network/include/emac/phy/rtl8201f.h index f2e54ee9..eaef1a2e --- a/lib-lightset/src/lightsetdmx.cpp +++ b/lib-network/include/emac/phy/rtl8201f.h @@ -1,8 +1,8 @@ /** - * @file lightset.cpp + * @file rtl8201f.h * */ -/* Copyright (C) 2016-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,20 +23,15 @@ * THE SOFTWARE. */ -#include - -#include "lightset.h" +#ifndef EMAC_PHY_RTL8201F_H_ +#define EMAC_PHY_RTL8201F_H_ -using namespace lightset; - -uint16_t LightSet::GetDmxStartAddress() { - return dmx::START_ADDRESS_DEFAULT; -} +#include -uint16_t LightSet::GetDmxFootprint() { - return dmx::UNIVERSE_SIZE; -} +namespace net::phy { +void rtl8201f_set_rxtiming(const uint32_t nRxTiming); +void rtl8201f_set_txtiming(const uint32_t nTxTiming); +void rtl8201f_get_timings(uint32_t& nRxTiming, uint32_t& nTxTiming); +} // namespace net::phy -bool LightSet::SetDmxStartAddress(__attribute__((unused)) uint16_t nDmxStartAddress) { - return false; -} +#endif /* EMAC_PHY_RTL8201F_H_ */ diff --git a/lib-network/include/ip4_address.h b/lib-network/include/ip4_address.h new file mode 100755 index 00000000..1ba355bd --- /dev/null +++ b/lib-network/include/ip4_address.h @@ -0,0 +1,79 @@ +/* + * ip4_address.h + */ + +#ifndef IP4_ADDRESS_H_ +#define IP4_ADDRESS_H_ + +#include + +#define IP2STR(addr) static_cast(addr & 0xFF), static_cast((addr >> 8) & 0xFF), static_cast((addr >> 16) & 0xFF), static_cast((addr >> 24) & 0xFF) +#define IPSTR "%d.%d.%d.%d" + +#define MAC2STR(mac) static_cast(mac[0]),static_cast(mac[1]),static_cast(mac[2]),static_cast(mac[3]), static_cast(mac[4]), static_cast(mac[5]) +#define MACSTR "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x" + +namespace network { +static constexpr uint32_t STORE = 96; ///< Configuration store in bytes +static constexpr uint32_t MAC_SIZE = 6; +static constexpr uint32_t HOSTNAME_SIZE = 64; ///< Including a terminating null byte. +static constexpr uint32_t DOMAINNAME_SIZE = 64; ///< Including a terminating null byte. +static constexpr uint32_t NAMESERVERS_COUNT = 3; +static constexpr uint32_t IP4_ANY = 0x00000000; +static constexpr uint32_t IP4_BROADCAST = 0xffffffff; + +static constexpr uint32_t convert_to_uint(const uint8_t a, const uint8_t b, const uint8_t c, const uint8_t d) { + return static_cast(a) | + static_cast(b) << 8 | + static_cast(c) << 16 | + static_cast(d) << 24; +} + +inline bool is_netmask_valid(uint32_t nNetMask) { + if (nNetMask == 0) { + return false; + } + nNetMask = __builtin_bswap32(nNetMask); + return !(nNetMask & (~nNetMask >> 1)); + +} +/** + * The private address ranges are defined in RFC1918. + */ +inline bool is_private_ip(const uint32_t nIp) { + const uint8_t n = (nIp >> 8) & 0xFF; + + switch (nIp & 0xFF) { + case 10: + return true; + break; + case 172: + return (n >= 16) && (n < 32); + case 192: + return n == 168; + default: + break; + } + + return false; +} + +inline bool is_linklocal_ip(const uint32_t nIp) { + return (nIp & 0xFFFF) == 0xA9FE; +} + +inline bool is_multicast_ip(const uint32_t nIp) { + return (nIp & 0xF0) == 0xE0; +} + +inline uint32_t cidr_to_netmask(const uint8_t nCIDR) { + if (nCIDR != 0) { + const auto nNetmask = __builtin_bswap32(static_cast(~0x0) << (32 - nCIDR)); + return nNetmask; + } + + return 0; +} +} // namespace network + +#endif /* IP4_ADDRESS_H_ */ diff --git a/lib-network/src/net/net.h b/lib-network/include/net.h old mode 100644 new mode 100755 similarity index 51% rename from lib-network/src/net/net.h rename to lib-network/include/net.h index 47a27861..a60df004 --- a/lib-network/src/net/net.h +++ b/lib-network/include/net.h @@ -2,7 +2,7 @@ * @file net.h * */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,46 +28,63 @@ #include -struct ip_addr { - uint32_t addr; -}; +#include "netif.h" +#include "emac/phy.h" +#include "net/dhcp.h" +#include "net/protocol/dhcp.h" -typedef struct ip_addr ip_addr_t; +#include "debug.h" -struct IpInfo { - struct ip_addr ip; - struct ip_addr netmask; - struct ip_addr gw; - struct ip_addr broadcast_ip; - struct ip_addr secondary_ip; -}; +namespace network { +void mdns_shutdown(); +} // namespace network -#define IP_BROADCAST (0xFFFFFFFF) -#define HOST_NAME_MAX 64 /* including a terminating null byte. */ +namespace net { +void tcp_shutdown(); +void igmp_shutdown(); +} -void net_init(const uint8_t *const, struct IpInfo *, const char *, bool *, bool *); -void net_shutdown(); +namespace net { +void net_init(net::Link link, ip4_addr_t ipaddr, ip4_addr_t netmask, ip4_addr_t gw, bool &bUseDhcp); +void net_set_primary_ip(const ip4_addr_t ipaddr); +void net_set_secondary_ip(); void net_handle(); -void net_set_ip(struct IpInfo *); -void net_set_netmask(struct IpInfo *); -void net_set_gw(struct IpInfo *); -bool net_set_zeroconf(struct IpInfo *); - -bool net_set_dhcp(struct IpInfo *, const char *const, bool *); -void net_dhcp_release(); +inline void net_link_down() { + network::mdns_shutdown(); +#if defined (ENABLE_HTTPD) + tcp_shutdown(); +#endif + igmp_shutdown(); + dhcp_release_and_stop(); +} int udp_begin(uint16_t); int udp_end(uint16_t); -uint16_t udp_recv1(int, uint8_t *, uint16_t, uint32_t *, uint16_t *); -uint16_t udp_recv2(int, const uint8_t **, uint32_t *, uint16_t *); -int udp_send(int, const uint8_t *, uint16_t, uint32_t, uint16_t); +uint32_t udp_recv1(int, uint8_t *, uint32_t, uint32_t *, uint16_t *); +uint32_t udp_recv2(int, const uint8_t **, uint32_t *, uint16_t *); +void udp_send(int, const uint8_t *, uint32_t, uint32_t, uint16_t); +void udp_send_timestamp(int, const uint8_t *, uint32_t, uint32_t, uint16_t); void igmp_join(uint32_t); void igmp_leave(uint32_t); int tcp_begin(const uint16_t); uint16_t tcp_read(const int32_t, const uint8_t **, uint32_t &); -void tcp_write(const int32_t, const uint8_t *, uint16_t, const uint32_t); +void tcp_write(const int32_t, const uint8_t *, uint32_t, const uint32_t); + +/** + * Must be provided by the application + */ +void display_emac_config(); +void display_emac_start(); +void display_emac_status(const bool); +void display_emac_shutdown(); +void display_ip(); +void display_netmask(); +void display_gateway(); +void display_hostname(); +void display_dhcp_status(net::dhcp::State); +} // namespace het #endif /* NET_H_ */ diff --git a/lib-network/include/net/acd.h b/lib-network/include/net/acd.h new file mode 100755 index 00000000..f4a8d4fe --- /dev/null +++ b/lib-network/include/net/acd.h @@ -0,0 +1,71 @@ +/** + * @file acd.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +/* This code is inspired by: lwIP + * https://savannah.nongnu.org/projects/lwip/ + */ + +#ifndef NET_ACD_H_ +#define NET_ACD_H_ + +#include + +#include "netif.h" +#include "arp.h" +#include "net/protocol/acd.h" +#include "ip4_address.h" + +/** + * https://datatracker.ietf.org/doc/html/rfc5227.html + * IPv4 Address Conflict Detection + */ + +namespace net { +typedef void (*acd_conflict_callback_t)(acd::Callback callback); + +namespace acd { +struct Acd { + ip4_addr_t ipaddr; + State state; + uint8_t sent_num; + uint8_t lastconflict; + uint8_t num_conflicts; + acd_conflict_callback_t acd_conflict_callback; + uint16_t ttw; +}; +} // namespace acd + +void acd_add(struct acd::Acd *, acd_conflict_callback_t); +void acd_remove(struct acd::Acd *); + +void acd_start(struct acd::Acd *, const ip4_addr_t ipaddr); +void acd_stop(struct acd::Acd *); + +void acd_arp_reply(struct t_arp *); + +void acd_network_changed_link_down(); +void acd_netif_ip_addr_changed(const ip4_addr_t nOldIpAddress, const ip4_addr_t nNewIpAddress); +} // namespace net + +#endif /* NET_ACD_H_ */ diff --git a/lib-network/include/mdns.h b/lib-network/include/net/apps/mdns.h similarity index 77% rename from lib-network/include/mdns.h rename to lib-network/include/net/apps/mdns.h index 71578e20..4cf05e60 100755 --- a/lib-network/include/mdns.h +++ b/lib-network/include/net/apps/mdns.h @@ -2,7 +2,7 @@ * @file mdns.h * */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,12 +23,13 @@ * THE SOFTWARE. */ -#ifndef MDNS_H_ -#define MDNS_H_ +#ifndef NET_APPS_MDNS_H_ +#define NET_APPS_MDNS_H_ #include #include "network.h" +#include "net/protocol/dns.h" #include "../config/apps_config.h" @@ -37,16 +38,6 @@ enum class Services { CONFIG, TFTP, HTTP, RDMNET_LLRP, NTP, MIDI, OSC, DDP, PP, LAST_NOT_USED }; -struct Header { - uint16_t xid; - uint8_t nFlag1; - uint8_t nFlag2; - uint16_t nQueryCount; - uint16_t nAnswerCount; - uint16_t nAuthorityCount; - uint16_t nAdditionalCount; -} __attribute__((__packed__)); - struct ServiceRecord { char *pName; char *pTextContent; @@ -61,25 +52,28 @@ class MDNS { MDNS(); ~MDNS(); - bool AddServiceRecord(const char *pName, const mdns::Services service, const char *pTextContent = nullptr, const uint16_t nPort = 0); + bool ServiceRecordAdd(const char *pName, const mdns::Services service, const char *pTextContent = nullptr, const uint16_t nPort = 0); + bool ServiceRecordDelete(const mdns::Services service); + void Print(); + void SendAnnouncement(const uint32_t nTTL); void Run() { s_nBytesReceived = Network::Get()->RecvFrom(s_nHandle, const_cast(reinterpret_cast(&s_pReceiveBuffer)), &s_nRemoteIp, &s_nRemotePort); - if (__builtin_expect((s_nBytesReceived < sizeof(struct mdns::Header)), 1)) { + if (__builtin_expect((s_nBytesReceived < sizeof(struct net::dns::Header)), 1)) { return; } - const auto *const pHeader = reinterpret_cast(s_pReceiveBuffer); + const auto *const pHeader = reinterpret_cast(s_pReceiveBuffer); const auto nFlag1 = pHeader->nFlag1; if ((nFlag1 >> 3) & 0xF) { return; } - HandleQuestions(__builtin_bswap16(pHeader->nQueryCount)); + HandleQuestions(static_cast(__builtin_bswap16(pHeader->nQueryCount))); } static MDNS *Get() { @@ -91,16 +85,16 @@ class MDNS { void HandleQuestions(const uint32_t nQuestions); void SendAnswerLocalIpAddress(const uint16_t nTransActionID, const uint32_t nTTL); void SendMessage(mdns::ServiceRecord const& serviceRecord, const uint16_t nTransActionID, const uint32_t nTTL); - void SendTo(const uint16_t nLength); + void SendTo(const uint32_t nLength); private: static int32_t s_nHandle; static uint32_t s_nRemoteIp; - static uint16_t s_nRemotePort; - static uint16_t s_nBytesReceived; + static uint32_t s_nBytesReceived; static uint8_t *s_pReceiveBuffer; + static uint16_t s_nRemotePort; static MDNS *s_pThis; }; -#endif /* MDNS_H_ */ +#endif /* NET_APPS_MDNS_H_ */ diff --git a/lib-network/include/net/apps/ntpclient.h b/lib-network/include/net/apps/ntpclient.h new file mode 100755 index 00000000..1a1d526a --- /dev/null +++ b/lib-network/include/net/apps/ntpclient.h @@ -0,0 +1,147 @@ +/** + * @file ntpclient.h + * + */ +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef NET_APPS_NTPCLIENT_H_ +#define NET_APPS_NTPCLIENT_H_ + +#include +#include +#include + +#include "net/protocol/ntp.h" +#include "hardware.h" + +#include "debug.h" + +#if !defined(CONFIG_NTP_CLIENT_POLL_POWER) +# define CONFIG_NTP_CLIENT_POLL_POWER 10 +#endif + +namespace ntpclient { +static constexpr uint32_t TIMEOUT_MILLIS = 3000; +static constexpr uint8_t POLL_POWER = CONFIG_NTP_CLIENT_POLL_POWER; +static constexpr uint32_t POLL_SECONDS = (1U << POLL_POWER); + +void display_status(const ::ntp::Status status); +} // namespace ntpclient + +class NtpClient { +public: + NtpClient(); + + void Start(); + void Stop(); + void Print(); + + void SetServerIp(const uint32_t nServerIp) { + m_nServerIp = nServerIp; + } + + ntp::Status GetStatus() const { + return m_Status; + } + + void Run() { + if (m_Status == ntp::Status::STOPPED) { + return; + } + + if ((m_Status == ntp::Status::IDLE) || (m_Status == ntp::Status::FAILED)) { + if (__builtin_expect(((Hardware::Get()->Millis() - m_MillisLastPoll) > (1000 * ntpclient::POLL_SECONDS)), 0)) { + Send(); + m_MillisRequest = Hardware::Get()->Millis(); + m_Status = ntp::Status::WAITING; + ntpclient::display_status(ntp::Status::WAITING); + DEBUG_PUTS("ntp::Status::WAITING"); + } + + return; + } + + if (m_Status == ntp::Status::WAITING) { + uint8_t LiVnMode; + + if (!Receive(LiVnMode)) { + if (__builtin_expect(((Hardware::Get()->Millis() - m_MillisRequest) > ntpclient::TIMEOUT_MILLIS), 0)) { + m_Status = ntp::Status::FAILED; + ntpclient::display_status(ntp::Status::FAILED); + DEBUG_PUTS("ntp::Status::FAILED"); + } + + return; + } + + if (__builtin_expect(((LiVnMode & ntp::MODE_SERVER) == ntp::MODE_SERVER), 1)) { + m_MillisLastPoll = Hardware::Get()->Millis(); + + SetTimeOfDay(); +#ifndef NDEBUG + const auto nTime = time(nullptr); + const auto *pLocalTime = localtime(&nTime); + DEBUG_PRINTF("localtime: %.4d/%.2d/%.2d %.2d:%.2d:%.2d", pLocalTime->tm_year + 1900, pLocalTime->tm_mon + 1, pLocalTime->tm_mday, pLocalTime->tm_hour, pLocalTime->tm_min, pLocalTime->tm_sec); +#endif + } else { + DEBUG_PUTS("!>> Invalid reply < +#include namespace tftp { enum class Mode { @@ -70,11 +71,11 @@ class TFTPDaemon { int m_nIdx { -1 }; uint8_t *m_pBuffer { nullptr }; uint32_t m_nFromIp { 0 }; + uint32_t m_nLength { 0 }; + uint32_t m_nDataLength { 0 }; + uint32_t m_nPacketLength { 0 }; uint16_t m_nFromPort { 0 }; - size_t m_nLength { 0 }; uint16_t m_nBlockNumber { 0 }; - size_t m_nDataLength { 0 }; - uint16_t m_nPacketLength { 0 }; bool m_bIsLastBlock { false }; static TFTPDaemon* Get() { @@ -85,4 +86,4 @@ class TFTPDaemon { static TFTPDaemon *s_pThis; }; -#endif /* TFTPDAEMON_H_ */ +#endif /* NET_APPS_TFTPDAEMON_H_ */ diff --git a/lib-network/src/net/net_debug.h b/lib-network/include/net/arp.h old mode 100644 new mode 100755 similarity index 60% rename from lib-network/src/net/net_debug.h rename to lib-network/include/net/arp.h index 85095c4b..cddb33d9 --- a/lib-network/src/net/net_debug.h +++ b/lib-network/include/net/arp.h @@ -1,8 +1,8 @@ /** - * @file net_debug.h + * @file arp_private.h * */ -/* Copyright (C) 2018-2019 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,22 +23,29 @@ * THE SOFTWARE. */ -#ifndef NET_DEBUG_H_ -#define NET_DEBUG_H_ +#ifndef ARP_PRIVATE_H_ +#define ARP_PRIVATE_H_ -#include "debug.h" +#include "netif.h" +#include "net/protocol/ip4.h" +#include "net/protocol/arp.h" +#include "net/protocol/udp.h" -#ifndef IP2STR - #define IP2STR(addr) (addr & 0xFF), ((addr >> 8) & 0xFF), ((addr >> 16) & 0xFF), ((addr >> 24) & 0xFF) - #define IPSTR "%d.%d.%d.%d" -#endif -#ifndef MAC2STR - #define MAC2STR(mac) (mac[0]),(mac[1]),(mac[2]),(mac[3]), (mac[4]), (mac[5]) - #define MACSTR "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x" -#endif +namespace net { +namespace arp { +enum class Flags { + FLAG_INSERT, FLAG_UPDATE +}; +} // namespace arp -#if defined (H3) -# include "h3_timer.h" +void arp_init(); +void arp_handle(struct t_arp *); +void arp_send(struct t_udp *, const uint32_t, const uint32_t); +#if defined CONFIG_ENET_ENABLE_PTP +void arp_send_timestamp(struct t_udp *, const uint32_t, const uint32_t); #endif +void arp_acd_probe(const ip4_addr_t ipaddr); +void arp_acd_send_announcement(const ip4_addr_t ipaddr); +} // namespace net -#endif /* NET_DEBUG_H_ */ +#endif /* ARP_PRIVATE_H_ */ diff --git a/lib-network/include/net/autoip.h b/lib-network/include/net/autoip.h new file mode 100755 index 00000000..332fd7df --- /dev/null +++ b/lib-network/include/net/autoip.h @@ -0,0 +1,90 @@ +/** + * @file autoip.h + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +/* This code is inspired by the lwIP TCP/IP stack. + * https://savannah.nongnu.org/projects/lwip/ + */ +/** + * The autoip.cpp aims to be conform to RFC 3927. + * https://datatracker.ietf.org/doc/html/rfc3927 + * Dynamic Configuration of IPv4 Link-Local Addresses + */ + +#ifndef NET_AUTOIP_H_ +#define NET_AUTOIP_H_ + +#include + +#include "netif.h" +#include "net/acd.h" +#include "net/protocol/autoip.h" + +#include "debug.h" + +namespace net { +namespace autoip { +struct Autoip { + ip4_addr_t llipaddr; + State state; + uint8_t tried_llipaddr; + acd::Acd acd; +}; +} // namespace autoip + +void autoip_start(); +void autoip_stop(); + +inline bool autoip_supplied_address() { + auto *autoip = reinterpret_cast(globals::netif_default.autoip); + + return (autoip != nullptr) + && (globals::netif_default.ip.addr == autoip->llipaddr.addr) + && (autoip->state == autoip::State::AUTOIP_STATE_BOUND); +} + +inline void autoip_network_changed_link_up() { + DEBUG_ENTRY + + auto *autoip = reinterpret_cast(globals::netif_default.autoip); + + if ((autoip != nullptr) && (autoip->state != autoip::State::AUTOIP_STATE_OFF)) { + acd_start(&autoip->acd, autoip->llipaddr); + } + + DEBUG_EXIT +} + +inline void autoip_network_changed_link_down() { + DEBUG_EXIT + + auto *autoip = reinterpret_cast(globals::netif_default.autoip); + + if ((autoip != nullptr) && (autoip->state != autoip::State::AUTOIP_STATE_OFF)) { + autoip_stop(); + } + + DEBUG_EXIT +} +} // namespace net + +#endif /* NET_AUTOIP_H_ */ diff --git a/lib-network/include/net/dhcp.h b/lib-network/include/net/dhcp.h new file mode 100755 index 00000000..1c6f1670 --- /dev/null +++ b/lib-network/include/net/dhcp.h @@ -0,0 +1,139 @@ +/** + * @file dhcp.h + * + */ +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef NET_DHCP_H_ +#define NET_DHCP_H_ + +#include +#include + +#include + +#include "netif.h" +#include "acd.h" +#include "ip4_address.h" +#include "net/protocol/dhcp.h" +#include "net/protocol/iana.h" + +#include "debug.h" + +namespace net { +namespace dhcp { +static constexpr uint32_t DHCP_COARSE_TIMER_SECS = 60; +/** period (in milliseconds) of the application calling dhcp_coarse_tmr() */ +static constexpr uint32_t DHCP_COARSE_TIMER_MSECS = (DHCP_COARSE_TIMER_SECS * 1000UL); +/** period (in milliseconds) of the application calling dhcp_fine_tmr() */ +static constexpr uint32_t DHCP_FINE_TIMER_MSECS = 500; + +#define DHCP_FLAG_SUBNET_MASK_GIVEN 0x01 +#define DHCP_AUTOIP_COOP_TRIES 9 + +enum class AutoipCoopState { + DHCP_AUTOIP_COOP_STATE_OFF = 0, + DHCP_AUTOIP_COOP_STATE_ON = 1 +}; + +typedef uint16_t dhcp_timeout_t; + +struct Dhcp { + int32_t nHandle; + uint32_t xid; + State state; + uint8_t tries; + uint8_t flags; + + dhcp_timeout_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */ + dhcp_timeout_t t1_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */ + dhcp_timeout_t t2_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */ + dhcp_timeout_t t1_renew_time; /* #ticks with period DHCP_COARSE_TIMER_SECS until next renew try */ + dhcp_timeout_t t2_rebind_time; /* #ticks with period DHCP_COARSE_TIMER_SECS until next rebind try */ + dhcp_timeout_t lease_used; /* #ticks with period DHCP_COARSE_TIMER_SECS since last received DHCP ack */ + dhcp_timeout_t t0_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for lease time */ + + ip4_addr_t server_ip_addr; + + struct Offered { + ip4_addr_t offered_ip_addr; + ip4_addr_t offered_sn_mask; + ip4_addr_t offered_gw_addr; + + uint32_t offered_t0_lease; /* lease period (in seconds) */ + uint32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */ + uint32_t offered_t2_rebind; /* recommended rebind time (usually 87.5 of lease period) */ + }; + + Offered offered; + + acd::Acd acd; +}; +} // namespace dhcp + +bool dhcp_start(); +bool dhcp_renew(); +bool dhcp_release(); +void dhcp_stop(); +void dhcp_release_and_stop(); +void dhcp_inform(); +void dhcp_network_changed_link_up(); + +uint32_t udp_recv2(int, const uint8_t **, uint32_t *, uint16_t *); +void dhcp_process(const dhcp::Message *const, const uint32_t nSize); + +inline void dhcp_run() { + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + if (dhcp == nullptr) { + return; + } + + uint8_t *pResponse; + uint32_t nFromIp; + uint16_t nFromPort; + + const auto nSize = udp_recv2(dhcp->nHandle, const_cast(&pResponse), &nFromIp, &nFromPort); + + if (__builtin_expect((nSize > 0), 0)) { + if (nFromPort == net::iana::IANA_PORT_DHCP_SERVER) { + const auto *const p = reinterpret_cast(pResponse); + + if (p->xid != dhcp->xid) { + DEBUG_PRINTF("pDhcpMessage->xid=%u, dhcp->xid=%u", p->xid, dhcp->xid); + return; + } + + dhcp_process(p, nSize); + } + } +} + +inline bool dhcp_supplied_address() { + const auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + if ((dhcp != nullptr)) { + return (dhcp->state == dhcp::State::STATE_BOUND) || (dhcp->state == dhcp::State::STATE_RENEWING) || (dhcp->state == dhcp::State::STATE_REBINDING); + } + return false; +} +} // namespace net + +#endif /* NET_DHCP_H_ */ diff --git a/lib-network/include/net/igmp.h b/lib-network/include/net/igmp.h new file mode 100755 index 00000000..252cce6c --- /dev/null +++ b/lib-network/include/net/igmp.h @@ -0,0 +1,13 @@ +/* + * igmp.h + */ + +#ifndef NET_IGMP_H_ +#define NET_IGMP_H_ + +namespace net { +//TODO implement +void igmp_report_groups(); +} // namespace net + +#endif /* NET_IGMP_H_ */ diff --git a/lib-network/include/net/protocol/acd.h b/lib-network/include/net/protocol/acd.h new file mode 100644 index 00000000..035b3e5d --- /dev/null +++ b/lib-network/include/net/protocol/acd.h @@ -0,0 +1,64 @@ +/** + * @file acd.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef NET_PROTOCOL_ACD_H_ +#define NET_PROTOCOL_ACD_H_ + +#include + +namespace net::acd { +/** + * RFC 5227 and RFC 3927 Constants + */ +#define PROBE_WAIT 1 ///< second (initial random delay) +#define PROBE_MIN 1 ///< second (minimum delay till repeated probe) +#define PROBE_MAX 2 ///< seconds (maximum delay till repeated probe) +#define PROBE_NUM 3 ///< (number of probe packets) +#define ANNOUNCE_NUM 2 ///< (number of announcement packets) +#define ANNOUNCE_INTERVAL 2 ///< seconds (time between announcement packets) +#define ANNOUNCE_WAIT 2 ///< seconds (delay before announcing) +#define MAX_CONFLICTS 10 ///< (max conflicts before rate limiting) +#define RATE_LIMIT_INTERVAL 60 ///< seconds (delay between successive attempts) +#define DEFEND_INTERVAL 10 ///< seconds (minimum interval between defensive ARPs) + +enum class State: uint8_t { + ACD_STATE_OFF, + ACD_STATE_PROBE_WAIT, + ACD_STATE_PROBING, + ACD_STATE_ANNOUNCE_WAIT, + ACD_STATE_ANNOUNCING, + ACD_STATE_ONGOING, + ACD_STATE_PASSIVE_ONGOING, + ACD_STATE_RATE_LIMIT +}; + +enum class Callback { + ACD_IP_OK, ///< IP address is good, no conflicts found in checking state + ACD_RESTART_CLIENT, ///< Conflict found -> the client should try again + ACD_DECLINE ///< Decline the received IP address (rate limiting) +}; +} // namespace acd + +#endif /* NET_PROTOCOL_ACD_H_ */ diff --git a/lib-network/src/net/dhcp_internal.h b/lib-network/include/net/protocol/arp.h old mode 100644 new mode 100755 similarity index 50% rename from lib-network/src/net/dhcp_internal.h rename to lib-network/include/net/protocol/arp.h index 1ce0e730..3d6b6b1c --- a/lib-network/src/net/dhcp_internal.h +++ b/lib-network/include/net/protocol/arp.h @@ -1,8 +1,8 @@ /** - * @file dhcp_internal.h + * @file arp.h * */ -/* Copyright (C) 2018-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,47 +23,54 @@ * THE SOFTWARE. */ -#ifndef DHCP_INTERNAL_H_ -#define DHCP_INTERNAL_H_ +#ifndef NET_PROTOCOL_ARP_H_ +#define NET_PROTOCOL_ARP_H_ -enum DHCP_PORT { - DHCP_PORT_SERVER = 67, - DHCP_PORT_CLIENT = 68 +#include "ip4_address.h" +#include "net/protocol/ethernet.h" +#include "net/protocol/ieee.h" + +#if !defined (PACKED) +# define PACKED __attribute__((packed)) +#endif + +enum ARP_HARDWARE_TYPE { + ARP_HWTYPE_ETHERNET = 1 }; -enum DHCP_OP { - DHCP_OP_BOOTREQUEST = 1, - DHCP_OP_BOOTREPLY = 2 +enum ARP_PROTOCOL_TYPE { + ARP_PRTYPE_IPv4 = ETHER_TYPE_IPv4 }; -enum DHCP_HTYPE { - DHCP_HTYPE_10MB = 1, - DHCP_HTYPE_100MB = 2 +enum ARP_HARDWARE { + ARP_HARDWARE_SIZE = ETH_ADDR_LEN }; -enum DCHP_TYPE { - DCHP_TYPE_DISCOVER = 1, - DCHP_TYPE_OFFER = 2, - DCHP_TYPE_REQUEST = 3, - DCHP_TYPE_DECLINE = 4, - DCHP_TYPE_ACK = 5, - DCHP_TYPE_NAK = 6, - DCHP_TYPE_RELEASE = 7, - DCHP_TYPE_INFORM = 8 +enum ARP_PROTOCOL { + ARP_PROTOCOL_SIZE = IPv4_ADDR_LEN }; -enum DHCP_STATE { - DHCP_STATE_DHCP_INIT = 0, - DHCP_STATE_DHCP_DISCOVER = 1, - DHCP_STATE_DHCP_REQUEST = 2, - DHCP_STATE_DHCP_LEASED = 3, - DHCP_STATE_DHCP_REREQUEST = 4, - DHCP_STATE_DHCP_RELEASE = 5, - DHCP_STATE_DHCP_STOP = 6 +enum ARP_OPCODE { + ARP_OPCODE_RQST = 1, + ARP_OPCODE_REPLY = 2 }; -#define DHCP_OPT_SIZE 312 +struct arp_packet { + uint16_t hardware_type; /* 2 */ + uint16_t protocol_type; /* 4 */ + uint8_t hardware_size; /* 5 */ + uint8_t protocol_size; /* 6 */ + uint16_t opcode; /* 8 */ + uint8_t sender_mac[ETH_ADDR_LEN];/*14 */ + uint8_t sender_ip[IPv4_ADDR_LEN];/* 18 */ + uint8_t target_mac[ETH_ADDR_LEN];/*24 */ + uint8_t target_ip[IPv4_ADDR_LEN];/* 28 */ + uint8_t padding[18]; /* 46 */ /* +14 = 60 */ +} PACKED; -#define MAGIC_COOKIE 0x63825363 ///< You should not modify it number. +struct t_arp { + struct ether_header ether; + struct arp_packet arp; +} PACKED; -#endif /* DHCP_INTERNAL_H_ */ +#endif /* NET_PROTOCOL_ARP_H_ */ diff --git a/lib-network/include/net/protocol/autoip.h b/lib-network/include/net/protocol/autoip.h new file mode 100644 index 00000000..dc3d900a --- /dev/null +++ b/lib-network/include/net/protocol/autoip.h @@ -0,0 +1,43 @@ +/** + * @file autoip.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef NET_PROTOCOL_AUTOIP_H_ +#define NET_PROTOCOL_AUTOIP_H_ + +#include "ip4_address.h" + +namespace net::autoip { +static constexpr auto AUTOIP_NET = network::convert_to_uint(169,254,0,0); +static constexpr auto AUTOIP_RANGE_START = network::convert_to_uint(169,254,1,0); +static constexpr auto AUTOIP_RANGE_END = network::convert_to_uint(169,254,254,255); + +enum class State { + AUTOIP_STATE_OFF, + AUTOIP_STATE_CHECKING, + AUTOIP_STATE_BOUND +}; +} // namespace autoip + +#endif /* NET_PROTOCOL_AUTOIP_H_ */ diff --git a/lib-network/include/net/protocol/dhcp.h b/lib-network/include/net/protocol/dhcp.h new file mode 100644 index 00000000..94064171 --- /dev/null +++ b/lib-network/include/net/protocol/dhcp.h @@ -0,0 +1,120 @@ +/** + * @file dhcp.h + * + */ +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef NET_PROTOCOL_DHCP_H +#define NET_PROTOCOL_DHCP_H + +#include + +#include "ip4.h" + +namespace net::dhcp { +static constexpr uint32_t OPT_SIZE = 312; +static constexpr uint32_t MAGIC_COOKIE = 0x63825363; ///< You should not modify it number. + +struct OpCode { + static constexpr uint8_t BOOTREQUEST = 1; + static constexpr uint8_t BOOTREPLY = 2; +}; + +struct HardwareType { + static constexpr uint8_t HTYPE_10MB = 1; + static constexpr uint8_t HTYPE_100MB = 2; +}; + +struct Type { + static constexpr uint8_t DISCOVER = 1; + static constexpr uint8_t OFFER = 2; + static constexpr uint8_t REQUEST = 3; + static constexpr uint8_t DECLINE = 4; + static constexpr uint8_t ACK = 5; + static constexpr uint8_t NAK = 6; + static constexpr uint8_t RELEASE = 7; + static constexpr uint8_t INFORM = 8; +}; + +struct Options { + /* BootP options */ + static constexpr uint8_t OPTION_PAD_OPTION = 0; + static constexpr uint8_t OPTION_SUBNET_MASK = 1; ///< RFC 2132 3.3 + static constexpr uint8_t OPTION_ROUTER = 3; + static constexpr uint8_t OPTION_DNS_SERVER = 6; + static constexpr uint8_t OPTION_HOSTNAME = 12; + static constexpr uint8_t OPTION_DOMAIN_NAME = 15; + static constexpr uint8_t OPTION_IP_TTL = 23; + static constexpr uint8_t OPTION_MTU = 26; + static constexpr uint8_t OPTION_BROADCAST = 28; + static constexpr uint8_t OPTION_TCP_TTL = 37; + static constexpr uint8_t OPTION_NTP = 42; + static constexpr uint8_t OPTION_END = 255; + /* DHCP options */ + static constexpr uint8_t OPTION_REQUESTED_IP = 50; ///< RFC 2132 9.1, requested IP address + static constexpr uint8_t OPTION_LEASE_TIME = 51; ///< RFC 2132 9.2, time in seconds, in 4 bytes + static constexpr uint8_t OPTION_OVERLOAD = 52; ///< RFC2132 9.3, use file and/or sname field for options + static constexpr uint8_t OPTION_MESSAGE_TYPE = 53; ///< RFC 2132 9.6, important for DHCP + static constexpr uint8_t OPTION_SERVER_IDENTIFIER = 54; ///< RFC 2132 9.7, server IP address + static constexpr uint8_t OPTION_PARAM_REQUEST = 55; ///< RFC 2132 9.8, requested option types + static constexpr uint8_t OPTION_MAX_MSG_SIZE = 57; ///< RFC 2132 9.10, message size accepted >= 576 + static constexpr uint8_t OPTION_DHCP_T1_VALUE = 58; ///< T1 renewal time + static constexpr uint8_t OPTION_DHCP_T2_VALUE = 59; ///< T2 renewal time + static constexpr uint8_t OPTION_CLIENT_IDENTIFIER = 61; +}; + +enum class State: uint8_t { + STATE_OFF = 0, + STATE_REQUESTING = 1, + STATE_INIT = 2, + STATE_REBOOTING = 3, + STATE_REBINDING = 4, + STATE_RENEWING = 5, + STATE_SELECTING = 6, + STATE_INFORMING = 7, + STATE_CHECKING = 8, + STATE_PERMANENT = 9, + STATE_BOUND = 10, + STATE_RELEASING = 11, + STATE_BACKING_OFF = 12 +}; + +struct Message { + uint8_t op; + uint8_t htype; + uint8_t hlen; + uint8_t hops; + uint32_t xid; + uint16_t secs; + uint16_t flags; + uint8_t ciaddr[IPv4_ADDR_LEN]; + uint8_t yiaddr[IPv4_ADDR_LEN]; + uint8_t siaddr[IPv4_ADDR_LEN]; + uint8_t giaddr[IPv4_ADDR_LEN]; + uint8_t chaddr[16]; + uint8_t sname[64]; + uint8_t file[128]; + uint8_t options[dhcp::OPT_SIZE]; +} __attribute__((packed)); +} // namespace net::dhcp + +#endif /* NET_PROTOCOL_DHCP_H */ diff --git a/lib-network/include/net/protocol/dns.h b/lib-network/include/net/protocol/dns.h new file mode 100644 index 00000000..e486563f --- /dev/null +++ b/lib-network/include/net/protocol/dns.h @@ -0,0 +1,93 @@ +/** + * @file dns.h + * + */ +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef NET_PROTOCOL_DNS_H_ +#define NET_PROTOCOL_DNS_H_ + +#include + +#include "ip4_address.h" + +namespace net { namespace dns { +static constexpr uint32_t SIZEOF_DNS_HDR = 12; + +enum class Flag1 : uint8_t { + FLAG1_RESPONSE = 0x80, ///< query (0), or a response (1). + FLAG1_OPCODE_STATUS = 0x10, ///< a server status request (STATUS) + FLAG1_OPCODE_IQUERY = 0x08, ///< an inverse query (IQUERY) + FLAG1_OPCODE_STANDARD = 0x00, ///< (RFC 6762, section 18.3) + FLAG1_AUTHORATIVE = 0x04, ///< Authoritative Answer + FLAG1_TRUNC = 0x02, ///< TrunCation + FLAG1_RD = 0x01 ///< If RD is set, it directs the name server to pursue the query recursively. +}; + +static constexpr uint8_t operator| (Flag1 a, Flag1 b) { + return static_cast((static_cast(a) | static_cast(b))); +} + +///< NS field TYPE used for "Resource Records" +enum class RRType : uint16_t { + RRTYPE_A = 1, ///< a host address + RRTYPE_PTR = 12, ///< a domain name pointer + RRTYPE_TXT = 16, ///< text strings + RRTYPE_SRV = 33, ///< service location + RRTYPE_ALL = 255 ///< any type +}; + +///< DNS field CLASS used for "Resource Records" +enum class RRClass : uint16_t { + RRCLASS_INTERNET = 1, ///< Internet + RRCLASS_ANY = 255, ///< Any class + RRCLASS_FLUSH = 0x8000 ///< Flush bit +}; + +static constexpr uint16_t operator| (RRClass a, RRClass b) { + return static_cast((static_cast(a) | static_cast(b))); +} + +struct Header { + uint16_t xid; + uint8_t nFlag1; + uint8_t nFlag2; + uint16_t nQueryCount; + uint16_t nAnswerCount; + uint16_t nAuthorityCount; + uint16_t nAdditionalCount; +} __attribute__((__packed__)); + +inline uint8_t dns_header_get_opcode(const Header *const header) { + return ((header->nFlag1) >> 3) & 0xF; +} + +/* + * mDNS + */ + +static constexpr uint32_t MULTICAST_MESSAGE_SIZE = 512; ///< The 1987 DNS specification [RFC1035] restricts DNS messages carried by UDP to no more than 512 bytes +static constexpr uint32_t MULTICAST_ADDRESS = network::convert_to_uint(224, 0, 0, 251); + +} } // namespace net::dns + +#endif /* NET_PROTOCOL_DNS_H_ */ diff --git a/lib-network/src/emac/gd32/debug_print_bits.c b/lib-network/include/net/protocol/ethernet.h old mode 100644 new mode 100755 similarity index 67% rename from lib-network/src/emac/gd32/debug_print_bits.c rename to lib-network/include/net/protocol/ethernet.h index 48747959..323c2339 --- a/lib-network/src/emac/gd32/debug_print_bits.c +++ b/lib-network/include/net/protocol/ethernet.h @@ -1,8 +1,8 @@ /** - * @file debug_print_bits.c + * @file ethernet.h * */ -/* Copyright (C) 2018-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,26 +23,33 @@ * THE SOFTWARE. */ -#include +#ifndef NET_PROTOCOL_ETHERNET_H_ +#define NET_PROTOCOL_ETHERNET_H_ + #include -#if defined (H3) -extern int uart0_printf(const char* fmt, ...); -# define printf uart0_printf +#if !defined (PACKED) +# define PACKED __attribute__((packed)) #endif -void debug_print_bits(uint32_t u) { - uint32_t i; +enum MTU { + MTU_SIZE = 1500 +}; + +enum ETH_ADDR { + ETH_ADDR_LEN = 6 +}; + +struct ether_header { + uint8_t dst[ETH_ADDR_LEN]; /* 6 */ + uint8_t src[ETH_ADDR_LEN]; /* 12 */ + uint16_t type; /* 14 */ +} PACKED; + +namespace net { +static constexpr uint32_t ETH_HWADDR_LEN = 6; - uint32_t b = 1U << 31; - for (i = 0; i < 32; i++) { - if ((b & u) == b) { - uint32_t bit_number = 31 - i; - printf("%-2d ", bit_number); - } - b = b >> 1; - } +} // namespace net - printf("\n"); -} +#endif /* NET_PROTOCOL_ETHERNET_H_ */ diff --git a/lib-network/include/net/protocol/iana.h b/lib-network/include/net/protocol/iana.h new file mode 100644 index 00000000..bc5c6990 --- /dev/null +++ b/lib-network/include/net/protocol/iana.h @@ -0,0 +1,40 @@ +/** + * @file iana.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef NET_PROTOCOL_IANA_H_ +#define NET_PROTOCOL_IANA_H_ + +#include + +namespace net::iana { +static constexpr uint16_t IANA_PORT_DHCP_SERVER = 67; +static constexpr uint16_t IANA_PORT_DHCP_CLIENT = 68; +static constexpr uint16_t IANA_PORT_TFTP = 69; +static constexpr uint16_t IANA_PORT_HTTP = 80; +static constexpr uint16_t IANA_PORT_NTP_SERVER = 123; +static constexpr uint16_t IANA_PORT_MDNS = 5353; +} // namespace net::iana + +#endif /* NET_PROTOCOL_IANA_H_ */ diff --git a/lib-network/include/net/protocol/icmp.h b/lib-network/include/net/protocol/icmp.h new file mode 100755 index 00000000..a9cb2a83 --- /dev/null +++ b/lib-network/include/net/protocol/icmp.h @@ -0,0 +1,65 @@ +/** + * @file icmp.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef NET_PROTOCOL_ICMP_H_ +#define NET_PROTOCOL_ICMP_H_ + +#include + +#include "net/protocol/ethernet.h" +#include "net/protocol/ip4.h" + +#if !defined (PACKED) +# define PACKED __attribute__((packed)) +#endif + +enum ICMP_TYPE { + ICMP_TYPE_ECHO_REPLY = 0, + ICMP_TYPE_ECHO = 8 +}; + +enum ICMP_CODE { + ICMP_CODE_ECHO = 0 +}; + +struct t_icmp_packet { + uint8_t type; /* 1 */ + uint8_t code; /* 2 */ + uint16_t checksum; /* 4 */ + uint8_t parameter[4]; /* 8 */ +#define ICMP_HEADER_SIZE 8 +#define ICMP_PAYLOAD_SIZE (MTU_SIZE - ICMP_HEADER_SIZE - sizeof(struct ip4_header)) + uint8_t payload[ICMP_PAYLOAD_SIZE]; +} PACKED; + +struct t_icmp { + struct ether_header ether; + struct ip4_header ip4; + struct t_icmp_packet icmp; +} PACKED; + +#define IPv4_ICMP_HEADERS_SIZE (sizeof(struct t_icmp) - sizeof(struct ether_header)) + +#endif /* NET_PROTOCOL_ICMP_H_ */ diff --git a/gd32_rdm_responder/lib/dmxstartaddressupdate.cpp b/lib-network/include/net/protocol/ieee.h old mode 100644 new mode 100755 similarity index 78% rename from gd32_rdm_responder/lib/dmxstartaddressupdate.cpp rename to lib-network/include/net/protocol/ieee.h index d5c8130d..c65ef053 --- a/gd32_rdm_responder/lib/dmxstartaddressupdate.cpp +++ b/lib-network/include/net/protocol/ieee.h @@ -1,8 +1,8 @@ /** - * @file dmxstartaddressupdate.cpp + * @file ieee.h * */ -/* Copyright (C) 2021 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,14 +23,15 @@ * THE SOFTWARE. */ -#include - -#include "rdmresponder.h" +#ifndef NET_PROTOCOL_IEEE_H_ +#define NET_PROTOCOL_IEEE_H_ -#include "displayudf.h" +#include -#include "debug.h" +enum ETHER_TYPE { + ETHER_TYPE_IPv4 = 0x0800, + ETHER_TYPE_ARP = 0x0806, + ETHER_TYPE_PTP = 0x88F7 /* IEEE1588v2 (PTPv2) over Ethernet */ +}; -void RDMResponder::DmxStartAddressUpdate(__attribute__((unused)) uint16_t nDmxStartAddress) { - DisplayUdf::Get()->Show(); -} +#endif /* NET_PROTOCOL_IEEE_H_ */ diff --git a/lib-artnet/include/artnetrdm.h b/lib-network/include/net/protocol/igmp.h old mode 100644 new mode 100755 similarity index 55% rename from lib-artnet/include/artnetrdm.h rename to lib-network/include/net/protocol/igmp.h index a36a5b60..d49a7d9f --- a/lib-artnet/include/artnetrdm.h +++ b/lib-network/include/net/protocol/igmp.h @@ -1,11 +1,8 @@ /** - * @file artnetrdm.h + * @file igmp.h * */ -/** - * Art-Net Designed by and Copyright Artistic Licence Holdings Ltd. - */ -/* Copyright (C) 2017-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,29 +23,44 @@ * THE SOFTWARE. */ -#ifndef ARTNETRDM_H_ -#define ARTNETRDM_H_ +#ifndef NET_PROTOCOL_IGMP_H_ +#define NET_PROTOCOL_IGMP_H_ #include -namespace artnet { -void rdm_send(uint32_t nPortIndex, const uint8_t *pRdmData); -} // namespace artnet +#include "net/protocol/ethernet.h" +#include "net/protocol/ip4.h" -class ArtNetRdm { -public: - virtual ~ArtNetRdm() {} +#if !defined (PACKED) +# define PACKED __attribute__((packed)) +#endif - virtual void Full(uint32_t nPortIndex)=0; - virtual uint32_t GetUidCount(uint32_t nPortIndex)=0; - virtual void TodCopy(uint32_t nPortIndex, uint8_t *)=0; +enum IGMP_TYPE { + IGMP_TYPE_QUERY = 0x11, + IGMP_TYPE_REPORT = 0x16, + IGMP_TYPE_LEAVE = 0x17 +}; - virtual void TodReset(uint32_t nPortIndex)=0; - virtual bool TodAddUid(uint32_t nPortIndex, const uint8_t *pUid)=0; +struct t_igmp_packet { + uint8_t type; + uint8_t max_resp_time; + uint16_t checksum; + uint8_t group_address[IPv4_ADDR_LEN]; +} PACKED; - virtual const uint8_t *Handler(uint32_t nPortIndex, const uint8_t *)=0; +struct t_igmp { + struct ether_header ether; + struct ip4_header ip4; + union { + struct { + uint32_t ip4_options; + struct t_igmp_packet igmp; + } report; + struct t_igmp_packet igmp; + } igmp; +} PACKED; - virtual bool RdmReceive(uint32_t nPortIndex, uint8_t *pRdmData)=0; -}; +#define IPv4_IGMP_REPORT_HEADERS_SIZE (sizeof(struct t_igmp) - sizeof(struct ether_header)) +#define IGMP_REPORT_PACKET_SIZE (sizeof(struct t_igmp)) -#endif /* ARTNETRDM_H_ */ +#endif /* NET_PROTOCOL_IGMP_H_ */ diff --git a/lib-network/include/net/protocol/ip4.h b/lib-network/include/net/protocol/ip4.h new file mode 100755 index 00000000..346b9974 --- /dev/null +++ b/lib-network/include/net/protocol/ip4.h @@ -0,0 +1,71 @@ +/** + * @file ip4.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef NET_PROTOCOL_IP4_H_ +#define NET_PROTOCOL_IP4_H_ + +#include + +#include "net/protocol/ethernet.h" + +#if !defined (PACKED) +# define PACKED __attribute__((packed)) +#endif + +enum IPv4_ADDR { + IPv4_ADDR_LEN = 4 +}; + +enum IPv4_PROTO { + IPv4_PROTO_ICMP = 1, + IPv4_PROTO_IGMP = 2, + IPv4_PROTO_TCP = 6, + IPv4_PROTO_UDP = 17 +}; + +enum IPv4_FLAG { + IPv4_FLAG_LF = 0x0000, + IPv4_FLAG_MF = 0x2000, + IPv4_FLAG_DF = 0x4000 +}; + +struct ip4_header { + uint8_t ver_ihl; /* 1 */ + uint8_t tos; /* 2 */ + uint16_t len; /* 4 */ + uint16_t id; /* 6 */ + uint16_t flags_froff; /* 8 */ + uint8_t ttl; /* 9 */ + uint8_t proto; /* 10 */ + uint16_t chksum; /* 12 */ + uint8_t src[IPv4_ADDR_LEN]; /* 16 */ + uint8_t dst[IPv4_ADDR_LEN]; /* 20 */ +} PACKED; + +struct t_ip4 { + struct ether_header ether; + struct ip4_header ip4; +} PACKED; + +#endif /* NET_PROTOCOL_IP4_H_ */ diff --git a/lib-network/include/ntp.h b/lib-network/include/net/protocol/ntp.h old mode 100644 new mode 100755 similarity index 50% rename from lib-network/include/ntp.h rename to lib-network/include/net/protocol/ntp.h index fdf6b0d4..2999c4ce --- a/lib-network/include/ntp.h +++ b/lib-network/include/net/protocol/ntp.h @@ -2,7 +2,7 @@ * @file ntp.h * */ -/* Copyright (C) 2019-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,34 +23,23 @@ * THE SOFTWARE. */ -#ifndef NTP_H_ -#define NTP_H_ +#ifndef NET_PROTOCOL_NTP_H_ +#define NET_PROTOCOL_NTP_H_ -static constexpr auto LOCAL_TIME_YEAR_OFFSET = 1900; -static constexpr auto NTP_TIMESTAMP_DELTA = 2208988800u; +#include -enum TNtpUdpPort { - NTP_UDP_PORT = 123 -}; - -enum TNtpVersion { - NTP_VERSION = (4 << 3) -}; +namespace ntp { +static constexpr uint32_t JAN_1970 = 0x83aa7e80; // 2208988800 1970 - 1900 in seconds +static constexpr uint32_t LOCAL_TIME_YEAR_OFFSET = 1900; +static constexpr uint32_t MICROSECONDS_IN_SECOND = 1000000; +static constexpr uint16_t UDP_PORT = 123; +static constexpr uint8_t VERSION = (4U << 3); +static constexpr uint8_t MODE_CLIENT = (3U << 0); +static constexpr uint8_t MODE_SERVER = (4U << 0); +static constexpr uint8_t STRATUM = 2; +static constexpr uint8_t MINPOLL = 4; -enum TNtpMode { - NTP_MODE_CLIENT = (3 << 0), - NTP_MODE_SERVER = (4 << 0) -}; - -enum TNtpStratum { - NTP_STRATUM = 2 -}; - -enum TNtpPoll { - NTP_MINPOLL = 4 -}; - -struct TNtpPacket { +struct Packet { uint8_t LiVnMode; uint8_t Stratum; uint8_t Poll; @@ -68,4 +57,45 @@ struct TNtpPacket { uint32_t TransmitTimestamp_f; }__attribute__((packed)); -#endif /* NTP_H_ */ +struct TimeStamp { + uint32_t nSeconds; + uint32_t nFraction; +}; + +struct time_t { + int32_t tv_sec; + int32_t tv_usec; +}; + +enum class Status { + STOPPED, IDLE, WAITING, FAILED +}; + +static constexpr char STATUS[4][8] = { "Stopped", "Idle", "Waiting", "Failed" }; + +enum class Modes { + BASIC, INTERLEAVED, UNKNOWN +}; + +inline void normalize_time(ntp::time_t *r) { + r->tv_sec += r->tv_usec / 1000000; + r->tv_usec -= r->tv_usec / 1000000 * 1000000; + + if (r->tv_sec > 0 && r->tv_usec < 0) { + r->tv_sec -= 1; + r->tv_usec += 1000000; + } else if (r->tv_sec < 0 && r->tv_usec > 0) { + r->tv_sec += 1; + r->tv_usec -= 1000000; + } +} + +inline void sub_time(struct ntp::time_t *r, const struct ntp::time_t *x, const struct ntp::time_t *y) { + r->tv_sec = x->tv_sec - y->tv_sec; + r->tv_usec = x->tv_usec - y->tv_usec; + + normalize_time(r); +} +} // namespace ntp + +#endif /* NET_PROTOCOL_NTP_H_ */ diff --git a/lib-network/include/net/protocol/tcp.h b/lib-network/include/net/protocol/tcp.h new file mode 100755 index 00000000..b20047f2 --- /dev/null +++ b/lib-network/include/net/protocol/tcp.h @@ -0,0 +1,62 @@ +/** + * @file tcp.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef NET_PROTOCOL_TCP_H_ +#define NET_PROTOCOL_TCP_H_ + +#include + +#include "net/protocol/ethernet.h" +#include "net/protocol/ip4.h" + +#if !defined (PACKED) +# define PACKED __attribute__((packed)) +#endif + +struct t_tcp_packet { + uint16_t srcpt; /* 2 */ + uint16_t dstpt; /* 4 */ + uint32_t seqnum; /* 8 */ + uint32_t acknum; /* 12 */ + uint8_t offset; /* 13 */ + uint8_t control; /* 14 */ + uint16_t window; /* 16 */ + uint16_t checksum; /* 18 */ + uint16_t urgent; /* 20 */ +#define TCP_HEADER_SIZE 20 +#define TCP_OPTIONS_SIZE 40 /* Assuming maximum TCP options size is 40 bytes */ +#define TCP_DATA_SIZE (MTU_SIZE - TCP_HEADER_SIZE - sizeof(struct ip4_header) - TCP_OPTIONS_SIZE) + uint8_t data[MTU_SIZE - TCP_HEADER_SIZE - sizeof(struct ip4_header)]; +} PACKED; + +struct t_tcp { + struct ether_header ether; + struct ip4_header ip4; + struct t_tcp_packet tcp; +} PACKED; + +#define IPv4_UDP_HEADERS_SIZE (sizeof(struct ip4_header) + UDP_HEADER_SIZE) /* IP | UDP */ + +#endif /* NET_PROTOCOL_TCP_H_ */ diff --git a/lib-gd32/include/gd32_micros.h b/lib-network/include/net/protocol/udp.h old mode 100644 new mode 100755 similarity index 58% rename from lib-gd32/include/gd32_micros.h rename to lib-network/include/net/protocol/udp.h index 14e654dd..49bd5ec2 --- a/lib-gd32/include/gd32_micros.h +++ b/lib-network/include/net/protocol/udp.h @@ -1,8 +1,8 @@ /** - * @file gd32_micros.h + * @file udp.h * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,33 +23,34 @@ * THE SOFTWARE. */ -#ifndef GD32_MICROS_H_ -#define GD32_MICROS_H_ +#ifndef NET_PROTOCOL_UDP_H_ +#define NET_PROTOCOL_UDP_H_ #include -#include "gd32.h" +#include "net/protocol/ethernet.h" +#include "net/protocol/ip4.h" -#if defined (GD32F4XX) && !defined(MICROS_DO_NOT_USE_TIMER4) -static inline uint32_t micros() { - return TIMER_CNT(TIMER4); -} -#else -static inline uint32_t micros() { - static uint32_t nMicrosPrevious; - static uint32_t nResult; - const auto nMicros = DWT->CYCCNT / (MCU_CLOCK_FREQ / 1000000U); - - if (nMicros > nMicrosPrevious) { - nResult += (nMicros - nMicrosPrevious); - } else { - nResult += ((UINT32_MAX/ (MCU_CLOCK_FREQ / 1000000U)) - nMicrosPrevious + nMicros); - } - - nMicrosPrevious = nMicros; - - return nResult; -} +#if !defined (PACKED) +# define PACKED __attribute__((packed)) #endif -#endif /* GD32_MICROS_H_ */ +struct t_udp_packet { + uint16_t source_port; /* 2 */ + uint16_t destination_port; /* 4 */ + uint16_t len; /* 6 */ + uint16_t checksum; /* 8 */ +#define UDP_HEADER_SIZE 8 +#define UDP_DATA_SIZE (MTU_SIZE - UDP_HEADER_SIZE - sizeof(struct ip4_header)) + uint8_t data[UDP_DATA_SIZE]; +}PACKED; + +struct t_udp { + struct ether_header ether; + struct ip4_header ip4; + struct t_udp_packet udp; +} PACKED; + +#define UDP_PACKET_HEADERS_SIZE (sizeof(struct ether_header) + IPv4_UDP_HEADERS_SIZE) /* ETH | IP | UDP */ + +#endif /* NET_PROTOCOL_UDP_H_ */ diff --git a/lib-network/include/netif.h b/lib-network/include/netif.h new file mode 100755 index 00000000..5e7f5dc0 --- /dev/null +++ b/lib-network/include/netif.h @@ -0,0 +1,168 @@ +/** + * @file netif.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef NETIF_H_ +#define NETIF_H_ + +#include + +#include "netif.h" +#include "ip4_address.h" + +#include "debug.h" + +#ifndef NETIF_MAX_HWADDR_LEN +# define NETIF_MAX_HWADDR_LEN 6U +#endif + +namespace net { +struct ip_addr { + uint32_t addr; +}; + +typedef struct ip_addr ip4_addr_t; + +struct netif { + static constexpr uint8_t NETIF_FLAG_LINK_UP = (1U << 0); + static constexpr uint8_t NETIF_FLAG_DHCP_OK = (1U << 1); + static constexpr uint8_t NETIF_FLAG_AUTOIP_OK = (1U << 2); + static constexpr uint8_t NETIF_FLAG_STATICIP_OK = (1U << 3); + + struct ip_addr ip; + struct ip_addr netmask; + struct ip_addr gw; + struct ip_addr broadcast_ip; + struct ip_addr secondary_ip; + + uint8_t hwaddr[NETIF_MAX_HWADDR_LEN]; + uint8_t flags; + + const char *hostname; + + void *dhcp; + void *acd; + void *autoip; +}; + +struct NetifReason { + static constexpr uint16_t NSC_NONE = 0x0000; + static constexpr uint16_t NSC_LINK_CHANGED = 0x0004; + static constexpr uint16_t NSC_IPV4_ADDRESS_CHANGED = 0x0010; + static constexpr uint16_t NSC_IPV4_GATEWAY_CHANGED = 0x0020; + static constexpr uint16_t NSC_IPV4_NETMASK_CHANGED = 0x0040; + static constexpr uint16_t NSC_IPV4_SETTINGS_CHANGED = 0x0080; + static constexpr uint16_t NSC_IPV4_ADDR_VALID = 0x0400; +}; + +struct ipv4_changed { + ip4_addr_t old_address; + ip4_addr_t old_netmask; + ip4_addr_t old_gw; +}; + +struct link_changed { + /** 1: up; 0: down */ + uint8_t state; +} ; + +union netif_ext_callback_args_t { + struct link_changed link_changed; + struct ipv4_changed ipv4_changed; +}; + +namespace globals { +extern struct netif netif_default; +} // namespace globals + +typedef void (* netif_ext_callback_fn)(const uint16_t reason, const netif_ext_callback_args_t *args); + +inline void netif_set_flags(uint8_t flags) { + globals::netif_default.flags |= flags; +} + +inline void netif_clear_flags(uint8_t flags) { + globals::netif_default.flags &= static_cast(~flags); +} + +inline bool netif_dhcp() { + return (globals::netif_default.flags & netif::NETIF_FLAG_DHCP_OK) == netif::NETIF_FLAG_DHCP_OK; +} + +inline bool netif_autoip() { + return (globals::netif_default.flags & netif::NETIF_FLAG_AUTOIP_OK) == netif::NETIF_FLAG_AUTOIP_OK; +} + +inline uint32_t netif_ipaddr() { + return globals::netif_default.ip.addr; +} + +inline uint32_t netif_netmask() { + return globals::netif_default.netmask.addr; +} + +inline uint32_t netif_gw() { + return globals::netif_default.gw.addr; +} + +inline void netif_set_hostname(const char *hostname) { + globals::netif_default.hostname = hostname; +} + +inline const char *netif_hostname() { + return globals::netif_default.hostname; +} + +inline uint32_t netif_secondary_ipaddr() { + return globals::netif_default.secondary_ip.addr; +} + +inline uint32_t netif_broadcast_ipaddr() { + return globals::netif_default.broadcast_ip.addr; +} + +inline const uint8_t *netif_hwaddr() { + return globals::netif_default.hwaddr; +} +void netif_init(); +void netif_set_ipaddr(const ip4_addr_t ipaddr); +void netif_set_netmask(const ip4_addr_t netmask); +void netif_set_gw(const ip4_addr_t gw); +void netif_set_addr(const ip4_addr_t ipaddr, const ip4_addr_t netmask, const ip4_addr_t gw); + +void netif_add_ext_callback(netif_ext_callback_fn fn); + +/** + * Link + */ + +void netif_set_link_up(); +void netif_set_link_down(); + +inline bool netif_is_link_up() { + return (globals::netif_default.flags & netif::NETIF_FLAG_LINK_UP) == netif::NETIF_FLAG_LINK_UP; +} +} // namespace net + +#endif /* NETIF_H_ */ diff --git a/lib-network/include/network.h b/lib-network/include/network.h index da334071..7fe09f45 100644 --- a/lib-network/include/network.h +++ b/lib-network/include/network.h @@ -2,7 +2,7 @@ * @file network.h * */ -/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,117 +28,25 @@ #include -#define IP2STR(addr) (addr & 0xFF), ((addr >> 8) & 0xFF), ((addr >> 16) & 0xFF), ((addr >> 24) & 0xFF) -#define IPSTR "%d.%d.%d.%d" - -#define MAC2STR(mac) static_cast(mac[0]),static_cast(mac[1]),static_cast(mac[2]),static_cast(mac[3]), static_cast(mac[4]), static_cast(mac[5]) -#define MACSTR "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x" +#include "ip4_address.h" namespace network { -static constexpr auto STORE = 96; ///< Configuration store in bytes -static constexpr auto IP_SIZE = 4U; -static constexpr auto MAC_SIZE = 6U; -static constexpr auto HOSTNAME_SIZE = 64U; ///< Including a terminating null byte. -static constexpr auto DOMAINNAME_SIZE = 64U; ///< Including a terminating null byte. -static constexpr auto IP4_BROADCAST = 0xffffffff; namespace dhcp { enum class Mode: uint8_t { INACTIVE = 0x00, ///< The IP address was not obtained via DHCP ACTIVE = 0x01, ///< The IP address was obtained via DHCP UNKNOWN = 0x02 ///< The system cannot determine if the address was obtained via DHCP }; -enum class ClientStatus { - IDLE, RENEW, GOT_IP, RETRYING, FAILED -}; } // namespace dhcp - -static constexpr uint32_t convert_to_uint(const uint8_t a, const uint8_t b, const uint8_t c, const uint8_t d) { - return static_cast(a) | - static_cast(b) << 8 | - static_cast(c) << 16 | - static_cast(d) << 24; -} - -inline bool is_netmask_valid(uint32_t nNetMask) { - if (nNetMask == 0) { - return false; - } - nNetMask = __builtin_bswap32(nNetMask); - return !(nNetMask & (~nNetMask >> 1)); - -} -/** - * The private address ranges are defined in RFC1918. - */ -inline bool is_private_ip(const uint32_t nIp) { - const uint8_t n = (nIp >> 8) & 0xFF; - - switch (nIp & 0xFF) { - case 10: - return true; - break; - case 172: - return (n >= 16) && (n < 32); - case 192: - return n == 168; - default: - break; - } - - return false; -} - -inline bool is_multicast_ip(const uint32_t nIp) { - if ((nIp & 0xE0) != 0xE0) { - return false; - } - - if ((nIp & 0xFFFFEF) == 0x0000E0) { // 224.0.0.0 to 224.0.0.255 Local subnetwork - return false; - } - - if ((nIp & 0xFFFFEF) == 0x0100E0) { // 224.0.1.0 to 224.0.1.255 Internetwork control - return false; - } - - return true; -} - -inline uint32_t cidr_to_netmask(const uint8_t nCIDR) { - if (nCIDR != 0) { - const auto nNetmask = __builtin_bswap32(static_cast(~0x0) << (32 - nCIDR)); - return nNetmask; - } - - return 0; -} - -void display_emac_config(); -void display_emac_start(); -void display_emac_status(const bool isLinkUp); -void display_ip(); -void display_netmask(); -void display_gateway(); -void display_hostname(); -void display_dhcp_status(network::dhcp::ClientStatus nStatus); -void display_emac_shutdown(); - -void mdns_announcement(); -void mdns_shutdown(); } // namespace network -class NetworkStore { -public: - virtual ~NetworkStore() {} - - virtual void SaveIp(uint32_t nIp)=0; - virtual void SaveNetMask(uint32_t nNetMask)=0; - virtual void SaveGatewayIp(uint32_t nGatewayIp)=0; - virtual void SaveHostName(const char *pHostName, uint32_t nLength)=0; - virtual void SaveDhcp(bool bIsDhcpUsed)=0; -}; - -#if defined (BARE_METAL) +#if defined(__linux__) || defined (__APPLE__) +# if defined (CONFIG_NETWORK_USE_MINIMUM) +# include "linux/minimum/network.h" +# else +# include "linux/network.h" +# endif +#else # if defined (ESP8266) # include "esp8266/network.h" # elif defined (NO_EMAC) @@ -146,8 +54,6 @@ class NetworkStore { # else # include "emac/network.h" # endif -#else -# include "linux/network.h" #endif #endif /* NETWORK_H_ */ diff --git a/lib-network/include/networkconst.h b/lib-network/include/networkconst.h index 4809ea1b..185d103c 100644 --- a/lib-network/include/networkconst.h +++ b/lib-network/include/networkconst.h @@ -2,7 +2,7 @@ * @file networkconst.h * */ -/* Copyright (C) 2019-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-network/include/networkparams.h b/lib-network/include/networkparams.h index c975b87d..33008df0 100644 --- a/lib-network/include/networkparams.h +++ b/lib-network/include/networkparams.h @@ -29,6 +29,7 @@ #include #include "network.h" +#include "configstore.h" namespace networkparams { namespace defaults { @@ -79,26 +80,27 @@ struct Mask { class NetworkParamsStore { public: - virtual ~NetworkParamsStore() {} + static void Update(const struct networkparams::Params *pParams) { + ConfigStore::Get()->Update(configstore::Store::NETWORK, pParams, sizeof(struct networkparams::Params)); + } - virtual void Update(const networkparams::Params *pNetworkParams)=0; - virtual void Copy(networkparams::Params *pNetworkParams)=0; + static void Copy(struct networkparams::Params *pParams) { + ConfigStore::Get()->Copy(configstore::Store::NETWORK, pParams, sizeof(struct networkparams::Params)); + } }; class NetworkParams { public: - NetworkParams(NetworkParamsStore *pNetworkParamsStore); + NetworkParams(); - bool Load(); + void Load(); void Load(const char *pBuffer, uint32_t nLength); - void Builder(const networkparams::Params *ptNetworkParams, char *pBuffer, uint32_t nLength, uint32_t& nSize); + void Builder(const networkparams::Params *pParams, char *pBuffer, uint32_t nLength, uint32_t& nSize); void Save(char *pBuffer, uint32_t nLength, uint32_t& nSize) { Builder(nullptr, pBuffer, nLength, nSize); } - void Dump(); - bool isDhcpUsed() const { return m_Params.bIsDhcpUsed; } @@ -155,13 +157,13 @@ class NetworkParams { static void staticCallbackFunction(void *p, const char *s); private: + void Dump(); void callbackFunction(const char *s); bool isMaskSet(uint32_t nMask) const { return (m_Params.nSetList & nMask) == nMask; } private: - NetworkParamsStore *m_pNetworkParamsStore; networkparams::Params m_Params; }; diff --git a/lib-network/include/networkparamsconst.h b/lib-network/include/networkparamsconst.h index 93aef889..a5af8678 100644 --- a/lib-network/include/networkparamsconst.h +++ b/lib-network/include/networkparamsconst.h @@ -2,7 +2,7 @@ * @file networkparamsconst.h * */ -/* Copyright (C) 2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -38,7 +38,6 @@ struct NetworkParamsConst { static const char HOSTNAME[]; static const char NTP_SERVER[]; - static const char NTP_UTC_OFFSET[]; #if defined (ESP8266) static const char NAME_SERVER[]; diff --git a/lib-network/include/networkstore.h b/lib-network/include/networkstore.h new file mode 100755 index 00000000..26fe06cf --- /dev/null +++ b/lib-network/include/networkstore.h @@ -0,0 +1,60 @@ +/** + * @file networkstore.h + * + */ +/* Copyright (C) 2023 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef NETWORKSTORE_H_ +#define NETWORKSTORE_H_ + +#include +#include +#include + +#include "networkparams.h" +#include "configstore.h" + +class NetworkStore { +public: + static void SaveIp(uint32_t nIp) { + ConfigStore::Get()->Update(configstore::Store::NETWORK, offsetof(struct networkparams::Params, nLocalIp), &nIp, sizeof(uint32_t), networkparams::Mask::IP_ADDRESS); + } + + static void SaveNetMask(uint32_t nNetMask) { + ConfigStore::Get()->Update(configstore::Store::NETWORK, offsetof(struct networkparams::Params, nNetmask), &nNetMask, sizeof(uint32_t), networkparams::Mask::NET_MASK); + } + + static void SaveGatewayIp(uint32_t nGatewayIp) { + ConfigStore::Get()->Update(configstore::Store::NETWORK, offsetof(struct networkparams::Params, nGatewayIp), &nGatewayIp, sizeof(uint32_t), networkparams::Mask::DEFAULT_GATEWAY); + } + + static void SaveHostName(const char *pHostName, uint32_t nLength) { + nLength = std::min(nLength,static_cast(network::HOSTNAME_SIZE)); + ConfigStore::Get()->Update(configstore::Store::NETWORK, offsetof(struct networkparams::Params, aHostName), pHostName, nLength, networkparams::Mask::HOSTNAME); + } + + static void SaveDhcp(bool bIsDhcpUsed) { + ConfigStore::Get()->Update(configstore::Store::NETWORK, offsetof(struct networkparams::Params, bIsDhcpUsed), &bIsDhcpUsed, sizeof(bool), networkparams::Mask::DHCP); + } +}; + +#endif /* NETWORKSTORE_H_ */ diff --git a/lib-network/include/ntpclient.h b/lib-network/include/ntpclient.h deleted file mode 100644 index a8eb05b7..00000000 --- a/lib-network/include/ntpclient.h +++ /dev/null @@ -1,96 +0,0 @@ -/** - * @file ntpclient.h - * - */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef NTPCLIENT_H_ -#define NTPCLIENT_H_ - -#include -#include - -#include "ntp.h" - -namespace ntpclient { -enum class Status { - IDLE, FAILED, STOPPED, WAITING -}; - -void display_status(Status status); -} // namespace ntpclient - -class NtpClient { -public: - NtpClient(uint32_t nServerIp = 0); - - void Start(); - void Stop(); - void Run(); - - void Print(); - - ntpclient::Status GetStatus() { - return m_Status; - } - - static NtpClient *Get() { - return s_pThis; - } - -private: - void SetUtcOffset(float fUtcOffset); - void GetTimeNtpFormat(uint32_t &nSeconds, uint32_t &nFraction); - void Send(); - bool Receive(uint8_t& LiVnMode); - - struct TimeStamp { - uint32_t nSeconds; - uint32_t nFraction; - }; - - void Difference(const struct TimeStamp *Start, const struct TimeStamp *Stop, int32_t &nDiffSeconds, uint32_t &nDiffFraction); - int SetTimeOfDay(); - - void PrintNtpTime(const char *pText, const struct TimeStamp *pNtpTime); - -private: - uint32_t m_nServerIp; - int32_t m_nUtcOffset; - int32_t m_nHandle { -1 }; - ntpclient::Status m_Status { ntpclient::Status::IDLE }; - struct TNtpPacket m_Request; - uint32_t m_MillisRequest { 0 }; - uint32_t m_MillisLastPoll { 0 }; - - struct TimeStamp T1 { 0, 0 }; // time request sent by client - struct TimeStamp T2 { 0, 0 }; // time request received by server - struct TimeStamp T3 { 0, 0 }; // time reply sent by server - struct TimeStamp T4 { 0, 0 }; // time reply received by client - - int32_t m_nOffsetSeconds { 0 }; - uint32_t m_nOffsetMicros { 0 }; - - static NtpClient *s_pThis; -}; - -#endif /* NTPCLIENT_H_ */ diff --git a/lib-network/src/apps/ntp/ntpclient.cpp b/lib-network/src/apps/ntp/ntpclient.cpp deleted file mode 100644 index 9d2a68d6..00000000 --- a/lib-network/src/apps/ntp/ntpclient.cpp +++ /dev/null @@ -1,365 +0,0 @@ -/** - * @file ntpclient.cpp - * - */ -/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#include -#include -#include - -#include "ntpclient.h" -#include "ntp.h" - -#include "utc.h" - -#include "network.h" -#include "hardware.h" - -#include "debug.h" - -static constexpr auto RETRIES = 3; -static constexpr auto TIMEOUT_MILLIS = 3000; // 3 seconds -static constexpr auto POLL_SECONDS = 1024; // 2ˆ10 -static constexpr auto JAN_1970 = 0x83aa7e80; // 2208988800 1970 - 1900 in seconds - -/* How to multiply by 4294.967296 quickly (and not quite exactly) - * without using floating point or greater than 32-bit integers. - * If you want to fix the last 12 microseconds of error, add in - * (2911*(x))>>28) - */ -#define NTPFRAC(x) ( 4294U*static_cast(x) + ( (1981U*static_cast(x))>>11 ) + ((2911U*static_cast(x))>>28) ) - -/* The reverse of the above, needed if we want to set our microsecond - * clock (via clock_settime) based on the incoming time in NTP format. - * Basically exact. - */ -#define USEC(x) ( ( (x) >> 12 ) - 759 * ( ( ( (x) >> 10 ) + 32768 ) >> 16 ) ) - -/* -Timestamp Name ID When Generated ----------------------------------------------------------------- -Originate Timestamp T1 time request sent by client -Receive Timestamp T2 time request received by server -Transmit Timestamp T3 time reply sent by server -Destination Timestamp T4 time reply received by client -*/ - -NtpClient *NtpClient::s_pThis; - -NtpClient::NtpClient(uint32_t nServerIp): m_nServerIp(nServerIp) { - DEBUG_ENTRY - assert(s_pThis == nullptr); - s_pThis = this; - - if (m_nServerIp == 0) { - m_nServerIp = Network::Get()->GetNtpServerIp(); - } - - SetUtcOffset(Network::Get()->GetNtpUtcOffset()); - - memset(&m_Request, 0, sizeof m_Request); - - m_Request.LiVnMode = NTP_VERSION | NTP_MODE_CLIENT; - m_Request.Poll = 10; // Poll: 1024 seconds - m_Request.ReferenceID = ('A' << 0) | ('V' << 8) | ('S' << 16); - - DEBUG_EXIT -} - -void NtpClient::SetUtcOffset(float fUtcOffset) { - // https://en.wikipedia.org/wiki/List_of_UTC_time_offsets - m_nUtcOffset = Utc::Validate(fUtcOffset); -} - -/* - * Seconds and Fractions since 01.01.1900 - */ -void NtpClient::GetTimeNtpFormat(uint32_t &nSeconds, uint32_t &nFraction) { - struct timeval now; - gettimeofday(&now, nullptr); - nSeconds = static_cast(now.tv_sec - m_nUtcOffset) + JAN_1970; - nFraction = NTPFRAC(now.tv_usec); -} - -void NtpClient::Send() { - GetTimeNtpFormat(T1.nSeconds, T1.nFraction); - - m_Request.OriginTimestamp_s = __builtin_bswap32(T1.nSeconds); - m_Request.OriginTimestamp_f = __builtin_bswap32(T1.nFraction); - - Network::Get()->SendTo(m_nHandle, &m_Request, sizeof m_Request, m_nServerIp, NTP_UDP_PORT); -} - -bool NtpClient::Receive(uint8_t& LiVnMode) { - uint32_t nFromIp; - uint16_t nFromPort; - TNtpPacket *pReply; - - const auto nBytesReceived = Network::Get()->RecvFrom(m_nHandle, const_cast(reinterpret_cast(&pReply)), &nFromIp, &nFromPort); - - if (__builtin_expect((nBytesReceived != sizeof(struct TNtpPacket)), 1)) { - return false; - } - - GetTimeNtpFormat(T4.nSeconds, T4.nFraction); - - if (__builtin_expect((nFromIp != m_nServerIp), 0)) { - DEBUG_PUTS("nFromIp != m_nServerIp"); - return false; - } - - LiVnMode = pReply->LiVnMode; - - T2.nSeconds = __builtin_bswap32(pReply->ReceiveTimestamp_s); - T2.nFraction = __builtin_bswap32(pReply->ReceiveTimestamp_f); - - T3.nSeconds = __builtin_bswap32(pReply->TransmitTimestamp_s); - T3.nFraction = __builtin_bswap32(pReply->TransmitTimestamp_f); - - PrintNtpTime("Originate", &T1); - PrintNtpTime("Receive", &T2); - PrintNtpTime("Transmit", &T3); - PrintNtpTime("Destination", &T4); - - return true; -} - -void NtpClient::Difference(const struct TimeStamp *Start, const struct TimeStamp *Stop, int32_t &nDiffSeconds, uint32_t &nDiffMicros) { - nDiffSeconds = static_cast(Stop->nSeconds - Start->nSeconds); - uint32_t nDiffFraction; - - if (Stop->nFraction >= Start->nFraction) { - nDiffFraction = Stop->nFraction - Start->nFraction; - } else { - nDiffFraction = Start->nFraction - Stop->nFraction; - nDiffFraction = ~nDiffFraction; - nDiffSeconds -= 1; - } - - nDiffMicros = USEC(nDiffFraction); - - DEBUG_PRINTF("Seconds %u - %u = %d", Stop->nSeconds, Start->nSeconds, nDiffSeconds); - DEBUG_PRINTF("Micros %u - %u = %u", USEC(Stop->nFraction), USEC(Start->nFraction), nDiffMicros); -} - -int NtpClient::SetTimeOfDay() { - int32_t nDiffSeconds1, nDiffSeconds2 ; - uint32_t nDiffFraction1, nDiffFraction2; - - Difference(&T1, &T2, nDiffSeconds1, nDiffFraction1); - Difference(&T4, &T3, nDiffSeconds2, nDiffFraction2); - - m_nOffsetSeconds = nDiffSeconds1 + nDiffSeconds2; - m_nOffsetMicros = nDiffFraction1 + nDiffFraction2; - - if (m_nOffsetMicros >= 1000000u) { - m_nOffsetMicros -= 1000000u; - m_nOffsetSeconds += 1; - } - - m_nOffsetSeconds /= 2; - m_nOffsetMicros /= 2; - - struct timeval tv; - - tv.tv_sec = static_cast(T4.nSeconds - JAN_1970) + m_nOffsetSeconds + m_nUtcOffset; - tv.tv_usec = (static_cast(USEC(T4.nFraction)) + static_cast(m_nOffsetMicros)); - - if (tv.tv_usec >= 1000000) { - tv.tv_sec++; - tv.tv_usec = 1000000 - tv.tv_usec; - } - - DEBUG_PRINTF("(%ld, %d) %s ", tv.tv_sec, static_cast(tv.tv_usec) , tv.tv_usec >= 1E6 ? "!" : ""); - DEBUG_PRINTF("%d %u",m_nOffsetSeconds, m_nOffsetMicros); - - return settimeofday(&tv, nullptr); -} - -void NtpClient::Start() { - DEBUG_ENTRY - - if (m_nServerIp == 0) { - m_Status = ntpclient::Status::FAILED; - ntpclient::display_status(ntpclient::Status::FAILED); - DEBUG_EXIT - return; - } - - if ((m_Status != ntpclient::Status::IDLE) && (m_Status != ntpclient::Status::STOPPED)) { - DEBUG_EXIT - return; - } - - m_nHandle = Network::Get()->Begin(NTP_UDP_PORT); - assert(m_nHandle != -1); - - ntpclient::display_status(ntpclient::Status::IDLE); - - const auto nNow = Hardware::Get()->Millis(); - uint32_t nRetries; - - for (nRetries = 0; nRetries < RETRIES; nRetries++) { - Send(); - - uint8_t LiVnMode = 0; - - while (!Receive(LiVnMode)) { -#if defined (HAVE_NET_HANDLE) - net_handle(); -#endif - if ((Hardware::Get()->Millis() - nNow) > TIMEOUT_MILLIS) { - break; - } - } - - if ((LiVnMode & NTP_MODE_SERVER) == NTP_MODE_SERVER) { - if (SetTimeOfDay() == 0) { - m_Status = ntpclient::Status::IDLE; - } else { - // Error - } - } else { - m_Status = ntpclient::Status::FAILED; - DEBUG_PUTS("!>> Invalid reply <Millis(); - - if (nRetries == RETRIES) { - m_Status = ntpclient::Status::FAILED; - ntpclient::display_status(ntpclient::Status::FAILED); - } - - DEBUG_PRINTF("nRetries=%d, m_Status=%d", nRetries, static_cast(m_Status)); - -#if !defined(DISABLE_RTC) - if (m_Status != ntpclient::Status::FAILED) { - printf("Set RTC from System Clock\n"); - HwClock::Get()->SysToHc(); -#ifndef NDEBUG - const auto rawtime = time(nullptr); - printf(asctime(localtime(&rawtime))); -#endif - } -#endif - - DEBUG_EXIT -} - -void NtpClient::Stop() { - DEBUG_ENTRY - - if (m_Status == ntpclient::Status::STOPPED) { - return; - } - - m_nHandle = Network::Get()->End(NTP_UDP_PORT); - m_Status = ntpclient::Status::STOPPED; - - ntpclient::display_status(ntpclient::Status::STOPPED); - - DEBUG_EXIT -} - -void NtpClient::Run() { - if (__builtin_expect((m_nServerIp == 0), 0)) { - return; - } - - if ((m_Status == ntpclient::Status::IDLE) || (m_Status == ntpclient::Status::FAILED)) { - if (__builtin_expect(((Hardware::Get()->Millis() - m_MillisLastPoll) > (1000 * POLL_SECONDS)), 0)) { - Send(); - m_MillisRequest = Hardware::Get()->Millis(); - m_Status = ntpclient::Status::WAITING; - DEBUG_PUTS("ntpclient::Status::WAITING"); - } - - return; - } - - if (m_Status == ntpclient::Status::WAITING) { - uint8_t LiVnMode; - - if (!Receive(LiVnMode)) { - if (__builtin_expect(((Hardware::Get()->Millis() - m_MillisRequest) > TIMEOUT_MILLIS), 0)) { - m_Status = ntpclient::Status::FAILED; - ntpclient::display_status(ntpclient::Status::FAILED); - DEBUG_PUTS("ntpclient::Status::FAILED"); - } - - return; - } - - if (__builtin_expect(((LiVnMode & NTP_MODE_SERVER) == NTP_MODE_SERVER), 1)) { - m_MillisLastPoll = Hardware::Get()->Millis(); - - if (SetTimeOfDay() == 0) { -#ifndef NDEBUG - const auto nTime = time(nullptr); - const auto *pLocalTime = localtime(&nTime); - DEBUG_PRINTF("%.4d/%.2d/%.2d %.2d:%.2d:%.2d", pLocalTime->tm_year, pLocalTime->tm_mon, pLocalTime->tm_mday, pLocalTime->tm_hour, pLocalTime->tm_min, pLocalTime->tm_sec); -#endif - } else { - // Error - } - } else { - DEBUG_PUTS("!>> Invalid reply <(pNtpTime->nSeconds - JAN_1970); - const auto *pTm = localtime(&nSeconds); - printf("%s %02d:%02d:%02d.%06d %04d [%u]\n", pText, pTm->tm_hour, pTm->tm_min, pTm->tm_sec, USEC(pNtpTime->nFraction), pTm->tm_year + 1900, pNtpTime->nSeconds); -#endif -} - -static constexpr char STATUS[4][8] = { "Idle", "Failed", "Stopped", "Waiting" }; - -void NtpClient::Print() { - printf("NTP v%d Client\n", NTP_VERSION >> 3); - if (m_nServerIp == 0) { - printf(" Not enabled\n"); - return; - } - printf(" Server : " IPSTR ":%d\n", IP2STR(m_nServerIp), NTP_UDP_PORT); - printf(" Status : %s\n", STATUS[static_cast(m_Status)]); - printf(" UTC offset : %d (seconds)\n", m_nUtcOffset); -#ifndef NDEBUG - PrintNtpTime("Originate", &T1); - PrintNtpTime("Receive", &T2); - PrintNtpTime("Transmit", &T3); - PrintNtpTime("Destination", &T4); -#endif -} diff --git a/lib-network/src/emac/gd32/emac.cpp b/lib-network/src/emac/gd32/emac.cpp index 811fedf3..e482d334 100644 --- a/lib-network/src/emac/gd32/emac.cpp +++ b/lib-network/src/emac/gd32/emac.cpp @@ -2,7 +2,7 @@ * emac.cpp * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -30,117 +30,23 @@ #include "emac/phy.h" +#include "hwclock.h" + #include "debug.h" -extern enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; +extern "C" { +void console_error(const char *); +} +extern void enet_gpio_config(); +extern enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; extern void mac_address_get(uint8_t paddr[]); -static void enet_gpio_config(void) { - DEBUG_ENTRY -#if defined (GD32F10X) || defined (GD32F20X) - rcu_periph_clock_enable(RCU_GPIOA); - rcu_periph_clock_enable(RCU_GPIOB); - rcu_periph_clock_enable(RCU_GPIOC); - rcu_periph_clock_enable(RCU_AF); - - gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_8); - - rcu_pll2_config(RCU_PLL2_MUL10); - rcu_osci_on(RCU_PLL2_CK); - rcu_osci_stab_wait(RCU_PLL2_CK); - /* get 50MHz from CK_PLL2 on CKOUT0 pin (PA8) to clock the PHY */ -# if defined (GD32F10X_CL) - rcu_ckout0_config(RCU_CKOUT0SRC_CKPLL2); -# else - rcu_ckout0_config(RCU_CKOUT0SRC_CKPLL2,RCU_CKOUT0_DIV1); -# endif - gpio_ethernet_phy_select(GPIO_ENET_PHY_RMII); - - /* PA1: ETH_RMII_REF_CLK */ - gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_1); - /* PA2: ETH_MDIO */ - gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2); - /* PA7: ETH_RMII_CRS_DV */ - gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_7); - - /* PC1: ETH_MDC */ - gpio_init(GPIOC, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_1); - /* PC4: ETH_RMII_RXD0 */ - gpio_init(GPIOC, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_4); - /* PC5: ETH_RMII_RXD1 */ - gpio_init(GPIOC, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_5); - - /* PB11: ETH_RMII_TX_EN */ - gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_11); - /* PB12: ETH_RMII_TXD0 */ - gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_12); - /* PB13: ETH_RMII_TXD1 */ - gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13); -#else - rcu_periph_clock_enable(RCU_GPIOA); - rcu_periph_clock_enable(RCU_GPIOB); - rcu_periph_clock_enable(RCU_GPIOC); - rcu_periph_clock_enable(RCU_SYSCFG); - - gpio_af_set(GPIOA, GPIO_AF_0, GPIO_PIN_8); - gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_8); - gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_8); - - /* choose DIV4 to get 50MHz from 200MHz on CKOUT0 pin (PA8) to clock the PHY */ - rcu_ckout0_config(RCU_CKOUT0SRC_PLLP, RCU_CKOUT0_DIV4); - syscfg_enet_phy_interface_config(SYSCFG_ENET_PHY_RMII); - - /* PA1: ETH_RMII_REF_CLK */ - gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_1); - gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_1); - - /* PA2: ETH_MDIO */ - gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_2); - gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_2); - - /* PA7: ETH_RMII_CRS_DV */ - gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_7); - gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_7); - - gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_1); - gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_2); - gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_7); - - /* PB11: ETH_RMII_TX_EN */ - gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_11); - gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_11); - - /* PB12: ETH_RMII_TXD0 */ - gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_12); - gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_13); - - /* PB13: ETH_RMII_TXD1 */ - gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13); - gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_14); - - gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_11); - gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_12); - gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_13); - - /* PC1: ETH_MDC */ - gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_1); - gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_1); - - /* PC4: ETH_RMII_RXD0 */ - gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4); - gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_4); - - /* PC5: ETH_RMII_RXD1 */ - gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_5); - gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_5); - - gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_1); - gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_4); - gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_5); +#if defined (CONFIG_ENET_ENABLE_PTP) +# include "gd32_ptp.h" +enet_descriptors_struct ptp_rxdesc_tab[ENET_RXBUF_NUM] __attribute__((aligned(4))); +enet_descriptors_struct ptp_txdesc_tab[ENET_TXBUF_NUM] __attribute__((aligned(4))); #endif - DEBUG_EXIT -} /* * Public function @@ -164,30 +70,40 @@ void __attribute__((cold)) emac_config() { rcu_periph_clock_enable(RCU_ENETTX); rcu_periph_clock_enable(RCU_ENETRX); - enet_deinit(); - enet_software_reset(); + enet_deinit(ENETx); + enet_software_reset(ENETx); - net::phy_config(PHY_ADDRESS); + if(!net::phy_config(PHY_ADDRESS)) { + console_error("net::phy_config(PHY_ADDRESS)"); + } DEBUG_EXIT } -void __attribute__((cold)) emac_start(uint8_t mac_address[], net::Link& link) { +void emac_adjust_link(const net::PhyStatus phyStatus) { DEBUG_ENTRY - DEBUG_PRINTF("ENET_RXBUF_NUM=%u, ENET_TXBUF_NUM=%u", ENET_RXBUF_NUM, ENET_TXBUF_NUM); - net::PhyStatus phyStatus; - net::phy_start(PHY_ADDRESS, phyStatus); - - link = phyStatus.link; + printf("Link %s, %d, %s\n", + phyStatus.link == net::Link::STATE_UP ? "Up" : "Down", + phyStatus.speed == net::Speed::SPEED10 ? 10 : 100, + phyStatus.duplex == net::Duplex::DUPLEX_HALF ? "HALF" : "FULL"); #ifndef NDEBUG { uint16_t phy_value; +#if defined (GD32H7XX) + ErrStatus phy_state = enet_phy_write_read(ENETx, ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value); +#else ErrStatus phy_state = enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value); +#endif printf("BCR: %.4x %s\n", phy_value, phy_state == SUCCESS ? "SUCCES" : "ERROR" ); +#if defined (GD32H7XX) + enet_phy_write_read(ENETx, ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); + phy_state = enet_phy_write_read(ENETx, ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); +#else enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); phy_state = enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); +#endif printf("BSR: %.4x %s\n", phy_value & (PHY_AUTONEGO_COMPLETE | PHY_LINKED_STATUS | PHY_JABBER_DETECTION), phy_state == SUCCESS ? "SUCCES" : "ERROR" ); } #endif @@ -204,12 +120,11 @@ void __attribute__((cold)) emac_start(uint8_t mac_address[], net::Link& link) { mediamode = ENET_10M_FULLDUPLEX; } - printf("Link %s, %d, %s\n", - phyStatus.link == net::Link::STATE_UP ? "Up" : "Down", - phyStatus.speed == net::Speed::SPEED10 ? 10 : 100, - phyStatus.duplex == net::Duplex::DUPLEX_HALF ? "HALF" : "FULL"); - +#if defined (GD32H7XX) + const auto enet_init_status = enet_init(ENETx, mediamode, ENET_AUTOCHECKSUM_DROP_FAILFRAMES, ENET_CUSTOM); +#else const auto enet_init_status = enet_init(mediamode, ENET_AUTOCHECKSUM_DROP_FAILFRAMES, ENET_CUSTOM); +#endif if (enet_init_status != SUCCESS) {} @@ -218,26 +133,71 @@ void __attribute__((cold)) emac_start(uint8_t mac_address[], net::Link& link) { #ifndef NDEBUG { uint16_t phy_value; +#if defined (GD32H7XX) + ErrStatus phy_state = enet_phy_write_read(ENETx, ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value); +#else ErrStatus phy_state = enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value); +#endif printf("BCR: %.4x %s\n", phy_value, phy_state == SUCCESS ? "SUCCES" : "ERROR" ); +#if defined (GD32H7XX) + enet_phy_write_read(ENETx, ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); + phy_state = enet_phy_write_read(ENETx, ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); +#else enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); phy_state = enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); +#endif printf("BSR: %.4x %s\n", phy_value & (PHY_AUTONEGO_COMPLETE | PHY_LINKED_STATUS | PHY_JABBER_DETECTION), phy_state == SUCCESS ? "SUCCES" : "ERROR" ); } #endif + DEBUG_EXIT +} + +void __attribute__((cold)) emac_start(uint8_t mac_address[], net::Link& link) { + DEBUG_ENTRY + DEBUG_PRINTF("ENET_RXBUF_NUM=%u, ENET_TXBUF_NUM=%u", ENET_RXBUF_NUM, ENET_TXBUF_NUM); + + net::PhyStatus phyStatus; + net::phy_start(PHY_ADDRESS, phyStatus); + + link = phyStatus.link; + + emac_adjust_link(phyStatus); mac_address_get(mac_address); +#if defined (GD32H7XX) + enet_mac_address_set(ENETx, ENET_MAC_ADDRESS0, mac_address); +# if defined (CONFIG_ENET_ENABLE_PTP) + enet_ptp_normal_descriptors_chain_init(ENETx, ENET_DMA_TX, ptp_txdesc_tab); + enet_ptp_normal_descriptors_chain_init(ENETx, ENET_DMA_RX, ptp_rxdesc_tab); +# else + enet_descriptors_chain_init(ENETx, ENET_DMA_TX); + enet_descriptors_chain_init(ENETx, ENET_DMA_RX); +# endif +#else enet_mac_address_set(ENET_MAC_ADDRESS0, mac_address); - +# if defined (CONFIG_ENET_ENABLE_PTP) + enet_ptp_normal_descriptors_chain_init(ENET_DMA_TX, ptp_txdesc_tab); + enet_ptp_normal_descriptors_chain_init(ENET_DMA_RX, ptp_rxdesc_tab); +# else enet_descriptors_chain_init(ENET_DMA_TX); enet_descriptors_chain_init(ENET_DMA_RX); +# endif +#endif - for (unsigned i = 0; i < ENET_TXBUF_NUM; i++) { + for (uint32_t i = 0; i < ENET_TXBUF_NUM; i++) { enet_transmit_checksum_config(&txdesc_tab[i], ENET_CHECKSUM_TCPUDPICMP_FULL); } - enet_enable(); +#if defined (CONFIG_ENET_ENABLE_PTP) + gd32_ptp_start(); +# if !defined(DISABLE_RTC) + // Set the System Clock from the Hardware Clock + HwClock::Get()->HcToSys(); +# endif +#endif + + enet_enable(ENETx); DEBUG_EXIT } diff --git a/lib-network/src/emac/gd32/f/emac.cpp b/lib-network/src/emac/gd32/f/emac.cpp new file mode 100644 index 00000000..b33bf4b2 --- /dev/null +++ b/lib-network/src/emac/gd32/f/emac.cpp @@ -0,0 +1,144 @@ +/** + * emac.cpp + * + */ +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "gd32.h" + +#include "debug.h" + +/** + * Needed for older GD32F firmware + */ +#if !defined(GPIO_OSPEED_MAX) +# define GPIO_OSPEED_MAX GPIO_OSPEED_200MHZ +#endif + +void enet_gpio_config() { + DEBUG_ENTRY +#if defined (GD32F10X) || defined (GD32F20X) + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_GPIOC); + rcu_periph_clock_enable(RCU_AF); + + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_8); + + rcu_pll2_config(RCU_PLL2_MUL10); + rcu_osci_on(RCU_PLL2_CK); + rcu_osci_stab_wait(RCU_PLL2_CK); + /* get 50MHz from CK_PLL2 on CKOUT0 pin (PA8) to clock the PHY */ +# if defined (GD32F10X_CL) + rcu_ckout0_config(RCU_CKOUT0SRC_CKPLL2); +# else + rcu_ckout0_config(RCU_CKOUT0SRC_CKPLL2,RCU_CKOUT0_DIV1); +# endif + gpio_ethernet_phy_select(GPIO_ENET_PHY_RMII); + + /* PA1: ETH_RMII_REF_CLK */ + gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_1); + /* PA2: ETH_MDIO */ + gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2); + /* PA7: ETH_RMII_CRS_DV */ + gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_7); + + /* PC1: ETH_MDC */ + gpio_init(GPIOC, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_1); + /* PC4: ETH_RMII_RXD0 */ + gpio_init(GPIOC, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_4); + /* PC5: ETH_RMII_RXD1 */ + gpio_init(GPIOC, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_5); + + /* PB11: ETH_RMII_TX_EN */ + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_11); + /* PB12: ETH_RMII_TXD0 */ + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_12); + /* PB13: ETH_RMII_TXD1 */ + gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13); +#else + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOB); + rcu_periph_clock_enable(RCU_GPIOC); + rcu_periph_clock_enable(RCU_SYSCFG); + + gpio_af_set(GPIOA, GPIO_AF_0, GPIO_PIN_8); + gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_8); + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_MAX,GPIO_PIN_8); + + /* choose DIV4 to get 50MHz from 200MHz on CKOUT0 pin (PA8) to clock the PHY */ + rcu_ckout0_config(RCU_CKOUT0SRC_PLLP, RCU_CKOUT0_DIV4); + syscfg_enet_phy_interface_config(SYSCFG_ENET_PHY_RMII); + + /* PA1: ETH_RMII_REF_CLK */ + gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_1); + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_MAX,GPIO_PIN_1); + + /* PA2: ETH_MDIO */ + gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_2); + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_MAX,GPIO_PIN_2); + + /* PA7: ETH_RMII_CRS_DV */ + gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_7); + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_MAX,GPIO_PIN_7); + + gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_1); + gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_2); + gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_7); + + /* PB11: ETH_RMII_TX_EN */ + gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_11); + gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_MAX,GPIO_PIN_11); + + /* PB12: ETH_RMII_TXD0 */ + gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_12); + gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_MAX,GPIO_PIN_13); + + /* PB13: ETH_RMII_TXD1 */ + gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13); + gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_MAX,GPIO_PIN_14); + + gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_11); + gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_12); + gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_13); + + /* PC1: ETH_MDC */ + gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_1); + gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_MAX,GPIO_PIN_1); + + /* PC4: ETH_RMII_RXD0 */ + gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4); + gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_MAX,GPIO_PIN_4); + + /* PC5: ETH_RMII_RXD1 */ + gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_5); + gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_MAX,GPIO_PIN_5); + + gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_1); + gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_4); + gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_5); +#endif + DEBUG_EXIT +} diff --git a/lib-network/src/emac/gd32/f/net.cpp b/lib-network/src/emac/gd32/f/net.cpp new file mode 100644 index 00000000..713d281b --- /dev/null +++ b/lib-network/src/emac/gd32/f/net.cpp @@ -0,0 +1,244 @@ +/** + * net.cpp + * + */ +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#if !defined (CONFIG_REMOTECONFIG_MINIMUM) +# pragma GCC push_options +# pragma GCC optimize ("O2") +# pragma GCC optimize ("no-tree-loop-distribute-patterns") +#endif + +#include +#include + +#include "gd32.h" +#include "../src/net/net_memcpy.h" + +#include "debug.h" + +#if defined (CONFIG_ENET_ENABLE_PTP) +#include "gd32_ptp.h" + +extern enet_descriptors_struct *dma_current_ptp_rxdesc; +extern enet_descriptors_struct *dma_current_ptp_txdesc; +namespace net { +namespace globals { +extern uint32_t ptpTimestamp[2]; +} // namespace globals +} // namespace net +#endif +extern enet_descriptors_struct *dma_current_rxdesc; +extern enet_descriptors_struct *dma_current_txdesc; + +int emac_eth_recv(uint8_t **ppPacket) { + const auto nLength = enet_desc_information_get(dma_current_rxdesc, RXDESC_FRAME_LENGTH); + + if (nLength > 0) { +#if defined (CONFIG_ENET_ENABLE_PTP) + *ppPacket = reinterpret_cast(dma_current_ptp_rxdesc->buffer1_addr); +#else + *ppPacket = reinterpret_cast(dma_current_rxdesc->buffer1_addr); +#endif + return nLength; + } + + return -1; +} + +#if defined (CONFIG_ENET_ENABLE_PTP) +static void ptpframe_receive_normal_mode() { + net::globals::ptpTimestamp[0] = dma_current_rxdesc->buffer1_addr; + net::globals::ptpTimestamp[1] = dma_current_rxdesc->buffer2_next_desc_addr; + + dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc->buffer1_addr; + dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc->buffer2_next_desc_addr; + dma_current_rxdesc->status = ENET_RDES0_DAV; + + if (0 != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { + /* clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0U; + } + + assert(0 != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)); + + dma_current_rxdesc = reinterpret_cast(dma_current_ptp_rxdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if (0 != dma_current_ptp_rxdesc->status) { + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_rxdesc = reinterpret_cast(dma_current_ptp_rxdesc->status); + } else { + /* ponter to the next ptp descriptor */ + dma_current_ptp_rxdesc++; + } +} +#else +static void frame_receive() { + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* check Rx buffer unavailable flag status */ + if (0 != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { + /* clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0U; + } + + assert(0 != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)); + + dma_current_rxdesc = reinterpret_cast(dma_current_rxdesc->buffer2_next_desc_addr); +} +#endif + +void emac_free_pkt() { + while(0 != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { + __DMB(); + } +#if defined (CONFIG_ENET_ENABLE_PTP) + ptpframe_receive_normal_mode(); +#else + frame_receive(); +#endif +} + +#if defined (CONFIG_ENET_ENABLE_PTP) +inline static void ptpframe_transmit(const uint8_t *pBuffer, const uint32_t nLength, const bool bCaptureTimestamp) { + assert (nullptr != pBuffer); + assert(nLength <= ENET_MAX_FRAME_SIZE); + + auto *pDst = reinterpret_cast(dma_current_ptp_txdesc->buffer1_addr); + net::memcpy(pDst, pBuffer, nLength); + + dma_current_txdesc->control_buffer_size = (nLength & (uint32_t)0x1FFF); + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + const auto dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + const auto dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if ((0 != dma_tbu_flag) || (0 != dma_tu_flag)) { + /* clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0U; + } + + uint32_t timeout = 0; + uint32_t tdes0_ttmss_flag; + + if (bCaptureTimestamp) { + do { + tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); + __DMB(); + timeout++; + } while((0 == tdes0_ttmss_flag) && (timeout < UINT32_MAX)); + + DEBUG_PRINTF("timeout=%x %d", timeout, (dma_current_txdesc->status & ENET_TDES0_TTMSS)); + + dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; + + net::globals::ptpTimestamp[0] = dma_current_txdesc->buffer1_addr; + net::globals::ptpTimestamp[1] = dma_current_txdesc->buffer2_next_desc_addr; + } + + dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc->buffer1_addr; + dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc->buffer2_next_desc_addr; + + assert(0 != (dma_current_txdesc->status & ENET_TDES0_TCHM)); /* chained mode */ + + /* update the current TxDMA descriptor pointer to the next descriptor in TxDMA descriptor table */ + dma_current_txdesc = reinterpret_cast(dma_current_ptp_txdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if(0 != dma_current_ptp_txdesc->status) { + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_txdesc = reinterpret_cast(dma_current_ptp_txdesc->status); + } else { + /* pointer to the next ptp descriptor */ + dma_current_ptp_txdesc++; + } +} + +void emac_eth_send(void *pBuffer, uint32_t nLength) { + while (0 != (dma_current_txdesc->status & ENET_TDES0_DAV)) { + __DMB(); + } + + auto nStatus = dma_current_txdesc->status; + nStatus &= ~ENET_TDES0_TTSEN; + dma_current_txdesc->status = nStatus; + + ptpframe_transmit(reinterpret_cast(pBuffer), nLength, false); +} + +void emac_eth_send_timestamp(void *pBuffer, uint32_t nLength) { + while (0 != (dma_current_txdesc->status & ENET_TDES0_DAV)) { + __DMB(); + } + + auto nStatus = dma_current_txdesc->status; + nStatus |= ENET_TDES0_TTSEN; + dma_current_txdesc->status = nStatus; + + ptpframe_transmit(reinterpret_cast(pBuffer), nLength, true); +} +#else +void emac_eth_send(void *pBuffer, uint32_t nLength) { + assert(nullptr != pBuffer); + assert(nLength <= static_cast(ENET_MAX_FRAME_SIZE)); + + while (0 != (dma_current_txdesc->status & ENET_TDES0_DAV)) { + __DMB(); + } + + auto *pDst = reinterpret_cast(dma_current_txdesc->buffer1_addr); + net::memcpy(pDst, pBuffer, nLength); + + /* set the frame length */ + dma_current_txdesc->control_buffer_size = nLength; + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + const auto dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + const auto dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if ((0 != dma_tbu_flag) || (0 != dma_tu_flag)) { + /* clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0; + } + + assert(0 != (dma_current_txdesc->status & ENET_TDES0_TCHM)); /* chained mode */ + + /* update the current TxDMA descriptor pointer to the next descriptor in TxDMA descriptor table*/ + dma_current_txdesc = reinterpret_cast(dma_current_txdesc->buffer2_next_desc_addr); +} +#endif diff --git a/lib-network/src/emac/gd32/net_link_check.cpp b/lib-network/src/emac/gd32/net_link_check.cpp index 15711075..f3efe054 100644 --- a/lib-network/src/emac/gd32/net_link_check.cpp +++ b/lib-network/src/emac/gd32/net_link_check.cpp @@ -25,6 +25,7 @@ #include +#include "emac/phy.h" #include "emac/net_link_check.h" #include "gd32.h" diff --git a/lib-network/src/emac/gd32/net_phy.cpp b/lib-network/src/emac/gd32/net_phy.cpp index 018729ac..693aa290 100644 --- a/lib-network/src/emac/gd32/net_phy.cpp +++ b/lib-network/src/emac/gd32/net_phy.cpp @@ -2,7 +2,7 @@ * net_phy.cpp * */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,22 +28,28 @@ #include "emac/phy.h" #include "emac/mmi.h" +#include "hardware.h" #include "gd32.h" #include "debug.h" -extern volatile uint32_t s_nSysTickMillis; - namespace net { - bool phy_read(uint32_t nAddress, const uint32_t nRegister, uint16_t &nValue) { +#if defined (GD32H7XX) + const auto bResult = enet_phy_write_read(ENETx, ENET_PHY_READ, nAddress, nRegister, &nValue) == SUCCESS; +#else const auto bResult = enet_phy_write_read(ENET_PHY_READ, nAddress, nRegister, &nValue) == SUCCESS; +#endif // DEBUG_PRINTF("%d %.2x %.2x %.4x", bResult, nAddress, nRegister, nValue); return bResult; } bool phy_write(uint32_t nAddress, const uint32_t nRegister, uint16_t nValue) { +#if defined (GD32H7XX) + const auto bResult = enet_phy_write_read(ENETx, ENET_PHY_WRITE, nAddress, nRegister, &nValue) == SUCCESS; +#else const auto bResult = enet_phy_write_read(ENET_PHY_WRITE, nAddress, nRegister, &nValue) == SUCCESS; +#endif // DEBUG_PRINTF("%d %.2x %.2x %.4x", bResult, nAddress, nRegister, nValue); return bResult; } @@ -51,11 +57,17 @@ bool phy_write(uint32_t nAddress, const uint32_t nRegister, uint16_t nValue) { bool phy_config(const uint32_t nAddress) { DEBUG_ENTRY +#if defined (GD32H7XX) + uint32_t reg = ENET_MAC_PHY_CTL(ENETx); +#else uint32_t reg = ENET_MAC_PHY_CTL; +#endif reg &= ~ENET_MAC_PHY_CTL_CLR; const uint32_t ahbclk = rcu_clock_freq_get(CK_AHB); + DEBUG_PRINTF("ahbclk=%u", ahbclk); + #if defined GD32F10X_CL if (ENET_RANGE(ahbclk, 20000000U, 35000000U)) { reg |= ENET_MDC_HCLK_DIV16; @@ -89,14 +101,38 @@ bool phy_config(const uint32_t nAddress) { reg |= ENET_MDC_HCLK_DIV42; } else if (ENET_RANGE(ahbclk, 100000000U, 150000000U)) { reg |= ENET_MDC_HCLK_DIV62; - } else if ((ENET_RANGE(ahbclk, 150000000U, 200000000U)) || (200000000U == ahbclk)) { + } else if ((ENET_RANGE(ahbclk, 150000000U, 240000000U)) || (240000000U == ahbclk)) { reg |= ENET_MDC_HCLK_DIV102; } else { return false; } +#elif defined GD32H7XX + if (ENET_RANGE(ahbclk, 20000000U, 35000000U)) { + reg |= ENET_MDC_HCLK_DIV16; + } else if (ENET_RANGE(ahbclk, 35000000U, 60000000U)) { + reg |= ENET_MDC_HCLK_DIV26; + } else if (ENET_RANGE(ahbclk, 60000000U, 100000000U)) { + reg |= ENET_MDC_HCLK_DIV42; + } else if (ENET_RANGE(ahbclk, 100000000U, 150000000U)) { + reg |= ENET_MDC_HCLK_DIV62; + } else if ((ENET_RANGE(ahbclk, 150000000U, 180000000U)) || (180000000U == ahbclk)) { + reg |= ENET_MDC_HCLK_DIV102; + } else if (ENET_RANGE(ahbclk, 250000000U, 300000000U)) { + reg |= ENET_MDC_HCLK_DIV124; + } else if (ENET_RANGE(ahbclk, 300000000U, 350000000U)) { + reg |= ENET_MDC_HCLK_DIV142; + } else if ((ENET_RANGE(ahbclk, 350000000U, 400000000U)) || (400000000U == ahbclk)) { + reg |= ENET_MDC_HCLK_DIV162; + } else { + return false; + } #endif +#if defined (GD32H7XX) + ENET_MAC_PHY_CTL(ENETx) = reg; +#else ENET_MAC_PHY_CTL = reg; +#endif if (!phy_write(nAddress, mmi::REG_BMCR, mmi::BMCR_RESET)) { DEBUG_PUTS("PHY reset failed"); @@ -109,17 +145,17 @@ bool phy_config(const uint32_t nAddress) { * IEEE spec. */ - const auto nMillis = s_nSysTickMillis; + const auto nMillis = Hardware::Get()->Millis(); uint16_t nValue; - while (s_nSysTickMillis - nMillis < 500) { + while (Hardware::Get()->Millis() - nMillis < 500) { if (!phy_read(nAddress, mmi::REG_BMCR, nValue)) { DEBUG_PUTS("PHY status read failed"); return false; } if (!(nValue & mmi::BMCR_RESET)) { - DEBUG_PRINTF("%u", s_nSysTickMillis - nMillis); + DEBUG_PRINTF("%u", Hardware::Get()->Millis() - nMillis); DEBUG_EXIT return true; } @@ -130,7 +166,7 @@ bool phy_config(const uint32_t nAddress) { return false; } - DEBUG_PRINTF("%u", s_nSysTickMillis - nMillis); + DEBUG_PRINTF("%u", Hardware::Get()->Millis() - nMillis); DEBUG_EXIT return true; } diff --git a/lib-network/src/emac/network.cpp b/lib-network/src/emac/network.cpp index 8ad248a3..e993f43b 100755 --- a/lib-network/src/emac/network.cpp +++ b/lib-network/src/emac/network.cpp @@ -2,7 +2,7 @@ * network.cpp * */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,29 +23,37 @@ * THE SOFTWARE. */ +#ifdef DEBUG_NETWORK +# undef NDEBUG +#endif + #include +#include #include #include #include #include "network.h" #include "networkparams.h" +#include "networkstore.h" #include "hardware.h" -#include "../net/net.h" -#include "../../config/net_config.h" - #include "emac/emac.h" #include "emac/phy.h" #include "emac/mmi.h" #include "emac/net_link_check.h" +#include "netif.h" +#include "net/autoip.h" +#include "net/dhcp.h" + +#include "../../config/net_config.h" + #include "debug.h" namespace network { void __attribute__((weak)) mdns_announcement() {} -void __attribute__((weak)) mdns_shutdown() {} } // namespace network static constexpr char TO_HEX(const char i) { @@ -56,42 +64,71 @@ static constexpr char TO_HEX(const char i) { # define PHY_ADDRESS 1 #endif +static void netif_ext_callback(const uint16_t reason, [[maybe_unused]] const net::netif_ext_callback_args_t *args) { + DEBUG_ENTRY + + if ((reason & net::NetifReason::NSC_IPV4_ADDRESS_CHANGED) == net::NetifReason::NSC_IPV4_ADDRESS_CHANGED) { + net::display_ip(); + network::mdns_announcement(); + + printf("ip: " IPSTR " -> " IPSTR "\n", IP2STR(args->ipv4_changed.old_address.addr), IP2STR(net::netif_ipaddr())); + } + + if ((reason & net::NetifReason::NSC_IPV4_NETMASK_CHANGED) == net::NetifReason::NSC_IPV4_NETMASK_CHANGED) { + net::display_netmask(); + + printf("netmask: " IPSTR " -> " IPSTR "\n", IP2STR(args->ipv4_changed.old_netmask.addr), IP2STR(net::netif_netmask())); + } + + if ((reason & net::NetifReason::NSC_IPV4_GATEWAY_CHANGED) == net::NetifReason::NSC_IPV4_GATEWAY_CHANGED) { + net::display_gateway(); + + printf("gw: " IPSTR " -> " IPSTR "\n", IP2STR(args->ipv4_changed.old_gw.addr), IP2STR(net::netif_gw())); + } + + if ((reason & net::NetifReason::NSC_LINK_CHANGED) == net::NetifReason::NSC_LINK_CHANGED) { + if (args->link_changed.state == 0) { // Link down + net::net_link_down(); + + DEBUG_EXIT + return; + } + } + + DEBUG_EXIT +} + Network *Network::s_pThis; -Network::Network(NetworkParamsStore *pNetworkParamsStore) { +Network::Network() { DEBUG_ENTRY assert(s_pThis == nullptr); s_pThis = this; - m_aDomainName[0] = '\0'; - strcpy(m_aIfName, "eth0"); + m_aDomainName[0] = '\0'; + memset(&m_nNameservers, 0, sizeof(m_nNameservers)); - network::display_emac_config(); + net::display_emac_config(); emac_config(); - network::display_emac_start(); - - emac_start(m_aNetMacaddr, s_lastState); - - NetworkParams params(pNetworkParamsStore); - - if (params.Load()) { - params.Dump(); - } + net::display_emac_start(); - m_IpInfo.ip.addr = params.GetIpAddress(); - m_IpInfo.netmask.addr = params.GetNetMask(); - m_IpInfo.gw.addr = params.GetDefaultGateway(); - m_IsDhcpUsed = params.isDhcpUsed(); - m_nNtpServerIp = params.GetNtpServer(); - m_fNtpUtcOffset = params.GetNtpUtcOffset(); + emac_start(net::globals::netif_default.hwaddr, s_lastState); + printf(MACSTR "\n", MAC2STR(net::globals::netif_default.hwaddr)); net::phy_customized_timing(); net::phy_customized_led(); + net::netif_init(); + net::netif_add_ext_callback(netif_ext_callback); + + NetworkParams params; + params.Load(); + const auto *p = params.GetHostName(); + assert(p != nullptr); if (*p == '\0') { uint32_t k = 0; @@ -100,18 +137,35 @@ Network::Network(NetworkParamsStore *pNetworkParamsStore) { m_aHostName[k++] = HOST_NAME_PREFIX[i]; } - m_aHostName[k++] = TO_HEX(m_aNetMacaddr[3] >> 4); - m_aHostName[k++] = TO_HEX(m_aNetMacaddr[3] & 0x0F); - m_aHostName[k++] = TO_HEX(m_aNetMacaddr[4] >> 4); - m_aHostName[k++] = TO_HEX(m_aNetMacaddr[4] & 0x0F); - m_aHostName[k++] = TO_HEX(m_aNetMacaddr[5] >> 4); - m_aHostName[k++] = TO_HEX(m_aNetMacaddr[5] & 0x0F); + auto hwaddr = net::globals::netif_default.hwaddr; + + m_aHostName[k++] = TO_HEX(hwaddr[3] >> 4); + m_aHostName[k++] = TO_HEX(hwaddr[3] & 0x0F); + m_aHostName[k++] = TO_HEX(hwaddr[4] >> 4); + m_aHostName[k++] = TO_HEX(hwaddr[4] & 0x0F); + m_aHostName[k++] = TO_HEX(hwaddr[5] >> 4); + m_aHostName[k++] = TO_HEX(hwaddr[5] & 0x0F); m_aHostName[k] = '\0'; } else { strncpy(m_aHostName, p, sizeof(m_aHostName) - 1); m_aHostName[sizeof(m_aHostName) - 1] = '\0'; } + net::netif_set_hostname(m_aHostName); + + net::ip4_addr_t ipaddr; + net::ip4_addr_t netmask; + net::ip4_addr_t gw; + + ipaddr.addr = params.GetIpAddress(); + netmask.addr = params.GetNetMask(); + gw.addr = params.GetDefaultGateway(); + + bool isDhcpUsed = params.isDhcpUsed(); + + net::display_emac_status(net::Link::STATE_UP == s_lastState); + net::net_init(s_lastState, ipaddr, netmask, gw, isDhcpUsed); + #if defined (ENET_LINK_CHECK_USE_INT) net::link_interrupt_init(); #elif defined (ENET_LINK_CHECK_USE_PIN_POLL) @@ -119,110 +173,23 @@ Network::Network(NetworkParamsStore *pNetworkParamsStore) { #elif defined (ENET_LINK_CHECK_REG_POLL) net::link_status_read(); #endif - - network::display_emac_status(net::Link::STATE_UP == s_lastState); - - if (net::Link::STATE_UP == s_lastState) { - DEBUG_PUTS("net::Link::STATE_UP"); - - if (!m_IsDhcpUsed) { - DEBUG_PUTS(""); - if (m_IpInfo.ip.addr == 0) { - DEBUG_PUTS(""); - } else if (!IsValidIp(m_IpInfo.gw.addr)) { - DEBUG_PUTS(""); - m_IpInfo.gw.addr = m_IpInfo.ip.addr; - } - } - - if (m_IsDhcpUsed) { - network::display_dhcp_status(network::dhcp::ClientStatus::RENEW); - } - - net_init(m_aNetMacaddr, &m_IpInfo, m_aHostName, &m_IsDhcpUsed, &m_IsZeroconfUsed); - - if (m_IsZeroconfUsed) { - network::display_dhcp_status(network::dhcp::ClientStatus::FAILED); - } - - const auto nRetryTime = params.GetDhcpRetryTime(); - const auto bUseDhcp = params.isDhcpUsed(); - - while (m_IsZeroconfUsed && (nRetryTime != 0) && bUseDhcp) { - Hardware::Get()->SetMode(hardware::ledblink::Mode::FAST); - - network::display_dhcp_status(network::dhcp::ClientStatus::RETRYING); - - DEBUG_PUTS(""); - auto nTime = time(nullptr); - while ((time(nullptr) - nTime) < (nRetryTime * 60)) { - Hardware::Get()->Run(); - } - - network::display_dhcp_status(network::dhcp::ClientStatus::RENEW); - - Hardware::Get()->SetMode(hardware::ledblink::Mode::OFF_ON); - - m_IsDhcpUsed = true; - m_IsZeroconfUsed = false; - - net_init(m_aNetMacaddr, &m_IpInfo, m_aHostName, &m_IsDhcpUsed, &m_IsZeroconfUsed); - - if (m_IsDhcpUsed) { - break; - } - } - } else { - DEBUG_PUTS("net::Link::STATE_DOWN"); - - if (m_IsDhcpUsed) { - DEBUG_PUTS("m_IsDhcpUsed=true"); - m_IpInfo.ip.addr = 0; - m_IpInfo.netmask.addr = 0; - m_IpInfo.gw.addr = 0; - } - - auto bFalse = false; - - net_init(m_aNetMacaddr, &m_IpInfo, m_aHostName, &bFalse, &bFalse); - } - - network::display_ip(); - network::display_netmask(); - network::display_gateway(); - DEBUG_EXIT } void Network::SetIp(uint32_t nIp) { DEBUG_ENTRY - if (m_IsDhcpUsed) { - m_IsDhcpUsed = false; - net_dhcp_release(); - } - - m_IsZeroconfUsed = false; - - m_IpInfo.ip.addr = nIp; - - if (nIp == 0) { - } else { - m_IpInfo.gw.addr = m_IpInfo.ip.addr; + if (nIp == net::netif_ipaddr()) { + DEBUG_EXIT + return; } - net_set_ip(&m_IpInfo); - net_set_gw(&m_IpInfo); - - if (m_pNetworkStore != nullptr) { - m_pNetworkStore->SaveIp(m_IpInfo.ip.addr); - m_pNetworkStore->SaveGatewayIp(m_IpInfo.gw.addr); - m_pNetworkStore->SaveDhcp(false); - } + net::ip4_addr_t ipaddr; + ipaddr.addr = nIp; + net_set_primary_ip(ipaddr); - network::mdns_announcement(); - network::display_ip(); - network::display_netmask(); + NetworkStore::SaveIp(nIp); + NetworkStore::SaveDhcp(false); DEBUG_EXIT } @@ -230,20 +197,17 @@ void Network::SetIp(uint32_t nIp) { void Network::SetNetmask(uint32_t nNetmask) { DEBUG_ENTRY - if (m_IpInfo.netmask.addr == nNetmask) { + if (nNetmask == net::netif_netmask()) { DEBUG_EXIT return; } - m_IpInfo.netmask.addr = nNetmask; - net_set_netmask(&m_IpInfo); + net::ip4_addr_t netmask; + netmask.addr = nNetmask; - if (m_pNetworkStore != nullptr) { - m_pNetworkStore->SaveNetMask(m_IpInfo.netmask.addr); - } + net::netif_set_netmask(netmask); - network::display_ip(); - network::display_netmask(); + NetworkStore::SaveNetMask(nNetmask); DEBUG_EXIT } @@ -251,19 +215,17 @@ void Network::SetNetmask(uint32_t nNetmask) { void Network::SetGatewayIp(uint32_t nGatewayIp) { DEBUG_ENTRY - if (m_IpInfo.gw.addr == nGatewayIp) { + if (nGatewayIp == net::netif_gw()) { DEBUG_EXIT return; } - m_IpInfo.gw.addr = nGatewayIp; - net_set_gw(&m_IpInfo); + net::ip4_addr_t gw; + gw.addr = nGatewayIp; - if (m_pNetworkStore != nullptr) { - m_pNetworkStore->SaveGatewayIp(m_IpInfo.gw.addr); - } + net::netif_set_gw(gw); - network::display_gateway(); + NetworkStore::SaveGatewayIp(nGatewayIp); DEBUG_EXIT } @@ -274,145 +236,126 @@ void Network::SetHostName(const char *pHostName) { strncpy(m_aHostName, pHostName, network::HOSTNAME_SIZE - 1); m_aHostName[network::HOSTNAME_SIZE - 1] = '\0'; - if (m_pNetworkStore != nullptr) { - m_pNetworkStore->SaveHostName(m_aHostName, static_cast(strlen(m_aHostName))); - } + NetworkStore::SaveHostName(m_aHostName, static_cast(strlen(m_aHostName))); network::mdns_announcement(); - network::display_hostname(); + net::display_hostname(); DEBUG_EXIT } -bool Network::SetZeroconf() { +void Network::SetZeroconf() { DEBUG_ENTRY - const auto bWatchdog = Hardware::Get()->IsWatchdog(); - - if (bWatchdog) { - Hardware::Get()->WatchdogStop(); - } - - m_IsZeroconfUsed = net_set_zeroconf(&m_IpInfo); - - if (m_IsZeroconfUsed) { - m_IsDhcpUsed = false; - - if (m_pNetworkStore != nullptr) { - m_pNetworkStore->SaveDhcp(true);// Zeroconf is enabled only when use_dhcp=1 - } - } - - network::mdns_announcement(); - network::display_ip(); - network::display_netmask(); + net::autoip_start(); - if (bWatchdog) { - Hardware::Get()->WatchdogInit(); - } + NetworkStore::SaveDhcp(false); DEBUG_EXIT - return m_IsZeroconfUsed; } -bool Network::EnableDhcp() { +void Network::EnableDhcp() { DEBUG_ENTRY - const auto bWatchdog = Hardware::Get()->IsWatchdog(); - - if (bWatchdog) { - Hardware::Get()->WatchdogStop(); - } - - network::display_dhcp_status(network::dhcp::ClientStatus::RENEW); + net::dhcp_start(); - m_IsDhcpUsed = net_set_dhcp(&m_IpInfo, m_aHostName, &m_IsZeroconfUsed); - - if (m_IsZeroconfUsed) { - network::display_dhcp_status(network::dhcp::ClientStatus::FAILED); - } else { - network::display_dhcp_status(network::dhcp::ClientStatus::GOT_IP); - } - - DEBUG_PRINTF("m_IsDhcpUsed=%d, m_IsZeroconfUsed=%d", m_IsDhcpUsed, m_IsZeroconfUsed); - - if (m_pNetworkStore != nullptr) { - m_pNetworkStore->SaveDhcp(m_IsDhcpUsed); - } - - network::mdns_announcement(); - network::display_ip(); - network::display_netmask(); - network::display_gateway(); - - if (bWatchdog) { - Hardware::Get()->WatchdogInit(); - } + NetworkStore::SaveDhcp(true); DEBUG_EXIT - return m_IsDhcpUsed; } -void Network::SetQueuedStaticIp(uint32_t nLocalIp, uint32_t nNetmask) { +void Network::SetQueuedStaticIp(const uint32_t nStaticIp, const uint32_t nNetmask) { DEBUG_ENTRY - DEBUG_PRINTF(IPSTR ", nNetmask=" IPSTR, IP2STR(nLocalIp), IP2STR(nNetmask)); + DEBUG_PRINTF(IPSTR ", nNetmask=" IPSTR, IP2STR(nStaticIp), IP2STR(nNetmask)); - if (nLocalIp != 0) { - m_QueuedConfig.nLocalIp = nLocalIp; + if (nStaticIp != 0) { + m_QueuedConfig.nStaticIp = nStaticIp; + } else { + m_QueuedConfig.nStaticIp = GetIp(); } if (nNetmask != 0) { m_QueuedConfig.nNetmask = nNetmask; + } else { + m_QueuedConfig.nNetmask = GetNetmask(); } m_QueuedConfig.nMask |= QueuedConfig::STATIC_IP; - m_QueuedConfig.nMask |= QueuedConfig::NET_MASK; + m_QueuedConfig.nMask |= QueuedConfig::NETMASK; DEBUG_EXIT } +void Network::SetQueuedDefaultRoute(const uint32_t nGatewayIp) { + if (nGatewayIp != 0) { + m_QueuedConfig.nGateway = nGatewayIp; + } else { + m_QueuedConfig.nGateway = GetGatewayIp(); + } + + m_QueuedConfig.nMask |= QueuedConfig::GW; +} + bool Network::ApplyQueuedConfig() { DEBUG_ENTRY - DEBUG_PRINTF("m_QueuedConfig.nMask=%x, " IPSTR ", " IPSTR, m_QueuedConfig.nMask, IP2STR(m_QueuedConfig.nLocalIp), IP2STR(m_QueuedConfig.nNetmask)); + DEBUG_PRINTF("m_QueuedConfig.nMask=%x, " IPSTR ", " IPSTR, m_QueuedConfig.nMask, IP2STR(m_QueuedConfig.nStaticIp), IP2STR(m_QueuedConfig.nNetmask)); if (m_QueuedConfig.nMask == QueuedConfig::NONE) { DEBUG_EXIT return false; } - if ((isQueuedMaskSet(QueuedConfig::STATIC_IP)) || (isQueuedMaskSet(QueuedConfig::NET_MASK))) { - if (isQueuedMaskSet(QueuedConfig::NET_MASK)) { + if ((isQueuedMaskSet(QueuedConfig::STATIC_IP)) || (isQueuedMaskSet(QueuedConfig::NETMASK)) || (isQueuedMaskSet(QueuedConfig::GW))) { + // After SetIp all ip address might be zero. + if (isQueuedMaskSet(QueuedConfig::STATIC_IP)) { + SetIp(m_QueuedConfig.nStaticIp); + } + + if (isQueuedMaskSet(QueuedConfig::NETMASK)) { SetNetmask(m_QueuedConfig.nNetmask); - m_QueuedConfig.nMask &= ~(QueuedConfig::NET_MASK); } - if (isQueuedMaskSet(QueuedConfig::STATIC_IP)) { - SetIp(m_QueuedConfig.nLocalIp); - m_QueuedConfig.nMask &= ~(QueuedConfig::STATIC_IP); + if (isQueuedMaskSet(QueuedConfig::GW)) { + SetGatewayIp(m_QueuedConfig.nGateway); } + + m_QueuedConfig.nMask = QueuedConfig::NONE; + + DEBUG_EXIT + return true; } if (isQueuedMaskSet(QueuedConfig::DHCP)) { - EnableDhcp(); - m_QueuedConfig.nMask &= ~(QueuedConfig::DHCP); + if (m_QueuedConfig.mode == network::dhcp::Mode::ACTIVE) { + EnableDhcp(); + } else if (m_QueuedConfig.mode == network::dhcp::Mode::INACTIVE) { + + } + + m_QueuedConfig.mode = network::dhcp::Mode::UNKNOWN; + m_QueuedConfig.nMask = QueuedConfig::NONE; + + DEBUG_EXIT + return true; } if (isQueuedMaskSet(QueuedConfig::ZEROCONF)) { SetZeroconf(); - m_QueuedConfig.nMask &= ~(QueuedConfig::ZEROCONF); + m_QueuedConfig.nMask = QueuedConfig::NONE; + + DEBUG_EXIT + return true; } DEBUG_EXIT - return true; + return false; } -#include - void Network::Print() { printf("Network [%c]\n", GetAddressingMode()); printf(" Hostname : %s\n", m_aHostName); - printf(" IfName : %d: %s " MACSTR "\n", m_nIfIndex, m_aIfName, MAC2STR(m_aNetMacaddr)); - printf(" Primary : " IPSTR "/%d (HTTP only " IPSTR ")\n", IP2STR(m_IpInfo.ip.addr), GetNetmaskCIDR(), IP2STR(m_IpInfo.secondary_ip.addr)); - printf(" Gateway : " IPSTR "\n", IP2STR(m_IpInfo.gw.addr)); + printf(" IfName : %u: %s " MACSTR "\n", static_cast(GetIfIndex()), m_aIfName, MAC2STR(net::netif_hwaddr())); + printf(" Primary : " IPSTR "/%u (HTTP only " IPSTR ")\n", IP2STR(net::netif_ipaddr()), static_cast(GetNetmaskCIDR()), IP2STR(net::netif_secondary_ipaddr())); + printf(" Gateway : " IPSTR "\n", IP2STR(net::netif_gw())); printf(" Broadcast : " IPSTR "\n", IP2STR(GetBroadcastIp())); } diff --git a/lib-network/src/emac/phy/json_get_phystatus.cpp b/lib-network/src/emac/phy/json_get_phystatus.cpp index 73fa4ee4..ace4991d 100755 --- a/lib-network/src/emac/phy/json_get_phystatus.cpp +++ b/lib-network/src/emac/phy/json_get_phystatus.cpp @@ -29,11 +29,11 @@ namespace remoteconfig { namespace net { -uint16_t json_get_phystatus(char *pOutBuffer, const uint16_t nOutBufferSize) { +uint32_t json_get_phystatus(char *pOutBuffer, const uint32_t nOutBufferSize) { ::net::PhyStatus phyStatus; ::net::phy_customized_status(phyStatus); - const auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, + const auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, "{\"link\":\"%s\",\"speed\":\"%s\",\"duplex\":\"%s\",\"autonegotiation\":\"%s\"}", ::net::phy_string_get_link(phyStatus.link), ::net::phy_string_get_speed(phyStatus.speed), diff --git a/lib-network/src/emac/phy/link_handle_change.cpp b/lib-network/src/emac/phy/link_handle_change.cpp old mode 100644 new mode 100755 index 5b86f3a6..44bd517c --- a/lib-network/src/emac/phy/link_handle_change.cpp +++ b/lib-network/src/emac/phy/link_handle_change.cpp @@ -2,7 +2,7 @@ * link_handle_change.cpp * */ -/* Copyright (C) 2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,23 +23,41 @@ * THE SOFTWARE. */ +#include "hardware.h" #include "network.h" +#include "netif.h" #include "debug.h" -/** - * Default implementation - */ +#if !defined(PHY_ADDRESS) +# define PHY_ADDRESS 1 +#endif + +extern void emac_adjust_link(const net::PhyStatus); namespace net { -void __attribute__((weak)) link_handle_change(const net::Link state) { +void link_handle_change(const net::Link state) { DEBUG_PRINTF("net::Link %s", state == net::Link::STATE_UP ? "UP" : "DOWN"); - if (net::Link::STATE_UP == state) { - if (Network::Get()->IsDhcpUsed()) { - DEBUG_PUTS("Enable DHCP"); - Network::Get()->EnableDhcp(); + if (Link::STATE_UP == state) { + const bool isWatchdog = Hardware::Get()->IsWatchdog(); + if (isWatchdog) { + Hardware::Get()->WatchdogStop(); } + + PhyStatus phyStatus; + phy_start(PHY_ADDRESS, phyStatus); + + emac_adjust_link(phyStatus); + + if (isWatchdog) { + Hardware::Get()->WatchdogInit(); + } + + netif_set_link_up(); + return; } + + netif_set_link_down(); } } // namespace net diff --git a/lib-network/src/emac/phy/net_link_check.cpp b/lib-network/src/emac/phy/net_link_check.cpp old mode 100644 new mode 100755 index c266780d..ddacbd92 --- a/lib-network/src/emac/phy/net_link_check.cpp +++ b/lib-network/src/emac/phy/net_link_check.cpp @@ -2,7 +2,7 @@ * net_link_check.cpp * */ -/* Copyright (C) 2022-2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -48,13 +48,6 @@ void link_pin_poll_init() { #endif net::Link link_status_read() { - uint16_t nValue = 0; - phy_read(PHY_ADDRESS, mmi::REG_BMSR, nValue); - - if (mmi::BMSR_LINKED_STATUS == (nValue & mmi::BMSR_LINKED_STATUS)) { - return net::Link::STATE_UP; - } - - return net::Link::STATE_DOWN; + return net::phy_get_link(PHY_ADDRESS); } } // namespace net diff --git a/lib-network/src/emac/phy/net_phy.cpp b/lib-network/src/emac/phy/net_phy.cpp index 61be500a..82190181 100755 --- a/lib-network/src/emac/phy/net_phy.cpp +++ b/lib-network/src/emac/phy/net_phy.cpp @@ -2,7 +2,7 @@ * net_phy.cpp * */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,10 +33,11 @@ #include "hardware.h" #include "debug.h" -namespace net { - -static PhyStatus s_phyStatus; +#if !defined(PHY_ADDRESS) +# define PHY_ADDRESS 1 +#endif +namespace net { bool phy_get_id(const uint32_t nAddress, PhyIdentifier& phyIdentifier) { DEBUG_ENTRY DEBUG_PRINTF("nAddress=%.2x", nAddress); @@ -64,6 +65,17 @@ bool phy_get_id(const uint32_t nAddress, PhyIdentifier& phyIdentifier) { return true; } +Link phy_get_link(const uint32_t nAddress) { + uint16_t nValue = 0; + phy_read(nAddress, mmi::REG_BMSR, nValue); + + if (mmi::BMSR_LINKED_STATUS == (nValue & mmi::BMSR_LINKED_STATUS)) { + return net::Link::STATE_UP; + } + + return net::Link::STATE_DOWN; +} + bool phy_powerdown(const uint32_t nAddress) { return phy_write(nAddress, mmi::REG_BMCR, mmi::BMCR_POWERDOWN); } @@ -163,7 +175,7 @@ static bool phy_config_autonegotiation(const uint32_t nAddress, const uint16_t n * @param nAddress PHY address * @return true for success, false for failure */ -static bool phy_update_link(const uint32_t nAddress) { +static bool phy_update_link(const uint32_t nAddress, PhyStatus& phyStatus) { DEBUG_ENTRY uint16_t nBMSR; @@ -178,7 +190,7 @@ static bool phy_update_link(const uint32_t nAddress) { * we don't need to wait for autoneg again */ - if ((s_phyStatus.link == Link::STATE_DOWN) && (nBMSR & mmi::BMSR_LINKED_STATUS)) { + if ((phyStatus.link == Link::STATE_DOWN) && (nBMSR & mmi::BMSR_LINKED_STATUS)) { DEBUG_EXIT return true; } @@ -195,14 +207,14 @@ static bool phy_update_link(const uint32_t nAddress) { phy_read(nAddress, mmi::REG_BMSR, nBMSR); } - s_phyStatus.link = Link::STATE_UP; + phyStatus.link = Link::STATE_UP; DEBUG_PRINTF("%u", Hardware::Get()->Millis() - nMillis); DEBUG_EXIT return true; } else { phy_read(nAddress, mmi::REG_BMSR, nBMSR); - s_phyStatus.link = nBMSR & mmi::BMSR_LINKED_STATUS ? Link::STATE_UP : Link::STATE_DOWN; + phyStatus.link = nBMSR & mmi::BMSR_LINKED_STATUS ? Link::STATE_UP : Link::STATE_DOWN; DEBUG_EXIT return true; @@ -214,10 +226,10 @@ static bool phy_update_link(const uint32_t nAddress) { return true; } -static bool phy_parse_link(const uint32_t nAddress) { +static void phy_parse_link(const uint32_t nAddress, PhyStatus& phyStatus) { - s_phyStatus.duplex = Duplex::DUPLEX_HALF; - s_phyStatus.speed = Speed::SPEED10; + phyStatus.duplex = Duplex::DUPLEX_HALF; + phyStatus.speed = Speed::SPEED10; uint16_t nADVERTISE; phy_read(nAddress, mmi::REG_ADVERTISE, nADVERTISE); @@ -227,16 +239,14 @@ static bool phy_parse_link(const uint32_t nAddress) { nLPA &= nADVERTISE; if (nLPA & (mmi::LPA_100FULL | mmi::LPA_100HALF)) { - s_phyStatus.speed = Speed::SPEED100; + phyStatus.speed = Speed::SPEED100; if (nLPA & mmi::LPA_100FULL) { - s_phyStatus.duplex = Duplex::DUPLEX_FULL; + phyStatus.duplex = Duplex::DUPLEX_FULL; } } else if (nLPA & mmi::LPA_10FULL) { - s_phyStatus.duplex = Duplex::DUPLEX_FULL; + phyStatus.duplex = Duplex::DUPLEX_FULL; } - - return true; } bool phy_start(const uint32_t nAddress, PhyStatus& phyStatus) { @@ -249,17 +259,19 @@ bool phy_start(const uint32_t nAddress, PhyStatus& phyStatus) { return false; } - if (!phy_update_link(nAddress)) { + if (!phy_update_link(nAddress, phyStatus)) { DEBUG_EXIT return false; } - if (!phy_parse_link(nAddress)) { - DEBUG_EXIT - return false; - } + phy_parse_link(nAddress, phyStatus); + + phyStatus.link = phy_get_link(nAddress); - phyStatus = s_phyStatus; + DEBUG_PRINTF("Link %s, %d, %s", + phyStatus.link == net::Link::STATE_UP ? "Up" : "Down", + phyStatus.speed == net::Speed::SPEED10 ? 10 : 100, + phyStatus.duplex == net::Duplex::DUPLEX_HALF ? "HALF" : "FULL"); DEBUG_EXIT return true; diff --git a/lib-network/src/emac/phy/phygen/net_phy.cpp b/lib-network/src/emac/phy/phygen/net_phy.cpp index 07b68f29..aeb63abb 100755 --- a/lib-network/src/emac/phy/phygen/net_phy.cpp +++ b/lib-network/src/emac/phy/phygen/net_phy.cpp @@ -53,16 +53,14 @@ void phy_customized_timing() { } void phy_customized_status(PhyStatus& phyStatus) { - phyStatus.link = link_status_read(); - uint16_t nValue; - phy_read(PHY_ADDRESS, mmi::REG_BMCR, nValue); + phy_read(PHY_ADDRESS, mmi::REG_BMSR, nValue); debug_print_bits(nValue); - phyStatus.duplex = ((nValue & BIT(8)) == BIT(8)) ? Duplex::DUPLEX_FULL : Duplex::DUPLEX_HALF; - phyStatus.speed = ((nValue & BIT(13)) == BIT(13)) ? Speed::SPEED100 : Speed::SPEED10; - phyStatus.bAutonegotiation = ((nValue & mmi::BMCR_AUTONEGOTIATION) == mmi::BMCR_AUTONEGOTIATION); - + phyStatus.duplex = Duplex::DUPLEX_FULL; + phyStatus.speed = Speed::SPEED100; + phyStatus.link = (nValue & mmi::BMSR_LINKED_STATUS) ? Link::STATE_UP : Link::STATE_DOWN; + phyStatus.bAutonegotiation = (nValue & mmi::BMSR_AUTONEGO_COMPLETE); } } // namespace net diff --git a/lib-network/src/emac/phy/rtl8201f/net_phy.cpp b/lib-network/src/emac/phy/rtl8201f/net_phy.cpp index f8c54332..38050050 100755 --- a/lib-network/src/emac/phy/rtl8201f/net_phy.cpp +++ b/lib-network/src/emac/phy/rtl8201f/net_phy.cpp @@ -2,7 +2,7 @@ * phy.cpp * */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -56,9 +56,16 @@ void phy_write_paged(uint16_t phy_page, uint16_t phy_reg, uint16_t phy_value, ui DEBUG_PRINTF("tmp_value=0x%.4x, phy_value=0x%.4x", tmp_value, phy_value); phy_write(PHY_ADDRESS, phy_reg, tmp_value); + phy_write(PHY_ADDRESS, PHY_REG_PAGE_SELECT, 0); +} - phy_page = 0; +void phy_read_paged(const uint16_t phy_page, const uint16_t phy_reg, uint16_t& phy_value, const uint16_t mask = 0x0) { phy_write(PHY_ADDRESS, PHY_REG_PAGE_SELECT, phy_page); + + phy_read(PHY_ADDRESS, phy_reg, phy_value); + phy_value &= mask; + + phy_write(PHY_ADDRESS, PHY_REG_PAGE_SELECT, 0); } void phy_customized_led() { @@ -75,18 +82,26 @@ void phy_customized_led() { DEBUG_EXIT } +#define RMSR_RX_TIMING_SHIFT 4 +#define RMSR_RX_TIMING_MASK 0xF0 + +#define RMSR_TX_TIMING_SHIFT 8 +#define RMSR_TX_TIMING_MASK 0xF00 + void phy_customized_timing() { DEBUG_ENTRY -#if defined (GD32F407) || defined (GD32F450) -# define RMSR_RX_TIMING_SHIFT 4 -# define RMSR_RX_TIMING_MASK 0xF0 +#if defined (GD32F4XX) # define RMSR_RX_TIMING_VAL 0x4 -# define RMSR_TX_TIMING_SHIFT 8 -# define RMSR_TX_TIMING_MASK 0xF00 -# define RMSR_TX_TIMING_VAL 0xF +# if defined (GD32F407) +# define RMSR_TX_TIMING_VAL 0x2 // The GD32F407 is now running at 200MHz +# elif defined (GD32F470) +# define RMSR_TX_TIMING_VAL 0x1 +# else +# define RMSR_TX_TIMING_VAL 0xF +# endif constexpr uint16_t phy_value = (RMSR_RX_TIMING_VAL << RMSR_RX_TIMING_SHIFT) - | (RMSR_TX_TIMING_VAL << RMSR_TX_TIMING_SHIFT); + | (RMSR_TX_TIMING_VAL << RMSR_TX_TIMING_SHIFT); phy_write_paged(0x7, PHY_REG_RMSR, phy_value, RMSR_RX_TIMING_MASK | RMSR_TX_TIMING_MASK); #endif DEBUG_EXIT @@ -103,4 +118,24 @@ void phy_customized_status(PhyStatus& phyStatus) { phyStatus.bAutonegotiation = ((nValue & mmi::BMCR_AUTONEGOTIATION) == mmi::BMCR_AUTONEGOTIATION); } +namespace phy { +void rtl8201f_get_timings(uint32_t& nRxTiming, uint32_t& nTxTiming) { + uint16_t nValue; + phy_read_paged(0x7, PHY_REG_RMSR, nValue, RMSR_RX_TIMING_MASK | RMSR_TX_TIMING_MASK); + + nRxTiming = (nValue >> RMSR_RX_TIMING_SHIFT) & 0xF; + nTxTiming = (nValue >> RMSR_TX_TIMING_SHIFT) & 0xF; +} + +void rtl8201f_set_rxtiming(const uint32_t nRxTiming) { + const auto nValue = static_cast((nRxTiming & 0xF) << RMSR_RX_TIMING_SHIFT); + phy_write_paged(0x7, PHY_REG_RMSR, nValue, RMSR_RX_TIMING_MASK); +} + +void rtl8201f_set_txtiming(const uint32_t nTxTiming) { + const auto nValue = static_cast((nTxTiming & 0xF) << RMSR_TX_TIMING_SHIFT); + phy_write_paged(0x7, PHY_REG_RMSR, nValue, RMSR_TX_TIMING_MASK); +} + +} // namespace phy } // namespace net diff --git a/lib-network/src/net/acd.cpp b/lib-network/src/net/acd.cpp new file mode 100755 index 00000000..ea97ef63 --- /dev/null +++ b/lib-network/src/net/acd.cpp @@ -0,0 +1,328 @@ +/** + * @file acd.cpp + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +/* This code is inspired by the lwIP TCP/IP stack. + * https://savannah.nongnu.org/projects/lwip/ + */ +/** + * The acp.cpp aims to be conform to RFC 5227. + * https://datatracker.ietf.org/doc/html/rfc5227.html + * IPv4 Address Conflict Detection + */ + +#if defined (DEBUG_NET_ACD) +# undef NDEBUG +#endif + +#pragma GCC push_options +#pragma GCC optimize ("Os") + +#include +#include +#include +#include + +#include "../../config/net_config.h" + +#include "net/acd.h" +#include "net/protocol/acd.h" +#include "net/protocol/arp.h" +#include "net_memcpy.h" + +#include "hardware.h" +#include "debug.h" + +namespace net { +namespace acd { +static constexpr uint32_t ACD_TMR_INTERVAL = 100; +static constexpr uint32_t ACD_TICKS_PER_SECOND = (1000U / ACD_TMR_INTERVAL); +} // namespace acd + +static int32_t nTimerId; + +static void acd_timer() { + auto *acd = reinterpret_cast(globals::netif_default.acd); + assert(acd != nullptr); + + if (acd->lastconflict > 0) { + acd->lastconflict--; + } + + DEBUG_PRINTF("state=%u, ttw=%u", static_cast(acd->state), acd->ttw); + + if (acd->ttw > 0) { + acd->ttw--; + } + + switch (acd->state) { + case acd::State::ACD_STATE_PROBE_WAIT: + case acd::State::ACD_STATE_PROBING: + if (acd->ttw == 0) { + acd->state = acd::State::ACD_STATE_PROBING; + arp_acd_probe(acd->ipaddr); + DEBUG_PUTS("PROBING Sent Probe"); + acd->sent_num++; + if (acd->sent_num >= PROBE_NUM) { + acd->state = acd::State::ACD_STATE_ANNOUNCE_WAIT; + acd->sent_num = 0; + acd->ttw = static_cast(ANNOUNCE_WAIT * acd::ACD_TICKS_PER_SECOND); + } else { + acd->ttw = static_cast(random() % (((PROBE_MAX - PROBE_MIN) * acd::ACD_TICKS_PER_SECOND)) + (PROBE_MIN * acd::ACD_TICKS_PER_SECOND)); + } + } + break; + case acd::State::ACD_STATE_ANNOUNCE_WAIT: + case acd::State::ACD_STATE_ANNOUNCING: + if (acd->ttw == 0) { + if (acd->sent_num == 0) { + acd->state = acd::State::ACD_STATE_ANNOUNCING; + acd->num_conflicts = 0; + } + arp_acd_send_announcement(acd->ipaddr); + DEBUG_PUTS("ANNOUNCING Sent Announce"); + acd->ttw = static_cast(ANNOUNCE_INTERVAL * acd::ACD_TICKS_PER_SECOND); + acd->sent_num++; + + if (acd->sent_num >= ANNOUNCE_NUM) { + acd->state = acd::State::ACD_STATE_ONGOING; + acd->sent_num = 0; + acd->ttw = 0; + acd->acd_conflict_callback(acd::Callback::ACD_IP_OK); + } + } + break; + case acd::State::ACD_STATE_RATE_LIMIT: + if (acd->ttw == 0) { + acd_stop(acd); + acd->acd_conflict_callback(acd::Callback::ACD_RESTART_CLIENT); + } + break; + default: + break; + } +} + +static void acd_restart(struct acd::Acd *acd) { + acd->num_conflicts++; + acd->acd_conflict_callback(acd::Callback::ACD_DECLINE); + + if (acd->num_conflicts >= MAX_CONFLICTS) { + acd->state = acd::State::ACD_STATE_RATE_LIMIT; + acd->ttw = static_cast(RATE_LIMIT_INTERVAL * acd::ACD_TICKS_PER_SECOND); + DEBUG_PUTS("rate limiting initiated. too many conflicts"); + } + else { + acd_stop(acd); + acd->acd_conflict_callback(acd::Callback::ACD_RESTART_CLIENT); + } +} + +static void acd_handle_arp_conflict(struct acd::Acd *acd) { + /* RFC5227, 2.4 "Ongoing Address Conflict Detection and Address Defense" + allows three options where: + a) means retreat on the first conflict, + b) allows to keep an already configured address when having only one + conflict in DEFEND_INTERVAL seconds and + c) the host will not give up it's address and defend it indefinitely + + We use option b) when the acd module represents the netif address, since it + helps to improve the chance that one of the two conflicting hosts may be + able to retain its address. while we are flexible enough to help network + performance + + We use option a) when the acd module does not represent the netif address, + since we cannot have the acd module announcing or restarting. This + situation occurs for the LL acd module when a routable address is used on + the netif but the LL address is still open in the background. */ + + if (acd->state == acd::State::ACD_STATE_PASSIVE_ONGOING) { + DEBUG_PUTS("conflict when we are in passive mode -> back off"); + acd_stop(acd); + acd->acd_conflict_callback(acd::Callback::ACD_DECLINE); + } + else { + if (acd->lastconflict > 0) { + DEBUG_PUTS("conflict within DEFEND_INTERVAL -> retreating"); + acd_restart(acd); + } else { + DEBUG_PUTS("we are defending, send ARP Announce"); + arp_acd_send_announcement(acd->ipaddr); + acd->lastconflict = DEFEND_INTERVAL * acd::ACD_TICKS_PER_SECOND; + } + } +} + +static void acd_put_in_passive_mode() { + auto *acd = reinterpret_cast(globals::netif_default.acd); + assert(acd != nullptr); + + switch (acd->state) { + case acd::State::ACD_STATE_OFF: + case acd::State::ACD_STATE_PASSIVE_ONGOING: + default: + /* do nothing */ + break; + case acd::State::ACD_STATE_PROBE_WAIT: + case acd::State::ACD_STATE_PROBING: + case acd::State::ACD_STATE_ANNOUNCE_WAIT: + case acd::State::ACD_STATE_RATE_LIMIT: + acd_stop(acd); + acd->acd_conflict_callback(acd::Callback::ACD_DECLINE); + break; + case acd::State::ACD_STATE_ANNOUNCING: + case acd::State::ACD_STATE_ONGOING: + acd->state = acd::State::ACD_STATE_PASSIVE_ONGOING; + break; + } +} + +/* + * Public interface + */ + +void acd_start(struct acd::Acd *acd, const ip4_addr_t ipaddr) { + DEBUG_ENTRY + assert(acd != nullptr); + + acd->ipaddr.addr = ipaddr.addr; + acd->state = acd::State::ACD_STATE_PROBE_WAIT; + acd->ttw = static_cast(random() % (PROBE_WAIT * acd::ACD_TICKS_PER_SECOND)); + + nTimerId = Hardware::Get()->SoftwareTimerAdd(acd::ACD_TMR_INTERVAL, acd_timer); + assert(nTimerId >= 0); + + DEBUG_EXIT +} + +void acd_stop(struct acd::Acd *acd) { + DEBUG_ENTRY + assert(acd != nullptr); + + acd->state = acd::State::ACD_STATE_OFF; + + assert(nTimerId >= 0); + Hardware::Get()->SoftwareTimerDelete(nTimerId); + nTimerId = -1; + + DEBUG_EXIT +} + +void acd_network_changed_link_down() { + DEBUG_ENTRY + + auto *acd = reinterpret_cast(globals::netif_default.acd); + acd_stop(acd); + + DEBUG_EXIT +} + +void acd_arp_reply(struct t_arp *pArp) { + DEBUG_ENTRY + auto *acd = reinterpret_cast(globals::netif_default.acd); + + switch (acd->state) { + case acd::State::ACD_STATE_OFF: + case acd::State::ACD_STATE_RATE_LIMIT: + default: + break; + case acd::State::ACD_STATE_PROBE_WAIT: + case acd::State::ACD_STATE_PROBING: + case acd::State::ACD_STATE_ANNOUNCE_WAIT: + /* RFC 5227 Section 2.1.1: + * from beginning to after ANNOUNCE_WAIT seconds we have a conflict if + * ip.sender == ipaddr (someone is already using the address) + * OR + * ip.dst == ipaddr && hw.src != own macAddress (someone else is probing it) + */ + if (((memcpy_ip(pArp->arp.sender_ip) == acd->ipaddr.addr)) + || (!(memcpy_ip(pArp->arp.sender_ip) == 0) + && ((memcpy_ip(pArp->arp.target_ip)) == acd->ipaddr.addr) + && (memcmp(pArp->arp.sender_mac, globals::netif_default.hwaddr, ETH_ADDR_LEN) == 0))) + { + DEBUG_PUTS("Probe Conflict detected"); + acd_restart(acd); + } + break; + case acd::State::ACD_STATE_ANNOUNCING: + case acd::State::ACD_STATE_ONGOING: + case acd::State::ACD_STATE_PASSIVE_ONGOING: + /* RFC 5227 Section 2.4: + * in any state we have a conflict if + * ip.sender == ipaddr && hw.src != own macAddress (someone is using our address) + */ + if ((memcpy_ip(pArp->arp.sender_ip) == acd->ipaddr.addr) + && (memcmp(pArp->arp.sender_mac, globals::netif_default.hwaddr, ETH_ADDR_LEN) != 0)) { + DEBUG_PUTS("Conflicting ARP-Packet detected"); + acd_handle_arp_conflict(acd); + } + break; + } + + DEBUG_EXIT +} + +void acd_add(struct acd::Acd *pAcd, acd_conflict_callback_t acd_conflict_callback) { + DEBUG_ENTRY + assert(pAcd != nullptr); + assert(acd_conflict_callback != nullptr); + + pAcd->acd_conflict_callback = acd_conflict_callback; + + auto &netif = globals::netif_default; + netif.acd = pAcd; + + DEBUG_EXIT +} + +void acd_remove(struct acd::Acd *pAcd) { + DEBUG_ENTRY + + assert(pAcd != nullptr); + auto &netif = globals::netif_default; + + if (netif.acd == pAcd) { + netif.acd = nullptr; + + DEBUG_EXIT + return; + } + + DEBUG_EXIT +} + +void acd_netif_ip_addr_changed(const ip4_addr_t old_addr, const ip4_addr_t new_addr) { + if ((old_addr.addr == 0) || (new_addr.addr == 0)) { + return; + } + + auto *acd = reinterpret_cast(globals::netif_default.acd); + + if (acd->ipaddr.addr == old_addr.addr) { + /* Did we change from a LL address to a routable address? */ + if (network::is_linklocal_ip(old_addr.addr) && !network::is_linklocal_ip(new_addr.addr)) { + /* Put the module in passive conflict detection mode */ + acd_put_in_passive_mode(); + } + } +} +} // namespace net diff --git a/lib-network/src/apps/mdns/mdns.cpp b/lib-network/src/net/apps/mdns/mdns.cpp similarity index 88% rename from lib-network/src/apps/mdns/mdns.cpp rename to lib-network/src/net/apps/mdns/mdns.cpp index 8bc029c2..669588ce 100755 --- a/lib-network/src/apps/mdns/mdns.cpp +++ b/lib-network/src/net/apps/mdns/mdns.cpp @@ -2,7 +2,7 @@ * @file mdns.cpp * */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,13 +23,21 @@ * THE SOFTWARE. */ +#if defined (DEBUG_NET_APPS_MDNS) +# if defined (NDEBUG) +# undef NDEBUG +# endif +#endif + #include #include #include #include #include -#include "mdns.h" +#include "net/apps/mdns.h" +#include "net/protocol/ip4.h" +#include "net/protocol/iana.h" #include "network.h" #include "hardware.h" @@ -43,10 +51,6 @@ static constexpr auto SERVICE_RECORDS_MAX = 8; static constexpr auto SERVICE_RECORDS_MAX = MDNS_SERVICE_RECORDS_MAX; #endif -static constexpr uint32_t MULTICAST_MESSAGE_SIZE = 512; ///< The 1987 DNS specification [RFC1035] restricts DNS messages carried by UDP to no more than 512 bytes -static constexpr uint32_t MULTICAST_ADDRESS = network::convert_to_uint(224, 0, 0, 251); -static constexpr uint16_t UDP_PORT = 5353; - static constexpr uint32_t MDNS_RESPONSE_TTL = 3600; ///< (in seconds) static constexpr size_t DOMAIN_MAXLEN = 256; @@ -69,24 +73,6 @@ static constexpr char DOMAIN_OSC[] = { 4 , '_','o','s','c'}; static constexpr char DOMAIN_DDP[] = { 4 , '_','d','d','p'}; static constexpr char DOMAIN_PP[] = { 3 , '_','p','p'}; -enum class Flags1 : uint8_t { - RESPONSE = 0x80, ///< query (0), or a response (1). - OPCODE_STATUS = 0x10, ///< a server status request (STATUS) - OPCODE_IQUERY = 0x08, ///< an inverse query (IQUERY) - OPCODE_STANDARD = 0x00, ///< (RFC 6762, section 18.3) - AUTHORATIVE = 0x04, ///< Authoritative Answer - TRUNC = 0x02, ///< TrunCation - RD = 0x01 ///< If RD is set, it directs the name server to pursue the query recursively. -}; - -enum class Classes : uint16_t { - Internet = 1, Any = 255, Flush = 0x8000 -}; - -enum class Types : uint16_t { - A = 1, PTR = 12, TXT = 16, SRV = 33, ALL = 255 -}; - enum class HostReply : uint32_t { A = 0x01, PTR = 0x02 }; @@ -206,20 +192,12 @@ static constexpr Domain DOMAIN_DNSSD { static ServiceRecord s_ServiceRecords[mdns::SERVICE_RECORDS_MAX]; static HostReply s_HostReplies; static ServiceReply s_ServiceReplies; -static uint8_t s_RecordsData[MULTICAST_MESSAGE_SIZE]; +static uint8_t s_RecordsData[net::dns::MULTICAST_MESSAGE_SIZE]; static bool s_isUnicast; static bool s_bLegacyQuery; } // namespace mdns -static constexpr uint8_t operator| (mdns::Flags1 a, mdns::Flags1 b) { - return static_cast((static_cast(a) | static_cast(b))); -} - -static constexpr uint16_t operator| (mdns::Classes a, mdns::Classes b) { - return static_cast((static_cast(a) | static_cast(b))); -} - static constexpr mdns::HostReply operator| (mdns::HostReply a, mdns::HostReply b) { return static_cast((static_cast(a) | static_cast(b))); } @@ -239,7 +217,7 @@ static constexpr mdns::ServiceReply operator& (mdns::ServiceReply a, mdns::Servi int32_t MDNS::s_nHandle; uint32_t MDNS::s_nRemoteIp; uint16_t MDNS::s_nRemotePort; -uint16_t MDNS::s_nBytesReceived; +uint32_t MDNS::s_nBytesReceived; uint8_t *MDNS::s_pReceiveBuffer; MDNS *MDNS::s_pThis; @@ -303,7 +281,7 @@ static void create_reverse_domain(Domain &domain) { auto nIp = Network::Get()->GetIp(); const auto *pIp = reinterpret_cast(&nIp); - for (int32_t i = network::IP_SIZE - 1; i >= 0; i--) { + for (int32_t i = IPv4_ADDR_LEN - 1; i >= 0; i--) { char buffer[3]; uint32_t nLength = 1; @@ -439,12 +417,12 @@ static uint8_t *put_domain_name_as_labels(uint8_t *ptr, Domain const &domain) { return ptr; } -static uint8_t *add_question(uint8_t *pDestination, const Domain& domain, const Types type, const bool bFlush) { +static uint8_t *add_question(uint8_t *pDestination, const Domain& domain, const net::dns::RRType type, const bool bFlush) { auto *pDst = put_domain_name_as_labels(pDestination, domain); *reinterpret_cast(pDst) = __builtin_bswap16(static_cast(type)); pDst += 2; - *reinterpret_cast(pDst) = __builtin_bswap16((bFlush ? Classes::Flush : static_cast(0)) | Classes::Internet); + *reinterpret_cast(pDst) = __builtin_bswap16((bFlush ? net::dns::RRClass::RRCLASS_FLUSH : static_cast(0)) | net::dns::RRClass::RRCLASS_INTERNET); pDst += 2; return pDst; @@ -456,7 +434,7 @@ static uint32_t add_answer_srv(mdns::ServiceRecord const& serviceRecord, uint8_t Domain domain; create_service_domain(domain, serviceRecord, true); - auto *pDst = add_question(pDestination, domain, Types::SRV, true); + auto *pDst = add_question(pDestination, domain, net::dns::RRType::RRTYPE_SRV, true); *reinterpret_cast(pDst) = __builtin_bswap32(nTTL); pDst += 4; @@ -483,7 +461,7 @@ static uint32_t add_answer_txt(mdns::ServiceRecord const& serviceRecord, uint8_t Domain domain; create_service_domain(domain, serviceRecord, true); - auto *pDst = add_question(pDestination, domain, Types::TXT, true); + auto *pDst = add_question(pDestination, domain, net::dns::RRType::RRTYPE_TXT, true); *reinterpret_cast(pDst) = __builtin_bswap32(nTTL); pDst += 4; @@ -513,7 +491,7 @@ static uint32_t add_answer_ptr(mdns::ServiceRecord const& serviceRecord, uint8_t Domain domain; create_service_domain(domain, serviceRecord, false); - auto *pDst = add_question(pDestination, domain, Types::PTR, false); + auto *pDst = add_question(pDestination, domain, net::dns::RRType::RRTYPE_PTR, false); *reinterpret_cast(pDst) = __builtin_bswap32(nTTL); pDst += 4; @@ -533,7 +511,7 @@ static uint32_t add_answer_ptr(mdns::ServiceRecord const& serviceRecord, uint8_t static uint32_t add_answer_dnsd_ptr(mdns::ServiceRecord const& serviceRecord, uint8_t *pDestination, const uint32_t nTTL) { DEBUG_ENTRY - auto *pDst = add_question(pDestination, DOMAIN_DNSSD, Types::PTR, false); + auto *pDst = add_question(pDestination, DOMAIN_DNSSD, net::dns::RRType::RRTYPE_PTR, false); *reinterpret_cast(pDst) = __builtin_bswap32(nTTL); pDst += 4; @@ -558,7 +536,7 @@ static uint32_t add_answer_a(uint8_t *pDestination, const uint32_t nTTL) { Domain domain; create_host_domain(domain); - auto *pDst = add_question(pDestination, domain, Types::A, true); + auto *pDst = add_question(pDestination, domain, net::dns::RRType::RRTYPE_A, true); *reinterpret_cast(pDst) = __builtin_bswap32(nTTL); pDst += 4; @@ -578,7 +556,7 @@ static uint32_t add_answer_hostv4_ptr(uint8_t *pDestination, const uint32_t nTTL Domain domain; create_reverse_domain(domain); - auto *pDst = add_question(pDestination, domain, Types::PTR, true); + auto *pDst = add_question(pDestination, domain, net::dns::RRType::RRTYPE_PTR, true); *reinterpret_cast(pDst) = __builtin_bswap32(nTTL); pDst += 4; @@ -675,14 +653,14 @@ void MDNS::SendAnswerLocalIpAddress(const uint16_t nTransActionID, const uint32_ DEBUG_ENTRY uint32_t nAnswers = 0; - uint8_t *pDst = reinterpret_cast(&s_RecordsData) + sizeof(struct Header); + uint8_t *pDst = reinterpret_cast(&s_RecordsData) + sizeof(struct net::dns::Header); #if defined (CONFIG_MDNS_DOMAIN_REVERSE) if ((HostReply::PTR & s_HostReplies) == HostReply::PTR) { if (s_bLegacyQuery) { Domain domain; create_reverse_domain(domain); - pDst = add_question(pDst, domain, Types::PTR, false); + pDst = add_question(pDst, domain, net::dns::RRType::RRTYPE_PTR, false); } } #endif @@ -698,10 +676,10 @@ void MDNS::SendAnswerLocalIpAddress(const uint16_t nTransActionID, const uint32_ } #endif - auto *pHeader = reinterpret_cast(&s_RecordsData); + auto *pHeader = reinterpret_cast< net::dns::Header *>(&s_RecordsData); pHeader->xid = nTransActionID; - pHeader->nFlag1 = Flags1::RESPONSE | Flags1::AUTHORATIVE; + pHeader->nFlag1 = net::dns::Flag1::FLAG1_RESPONSE | net::dns::Flag1::FLAG1_AUTHORATIVE; pHeader->nFlag2 = 0; #if defined (CONFIG_MDNS_DOMAIN_REVERSE) pHeader->nQueryCount = __builtin_bswap16(static_cast(s_bLegacyQuery)); @@ -726,10 +704,10 @@ MDNS::MDNS() { record.services = Services::LAST_NOT_USED; } - s_nHandle = Network::Get()->Begin(mdns::UDP_PORT); + s_nHandle = Network::Get()->Begin(net::iana::IANA_PORT_MDNS); assert(s_nHandle != -1); - Network::Get()->JoinGroup(s_nHandle, mdns::MULTICAST_ADDRESS); + Network::Get()->JoinGroup(s_nHandle, net::dns::MULTICAST_ADDRESS); Network::Get()->SetDomainName(&DOMAIN_LOCAL[1]); SendAnnouncement(MDNS_RESPONSE_TTL); @@ -748,15 +726,15 @@ MDNS::~MDNS() { } } - Network::Get()->LeaveGroup(s_nHandle, mdns::MULTICAST_ADDRESS); - Network::Get()->End(mdns::UDP_PORT); + Network::Get()->LeaveGroup(s_nHandle, net::dns::MULTICAST_ADDRESS); + Network::Get()->End(net::iana::IANA_PORT_MDNS); s_nHandle = -1; } void MDNS::SendAnnouncement(const uint32_t nTTL) { DEBUG_ENTRY - s_nRemotePort = mdns::UDP_PORT; //FIXME Hack ;-) + s_nRemotePort = net::iana::IANA_PORT_MDNS; //FIXME Hack ;-) s_HostReplies = HostReply::A; SendAnswerLocalIpAddress(0, nTTL); @@ -774,7 +752,7 @@ void MDNS::SendAnnouncement(const uint32_t nTTL) { DEBUG_EXIT } -bool MDNS::AddServiceRecord(const char *pName, const mdns::Services services, const char *pTextContent, const uint16_t nPort) { +bool MDNS::ServiceRecordAdd(const char *pName, const mdns::Services services, const char *pTextContent, const uint16_t nPort) { DEBUG_ENTRY assert(services < mdns::Services::LAST_NOT_USED); @@ -812,7 +790,7 @@ bool MDNS::AddServiceRecord(const char *pName, const mdns::Services services, co record.nTextContentLength = static_cast(nLength); } - s_nRemotePort = mdns::UDP_PORT; //FIXME Hack ;-) + s_nRemotePort = net::iana::IANA_PORT_MDNS; //FIXME Hack ;-) s_ServiceReplies = ServiceReply::TYPE_PTR | ServiceReply::NAME_PTR @@ -828,9 +806,34 @@ bool MDNS::AddServiceRecord(const char *pName, const mdns::Services services, co return false; } -void MDNS::SendTo(const uint16_t nLength) { +bool MDNS::ServiceRecordDelete(const mdns::Services service) { + DEBUG_ENTRY + assert(service < mdns::Services::LAST_NOT_USED); + + for (auto &record : s_ServiceRecords) { + if (record.services == service) { + SendMessage(record, 0, 0); + + if (record.pName != nullptr) { + delete[] record.pName; + } + + if (record.pTextContent != nullptr) { + delete[] record.pTextContent; + } + + DEBUG_EXIT + return true; + } + } + + DEBUG_EXIT + return false; +} + +void MDNS::SendTo(const uint32_t nLength) { if (!s_isUnicast) { - Network::Get()->SendTo(s_nHandle, s_RecordsData, nLength, mdns::MULTICAST_ADDRESS, mdns::UDP_PORT); + Network::Get()->SendTo(s_nHandle, s_RecordsData, nLength, net::dns::MULTICAST_ADDRESS, net::iana::IANA_PORT_MDNS); return; } @@ -841,7 +844,7 @@ void MDNS::SendMessage(mdns::ServiceRecord const& serviceRecord, const uint16_t DEBUG_ENTRY uint32_t nAnswers = 0; - auto *pDst = reinterpret_cast(&s_RecordsData) + sizeof(struct Header); + auto *pDst = reinterpret_cast(&s_RecordsData) + sizeof(struct net::dns::Header); if ((s_ServiceReplies & ServiceReply::TYPE_PTR) == ServiceReply::TYPE_PTR) { nAnswers++; @@ -865,10 +868,10 @@ void MDNS::SendMessage(mdns::ServiceRecord const& serviceRecord, const uint16_t pDst += add_answer_a(pDst, nTT); - auto *pHeader = reinterpret_cast
(&s_RecordsData); + auto *pHeader = reinterpret_cast(&s_RecordsData); pHeader->xid = nTransActionID; - pHeader->nFlag1 = Flags1::RESPONSE | Flags1::AUTHORATIVE; + pHeader->nFlag1 = net::dns::Flag1::FLAG1_RESPONSE | net::dns::Flag1::FLAG1_AUTHORATIVE; pHeader->nFlag2 = 0; pHeader->nQueryCount = 0; pHeader->nAnswerCount = __builtin_bswap16(static_cast(nAnswers)); @@ -886,12 +889,12 @@ void MDNS::HandleQuestions(const uint32_t nQuestions) { DEBUG_PRINTF("nQuestions=%u", nQuestions); s_HostReplies = static_cast(0); - s_isUnicast = (s_nRemotePort != mdns::UDP_PORT); + s_isUnicast = (s_nRemotePort != net::iana::IANA_PORT_MDNS); s_bLegacyQuery = s_isUnicast && (nQuestions == 1); const auto nTransactionID = s_bLegacyQuery ? *reinterpret_cast(&s_pReceiveBuffer[0]) : static_cast(0); - uint32_t nOffset = sizeof(struct Header); + uint32_t nOffset = sizeof(struct net::dns::Header); for (uint32_t i = 0; i < nQuestions; i++) { Domain resourceDomain; @@ -905,10 +908,10 @@ void MDNS::HandleQuestions(const uint32_t nQuestions) { resourceDomain.nLength = static_cast(pResult - &s_pReceiveBuffer[nOffset]); nOffset += resourceDomain.nLength; - const auto nType = static_cast(__builtin_bswap16(*reinterpret_cast(&s_pReceiveBuffer[nOffset]))); + const auto nType = static_cast(__builtin_bswap16(*reinterpret_cast(&s_pReceiveBuffer[nOffset]))); nOffset += 2; - const auto nClass = static_cast(__builtin_bswap16(*reinterpret_cast(&s_pReceiveBuffer[nOffset])) & 0x7F); + const auto nClass = static_cast(__builtin_bswap16(*reinterpret_cast(&s_pReceiveBuffer[nOffset])) & 0x7F); nOffset += 2; #ifndef NDEBUG @@ -916,7 +919,7 @@ void MDNS::HandleQuestions(const uint32_t nQuestions) { printf(" ==> Type : %d, Class: %d\n", static_cast(nType), static_cast(nClass)); #endif - if ((nClass != Classes::Internet) && (nClass != Classes::Any)) { + if ((nClass != net::dns::RRClass::RRCLASS_INTERNET) && (nClass != net::dns::RRClass::RRCLASS_ANY)) { continue; } @@ -926,7 +929,7 @@ void MDNS::HandleQuestions(const uint32_t nQuestions) { Domain domainHost; - if ((nType == Types::A) || (nType == Types::ALL)) { + if ((nType == net::dns::RRType::RRTYPE_A) || (nType == net::dns::RRType::RRTYPE_ALL)) { DEBUG_PUTS(""); create_host_domain(domainHost); @@ -936,7 +939,7 @@ void MDNS::HandleQuestions(const uint32_t nQuestions) { } #if defined (CONFIG_MDNS_DOMAIN_REVERSE) - if (nType == Types::PTR || nType == Types::ALL) { + if (nType == net::dns::RRType::RRTYPE_PTR || nType == net::dns::RRType::RRTYPE_ALL) { DEBUG_PUTS(""); create_reverse_domain(domainHost); @@ -956,7 +959,7 @@ void MDNS::HandleQuestions(const uint32_t nQuestions) { s_ServiceReplies = static_cast(0); Domain serviceDomain; - if (nType == Types::PTR || nType == Types::ALL) { + if (nType == net::dns::RRType::RRTYPE_PTR || nType == net::dns::RRType::RRTYPE_ALL) { if (DOMAIN_DNSSD == resourceDomain) { s_ServiceReplies = s_ServiceReplies | ServiceReply::TYPE_PTR; } @@ -971,11 +974,11 @@ void MDNS::HandleQuestions(const uint32_t nQuestions) { create_service_domain(serviceDomain, record, true); if (serviceDomain == resourceDomain) { - if ((nType == Types::SRV) || (nType == Types::ALL)) { + if ((nType == net::dns::RRType::RRTYPE_SRV) || (nType == net::dns::RRType::RRTYPE_ALL)) { s_ServiceReplies = s_ServiceReplies | ServiceReply::SRV; } - if ((nType == Types::TXT) || (nType == Types::ALL)) { + if ((nType == net::dns::RRType::RRTYPE_TXT) || (nType == net::dns::RRType::RRTYPE_ALL)) { s_ServiceReplies = s_ServiceReplies | ServiceReply::TXT; } } diff --git a/lib-network/src/net/apps/ntp/gd32/ptp/net_ptp.cpp b/lib-network/src/net/apps/ntp/gd32/ptp/net_ptp.cpp new file mode 100644 index 00000000..4f69e630 --- /dev/null +++ b/lib-network/src/net/apps/ntp/gd32/ptp/net_ptp.cpp @@ -0,0 +1,484 @@ +/** + * @file net_ptp.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/** + * https://www.ietf.org/archive/id/draft-ietf-ntp-interleaved-modes-07.html#name-interleaved-client-server-m + */ +/* +Server t2 t3 t6 t7 t10 t11 + -----+----+----------------+----+----------------+----+----- + / \ / \ / \ +Client / \ / \ / \ + --+----------+----------+----------+----------+----------+-- + t1 t4 t5 t8 t9 t12 + +Mode: B B I I I I + +----+ +----+ +----+ +----+ +----+ +----+ +Org | 0 | | t1~| | t2 | | t4 | | t6 | | t8 | +Rx | 0 | | t2 | | t4 | | t6 | | t8 | |t10 | +Tx | t1~| | t3~| | t1 | | t3 | | t5 | | t7 | + +----+ +----+ +----+ +----+ +----+ +----+ + +T1 - local transmit timestamp of the latest request (t5) +T2 - remote receive timestamp from the latest response (t6) +T3 - remote transmit timestamp from the latest response (t3) +T4 - local receive timestamp of the previous response (t4) + */ + +#undef NDEBUG + +#if !defined (CONFIG_ENET_ENABLE_PTP) +# error +#endif +#if defined (ENABLE_NTP_CLIENT) +# error +#endif + +#pragma GCC push_options +#pragma GCC optimize ("O2") +#pragma GCC optimize ("no-tree-loop-distribute-patterns") + +#include +#include +#include +#include + +#include "hardware.h" +#include "network.h" +#include "networkparams.h" + +#include "net/protocol/ntp.h" + +#include "gd32_ptp.h" + +#include "debug.h" + +namespace net { +namespace globals { +extern uint32_t ptpTimestamp[2]; +} // namespace globals + +#define _NTPFRAC_(x) ( 4294U*static_cast(x) + ( (1981U*static_cast(x))>>11 ) + ((2911U*static_cast(x))>>28) ) +#define NTPFRAC(x) _NTPFRAC_(x / 1000) + +/** + * The reverse of the above, needed if we want to set our microsecond + * clock (via clock_settime) based on the incoming time in NTP format. + * Basically exact. + */ +#define USEC(x) ( ( (x) >> 12 ) - 759 * ( ( ( (x) >> 10 ) + 32768 ) >> 16 ) ) + +static constexpr uint32_t TIMEOUT_SECONDS = 3; +static constexpr uint8_t POLL_POWER = 3; +static constexpr uint32_t POLL_SECONDS = (1U << POLL_POWER); + +struct ntpClient { + uint32_t nServerIp; + int32_t nHandle; + ntp::Packet *pReply; + uint32_t nMillisRequest; + uint32_t nMillisLastPoll; + ntp::Status status; + ntp::Packet Request; + ntp::TimeStamp T1; // time request sent by client + ntp::TimeStamp T2; // time request received by server + ntp::TimeStamp T3; // time reply sent by server + ntp::TimeStamp T4; // time reply received by client + ntp::TimeStamp cookieBasic; + struct { + ntp::TimeStamp previousReceive; + ntp::TimeStamp dst; // destination timestamp + ntp::TimeStamp sentA; + ntp::TimeStamp sentB; + int32_t x; // interleave switch + uint32_t missedResponses; +#ifndef NDEBUG + ntp::Modes mode; +#endif + } state; +}; + +static ntpClient s_ntpClient; +static uint16_t s_id; +static constexpr uint16_t REQUEST_SIZE = sizeof s_ntpClient.Request; + +static void print(const char *pText, const struct ntp::TimeStamp *pNtpTime) { +#ifndef NDEBUG + const auto nSeconds = static_cast(pNtpTime->nSeconds - ntp::JAN_1970); + const auto *pTm = localtime(&nSeconds); + printf("%s %02d:%02d:%02d.%06d %04d [%u][0x%.8x]\n", pText, pTm->tm_hour, pTm->tm_min, pTm->tm_sec, USEC(pNtpTime->nFraction), pTm->tm_year + 1900, pNtpTime->nSeconds, pNtpTime->nFraction); +#endif +} + +void ptp_init() { + DEBUG_ENTRY + + memset(&s_ntpClient, 0, sizeof(struct ntpClient)); + s_ntpClient.state.previousReceive.nSeconds = ntp::JAN_1970; + s_ntpClient.state.dst.nSeconds = ntp::JAN_1970; + s_ntpClient.state.sentA.nSeconds = ntp::JAN_1970; + s_ntpClient.state.sentB.nSeconds = ntp::JAN_1970; + + s_ntpClient.state.missedResponses = 4; + + NetworkParams networkParams; + networkParams.Load(); + + s_ntpClient.nServerIp = networkParams.GetNtpServer(); + + if (s_ntpClient.nServerIp == 0) { + s_ntpClient.status = ntp::Status::STOPPED; + DEBUG_EXIT + return; + } + + struct timeval tv; + gettimeofday(&tv, nullptr); + srandom(static_cast(tv.tv_sec ^ tv.tv_usec)); + + s_ntpClient.Request.LiVnMode = ntp::VERSION | ntp::MODE_CLIENT; + s_ntpClient.Request.Poll = POLL_POWER; + + s_ntpClient.state.x = 1; + + s_ntpClient.nHandle = Network::Get()->Begin(ntp::UDP_PORT); + assert(s_ntpClient.nHandle != -1); + + s_ntpClient.status = ntp::Status::IDLE; + s_ntpClient.nMillisLastPoll = Hardware::Get()->Millis() - (1000U * POLL_SECONDS); + + DEBUG_PRINTF("Poll: %u", POLL_SECONDS); + DEBUG_EXIT +} + +void ptp_ntp_set_server_ip(const uint32_t nServerIp) { + s_ntpClient.nServerIp = nServerIp; +} + +void ptp_handle([[maybe_unused]] const uint8_t *pBuffer, [[maybe_unused]] const uint32_t nLength) { + /* Can only be used for PTP level 2 messages */ +} + +/** + * The interleaved client/server mode is similar to the basic client/ server mode. + * The difference between the two modes is in the values saved to the origin and transmit timestamp fields. + */ + +static bool send() { + s_ntpClient.state.missedResponses++; + + /** + * The first request from a client is always in the basic mode and so is the server response. + * It has a zero origin timestamp and zero receive timestamp. + * Only when the client receives a valid response from the server, + * it will be able to send a request in the interleaved mode + */ + if (s_ntpClient.state.missedResponses > 4) { + s_ntpClient.cookieBasic.nSeconds = random(); + s_ntpClient.cookieBasic.nFraction = 0; + + s_ntpClient.Request.OriginTimestamp_s = 0; + s_ntpClient.Request.OriginTimestamp_f = 0; + + s_ntpClient.Request.ReceiveTimestamp_s = 0; + s_ntpClient.Request.ReceiveTimestamp_f = 0; + + /** + * The origin timestamp is a cookie which is used to detect that a received packet + * is a response to the last packet sent in the other direction of the association. + */ + s_ntpClient.Request.TransmitTimestamp_s = __builtin_bswap32(s_ntpClient.cookieBasic.nSeconds); + s_ntpClient.Request.TransmitTimestamp_f = __builtin_bswap32(s_ntpClient.cookieBasic.nFraction); + } else { + /** + * A client request in the interleaved mode has an origin timestamp equal to + * the receive timestamp from the last valid server response. + */ + s_ntpClient.Request.OriginTimestamp_s = __builtin_bswap32(s_ntpClient.state.dst.nSeconds); + s_ntpClient.Request.OriginTimestamp_f = __builtin_bswap32(s_ntpClient.state.dst.nFraction); + + s_ntpClient.Request.ReceiveTimestamp_s = __builtin_bswap32(s_ntpClient.state.previousReceive.nSeconds); + s_ntpClient.Request.ReceiveTimestamp_f = __builtin_bswap32(s_ntpClient.state.previousReceive.nFraction); + + if (s_ntpClient.state.x > 0) { + s_ntpClient.Request.TransmitTimestamp_s = __builtin_bswap32(s_ntpClient.state.sentB.nSeconds); + s_ntpClient.Request.TransmitTimestamp_f = __builtin_bswap32(s_ntpClient.state.sentB.nFraction); + } else { + s_ntpClient.Request.TransmitTimestamp_s = __builtin_bswap32(s_ntpClient.state.sentA.nSeconds); + s_ntpClient.Request.TransmitTimestamp_f = __builtin_bswap32(s_ntpClient.state.sentA.nFraction); + } + } + + Network::Get()->SendToTimestamp(s_ntpClient.nHandle, &s_ntpClient.Request, REQUEST_SIZE, s_ntpClient.nServerIp, ntp::UDP_PORT); + +#ifndef NDEBUG + printf("Request: org=%.8x%.8x rx=%.8x%.8x tx=%.8x%.8x\n", + __builtin_bswap32(s_ntpClient.Request.OriginTimestamp_s), __builtin_bswap32(s_ntpClient.Request.OriginTimestamp_f), + __builtin_bswap32(s_ntpClient.Request.ReceiveTimestamp_s), __builtin_bswap32(s_ntpClient.Request.ReceiveTimestamp_f), + __builtin_bswap32(s_ntpClient.Request.TransmitTimestamp_s), __builtin_bswap32(s_ntpClient.Request.TransmitTimestamp_f)); +#endif + + if (s_ntpClient.state.x > 0) { + s_ntpClient.state.sentA.nSeconds = net::globals::ptpTimestamp[1] + ntp::JAN_1970; + s_ntpClient.state.sentA.nFraction = NTPFRAC(gd32::ptp_subsecond_2_nanosecond(net::globals::ptpTimestamp[0])); + } else { + s_ntpClient.state.sentB.nSeconds = net::globals::ptpTimestamp[1] + ntp::JAN_1970; + s_ntpClient.state.sentB.nFraction = NTPFRAC(gd32::ptp_subsecond_2_nanosecond(net::globals::ptpTimestamp[0])); + } + + s_ntpClient.state.x = -s_ntpClient.state.x; + s_id++; + + return true; +} + +static void difference(const ntp::TimeStamp& Start, const ntp::TimeStamp& Stop, int32_t& nDiffSeconds, int32_t& nDiffNanoSeconds) { + gd32::ptp::time_t r; + const gd32::ptp::time_t x = {.tv_sec = static_cast(Stop.nSeconds), .tv_nsec = static_cast(USEC(Stop.nFraction) * 1000)}; + const gd32::ptp::time_t y = {.tv_sec = static_cast(Start.nSeconds), .tv_nsec = static_cast(USEC(Start.nFraction) * 1000)}; + gd32::sub_time(&r, &x, &y); + + nDiffSeconds = r.tv_sec; + nDiffNanoSeconds = r.tv_nsec; +} + +static void update_ptp_time() { + int32_t nDiffSeconds1, nDiffNanoSeconds1; + difference(s_ntpClient.T1, s_ntpClient.T2, nDiffSeconds1, nDiffNanoSeconds1); + + int32_t nDiffSeconds2, nDiffNanoSeconds2; + difference(s_ntpClient.T4, s_ntpClient.T3, nDiffSeconds2, nDiffNanoSeconds2); + + auto nOffsetSeconds = static_cast(nDiffSeconds1) + static_cast(nDiffSeconds2); + auto nOffsetNanoSeconds = static_cast(nDiffNanoSeconds1) + static_cast(nDiffNanoSeconds2); + + const int32_t nOffsetSecondsAverage = nOffsetSeconds / 2; + const int32_t nOffsetNanosverage = nOffsetNanoSeconds / 2; + + gd32::ptp::time_t ptpOffset = {.tv_sec = nOffsetSecondsAverage, .tv_nsec = nOffsetNanosverage}; + gd32::normalize_time(&ptpOffset); + gd32_ptp_update_time(&ptpOffset); + + gd32::ptp::ptptime ptp_get; + gd32_ptp_get_time(&ptp_get); + + s_ntpClient.Request.ReferenceTimestamp_s = __builtin_bswap32(static_cast(ptp_get.tv_sec) + ntp::JAN_1970); + s_ntpClient.Request.ReferenceTimestamp_f = __builtin_bswap32(NTPFRAC(ptp_get.tv_nsec)); + +#ifndef NDEBUG + /** + * Network delay calculation + */ + gd32::ptp::time_t diff1; + gd32::ptp::time_t diff2; + + if (s_ntpClient.state.mode == ntp::Modes::BASIC) { + difference(s_ntpClient.T1, s_ntpClient.T4, diff1.tv_sec, diff1.tv_nsec); + difference(s_ntpClient.T2, s_ntpClient.T3, diff2.tv_sec, diff2.tv_nsec); + } else { + ntp::TimeStamp start; + start.nSeconds = __builtin_bswap32(s_ntpClient.Request.TransmitTimestamp_s); + start.nFraction = __builtin_bswap32(s_ntpClient.Request.TransmitTimestamp_f); + ntp::TimeStamp stop; + stop.nSeconds = __builtin_bswap32(s_ntpClient.Request.ReceiveTimestamp_s); + stop.nFraction = __builtin_bswap32(s_ntpClient.Request.ReceiveTimestamp_f); + difference(start, stop, diff1.tv_sec, diff1.tv_nsec); + + const auto *const pReply = s_ntpClient.pReply; + start.nSeconds = __builtin_bswap32(s_ntpClient.Request.OriginTimestamp_s); + start.nFraction = __builtin_bswap32(s_ntpClient.Request.OriginTimestamp_f); + stop.nSeconds = __builtin_bswap32(pReply->TransmitTimestamp_s); + stop.nFraction = __builtin_bswap32(pReply->TransmitTimestamp_f); + difference(start, stop, diff2.tv_sec, diff2.tv_nsec); + } + + gd32::ptp::time_t ptpDelay; + gd32::sub_time(&ptpDelay, &diff1, &diff2); + + char sign = '+'; + + if (ptpOffset.tv_sec < 0) { + ptpOffset.tv_sec = -ptpOffset.tv_sec; + sign = '-'; + } + + if (ptpOffset.tv_nsec < 0) { + ptpOffset.tv_nsec = -ptpOffset.tv_nsec; + sign = '-'; + } + + printf(" %s : offset=%c%d.%09d delay=%d.%09d\n", + s_ntpClient.state.mode == ntp::Modes::BASIC ? "Basic" : "Interleaved", + sign, ptpOffset.tv_sec, ptpOffset.tv_nsec, + ptpDelay.tv_sec, ptpDelay.tv_nsec); +#endif +} + +/** + * Two of the tests are modified for the interleaved mode: + * + * 1. The check for duplicate packets SHOULD compare both receive and + * transmit timestamps in order to not drop a valid response in the interleaved mode if + * it follows a response in the basic mode and they contain the same transmit timestamp. + * 2. The check for bogus packets SHOULD compare the origin timestamp with both transmit and + * receive timestamps from the request. + * If the origin timestamp is equal to the transmit timestamp, the response is in the basic mode. + * If the origin timestamp is equal to the receive timestamp, the response is in the interleaved mode. + */ + +static bool receive() { + uint32_t nFromIp; + uint16_t nFromPort; + + const auto nBytesReceived = Network::Get()->RecvFrom(s_ntpClient.nHandle, const_cast(reinterpret_cast(&s_ntpClient.pReply)), &nFromIp, &nFromPort); + + if (__builtin_expect((nBytesReceived != sizeof(struct ntp::Packet)), 1)) { + return false; + } + + if (__builtin_expect((nFromIp != s_ntpClient.nServerIp), 0)) { + DEBUG_PUTS("nFromIp != s_ntpClient.nServerIp"); + return false; + } + + if (s_ntpClient.state.missedResponses == 0) { + DEBUG_PUTS("Ignore duplicates"); + return false; + } + + return true; +} + +static void process() { + const auto *const pReply = s_ntpClient.pReply; +#ifndef NDEBUG + printf("Response: org=%.8x%.8x rx=%.8x%.8x tx=%.8x%.8x\n", + __builtin_bswap32(pReply->OriginTimestamp_s), __builtin_bswap32(pReply->OriginTimestamp_f), + __builtin_bswap32(pReply->ReceiveTimestamp_s), __builtin_bswap32(pReply->ReceiveTimestamp_f), + __builtin_bswap32(pReply->TransmitTimestamp_s), __builtin_bswap32(pReply->TransmitTimestamp_f)); +#endif + /** + * If the origin timestamp is equal to the transmit timestamp, + * the response is in the basic mode. + */ + if ((pReply->OriginTimestamp_s == s_ntpClient.Request.TransmitTimestamp_s) && (pReply->OriginTimestamp_f == s_ntpClient.Request.TransmitTimestamp_f)) { + if (s_ntpClient.state.x < 0) { + s_ntpClient.T1.nSeconds = s_ntpClient.state.sentA.nSeconds; + s_ntpClient.T1.nFraction = s_ntpClient.state.sentA.nFraction; + } else { + s_ntpClient.T1.nSeconds = s_ntpClient.state.sentB.nSeconds; + s_ntpClient.T1.nFraction = s_ntpClient.state.sentB.nFraction; + } + + s_ntpClient.T4.nSeconds = net::globals::ptpTimestamp[1] + ntp::JAN_1970; + s_ntpClient.T4.nFraction = NTPFRAC(gd32::ptp_subsecond_2_nanosecond(net::globals::ptpTimestamp[0])); +#ifndef NDEBUG + s_ntpClient.state.mode = ntp::Modes::BASIC; +#endif + } else + /** + * If the origin timestamp is equal to the receive timestamp, + * the response is in the interleaved mode. + */ + if ((pReply->OriginTimestamp_s == s_ntpClient.Request.ReceiveTimestamp_s) && (pReply->OriginTimestamp_f == s_ntpClient.Request.ReceiveTimestamp_f)) { + if (s_ntpClient.state.x > 0) { + s_ntpClient.T1.nSeconds = s_ntpClient.state.sentB.nSeconds; + s_ntpClient.T1.nFraction = s_ntpClient.state.sentB.nFraction; + } else { + s_ntpClient.T1.nSeconds = s_ntpClient.state.sentA.nSeconds; + s_ntpClient.T1.nFraction = s_ntpClient.state.sentA.nFraction; + } + + s_ntpClient.T4.nSeconds = s_ntpClient.state.previousReceive.nSeconds; + s_ntpClient.T4.nFraction = s_ntpClient.state.previousReceive.nFraction; +#ifndef NDEBUG + s_ntpClient.state.mode = ntp::Modes::INTERLEAVED; +#endif + } else { + DEBUG_PUTS("INVALID RESPONSE"); + return; + } + + s_ntpClient.T2.nSeconds = __builtin_bswap32(pReply->ReceiveTimestamp_s); + s_ntpClient.T2.nFraction = __builtin_bswap32(pReply->ReceiveTimestamp_f); + + s_ntpClient.T3.nSeconds = __builtin_bswap32(pReply->TransmitTimestamp_s); + s_ntpClient.T3.nFraction = __builtin_bswap32(pReply->TransmitTimestamp_f); + + s_ntpClient.state.dst.nSeconds = __builtin_bswap32(pReply->ReceiveTimestamp_s); + s_ntpClient.state.dst.nFraction = __builtin_bswap32(pReply->ReceiveTimestamp_f); + + s_ntpClient.state.previousReceive.nSeconds = net::globals::ptpTimestamp[1] + ntp::JAN_1970; + s_ntpClient.state.previousReceive.nFraction = NTPFRAC(gd32::ptp_subsecond_2_nanosecond(net::globals::ptpTimestamp[0])); + + update_ptp_time(); + + s_ntpClient.state.missedResponses = 0; + + print("T1: ", &s_ntpClient.T1); + print("T2: ", &s_ntpClient.T2); + print("T3: ", &s_ntpClient.T3); + print("T4: ", &s_ntpClient.T4); +} + +void ptp_run() { + if (s_ntpClient.status == ntp::Status::STOPPED) { + return; + } + + if ((s_ntpClient.status == ntp::Status::IDLE) || (s_ntpClient.status == ntp::Status::FAILED)) { + const auto nMillis = Hardware::Get()->Millis(); + if (__builtin_expect(((nMillis - s_ntpClient.nMillisLastPoll) > (1000U * POLL_SECONDS)), 0)) { + if (send()) { + s_ntpClient.status = ntp::Status::WAITING; + s_ntpClient.nMillisRequest = nMillis; + } else { + s_ntpClient.status = ntp::Status::FAILED; + s_ntpClient.nMillisLastPoll = nMillis; + } + } + return; + } + + if (s_ntpClient.status == ntp::Status::WAITING) { + if (__builtin_expect((!receive()), 1)) { + if (__builtin_expect(((Hardware::Get()->Millis() - s_ntpClient.nMillisRequest) > (1000U * TIMEOUT_SECONDS)), 0)) { + s_ntpClient.status = ntp::Status::FAILED; + DEBUG_PUTS("FAILED"); + } + return; + } + + if (__builtin_expect(((s_ntpClient.pReply->LiVnMode & ntp::MODE_SERVER) == ntp::MODE_SERVER), 1)) { + s_ntpClient.nMillisLastPoll = Hardware::Get()->Millis(); + process(); + } else { + DEBUG_PUTS("INVALID REPLY"); + } + + s_ntpClient.status = ntp::Status::IDLE; + } +} +} // namespace net diff --git a/lib-network/src/net/apps/ntp/ntpclient.cpp b/lib-network/src/net/apps/ntp/ntpclient.cpp new file mode 100755 index 00000000..4db22dce --- /dev/null +++ b/lib-network/src/net/apps/ntp/ntpclient.cpp @@ -0,0 +1,263 @@ +/** + * @file ntpclient.cpp + * + */ +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#if defined (DEBUG_NTP_CLIENT) +# if defined (NDEBUG) +# undef NDEBUG +# endif +#endif + +#include +#include +#include +#include +#include + +#include "net/apps/ntpclient.h" +#include "net/protocol/ntp.h" +#include "utc.h" + +#include "network.h" +#include "networkparams.h" +#include "hardware.h" + +#include "debug.h" + +/* How to multiply by 4294.967296 quickly (and not quite exactly) + * without using floating point or greater than 32-bit integers. + * If you want to fix the last 12 microseconds of error, add in + * (2911*(x))>>28) + */ +#define NTPFRAC(x) ( 4294U*static_cast(x) + ( (1981U*static_cast(x))>>11 ) + ((2911U*static_cast(x))>>28) ) + +/* The reverse of the above, needed if we want to set our microsecond + * clock (via clock_settime) based on the incoming time in NTP format. + * Basically exact. + */ +#define USEC(x) ( ( (x) >> 12 ) - 759 * ( ( ( (x) >> 10 ) + 32768 ) >> 16 ) ) + +/* +Timestamp Name ID When Generated +---------------------------------------------------------------- +Originate Timestamp T1 time request sent by client +Receive Timestamp T2 time request received by server +Transmit Timestamp T3 time reply sent by server +Destination Timestamp T4 time reply received by client +*/ + +NtpClient *NtpClient::s_pThis; + +NtpClient::NtpClient() { + DEBUG_ENTRY + assert(s_pThis == nullptr); + s_pThis = this; + + memset(&m_Request, 0, sizeof m_Request); + + m_Request.LiVnMode = ntp::VERSION | ntp::MODE_CLIENT; + m_Request.Poll = ntpclient::POLL_POWER; + m_Request.ReferenceID = ('A' << 0) | ('V' << 8) | ('S' << 16); + + NetworkParams networkParams; + networkParams.Load(); + + m_nServerIp = networkParams.GetNtpServer(); + + if (m_nServerIp == 0) { + m_Status = ntp::Status::STOPPED; + } + + DEBUG_EXIT +} + +/* + * Seconds and Fractions since 01.01.1900 + */ +void NtpClient::GetTimeNtpFormat(uint32_t &nSeconds, uint32_t &nFraction) { + struct timeval now; + gettimeofday(&now, nullptr); + nSeconds = now.tv_sec + ntp::JAN_1970; + nFraction = NTPFRAC(now.tv_usec); +} + +void NtpClient::Send() { + GetTimeNtpFormat(T1.nSeconds, T1.nFraction); + + m_Request.OriginTimestamp_s = __builtin_bswap32(T1.nSeconds); + m_Request.OriginTimestamp_f = __builtin_bswap32(T1.nFraction); + + Network::Get()->SendTo(m_nHandle, &m_Request, sizeof m_Request, m_nServerIp, ntp::UDP_PORT); +} + +bool NtpClient::Receive(uint8_t& LiVnMode) { + uint32_t nFromIp; + uint16_t nFromPort; + ntp::Packet *pReply; + + const auto nBytesReceived = Network::Get()->RecvFrom(m_nHandle, const_cast(reinterpret_cast(&pReply)), &nFromIp, &nFromPort); + + if (__builtin_expect((nBytesReceived != sizeof(struct ntp::Packet)), 1)) { + return false; + } + + GetTimeNtpFormat(T4.nSeconds, T4.nFraction); + + if (__builtin_expect((nFromIp != m_nServerIp), 0)) { + DEBUG_PUTS("nFromIp != m_nServerIp"); + return false; + } + + LiVnMode = pReply->LiVnMode; + + T2.nSeconds = __builtin_bswap32(pReply->ReceiveTimestamp_s); + T2.nFraction = __builtin_bswap32(pReply->ReceiveTimestamp_f); + + T3.nSeconds = __builtin_bswap32(pReply->TransmitTimestamp_s); + T3.nFraction = __builtin_bswap32(pReply->TransmitTimestamp_f); + + PrintNtpTime("T1: ", &T1); + PrintNtpTime("T2: ", &T2); + PrintNtpTime("T3: ", &T3); + PrintNtpTime("T4: ", &T4); + + return true; +} + +void NtpClient::Difference(const struct ntp::TimeStamp& Start, const struct ntp::TimeStamp& Stop, int32_t &nDiffSeconds, int32_t &nDiffMicroSeconds) { + ntp::time_t r; + const ntp::time_t x = {.tv_sec = static_cast(Stop.nSeconds), .tv_usec = static_cast(USEC(Stop.nFraction))}; + const ntp::time_t y = {.tv_sec = static_cast(Start.nSeconds), .tv_usec = static_cast(USEC(Start.nFraction))}; + ntp::sub_time(&r, &x, &y); + + nDiffSeconds = r.tv_sec; + nDiffMicroSeconds = r.tv_usec; +} + +void NtpClient::SetTimeOfDay() { + int32_t nDiffSeconds1, nDiffSeconds2 ; + int32_t nDiffMicroSeconds1, nDiffMicroSeconds2; + + Difference(T1, T2, nDiffSeconds1, nDiffMicroSeconds1); + Difference(T4, T3, nDiffSeconds2, nDiffMicroSeconds2); + + auto nOffsetSeconds = static_cast(nDiffSeconds1) + static_cast(nDiffSeconds2); + auto nOffsetMicroSeconds = static_cast(nDiffMicroSeconds1) + static_cast(nDiffMicroSeconds2); + + const int32_t nOffsetSecondsAverage = nOffsetSeconds / 2; + const int32_t nOffsetMicrosAverage = nOffsetMicroSeconds / 2; + + ntp::time_t ptpOffset = {.tv_sec = nOffsetSecondsAverage, .tv_usec = nOffsetMicrosAverage}; + ntp::normalize_time(&ptpOffset); + + struct timeval tv; + + tv.tv_sec = static_cast(T4.nSeconds - ntp::JAN_1970) + nOffsetSecondsAverage; + tv.tv_usec = (static_cast(USEC(T4.nFraction)) + static_cast(nOffsetMicrosAverage)); + + settimeofday(&tv, nullptr); + +#ifndef NDEBUG + /* delay */ + ntp::time_t diff1; + ntp::time_t diff2; + + Difference(T1, T4, diff1.tv_sec, diff1.tv_usec); + Difference(T2, T3, diff2.tv_sec, diff2.tv_usec); + + ntp::time_t ntpDelay; + ntp::sub_time(&ntpDelay, &diff1, &diff2); + + char sign = '+'; + + if (ptpOffset.tv_sec < 0) { + ptpOffset.tv_sec = -ptpOffset.tv_sec; + sign = '-'; + } + + if (ptpOffset.tv_usec < 0) { + ptpOffset.tv_usec = -ptpOffset.tv_usec; + sign = '-'; + } + + printf(" offset=%c%d.%06d delay=%d.%06d\n", sign, ptpOffset.tv_sec, ptpOffset.tv_usec, ntpDelay.tv_sec, ntpDelay.tv_usec); +#endif +} + +void NtpClient::Start() { + DEBUG_ENTRY + + if (m_nServerIp == 0) { + m_Status = ntp::Status::STOPPED; + ntpclient::display_status(ntp::Status::STOPPED); + DEBUG_EXIT + return; + } + + assert(m_nHandle == -1); + m_nHandle = Network::Get()->Begin(ntp::UDP_PORT); + assert(m_nHandle != -1); + + m_MillisLastPoll = Hardware::Get()->Millis() - (1000 * ntpclient::POLL_SECONDS); + + m_Status = ntp::Status::IDLE; + ntpclient::display_status(ntp::Status::IDLE); + + DEBUG_EXIT +} + +void NtpClient::Stop() { + DEBUG_ENTRY + + if (m_Status == ntp::Status::STOPPED) { + return; + } + + assert(m_nHandle != -1); + Network::Get()->End(ntp::UDP_PORT); + m_nHandle = -1; + + m_Status = ntp::Status::STOPPED; + + ntpclient::display_status(ntp::Status::STOPPED); + + DEBUG_EXIT +} + +void NtpClient::PrintNtpTime([[maybe_unused]] const char *pText, [[maybe_unused]] const struct ntp::TimeStamp *pNtpTime) { +#ifndef NDEBUG + const auto nSeconds = static_cast(pNtpTime->nSeconds - ntp::JAN_1970); + const auto *pTm = localtime(&nSeconds); + printf("%s %02d:%02d:%02d.%06d %04d [%u]\n", pText, pTm->tm_hour, pTm->tm_min, pTm->tm_sec, USEC(pNtpTime->nFraction), pTm->tm_year + 1900, pNtpTime->nSeconds); +#endif +} + +void NtpClient::Print() { + printf("NTP v%d Client [%s]\n", (ntp::VERSION >> 3), ntp::STATUS[static_cast(m_Status)]); + if (m_Status == ntp::Status::STOPPED) { + puts(" Not enabled"); + return; + } + printf(" Server : " IPSTR ":%d\n", IP2STR(m_nServerIp), ntp::UDP_PORT); +} diff --git a/lib-network/src/apps/tftp/tftpdaemon.cpp b/lib-network/src/net/apps/tftp/tftpdaemon.cpp similarity index 96% rename from lib-network/src/apps/tftp/tftpdaemon.cpp rename to lib-network/src/net/apps/tftp/tftpdaemon.cpp index ca311230..3d0c3d9d 100644 --- a/lib-network/src/apps/tftp/tftpdaemon.cpp +++ b/lib-network/src/net/apps/tftp/tftpdaemon.cpp @@ -2,7 +2,7 @@ * @file tftpdaemon.cpp * */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -31,7 +31,7 @@ #include #include -#include "tftpdaemon.h" +#include "net/apps/tftpdaemon.h" #include "network.h" @@ -259,7 +259,7 @@ void TFTPDaemon::DoRead() { FileClose(); } - DEBUG_PRINTF("m_nDataLength=%ld, m_nPacketLength=%d, m_bIsLastBlock=%d", m_nDataLength, m_nPacketLength, m_bIsLastBlock); + DEBUG_PRINTF("m_nDataLength=%u, m_nPacketLength=%d, m_bIsLastBlock=%d", m_nDataLength, m_nPacketLength, m_bIsLastBlock); } DEBUG_PRINTF("Sending to " IPSTR ":%d", IP2STR(m_nFromIp), m_nFromPort); @@ -304,7 +304,7 @@ void TFTPDaemon::HandleRecvData() { m_nDataLength = m_nLength - 4; m_nBlockNumber = __builtin_bswap16(pDataPacket->BlockNumber); - DEBUG_PRINTF("Incoming from " IPSTR ", m_nLength=%u, m_nBlockNumber=%d, m_nDataLength=%u", IP2STR(m_nFromIp), static_cast(m_nLength), m_nBlockNumber, static_cast(m_nDataLength)); + DEBUG_PRINTF("Incoming from " IPSTR ", m_nLength=%u, m_nBlockNumber=%d, m_nDataLength=%u", IP2STR(m_nFromIp), m_nLength, m_nBlockNumber, m_nDataLength); if (m_nDataLength == FileWrite(pDataPacket->Data, m_nDataLength, m_nBlockNumber)) { diff --git a/lib-network/src/net/arp.cpp b/lib-network/src/net/arp.cpp old mode 100644 new mode 100755 index 1cb8e094..466e9235 --- a/lib-network/src/net/arp.cpp +++ b/lib-network/src/net/arp.cpp @@ -2,7 +2,7 @@ * @file arp.cpp * */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -22,228 +22,497 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ +/** + * https://datatracker.ietf.org/doc/html/rfc826 + * An Ethernet Address Resolution Protocol + * -- or -- + * Converting Network Protocol Addresses + */ + +#if defined (DEBUG_NET_ARP) +# undef NDEBUG +#endif + +#if !defined (CONFIG_REMOTECONFIG_MINIMUM) +# pragma GCC push_options +# pragma GCC optimize ("O2") +# pragma GCC optimize ("no-tree-loop-distribute-patterns") +#endif #include #include +#include #include -#include "net.h" +#include "../../config/net_config.h" + +#include "net_memcpy.h" #include "net_private.h" -#include "../../config/net_config.h" +#include "net/arp.h" +#include "net/acd.h" +#include "net/protocol/arp.h" +#include "net/protocol/udp.h" +#include "netif.h" -namespace net { -namespace arp { -enum class RequestType { - REQUEST, - PROBE, - ANNNOUNCEMENT -}; -} // namespace arp -} // namespace net +#include "hardware.h" -static struct t_arp s_arp_request ALIGNED ; -static struct t_arp s_arp_reply ALIGNED; -static net::arp::RequestType s_requestType ALIGNED; -static bool s_isProbeReplyReceived ALIGNED; +#include "debug.h" + +#if !defined ARP_MAX_RECORDS +static constexpr auto MAX_RECORDS = 16; +#else +static constexpr auto MAX_RECORDS = ARP_MAX_RECORDS; +#endif namespace net { namespace globals { -extern struct IpInfo ipInfo; -extern uint8_t macAddress[ETH_ADDR_LEN]; +extern uint32_t nOnNetworkMask; } // namespace globals -} // namespace net -typedef union pcast32 { - uint32_t u32; - uint8_t u8[4]; -} _pcast32; +namespace arp { +static constexpr uint32_t TIMER_INTERVAL = 1000; ///< 1 second +static constexpr uint32_t MAX_PROBING = 2; ///< 2 * 1 second +static constexpr uint32_t MAX_REACHABLE = (10 * 60); ///< (10 * 60) * 1 second = 10 minutes +static constexpr uint32_t MAX_STALE = ( 5 * 60); ///< ( 5 * 60) * 1 second = 5 minutes -void __attribute__((cold)) arp_init() { - arp_cache_init(); +enum class State { + STATE_EMPTY, STATE_PROBE, STATE_REACHABLE, STATE_STALE, +}; - s_requestType = net::arp::RequestType::REQUEST; +struct Packet { + uint8_t *p; + uint32_t nSize; +#if defined CONFIG_ENET_ENABLE_PTP + bool isTimestamp; +#endif +}; - // ARP Request template - // Ethernet header - memcpy(s_arp_request.ether.src, net::globals::macAddress, ETH_ADDR_LEN); - memset(s_arp_request.ether.dst, 0xFF , ETH_ADDR_LEN); - s_arp_request.ether.type = __builtin_bswap16(ETHER_TYPE_ARP); +struct Record { + uint32_t nIp; + Packet packet; + uint8_t mac_address[ETH_ADDR_LEN]; + uint16_t nAge; + State state; +}; +} // namespace arp - // ARP Header - s_arp_request.arp.hardware_type = __builtin_bswap16(ARP_HWTYPE_ETHERNET); - s_arp_request.arp.protocol_type = __builtin_bswap16(ARP_PRTYPE_IPv4); - s_arp_request.arp.hardware_size = ARP_HARDWARE_SIZE; - s_arp_request.arp.protocol_size = ARP_PROTOCOL_SIZE; - s_arp_request.arp.opcode = __builtin_bswap16(ARP_OPCODE_RQST); +static net::arp::Record s_ArpRecords[MAX_RECORDS] SECTION_NETWORK ALIGNED; - memcpy(s_arp_request.arp.sender_mac, net::globals::macAddress, ETH_ADDR_LEN); - _pcast32 ip_addr; - ip_addr.u32 = net::globals::ipInfo.ip.addr; - memcpy(s_arp_request.arp.sender_ip, ip_addr.u8, IPv4_ADDR_LEN); - memset(s_arp_request.arp.target_mac, 0x00, ETH_ADDR_LEN); +static struct t_arp s_arp_request ALIGNED ; +static struct t_arp s_arp_reply ALIGNED; - // ARP Reply Template - // Ethernet header - memcpy(s_arp_reply.ether.src, net::globals::macAddress, ETH_ADDR_LEN); - s_arp_reply.ether.type = __builtin_bswap16(ETHER_TYPE_ARP); +#ifndef NDEBUG +static constexpr char STATE[4][12] = { "EMPTY", "PROBE", "REACHABLE", "STALE", }; - // ARP Header - s_arp_reply.arp.hardware_type = __builtin_bswap16(ARP_HWTYPE_ETHERNET); - s_arp_reply.arp.protocol_type = __builtin_bswap16(ARP_PRTYPE_IPv4); - s_arp_reply.arp.hardware_size = ARP_HARDWARE_SIZE; - s_arp_reply.arp.protocol_size = ARP_PROTOCOL_SIZE; - s_arp_reply.arp.opcode = __builtin_bswap16(ARP_OPCODE_REPLY); +void static arp_cache_record_dump(net::arp::Record *pRecord) { + printf("%p %-4d %c " MACSTR " %-10s " IPSTR "\n", pRecord, pRecord->nAge, pRecord->packet.p == nullptr ? '-' : 'Q' , MAC2STR(pRecord->mac_address), STATE[static_cast(pRecord->state)], IP2STR(pRecord->nIp)); +} - memcpy(s_arp_reply.arp.sender_mac, net::globals::macAddress, ETH_ADDR_LEN); +void static arp_cache_dump() { + uint32_t nIndex = 0; + for (auto &record : s_ArpRecords) { + printf("%p %02d %-4d" MACSTR " %-10s " IPSTR "\n", &record, nIndex++, record.nAge, MAC2STR(record.mac_address), STATE[static_cast(record.state)], IP2STR(record.nIp)); + if (nIndex ==6) { + return; + } + } } +#else +void static arp_cache_record_dump([[maybe_unused]] net::arp::Record *pRecord) {} +void static arp_cache_dump() {} +#endif -bool arp_do_probe() { - int32_t nTimeout; - auto nRetries = 3; +static net::arp::Record *arp_find_record(const uint32_t nDestinationIp, [[maybe_unused]] const arp::Flags flag) { + DEBUG_ENTRY - while (nRetries--) { - arp_send_probe(); + net::arp::Record *pStale = nullptr; + net::arp::Record *pReachable = nullptr; + uint32_t nAgeStale = 0; + uint32_t nAgeReachable = 0; - nTimeout = 0x1FFFF; -#ifndef NDEBUG - nTimeout+= 0x40000; -#endif + for (auto &record : s_ArpRecords) { + if (record.nIp == nDestinationIp) { + DEBUG_EXIT + return &record; + } + + if (flag == arp::Flags::FLAG_UPDATE) { + continue; + } - while ((nTimeout-- > 0) && !s_isProbeReplyReceived) { - net_handle(); + if (record.state == net::arp::State::STATE_EMPTY) { + record.nIp = nDestinationIp; + DEBUG_EXIT + return &record; } - if (s_isProbeReplyReceived) { - return true; + if (record.state == net::arp::State::STATE_REACHABLE) { + if (record.nAge > nAgeReachable) { + nAgeReachable = record.nAge; + pReachable = &record; + } + continue; } + + + if (record.state == net::arp::State::STATE_STALE) { + if (record.nAge > nAgeStale) { + nAgeStale = record.nAge; + pStale = &record; + } + continue; + } + } + + if (pStale != nullptr) { + DEBUG_EXIT + return pStale; } - return false; + if (pReachable != nullptr) { + DEBUG_EXIT + return pReachable; + } + + DEBUG_EXIT + return nullptr; } -void arp_send_request(uint32_t nIp) { +static void arp_cache_update(const uint8_t *pMacAddress, const uint32_t nIp, const arp::Flags flag) { DEBUG_ENTRY - DEBUG_PRINTF(IPSTR, IP2STR(nIp)); + DEBUG_PRINTF(MACSTR " " IPSTR " flag=%d", MAC2STR(pMacAddress), IP2STR(nIp), flag); - s_requestType = net::arp::RequestType::REQUEST; + auto *record = arp_find_record(nIp, flag); - _pcast32 ip_addr; - ip_addr.u32 = nIp; + if (record == nullptr) { + assert(flag == arp::Flags::FLAG_UPDATE); + DEBUG_EXIT + return; + } - memcpy(s_arp_request.arp.target_ip, ip_addr.u8, IPv4_ADDR_LEN); + record->state = net::arp::State::STATE_REACHABLE; + record->nAge = 0; + std::memcpy(record->mac_address, pMacAddress, ETH_ADDR_LEN); - emac_eth_send(reinterpret_cast(&s_arp_request), sizeof(struct t_arp)); + arp_cache_record_dump(record); + + if (record->packet.p != nullptr) { + auto *udp = reinterpret_cast(record->packet.p); + std::memcpy(udp->ether.dst, record->mac_address, ETH_ADDR_LEN); + udp->ip4.chksum = 0; +#if !defined (CHECKSUM_BY_HARDWARE) + udp->ip4.chksum = net_chksum(reinterpret_cast(&udp->ip4), sizeof(udp->ip4)); +#endif +#if defined CONFIG_ENET_ENABLE_PTP + if (!record->packet.isTimestamp) { +#endif + emac_eth_send(record->packet.p, record->packet.nSize); +#if defined CONFIG_ENET_ENABLE_PTP + } else { + emac_eth_send_timestamp(record->packet.p, record->packet.nSize); + } +#endif + delete [] record->packet.p; + record->packet.p = nullptr; + } DEBUG_EXIT } -/* - * The Sender IP is set to all zeros, - * which means it cannot map to the Sender MAC address. - * The Target MAC address is all zeros, - * which means it cannot map to the Target IP address. - */ -void arp_send_probe() { +static void arp_send_request(const uint32_t nIp) { + DEBUG_PRINTF(IPSTR, IP2STR(nIp)); + + net::memcpy_ip(s_arp_request.arp.target_ip, nIp); + + emac_eth_send(reinterpret_cast(&s_arp_request), sizeof(struct t_arp)); +} + +template +static void arp_query(const uint32_t nDestinationIp, struct t_udp *pPacket, const uint32_t nSize, [[maybe_unused]] const arp::Flags flag) { DEBUG_ENTRY + DEBUG_PRINTF(IPSTR " %c", IP2STR(nDestinationIp), flag == arp::Flags::FLAG_UPDATE ? 'U' : 'I'); - s_requestType = net::arp::RequestType::PROBE; - s_isProbeReplyReceived = false; + auto *recordFound = arp_find_record(nDestinationIp, flag); + assert(recordFound != nullptr); - memset(s_arp_request.arp.sender_ip, 0, IPv4_ADDR_LEN); + arp_cache_record_dump(recordFound); + + if (recordFound->state == net::arp::State::STATE_EMPTY) { + recordFound->state = net::arp::State::STATE_PROBE; + recordFound->nAge = 0; + arp_send_request(nDestinationIp); + } + + if (recordFound->state == net::arp::State::STATE_PROBE) { + if (recordFound->packet.p != nullptr) { + delete[] recordFound->packet.p; + } - arp_send_request(net::globals::ipInfo.ip.addr); + recordFound->packet.p = new uint8_t[nSize]; + assert(recordFound->packet.p != nullptr); - _pcast32 ip_addr; - ip_addr.u32 = net::globals::ipInfo.ip.addr; - memcpy(s_arp_request.arp.sender_ip, ip_addr.u8, IPv4_ADDR_LEN); + net::memcpy(recordFound->packet.p, pPacket, nSize); + recordFound->packet.nSize = nSize; +#if defined CONFIG_ENET_ENABLE_PTP + recordFound->packet.isTimestamp = (S != net::arp::EthSend::IS_NORMAL); +#endif + } DEBUG_EXIT } -/* - * The packet structure is identical to the ARP Probe above, - * with the exception that a complete mapping exists. - * Both the Sender MAC address and the Sender IP address create a complete ARP mapping, - * and hosts on the network can use this pair of addresses in their ARP table. - */ -void arp_send_announcement() { - DEBUG_ENTRY +static void arp_cache_clean_record(net::arp::Record& record) { + if (record.packet.p != nullptr) { + delete[] record.packet.p; + } + memset(&record, 0, sizeof(struct net::arp::Record)); +} - s_requestType = net::arp::RequestType::ANNNOUNCEMENT; +static void arp_send_request_unicast(const uint32_t nIp, const uint8_t *pMacAddress) { + DEBUG_PRINTF(IPSTR, IP2STR(nIp)); - arp_send_request(net::globals::ipInfo.ip.addr); + net::memcpy(s_arp_request.ether.dst, pMacAddress , ETH_ADDR_LEN); + net::memcpy_ip(s_arp_request.arp.target_ip, nIp); - DEBUG_EXIT + emac_eth_send(reinterpret_cast(&s_arp_request), sizeof(struct t_arp)); + + memset(s_arp_request.ether.dst, 0xFF , ETH_ADDR_LEN); +} + +static void arp_timer() { + for (auto &record : s_ArpRecords) { + const auto state = record.state; + if (state != net::arp::State::STATE_EMPTY) { + record.nAge++; + + switch (state) { + case net::arp::State::STATE_PROBE: + if (record.nAge > net::arp::MAX_PROBING) { + arp_cache_clean_record(record); + } + break; + + case net::arp::State::STATE_REACHABLE: + if (record.nAge > net::arp::MAX_REACHABLE) { + record.state = net::arp::State::STATE_STALE; + record.nAge = 0; + } + break; + + case net::arp::State::STATE_STALE: + if (record.nAge > net::arp::MAX_STALE) { + record.state = net::arp::State::STATE_PROBE; + arp_send_request_unicast(record.nIp, record.mac_address); + } + break; + + default: + break; + } + } + } + + arp_cache_dump(); } -void arp_handle_request(struct t_arp *p_arp) { +static void arp_send_reply(const struct t_arp *p_arp) { DEBUG_ENTRY - _pcast32 target; + // Ethernet header + std::memcpy(s_arp_reply.ether.dst, p_arp->ether.src, ETH_ADDR_LEN); + // ARP Header + const auto nIpTarget = net::memcpy_ip(p_arp->arp.target_ip); + std::memcpy(s_arp_reply.arp.target_mac, p_arp->arp.sender_mac, ETH_ADDR_LEN); + std::memcpy(s_arp_reply.arp.target_ip, p_arp->arp.sender_ip, IPv4_ADDR_LEN); + net::memcpy_ip(s_arp_reply.arp.sender_ip, nIpTarget); - memcpy(target.u8, p_arp->arp.target_ip, IPv4_ADDR_LEN); + emac_eth_send(reinterpret_cast(&s_arp_reply), sizeof(struct t_arp)); - _pcast32 sender; + DEBUG_EXIT +} - memcpy(sender.u8, p_arp->arp.sender_ip, IPv4_ADDR_LEN); +// Public interface - DEBUG_PRINTF("Sender " IPSTR " Target " IPSTR, IP2STR(sender.u32), IP2STR(target.u32)); +void __attribute__((cold)) arp_init() { + DEBUG_ENTRY - if (!((target.u32 == net::globals::ipInfo.ip.addr) || (target.u32 == net::globals::ipInfo.secondary_ip.addr) || (target.u32 == net::globals::ipInfo.broadcast_ip.addr))) { - DEBUG_PUTS("No for me."); - DEBUG_EXIT - return; + for (auto& record : s_ArpRecords) { + std::memset(&record, 0, sizeof(struct net::arp::Record)); } + // ARP Request template // Ethernet header - memcpy(s_arp_reply.ether.dst, p_arp->ether.src, ETH_ADDR_LEN); + std::memcpy(s_arp_request.ether.src, net::globals::netif_default.hwaddr, ETH_ADDR_LEN); + std::memset(s_arp_request.ether.dst, 0xFF , ETH_ADDR_LEN); + s_arp_request.ether.type = __builtin_bswap16(ETHER_TYPE_ARP); + // ARP Header - memcpy(s_arp_reply.arp.target_mac, p_arp->arp.sender_mac, ETH_ADDR_LEN); - memcpy(s_arp_reply.arp.target_ip, p_arp->arp.sender_ip, IPv4_ADDR_LEN); - memcpy(s_arp_reply.arp.sender_ip, target.u8, IPv4_ADDR_LEN); + s_arp_request.arp.hardware_type = __builtin_bswap16(ARP_HWTYPE_ETHERNET); + s_arp_request.arp.protocol_type = __builtin_bswap16(ARP_PRTYPE_IPv4); + s_arp_request.arp.hardware_size = ARP_HARDWARE_SIZE; + s_arp_request.arp.protocol_size = ARP_PROTOCOL_SIZE; + s_arp_request.arp.opcode = __builtin_bswap16(ARP_OPCODE_RQST); - emac_eth_send(reinterpret_cast(&s_arp_reply), sizeof(struct t_arp)); + std::memcpy(s_arp_request.arp.sender_mac, net::globals::netif_default.hwaddr, ETH_ADDR_LEN); + net::memcpy_ip(s_arp_request.arp.sender_ip, net::globals::netif_default.ip.addr); + std::memset(s_arp_request.arp.target_mac, 0x00, ETH_ADDR_LEN); + + // ARP Reply Template + // Ethernet header + std::memcpy(s_arp_reply.ether.src, net::globals::netif_default.hwaddr, ETH_ADDR_LEN); + s_arp_reply.ether.type = __builtin_bswap16(ETHER_TYPE_ARP); + + // ARP Header + s_arp_reply.arp.hardware_type = __builtin_bswap16(ARP_HWTYPE_ETHERNET); + s_arp_reply.arp.protocol_type = __builtin_bswap16(ARP_PRTYPE_IPv4); + s_arp_reply.arp.hardware_size = ARP_HARDWARE_SIZE; + s_arp_reply.arp.protocol_size = ARP_PROTOCOL_SIZE; + s_arp_reply.arp.opcode = __builtin_bswap16(ARP_OPCODE_REPLY); + + std::memcpy(s_arp_reply.arp.sender_mac, net::globals::netif_default.hwaddr, ETH_ADDR_LEN); + + Hardware::Get()->SoftwareTimerAdd(net::arp::TIMER_INTERVAL, arp_timer); DEBUG_EXIT } -void arp_handle_reply(struct t_arp *p_arp) { - DEBUG_ENTRY - - switch (s_requestType) { - case net::arp::RequestType::REQUEST: { - _pcast32 sender; - memcpy(sender.u8, p_arp->arp.sender_ip, IPv4_ADDR_LEN); - arp_cache_update(p_arp->arp.sender_mac, sender.u32); +__attribute__((hot)) void arp_handle(struct t_arp *pArp) { + /* + * RFC 826 Packet Reception: + */ + if (__builtin_expect(((pArp->arp.hardware_type != __builtin_bswap16(ARP_HWTYPE_ETHERNET)) + || (pArp->arp.protocol_type != __builtin_bswap16(ARP_PRTYPE_IPv4)) + || (pArp->arp.hardware_size != ARP_HARDWARE_SIZE) + || (pArp->arp.protocol_size != ARP_PROTOCOL_SIZE)), 0)) { + DEBUG_EXIT + return; } + + acd_arp_reply(pArp); + + /* ARP packet directed to us? */ + const auto nIpTarget = net::memcpy_ip(pArp->arp.target_ip); + const auto bToUs = ((nIpTarget == net::globals::netif_default.ip.addr) || (nIpTarget == net::globals::netif_default.secondary_ip.addr)); + /* ARP packet from us? */ + const auto bFromUs = (net::memcpy_ip(pArp->arp.sender_ip) == net::globals::netif_default.ip.addr); + + DEBUG_PRINTF("bToUs:%d, bFromUs:%d", bToUs, bFromUs); + + /* + * ARP message directed to us? + * -> add IP address in ARP cache; assume requester wants to talk to us, + * can result in directly sending the queued packets for this host. + * ARP message not directed to us? + * -> update the source IP address in the cache, if present + */ + arp_cache_update(pArp->arp.sender_mac, net::memcpy_ip(pArp->arp.sender_ip), bToUs ? arp::Flags::FLAG_INSERT : arp::Flags::FLAG_UPDATE); + + switch (pArp->arp.opcode) { + case __builtin_bswap16(ARP_OPCODE_RQST): + if (bToUs && !bFromUs) { + arp_send_reply(pArp); + } else { + DEBUG_PUTS("ARP request was not for us"); + } break; - case net::arp::RequestType::PROBE: - s_isProbeReplyReceived = true; + case __builtin_bswap16(ARP_OPCODE_REPLY): + /* Cache update is handled earlier */ break; default: - assert(0); - __builtin_unreachable(); + DEBUG_PRINTF("opcode %04x not handled", __builtin_bswap16(pArp->arp.opcode)); break; } +} + +template +static void arp_send_implementation(struct t_udp *pPacket, const uint32_t nSize, const uint32_t nRemoteIp) { + DEBUG_ENTRY + DEBUG_PRINTF(IPSTR, IP2STR(nRemoteIp)); + + net::memcpy_ip(pPacket->ip4.dst, nRemoteIp); + pPacket->ip4.chksum = 0; +#if !defined (CHECKSUM_BY_HARDWARE) + pPacket->ip4.chksum = net_chksum(reinterpret_cast(&pPacket->ip4), sizeof(pPacket->ip4)); +#endif + + auto nDestinationIp = nRemoteIp; + + if (__builtin_expect((net::globals::nOnNetworkMask != (nRemoteIp & net::globals::nOnNetworkMask)), 0)) { + /* According to RFC 3297, chapter 2.6.2 (Forwarding Rules), a packet with + a link-local source address must always be "directly to its destination + on the same physical link. The host MUST NOT send the packet to any + router for forwarding". */ + if (!network::is_linklocal_ip(nRemoteIp)) { + nDestinationIp = net::globals::netif_default.gw.addr; + DEBUG_PUTS(""); + } + } + + for (auto &record : s_ArpRecords) { + if (record.state >= net::arp::State::STATE_REACHABLE) { + if (record.nIp == nDestinationIp) { + std::memcpy(pPacket->ether.dst, record.mac_address, ETH_ADDR_LEN); + + if (S == net::arp::EthSend::IS_NORMAL) { + emac_eth_send(reinterpret_cast(pPacket), nSize); + } +#if defined CONFIG_ENET_ENABLE_PTP + else if (S == net::arp::EthSend::IS_TIMESTAMP) { + emac_eth_send_timestamp(reinterpret_cast(pPacket), nSize); + } +#endif + DEBUG_EXIT + return; + } + } + } + + arp_query(nDestinationIp, pPacket, nSize, arp::Flags::FLAG_INSERT); DEBUG_EXIT + return; } -__attribute__((hot)) void arp_handle(struct t_arp *pArp) { +void arp_send(struct t_udp *pPacket, const uint32_t nSize, const uint32_t nRemoteIp) { + arp_send_implementation(pPacket, nSize, nRemoteIp); +} + +#if defined CONFIG_ENET_ENABLE_PTP +void arp_send_timestamp(struct t_udp *pPacket, const uint32_t nSize, const uint32_t nRemoteIp) { + arp_send_implementation(pPacket, nSize, nRemoteIp); +} +#endif + +/* + * The Sender IP is set to all zeros, + * which means it cannot map to the Sender MAC address. + * The Target MAC address is all zeros, + * which means it cannot map to the Target IP address. + */ +void arp_acd_probe(const ip4_addr_t ipaddr) { DEBUG_ENTRY - switch (pArp->arp.opcode) { - case __builtin_bswap16(ARP_OPCODE_RQST): - arp_handle_request(pArp); - break; - case __builtin_bswap16(ARP_OPCODE_REPLY): - arp_handle_reply(pArp); - break; - default: - DEBUG_PRINTF("opcode %04x not handled", __builtin_bswap16(pArp->arp.opcode)); - break; - } + memset(s_arp_request.arp.sender_ip, 0, IPv4_ADDR_LEN); + net::memcpy_ip(s_arp_request.arp.target_ip, ipaddr.addr); + + emac_eth_send(reinterpret_cast(&s_arp_request), sizeof(struct t_arp)); + + net::memcpy_ip(s_arp_request.arp.sender_ip, net::globals::netif_default.ip.addr); DEBUG_EXIT } + +/* + * The packet structure is identical to the ARP Probe above, + * with the exception that a complete mapping exists. + * Both the Sender MAC address and the Sender IP address create a complete ARP mapping, + * and hosts on the network can use this pair of addresses in their ARP table. + */ +void arp_acd_send_announcement(const ip4_addr_t ipaddr) { + net::memcpy_ip(s_arp_request.arp.target_ip, ipaddr.addr); + net::memcpy_ip(s_arp_request.arp.sender_ip, ipaddr.addr); + + emac_eth_send(reinterpret_cast(&s_arp_request), sizeof(struct t_arp)); +} +} // namespace net diff --git a/lib-network/src/net/arp_cache.cpp b/lib-network/src/net/arp_cache.cpp deleted file mode 100644 index 97f2795b..00000000 --- a/lib-network/src/net/arp_cache.cpp +++ /dev/null @@ -1,171 +0,0 @@ -/** - * @file arp_cache.cpp - * - */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#include - -#include "net_private.h" -#include "net_packets.h" -#include "net_platform.h" -#include "net_debug.h" - -#include "emac/net_link_check.h" - -#include "../../config/net_config.h" - -#if !defined ARP_MAX_RECORDS -static constexpr auto MAX_RECORDS = 32; -#else -static constexpr auto MAX_RECORDS = ARP_MAX_RECORDS; -#endif - -struct ArpRecord { - uint32_t nIp; - uint8_t mac_address[ETH_ADDR_LEN]; -}; - -typedef union pcast32 { - uint32_t u32; - uint8_t u8[4]; -} _pcast32; - -static ArpRecord s_ArpRecords[MAX_RECORDS] SECTION_NETWORK ALIGNED; -static uint16_t s_Entries SECTION_NETWORK ALIGNED; - -#ifndef NDEBUG -# define TICKER_COUNT 100 ///< 10 seconds - static volatile uint32_t s_ticker ; -#endif - -void __attribute__((cold)) arp_cache_init() { - s_Entries = 0; - - for (auto& record : s_ArpRecords) { - memset(&record, 0, sizeof(struct ArpRecord)); - } - -#ifndef NDEBUG - s_ticker = TICKER_COUNT; -#endif -} - -void arp_cache_update(const uint8_t *pMacAddress, uint32_t nIp) { - DEBUG_ENTRY - DEBUG_PRINTF(MACSTR " " IPSTR, MAC2STR(pMacAddress), IP2STR(nIp)); - - if (s_Entries == MAX_RECORDS) { - console_error("ARP cache is full\n"); - return; - } - - for (auto i = 0; i < s_Entries; i++) { - if (s_ArpRecords[i].nIp == nIp) { - DEBUG_EXIT - return; - } - } - - memcpy(s_ArpRecords[s_Entries].mac_address, pMacAddress, ETH_ADDR_LEN); - s_ArpRecords[s_Entries].nIp = nIp; - - s_Entries++; - - DEBUG_EXIT -} - -uint32_t arp_cache_lookup(uint32_t nIp, uint8_t *pMacAddress) { - DEBUG_ENTRY - DEBUG_PRINTF(IPSTR " " MACSTR, IP2STR(nIp), MAC2STR(pMacAddress)); - - uint32_t i; - - for (i = 0; i < MAX_RECORDS; i++) { - if (s_ArpRecords[i].nIp == nIp) { - memcpy(pMacAddress, s_ArpRecords[i].mac_address, ETH_ADDR_LEN); - DEBUG_EXIT - return nIp; - } - - if (s_ArpRecords[i].nIp == 0) { - break; - } - } - - if (net::link_status_read() == net::Link::STATE_DOWN) { - DEBUG_EXIT - return 0; - } - - const auto nEntries = s_Entries; - int32_t nTimeout; - auto nRetries = 3; - - while (nRetries--) { - arp_send_request(nIp); - - nTimeout = 0x1FFFF; -#ifndef NDEBUG - nTimeout+= 0x40000; -#endif - - while ((nTimeout-- > 0) && (nEntries == s_Entries)) { - net_handle(); - } - - if (nEntries != s_Entries) { - memcpy(pMacAddress, s_ArpRecords[nEntries].mac_address, ETH_ADDR_LEN); - DEBUG_PRINTF("timeout=%x", nTimeout); - DEBUG_EXIT - return nIp; - } - - DEBUG_PRINTF("timeout=%d, current_entry=%d, s_entry_current=%d", nTimeout, nEntries, s_Entries); - } - - DEBUG_EXIT - return 0; -} - -void arp_cache_dump() { -#ifndef NDEBUG - printf("ARP Cache size=%d\n", s_Entries); - - for (auto i = 0; i < s_Entries; i++) { - printf("%02d " IPSTR " " MACSTR "\n", i, IP2STR(s_ArpRecords[i].nIp),MAC2STR(s_ArpRecords[i].mac_address)); - } -#endif -} - -#ifndef NDEBUG -void arp_cache_timer(void) { - s_ticker--; - - if (s_ticker == 0) { - s_ticker = TICKER_COUNT; - arp_cache_dump(); - } -} -#endif diff --git a/lib-network/src/net/autoip.cpp b/lib-network/src/net/autoip.cpp new file mode 100755 index 00000000..cb2fedfd --- /dev/null +++ b/lib-network/src/net/autoip.cpp @@ -0,0 +1,172 @@ +/** + * @file autoip.cpp + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +/* This code is inspired by the lwIP TCP/IP stack. + * https://savannah.nongnu.org/projects/lwip/ + */ +/** + * The autoip.cpp aims to be conform to RFC 3927. + * https://datatracker.ietf.org/doc/html/rfc3927 + * Dynamic Configuration of IPv4 Link-Local Addresses + */ + +#ifdef DEBUG_AUTOIP +# undef NDEBUG +#endif + +#include +#include + +#include "netif.h" +#include "net/autoip.h" +#include "net/protocol/autoip.h" +#include "net/acd.h" +#include "net/arp.h" + +#include "debug.h" + +namespace net { +static void autoip_bind(){ + auto *autoip = reinterpret_cast(globals::netif_default.autoip); + assert(autoip != nullptr); + + autoip->state = autoip::State::AUTOIP_STATE_BOUND; + + ip4_addr_t sn_mask, gw_addr; + + sn_mask.addr = network::convert_to_uint(255,255,0,0); + gw_addr.addr = 0; + + netif_set_addr(autoip->llipaddr, sn_mask, gw_addr); +} + +static void autoip_restart() { + auto *autoip = reinterpret_cast(globals::netif_default.autoip); + assert(autoip != nullptr); + + autoip->tried_llipaddr++; + autoip_start(); +} + +static void autoip_conflict_callback(net::acd::Callback state) { + auto *autoip = reinterpret_cast(globals::netif_default.autoip); + assert(autoip != nullptr); + + switch (state) { + case net::acd::Callback::ACD_IP_OK: + autoip_bind(); + netif_set_flags(netif::NETIF_FLAG_AUTOIP_OK); + break; + case net::acd::Callback::ACD_RESTART_CLIENT: + autoip_restart(); + break; + case net::acd::Callback::ACD_DECLINE: + /* "delete" conflicting address so a new one will be selected in autoip_start() */ + autoip->llipaddr.addr = network::IP4_ANY; + autoip_stop(); + netif_clear_flags(netif::NETIF_FLAG_AUTOIP_OK); + break; + default: + break; + } +} + +static void autoip_create_addr(uint32_t &ipaddr) { + auto *autoip = reinterpret_cast(globals::netif_default.autoip); + assert(autoip != nullptr); + + /* Here we create an IP-Address out of range 169.254.1.0 to 169.254.254.255 + * compliant to RFC 3927 Section 2.1 */ + const auto mask = globals::netif_default.hwaddr[3] + (globals::netif_default.hwaddr[4] << 8); + ipaddr = static_cast(mask << 16) | autoip::AUTOIP_RANGE_START; + ipaddr = __builtin_bswap32(ipaddr); + + ipaddr += autoip->tried_llipaddr; + ipaddr = __builtin_bswap32(autoip::AUTOIP_NET) | (ipaddr & 0xffff); + + if (ipaddr < __builtin_bswap32(autoip::AUTOIP_RANGE_START)) { + ipaddr += __builtin_bswap32(autoip::AUTOIP_RANGE_END) - __builtin_bswap32(autoip::AUTOIP_RANGE_START) + 1; + } + + if (ipaddr > __builtin_bswap32(autoip::AUTOIP_RANGE_END)) { + ipaddr -= __builtin_bswap32(autoip::AUTOIP_RANGE_END) - __builtin_bswap32(autoip::AUTOIP_RANGE_START) + 1; + } + + ipaddr = __builtin_bswap32(ipaddr); + + DEBUG_PRINTF(IPSTR, IP2STR(ipaddr)); +} + +/* + * Public interface + */ + +void autoip_start() { + DEBUG_ENTRY + + auto *autoip = reinterpret_cast(globals::netif_default.autoip); + + if (autoip == nullptr) { + autoip = new (struct autoip::Autoip); + assert(autoip != nullptr); + memset(autoip, 0, sizeof(struct autoip::Autoip)); + } + + if (autoip->state == autoip::State::AUTOIP_STATE_OFF) { + acd_add(&autoip->acd, autoip_conflict_callback); + + /* In accordance to RFC3927 section 2.1: + * Keep using the same link local address as much as possible. + * Only when there is none or when there was a conflict, select a new one. + */ + if (!network::is_linklocal_ip(autoip->llipaddr.addr)) { + autoip_create_addr(autoip->llipaddr.addr); + } + + autoip->state = autoip::State::AUTOIP_STATE_CHECKING; + acd_start(&autoip->acd, autoip->llipaddr); + } else { + DEBUG_PUTS("Already started"); + } + + DEBUG_EXIT +} + +void autoip_stop() { + DEBUG_ENTRY + auto *autoip = reinterpret_cast(globals::netif_default.autoip); + + if (autoip != nullptr) { + autoip->state = autoip::State::AUTOIP_STATE_OFF; + + ip4_addr_t any; + any.addr = network::IP4_ANY; + + if (network::is_linklocal_ip(globals::netif_default.ip.addr)) { + netif_set_addr(any, any, any); + } + } + + DEBUG_EXIT +} +} // namespace net diff --git a/lib-network/src/net/dhcp.cpp b/lib-network/src/net/dhcp.cpp old mode 100644 new mode 100755 index a160ece6..7bc1f309 --- a/lib-network/src/net/dhcp.cpp +++ b/lib-network/src/net/dhcp.cpp @@ -1,8 +1,7 @@ /** * @file dhcp.cpp - * */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -22,372 +21,852 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ +/* This code is inspired by the lwIP TCP/IP stack. + * https://savannah.nongnu.org/projects/lwip/ + */ + +#if defined (DEBUG_NET_DHCP) +# undef NDEBUG +#endif + +#pragma GCC push_options +#pragma GCC optimize ("Os") #include #include #include -#include "dhcp_internal.h" - #include "net.h" +#include "net_memcpy.h" #include "net_private.h" #include "hardware.h" +#include "network.h" #include "../../config/net_config.h" -namespace net { -namespace globals { -extern struct IpInfo ipInfo; -extern uint8_t macAddress[ETH_ADDR_LEN]; -} // namespace globals -} // namespace net +#include "net/dhcp.h" +#include "net/protocol/dhcp.h" +#include "net/protocol/iana.h" +#include "net/acd.h" +#include "net/autoip.h" +#include "netif.h" -typedef union pcast32 { - uint32_t u32; - uint8_t u8[4]; -} _pcast32; +#define REBOOT_TRIES 2 + +static int32_t nTimerId; // https://tools.ietf.org/html/rfc1541 +namespace net { +static dhcp::Message s_dhcp_message SECTION_NETWORK ALIGNED; + +static void message_init() { + memset(&s_dhcp_message, 0, sizeof(dhcp::Message)); -namespace dhcp { -struct Message { - uint8_t op; - uint8_t htype; - uint8_t hlen; - uint8_t hops; - uint32_t xid; - uint16_t secs; - uint16_t flags; - uint8_t ciaddr[IPv4_ADDR_LEN]; - uint8_t yiaddr[IPv4_ADDR_LEN]; - uint8_t siaddr[IPv4_ADDR_LEN]; - uint8_t giaddr[IPv4_ADDR_LEN]; - uint8_t chaddr[16]; - uint8_t sname[64]; - uint8_t file[128]; - uint8_t options[DHCP_OPT_SIZE]; -}PACKED; -} // namespace dhcp - -enum OPTIONS { - OPTIONS_PAD_OPTION = 0, - OPTIONS_SUBNET_MASK = 1, - OPTIONS_ROUTERS_ON_SUBNET = 3, - OPTIONS_DNS = 6, - OPTIONS_HOSTNAME = 12, - OPTIONS_DOMAIN_NAME = 15, - OPTIONS_REQUESTED_IP = 50, - OPTIONS_MESSAGE_TYPE = 53, - OPTIONS_SERVER_IDENTIFIER = 54, - OPTIONS_PARAM_REQUEST = 55, - OPTIONS_DHCP_T1_VALUE = 58, - OPTIONS_DHCP_T2_VALUE = 59, - OPTIONS_CLIENT_IDENTIFIER = 61, - OPTIONS_END_OPTION = 255 -}; - -static dhcp::Message s_dhcp_message ALIGNED; - -static uint8_t s_dhcp_server_ip[IPv4_ADDR_LEN] ALIGNED = { 0, }; -static uint8_t s_dhcp_allocated_ip[IPv4_ADDR_LEN] ALIGNED = { 0, }; -static uint8_t s_dhcp_allocated_gw[IPv4_ADDR_LEN] ALIGNED = { 0, }; -static uint8_t s_dhcp_allocated_netmask[IPv4_ADDR_LEN] ALIGNED = { 0, }; - -static void message_init(const uint8_t *pMacAddress) { - auto *p = reinterpret_cast(&s_dhcp_message); - - for (uint32_t i = 0; i < sizeof(dhcp::Message); i++) { - *p++ = 0; - } - - s_dhcp_message.op = DHCP_OP_BOOTREQUEST; - s_dhcp_message.htype = DHCP_HTYPE_10MB; // This is the current default - s_dhcp_message.hlen = ETH_ADDR_LEN; - memcpy(s_dhcp_message.chaddr, pMacAddress, ETH_ADDR_LEN); - - s_dhcp_message.options[0] = static_cast((MAGIC_COOKIE & 0xFF000000) >> 24); - s_dhcp_message.options[1] = static_cast((MAGIC_COOKIE & 0x00FF0000) >> 16); - s_dhcp_message.options[2] = static_cast((MAGIC_COOKIE & 0x0000FF00) >> 8); - s_dhcp_message.options[3] = static_cast(MAGIC_COOKIE & 0x000000FF) >> 0; - - s_dhcp_message.options[4] = OPTIONS_MESSAGE_TYPE; + s_dhcp_message.op = dhcp::OpCode::BOOTREQUEST; + s_dhcp_message.htype = dhcp::HardwareType::HTYPE_10MB; // This is the current default + s_dhcp_message.hlen = network::MAC_SIZE; + memcpy(s_dhcp_message.chaddr, net::globals::netif_default.hwaddr, network::MAC_SIZE); + + s_dhcp_message.options[0] = static_cast((dhcp::MAGIC_COOKIE & 0xFF000000) >> 24); + s_dhcp_message.options[1] = static_cast((dhcp::MAGIC_COOKIE & 0x00FF0000) >> 16); + s_dhcp_message.options[2] = static_cast((dhcp::MAGIC_COOKIE & 0x0000FF00) >> 8); + s_dhcp_message.options[3] = static_cast(dhcp::MAGIC_COOKIE & 0x000000FF) >> 0; + + s_dhcp_message.options[4] = dhcp::Options::OPTION_MESSAGE_TYPE; s_dhcp_message.options[5] = 0x01; } -static void send_discover(int nHandle, const uint8_t *pMacAddress) { +static void dhcp_update_msg(const uint8_t message_type) { + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + assert(dhcp != nullptr); + + /* DHCP_REQUEST should reuse 'xid' from DHCPOFFER */ + if ((message_type != dhcp::Type::REQUEST) || (dhcp->state == dhcp::State::STATE_REBOOTING)) { + /* reuse transaction identifier in retransmissions */ + if (dhcp->tries == 0) { + auto xid = __builtin_bswap32(dhcp->xid); + xid++; + dhcp->xid = __builtin_bswap32(xid); + } + } + + s_dhcp_message.xid = dhcp->xid; + + if ((message_type == dhcp::Type::INFORM) + || (message_type == dhcp::Type::DECLINE) + || (message_type == dhcp::Type::RELEASE) + || ((message_type == dhcp::Type::REQUEST) + && /* DHCP_STATE_BOUND not used for sending! */ + ((dhcp->state == dhcp::State::STATE_RENEWING) || dhcp->state == dhcp::State::STATE_REBINDING))) { + + const auto &netif = net::globals::netif_default; + net::memcpy_ip(s_dhcp_message.ciaddr, netif.ip.addr); + } +} + +static void send_discover() { DEBUG_ENTRY + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + assert(dhcp != nullptr); + + dhcp_update_msg(dhcp::Type::DISCOVER); uint32_t k = 6; - s_dhcp_message.options[k++] = DCHP_TYPE_DISCOVER; + s_dhcp_message.options[k++] = dhcp::Type::DISCOVER; - s_dhcp_message.options[k++] = OPTIONS_CLIENT_IDENTIFIER; + s_dhcp_message.options[k++] = dhcp::Options::OPTION_CLIENT_IDENTIFIER; s_dhcp_message.options[k++] = 0x07; s_dhcp_message.options[k++] = 0x01; - s_dhcp_message.options[k++] = pMacAddress[0]; - s_dhcp_message.options[k++] = pMacAddress[1]; - s_dhcp_message.options[k++] = pMacAddress[2]; - s_dhcp_message.options[k++] = pMacAddress[3]; - s_dhcp_message.options[k++] = pMacAddress[4]; - s_dhcp_message.options[k++] = pMacAddress[5]; - - s_dhcp_message.options[k++] = OPTIONS_PARAM_REQUEST; + s_dhcp_message.options[k++] = net::globals::netif_default.hwaddr[0]; + s_dhcp_message.options[k++] = net::globals::netif_default.hwaddr[1]; + s_dhcp_message.options[k++] = net::globals::netif_default.hwaddr[2]; + s_dhcp_message.options[k++] = net::globals::netif_default.hwaddr[3]; + s_dhcp_message.options[k++] = net::globals::netif_default.hwaddr[4]; + s_dhcp_message.options[k++] = net::globals::netif_default.hwaddr[5]; + + s_dhcp_message.options[k++] = dhcp::Options::OPTION_PARAM_REQUEST; s_dhcp_message.options[k++] = 0x06; // length of request - s_dhcp_message.options[k++] = OPTIONS_SUBNET_MASK; - s_dhcp_message.options[k++] = OPTIONS_ROUTERS_ON_SUBNET; - s_dhcp_message.options[k++] = OPTIONS_DNS; - s_dhcp_message.options[k++] = OPTIONS_DOMAIN_NAME; - s_dhcp_message.options[k++] = OPTIONS_DHCP_T1_VALUE; - s_dhcp_message.options[k++] = OPTIONS_DHCP_T2_VALUE; - s_dhcp_message.options[k++] = OPTIONS_END_OPTION; + s_dhcp_message.options[k++] = dhcp::Options::OPTION_SUBNET_MASK; + s_dhcp_message.options[k++] = dhcp::Options::OPTION_ROUTER; + s_dhcp_message.options[k++] = dhcp::Options::OPTION_DOMAIN_NAME; + s_dhcp_message.options[k++] = dhcp::Options::OPTION_LEASE_TIME; + s_dhcp_message.options[k++] = dhcp::Options::OPTION_DHCP_T1_VALUE; + s_dhcp_message.options[k++] = dhcp::Options::OPTION_DHCP_T2_VALUE; + s_dhcp_message.options[k++] = dhcp::Options::OPTION_END; - udp_send(nHandle, reinterpret_cast(&s_dhcp_message), static_cast(k + sizeof(dhcp::Message) - DHCP_OPT_SIZE), IP_BROADCAST, DHCP_PORT_SERVER); + udp_send(dhcp->nHandle, reinterpret_cast(&s_dhcp_message), static_cast(k + sizeof(dhcp::Message) - dhcp::OPT_SIZE), network::IP4_BROADCAST, net::iana::IANA_PORT_DHCP_SERVER); DEBUG_EXIT } -static void _send_request(int idx, const uint8_t *pMacAddress, const char *pHostname) { +static void send_request() { DEBUG_ENTRY + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + assert(dhcp != nullptr); uint32_t i; uint32_t k = 6; - s_dhcp_message.options[k++] = DCHP_TYPE_REQUEST; + s_dhcp_message.options[k++] = dhcp::Type::REQUEST; - s_dhcp_message.options[k++] = OPTIONS_CLIENT_IDENTIFIER; + s_dhcp_message.options[k++] = dhcp::Options::OPTION_CLIENT_IDENTIFIER; s_dhcp_message.options[k++] = 0x07; s_dhcp_message.options[k++] = 0x01; - s_dhcp_message.options[k++] = pMacAddress[0]; - s_dhcp_message.options[k++] = pMacAddress[1]; - s_dhcp_message.options[k++] = pMacAddress[2]; - s_dhcp_message.options[k++] = pMacAddress[3]; - s_dhcp_message.options[k++] = pMacAddress[4]; - s_dhcp_message.options[k++] = pMacAddress[5]; - - s_dhcp_message.options[k++] = OPTIONS_REQUESTED_IP; + s_dhcp_message.options[k++] = net::globals::netif_default.hwaddr[0]; + s_dhcp_message.options[k++] = net::globals::netif_default.hwaddr[1]; + s_dhcp_message.options[k++] = net::globals::netif_default.hwaddr[2]; + s_dhcp_message.options[k++] = net::globals::netif_default.hwaddr[3]; + s_dhcp_message.options[k++] = net::globals::netif_default.hwaddr[4]; + s_dhcp_message.options[k++] = net::globals::netif_default.hwaddr[5]; + + s_dhcp_message.options[k++] = dhcp::Options::OPTION_REQUESTED_IP; s_dhcp_message.options[k++] = 0x04; - s_dhcp_message.options[k++] = s_dhcp_allocated_ip[0]; - s_dhcp_message.options[k++] = s_dhcp_allocated_ip[1]; - s_dhcp_message.options[k++] = s_dhcp_allocated_ip[2]; - s_dhcp_message.options[k++] = s_dhcp_allocated_ip[3]; + memcpy_ip(&s_dhcp_message.options[k], dhcp->offered.offered_ip_addr.addr); + k = k + 4; - s_dhcp_message.options[k++] = OPTIONS_SERVER_IDENTIFIER; + s_dhcp_message.options[k++] = dhcp::Options::OPTION_SERVER_IDENTIFIER; s_dhcp_message.options[k++] = 0x04; - s_dhcp_message.options[k++] = s_dhcp_server_ip[0]; - s_dhcp_message.options[k++] = s_dhcp_server_ip[1]; - s_dhcp_message.options[k++] = s_dhcp_server_ip[2]; - s_dhcp_message.options[k++] = s_dhcp_server_ip[3]; + memcpy_ip(&s_dhcp_message.options[k], dhcp->server_ip_addr.addr); + k = k + 4; - s_dhcp_message.options[k++] = OPTIONS_HOSTNAME; + s_dhcp_message.options[k++] = dhcp::Options::OPTION_HOSTNAME; s_dhcp_message.options[k++] = 0; // length of hostname - for (i = 0; pHostname[i] != 0; i++) { - s_dhcp_message.options[k++] = pHostname[i]; + for (i = 0; net::globals::netif_default.hostname[i] != 0; i++) { + s_dhcp_message.options[k++] = net::globals::netif_default.hostname[i]; } s_dhcp_message.options[k - (i + 1)] = static_cast(i); // length of hostname - s_dhcp_message.options[k++] = OPTIONS_PARAM_REQUEST; + s_dhcp_message.options[k++] = dhcp::Options::OPTION_PARAM_REQUEST; s_dhcp_message.options[k++] = 0x06; // length of request - s_dhcp_message.options[k++] = OPTIONS_SUBNET_MASK; - s_dhcp_message.options[k++] = OPTIONS_ROUTERS_ON_SUBNET; - s_dhcp_message.options[k++] = OPTIONS_DNS; - s_dhcp_message.options[k++] = OPTIONS_DOMAIN_NAME; - s_dhcp_message.options[k++] = OPTIONS_DHCP_T1_VALUE; - s_dhcp_message.options[k++] = OPTIONS_DHCP_T2_VALUE; - s_dhcp_message.options[k++] = OPTIONS_END_OPTION; + s_dhcp_message.options[k++] = dhcp::Options::OPTION_SUBNET_MASK; + s_dhcp_message.options[k++] = dhcp::Options::OPTION_ROUTER; + s_dhcp_message.options[k++] = dhcp::Options::OPTION_DNS_SERVER; + s_dhcp_message.options[k++] = dhcp::Options::OPTION_DOMAIN_NAME; + s_dhcp_message.options[k++] = dhcp::Options::OPTION_DHCP_T1_VALUE; + s_dhcp_message.options[k++] = dhcp::Options::OPTION_DHCP_T2_VALUE; + s_dhcp_message.options[k++] = dhcp::Options::OPTION_END; - udp_send(idx, reinterpret_cast(&s_dhcp_message), static_cast(k + sizeof(dhcp::Message) - DHCP_OPT_SIZE), IP_BROADCAST, DHCP_PORT_SERVER); + udp_send(dhcp->nHandle, reinterpret_cast(&s_dhcp_message), static_cast(k + sizeof(dhcp::Message) - dhcp::OPT_SIZE), network::IP4_BROADCAST, net::iana::IANA_PORT_DHCP_SERVER); DEBUG_EXIT } -static int parse_response(int nHandle, const uint8_t *pMacAddress) { - uint8_t *pResponse; - const auto nMillis = Hardware::Get()->Millis(); - uint32_t nSize = 0; +static void dhcp_send_release(const uint32_t nDestinationIp) { + DEBUG_ENTRY + DEBUG_PRINTF(IPSTR, IP2STR(nDestinationIp)); + + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + assert(dhcp != nullptr); - do { - net_handle(); + uint32_t k = 6; - uint32_t nFromIp; - uint16_t nFromPort; + s_dhcp_message.options[k++] = dhcp::Type::RELEASE; - nSize = udp_recv2(nHandle, const_cast(&pResponse), &nFromIp, &nFromPort); + s_dhcp_message.options[k++] = dhcp::Options::OPTION_SERVER_IDENTIFIER; + s_dhcp_message.options[k++] = 0x04; + net::memcpy_ip(&s_dhcp_message.options[k], dhcp->server_ip_addr.addr); + k = k + 4; - if ((nSize > 0) && (nFromPort == DHCP_PORT_SERVER)) { + s_dhcp_message.options[k++] = dhcp::Options::OPTION_END; - const auto *const pDhcpMessage = reinterpret_cast(pResponse); + udp_send(dhcp->nHandle, reinterpret_cast(&s_dhcp_message), static_cast(k + sizeof(dhcp::Message) - dhcp::OPT_SIZE), nDestinationIp, net::iana::IANA_PORT_DHCP_SERVER); - if (memcmp(pDhcpMessage->chaddr, pMacAddress, ETH_ADDR_LEN) == 0) { - break; - } - } - } while ((Hardware::Get()->Millis() - nMillis) < 500); + DEBUG_EXIT +} - DEBUG_PRINTF("timeout %u", Hardware::Get()->Millis() - nMillis); +void dhcp_inform() { + DEBUG_ENTRY - int type = 0; - uint8_t opt_len = 0; + const auto nHandle = udp_begin(net::iana::IANA_PORT_DHCP_CLIENT); +#ifndef NDEBUG + if (nHandle < 0) { + console_error("DHCP Inform\n"); + return; + } +#endif - if (nSize > 0) { - auto *p = pResponse; - p = p + sizeof(dhcp::Message) - DHCP_OPT_SIZE + 4; - auto *e = pResponse + nSize; - - while (p < e) { - switch (*p) { - case OPTIONS_END_OPTION: - p = e; - break; - case OPTIONS_PAD_OPTION: - p++; - break; - case OPTIONS_MESSAGE_TYPE: - p++; - p++; - type = *p++; - break; - case OPTIONS_SUBNET_MASK: - p++; - p++; - s_dhcp_allocated_netmask[0] = *p++; - s_dhcp_allocated_netmask[1] = *p++; - s_dhcp_allocated_netmask[2] = *p++; - s_dhcp_allocated_netmask[3] = *p++; - break; - case OPTIONS_ROUTERS_ON_SUBNET: - p++; - opt_len = *p++; - s_dhcp_allocated_gw[0] = *p++; - s_dhcp_allocated_gw[1] = *p++; - s_dhcp_allocated_gw[2] = *p++; - s_dhcp_allocated_gw[3] = *p++; - p = p + (opt_len - 4); - break; - case OPTIONS_SERVER_IDENTIFIER : - p++; - opt_len = *p++; - s_dhcp_server_ip[0] = *p++; - s_dhcp_server_ip[1] = *p++; - s_dhcp_server_ip[2] = *p++; - s_dhcp_server_ip[3] = *p++; - break; - default: - p++; - opt_len = *p++; - p += opt_len; - break; - } - } + message_init(); + net::memcpy_ip(&s_dhcp_message.ciaddr[0], net::globals::netif_default.ip.addr); + + uint32_t k = 6; + + s_dhcp_message.options[k++] = dhcp::Type::INFORM; + + s_dhcp_message.options[k++] = dhcp::Options::OPTION_CLIENT_IDENTIFIER; + s_dhcp_message.options[k++] = 0x07; + s_dhcp_message.options[k++] = 0x01; + s_dhcp_message.options[k++] = net::globals::netif_default.hwaddr[0]; + s_dhcp_message.options[k++] = net::globals::netif_default.hwaddr[1]; + s_dhcp_message.options[k++] = net::globals::netif_default.hwaddr[2]; + s_dhcp_message.options[k++] = net::globals::netif_default.hwaddr[3]; + s_dhcp_message.options[k++] = net::globals::netif_default.hwaddr[4]; + s_dhcp_message.options[k++] = net::globals::netif_default.hwaddr[5]; + + s_dhcp_message.options[k++] = dhcp::Options::OPTION_END; + + udp_send(nHandle, reinterpret_cast(&s_dhcp_message), static_cast(k + sizeof(dhcp::Message) - dhcp::OPT_SIZE), network::IP4_BROADCAST, net::iana::IANA_PORT_DHCP_SERVER); + udp_end(net::iana::IANA_PORT_DHCP_CLIENT); + + DEBUG_EXIT +} + +#define SET_TIMEOUT_FROM_OFFERED(result, offered, min, max) do { \ + uint32_t timeout = (offered + dhcp::DHCP_COARSE_TIMER_SECS / 2) / dhcp::DHCP_COARSE_TIMER_SECS; \ + if (timeout > max) { \ + timeout = max; \ + } \ + if (timeout == min) { \ + timeout = 1; \ + } \ + result = static_cast(timeout); \ +} while(0) + +#define DHCP_SET_TIMEOUT_FROM_OFFERED_T0_LEASE(res, dhcp) SET_TIMEOUT_FROM_OFFERED(res, (dhcp)->offered.offered_t0_lease, 0, 0xffff) +#define DHCP_SET_TIMEOUT_FROM_OFFERED_T1_RENEW(res, dhcp) SET_TIMEOUT_FROM_OFFERED(res, (dhcp)->offered.offered_t1_renew, 0, 0xffff) +#define DHCP_SET_TIMEOUT_FROM_OFFERED_T2_REBIND(res, dhcp) SET_TIMEOUT_FROM_OFFERED(res, (dhcp)->offered.offered_t2_rebind, 0, 0xffff) + +#define DHCP_NEXT_TIMEOUT_THRESHOLD ((60 + net::dhcp::DHCP_COARSE_TIMER_SECS / 2) / net::dhcp::DHCP_COARSE_TIMER_SECS) +#define DHCP_REQUEST_BACKOFF_SEQUENCE(tries) (( (tries) < 6U ? 1U << (tries) : 60U) * 1000U) + +static void dhcp_set_state(struct dhcp::Dhcp *dhcp, dhcp::State new_state) { + if (new_state != dhcp->state) { + DEBUG_PRINTF("%u -> %u", static_cast(dhcp->state), static_cast(new_state)); + + dhcp->state = new_state; + dhcp->tries = 0; + dhcp->request_timeout = 0; + } +} + +static void dhcp_bind() { + DEBUG_ENTRY + + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + assert(dhcp != nullptr); + + /* reset time used of lease */ + dhcp->lease_used = 0; - if (type == DCHP_TYPE_OFFER) { - const auto *const pDhcpMessage = reinterpret_cast(pResponse); - s_dhcp_allocated_ip[0] = pDhcpMessage->yiaddr[0]; - s_dhcp_allocated_ip[1] = pDhcpMessage->yiaddr[1]; - s_dhcp_allocated_ip[2] = pDhcpMessage->yiaddr[2]; - s_dhcp_allocated_ip[3] = pDhcpMessage->yiaddr[3]; + if (dhcp->offered.offered_t0_lease != 0xffffffffUL) { + /* set renewal period timer */ + DHCP_SET_TIMEOUT_FROM_OFFERED_T0_LEASE(dhcp->t0_timeout, dhcp); + } + + /* temporary DHCP lease? */ + if (dhcp->offered.offered_t1_renew != 0xffffffffUL) { + /* set renewal period timer */ + DHCP_SET_TIMEOUT_FROM_OFFERED_T1_RENEW(dhcp->t1_timeout, dhcp); + dhcp->t1_renew_time = dhcp->t1_timeout; + } + /* set renewal period timer */ + if (dhcp->offered.offered_t2_rebind != 0xffffffffUL) { + DHCP_SET_TIMEOUT_FROM_OFFERED_T2_REBIND(dhcp->t2_timeout, dhcp); + dhcp->t2_rebind_time = dhcp->t2_timeout; + } + + /* If we have sub 1 minute lease, t2 and t1 will kick in at the same time. */ + if ((dhcp->t1_timeout >= dhcp->t2_timeout) && (dhcp->t2_timeout > 0)) { + dhcp->t1_timeout = 0; + } + + ip4_addr_t sn_mask; + + if (dhcp->flags & DHCP_FLAG_SUBNET_MASK_GIVEN) { + /* copy offered network mask */ + sn_mask.addr = dhcp->offered.offered_sn_mask.addr; + } else { + /* subnet mask not given, choose a safe subnet mask given the network class */ + const uint8_t first_octet = dhcp->offered.offered_ip_addr.addr & 0xFF; + if (first_octet <= 127) { + sn_mask.addr = 0xFF; + } else if (first_octet >= 192) { + sn_mask.addr = 0xFFFFFF; + } else { + sn_mask.addr = 0xFFFF; } + } + + ip4_addr_t gw_addr; + gw_addr.addr = dhcp->offered.offered_gw_addr.addr; + + dhcp_set_state(dhcp, dhcp::State::STATE_BOUND); + + netif_set_flags(netif::NETIF_FLAG_DHCP_OK); + netif_set_addr(dhcp->offered.offered_ip_addr, sn_mask, gw_addr); + + DEBUG_EXIT +} + +static void dhcp_rebind() { + DEBUG_ENTRY + + DEBUG_EXIT +} + +#if defined (CONFIG_NET_DHCP_USE_ACD) +static void dhcp_send_decline() { + DEBUG_ENTRY + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + assert(dhcp != nullptr); + + dhcp_update_msg(dhcp::Type::DECLINE); + + uint32_t k = 6; + + s_dhcp_message.options[k++] = dhcp::Type::DECLINE; + + s_dhcp_message.options[k++] = dhcp::Options::OPTION_REQUESTED_IP; + s_dhcp_message.options[k++] = 0x04; + net::memcpy_ip(&s_dhcp_message.options[k], dhcp->offered.offered_ip_addr.addr); + k = k + 4; + s_dhcp_message.options[k++] = dhcp::Options::OPTION_END; + + udp_send(dhcp->nHandle, reinterpret_cast(&s_dhcp_message), static_cast(k + sizeof(dhcp::Message) - dhcp::OPT_SIZE), network::IP4_BROADCAST, net::iana::IANA_PORT_DHCP_SERVER); + + DEBUG_EXIT +} + +static void dhcp_decline() { + DEBUG_ENTRY - return type; + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + assert(dhcp != nullptr); + + dhcp_set_state(dhcp, dhcp::State::STATE_BACKING_OFF); + /* per section 4.4.4, broadcast DECLINE messages */ + dhcp_send_decline(); + + DEBUG_EXIT + return; +} + +static void dhcp_conflict_callback(net::acd::Callback callback) { + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + assert(dhcp != nullptr); + assert(dhcp->state != dhcp::State::STATE_OFF); + + uint16_t msecs; + + switch (callback) { + case net::acd::Callback::ACD_IP_OK: + dhcp_bind(); + break; + case net::acd::Callback::ACD_RESTART_CLIENT: + /* wait 10s before restarting + * According to RFC2131 section 3.1 point 5: + * If the client detects that the address is already in use (e.g., through + * the use of ARP), the client MUST send a DHCPDECLINE message to the + * server and restarts the configuration process. The client SHOULD wait + * a minimum of ten seconds before restarting the configuration process to + * avoid excessive network traffic in case of looping. */ + dhcp_set_state (dhcp, dhcp::State::STATE_BACKING_OFF); + msecs = 10U * 1000U; + dhcp->request_timeout = static_cast((msecs + dhcp::DHCP_FINE_TIMER_MSECS - 1) / dhcp::DHCP_FINE_TIMER_MSECS); + break; + case net::acd::Callback::ACD_DECLINE: + /* remove IP address from interface + * (prevents routing from selecting this interface) */ + ip4_addr_t any; + any.addr = 0; + netif_set_addr(any, any, any); + /* Let the DHCP server know we will not use the address */ + dhcp_decline(); + netif_clear_flags(netif::NETIF_FLAG_DHCP_OK); + break; + default: + break; } +} - return -1; +static void dhcp_check() { + DEBUG_ENTRY + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + + dhcp_set_state(dhcp, dhcp::State::STATE_CHECKING); + + acd_start(&dhcp->acd, dhcp->offered.offered_ip_addr); + + DEBUG_EXIT } +#endif -int dhcp_client(const char *pHostname) { +static void dhcp_discover() { DEBUG_ENTRY + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + assert(dhcp != nullptr); - auto bHaveIp = false; - int32_t retries = 20; +#if defined (CONFIG_NET_DHCP_USE_AUTOIP) + if (dhcp->tries >= DHCP_AUTOIP_COOP_TRIES) { + autoip_start(); + } +#endif - message_init(net::globals::macAddress); + dhcp->offered.offered_ip_addr.addr = 0; - auto nHandle = udp_begin(DHCP_PORT_CLIENT); + dhcp_set_state(dhcp, dhcp::State::STATE_SELECTING); - if (nHandle < 0) { - return -1; + send_discover(); + + if (dhcp->tries < 255) { + dhcp->tries++; } - net::globals::ipInfo.ip.addr = 0; - ip_set_ip(); + const auto msecs = DHCP_REQUEST_BACKOFF_SEQUENCE(dhcp->tries); + dhcp->request_timeout = static_cast((msecs + dhcp::DHCP_FINE_TIMER_MSECS - 1) / dhcp::DHCP_FINE_TIMER_MSECS); +} - while (!bHaveIp && (retries-- > 0)) { - DEBUG_PRINTF("retries=%d", retries); +static void dhcp_reboot() { + DEBUG_ENTRY + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + assert(dhcp != nullptr); - send_discover(static_cast(nHandle), net::globals::macAddress); + dhcp_set_state(dhcp, dhcp::State::STATE_REBOOTING); - int type; + send_request(); - if ((type = parse_response(static_cast(nHandle), net::globals::macAddress)) < 0) { - continue; - } + if (dhcp->tries < 255) { + dhcp->tries++; + } - DEBUG_PRINTF("type=%d", type); + const auto msecs = static_cast(dhcp->tries < 10U ? dhcp->tries * 1000U : 10U * 1000U); + dhcp->request_timeout = static_cast((msecs + dhcp::DHCP_FINE_TIMER_MSECS - 1) / dhcp::DHCP_FINE_TIMER_MSECS); - if (type != DCHP_TYPE_OFFER) { - continue; - } + DEBUG_EXIT +} + +static void dhcp_select() { + DEBUG_ENTRY + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); - DEBUG_PRINTF(IPSTR, s_dhcp_server_ip[0],s_dhcp_server_ip[1],s_dhcp_server_ip[2],s_dhcp_server_ip[3]); + dhcp_set_state(dhcp, dhcp::State::STATE_REQUESTING); + + send_request(); + + if (dhcp->tries < 255) { + dhcp->tries++; + } + + const auto msecs = static_cast((dhcp->tries < 6 ? 1 << dhcp->tries : 60U) * 1000U); + dhcp->request_timeout = static_cast((msecs + dhcp::DHCP_FINE_TIMER_MSECS - 1) / dhcp::DHCP_FINE_TIMER_MSECS); +} + +static void dhcp_timeout() { + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + assert(dhcp != nullptr); + + /* back-off period has passed, or server selection timed out */ + if ((dhcp->state == dhcp::State::STATE_BACKING_OFF) || (dhcp->state == dhcp::State::STATE_SELECTING)) { + dhcp_discover(); + /* receiving the requested lease timed out */ + } else if (dhcp->state == dhcp::State::STATE_REQUESTING) { + if (dhcp->tries <= 5) { + dhcp_select(); + } else { + dhcp_release_and_stop(); + dhcp_start(); + } + } else if (dhcp->state == dhcp::State::STATE_REBOOTING) { + if (dhcp->tries < REBOOT_TRIES) { + dhcp_reboot(); + } else { + dhcp_discover(); + } + } +} - _send_request(static_cast(nHandle), net::globals::macAddress, pHostname); +static void dhcp_t1_timeout() { + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + + if ((dhcp->state == dhcp::State::STATE_REQUESTING) + || (dhcp->state == dhcp::State::STATE_BOUND) + || (dhcp->state == dhcp::State::STATE_RENEWING)) { + /* just retry to renew - note that the rebind timer (t2) will + * eventually time-out if renew tries fail. */ + /* This slightly different to RFC2131: DHCPREQUEST will be sent from state + DHCP_STATE_RENEWING, not DHCP_STATE_BOUND */ + dhcp_renew(); + /* Calculate next timeout */ + if (static_cast((dhcp->t2_timeout - dhcp->lease_used) / 2) >= DHCP_NEXT_TIMEOUT_THRESHOLD) { + dhcp->t1_renew_time = static_cast((dhcp->t2_timeout - dhcp->lease_used) / 2); + } + } +} - if ((type =parse_response(static_cast(nHandle), net::globals::macAddress)) < 0) { - continue; +static void dhcp_t2_timeout() { + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + + if ((dhcp->state == dhcp::State::STATE_REQUESTING) + || (dhcp->state == dhcp::State::STATE_BOUND) + || (dhcp->state == dhcp::State::STATE_RENEWING) + || (dhcp->state == dhcp::State::STATE_REBINDING)) { + /* just retry to rebind */ + /* This slightly different to RFC2131: DHCPREQUEST will be sent from state + DHCP_STATE_REBINDING, not DHCP_STATE_BOUND */ + dhcp_rebind(); + /* Calculate next timeout */ + if (static_cast((dhcp->t0_timeout - dhcp->lease_used) / 2) >= DHCP_NEXT_TIMEOUT_THRESHOLD) { + dhcp->t2_rebind_time = static_cast((dhcp->t0_timeout - dhcp->lease_used) / 2); } + } +} - DEBUG_PRINTF("type=%d", type); +void dhcp_coarse_tmr() { + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + + if ((dhcp != nullptr) && (dhcp->state != dhcp::State::STATE_OFF)) { + /* compare lease time to expire timeout */ + if (dhcp->t0_timeout && (++dhcp->lease_used == dhcp->t0_timeout)) { + /* this clients' lease time has expired */ + dhcp_release_and_stop(); + dhcp_start(); + /* timer is active (non zero), and triggers (zeroes) now? */ + } else if (dhcp->t2_rebind_time && (dhcp->t2_rebind_time-- == 1)) { + /* this clients' rebind timeout triggered */ + dhcp_t2_timeout(); + /* timer is active (non zero), and triggers (zeroes) now */ + } else if (dhcp->t1_renew_time && (dhcp->t1_renew_time-- == 1)) { + /* this clients' renewal timeout triggered */ + dhcp_t1_timeout(); + } + } +} - if (type == DCHP_TYPE_ACK) { - bHaveIp = true; - break; +static void dhcp_fine_tmr() { + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + + if (dhcp != nullptr) { + /* timer is active (non zero), and is about to trigger now */ + if (dhcp->request_timeout > 1) { + dhcp->request_timeout--; + } else if (dhcp->request_timeout == 1) { + dhcp->request_timeout--; + /* this client's request timeout triggered */ + dhcp_timeout(); } } +} + +static void dhcp_handle_offer(const dhcp::Message *const pResponse) { + DEBUG_ENTRY + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + + if (dhcp->server_ip_addr.addr != 0) { + dhcp->request_timeout = 0; /* stop timer */ + dhcp->offered.offered_ip_addr.addr = net::memcpy_ip(pResponse->yiaddr); + DEBUG_PRINTF(IPSTR " -> " IPSTR, IP2STR(dhcp->server_ip_addr.addr), IP2STR(dhcp->offered.offered_ip_addr.addr)); + dhcp_select(); + } else { + DEBUG_PUTS("did not get server ID!"); + } + + DEBUG_EXIT +} - udp_end(DHCP_PORT_CLIENT); +static void dhcp_handle_ack(const dhcp::Message *const pResponse) { + DEBUG_ENTRY + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); - if (bHaveIp) { - _pcast32 ip; + DEBUG_PRINTF("t0=%u, t1=%u, t2=%u", dhcp->offered.offered_t0_lease, dhcp->offered.offered_t1_renew, dhcp->offered.offered_t2_rebind); - memcpy(ip.u8, s_dhcp_allocated_ip, IPv4_ADDR_LEN); - net::globals::ipInfo.ip.addr = ip.u32; + if (dhcp->offered.offered_t1_renew == 0) { + /* calculate safe periods for renewal */ + dhcp->offered.offered_t1_renew = dhcp->offered.offered_t0_lease / 2; + } - memcpy(ip.u8, s_dhcp_allocated_gw, IPv4_ADDR_LEN); - net::globals::ipInfo.gw.addr = ip.u32; + if (dhcp->offered.offered_t2_rebind == 0) { + /* calculate safe periods for rebinding (offered_t0_lease * 0.875 -> 87.5%)*/ + dhcp->offered.offered_t2_rebind = (dhcp->offered.offered_t0_lease * 7U) / 8U; + } + + dhcp->offered.offered_ip_addr.addr = net::memcpy_ip(pResponse->yiaddr); - memcpy(ip.u8, s_dhcp_allocated_netmask, IPv4_ADDR_LEN); - net::globals::ipInfo.netmask.addr = ip.u32; + if (dhcp->offered.offered_sn_mask.addr != 0) { + dhcp->flags |= DHCP_FLAG_SUBNET_MASK_GIVEN; + } else { + dhcp->flags &= ~DHCP_FLAG_SUBNET_MASK_GIVEN; } + DEBUG_PRINTF("t0=%u, t1=%u, t2=%u", dhcp->offered.offered_t0_lease, dhcp->offered.offered_t1_renew, dhcp->offered.offered_t2_rebind); DEBUG_EXIT - return bHaveIp ? 0 : -2; } -void dhcp_client_release() { +static void dhcp_handle_nak() { DEBUG_ENTRY + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + + // Change to a defined state - set this before assigning the address + // to ensure the callback can use dhcp_supplied_address() + dhcp_set_state(dhcp, dhcp::State::STATE_BACKING_OFF); + // remove IP address from interface (must no longer be used, as per RFC2131) + ip4_addr_t any; + any.addr = 0; + netif_set_addr(any, any, any); + // We can immediately restart discovery + dhcp_discover(); - auto nHandle = udp_begin(DHCP_PORT_CLIENT); + DEBUG_EXIT +} - if (nHandle < 0) { - console_error("dhcp_client_release\n"); +bool dhcp_start() { + DEBUG_ENTRY + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + + if (dhcp == nullptr) { + dhcp = new (struct dhcp::Dhcp); + assert(dhcp != nullptr); + globals::netif_default.dhcp = dhcp; + + nTimerId = Hardware::Get()->SoftwareTimerAdd(dhcp::DHCP_FINE_TIMER_MSECS, dhcp_fine_tmr); + assert(nTimerId >= 0); + } + + memset(dhcp, 0, sizeof(struct dhcp::Dhcp)); + dhcp->nHandle = udp_begin(net::iana::IANA_PORT_DHCP_CLIENT); + +#ifndef NDEBUG + if (dhcp->nHandle < 0) { + console_error("DHCP Start\n"); + DEBUG_EXIT + return false; + } +#endif + + message_init(); + +#if defined (CONFIG_NET_DHCP_USE_ACD) + acd_add(&dhcp->acd, dhcp_conflict_callback); +#endif + + if (!netif_is_link_up()) { + dhcp_set_state(dhcp, dhcp::State::STATE_INIT); + return false; + } + + dhcp_discover(); + + DEBUG_EXIT + return true; +} + +void dhcp_release_and_stop() { + DEBUG_ENTRY + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + + if (dhcp == nullptr) { + DEBUG_EXIT return; } - uint32_t k = 6; + if (dhcp->state == dhcp::State::STATE_OFF) { + return; + } - s_dhcp_message.options[k++] = DCHP_TYPE_RELEASE; + ip4_addr_t server_ip_addr; - s_dhcp_message.options[k++] = OPTIONS_SERVER_IDENTIFIER; - s_dhcp_message.options[k++] = 0x04; - s_dhcp_message.options[k++] = s_dhcp_server_ip[0]; - s_dhcp_message.options[k++] = s_dhcp_server_ip[1]; - s_dhcp_message.options[k++] = s_dhcp_server_ip[2]; - s_dhcp_message.options[k++] = s_dhcp_server_ip[3]; + server_ip_addr.addr = dhcp->server_ip_addr.addr; + + /* clean old DHCP offer */ + dhcp->server_ip_addr.addr = 0; + memset(&dhcp->offered, 0, sizeof(struct dhcp::Dhcp::Offered)); + dhcp->t1_renew_time = dhcp->t2_rebind_time = dhcp->lease_used = dhcp->t0_timeout = 0; + + if (dhcp_supplied_address()) { + dhcp_set_state(dhcp, dhcp::State::STATE_OFF); + + dhcp_send_release(server_ip_addr.addr); + + udp_end(net::iana::IANA_PORT_DHCP_CLIENT); + + /* remove IP address from interface (prevents routing from selecting this interface) */ + ip4_addr_t any; + any.addr = 0; + netif_set_addr(any, any, any); + } + +#if defined (CONFIG_NET_DHCP_USE_ACD) + acd_remove(&dhcp->acd); +#endif + + delete reinterpret_cast(globals::netif_default.dhcp); + globals::netif_default.dhcp = nullptr; +} + +void dhcp_network_changed_link_up() { + DEBUG_ENTRY + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); - s_dhcp_message.options[k++] = OPTIONS_END_OPTION; + if (dhcp == nullptr) { + DEBUG_EXIT + return; + } + + switch (dhcp->state) { + case dhcp::State::STATE_REBINDING: + case dhcp::State::STATE_RENEWING: + case dhcp::State::STATE_BOUND: + case dhcp::State::STATE_REBOOTING: + dhcp->tries = 0; + dhcp_reboot(); + break; + case dhcp::State::STATE_OFF: + break; + default: + dhcp->tries = 0; + dhcp_discover(); + break; + } +} + +void dhcp_process(const dhcp::Message *const pResponse, const uint32_t nSize) { + DEBUG_ENTRY + + assert(pResponse != nullptr); + + uint8_t msg_type = 0; + uint8_t opt_len = 0; - udp_send(static_cast(nHandle), reinterpret_cast(&s_dhcp_message), static_cast(k + sizeof(dhcp::Message) - DHCP_OPT_SIZE), IP_BROADCAST, DHCP_PORT_SERVER); - udp_end(DHCP_PORT_CLIENT); + auto *dhcp = reinterpret_cast(globals::netif_default.dhcp); + assert(dhcp != nullptr); + + memset(&dhcp->offered, 0, sizeof(struct dhcp::Dhcp::Offered)); + + dhcp->server_ip_addr.addr = 0; + + const auto *p = reinterpret_cast(pResponse); + p = p + sizeof(dhcp::Message) - dhcp::OPT_SIZE + 4; + auto *e = p + nSize; + + while (p < e) { + switch (*p) { + case dhcp::Options::OPTION_END: + p = e; + break; + case dhcp::Options::OPTION_PAD_OPTION: + p++; + break; + case dhcp::Options::OPTION_MESSAGE_TYPE: + p++; + p++; + msg_type = *p++; + break; + case dhcp::Options::OPTION_SUBNET_MASK: + p++; + p++; + dhcp->offered.offered_sn_mask.addr = net::memcpy_ip(p); + p = p + 4; + break; + case dhcp::Options::OPTION_ROUTER: + p++; + p++; + dhcp->offered.offered_gw_addr.addr = net::memcpy_ip(p); + p = p + 4; + break; + case dhcp::Options::OPTION_SERVER_IDENTIFIER: + p++; + p++; + dhcp->server_ip_addr.addr = net::memcpy_ip(p); + p += 4; + break; + case dhcp::Options::OPTION_LEASE_TIME: + p++; + p++; + dhcp->offered.offered_t0_lease = __builtin_bswap32(net::memcpy_ip(p)); + p += 4; + break; + case dhcp::Options::OPTION_DHCP_T1_VALUE: + p++; + p++; + dhcp->offered.offered_t1_renew = __builtin_bswap32(net::memcpy_ip(p)); + p += 4; + break; + case dhcp::Options::OPTION_DHCP_T2_VALUE: + p++; + p++; + dhcp->offered.offered_t2_rebind = __builtin_bswap32(net::memcpy_ip(p)); + p += 4; + break; + default: + p++; + opt_len = *p++; + p += opt_len; + break; + } + } + + if (msg_type == dhcp::Type::OFFER) { + dhcp->offered.offered_ip_addr.addr = net::memcpy_ip(pResponse->yiaddr); + } + + DEBUG_PRINTF("msg_type=%u", msg_type); + + if (msg_type == dhcp::Type::ACK) { + /* in requesting state or just reconnected to the network? */ + if ((dhcp->state == dhcp::State::STATE_REQUESTING) || + (dhcp->state == dhcp::State::STATE_REBOOTING)) { + dhcp_handle_ack(pResponse); +#if defined (CONFIG_NET_DHCP_USE_ACD) + dhcp_check(); +#else + dhcp_bind(); +#endif + } + else if ((dhcp->state == dhcp::State::STATE_REBINDING) || + (dhcp->state == dhcp::State::STATE_RENEWING)) { + dhcp_handle_ack(pResponse); + dhcp_bind(); + } + } + else if ((msg_type == dhcp::Type::NAK) && + ((dhcp->state == dhcp::State::STATE_REBOOTING) || (dhcp->state == dhcp::State::STATE_REQUESTING) || + (dhcp->state == dhcp::State::STATE_REBINDING) || (dhcp->state == dhcp::State::STATE_RENEWING ))) { + dhcp_handle_nak(); + } + else if ((msg_type == dhcp::Type::OFFER) && (dhcp->state == dhcp::State::STATE_SELECTING)) { + dhcp_handle_offer(pResponse); + } DEBUG_EXIT } +} // namespace net diff --git a/lib-network/src/net/icmp.cpp b/lib-network/src/net/icmp.cpp old mode 100644 new mode 100755 index 17afb636..51d8b235 --- a/lib-network/src/net/icmp.cpp +++ b/lib-network/src/net/icmp.cpp @@ -2,7 +2,7 @@ * @file icmp.cpp * */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,39 +23,48 @@ * THE SOFTWARE. */ +#if defined (DEBUG_NET_ICMP) +# undef NDEBUG +#endif + +#if !defined (CONFIG_REMOTECONFIG_MINIMUM) +# pragma GCC push_options +# pragma GCC optimize ("O2") +# pragma GCC optimize ("no-tree-loop-distribute-patterns") +#endif + #include #include -#include "net.h" -#include "net_private.h" - #include "../../config/net_config.h" -namespace net { -namespace globals { -extern struct IpInfo ipInfo; -extern uint8_t macAddress[ETH_ADDR_LEN]; -} // namespace globals -} // namespace net +#include "net_memcpy.h" +#include "net_private.h" -typedef union pcast32 { - uint32_t u32; - uint8_t u8[4]; -} _pcast32; +#include "net/protocol/icmp.h" +#include "debug.h" + +namespace net { __attribute__((hot)) void icmp_handle(struct t_icmp *p_icmp) { if (p_icmp->icmp.type == ICMP_TYPE_ECHO) { if (p_icmp->icmp.code == ICMP_CODE_ECHO) { // Ethernet - memcpy(p_icmp->ether.dst, p_icmp->ether.src, ETH_ADDR_LEN); - memcpy(p_icmp->ether.src, net::globals::macAddress, ETH_ADDR_LEN); - + std::memcpy(p_icmp->ether.dst, p_icmp->ether.src, ETH_ADDR_LEN); + std::memcpy(p_icmp->ether.src, globals::netif_default.hwaddr, ETH_ADDR_LEN); // IPv4 p_icmp->ip4.id = static_cast(~p_icmp->ip4.id); - uint8_t dst[IPv4_ADDR_LEN]; - memcpy(dst, p_icmp->ip4.dst, IPv4_ADDR_LEN); - memcpy(p_icmp->ip4.dst, p_icmp->ip4.src, IPv4_ADDR_LEN); - memcpy(p_icmp->ip4.src, dst, IPv4_ADDR_LEN); + + const auto nIpDestination = net::memcpy_ip(p_icmp->ip4.dst); + + std::memcpy(p_icmp->ip4.dst, p_icmp->ip4.src, IPv4_ADDR_LEN); + + if (nIpDestination == globals::netif_default.secondary_ip.addr) { + net::memcpy_ip(p_icmp->ip4.src, globals::netif_default.secondary_ip.addr); + } else { + net::memcpy_ip(p_icmp->ip4.src, globals::netif_default.ip.addr); + } + p_icmp->ip4.chksum = 0; #if !defined (CHECKSUM_BY_HARDWARE) p_icmp->ip4.chksum = net_chksum(reinterpret_cast(&p_icmp->ip4), 20); //TODO @@ -66,7 +75,8 @@ __attribute__((hot)) void icmp_handle(struct t_icmp *p_icmp) { #if !defined (CHECKSUM_BY_HARDWARE) p_icmp->icmp.checksum = net_chksum(reinterpret_cast(&p_icmp->ip4), static_cast(__builtin_bswap16(p_icmp->ip4.len))); #endif - emac_eth_send(reinterpret_cast(p_icmp), (sizeof(struct ether_header) + __builtin_bswap16(p_icmp->ip4.len))); + emac_eth_send(reinterpret_cast(p_icmp), static_cast(sizeof(struct ether_header) + __builtin_bswap16(p_icmp->ip4.len))); } } } +} // namespace net diff --git a/lib-network/src/net/igmp.cpp b/lib-network/src/net/igmp.cpp index ac58a969..35456eec 100644 --- a/lib-network/src/net/igmp.cpp +++ b/lib-network/src/net/igmp.cpp @@ -2,7 +2,7 @@ * @file igmp.cpp * */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,20 +23,44 @@ * THE SOFTWARE. */ +#if defined (DEBUG_NET_IGMP) +# undef NDEBUG +#endif + +#if !defined (CONFIG_REMOTECONFIG_MINIMUM) +# pragma GCC push_options +# pragma GCC optimize ("O2") +# pragma GCC optimize ("no-tree-loop-distribute-patterns") +#endif + #include -#include +#include #include +#include + +#include "../../config/net_config.h" #include "net.h" +#include "netif.h" +#include "net/igmp.h" +#include "net/protocol/igmp.h" + +#include "net_memcpy.h" #include "net_private.h" -#include "../../config/net_config.h" +#include "hardware.h" + +#include "debug.h" /* * https://www.rfc-editor.org/rfc/rfc2236.html * Internet Group Management Protocol, Version 2 */ +namespace net { +#define IGMP_TMR_INTERVAL 100 /* Milliseconds */ +#define IGMP_JOIN_DELAYING_MEMBER_TMR (500 /IGMP_TMR_INTERVAL) + enum State { NON_MEMBER, DELAYING_MEMBER, IDLE_MEMBER }; @@ -57,23 +81,68 @@ static struct t_igmp s_leave SECTION_NETWORK ALIGNED; static uint8_t s_multicast_mac[ETH_ADDR_LEN] SECTION_NETWORK ALIGNED; static struct t_group_info s_groups[IGMP_MAX_JOINS_ALLOWED] SECTION_NETWORK ALIGNED; static uint16_t s_id SECTION_NETWORK ALIGNED; +static int32_t nTimerId; -namespace net { -namespace globals { -extern struct IpInfo ipInfo; -extern uint8_t macAddress[ETH_ADDR_LEN]; -} // namespace globals -} // namespace net +void igmp_set_ip() { + net::memcpy_ip(s_report.ip4.src, net::globals::netif_default.ip.addr); + net::memcpy_ip(s_leave.ip4.src, net::globals::netif_default.ip.addr); +} -static void _send_report(uint32_t nGroupAddress); +static void igmp_send_report(const uint32_t nGroupAddress) { + DEBUG_ENTRY + _pcast32 multicast_ip; -void igmp_set_ip() { - _pcast32 src; + multicast_ip.u32 = nGroupAddress; + + s_multicast_mac[3] = multicast_ip.u8[1] & 0x7F; + s_multicast_mac[4] = multicast_ip.u8[2]; + s_multicast_mac[5] = multicast_ip.u8[3]; - src.u32 = net::globals::ipInfo.ip.addr; + DEBUG_PRINTF(IPSTR " " MACSTR, IP2STR(nGroupAddress),MAC2STR(s_multicast_mac)); - memcpy(s_report.ip4.src, src.u8, IPv4_ADDR_LEN); - memcpy(s_leave.ip4.src, src.u8, IPv4_ADDR_LEN); + // Ethernet + std::memcpy(s_report.ether.dst, s_multicast_mac, ETH_ADDR_LEN); + // IPv4 + s_report.ip4.id = s_id; + std::memcpy(s_report.ip4.dst, multicast_ip.u8, IPv4_ADDR_LEN); + s_report.ip4.chksum = 0; + s_report.ip4.chksum = net_chksum(reinterpret_cast(&s_report.ip4), 24); //TODO + // IGMP + std::memcpy(s_report.igmp.report.igmp.group_address, multicast_ip.u8, IPv4_ADDR_LEN); + s_report.igmp.report.igmp.checksum = 0; + s_report.igmp.report.igmp.checksum = net_chksum(reinterpret_cast(&s_report.ip4), IPv4_IGMP_REPORT_HEADERS_SIZE); + + emac_eth_send(reinterpret_cast(&s_report), IGMP_REPORT_PACKET_SIZE); + + s_id++; + + DEBUG_EXIT +} + +static void igmp_start_timer(struct t_group_info &group, const uint32_t max_time) { + group.nTimer = (max_time > 2 ? (random() % max_time) : 1); + + if (group.nTimer == 0) { + group.nTimer = 1; + } +} + +static void igmp_timeout(struct t_group_info &group) { + if ((group.state == DELAYING_MEMBER) && (group.nGroupAddress != 0x010000e0)) { //FIXME all-systems + group.state = IDLE_MEMBER; + igmp_send_report(group.nGroupAddress); + } +} + +static void igmp_timer() { + for (auto &group : s_groups) { + if (group.nTimer > 0) { + group.nTimer--; + if (group.nTimer == 0) { + igmp_timeout(group); + } + } + } } void __attribute__((cold)) igmp_init() { @@ -84,7 +153,7 @@ void __attribute__((cold)) igmp_init() { s_multicast_mac[2] = 0x5E; // Ethernet - memcpy(s_report.ether.src, net::globals::macAddress, ETH_ADDR_LEN); + std::memcpy(s_report.ether.src, net::globals::netif_default.hwaddr, ETH_ADDR_LEN); s_report.ether.type = __builtin_bswap16(ETHER_TYPE_IPv4); // IPv4 @@ -108,7 +177,7 @@ void __attribute__((cold)) igmp_init() { s_leave.ether.dst[3] = 0x00; s_leave.ether.dst[4] = 0x00; s_leave.ether.dst[5] = 0x02; - memcpy(s_leave.ether.src, net::globals::macAddress, ETH_ADDR_LEN); + std::memcpy(s_leave.ether.src, net::globals::netif_default.hwaddr, ETH_ADDR_LEN); s_leave.ether.type = __builtin_bswap16(ETHER_TYPE_IPv4); // IPv4 @@ -129,14 +198,8 @@ void __attribute__((cold)) igmp_init() { s_leave.igmp.report.igmp.type = IGMP_TYPE_LEAVE; s_leave.igmp.report.igmp.max_resp_time = 0; - /* - * https://tldp.org/HOWTO/Multicast-HOWTO-2.html - * 224.0.0.1 is the all-hosts group. If you ping that group, - * all multicast capable hosts on the network should answer, - * as every multicast capable host must join that group - * at start-up on all it's multicast capable interfaces. - */ - _send_report(0x010000e0); + nTimerId = Hardware::Get()->SoftwareTimerAdd(IGMP_TMR_INTERVAL, igmp_timer); + assert(nTimerId >= 0); } void __attribute__((cold)) igmp_shutdown() { @@ -153,43 +216,8 @@ void __attribute__((cold)) igmp_shutdown() { DEBUG_EXIT } -static void _send_report(const uint32_t nGroupAddress) { - DEBUG_ENTRY - _pcast32 multicast_ip; - - multicast_ip.u32 = nGroupAddress; - - s_multicast_mac[3] = multicast_ip.u8[1] & 0x7F; - s_multicast_mac[4] = multicast_ip.u8[2]; - s_multicast_mac[5] = multicast_ip.u8[3]; - - DEBUG_PRINTF(IPSTR " " MACSTR, IP2STR(nGroupAddress),MAC2STR(s_multicast_mac)); - - // Ethernet - memcpy(s_report.ether.dst, s_multicast_mac, ETH_ADDR_LEN); - // IPv4 - s_report.ip4.id = s_id; - memcpy(s_report.ip4.dst, multicast_ip.u8, IPv4_ADDR_LEN); - s_report.ip4.chksum = 0; - s_report.ip4.chksum = net_chksum(reinterpret_cast(&s_report.ip4), 24); //TODO - // IGMP - memcpy(s_report.igmp.report.igmp.group_address, multicast_ip.u8, IPv4_ADDR_LEN); - s_report.igmp.report.igmp.checksum = 0; - s_report.igmp.report.igmp.checksum = net_chksum(reinterpret_cast(&s_report.ip4), IPv4_IGMP_REPORT_HEADERS_SIZE); - - emac_eth_send(reinterpret_cast(&s_report), IGMP_REPORT_PACKET_SIZE); - - s_id++; - - DEBUG_EXIT -} - -static void _send_leave(const uint32_t nGroupAddress) { +static void igmp_send_leave(const uint32_t nGroupAddress) { DEBUG_ENTRY - _pcast32 multicast_ip; - - multicast_ip.u32 = nGroupAddress; - DEBUG_PRINTF(IPSTR " " MACSTR, IP2STR(nGroupAddress), MAC2STR(s_multicast_mac)); // IPv4 @@ -199,7 +227,7 @@ static void _send_leave(const uint32_t nGroupAddress) { s_leave.ip4.chksum = net_chksum(reinterpret_cast(&s_leave.ip4), 24); //TODO #endif // IGMP - memcpy(s_leave.igmp.report.igmp.group_address, multicast_ip.u8, IPv4_ADDR_LEN); + net::memcpy_ip(s_leave.igmp.report.igmp.group_address, nGroupAddress); s_leave.igmp.report.igmp.checksum = 0; #if !defined (CHECKSUM_BY_HARDWARE) s_leave.igmp.report.igmp.checksum = net_chksum(reinterpret_cast(&s_leave.ip4), IPv4_IGMP_REPORT_HEADERS_SIZE); @@ -251,16 +279,11 @@ __attribute__((hot)) void igmp_handle(struct t_igmp *p_igmp) { DEBUG_EXIT } -void igmp_timer() { - for (auto& group : s_groups) { - if ((group.state == DELAYING_MEMBER) && (group.nTimer > 0)) { - group.nTimer--; - - if (group.nTimer == 0) { - _send_report(group.nGroupAddress); - group.state = IDLE_MEMBER; - } - } +static void igmp_delaying_member(struct t_group_info &group, const uint32_t maxresp) { + if ((group.state == IDLE_MEMBER) + || ((group.state == DELAYING_MEMBER) && ((group.nTimer == 0) || (maxresp < group.nTimer)))) { + igmp_start_timer(group, maxresp); + group.state = DELAYING_MEMBER; } } @@ -286,7 +309,7 @@ void igmp_join(uint32_t nGroupAddress) { s_groups[i].state = DELAYING_MEMBER; s_groups[i].nTimer = 2; // TODO - _send_report(nGroupAddress); + igmp_send_report(nGroupAddress); DEBUG_EXIT return; @@ -306,7 +329,7 @@ void igmp_leave(uint32_t nGroupAddress) { for (auto& group : s_groups) { if (group.nGroupAddress == nGroupAddress) { - _send_leave(group.nGroupAddress); + igmp_send_leave(group.nGroupAddress); group.nGroupAddress = 0; group.state = NON_MEMBER; @@ -324,4 +347,10 @@ void igmp_leave(uint32_t nGroupAddress) { DEBUG_EXIT } +void igmp_report_groups() { + for (auto& group : s_groups) { + igmp_delaying_member(group, IGMP_JOIN_DELAYING_MEMBER_TMR); + } +} +} // namespace net // <--- diff --git a/lib-network/src/net/ip.cpp b/lib-network/src/net/ip.cpp index e697459c..b2f3c6bf 100644 --- a/lib-network/src/net/ip.cpp +++ b/lib-network/src/net/ip.cpp @@ -2,7 +2,7 @@ * @file ip.cpp * */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,13 +23,26 @@ * THE SOFTWARE. */ +#if defined (DEBUG_NET_IP) +# undef NDEBUG +#endif + +#if !defined (CONFIG_REMOTECONFIG_MINIMUM) +# pragma GCC push_options +# pragma GCC optimize ("O2") +# pragma GCC optimize ("no-tree-loop-distribute-patterns") +#endif + #include +#include "../../config/net_config.h" + #include "net.h" #include "net_private.h" -#include "../../config/net_config.h" +#include "debug.h" +namespace net { void ip_set_ip() { udp_set_ip(); igmp_set_ip(); @@ -40,16 +53,9 @@ void __attribute__((cold)) ip_init() { udp_init(); igmp_init(); +#if defined (ENABLE_HTTPD) tcp_init(); - - DEBUG_EXIT -} - -void __attribute__((cold)) ip_shutdown() { - DEBUG_ENTRY - - tcp_shutdown(); - igmp_shutdown(); +#endif DEBUG_EXIT } @@ -85,3 +91,4 @@ __attribute__((hot)) void ip_handle(struct t_ip4 *p_ip4) { break; } } +} // namespace net diff --git a/lib-network/src/net/net.cpp b/lib-network/src/net/net.cpp old mode 100644 new mode 100755 index 0afe1e2b..ae8402e2 --- a/lib-network/src/net/net.cpp +++ b/lib-network/src/net/net.cpp @@ -2,7 +2,7 @@ * @file net.cpp * */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,200 +23,160 @@ * THE SOFTWARE. */ +#if defined (DEBUG_NET_NET) +# if defined (NDEBUG) +# undef NDEBUG +# endif +#endif + +#if !defined (CONFIG_REMOTECONFIG_MINIMUM) +# pragma GCC push_options +# pragma GCC optimize ("O2") +# pragma GCC optimize ("no-tree-loop-distribute-patterns") +#endif + #include #include +#include "../../config/net_config.h" + #include "net.h" #include "net_private.h" -#include "net_packets.h" -#include "net_debug.h" -#include "../../config/net_config.h" +#include "netif.h" +#include "net/acd.h" +#include "net/dhcp.h" + +#include "debug.h" + +static struct net::acd::Acd s_acd; + +namespace network { +__attribute__((weak)) void mdns_shutdown() {} +} // namespace network namespace net { namespace globals { -struct IpInfo ipInfo ALIGNED; uint32_t nBroadcastMask; uint32_t nOnNetworkMask; -uint8_t macAddress[ETH_ADDR_LEN] ALIGNED; } // namespace globals -} // namespace net - -static uint8_t *s_p; -static bool s_isDhcp = false; - -static void refresh_and_init(struct IpInfo *pIpInfo, bool doInit) { - net::globals::ipInfo.broadcast_ip.addr = net::globals::ipInfo.ip.addr | ~net::globals::ipInfo.netmask.addr; - - net::globals::nBroadcastMask = ~(net::globals::ipInfo.netmask.addr); - net::globals::nOnNetworkMask = net::globals::ipInfo.ip.addr & net::globals::ipInfo.netmask.addr; - - if (doInit) { - arp_init(); - ip_set_ip(); - } - - const auto *pSrc = reinterpret_cast(&net::globals::ipInfo); - auto *pDst = reinterpret_cast(pIpInfo); - - memcpy(pDst, pSrc, sizeof(struct IpInfo)); -} - -void set_secondary_ip() { - net::globals::ipInfo.ip.addr = net::globals::ipInfo.secondary_ip.addr; - net::globals::ipInfo.netmask.addr = 255; - net::globals::ipInfo.gw.addr = net::globals::ipInfo.ip.addr; -} +#if defined (CONFIG_ENET_ENABLE_PTP) +void ptp_init(); +void ptp_handle(const uint8_t *, const uint32_t); +#endif -void __attribute__((cold)) net_init(const uint8_t *const pMacAddress, struct IpInfo *pIpInfo, const char *pHostname, bool *bUseDhcp, bool *isZeroconfUsed) { +void net_shutdown() { DEBUG_ENTRY - memcpy(net::globals::macAddress, pMacAddress, ETH_ADDR_LEN); - - const auto *pSrc = reinterpret_cast(pIpInfo); - auto *pDst = reinterpret_cast(&net::globals::ipInfo); - - memcpy(pDst, pSrc, sizeof(struct IpInfo)); - - net::globals::ipInfo.secondary_ip.addr = 2 - + ((static_cast(net::globals::macAddress[3])) << 8) - + ((static_cast(net::globals::macAddress[4])) << 16) - + ((static_cast(net::globals::macAddress[5])) << 24); - - - if (net::globals::ipInfo.ip.addr == 0) { - set_secondary_ip(); - } - /* - * The macAddress is set - */ - ip_init(); - - *isZeroconfUsed = false; - - if (*bUseDhcp) { - if (dhcp_client(pHostname) < 0) { - *bUseDhcp = false; - DEBUG_PUTS("DHCP Client failed"); - *isZeroconfUsed = rfc3927(); - } - } - - refresh_and_init(pIpInfo, true); - - s_isDhcp = *bUseDhcp; - - if (!arp_do_probe()) { - DEBUG_PRINTF(IPSTR " " MACSTR, IP2STR(net::globals::ipInfo.ip.addr), MAC2STR(net::globals::macAddress)); - arp_send_announcement(); - } else { - console_error("IP Conflict!\n"); - } + net::netif_set_link_down(); DEBUG_EXIT } -void __attribute__((cold)) net_shutdown() { - ip_shutdown(); +static void primary_ip_conflict_callback(net::acd::Callback callback) { + auto &netif = net::globals::netif_default; - if (s_isDhcp) { - dhcp_client_release(); + switch (callback) { + case net::acd::Callback::ACD_IP_OK: + if (s_acd.ipaddr.addr == netif.secondary_ip.addr) { + net_set_secondary_ip(); + } else { + net::netif_set_ipaddr(s_acd.ipaddr); + } + dhcp_inform(); + netif_set_flags(netif::NETIF_FLAG_STATICIP_OK); + break; + case net::acd::Callback::ACD_RESTART_CLIENT: + break; + case net::acd::Callback::ACD_DECLINE: + netif_clear_flags(netif::NETIF_FLAG_STATICIP_OK); + break; + default: + break; } } -void net_set_ip(struct IpInfo *pIpInfo) { - net::globals::ipInfo.ip.addr = pIpInfo->ip.addr; +void net_set_primary_ip(const ip4_addr_t ipaddr) { + auto &netif = net::globals::netif_default; - if (net::globals::ipInfo.ip.addr == 0) { - set_secondary_ip(); - } + net::dhcp_release_and_stop(); - refresh_and_init(pIpInfo, true); + acd_add(&s_acd, primary_ip_conflict_callback); - if (!arp_do_probe()) { - DEBUG_PRINTF(IPSTR " " MACSTR, IP2STR(net::globals::ipInfo.ip.addr), MAC2STR(net::globals::macAddress)); - arp_send_announcement(); + if (ipaddr.addr == 0) { + acd_start(&s_acd, netif.secondary_ip); } else { - console_error("IP Conflict!\n"); + acd_start(&s_acd, ipaddr); } } -void net_set_netmask(struct IpInfo *pIpInfo) { - net::globals::ipInfo.netmask.addr = pIpInfo->netmask.addr; - - refresh_and_init(pIpInfo, false); -} - -void net_set_gw(struct IpInfo *pIpInfo) { - net::globals::ipInfo.gw.addr = pIpInfo->gw.addr; - - ip_set_ip(); +void net_set_secondary_ip() { + auto &netif = net::globals::netif_default; + ip4_addr_t netmask; + netmask.addr = 255; + net::netif_set_addr(netif.secondary_ip, netmask, netif.secondary_ip); } -bool net_set_dhcp(struct IpInfo *pIpInfo, const char *const pHostname, bool *isZeroconfUsed) { - bool isDhcp = false; - *isZeroconfUsed = false; - - if (dhcp_client(pHostname) < 0) { - DEBUG_PUTS("DHCP Client failed"); - *isZeroconfUsed = rfc3927(); - } else { - isDhcp = true; - } +void __attribute__((cold)) net_init(const net::Link link, ip4_addr_t ipaddr, ip4_addr_t netmask, ip4_addr_t gw, bool &bUseDhcp) { + DEBUG_ENTRY + globals::netif_default.secondary_ip.addr = 2 + + ((static_cast(globals::netif_default.hwaddr[3])) << 8) + + ((static_cast(globals::netif_default.hwaddr[4])) << 16) + + ((static_cast(globals::netif_default.hwaddr[5])) << 24); - refresh_and_init(pIpInfo, true); + net::arp_init(); + ip_init(); - s_isDhcp = isDhcp; + if (net::Link::STATE_UP == link) { + net::netif_set_flags(net::netif::NETIF_FLAG_LINK_UP); - if (!arp_do_probe()) { - DEBUG_PRINTF(IPSTR " " MACSTR, IP2STR(net::globals::ipInfo.ip.addr), MAC2STR(net::globals::macAddress)); - arp_send_announcement(); + if (bUseDhcp) { + dhcp_start(); + } else { +// if (ipaddr.addr == 0) { +// net_set_secondary_ip(); +// } else { +// net::netif_set_addr(ipaddr, netmask, gw); +// } +// dhcp_inform(); + if (ipaddr.addr != 0) { + net::netif_set_netmask(netmask); + net::netif_set_gw(gw); + } + net_set_primary_ip(ipaddr); + } } else { - console_error("IP Conflict!\n"); + net::netif_clear_flags(net::netif::NETIF_FLAG_LINK_UP); } - return isDhcp; -} - -void net_dhcp_release() { - dhcp_client_release(); - s_isDhcp = false; -} - -bool net_set_zeroconf(struct IpInfo *pIpInfo) { - const auto b = rfc3927(); - - if (b) { - refresh_and_init(pIpInfo, true); - - s_isDhcp = false; - - DEBUG_PRINTF(IPSTR " " MACSTR, IP2STR(net::globals::ipInfo.ip.addr), MAC2STR(net::globals::macAddress)); - arp_send_announcement(); +#if defined (CONFIG_ENET_ENABLE_PTP) + net::ptp_init(); +#endif - return true; - } - - DEBUG_PUTS("Zeroconf failed"); - return false; + DEBUG_EXIT } __attribute__((hot)) void net_handle() { + uint8_t *s_p; const auto nLength = emac_eth_recv(&s_p); if (__builtin_expect((nLength > 0), 0)) { const auto *const eth = reinterpret_cast(s_p); - if (eth->type == __builtin_bswap16(ETHER_TYPE_IPv4)) { - ip_handle(reinterpret_cast(s_p)); - } else if (eth->type == __builtin_bswap16(ETHER_TYPE_ARP)) { - arp_handle(reinterpret_cast(s_p)); - } else { - DEBUG_PRINTF("type %04x is not implemented", __builtin_bswap16(eth->type)); - } +#if defined (CONFIG_ENET_ENABLE_PTP) + if (eth->type == __builtin_bswap16(ETHER_TYPE_PTP)) { + net::ptp_handle(const_cast(s_p), nLength); + } else +#endif + if (eth->type == __builtin_bswap16(ETHER_TYPE_IPv4)) { + ip_handle(reinterpret_cast(s_p)); + } else if (eth->type == __builtin_bswap16(ETHER_TYPE_ARP)) { + net::arp_handle(reinterpret_cast(s_p)); + } else { + DEBUG_PRINTF("type %04x is not implemented", __builtin_bswap16(eth->type)); + } emac_free_pkt(); } - - net_timers_run(); } +} // namespace net diff --git a/lib-network/src/net/net_chksum.cpp b/lib-network/src/net/net_chksum.cpp index 75fcb516..408ebaa7 100644 --- a/lib-network/src/net/net_chksum.cpp +++ b/lib-network/src/net/net_chksum.cpp @@ -2,7 +2,7 @@ * @file net_chksum.cpp * */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,10 +23,13 @@ * THE SOFTWARE. */ -#include +#pragma GCC push_options +#pragma GCC optimize ("O2") +#pragma GCC optimize ("no-tree-loop-distribute-patterns") -#include "net_private.h" +#include +namespace net { uint16_t net_chksum(const void *data, uint32_t len) { auto *ptr = reinterpret_cast(data); uint32_t sum = 0; @@ -49,3 +52,4 @@ uint16_t net_chksum(const void *data, uint32_t len) { return static_cast(~sum); } +} // namespace net diff --git a/lib-network/src/net/net_memcpy.h b/lib-network/src/net/net_memcpy.h index c7a70bd0..ca4f1d55 100644 --- a/lib-network/src/net/net_memcpy.h +++ b/lib-network/src/net/net_memcpy.h @@ -2,7 +2,7 @@ * @file net_memcpy.h * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,19 +27,23 @@ #include #include -inline void *net_memcpy(void *__restrict__ dest, void const *__restrict__ src, size_t n) { - auto *plDst = reinterpret_cast(dest); - auto const *plSrc = reinterpret_cast(src); +#include "net/protocol/ip4.h" - if (((reinterpret_cast(src) & 0x3) == 0) && ((reinterpret_cast(dest) & 0x3) == 0)) { - while (n >= 4) { +namespace net { +inline void* memcpy(void *__restrict__ dest, void const *__restrict__ src, size_t n) { + auto *plDst = reinterpret_cast(dest); + auto const *plSrc = reinterpret_cast(src); + + if (((reinterpret_cast(src) & (sizeof(uintptr_t) - 1)) == 0) + && ((reinterpret_cast(dest) & (sizeof(uintptr_t) - 1)) == 0)) { + while (n >= sizeof(uintptr_t)) { *plDst++ = *plSrc++; - n -= 4; + n -= sizeof(uintptr_t); } } - auto *pcDst = reinterpret_cast(plDst); - auto const *pcSrc = reinterpret_cast(plSrc); + auto *pcDst = reinterpret_cast(plDst); + auto const *pcSrc = reinterpret_cast(plSrc); while (n--) { *pcDst++ = *pcSrc++; @@ -48,4 +52,64 @@ inline void *net_memcpy(void *__restrict__ dest, void const *__restrict__ src, s return dest; } +inline void memcpy_ip(uint8_t *pIpAddress, const uint32_t nIpAddress) { +#ifdef __ARM_ARCH_7A__ + // Ensure destination pointer is aligned + if ((reinterpret_cast(pIpAddress) & ((sizeof(uint32_t) - 1))) == 0) { + // Destination pointer is already aligned, perform fast copy + *reinterpret_cast(pIpAddress) = nIpAddress; + } else +#endif + { // Destination pointer is not aligned, copy byte by byte + typedef union pcast32 { + uint32_t u32; + uint8_t u8[4]; + } _pcast32; + + _pcast32 src; + src.u32 = nIpAddress; +#ifdef __ARM_ARCH_7A__ + volatile auto *pSrc = src.u8; + volatile auto *pDst = pIpAddress; +#else + auto *pSrc = src.u8; + auto *pDst = pIpAddress; +#endif + for (uint32_t i = 0; i < IPv4_ADDR_LEN; i++) { + pDst[i] = pSrc[i]; + } + } +} + +inline uint32_t memcpy_ip(const uint8_t *pIpAddress) { +#ifdef __ARM_ARCH_7A__ + // Ensure destination pointer is aligned + if ((reinterpret_cast(pIpAddress) & ((sizeof(uint32_t) - 1))) == 0) { + // Destination pointer is already aligned, perform fast copy + return *reinterpret_cast(pIpAddress); + } else +#endif + { // Destination pointer is not aligned, copy byte by byte + typedef union pcast32 { + uint32_t u32; + uint8_t u8[4]; + } _pcast32; + + _pcast32 src; +#ifdef __ARM_ARCH_7A__ + volatile auto *pSrc = pIpAddress; + volatile auto *pDst = src.u8; +#else + auto *pSrc = pIpAddress; + auto *pDst = src.u8; +#endif + for (uint32_t i = 0; i < IPv4_ADDR_LEN; i++) { + pDst[i] = pSrc[i]; + } + + return src.u32; + } +} +} // namespace net + #endif /* NET_MEMCPY_H_ */ diff --git a/lib-network/src/net/net_packets.h b/lib-network/src/net/net_packets.h deleted file mode 100644 index d3b0f3e9..00000000 --- a/lib-network/src/net/net_packets.h +++ /dev/null @@ -1,225 +0,0 @@ -/** - * @file net_packets.h - * - */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef NET_PACKETS_H_ -#define NET_PACKETS_H_ - -#include - -#if !defined (PACKED) -# define PACKED __attribute__((packed)) -#endif - -enum MTU { - MTU_SIZE = 1500 -}; - -enum ETHER_TYPE { - ETHER_TYPE_IPv4 = 0x0800, - ETHER_TYPE_ARP = 0x0806 -}; - -enum ETH_ADDR { - ETH_ADDR_LEN = 6 -}; - -enum IPv4_ADDR { - IPv4_ADDR_LEN = 4 -}; - -enum IPv4_PROTO { - IPv4_PROTO_ICMP = 1, - IPv4_PROTO_IGMP = 2, - IPv4_PROTO_TCP = 6, - IPv4_PROTO_UDP = 17 -}; - -enum IPv4_FLAG { - IPv4_FLAG_LF = 0x0000, - IPv4_FLAG_MF = 0x2000, - IPv4_FLAG_DF = 0x4000 -}; - -#define IPv4_BROADCAST 0xffffffff - -enum ARP_HARDWARE_TYPE { - ARP_HWTYPE_ETHERNET = 1 -}; - -enum ARP_PROTOCOL_TYPE { - ARP_PRTYPE_IPv4 = ETHER_TYPE_IPv4 -}; - -enum ARP_HARDWARE { - ARP_HARDWARE_SIZE = ETH_ADDR_LEN -}; - -enum ARP_PROTOCOL { - ARP_PROTOCOL_SIZE = IPv4_ADDR_LEN -}; - -enum ARP_OPCODE { - ARP_OPCODE_RQST = 1, - ARP_OPCODE_REPLY = 2 -}; - -enum IGMP_TYPE { - IGMP_TYPE_QUERY = 0x11, - IGMP_TYPE_REPORT = 0x16, - IGMP_TYPE_LEAVE = 0x17 -}; - -enum ICMP_TYPE { - ICMP_TYPE_ECHO_REPLY = 0, - ICMP_TYPE_ECHO = 8 -}; - -enum ICMP_CODE { - ICMP_CODE_ECHO = 0 -}; - -struct ether_header { - uint8_t dst[ETH_ADDR_LEN]; /* 6 */ - uint8_t src[ETH_ADDR_LEN]; /* 12 */ - uint16_t type; /* 14 */ -} PACKED; - -struct arp_packet { - uint16_t hardware_type; /* 2 */ - uint16_t protocol_type; /* 4 */ - uint8_t hardware_size; /* 5 */ - uint8_t protocol_size; /* 6 */ - uint16_t opcode; /* 8 */ - uint8_t sender_mac[ETH_ADDR_LEN];/*14 */ - uint8_t sender_ip[IPv4_ADDR_LEN];/* 18 */ - uint8_t target_mac[ETH_ADDR_LEN];/*24 */ - uint8_t target_ip[IPv4_ADDR_LEN];/* 28 */ - uint8_t padding[18]; /* 46 */ /* +14 = 60 */ -} PACKED; - -struct ip4_header { - uint8_t ver_ihl; /* 1 */ - uint8_t tos; /* 2 */ - uint16_t len; /* 4 */ - uint16_t id; /* 6 */ - uint16_t flags_froff; /* 8 */ - uint8_t ttl; /* 9 */ - uint8_t proto; /* 10 */ - uint16_t chksum; /* 12 */ - uint8_t src[IPv4_ADDR_LEN]; /* 16 */ - uint8_t dst[IPv4_ADDR_LEN]; /* 20 */ -} PACKED; - -struct t_igmp_packet { - uint8_t type; - uint8_t max_resp_time; - uint16_t checksum; - uint8_t group_address[IPv4_ADDR_LEN]; -} PACKED; - -struct t_icmp_packet { - uint8_t type; /* 1 */ - uint8_t code; /* 2 */ - uint16_t checksum; /* 4 */ - uint8_t parameter[4]; /* 8 */ -#define ICMP_HEADER_SIZE 8 -#define ICMP_PAYLOAD_SIZE (MTU_SIZE - ICMP_HEADER_SIZE - sizeof(struct ip4_header)) - uint8_t payload[ICMP_PAYLOAD_SIZE]; -} PACKED; - -struct t_udp_packet { - uint16_t source_port; /* 2 */ - uint16_t destination_port; /* 4 */ - uint16_t len; /* 6 */ - uint16_t checksum; /* 8 */ -#define UDP_HEADER_SIZE 8 -#define UDP_DATA_SIZE (MTU_SIZE - UDP_HEADER_SIZE - sizeof(struct ip4_header)) - uint8_t data[UDP_DATA_SIZE]; -}PACKED; - -struct t_tcp_packet { - uint16_t srcpt; /* 2 */ - uint16_t dstpt; /* 4 */ - uint32_t seqnum; /* 8 */ - uint32_t acknum; /* 12 */ - uint8_t offset; /* 13 */ - uint8_t control; /* 14 */ - uint16_t window; /* 16 */ - uint16_t checksum; /* 18 */ - uint16_t urgent; /* 20 */ -#define TCP_HEADER_SIZE 20 -#define TCP_DATA_SIZE (MTU_SIZE - TCP_HEADER_SIZE - sizeof(struct ip4_header) - 20U) - uint8_t data[TCP_DATA_SIZE]; -} PACKED; - -struct t_arp { - struct ether_header ether; - struct arp_packet arp; -} PACKED; - -struct t_ip4 { - struct ether_header ether; - struct ip4_header ip4; -} PACKED; - -struct t_igmp { - struct ether_header ether; - struct ip4_header ip4; - union { - struct { - uint32_t ip4_options; - struct t_igmp_packet igmp; - } report; - struct t_igmp_packet igmp; - } igmp; -} PACKED; - -struct t_icmp { - struct ether_header ether; - struct ip4_header ip4; - struct t_icmp_packet icmp; -} PACKED; - -struct t_udp { - struct ether_header ether; - struct ip4_header ip4; - struct t_udp_packet udp; -} PACKED; - -struct t_tcp { - struct ether_header ether; - struct ip4_header ip4; - struct t_tcp_packet tcp; -} PACKED; - -#define IPv4_UDP_HEADERS_SIZE (sizeof(struct ip4_header) + UDP_HEADER_SIZE) /* IP | UDP */ -#define UDP_PACKET_HEADERS_SIZE (sizeof(struct ether_header) + IPv4_UDP_HEADERS_SIZE) /* ETH | IP | UDP */ - -#define IPv4_IGMP_REPORT_HEADERS_SIZE (sizeof(struct t_igmp) - sizeof(struct ether_header)) -#define IGMP_REPORT_PACKET_SIZE (sizeof(struct t_igmp)) - -#define IPv4_ICMP_HEADERS_SIZE (sizeof(struct t_icmp) - sizeof(struct ether_header)) - -#endif /* NET_PACKETS_H_ */ diff --git a/lib-network/src/net/net_platform.h b/lib-network/src/net/net_platform.h index 79f9343c..8f5ce447 100644 --- a/lib-network/src/net/net_platform.h +++ b/lib-network/src/net/net_platform.h @@ -31,7 +31,7 @@ * https://www.gd32-dmx.org/memory.html */ # include "gd32.h" -# if defined (GD32F207RG) || defined (GD32F4XX) +# if defined (GD32F207RG) || defined (GD32F4XX) || defined(GD32H7XX) # define SECTION_NETWORK __attribute__ ((section (".network"))) # else # define SECTION_NETWORK diff --git a/lib-network/src/net/net_private.h b/lib-network/src/net/net_private.h old mode 100755 new mode 100644 index 93c4da72..336c4c58 --- a/lib-network/src/net/net_private.h +++ b/lib-network/src/net/net_private.h @@ -2,7 +2,7 @@ * @file net_private.h * */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,50 +28,47 @@ #include -#include "net_packets.h" #include "net_platform.h" -#include "net_debug.h" -#include "dhcp_internal.h" -#include "tftp_internal.h" -#include "ntp_internal.h" +#include "net/arp.h" +#include "net/protocol/icmp.h" +#include "net/protocol/igmp.h" +#include "net/protocol/udp.h" +#include "net/protocol/tcp.h" #ifndef ALIGNED # define ALIGNED __attribute__ ((aligned (4))) #endif -extern "C" { -int console_error(const char *); -void emac_eth_send(void *, int); +namespace net::arp { +enum class EthSend { + IS_NORMAL +#if defined CONFIG_ENET_ENABLE_PTP + , IS_TIMESTAMP +#endif +}; +} // namespace net::arp + +extern "C" void console_error(const char *); + +void emac_eth_send(void *, uint32_t); +#if defined CONFIG_ENET_ENABLE_PTP +void emac_eth_send_timestamp(void *, uint32_t); +#endif int emac_eth_recv(uint8_t **); -void emac_free_pkt(void); -} +void emac_free_pkt(); +namespace net { void net_handle(); uint16_t net_chksum(const void *, uint32_t); void net_timers_run(); -void arp_init(); -void arp_handle(struct t_arp *); -bool arp_do_probe(); -void arp_cache_init(); -void arp_send_request(uint32_t); -void arp_send_probe(); -void arp_send_announcement(); -void arp_cache_update(const uint8_t *, uint32_t); -uint32_t arp_cache_lookup(uint32_t, uint8_t *); - void ip_init(); void ip_set_ip(); void ip_shutdown(); void ip_handle(struct t_ip4 *); -int dhcp_client(const char *); -void dhcp_client_release(); - -bool rfc3927(); - void udp_init(); void udp_set_ip(); void udp_handle(struct t_udp *); @@ -81,7 +78,6 @@ void igmp_init(); void igmp_set_ip(); void igmp_handle(struct t_igmp *); void igmp_shutdown(); -void igmp_timer(); void icmp_handle(struct t_icmp *); void icmp_shutdown(); @@ -90,5 +86,6 @@ void tcp_init(); void tcp_run(); void tcp_handle(struct t_tcp *); void tcp_shutdown(); +} // namespace net #endif /* NET_PRIVATE_H_ */ diff --git a/lib-network/src/net/net_ptp.cpp b/lib-network/src/net/net_ptp.cpp new file mode 100755 index 00000000..8a4b6951 --- /dev/null +++ b/lib-network/src/net/net_ptp.cpp @@ -0,0 +1,35 @@ +/** + * @file net_ptp.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +namespace net { +namespace globals { +uint32_t ptpTimestamp[2]; +} // namespace globals + +void __attribute__((weak)) ptp_handle([[maybe_unused]] const uint8_t *pBuffer, [[maybe_unused]] const uint32_t nLength) {} +void __attribute__((weak)) ptp_run() {} +} // namespace net diff --git a/lib-network/src/net/netif.cpp b/lib-network/src/net/netif.cpp new file mode 100755 index 00000000..975b1e6f --- /dev/null +++ b/lib-network/src/net/netif.cpp @@ -0,0 +1,306 @@ +/** + * @file netif.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#if defined (DEBUG_NET_NETIF) +# undef NDEBUG +#endif + +#include + +#include "netif.h" +#include "net/acd.h" +#include "net/autoip.h" +#include "net/dhcp.h" +#include "net/igmp.h" + +#include "debug.h" + +namespace net { +namespace globals { +struct netif netif_default; +extern uint32_t nBroadcastMask; +extern uint32_t nOnNetworkMask; +} // namespace globals + +extern void arp_init(); +extern void ip_set_ip(); + +static netif_ext_callback_fn callback_fn; + +static void default_callback([[maybe_unused]] const uint16_t reason, [[maybe_unused]] const netif_ext_callback_args_t* args) { + DEBUG_PRINTF("%u", reason); +} + +void netif_init() { + auto &netif = net::globals::netif_default; + + netif.ip.addr = 0; + netif.netmask.addr = 0; + netif.gw.addr = 0; + netif.broadcast_ip.addr = 0; + netif.secondary_ip.addr = 2 + + ((static_cast(netif.hwaddr[3])) << 8) + + ((static_cast(netif.hwaddr[4])) << 16) + + ((static_cast(netif.hwaddr[5])) << 24); + netif.flags = 0; + netif.dhcp = nullptr; + netif.acd = nullptr; + netif.autoip = nullptr; + + callback_fn = &default_callback; + + net::arp_init(); +} + +static void netif_do_update_globals() { + auto &netif = net::globals::netif_default; + netif.broadcast_ip.addr = (netif.ip.addr | ~netif.netmask.addr); + + globals::nBroadcastMask = ~(netif.netmask.addr); + globals::nOnNetworkMask =netif.ip.addr & netif.netmask.addr; + + ip_set_ip(); +} + +static void netif_do_ip_addr_changed([[maybe_unused]] const ip4_addr_t old_addr,[[maybe_unused]] const ip4_addr_t new_addr) { +// tcp_netif_ip_addr_changed(old_addr, new_addr); +// udp_netif_ip_addr_changed(old_addr, new_addr); + ip_set_ip(); +} + +static void netif_issue_reports() { + const auto &netif = net::globals::netif_default; + + if (!(netif.flags & netif::NETIF_FLAG_LINK_UP)) { + return; + } + + if (netif.ip.addr != 0) { + igmp_report_groups(); + } +} + +static bool netif_do_set_ipaddr(const ip4_addr_t ipaddr, ip4_addr_t &old_addr) { + DEBUG_ENTRY + auto &netif = net::globals::netif_default; + + DEBUG_PRINTF(IPSTR " " IPSTR, IP2STR(ipaddr.addr), IP2STR(netif.ip.addr)); + + // Update the address if it's different + if (ipaddr.addr != netif.ip.addr) { + old_addr.addr = netif.ip.addr; + + netif_do_ip_addr_changed(old_addr, ipaddr); + acd_netif_ip_addr_changed(old_addr, ipaddr); + + netif.ip.addr = ipaddr.addr; + + netif_do_update_globals(); + netif_issue_reports(); + + DEBUG_EXIT + return true; // address changed + } + + DEBUG_EXIT + return false; // address unchanged +} + +static bool netif_do_set_netmask(const ip4_addr_t netmask, ip4_addr_t &old_nm) { + DEBUG_ENTRY + auto &netif = net::globals::netif_default; + + if (netmask.addr != netif.netmask.addr) { + old_nm.addr = netif.netmask.addr; + netif.netmask.addr = netmask.addr; + + netif_do_update_globals(); + + DEBUG_EXIT + return true; // netmask changed + } + + DEBUG_EXIT + return false; // netmask unchanged +} + +static bool netif_do_set_gw(const ip4_addr_t gw, ip4_addr_t &old_gw) { + DEBUG_ENTRY + auto &netif = net::globals::netif_default; + + if (gw.addr != netif.gw.addr) { + old_gw.addr = netif.gw.addr; + netif.gw.addr = gw.addr; + + DEBUG_EXIT + return true; // gateway changed + } + + DEBUG_EXIT + return false; // gateway unchanged +} + +void netif_set_ipaddr(const ip4_addr_t ipaddr) { + ip4_addr_t old_addr; + + if (netif_do_set_ipaddr(ipaddr, old_addr)) { + netif_ext_callback_args_t args; + args.ipv4_changed.old_address.addr = old_addr.addr; + callback_fn(NetifReason::NSC_IPV4_ADDRESS_CHANGED, &args); + } +} + +void netif_set_netmask(const ip4_addr_t netmask) { + ip4_addr_t old_nm; + + if (netif_do_set_netmask(netmask, old_nm)) { + netif_ext_callback_args_t args; + args.ipv4_changed.old_netmask = old_nm; + callback_fn(NetifReason::NSC_IPV4_NETMASK_CHANGED, &args); + } +} + +void netif_set_gw(const ip4_addr_t gw) { + ip4_addr_t old_gw; + + if (netif_do_set_gw(gw, old_gw)) { + netif_ext_callback_args_t args; + args.ipv4_changed.old_gw = old_gw; + callback_fn(NetifReason::NSC_IPV4_GATEWAY_CHANGED, &args); + } +} + +void netif_set_addr(const ip4_addr_t ipaddr, const ip4_addr_t netmask, const ip4_addr_t gw) { + DEBUG_ENTRY + DEBUG_PRINTF(IPSTR " " IPSTR " " IPSTR, IP2STR(ipaddr.addr), IP2STR(netmask.addr), IP2STR(gw.addr)); + + auto change_reason = NetifReason::NSC_NONE; + netif_ext_callback_args_t cb_args; + + ip4_addr_t old_addr; + ip4_addr_t old_nm; + ip4_addr_t old_gw; + + const auto remove = (ipaddr.addr == 0); + + if (remove) { + /* when removing an address, we have to remove it *before* changing netmask/gw + to ensure that tcp RST segment can be sent correctly */ + if (netif_do_set_ipaddr(ipaddr, old_addr)) { + change_reason |= NetifReason::NSC_IPV4_ADDRESS_CHANGED; + cb_args.ipv4_changed.old_address.addr = old_addr.addr; + } + } + + if (netif_do_set_netmask(netmask, old_nm)) { + change_reason |= NetifReason::NSC_IPV4_NETMASK_CHANGED; + cb_args.ipv4_changed.old_netmask.addr = old_nm.addr; + } + + if (netif_do_set_gw(gw, old_gw)) { + change_reason |= NetifReason::NSC_IPV4_GATEWAY_CHANGED; + cb_args.ipv4_changed.old_gw = old_gw; + } + + if (!remove) { + /* set ipaddr last to ensure netmask/gw have been set when status callback is called */ + if (netif_do_set_ipaddr(ipaddr, old_addr)) { + change_reason |= NetifReason::NSC_IPV4_ADDRESS_CHANGED; + cb_args.ipv4_changed.old_address.addr = old_addr.addr; + } + } + + if (change_reason != NetifReason::NSC_NONE) { + change_reason |= NetifReason::NSC_IPV4_SETTINGS_CHANGED; + } + + if (!remove) { + /* Issue a callback even if the address hasn't changed, eg. DHCP reboot */ + change_reason |= NetifReason::NSC_IPV4_ADDR_VALID; + } + + DEBUG_PRINTF("change_reason=%u", change_reason); + + if (change_reason != NetifReason::NSC_NONE) { + callback_fn(change_reason, &cb_args); + } + + DEBUG_EXIT +} + +void netif_add_ext_callback(netif_ext_callback_fn fn) { + callback_fn = fn; +} + +/* + * Link + */ + +void netif_set_link_up() { + DEBUG_ENTRY + const auto &netif = net::globals::netif_default; + + if (!(netif.flags & netif::NETIF_FLAG_LINK_UP)) { + netif_set_flags(netif::NETIF_FLAG_LINK_UP); + + dhcp_network_changed_link_up(); + + autoip_network_changed_link_up(); + + netif_issue_reports(); + + netif_ext_callback_args_t args; + args.link_changed.state = 1; + callback_fn(NetifReason::NSC_LINK_CHANGED, &args); + + DEBUG_EXIT + return; + } + + DEBUG_EXIT +} + +void netif_set_link_down() { + DEBUG_ENTRY + const auto &netif = net::globals::netif_default; + + if (netif.flags & netif::NETIF_FLAG_LINK_UP) { + netif_clear_flags(netif::NETIF_FLAG_LINK_UP); + + autoip_network_changed_link_down(); + + acd_network_changed_link_down(); + + netif_ext_callback_args_t args; + args.link_changed.state = 0; + callback_fn(NetifReason::NSC_LINK_CHANGED, &args); + + DEBUG_EXIT + return; + } + + DEBUG_EXIT +} +} // namespace net diff --git a/lib-network/src/net/rfc3927.cpp b/lib-network/src/net/rfc3927.cpp deleted file mode 100644 index ba7b9c4f..00000000 --- a/lib-network/src/net/rfc3927.cpp +++ /dev/null @@ -1,90 +0,0 @@ -/** - * @file rfc3927.cpp - * - */ -/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include - -#include "net.h" -#include "net_private.h" - -#include "hardware.h" - -#include "../../config/net_config.h" - -/* - * https://www.rfc-editor.org/rfc/rfc3927.html - * Dynamic Configuration of IPv4 Link-Local Addresses - */ - -static const uint32_t s_ip_begin = 0x0100FEA9; // 169.254.0.1 -static const uint32_t s_ip_end = 0xFFFEFEA9; // 169.254.254.255 - -namespace net { -namespace globals { -extern struct IpInfo ipInfo; -extern uint8_t macAddress[ETH_ADDR_LEN]; -} // namespace globals -} // namespace net - -bool rfc3927() { - DEBUG_ENTRY - - const auto mask = net::globals::macAddress[3] + (net::globals::macAddress[4] << 8); - auto ip = s_ip_begin | static_cast(mask << 16); - - DEBUG_PRINTF("ip=" IPSTR, IP2STR(ip)); - - auto nCount = 0; - const auto nMillis = Hardware::Get()->Millis(); - - do { - DEBUG_PRINTF(IPSTR, IP2STR(ip)); - - net::globals::ipInfo.ip.addr = ip; - - if (!arp_do_probe()) { - net::globals::ipInfo.gw.addr = ip; - net::globals::ipInfo.netmask.addr = 0x0000FFFF; - - DEBUG_EXIT - return true; - } - - ip = __builtin_bswap32(__builtin_bswap32(ip) + 1); - - if (ip == s_ip_end) { - ip = s_ip_begin; - } - - nCount++; - } while ((nCount < 0xFF) && ((Hardware::Get()->Millis() - nMillis) < 500)); - - net::globals::ipInfo.ip.addr = 0; - net::globals::ipInfo.gw.addr = 0; - net::globals::ipInfo.netmask.addr = 0; - - DEBUG_EXIT - return false; -} diff --git a/lib-network/src/net/tcp.cpp b/lib-network/src/net/tcp.cpp index 4dda2074..c219828b 100644 --- a/lib-network/src/net/tcp.cpp +++ b/lib-network/src/net/tcp.cpp @@ -2,7 +2,7 @@ * @file tcp.cpp * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,39 +29,43 @@ * LISTEN -> ESTABLISHED -> CLOSE_WAIT -> LAST_ACK -> CLOSED:LISTEN */ +#if defined (DEBUG_NET_TCP) +# undef NDEBUG +#endif + +#pragma GCC diagnostic push #if (__GNUC__ < 10) -# pragma GCC diagnostic push # pragma GCC diagnostic ignored "-Wconversion" # pragma GCC diagnostic ignored "-Wsign-conversion" #endif +#pragma GCC push_options +#pragma GCC optimize ("O2") +#pragma GCC optimize ("no-tree-loop-distribute-patterns") #include #include #include #include +#include "../config/net_config.h" + #include "net.h" +#include "net/protocol/tcp.h" + +#include "net_memcpy.h" #include "net_private.h" #include "hardware.h" -#include "../config/net_config.h" +#include "debug.h" +namespace net { #define TCP_RX_MSS (TCP_DATA_SIZE) #define TCP_RX_MAX_ENTRIES (1U << 1) // Must always be a power of 2 #define TCP_RX_MAX_ENTRIES_MASK (TCP_RX_MAX_ENTRIES - 1) #define TCP_MAX_RX_WND (TCP_RX_MAX_ENTRIES * TCP_RX_MSS); - #define TCP_TX_MSS (TCP_DATA_SIZE) -#define MAX_TCBS_ALLOWED 6 - -namespace net { -namespace globals { -extern uint8_t macAddress[ETH_ADDR_LEN]; -} // namespace globals -} // namespace net - /** * Transmission control block (TCB) */ @@ -128,7 +132,7 @@ struct ReceiveQueue { }; struct Port { - tcb TCB[MAX_TCBS_ALLOWED]; + tcb TCB[TCP_MAX_TCBS_ALLOWED]; ReceiveQueue receiveQueue; uint16_t nLocalPort; }; @@ -253,13 +257,13 @@ static constexpr bool SEQ_GT(const uint32_t x, const uint32_t y) { return static_cast(x - y) > 0; } -static constexpr bool SEQ_GEQ(const uint32_t x, const uint32_t y) { - return static_cast(x - y) >= 0; -} - -static constexpr bool SEQ_BETWEEN(const uint32_t l, const uint32_t x, const uint32_t h) { - return SEQ_LT(l, x) && SEQ_LT(x, h); -} +//static constexpr bool SEQ_GEQ(const uint32_t x, const uint32_t y) { +// return static_cast(x - y) >= 0; +//} +// +//static constexpr bool SEQ_BETWEEN(const uint32_t l, const uint32_t x, const uint32_t h) { +// return SEQ_LT(l, x) && SEQ_LT(x, h); +//} static constexpr bool SEQ_BETWEEN_L(const uint32_t l, const uint32_t x, const uint32_t h) { return SEQ_LEQ(l, x) && SEQ_LT(x, h); // low border inclusive @@ -322,7 +326,7 @@ __attribute__((cold)) void tcp_init() { DEBUG_ENTRY /* Ethernet */ - memcpy(s_tcp.ether.src, net::globals::macAddress, ETH_ADDR_LEN); + std::memcpy(s_tcp.ether.src, net::globals::netif_default.hwaddr, ETH_ADDR_LEN); s_tcp.ether.type = __builtin_bswap16(ETHER_TYPE_IPv4); /* IPv4 */ s_tcp.ip4.ver_ihl = 0x45; @@ -360,8 +364,8 @@ static uint16_t _chksum(struct t_tcp *pTcp, const struct tcb *pTcb, uint16_t nLe memcpy(buf, pseu, TCP_PSEUDO_LEN); // Generate TCP psuedo header - memcpy(pseu->srcIp, pTcb->localIp, IPv4_ADDR_LEN); - memcpy(pseu->dstIp, pTcb->remoteIp, IPv4_ADDR_LEN); + std::memcpy(pseu->srcIp, pTcb->localIp, IPv4_ADDR_LEN); + std::memcpy(pseu->dstIp, pTcb->remoteIp, IPv4_ADDR_LEN); pseu->zero = 0; pseu->proto = IPv4_PROTO_TCP; pseu->length = __builtin_bswap16(nLength); @@ -391,12 +395,12 @@ static void send_package(const struct tcb *pTcb, const struct SendInfo &sendInfo const auto tcplen = nHeaderLength + pTcb->TX.size; /* Ethernet */ - memcpy(s_tcp.ether.dst, pTcb->remoteEthAddr, ETH_ADDR_LEN); + std::memcpy(s_tcp.ether.dst, pTcb->remoteEthAddr, ETH_ADDR_LEN); /* IPv4 */ s_tcp.ip4.id = s_id++; s_tcp.ip4.len = __builtin_bswap16(static_cast(tcplen + sizeof(struct ip4_header))); - memcpy(s_tcp.ip4.src, pTcb->localIp, IPv4_ADDR_LEN); - memcpy(s_tcp.ip4.dst, pTcb->remoteIp, IPv4_ADDR_LEN); + std::memcpy(s_tcp.ip4.src, pTcb->localIp, IPv4_ADDR_LEN); + std::memcpy(s_tcp.ip4.dst, pTcb->remoteIp, IPv4_ADDR_LEN); s_tcp.ip4.chksum = 0; #if !defined (CHECKSUM_BY_HARDWARE) s_tcp.ip4.chksum = net_chksum(reinterpret_cast(&s_tcp.ip4), 20); @@ -545,26 +549,79 @@ static void scan_options(struct t_tcp *pTcp, struct tcb *pTcb, const int32_t nDa } __attribute__((hot)) void tcp_run() { - for (auto nIndexPort = 0; nIndexPort < TCP_MAX_PORTS_ALLOWED; nIndexPort++) { - for (auto nIndexTCB = 0; nIndexTCB < MAX_TCBS_ALLOWED; nIndexTCB++) { - auto *pTCB = &s_Port[nIndexPort].TCB[nIndexTCB]; - - if (pTCB->state == STATE_CLOSE_WAIT) { - struct SendInfo info; - info.SEQ = pTCB->SND.NXT; - info.ACK = pTCB->RCV.NXT; + for (auto& port : s_Port) { + for (auto& tcb : port.TCB) { + if (tcb.state == STATE_CLOSE_WAIT) { + SendInfo info; + info.SEQ = tcb.SND.NXT; + info.ACK = tcb.RCV.NXT; info.CTL = Control::FIN | Control::ACK; - send_package(pTCB, info); + send_package(&tcb, info); - NEW_STATE(pTCB, STATE_LAST_ACK); + NEW_STATE(&tcb, STATE_LAST_ACK); - pTCB->SND.NXT++; + tcb.SND.NXT++; } } } } +static bool find_matching_tcb(const t_tcp *pTcp, const uint32_t nIndexPort, uint32_t& nIndexTCB) { + for (nIndexTCB = 0; nIndexTCB < TCP_MAX_TCBS_ALLOWED; nIndexTCB++) { + auto *pTCB = &s_Port[nIndexPort].TCB[nIndexTCB]; + + if (pTCB->state == STATE_LISTEN) { + continue; + } + + if (pTCB->nRemotePort == pTcp->tcp.srcpt && memcmp(pTCB->remoteIp, pTcp->ip4.src, IPv4_ADDR_LEN) == 0) { + return true; + } + } + + return false; +} + +static bool find_available_tcb(const uint32_t nIndexPort, uint32_t& nIndexTCB) { + for (nIndexTCB = 0; nIndexTCB < TCP_MAX_TCBS_ALLOWED; nIndexTCB++) { + auto *pTCB = &s_Port[nIndexPort].TCB[nIndexTCB]; + + if (pTCB->state == STATE_LISTEN) { + DEBUG_PUTS("pTCB->state == STATE_LISTEN"); + return true; + } + } + + return false; +} + +static void find_tcb(const t_tcp *pTcp, uint32_t& nIndexPort, uint32_t& nIndexTCB) { + // Search each port for a match with the destination port + for (nIndexPort = 0; nIndexPort < TCP_MAX_PORTS_ALLOWED; nIndexPort++) { + if (s_Port[nIndexPort].nLocalPort != pTcp->tcp.dstpt) { + continue; + } + + // Search for an existing active TCB matching the source IP and port + if (find_matching_tcb(pTcp, nIndexPort, nIndexTCB)) { + DEBUG_EXIT + return; + } + + // If no matching TCB, find an available TCB in listening state + if (find_available_tcb(nIndexPort, nIndexTCB)) { + DEBUG_EXIT + return; + } + + // If no available TCB, trigger retransmission + DEBUG_PUTS("MAX_TCB_ALLOWED -> Force retransmission"); + DEBUG_EXIT + return; + } +} + /** * https://www.rfc-editor.org/rfc/rfc9293.html#name-segment-arrives */ @@ -576,69 +633,33 @@ __attribute__((hot)) void tcp_handle(struct t_tcp *pTcp) { DEBUG_PRINTF(IPSTR ":%d[%d] -> %d", pTcp->ip4.src[0], pTcp->ip4.src[1], pTcp->ip4.src[2], pTcp->ip4.src[3], pTcp->tcp.dstpt, pTcp->tcp.srcpt, tcplen); - uint32_t nIndexPort; - /* - src/net/tcp.cpp: In function 'void tcp_handle(t_tcp*)': -src/net/tcp.cpp:871:31: error: 'nIndexTCB' may be used uninitialized in this function [-Werror=maybe-uninitialized] - 871 | switch (pTCB->state) { - */ + uint32_t nIndexPort = 0; uint32_t nIndexTCB = 0; - - // Find a TCB - for (nIndexPort = 0; nIndexPort < TCP_MAX_PORTS_ALLOWED; nIndexPort++) { - if (s_Port[nIndexPort].nLocalPort == pTcp->tcp.dstpt) { - // Find an active TCB - for (nIndexTCB = 0; nIndexTCB < MAX_TCBS_ALLOWED; nIndexTCB++) { - auto *pTCB = &s_Port[nIndexPort].TCB[nIndexTCB]; - if (pTCB->state != STATE_LISTEN) { - if ((pTCB->nRemotePort == pTcp->tcp.srcpt) && (memcmp(pTCB->remoteIp, pTcp->ip4.src, IPv4_ADDR_LEN) == 0)) { - break; - } - } - } - - if (nIndexTCB == MAX_TCBS_ALLOWED) { - // Find an available TCB - for (nIndexTCB = 0; nIndexTCB < MAX_TCBS_ALLOWED; nIndexTCB++) { - auto *pTCB = &s_Port[nIndexPort].TCB[nIndexTCB]; - if (pTCB->state == STATE_LISTEN) { - break; - } - } - - if (nIndexTCB == MAX_TCBS_ALLOWED) { - DEBUG_PUTS("MAX_TCB_ALLOWED -> Force retransmission"); - DEBUG_EXIT - return; - } - } - - break; - } - } + find_tcb(pTcp, nIndexPort, nIndexTCB); + DEBUG_PRINTF("nIndexPort=%u, nIndexTCB=%u", nIndexPort, nIndexTCB); const auto nDataOffset = offset2octets(pTcp->tcp.offset); // https://www.rfc-editor.org/rfc/rfc9293.html#name-closed-state // CLOSED (i.e., TCB does not exist) if (nIndexPort == TCP_MAX_PORTS_ALLOWED) { - DEBUG_PUTS("TCP_MAX_PORTS_ALLOWED"); struct tcb TCB; - memset(&TCB, 0, sizeof(struct tcb)); + std::memset(&TCB, 0, sizeof(struct tcb)); TCB.nLocalPort = pTcp->tcp.dstpt; - memcpy(TCB.localIp, pTcp->ip4.dst, IPv4_ADDR_LEN); + std::memcpy(TCB.localIp, pTcp->ip4.dst, IPv4_ADDR_LEN); TCB.nRemotePort = pTcp->tcp.srcpt; - memcpy(TCB.remoteIp, pTcp->ip4.src, IPv4_ADDR_LEN); - memcpy(TCB.remoteEthAddr, pTcp->ether.src, ETH_ADDR_LEN); + std::memcpy(TCB.remoteIp, pTcp->ip4.src, IPv4_ADDR_LEN); + std::memcpy(TCB.remoteEthAddr, pTcp->ether.src, ETH_ADDR_LEN); _bswap32(pTcp); scan_options(pTcp, &TCB, nDataOffset); send_reset(pTcp, &TCB); + DEBUG_PUTS("TCP_MAX_PORTS_ALLOWED"); DEBUG_EXIT return; } @@ -649,19 +670,6 @@ src/net/tcp.cpp:871:31: error: 'nIndexTCB' may be used uninitialized in this fun pTcp->tcp.window = __builtin_bswap16(pTcp->tcp.window); pTcp->tcp.urgent = __builtin_bswap16(pTcp->tcp.urgent); - DEBUG_PRINTF("%c%c%c%c%c%c SEQ=%u, ACK=%u, tcplen=%u, data_offset=%u, data_length=%u", - pTcp->tcp.control & Control::URG ? 'U' : '-', - pTcp->tcp.control & Control::ACK ? 'A' : '-', - pTcp->tcp.control & Control::PSH ? 'P' : '-', - pTcp->tcp.control & Control::RST ? 'R' : '-', - pTcp->tcp.control & Control::SYN ? 'S' : '-', - pTcp->tcp.control & Control::FIN ? 'F' : '-', - _get_seqnum(pTcp), - _get_acknum(pTcp), - tcplen, - nDataOffset, - nDataLength); - SendInfo sendInfo; const auto SEG_LEN = nDataLength; @@ -691,11 +699,11 @@ src/net/tcp.cpp:871:31: error: 'nIndexTCB' may be used uninitialized in this fun // https://www.rfc-editor.org/rfc/rfc9293.html#name-listen-state if (pTCB->state == STATE_LISTEN) { - memcpy(pTCB->localIp, pTcp->ip4.dst, IPv4_ADDR_LEN); + std::memcpy(pTCB->localIp, pTcp->ip4.dst, IPv4_ADDR_LEN); pTCB->nRemotePort = pTcp->tcp.srcpt; - memcpy(pTCB->remoteIp, pTcp->ip4.src, IPv4_ADDR_LEN); - memcpy(pTCB->remoteEthAddr, pTcp->ether.src, ETH_ADDR_LEN); + std::memcpy(pTCB->remoteIp, pTcp->ip4.src, IPv4_ADDR_LEN); + std::memcpy(pTCB->remoteEthAddr, pTcp->ether.src, ETH_ADDR_LEN); // First, check for a RST // An incoming RST should be ignored. @@ -711,6 +719,7 @@ src/net/tcp.cpp:871:31: error: 'nIndexTCB' may be used uninitialized in this fun if (pTcp->tcp.control & Control::ACK) { send_reset(pTcp, pTCB); + DEBUG_PUTS("pTcp->tcp.control & Control::ACK"); DEBUG_EXIT return; } @@ -848,8 +857,9 @@ src/net/tcp.cpp:871:31: error: 'nIndexTCB' may be used uninitialized in this fun return; } - DEBUG_PUTS("_send_reset"); send_reset(pTcp, pTCB); + + DEBUG_PUTS("pTcp->tcp.control & Control::SYN"); } /* fifth check the ACK field, *//* Page 72 */ @@ -874,8 +884,9 @@ src/net/tcp.cpp:871:31: error: 'nIndexTCB' may be used uninitialized in this fun return; } else { // - DEBUG_PUTS("_send_reset"); send_reset(pTcp, pTCB); + + DEBUG_PUTS(""); } break; case STATE_ESTABLISHED: @@ -1083,7 +1094,7 @@ int tcp_begin(const uint16_t nLocalPort) { if (s_Port[i].nLocalPort == 0) { s_Port[i].nLocalPort = nLocalPort; - for (uint32_t nIndexTCB = 0; nIndexTCB < MAX_TCBS_ALLOWED; nIndexTCB++) { + for (uint32_t nIndexTCB = 0; nIndexTCB < TCP_MAX_TCBS_ALLOWED; nIndexTCB++) { // create transmission control block's (TCB) _init_tcb(&s_Port[i].TCB[nIndexTCB], nLocalPort); } @@ -1125,15 +1136,17 @@ uint16_t tcp_read(const int32_t nHandleListen, const uint8_t **pData, uint32_t & return pQueueEntry->nSize; } -void tcp_write(const int32_t nHandleListen, const uint8_t *pBuffer, uint16_t nLength, uint32_t nHandleConnection) { - assert(nHandleListen >= 0); - assert(nHandleListen < TCP_MAX_PORTS_ALLOWED); - assert(pBuffer != nullptr); - assert(nHandleConnection < MAX_TCBS_ALLOWED); +static void _write(struct tcb *pTCB, const uint8_t *pBuffer, const uint32_t nLength, const bool isLastSegment) { + assert(nLength != 0); + assert(nLength <= static_cast(TCP_DATA_SIZE)); - nLength = std::min(nLength, static_cast(TCP_DATA_SIZE)); + DEBUG_PRINTF("nLength=%u, pTCB->SND.WND=%u", nLength, pTCB->SND.WND); - auto *pTCB = &s_Port[nHandleListen].TCB[nHandleConnection]; + if (nLength > pTCB->SND.WND) { + console_error("Retry or queue the data for later transmission\n"); + // TODO retry or queue the data for later transmission. + return; + } pTCB->TX.data = const_cast(pBuffer); pTCB->TX.size = nLength; @@ -1141,14 +1154,38 @@ void tcp_write(const int32_t nHandleListen, const uint8_t *pBuffer, uint16_t nLe struct SendInfo info; info.SEQ = pTCB->SND.NXT; info.ACK = pTCB->RCV.NXT; - info.CTL = Control::ACK | Control::PSH; + info.CTL = Control::ACK; + if (isLastSegment) { + info.CTL |= Control::PSH; + } send_package(pTCB, info); pTCB->TX.data = nullptr; pTCB->TX.size = 0; - pTCB->SND.NXT += nLength; + pTCB->SND.NXT += nLength; + pTCB->SND.WND -= nLength; } +void tcp_write(const int32_t nHandleListen, const uint8_t *pBuffer, uint32_t nLength, uint32_t nHandleConnection) { + assert(nHandleListen >= 0); + assert(nHandleListen < TCP_MAX_PORTS_ALLOWED); + assert(pBuffer != nullptr); + assert(nHandleConnection < TCP_MAX_TCBS_ALLOWED); + + auto *pTCB = &s_Port[nHandleListen].TCB[nHandleConnection]; + assert(pTCB != nullptr); + + const auto *p = pBuffer; + + while (nLength > 0) { + const auto nWriteLength = (nLength > TCP_DATA_SIZE) ? TCP_DATA_SIZE : nLength; + const bool isLastSegment = (nLength < TCP_DATA_SIZE); + _write(pTCB, p, nWriteLength, isLastSegment); + p += nWriteLength; + nLength -= nWriteLength; + } +} +} // namespace net // <--- diff --git a/lib-network/src/net/udp.cpp b/lib-network/src/net/udp.cpp index 5def0c6a..f34f7688 100644 --- a/lib-network/src/net/udp.cpp +++ b/lib-network/src/net/udp.cpp @@ -2,7 +2,7 @@ * @file udp.cpp * */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,50 +23,51 @@ * THE SOFTWARE. */ +#if defined (DEBUG_NET_UDP) +# undef NDEBUG +#endif + +#if !defined (CONFIG_REMOTECONFIG_MINIMUM) +# pragma GCC push_options +# pragma GCC optimize ("O2") +# pragma GCC optimize ("no-tree-loop-distribute-patterns") +#endif + #include #include -#include #include #include +#include "../../config/net_config.h" + +#include "net/protocol/udp.h" + #include "net.h" #include "net_private.h" #include "net_memcpy.h" -#include "../../config/net_config.h" +#include "debug.h" + +namespace net { +namespace globals { +extern uint32_t nBroadcastMask; +} // namespace globals struct data_entry { uint32_t from_ip; + uint32_t size; uint16_t from_port; - uint16_t size; uint8_t data[UDP_DATA_SIZE]; } ALIGNED; -typedef union pcast32 { - uint32_t u32; - uint8_t u8[4]; -} _pcast32; - static uint16_t s_Port[UDP_MAX_PORTS_ALLOWED] SECTION_NETWORK ALIGNED; static struct data_entry s_data[UDP_MAX_PORTS_ALLOWED] SECTION_NETWORK ALIGNED; static struct t_udp s_send_packet SECTION_NETWORK ALIGNED; static uint16_t s_id SECTION_NETWORK ALIGNED; static uint8_t s_multicast_mac[ETH_ADDR_LEN] SECTION_NETWORK ALIGNED; -namespace net { -namespace globals { -extern struct IpInfo ipInfo; -extern uint32_t nBroadcastMask; -extern uint32_t nOnNetworkMask; -extern uint8_t macAddress[ETH_ADDR_LEN]; -} // namespace globals -} // namespace net - void udp_set_ip() { - _pcast32 src; - - src.u32 = net::globals::ipInfo.ip.addr; - memcpy(s_send_packet.ip4.src, src.u8, IPv4_ADDR_LEN); + net::memcpy_ip(s_send_packet.ip4.src, net::globals::netif_default.ip.addr); } void __attribute__((cold)) udp_init() { @@ -75,7 +76,7 @@ void __attribute__((cold)) udp_init() { s_multicast_mac[1] = 0x00; s_multicast_mac[2] = 0x5E; // Ethernet - memcpy(s_send_packet.ether.src, net::globals::macAddress, ETH_ADDR_LEN); + std::memcpy(s_send_packet.ether.src, net::globals::netif_default.hwaddr, ETH_ADDR_LEN); s_send_packet.ether.type = __builtin_bswap16(ETHER_TYPE_IPv4); // IPv4 s_send_packet.ip4.ver_ihl = 0x45; @@ -107,21 +108,86 @@ __attribute__((hot)) void udp_handle(struct t_udp *pUdp) { const auto nDataLength = static_cast(__builtin_bswap16(pUdp->udp.len) - UDP_HEADER_SIZE); const auto i = std::min(static_cast(UDP_DATA_SIZE), nDataLength); - net_memcpy(p_queue_entry->data, pUdp->udp.data, i); + net::memcpy(p_queue_entry->data, pUdp->udp.data, i); - _pcast32 src; - - memcpy(src.u8, pUdp->ip4.src, IPv4_ADDR_LEN); - p_queue_entry->from_ip = src.u32; + p_queue_entry->from_ip = net::memcpy_ip(pUdp->ip4.src); p_queue_entry->from_port = __builtin_bswap16(pUdp->udp.source_port); p_queue_entry->size = static_cast(i); return; + } + } + DEBUG_PRINTF(IPSTR ":%d[%x] " MACSTR, pUdp->ip4.src[0],pUdp->ip4.src[1],pUdp->ip4.src[2],pUdp->ip4.src[3], nDestinationPort, nDestinationPort, MAC2STR(pUdp->ether.dst)); +} + +template +static void udp_send_implementation(int nIndex, const uint8_t *pData, uint32_t nSize, uint32_t nRemoteIp, uint16_t nRemotePort) { + assert(nIndex >= 0); + assert(nIndex < UDP_MAX_PORTS_ALLOWED); + assert(s_Port[nIndex] != 0); + + //IPv4 + s_send_packet.ip4.id = s_id++; + s_send_packet.ip4.len = __builtin_bswap16(static_cast(nSize + IPv4_UDP_HEADERS_SIZE)); + s_send_packet.ip4.chksum = 0; + + //UDP + s_send_packet.udp.source_port = __builtin_bswap16( s_Port[nIndex]); + s_send_packet.udp.destination_port = __builtin_bswap16(nRemotePort); + s_send_packet.udp.len = __builtin_bswap16(static_cast(nSize + UDP_HEADER_SIZE)); + + nSize = std::min(static_cast(UDP_DATA_SIZE), nSize); + + net::memcpy(s_send_packet.udp.data, pData, nSize); + + if (nRemoteIp == network::IP4_BROADCAST) { + memset(s_send_packet.ether.dst, 0xFF, ETH_ADDR_LEN); + memset(s_send_packet.ip4.dst, 0xFF, IPv4_ADDR_LEN); + } else if ((nRemoteIp & net::globals::nBroadcastMask) == net::globals::nBroadcastMask) { + memset(s_send_packet.ether.dst, 0xFF, ETH_ADDR_LEN); + net::memcpy_ip(s_send_packet.ip4.dst, nRemoteIp); + } else { + if ((nRemoteIp & 0xF0) == 0xE0) { // Multicast, we know the MAC Address + typedef union pcast32 { + uint32_t u32; + uint8_t u8[4]; + } _pcast32; + _pcast32 multicast_ip; + + multicast_ip.u32 = nRemoteIp; + s_multicast_mac[3] = multicast_ip.u8[1] & 0x7F; + s_multicast_mac[4] = multicast_ip.u8[2]; + s_multicast_mac[5] = multicast_ip.u8[3]; + + std::memcpy(s_send_packet.ether.dst, s_multicast_mac, ETH_ADDR_LEN); + net::memcpy_ip(s_send_packet.ip4.dst, nRemoteIp); + } else { + if (S == net::arp::EthSend::IS_NORMAL) { + net::arp_send(&s_send_packet, nSize + UDP_PACKET_HEADERS_SIZE, nRemoteIp); + } +#if defined CONFIG_ENET_ENABLE_PTP + else if (S == net::arp::EthSend::IS_TIMESTAMP) { + net::arp_send_timestamp(&s_send_packet, nSize + UDP_PACKET_HEADERS_SIZE, nRemoteIp); + } +#endif + return; } } - DEBUG_PRINTF(IPSTR ":%d[%x]", pUdp->ip4.src[0],pUdp->ip4.src[1],pUdp->ip4.src[2],pUdp->ip4.src[3], nDestinationPort, nDestinationPort); +#if !defined (CHECKSUM_BY_HARDWARE) + s_send_packet.ip4.chksum = net_chksum(reinterpret_cast(&s_send_packet.ip4), sizeof(s_send_packet.ip4)); +#endif + + if (S == net::arp::EthSend::IS_NORMAL) { + emac_eth_send(reinterpret_cast(&s_send_packet), nSize + UDP_PACKET_HEADERS_SIZE); + } +#if defined CONFIG_ENET_ENABLE_PTP + else if (S == net::arp::EthSend::IS_TIMESTAMP) { + emac_eth_send_timestamp(reinterpret_cast(&s_send_packet), nSize); + } +#endif + return; } // --> @@ -163,7 +229,7 @@ int udp_end(uint16_t nLocalPort) { return -1; } -uint16_t udp_recv1(int nIndex, uint8_t *pData, uint16_t nSize, uint32_t *pFromIp, uint16_t *FromPort) { +uint32_t udp_recv1(int nIndex, uint8_t *pData, uint32_t nSize, uint32_t *pFromIp, uint16_t *FromPort) { assert(nIndex >= 0); assert(nIndex < UDP_MAX_PORTS_ALLOWED); @@ -174,7 +240,7 @@ uint16_t udp_recv1(int nIndex, uint8_t *pData, uint16_t nSize, uint32_t *pFromIp auto *p_data = &s_data[nIndex]; const auto i = std::min(nSize, p_data->size); - net_memcpy(pData, p_data->data, i); + net::memcpy(pData, p_data->data, i); *pFromIp = p_data->from_ip; *FromPort = p_data->from_port; @@ -184,104 +250,35 @@ uint16_t udp_recv1(int nIndex, uint8_t *pData, uint16_t nSize, uint32_t *pFromIp return i; } -uint16_t udp_recv2(int nIndex, const uint8_t **pData, uint32_t *pFromIp, uint16_t *pFromPort) { +uint32_t udp_recv2(int nIndex, const uint8_t **pData, uint32_t *pFromIp, uint16_t *pFromPort) { assert(nIndex >= 0); assert(nIndex < UDP_MAX_PORTS_ALLOWED); - if (__builtin_expect((s_data[nIndex].size == 0), 1)) { + auto &p_data = s_data[nIndex]; + + if (__builtin_expect((p_data.size == 0), 1)) { return 0; } - auto *p_data = &s_data[nIndex]; - - *pData = p_data->data; - *pFromIp = p_data->from_ip; - *pFromPort = p_data->from_port; + *pData = p_data.data; + *pFromIp = p_data.from_ip; + *pFromPort = p_data.from_port; - const auto nSize = p_data->size; + const auto nSize = p_data.size; - p_data->size = 0; + p_data.size = 0; return nSize; } -int udp_send(int nIndex, const uint8_t *pData, uint16_t nSize, uint32_t RemoteIp, uint16_t RemotePort) { - assert(nIndex >= 0); - assert(nIndex < UDP_MAX_PORTS_ALLOWED); - _pcast32 dst; - - if (__builtin_expect ((s_Port[nIndex] == 0), 0)) { - DEBUG_PUTS("ports_allowed[idx] == 0"); - return -1; - } - - if (RemoteIp == IPv4_BROADCAST) { - memset(s_send_packet.ether.dst, 0xFF, ETH_ADDR_LEN); - memset(s_send_packet.ip4.dst, 0xFF, IPv4_ADDR_LEN); - } else if ((RemoteIp & net::globals::nBroadcastMask) == net::globals::nBroadcastMask) { - memset(s_send_packet.ether.dst, 0xFF, ETH_ADDR_LEN); - dst.u32 = RemoteIp; - memcpy(s_send_packet.ip4.dst, dst.u8, IPv4_ADDR_LEN); - } else { - if ((RemoteIp & 0xE0) == 0xE0) { // Multicast, we know the MAC Address - _pcast32 multicast_ip; - - multicast_ip.u32 = RemoteIp; - - s_multicast_mac[3] = multicast_ip.u8[1] & 0x7F; - s_multicast_mac[4] = multicast_ip.u8[2]; - s_multicast_mac[5] = multicast_ip.u8[3]; - - memcpy(s_send_packet.ether.dst, s_multicast_mac, ETH_ADDR_LEN); - - dst.u32 = RemoteIp; - memcpy(s_send_packet.ip4.dst, dst.u8, IPv4_ADDR_LEN); - } else { - if (__builtin_expect((net::globals::nOnNetworkMask != (RemoteIp & net::globals::nOnNetworkMask)), 0)) { - if (net::globals::ipInfo.gw.addr == arp_cache_lookup(net::globals::ipInfo.gw.addr, s_send_packet.ether.dst)) { - dst.u32 = RemoteIp; - memcpy(s_send_packet.ip4.dst, dst.u8, IPv4_ADDR_LEN); - } else { -#ifndef NDEBUG - console_error("ARP lookup failed -> default gateway :"); - printf(IPSTR " [%d]\n", IP2STR(RemoteIp), s_Port[nIndex]); -#endif - return -3; - } - } else { - if (RemoteIp == arp_cache_lookup(RemoteIp, s_send_packet.ether.dst)) { - dst.u32 = RemoteIp; - memcpy(s_send_packet.ip4.dst, dst.u8, IPv4_ADDR_LEN); - } else { -#ifndef NDEBUG - console_error("ARP lookup failed: "); - printf(IPSTR "\n", IP2STR(RemoteIp)); -#endif - return -2; - } - } - } - } - - //IPv4 - s_send_packet.ip4.id = s_id; - s_send_packet.ip4.len = __builtin_bswap16((nSize + IPv4_UDP_HEADERS_SIZE)); - s_send_packet.ip4.chksum = 0; -#if !defined (CHECKSUM_BY_HARDWARE) - s_send_packet.ip4.chksum = net_chksum(reinterpret_cast(&s_send_packet.ip4), sizeof(s_send_packet.ip4)); -#endif - //UDP - s_send_packet.udp.source_port = __builtin_bswap16( s_Port[nIndex]); - s_send_packet.udp.destination_port = __builtin_bswap16(RemotePort); - s_send_packet.udp.len = __builtin_bswap16((nSize + UDP_HEADER_SIZE)); - - net_memcpy(s_send_packet.udp.data, pData, std::min(static_cast(UDP_DATA_SIZE), nSize)); - - emac_eth_send(reinterpret_cast(&s_send_packet), nSize + UDP_PACKET_HEADERS_SIZE); - - s_id++; - - return 0; +void udp_send(int nIndex, const uint8_t *pData, uint32_t nSize, uint32_t nRemoteIp, uint16_t nRemotePort) { + udp_send_implementation(nIndex, pData, nSize, nRemoteIp, nRemotePort); } +#if defined CONFIG_ENET_ENABLE_PTP +void udp_send_timestamp(int nIndex, const uint8_t *pData, uint32_t nSize, uint32_t nRemoteIp, uint16_t nRemotePort) { + udp_send_implementation(nIndex, pData, nSize, nRemoteIp, nRemotePort); +} +#endif +} // namespace net // <--- diff --git a/lib-network/src/networkconst.cpp b/lib-network/src/networkconst.cpp index b70872ef..8775c8d6 100644 --- a/lib-network/src/networkconst.cpp +++ b/lib-network/src/networkconst.cpp @@ -2,7 +2,7 @@ * @file networkconst.cpp * */ -/* Copyright (C) 2019-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-network/src/params/networkparams.cpp b/lib-network/src/params/networkparams.cpp index 03d4eafb..76c9ebe1 100644 --- a/lib-network/src/params/networkparams.cpp +++ b/lib-network/src/params/networkparams.cpp @@ -2,7 +2,7 @@ * @file networkparams.cpp * */ -/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -36,6 +36,7 @@ #include "networkparams.h" #include "networkparamsconst.h" + #include "readconfigfile.h" #include "sscan.h" @@ -45,7 +46,7 @@ using namespace networkparams; -NetworkParams::NetworkParams(NetworkParamsStore *pNetworkParamsStore): m_pNetworkParamsStore(pNetworkParamsStore) { +NetworkParams::NetworkParams() { DEBUG_ENTRY memset(&m_Params, 0, sizeof(struct networkparams::Params)); @@ -55,7 +56,7 @@ NetworkParams::NetworkParams(NetworkParamsStore *pNetworkParamsStore): m_pNetwor DEBUG_EXIT } -bool NetworkParams::Load() { +void NetworkParams::Load() { DEBUG_ENTRY m_Params.nSetList = 0; @@ -63,20 +64,15 @@ bool NetworkParams::Load() { ReadConfigFile configfile(NetworkParams::staticCallbackFunction, this); if (configfile.Read(NetworkParamsConst::FILE_NAME)) { - if (m_pNetworkParamsStore != nullptr) { - m_pNetworkParamsStore->Update(&m_Params); - } + NetworkParamsStore::Update(&m_Params); } else #endif - if (m_pNetworkParamsStore != nullptr) { - m_pNetworkParamsStore->Copy(&m_Params); - } else { - DEBUG_EXIT - return false; - } + NetworkParamsStore::Copy(&m_Params); +#ifndef NDEBUG + Dump(); +#endif DEBUG_EXIT - return true; } void NetworkParams::Load(const char *pBuffer, uint32_t nLength) { @@ -91,9 +87,11 @@ void NetworkParams::Load(const char *pBuffer, uint32_t nLength) { config.Read(pBuffer, nLength); - assert(m_pNetworkParamsStore != nullptr); - m_pNetworkParamsStore->Update(&m_Params); + NetworkParamsStore::Update(&m_Params); +#ifndef NDEBUG + Dump(); +#endif DEBUG_EXIT } @@ -145,8 +143,13 @@ void NetworkParams::callbackFunction(const char *pLine) { } if (Sscan::IpAddress(pLine, NetworkParamsConst::DEFAULT_GATEWAY, nValue32) == Sscan::OK) { - m_Params.nGatewayIp = nValue32; - m_Params.nSetList |= networkparams::Mask::DEFAULT_GATEWAY; + if (nValue32 != 0) { + m_Params.nSetList |= networkparams::Mask::DEFAULT_GATEWAY; + m_Params.nGatewayIp = nValue32; + } else { + m_Params.nSetList &= ~networkparams::Mask::DEFAULT_GATEWAY; + } + return; } @@ -158,8 +161,6 @@ void NetworkParams::callbackFunction(const char *pLine) { return; } - -#if !defined(DISABLE_RTC) if (Sscan::IpAddress(pLine, NetworkParamsConst::NTP_SERVER, nValue32) == Sscan::OK) { if (nValue32 != 0) { m_Params.nSetList |= networkparams::Mask::NTP_SERVER; @@ -170,21 +171,6 @@ void NetworkParams::callbackFunction(const char *pLine) { return; } - float fValue; - - if (Sscan::Float(pLine, NetworkParamsConst::NTP_UTC_OFFSET, fValue) == Sscan::OK) { - // https://en.wikipedia.org/wiki/List_of_UTC_time_offsets - if ((static_cast(fValue) >= -12) && (static_cast(fValue) <= 14) && (static_cast(fValue) != 0)) { - m_Params.fNtpUtcOffset = fValue; - m_Params.nSetList |= networkparams::Mask::NTP_UTC_OFFSET; - } else { - m_Params.fNtpUtcOffset = 0; - m_Params.nSetList &= ~networkparams::Mask::NTP_UTC_OFFSET; - } - return; - } -#endif - #if defined (ESP8266) if (Sscan::IpAddress(pLine, NetworkParamsConst::NAME_SERVER, nValue32) == Sscan::OK) { m_Params.nNameServerIp = nValue32; @@ -223,8 +209,7 @@ void NetworkParams::Builder(const struct networkparams::Params *ptNetworkParams, if (ptNetworkParams != nullptr) { memcpy(&m_Params, ptNetworkParams, sizeof(struct networkparams::Params)); } else { - assert(m_pNetworkParamsStore != nullptr); - m_pNetworkParamsStore->Copy(&m_Params); + NetworkParamsStore::Copy(&m_Params); } PropertiesBuilder builder(NetworkParamsConst::FILE_NAME, pBuffer, nLength); @@ -259,14 +244,27 @@ void NetworkParams::Builder(const struct networkparams::Params *ptNetworkParams, #endif builder.Add(NetworkParamsConst::HOSTNAME, m_Params.aHostName, isMaskSet(networkparams::Mask::HOSTNAME)); -#if !defined(DISABLE_RTC) builder.AddComment("NTP Server"); builder.AddIpAddress(NetworkParamsConst::NTP_SERVER, m_Params.nNtpServerIp, isMaskSet(networkparams::Mask::NTP_SERVER)); - builder.Add(NetworkParamsConst::NTP_UTC_OFFSET, m_Params.fNtpUtcOffset, isMaskSet(networkparams::Mask::NTP_UTC_OFFSET)); -#endif nSize = builder.GetSize(); DEBUG_PRINTF("nSize=%d", nSize); DEBUG_EXIT } + +void NetworkParams::Dump() { + printf("%s::%s \'%s\':\n", __FILE__, __FUNCTION__, NetworkParamsConst::FILE_NAME); + + printf(" %s=%d [%s]\n", NetworkParamsConst::USE_DHCP, static_cast(m_Params.bIsDhcpUsed), m_Params.bIsDhcpUsed != 0 ? "Yes" : "No"); + printf(" %s=" IPSTR "\n", NetworkParamsConst::IP_ADDRESS, IP2STR(m_Params.nLocalIp)); + printf(" %s=" IPSTR "\n", NetworkParamsConst::NET_MASK, IP2STR(m_Params.nNetmask)); + printf(" %s=" IPSTR "\n", NetworkParamsConst::DEFAULT_GATEWAY, IP2STR(m_Params.nGatewayIp)); + +#if defined (ESP8266) + printf(" %s=" IPSTR "\n", NetworkParamsConst::NAME_SERVER, IP2STR(m_Params.nNameServerIp)); +#endif + + printf(" %s=%s\n", NetworkParamsConst::HOSTNAME, m_Params.aHostName); + printf(" %s=" IPSTR "\n", NetworkParamsConst::NTP_SERVER, IP2STR(m_Params.nNtpServerIp)); +} diff --git a/lib-network/src/networkparamsconst.cpp b/lib-network/src/params/networkparamsconst.cpp old mode 100644 new mode 100755 similarity index 93% rename from lib-network/src/networkparamsconst.cpp rename to lib-network/src/params/networkparamsconst.cpp index 50811878..ae28a8d7 --- a/lib-network/src/networkparamsconst.cpp +++ b/lib-network/src/params/networkparamsconst.cpp @@ -2,7 +2,7 @@ * @file networkparamsconst.cpp * */ -/* Copyright (C) 2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -36,7 +36,6 @@ const char NetworkParamsConst::DEFAULT_GATEWAY[] = "default_gateway"; const char NetworkParamsConst::HOSTNAME[] = "hostname"; const char NetworkParamsConst::NTP_SERVER[] = "ntp_server"; -const char NetworkParamsConst::NTP_UTC_OFFSET[] = "ntp_utc_offset"; #if defined (ESP8266) const char NetworkParamsConst::NAME_SERVER[] = "name_server"; diff --git a/lib-network/src/params/networkparamsdump.cpp b/lib-network/src/params/networkparamsdump.cpp deleted file mode 100644 index ada0652d..00000000 --- a/lib-network/src/params/networkparamsdump.cpp +++ /dev/null @@ -1,58 +0,0 @@ -/** - * @file networkparamsdump.cpp - * - */ -/* Copyright (C) 2020 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#if !defined(__clang__) // Needed for compiling on MacOS -# pragma GCC push_options -# pragma GCC optimize ("Os") -#endif - -#include - -#include "network.h" -#include "networkparams.h" -#include "networkparamsconst.h" - -#include "debug.h" - -void NetworkParams::Dump() { -#ifndef NDEBUG - printf("%s::%s \'%s\':\n", __FILE__, __FUNCTION__, NetworkParamsConst::FILE_NAME); - - debug_print_bits(m_Params.nSetList); - - printf(" %s=%d [%s]\n", NetworkParamsConst::USE_DHCP, static_cast(m_Params.bIsDhcpUsed), m_Params.bIsDhcpUsed != 0 ? "Yes" : "No"); - printf(" %s=" IPSTR "\n", NetworkParamsConst::IP_ADDRESS, IP2STR(m_Params.nLocalIp)); - printf(" %s=" IPSTR "\n", NetworkParamsConst::NET_MASK, IP2STR(m_Params.nNetmask)); - -#if defined (ESP8266) - printf(" %s=" IPSTR "\n", NetworkParamsConst::DEFAULT_GATEWAY, IP2STR(m_Params.nGatewayIp)); - printf(" %s=" IPSTR "\n", NetworkParamsConst::NAME_SERVER, IP2STR(m_Params.nNameServerIp)); -#endif - - printf(" %s=%s\n", NetworkParamsConst::HOSTNAME, m_Params.aHostName); - printf(" %s=" IPSTR "\n", NetworkParamsConst::NTP_SERVER, IP2STR(m_Params.nNtpServerIp)); - printf(" %s=%1.1f\n", NetworkParamsConst::NTP_UTC_OFFSET, m_Params.fNtpUtcOffset); -#endif -} diff --git a/lib-osc/.cproject b/lib-osc/.cproject new file mode 100755 index 00000000..9b0f24de --- /dev/null +++ b/lib-osc/.cproject @@ -0,0 +1,216 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/lib-c++/.project b/lib-osc/.project old mode 100644 new mode 100755 similarity index 94% rename from lib-c++/.project rename to lib-osc/.project index bb75ddd3..573102de --- a/lib-c++/.project +++ b/lib-osc/.project @@ -1,6 +1,6 @@ - lib-c++ + lib-osc diff --git a/lib-rdmdiscovery/.settings/language.settings.xml b/lib-osc/.settings/language.settings.xml old mode 100644 new mode 100755 similarity index 93% rename from lib-rdmdiscovery/.settings/language.settings.xml rename to lib-osc/.settings/language.settings.xml index 4d2bde8f..a20879f9 --- a/lib-rdmdiscovery/.settings/language.settings.xml +++ b/lib-osc/.settings/language.settings.xml @@ -1,12 +1,12 @@ - - - - - - - - - - - + + + + + + + + + + + \ No newline at end of file diff --git a/lib-osc/.settings/org.eclipse.cdt.codan.core.prefs b/lib-osc/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100755 index 00000000..a007028e --- /dev/null +++ b/lib-osc/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,107 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.codan.checkers.errnoreturn=Warning +org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false} +org.eclipse.cdt.codan.checkers.errreturnvalue=Error +org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"} +org.eclipse.cdt.codan.checkers.localvarreturn=Warning +org.eclipse.cdt.codan.checkers.localvarreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Returning the address of a local variable\\")"} +org.eclipse.cdt.codan.checkers.nocommentinside=Error +org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"} +org.eclipse.cdt.codan.checkers.nolinecomment=Error +org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"} +org.eclipse.cdt.codan.checkers.noreturn=Error +org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false} +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"} +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous problem\\")"} +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment in condition\\")"} +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment to itself\\")"} +org.eclipse.cdt.codan.internal.checkers.BlacklistProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.BlacklistProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function or method is blacklisted\\")",blacklist\=>()} +org.eclipse.cdt.codan.internal.checkers.CStyleCastProblem=Warning +org.eclipse.cdt.codan.internal.checkers.CStyleCastProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"C-Style cast instead of C++ cast\\")",checkMacro\=>true} +org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning +org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No break at end of case\\")",no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false,enable_fallthrough_quickfix_param\=>false} +org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning +org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Catching by reference is recommended\\")",unknown\=>false,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Circular inheritance\\")"} +org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization=Warning +org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class members should be properly initialized\\")",skip\=>true} +org.eclipse.cdt.codan.internal.checkers.CopyrightProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.CopyrightProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Lack of copyright information\\")",regex\=>".*Copyright.*"} +org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem=Error +org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid 'decltype(auto)' specifier\\")"} +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Field cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.FloatCompareProblem=Warning +org.eclipse.cdt.codan.internal.checkers.FloatCompareProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Direct float comparison\\")"} +org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem=Warning +org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Goto statement used\\")"} +org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error +org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid arguments\\")"} +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"} +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"} +org.eclipse.cdt.codan.internal.checkers.MagicNumberProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MagicNumberProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Avoid magic numbers\\")",checkArray\=>true,checkOperatorParen\=>true,exceptions\=>(1,0,-1,2,1.0,0.0,-1.0)} +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Member declaration not found\\")"} +org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Method cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.MissCaseProblem=Warning +org.eclipse.cdt.codan.internal.checkers.MissCaseProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing cases in switch\\")"} +org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem=Warning +org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing default in switch\\")",defaultWithAllEnums\=>false} +org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem=Warning +org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing reference return value in assignment operator\\")"} +org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem=Warning +org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing self check in assignment operator\\")"} +org.eclipse.cdt.codan.internal.checkers.MultipleDeclarationsProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MultipleDeclarationsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Multiple variable declaration\\")"} +org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker=-Info +org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Name convention for function\\")",pattern\=>"^[a-z]",macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem=Warning +org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class has a virtual method and non-virtual destructor\\")"} +org.eclipse.cdt.codan.internal.checkers.OverloadProblem=Error +org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid overload\\")"} +org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem=Error +org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redeclaration\\")"} +org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem=Error +org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redefinition\\")"} +org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"} +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"} +org.eclipse.cdt.codan.internal.checkers.ShallowCopyProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ShallowCopyProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Miss copy constructor or assignment operator\\")",onlynew\=>false} +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Statement has no effect\\")",macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.StaticVariableInHeaderProblem=Warning +org.eclipse.cdt.codan.internal.checkers.StaticVariableInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Static variable in header file\\")"} +org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning +org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suggested parenthesis around expression\\")",paramNot\=>false} +org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning +org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suspicious semicolon\\")",else\=>false,afterelse\=>false} +org.eclipse.cdt.codan.internal.checkers.SymbolShadowingProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.SymbolShadowingProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol shadowing\\")",paramFuncParameters\=>true} +org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")} +org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Using directive in header\\")"} +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem=Error +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Virtual method call in constructor/destructor\\")"} diff --git a/gd32_rdm_responder/.settings/org.eclipse.cdt.core.prefs b/lib-osc/.settings/org.eclipse.cdt.core.prefs old mode 100644 new mode 100755 similarity index 100% rename from gd32_rdm_responder/.settings/org.eclipse.cdt.core.prefs rename to lib-osc/.settings/org.eclipse.cdt.core.prefs diff --git a/lib-debug/.settings/org.eclipse.core.resources.prefs b/lib-osc/.settings/org.eclipse.core.resources.prefs similarity index 100% rename from lib-debug/.settings/org.eclipse.core.resources.prefs rename to lib-osc/.settings/org.eclipse.core.resources.prefs diff --git a/lib-rdmresponder/Makefile.GD32 b/lib-osc/Makefile.GD32 old mode 100644 new mode 100755 similarity index 86% rename from lib-rdmresponder/Makefile.GD32 rename to lib-osc/Makefile.GD32 index 5f6d2d93..710ad717 --- a/lib-rdmresponder/Makefile.GD32 +++ b/lib-osc/Makefile.GD32 @@ -2,5 +2,7 @@ DEFINES=NDEBUG EXTRA_INCLUDES= +EXTRA_SRCDIR= + include Rules.mk include ../firmware-template-gd32/lib/Rules.mk \ No newline at end of file diff --git a/lib-osc/Rules.mk b/lib-osc/Rules.mk new file mode 100755 index 00000000..20152ce3 --- /dev/null +++ b/lib-osc/Rules.mk @@ -0,0 +1,24 @@ +$(info [${CURDIR}]) +$(info $$MAKE_FLAGS [${MAKE_FLAGS}]) + +EXTRA_INCLUDES+=../lib-display/include ../lib-properties/include ../lib-network/include + +ifneq ($(MAKE_FLAGS),) + ifneq (,$(findstring NODE_OSC_CLIENT,$(MAKE_FLAGS))) + EXTRA_SRCDIR+=src/client + DO_INCLUDE=1 + endif + ifneq (,$(findstring NODE_OSC_SERVER,$(MAKE_FLAGS))) + EXTRA_SRCDIR+=src/server + EXTRA_INCLUDES+=../lib-lightset/include + DO_INCLUDE=1 + endif +else + EXTRA_SRCDIR+=src/client + EXTRA_SRCDIR+=src/server + DO_INCLUDE=1 +endif + +ifdef DO_INCLUDE + EXTRA_INCLUDES+=../lib-display/include ../lib-properties/include ../lib-network/include +endif \ No newline at end of file diff --git a/lib-osc/include/osc.h b/lib-osc/include/osc.h new file mode 100644 index 00000000..156f45b2 --- /dev/null +++ b/lib-osc/include/osc.h @@ -0,0 +1,93 @@ +/** + * @file osc.h + * + */ +/* Copyright (C) 2016-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef OSC_H_ +#define OSC_H_ + +#include + +namespace osc { +namespace validate { +static constexpr auto INVALID_SIZE = 1; +static constexpr auto NOT_TERMINATED = 2; +static constexpr auto NONE_ZERO_IN_PADDING = 3; +} // namespace validate +namespace type { +/* basic OSC types */ +/* 32 bit signed integer. */ +static constexpr char INT32 = 'i'; +/* 32 bit IEEE-754 float. */ +static constexpr char FLOAT = 'f'; +/* Standard C, NULL terminated string. */ +static constexpr char STRING = 's'; +/* OSC binary blob type. */ +static constexpr char BLOB = 'b'; +/* extended OSC types */ +/* 64 bit signed integer. */ +static constexpr char INT64 = 'h'; +/* OSC TimeTag type. */ +static constexpr char TIMETAG = 't'; +/* 64 bit IEEE-754 double. */ +static constexpr char DOUBLE = 'd'; +/* Standard C, NULL terminated, string. Used in systems which distinguish strings and symbols. */ +static constexpr char SYMBOL = 'S'; +/* Standard C, 8 bit, char variable. */ +static constexpr char CHAR = 'c'; +/* A 4 byte MIDI packet. */ +static constexpr char MIDI = 'm'; +/* Symbol representing the value True. */ +static constexpr char TRUE = 'T'; +/* Symbol representing the value False. */ +static constexpr char FALSE = 'F'; +/* Symbol representing the value Nil. */ +static constexpr char NIL = 'N'; +/* Symbol representing the value Infinitum. */ +static constexpr char INFINITUM = 'I'; +/* */ +static constexpr char UNKNOWN = '\0'; +} // namespace type +namespace port { +static constexpr uint16_t DEFAULT_INCOMING = 8000; +static constexpr uint16_t DEFAULT_OUTGOING = 9000; +} // namespace port +} // namespace osc + +extern "C" { +int lo_pattern_match(const char *, const char *); +} + +#include "oscstring.h" + +namespace osc { +inline static char *get_path(void *pPath, unsigned nSize) { + return (string_validate(pPath, nSize) >= 4) ? reinterpret_cast(pPath) : nullptr; +} + +inline static bool is_match(const char *str, const char *p) { + return lo_pattern_match(str, p) == 0 ? false : true; +} +} // namespace osc + +#endif /* OSC_H_ */ diff --git a/lib-rdmdiscovery/include/rdmdiscovery.h b/lib-osc/include/oscblob.h similarity index 57% rename from lib-rdmdiscovery/include/rdmdiscovery.h rename to lib-osc/include/oscblob.h index df7e6f90..fe0346ea 100644 --- a/lib-rdmdiscovery/include/rdmdiscovery.h +++ b/lib-osc/include/oscblob.h @@ -1,8 +1,8 @@ /** - * @file rdmddiscovery.h + * @file oscblob.h * */ -/* Copyright (C) 2017-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2016-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,39 +23,48 @@ * THE SOFTWARE. */ -#ifndef RDMDISCOVERY_H_ -#define RDMDISCOVERY_H_ +#ifndef OSCBLOB_H_ +#define OSCBLOB_H_ #include -#include "rdm.h" - -#include "rdmmessage.h" -#include "rdmtod.h" +/* + * OSC-blob + * An int32 size count, followed by that many 8-bit bytes of arbitrary binary data, + * followed by 0-3 additional zero bytes to make the total number of bits a multiple of 32. + */ -class RDMDiscovery { +class OSCBlob { public: - RDMDiscovery(const uint8_t *pUid); + OSCBlob(const uint8_t *pData, uint32_t nSize) : + m_pData(const_cast(pData)), m_nSize(nSize) { + } + ~OSCBlob() { + } - void Full(uint32_t m_nPortIndex, RDMTod *pRDMTod); + uint32_t GetDataSize() { + return m_nSize; + } -private: - bool FindDevices(uint64_t LowerBound, uint64_t UpperBound); - bool QuickFind(const uint8_t *pUid); + const uint8_t* GetDataPtr() { + return m_pData; + } - bool IsValidDiscoveryResponse(const uint8_t *pDiscResponse, uint8_t *pUid); + uint32_t GetSize() { + const uint32_t nBlobSize = sizeof(int32_t) + m_nSize; + return (4 * ((nBlobSize + 3) / 4)); + } - void PrintUid(uint64_t nUid); - void PrintUid(const uint8_t *pUid); - const uint8_t *ConvertUid(uint64_t nUid); - uint64_t ConvertUid(const uint8_t *pUid); + uint8_t GetByte(uint32_t nIndex) { + if (nIndex < m_nSize) { + return m_pData[nIndex]; + } + return 0; + } private: - RDMMessage m_Message; - uint32_t m_nPortIndex; - RDMTod *m_pRDMTod; - uint8_t m_Uid[RDM_UID_SIZE]; - uint8_t m_Pdl[2][RDM_UID_SIZE]; + uint8_t *m_pData; + uint32_t m_nSize; }; -#endif /* RDMDISCOVERY_H_ */ +#endif /* OSCBLOB_H_ */ diff --git a/lib-osc/include/oscclient.h b/lib-osc/include/oscclient.h new file mode 100755 index 00000000..de81dc8a --- /dev/null +++ b/lib-osc/include/oscclient.h @@ -0,0 +1,147 @@ +/** + * @file oscclient.h + * + */ +/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef OSCCLIENT_H_ +#define OSCCLIENT_H_ + +#include +#include + +#include "oscclientled.h" + +namespace oscclient { +static constexpr auto STORE = 944; ///< Configuration store in bytes +namespace defaults { +static constexpr auto PORT_OUTGOING = 8000; +static constexpr auto PORT_INCOMING = 9000; +static constexpr auto PING_DELAY_SECONDS = 10; +} // namespace defaults +namespace max { +static constexpr uint32_t CMD_COUNT = 8; +static constexpr uint32_t CMD_PATH_LENGTH = 64; +static constexpr uint32_t LED_COUNT = 8; +static constexpr uint32_t LED_PATH_LENGTH = 48; +} // namespace max +namespace buffer { +namespace size { +static constexpr uint32_t CMD = oscclient::max::CMD_COUNT * oscclient::max::CMD_PATH_LENGTH; +static constexpr uint32_t LED = oscclient::max::LED_COUNT * oscclient::max::LED_PATH_LENGTH; +} // namespace size +} // namespace buffer +} // namespace oscclient + +class OscClient { +public: + OscClient(); + ~OscClient() { + Stop(); + } + + void Start(); + void Stop(); + + void Run(); + + void Send(const char *pPath); + void SendCmd(uint32_t nCmd); + + void Print(); + + void SetServerIP(uint32_t nServerIP) { + m_nServerIP = nServerIP; + } + + uint32_t GetServerIP() const { + return m_nServerIP; + } + + void SetPortOutgoing(uint16_t nPortOutgoing) { + assert(nPortOutgoing > 1023); + m_nPortOutgoing = nPortOutgoing; + } + + uint16_t GetPortOutgoing() const { + return m_nPortOutgoing; + } + + void SetPortIncoming(uint16_t nPortIncoming) { + assert(nPortIncoming > 1023); + m_nPortIncoming = nPortIncoming; + } + + uint16_t GetPortIncoming() const { + return m_nPortIncoming; + } + + void SetPingDisable(bool nPingDisable = true) { + m_bPingDisable = nPingDisable; + } + + bool GetPingDisable() const { + return m_bPingDisable; + } + + void SetPingDelay(uint32_t nPingDelay = oscclient::defaults::PING_DELAY_SECONDS) { + if ((nPingDelay >=2) && (nPingDelay <= 60)) { + m_nPingDelayMillis = nPingDelay * 1000; + } + } + + uint32_t GetPingDelay() const { + return m_nPingDelayMillis / 1000U; + } + + void CopyCmds(const char *pCmds, uint32_t nCount, uint32_t nLength); + void CopyLeds(const char *pLeds, uint32_t nCount, uint32_t nLength); + + void SetLedHandler(OscClientLed *pOscClientLed) { + assert(pOscClientLed != nullptr); + m_pOscClientLed = pOscClientLed; + } + +private: + bool HandleLedMessage(const uint16_t nBytesReceived); + +private: + uint32_t m_nServerIP { 0 }; + uint16_t m_nPortOutgoing; + uint16_t m_nPortIncoming; + int32_t m_nHandle { -1 }; + bool m_bPingDisable { false }; + uint32_t m_nPingDelayMillis; + bool m_bPingSent { false }; + bool m_bPongReceived { false }; + char *m_pBuffer { nullptr }; + uint32_t m_nCurrenMillis { 0 }; + uint32_t m_nPreviousMillis { 0 }; + uint32_t m_nPingTimeMillis { 0 }; + + OscClientLed *m_pOscClientLed { nullptr }; + + static char m_pCmds[oscclient::buffer::size::CMD]; + static char m_pLeds[oscclient::buffer::size::LED]; +}; + +#endif /* OSCCLIENT_H_ */ diff --git a/lib-osc/include/oscclientled.h b/lib-osc/include/oscclientled.h new file mode 100755 index 00000000..883921c4 --- /dev/null +++ b/lib-osc/include/oscclientled.h @@ -0,0 +1,36 @@ +/** + * @file oscclientled.h + * + */ +/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef OSCCLIENTLED_H_ +#define OSCCLIENTLED_H_ + +class OscClientLed { +public: + virtual ~OscClientLed() {} + + virtual void SetLed(const uint32_t nLed, const bool bOn) = 0; +}; + +#endif /* OSCCLIENTLED_H_ */ diff --git a/lib-configstore/src/rdm/storerdmdevice.cpp b/lib-osc/include/oscclientmsgconst.h old mode 100644 new mode 100755 similarity index 78% rename from lib-configstore/src/rdm/storerdmdevice.cpp rename to lib-osc/include/oscclientmsgconst.h index f7232a9d..2af28069 --- a/lib-configstore/src/rdm/storerdmdevice.cpp +++ b/lib-osc/include/oscclientmsgconst.h @@ -1,5 +1,5 @@ /** - * @file storerdmdevice.cpp + * @file oscclientconst.h * */ /* Copyright (C) 2019-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl @@ -23,21 +23,13 @@ * THE SOFTWARE. */ -#include +#ifndef OSCCLIENTMSGCONST_H_ +#define OSCCLIENTMSGCONST_H_ -#include "storerdmdevice.h" - -#include "debug.h" - -StoreRDMDevice *StoreRDMDevice::s_pThis = nullptr; - -StoreRDMDevice::StoreRDMDevice() { - DEBUG_ENTRY - - assert(s_pThis == nullptr); - s_pThis = this; - - DEBUG_PRINTF("%p", reinterpret_cast(s_pThis)); - DEBUG_EXIT -} +struct OscClientMsgConst { + static const char PARAMS[]; + static const char START[]; + static const char STARTED[]; +}; +#endif /* OSCCLIENTMSGCONST_H_ */ diff --git a/lib-osc/include/oscclientparams.h b/lib-osc/include/oscclientparams.h new file mode 100755 index 00000000..0a9b151b --- /dev/null +++ b/lib-osc/include/oscclientparams.h @@ -0,0 +1,119 @@ +/** + * @file oscclientparams.h + * + */ +/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef OSCCLIENTPARAMS_H_ +#define OSCCLIENTPARAMS_H_ + +#include + +#include "oscclient.h" +#include "configstore.h" + +namespace oscclientparams { +struct ParamsMax { + static constexpr uint32_t CMD_COUNT = 8; + static constexpr uint32_t CMD_PATH_LENGTH = 64; + static constexpr uint32_t LED_COUNT = 8; + static constexpr uint32_t LED_PATH_LENGTH = 48; +}; + +struct Params { + uint32_t nSetList; + uint32_t nServerIp; + uint16_t nOutgoingPort; + uint16_t nIncomingPort; + uint8_t nPingDisable; + uint8_t nPingDelay; + char aCmd[ParamsMax::CMD_COUNT][ParamsMax::CMD_PATH_LENGTH]; + char aLed[ParamsMax::LED_COUNT][ParamsMax::LED_PATH_LENGTH]; +} __attribute__((packed)); + +static_assert(sizeof(struct oscclientparams::Params) <= oscclient::STORE, "struct Params is too large"); + +struct Mask { + static constexpr auto SERVER_IP = (1U << 0); + static constexpr auto OUTGOING_PORT = (1U << 1); + static constexpr auto INCOMING_PORT = (1U << 2); + static constexpr auto PING_DISABLE = (1U << 3); + static constexpr auto PING_DELAY = (1U << 4); + static constexpr auto CMD = (1U << 5); + static constexpr auto LED = (1U << 6); +}; +} // namespace oscclientparams + +class OscClientParamsStore { +public: + static void Update(const struct oscclientparams::Params *pParams) { + ConfigStore::Get()->Update(configstore::Store::OSC_CLIENT, pParams, sizeof(struct oscclientparams::Params)); + } + + static void Copy(struct oscclientparams::Params *pParams) { + ConfigStore::Get()->Copy(configstore::Store::OSC_CLIENT, pParams, sizeof(struct oscclientparams::Params)); + } +}; + +class OscClientParams { +public: + OscClientParams(); + + void Load(); + void Load(const char *pBuffer, uint32_t nLength); + + void Builder(const struct oscclientparams::Params *pParams, char *pBuffer, uint32_t nLength, uint32_t& nSize); + void Save(char *pBuffer, uint32_t nLength, uint32_t& nSize) { + Builder(nullptr, pBuffer, nLength, nSize); + } + + void Set(OscClient *pOscClient); + + uint32_t GetServerIP() { + return m_Params.nServerIp; + } + + uint16_t GetOutgoingPort() { + return m_Params.nOutgoingPort; + } + + uint16_t GetIncomingPort() { + return m_Params.nIncomingPort; + } + +public: + static void staticCallbackFunction(void *p, const char *s); + +private: + void Dump(); + void callbackFunction(const char *s); + bool isMaskSet(uint32_t nMask) const { + return (m_Params.nSetList & nMask) == nMask; + } + +private: + oscclientparams::Params m_Params; + char m_aCmd[8]; + char m_aLed[8]; +}; + +#endif /* OSCCLIENTPARAMS_H_ */ diff --git a/lib-osc/include/oscclientparamsconst.h b/lib-osc/include/oscclientparamsconst.h new file mode 100755 index 00000000..0d0804d0 --- /dev/null +++ b/lib-osc/include/oscclientparamsconst.h @@ -0,0 +1,43 @@ +/** + * @file oscclientparamsconst.h + * + */ +/* Copyright (C) 2019 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef OSCCLIENTPARAMSCONST_H_ +#define OSCCLIENTPARAMSCONST_H_ + +#include + +struct OscClientParamsConst { + static const char FILE_NAME[]; + + static const char SERVER_IP[]; + + static const char PING_DISABLE[]; + static const char PING_DELAY[]; + + static const char CMD[]; + static const char LED[]; +}; + +#endif /* OSCCLIENTPARAMSCONST_H_ */ diff --git a/lib-osc/include/oscparamsconst.h b/lib-osc/include/oscparamsconst.h new file mode 100644 index 00000000..521ae0c6 --- /dev/null +++ b/lib-osc/include/oscparamsconst.h @@ -0,0 +1,34 @@ +/** + * @file oscconst.h + * + */ +/* Copyright (C) 2020 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef OSCPARAMSCONST_H_ +#define OSCPARAMSCONST_H_ + +struct OscParamsConst { + static const char INCOMING_PORT[]; + static const char OUTGOING_PORT[]; +}; + +#endif /* OSCPARAMSCONST_H_ */ diff --git a/lib-osc/include/oscserver.h b/lib-osc/include/oscserver.h new file mode 100755 index 00000000..2f73c666 --- /dev/null +++ b/lib-osc/include/oscserver.h @@ -0,0 +1,165 @@ +/** + * @file oscserver.h + * + */ +/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef OSCSERVER_H_ +#define OSCSERVER_H_ + +#include +#include + +#include "lightset.h" + +namespace osc { +namespace server { +struct DefaultPort { + static constexpr auto INCOMING = 8000U; + static constexpr auto OUTGOING = 9000U; +}; + +struct Max { + static constexpr auto PATH_LENGTH = 128U; +}; +} // namespace server +} // namespace osc + +class OscServerHandler { +public: + virtual ~OscServerHandler() {} + virtual void Blackout()=0; + virtual void Update()=0; + virtual void Info(int32_t nHandle, uint32_t nRemoteIp, uint16_t nPortOutgoing)=0; +}; + +class OscServer { +public: + OscServer(); + ~OscServer(); + + void SetOutput(LightSet *pLightSet) { + assert(pLightSet != nullptr); + m_pLightSet = pLightSet; + } + + void SetOscServerHandler(OscServerHandler *pOscServerHandler) { + assert(pOscServerHandler != nullptr); + m_pOscServerHandler = pOscServerHandler; + } + + void SetPortIncoming(uint16_t nPortIncoming = osc::server::DefaultPort::INCOMING) { + assert(nPortIncoming > 1023); + m_nPortIncoming = nPortIncoming; + } + + uint16_t GetPortIncoming() const { + return m_nPortIncoming; + } + + void SetPortOutgoing(uint16_t nPortOutgoing) { + assert(nPortOutgoing > 1023); + m_nPortOutgoing = nPortOutgoing; + } + + uint16_t GetPortOutgoing() const { + return m_nPortOutgoing; + } + + void SetPath(const char *pPath); + + const char*GetPath() { + return s_aPath; + } + + void SetPathInfo(const char *pPathInfo); + + const char*GetPathInfo() { + return s_aPathInfo; + } + + void SetPathBlackOut(const char *pPathBlackOut); + + const char*GetPathBlackOut() { + return s_aPathBlackOut; + } + + void SetPartialTransmission(bool bPartialTransmission = false) { + m_bPartialTransmission = bPartialTransmission; + } + + bool IsPartialTransmission() const { + return m_bPartialTransmission; + } + + void SetEnableNoChangeUpdate(bool bEnableNoChangeUpdate) { + m_bEnableNoChangeUpdate = bEnableNoChangeUpdate; + } + bool GetEnableNoChangeUpdate() { + return m_bEnableNoChangeUpdate; + } + + void Print(); + + void Start(); + void Stop(); + + void Run(); + + static OscServer* Get() { + return s_pThis; + } + +private: + int GetChannel(const char *p); + bool IsDmxDataChanged(const uint8_t *pData, uint16_t nStartChannel, uint32_t nLength); + +private: + uint16_t m_nPortIncoming { osc::server::DefaultPort::INCOMING }; + uint16_t m_nPortOutgoing { osc::server::DefaultPort::OUTGOING }; + int32_t m_nHandle { -1 }; + uint16_t m_nLastChannel { 0 }; + + bool m_bPartialTransmission { false }; + bool m_bEnableNoChangeUpdate { false }; + bool m_bIsRunning { false }; + char m_Os[32]; + + OscServerHandler *m_pOscServerHandler { nullptr }; + LightSet *m_pLightSet { nullptr }; + + const char *m_pModel; + const char *m_pSoC; + + static char s_aPath[osc::server::Max::PATH_LENGTH]; + static char s_aPathSecond[osc::server::Max::PATH_LENGTH]; + static char s_aPathInfo[osc::server::Max::PATH_LENGTH]; + static char s_aPathBlackOut[osc::server::Max::PATH_LENGTH]; + + static uint8_t s_pData[lightset::dmx::UNIVERSE_SIZE]; + static uint8_t s_pOsc[lightset::dmx::UNIVERSE_SIZE]; + + static char *s_pUdpBuffer; + static OscServer *s_pThis; +}; + +#endif /* OSCSERVER_H_ */ diff --git a/lib-osc/include/oscserverconst.h b/lib-osc/include/oscserverconst.h new file mode 100755 index 00000000..863c6cc9 --- /dev/null +++ b/lib-osc/include/oscserverconst.h @@ -0,0 +1,35 @@ +/** + * @file oscserverconst.h + * + */ +/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef OSCSERVERCONST_H_ +#define OSCSERVERCONST_H_ + +struct OSCServerConst { + static const char MSG_BRIDGE_PARAMS[]; + static const char MSG_BRIDGE_START[]; + static const char MSG_BRIDGE_STARTED[]; +}; + +#endif /* OSCSERVERCONST_H_ */ diff --git a/lib-configstore/src/rdm/storerdmsensors.cpp b/lib-osc/include/oscservermsgconst.h old mode 100644 new mode 100755 similarity index 78% rename from lib-configstore/src/rdm/storerdmsensors.cpp rename to lib-osc/include/oscservermsgconst.h index a4ff5058..46626238 --- a/lib-configstore/src/rdm/storerdmsensors.cpp +++ b/lib-osc/include/oscservermsgconst.h @@ -1,5 +1,5 @@ /** - * @file storerdmsensors.cpp + * @file oscservermsgconst.h * */ /* Copyright (C) 2020 by Arjan van Vught mailto:info@orangepi-dmx.nl @@ -23,20 +23,13 @@ * THE SOFTWARE. */ -#include +#ifndef OSCSERVERMSGCONST_H_ +#define OSCSERVERMSGCONST_H_ -#include "storerdmsensors.h" +struct OscServerMsgConst { + static const char PARAMS[]; + static const char START[]; + static const char STARTED[]; +}; -#include "debug.h" - -StoreRDMSensors *StoreRDMSensors::s_pThis = nullptr; - -StoreRDMSensors::StoreRDMSensors() { - DEBUG_ENTRY - - assert(s_pThis == nullptr); - s_pThis = this; - - DEBUG_PRINTF("%p", reinterpret_cast(s_pThis)); - DEBUG_EXIT -} +#endif /* OSCSERVERMSGCONST_H_ */ diff --git a/lib-osc/include/oscserverparams.h b/lib-osc/include/oscserverparams.h new file mode 100755 index 00000000..1e08af7e --- /dev/null +++ b/lib-osc/include/oscserverparams.h @@ -0,0 +1,110 @@ +/** + * @file oscserverparams.h + * + */ +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef OSCSERVERPARAMS_H_ +#define OSCSERVERPARAMS_H_ + +#include + +#include "oscserver.h" +#include "configstore.h" +#include "lightset.h" + +namespace osc { +namespace server { +struct Params { + uint32_t nSetList; + uint16_t nIncomingPort; + uint16_t nOutgoingPort; + uint8_t tOutputType; + bool bPartialTransmission; + char aPath[osc::server::Max::PATH_LENGTH]; + char aPathInfo[osc::server::Max::PATH_LENGTH]; + char aPathBlackOut[osc::server::Max::PATH_LENGTH]; +} __attribute__((packed)); + +struct ParamsMask { + static constexpr uint32_t INCOMING_PORT = (1U << 0); + static constexpr uint32_t OUTGOING_PORT = (1U << 1); + static constexpr uint32_t PATH = (1U << 2); + static constexpr uint32_t TRANSMISSION = (1U << 3); + static constexpr uint32_t OUTPUT = (1U << 4); + static constexpr uint32_t PATH_INFO = (1U << 5); + static constexpr uint32_t PATH_BLACKOUT = (1U << 6); +}; +} // namespace server +} // namespace osc + +class StoreOscServer { +public: + static void Update(const struct osc::server::Params *pParams) { + ConfigStore::Get()->Update(configstore::Store::OSC, pParams, sizeof(struct osc::server::Params)); + } + + static void Copy(struct osc::server::Params *pParams) { + ConfigStore::Get()->Copy(configstore::Store::OSC, pParams, sizeof(struct osc::server::Params)); + } +}; + +class OSCServerParams { +public: + OSCServerParams(); + + void Load(); + void Load(const char *pBuffer, uint32_t nLength); + + void Builder(const osc::server::Params *pParams, char *pBuffer, uint32_t nLength, uint32_t& nSize); + void Save(char *pBuffer, uint32_t nLength, uint32_t& nSize) { + Builder(nullptr, pBuffer, nLength, nSize); + } + + void Set(OscServer *pOscServer); + + uint16_t GetIncomingPort() const { + return m_Params.nIncomingPort; + } + + uint16_t GetOutgoingPort() const { + return m_Params.nOutgoingPort; + } + + bool GetPartialTransmission() const { + return m_Params.bPartialTransmission; + } + + static void staticCallbackFunction(void *p, const char *s); + +private: + void Dump(); + void callbackFunction(const char *s); + bool isMaskSet(uint32_t nMask) const { + return (m_Params.nSetList & nMask) == nMask; + } + +private: + osc::server::Params m_Params; +}; + +#endif /* OSCSERVERPARAMS_H_ */ diff --git a/lib-display/src/display_timeout.cpp b/lib-osc/include/oscserverparamsconst.h old mode 100644 new mode 100755 similarity index 77% rename from lib-display/src/display_timeout.cpp rename to lib-osc/include/oscserverparamsconst.h index 5b403dd1..5649e1d6 --- a/lib-display/src/display_timeout.cpp +++ b/lib-osc/include/oscserverparamsconst.h @@ -1,5 +1,5 @@ /** - * @file display_timeout.cpp + * @file oscserverparamsconst.h * */ /* Copyright (C) 2022 by Arjan van Vught mailto:info@orangepi-dmx.nl @@ -23,9 +23,17 @@ * THE SOFTWARE. */ -namespace display { -namespace timeout { -void __attribute__((weak)) gpio_init() {} -bool __attribute__((weak)) gpio_renew() { return false;} -} // namespace timeout -} // namespace display +#ifndef OSCSERVERPARAMSCONST_H_ +#define OSCSERVERPARAMSCONST_H_ + +struct OscServerParamsConst { + static const char FILE_NAME[]; + + static const char PATH[]; + static const char PATH_INFO[]; + static const char PATH_BLACKOUT[]; + + static const char TRANSMISSION[]; +}; + +#endif /* OSCSERVERPARAMSCONST_H_ */ diff --git a/lib-osc/include/oscsimplemessage.h b/lib-osc/include/oscsimplemessage.h new file mode 100644 index 00000000..fa15a01a --- /dev/null +++ b/lib-osc/include/oscsimplemessage.h @@ -0,0 +1,73 @@ +/** + * @file oscsimplemessage.h + * + */ +/* Copyright (C) 2020 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef OSCSIMPLEMESSAGE_H_ +#define OSCSIMPLEMESSAGE_H_ + +#include + +#include "osc.h" +#include "oscblob.h" + +class OscSimpleMessage { +public: + OscSimpleMessage(void *pData, unsigned nLength); + + bool IsValid() { + return m_bIsValid; + } + + int GetArgc() { + if (m_bIsValid) { + return static_cast(m_nArgc); + } + + return -1; + } + + char GetType(unsigned argc) { + if (argc < m_nArgc) { + return static_cast(m_pArg[argc]); + } + + return osc::type::UNKNOWN; + } + + float GetFloat(unsigned argc); + int GetInt(unsigned argc); + char* GetString(unsigned argc); + OSCBlob GetBlob(unsigned argc); + +private: + uint8_t *m_pOscMessage; + uint32_t m_nLength; + bool m_bIsValid = false; + uint8_t *m_pArg; + uint32_t m_nArgc = 0; + uint8_t *m_pOscMessageData = nullptr; + uint32_t m_nOscMessageDataLength = 0; +}; + +#endif /* OSCSIMPLEMESSAGE_H_ */ diff --git a/lib-osc/include/oscsimplesend.h b/lib-osc/include/oscsimplesend.h new file mode 100644 index 00000000..912c8025 --- /dev/null +++ b/lib-osc/include/oscsimplesend.h @@ -0,0 +1,58 @@ +/** + * @file oscsimplesend.h + * + */ +/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef OSCSIMPLESEND_H_ +#define OSCSIMPLESEND_H_ + +#include + +namespace osc { +namespace simple { +namespace send { +static constexpr auto BUFFER_SIZE = 512U; +} // namespace send +} // namespace simple +} // namespace osc + +class OscSimpleSend { +public: + // Support for path only + OscSimpleSend(int32_t nHandle, uint32_t nIpAddress , uint16_t nPort, const char *pPath, const char *pType); + // Support for 's' + OscSimpleSend(int32_t nHandle, uint32_t nIpAddress , uint16_t nPort, const char *pPath, const char *pType, const char *pString); + // Support for type 'i' + OscSimpleSend(int32_t nHandle, uint32_t nIpAddress , uint16_t nPort, const char *pPath, const char *pType, int nValue); + // Support for type 'f' + OscSimpleSend(int32_t nHandle, uint32_t nIpAddress , uint16_t nPort, const char *pPath, const char *pType, float fValue); + +private: + void UpdateMessage(const char *pPath, uint32_t nPathLength, char cType); + void Send(uint32_t nMessageLength, int32_t nHandle, uint32_t nIpAddress, uint16_t nPort); + +private: + static char s_Message[osc::simple::send::BUFFER_SIZE]; +}; + +#endif /* OSCSIMPLESEND_H_ */ diff --git a/lib-ws28xxdmx/include/ws28xxdmxstartstop.h b/lib-osc/include/oscstring.h similarity index 52% rename from lib-ws28xxdmx/include/ws28xxdmxstartstop.h rename to lib-osc/include/oscstring.h index ab14753f..5658cf38 100644 --- a/lib-ws28xxdmx/include/ws28xxdmxstartstop.h +++ b/lib-osc/include/oscstring.h @@ -1,8 +1,8 @@ /** - * @file pixeldmxstartstop.h + * @file oscstring.h * */ -/* Copyright (C) 2020-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2016-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,32 +23,53 @@ * THE SOFTWARE. */ -#ifndef WS28XXDMXSTARTSTOP_H_ -#define WS28XXDMXSTARTSTOP_H_ +#ifndef OSCSTRING_H_ +#define OSCSTRING_H_ -#include "pixeldmxhandler.h" +#include -#include "hal_gpio.h" +#include "osc.h" -#define GPIO_START_STOP GPIO_EXT_12 +/* + * OSC-string + * A sequence of non-null ASCII characters followed by a null, + * followed by 0-3 additional null characters to make the total number of bits a multiple of 32. + */ + +namespace osc { +inline static int string_validate(void *pData, unsigned nSize) { + unsigned nLength = 0; + char *pSrc = reinterpret_cast(pData); + + unsigned i = 0; -class PixelDmxStartStop final: public PixelDmxHandler { -public: - PixelDmxStartStop() { - FUNC_PREFIX(gpio_fsel(GPIO_START_STOP, GPIO_FSEL_OUTPUT)); - FUNC_PREFIX(gpio_clr(GPIO_START_STOP)); + for (i = 0; i < nSize; ++i) { + if (pSrc[i] == '\0') { + nLength = 4 * (i / 4 + 1); + break; + } } - ~PixelDmxStartStop() override { + if (0 == nLength) { + return -osc::validate::NOT_TERMINATED; } - void Start() override { - FUNC_PREFIX(gpio_set(GPIO_START_STOP)); + if (nLength > nSize) { + return -osc::validate::INVALID_SIZE; } - void Stop() override { - FUNC_PREFIX(gpio_clr(GPIO_START_STOP)); + for (; i < nLength; ++i) { + if (pSrc[i] != '\0') { + return -osc::validate::NONE_ZERO_IN_PADDING; + } } -}; -#endif /* WS28XXDMXSTARTSTOP_H_ */ + return static_cast(nLength); +} + +inline static unsigned string_size(const char *pString) { + return 4 * (strlen(pString) / 4 + 1); +} +} // namespace osc + +#endif /* OSCSTRING_H_ */ diff --git a/lib-osc/src/client/oscclient.cpp b/lib-osc/src/client/oscclient.cpp new file mode 100755 index 00000000..11e20383 --- /dev/null +++ b/lib-osc/src/client/oscclient.cpp @@ -0,0 +1,211 @@ +/** + * @file oscclient.cpp + * + */ +/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include +#include +#include + +#include "oscclient.h" +#include "oscsimplesend.h" +#include "oscsimplemessage.h" +#include "osc.h" + +#include "hardware.h" +#include "network.h" +#include "display.h" + +#include "debug.h" + +char OscClient::m_pCmds[oscclient::buffer::size::CMD]; +char OscClient::m_pLeds[oscclient::buffer::size::LED]; + +OscClient::OscClient() : + m_nPortOutgoing(oscclient::defaults::PORT_OUTGOING), + m_nPortIncoming(oscclient::defaults::PORT_INCOMING), + m_nPingDelayMillis(oscclient::defaults::PING_DELAY_SECONDS * 1000) +{ + DEBUG_ENTRY + + DEBUG_EXIT +} + +void OscClient::Start() { + DEBUG_ENTRY + + m_nHandle = Network::Get()->Begin(m_nPortIncoming); + assert(m_nHandle != -1); + + DEBUG_EXIT +} + +void OscClient::Stop() { + m_nHandle = Network::Get()->End(m_nPortIncoming); +} + +void OscClient::Run() { + if (!m_bPingDisable) { + m_nCurrenMillis = Hardware::Get()->Millis(); + + if ((m_nCurrenMillis - m_nPreviousMillis) >= m_nPingDelayMillis) { + OscSimpleSend MsgSend(m_nHandle, m_nServerIP, m_nPortOutgoing, "/ping", nullptr); + m_bPingSent = true; + m_nPreviousMillis = m_nCurrenMillis; + m_nPingTimeMillis = m_nCurrenMillis; + DEBUG_PUTS("Ping sent"); + } + } + + uint32_t nRemoteIp; + uint16_t nRemotePort; + + const auto nBytesReceived = Network::Get()->RecvFrom(m_nHandle, const_cast(reinterpret_cast(&m_pBuffer)), &nRemoteIp, &nRemotePort); + + if (__builtin_expect((nBytesReceived == 0), 1)) { + if (m_bPingSent && ((m_nCurrenMillis - m_nPingTimeMillis) >= 1000)) { + if (m_bPongReceived) { + m_bPongReceived = false; + Display::Get()->TextStatus("No /Pong"); + DEBUG_PUTS("No /Pong"); + } + } + return; + } + + if (nRemoteIp != m_nServerIP) { + DEBUG_PRINTF("Data not received from server " IPSTR , IP2STR(nRemoteIp)); + return; + } + + if ((m_pOscClientLed != nullptr) && (HandleLedMessage(nBytesReceived))) { + DEBUG_EXIT + return; + } + + + if (!m_bPingDisable) { + if (!osc::is_match(m_pBuffer, "/pong")) { + DEBUG_PUTS(m_pBuffer); + return; + } + + + if (!m_bPongReceived) { + Display::Get()->TextStatus("Ping-Pong"); + DEBUG_PUTS("Ping-Pong"); + } + + m_bPongReceived = true; + m_bPingSent = false; + } +} + +void OscClient::CopyCmds(const char *pCmds, uint32_t nCount, uint32_t nLength) { + assert(pCmds != nullptr); + + for (uint32_t i = 0; i < std::min(nCount, oscclient::max::CMD_COUNT); i++) { + char *dst = &m_pCmds[i * oscclient::max::CMD_PATH_LENGTH]; + strncpy(dst, &pCmds[i * nLength], oscclient::max::CMD_PATH_LENGTH - 1); + dst[oscclient::max::CMD_PATH_LENGTH - 1] = '\0'; + } +} + +void OscClient::CopyLeds(const char *pLeds, uint32_t nCount, uint32_t nLength) { + assert(pLeds != nullptr); + + for (uint32_t i = 0; i < std::min(nCount, oscclient::max::LED_COUNT); i++) { + char *dst = &m_pLeds[i * oscclient::max::LED_PATH_LENGTH]; + strncpy(dst, &pLeds[i * nLength], oscclient::max::LED_PATH_LENGTH - 1); + dst[oscclient::max::LED_PATH_LENGTH - 1] = '\0'; + } +} + +bool OscClient::HandleLedMessage(const uint16_t nBytesReceived) { + DEBUG_ENTRY + + uint32_t i; + + for (i = 0; i < oscclient::max::LED_COUNT; i++) { + const char *src = &m_pLeds[i * oscclient::max::LED_PATH_LENGTH]; + if (osc::is_match(m_pBuffer, src)) { + DEBUG_PUTS(""); + break; + } + } + + if (i == oscclient::max::LED_COUNT) { + DEBUG_EXIT + return false; + } + + OscSimpleMessage Msg(m_pBuffer, nBytesReceived); + + const int nArgc = Msg.GetArgc(); + + if (nArgc != 1) { + DEBUG_EXIT + return false; + } + + if (Msg.GetType(0) == osc::type::INT32) { + m_pOscClientLed->SetLed(static_cast(i), static_cast(Msg.GetInt(0)) != 0); + DEBUG_PRINTF("%d", Msg.GetInt(0)); + } else if (Msg.GetType(0) == osc::type::FLOAT) { + m_pOscClientLed->SetLed(static_cast(i), static_cast(Msg.GetFloat(0)) != 0); + DEBUG_PRINTF("%f", Msg.GetFloat(0)); + } else { + return false; + } + + DEBUG_EXIT + return true; +} + +void OscClient::Print() { + puts("OSC Client"); + printf(" Server ip-address :" IPSTR "\n", IP2STR(m_nServerIP)); + printf(" Outgoing Port : %d\n", m_nPortOutgoing); + printf(" Incoming Port : %d\n", m_nPortIncoming); + printf(" Disable /ping : %s\n", m_bPingDisable ? "Yes" : "No"); + + if (!m_bPingDisable) { + printf(" Ping delay : %ds\n", m_nPingDelayMillis / 1000); + } + + for (uint32_t i = 0; i < oscclient::max::CMD_COUNT; i++) { + const char *p = &m_pCmds[i * oscclient::max::CMD_PATH_LENGTH]; + if (*p != '\0') { + printf(" cmd%c : [%s]\n", i + '0', p); + } + } + + for (uint32_t i = 0; i < oscclient::max::LED_COUNT; i++) { + const char *p = &m_pLeds[i * oscclient::max::LED_PATH_LENGTH]; + if (*p != '\0') { + printf(" led%c : [%s]\n", i + '0', p); + } + } +} diff --git a/lib-configstore/src/storedisplayudf.cpp b/lib-osc/src/client/oscclientmsgconst.cpp old mode 100644 new mode 100755 similarity index 78% rename from lib-configstore/src/storedisplayudf.cpp rename to lib-osc/src/client/oscclientmsgconst.cpp index ac5e8f22..7d56b151 --- a/lib-configstore/src/storedisplayudf.cpp +++ b/lib-osc/src/client/oscclientmsgconst.cpp @@ -1,5 +1,5 @@ /** - * @file storedisplayudf.cpp + * @file oscclientconst.cpp * */ /* Copyright (C) 2019-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl @@ -23,20 +23,8 @@ * THE SOFTWARE. */ -#include +#include "oscclientmsgconst.h" -#include "storedisplayudf.h" - -#include "debug.h" - -StoreDisplayUdf *StoreDisplayUdf::s_pThis = nullptr; - -StoreDisplayUdf::StoreDisplayUdf() { - DEBUG_ENTRY - - assert(s_pThis == nullptr); - s_pThis = this; - - DEBUG_PRINTF("%p", reinterpret_cast(s_pThis)); - DEBUG_EXIT -} +const char OscClientMsgConst::PARAMS[] = "Setting Client parameters"; +const char OscClientMsgConst::START[] = "Starting the Client"; +const char OscClientMsgConst::STARTED[] = "Client started"; diff --git a/lib-osc/src/client/oscclientparams.cpp b/lib-osc/src/client/oscclientparams.cpp new file mode 100755 index 00000000..99b9a410 --- /dev/null +++ b/lib-osc/src/client/oscclientparams.cpp @@ -0,0 +1,292 @@ +/** + * @file oscclientparams.cpp + * + */ +/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#if !defined(__clang__) // Needed for compiling on MacOS +# pragma GCC push_options +# pragma GCC optimize ("Os") +#endif + +#include +#include +#ifndef NDEBUG +# include +#endif +#include + +#include "oscclientparams.h" +#include "oscclientparamsconst.h" +#include "oscparamsconst.h" + +#include "network.h" + +#include "readconfigfile.h" +#include "sscan.h" +#include "propertiesbuilder.h" + +#include "debug.h" + +OscClientParams::OscClientParams() { + DEBUG_ENTRY + + memset(&m_Params, 0, sizeof(struct oscclientparams::Params)); + m_Params.nOutgoingPort = oscclient::defaults::PORT_OUTGOING; + m_Params.nIncomingPort = oscclient::defaults::PORT_INCOMING; + m_Params.nPingDelay = oscclient::defaults::PING_DELAY_SECONDS; + + assert(sizeof(m_aCmd) > strlen(OscClientParamsConst::CMD)); + strncpy(m_aCmd, OscClientParamsConst::CMD, sizeof(m_aCmd)); + + assert(sizeof(m_aLed) > strlen(OscClientParamsConst::LED)); + strncpy(m_aLed, OscClientParamsConst::LED, sizeof(m_aLed)); + + DEBUG_EXIT +} + +void OscClientParams::Load() { + DEBUG_ENTRY + + m_Params.nSetList = 0; + +#if !defined(DISABLE_FS) + ReadConfigFile configfile(OscClientParams::staticCallbackFunction, this); + + if (configfile.Read(OscClientParamsConst::FILE_NAME)) { + OscClientParamsStore::Update(&m_Params); + } else +#endif + OscClientParamsStore::Copy(&m_Params); + +#ifndef NDEBUG + Dump(); +#endif + DEBUG_EXIT +} + +void OscClientParams::Load(const char *pBuffer, uint32_t nLength) { + DEBUG_ENTRY + + assert(pBuffer != nullptr); + assert(nLength != 0); + + m_Params.nSetList = 0; + + ReadConfigFile config(OscClientParams::staticCallbackFunction, this); + + config.Read(pBuffer, nLength); + + OscClientParamsStore::Update(&m_Params); + +#ifndef NDEBUG + Dump(); +#endif + DEBUG_EXIT +} + +void OscClientParams::callbackFunction(const char *pLine) { + assert(pLine != nullptr); + + uint32_t nValue32; + + if (Sscan::IpAddress(pLine, OscClientParamsConst::SERVER_IP, nValue32) == Sscan::OK) { + m_Params.nServerIp = nValue32; + m_Params.nSetList |= oscclientparams::Mask::SERVER_IP; + return; + } + + uint16_t nValue16; + + if (Sscan::Uint16(pLine, OscParamsConst::OUTGOING_PORT, nValue16) == Sscan::OK) { + if (nValue16 > 1023) { + m_Params.nOutgoingPort = nValue16; + m_Params.nSetList |= oscclientparams::Mask::OUTGOING_PORT; + } else { + m_Params.nSetList &= ~oscclientparams::Mask::OUTGOING_PORT; + } + return; + } + + if (Sscan::Uint16(pLine, OscParamsConst::INCOMING_PORT, nValue16) == Sscan::OK) { + if (nValue16 > 1023) { + m_Params.nIncomingPort = nValue16; + m_Params.nSetList |= oscclientparams::Mask::INCOMING_PORT; + } else { + m_Params.nSetList &= ~oscclientparams::Mask::INCOMING_PORT; + } + return; + } + + uint8_t nValue8; + + if (Sscan::Uint8(pLine, OscClientParamsConst::PING_DISABLE, nValue8) == Sscan::OK) { + m_Params.nPingDisable = (nValue8 != 0); + m_Params.nSetList |= oscclientparams::Mask::PING_DISABLE; + return; + } + + if (Sscan::Uint8(pLine, OscClientParamsConst::PING_DELAY, nValue8) == Sscan::OK) { + if ((nValue8 >= 2) && (nValue8 <= 60)) { + m_Params.nPingDelay = nValue8; + m_Params.nSetList |= oscclientparams::Mask::PING_DELAY; + } else { + m_Params.nSetList &= ~oscclientparams::Mask::PING_DELAY; + } + return; + } + + for (uint32_t i = 0; i < oscclientparams::ParamsMax::CMD_COUNT; i++) { + m_aCmd[strlen(OscClientParamsConst::CMD) - 1] = static_cast(i + '0'); + if (Sscan::Char(pLine, m_aCmd, reinterpret_cast(&m_Params.aCmd[i]), nValue32) == Sscan::OK) { + if (m_Params.aCmd[i][0] == '/') { + m_Params.nSetList |= oscclientparams::Mask::CMD; + } else { + m_Params.aCmd[i][0] = '\0'; + } + } + } + + for (uint32_t i = 0; i < oscclientparams::ParamsMax::LED_COUNT; i++) { + m_aLed[strlen(OscClientParamsConst::LED) - 1] = static_cast(i + '0'); + if (Sscan::Char(pLine, m_aLed, reinterpret_cast(&m_Params.aLed[i]), nValue32) == Sscan::OK) { + if (m_Params.aLed[i][0] == '/') { + m_Params.nSetList |= oscclientparams::Mask::LED; + } else { + m_Params.aLed[i][0] = '\0'; + } + } + } +} + +void OscClientParams::Builder(const struct oscclientparams::Params *pParams, char *pBuffer, uint32_t nLength, uint32_t& nSize) { + DEBUG_ENTRY + + assert(pBuffer != nullptr); + + if (pParams != nullptr) { + memcpy(&m_Params, pParams, sizeof(struct oscclientparams::Params)); + } else { + OscClientParamsStore::Copy(&m_Params); + } + + PropertiesBuilder builder(OscClientParamsConst::FILE_NAME, pBuffer, nLength); + + builder.AddIpAddress(OscClientParamsConst::SERVER_IP, m_Params.nServerIp, isMaskSet(oscclientparams::Mask::SERVER_IP)); + builder.Add(OscParamsConst::OUTGOING_PORT, m_Params.nOutgoingPort, isMaskSet(oscclientparams::Mask::OUTGOING_PORT)); + builder.Add(OscParamsConst::INCOMING_PORT, m_Params.nIncomingPort, isMaskSet(oscclientparams::Mask::INCOMING_PORT)); + builder.Add(OscClientParamsConst::PING_DISABLE, m_Params.nPingDisable, isMaskSet(oscclientparams::Mask::PING_DISABLE)); + builder.Add(OscClientParamsConst::PING_DELAY, m_Params.nPingDelay, isMaskSet(oscclientparams::Mask::PING_DELAY)); + + for (uint32_t i = 0; i < oscclientparams::ParamsMax::CMD_COUNT; i++) { + m_aCmd[strlen(OscClientParamsConst::CMD) - 1] = static_cast(i + '0'); + const char *cmd = reinterpret_cast(&m_Params.aCmd[i]); + builder.Add(m_aCmd, cmd, *cmd == '/'); + } + + for (uint32_t i = 0; i < oscclientparams::ParamsMax::LED_COUNT; i++) { + m_aLed[strlen(OscClientParamsConst::LED) - 1] = static_cast(i + '0'); + const char *led = reinterpret_cast(&m_Params.aLed[i]); + builder.Add(m_aLed, led, *led == '/'); + } + + nSize = builder.GetSize(); + + DEBUG_EXIT +} + +void OscClientParams::Set(OscClient* pOscClient) { + assert(pOscClient != nullptr); + + if (isMaskSet(oscclientparams::Mask::SERVER_IP)) { + pOscClient->SetServerIP(m_Params.nServerIp); + } + + if (isMaskSet(oscclientparams::Mask::OUTGOING_PORT)) { + pOscClient->SetPortOutgoing(m_Params.nOutgoingPort); + } + + if (isMaskSet(oscclientparams::Mask::INCOMING_PORT)) { + pOscClient->SetPortIncoming(m_Params.nIncomingPort); + } + + if (isMaskSet(oscclientparams::Mask::PING_DISABLE)) { + pOscClient->SetPingDisable(m_Params.nPingDisable); + } + + if (isMaskSet(oscclientparams::Mask::PING_DELAY)) { + pOscClient->SetPingDelay(m_Params.nPingDelay); + } + + if (isMaskSet(oscclientparams::Mask::CMD)) { + pOscClient->CopyCmds(reinterpret_cast(&m_Params.aCmd), oscclientparams::ParamsMax::CMD_COUNT, oscclientparams::ParamsMax::CMD_PATH_LENGTH); + } + + if (isMaskSet(oscclientparams::Mask::LED)) { + pOscClient->CopyLeds(reinterpret_cast(&m_Params.aLed), oscclientparams::ParamsMax::LED_COUNT, oscclientparams::ParamsMax::LED_PATH_LENGTH); + } +} + +void OscClientParams::staticCallbackFunction(void* p, const char* s) { + assert(p != nullptr); + assert(s != nullptr); + + (static_cast(p))->callbackFunction(s); +} + +void OscClientParams::Dump() { + printf("%s::%s \'%s\':\n", __FILE__, __FUNCTION__, OscClientParamsConst::FILE_NAME); + + if (isMaskSet(oscclientparams::Mask::SERVER_IP)) { + printf(" %s=" IPSTR "\n", OscClientParamsConst::SERVER_IP, IP2STR(m_Params.nServerIp)); + } + + if (isMaskSet(oscclientparams::Mask::OUTGOING_PORT)) { + printf(" %s=%d\n", OscParamsConst::OUTGOING_PORT, m_Params.nOutgoingPort); + } + + if (isMaskSet(oscclientparams::Mask::INCOMING_PORT)) { + printf(" %s=%d\n", OscParamsConst::INCOMING_PORT, m_Params.nIncomingPort); + } + + if (isMaskSet(oscclientparams::Mask::PING_DISABLE)) { + printf(" %s=%d [%s]\n", OscClientParamsConst::PING_DISABLE, m_Params.nPingDisable, m_Params.nPingDisable == 0 ? "No" : "Yes"); + } + + if (isMaskSet(oscclientparams::Mask::PING_DELAY)) { + printf(" %s=%ds\n", OscClientParamsConst::PING_DELAY, m_Params.nPingDelay); + } + + if (isMaskSet(oscclientparams::Mask::CMD)) { + for (uint32_t i = 0; i < oscclientparams::ParamsMax::CMD_COUNT; i++) { + m_aCmd[strlen(OscClientParamsConst::CMD) - 1] = static_cast(i + '0'); + printf(" %s=[%s]\n", m_aCmd, reinterpret_cast(&m_Params.aCmd[i])); + } + } + + if (isMaskSet(oscclientparams::Mask::LED)) { + for (uint32_t i = 0; i < oscclientparams::ParamsMax::LED_COUNT; i++) { + m_aLed[strlen(OscClientParamsConst::LED) - 1] = static_cast(i + '0'); + printf(" %s=[%s]\n", m_aLed, reinterpret_cast(&m_Params.aLed[i])); + } + } +} diff --git a/lib-configstore/src/storeremoteconfig.cpp b/lib-osc/src/client/oscclientparamsconst.cpp old mode 100644 new mode 100755 similarity index 73% rename from lib-configstore/src/storeremoteconfig.cpp rename to lib-osc/src/client/oscclientparamsconst.cpp index 8c36decb..2c514027 --- a/lib-configstore/src/storeremoteconfig.cpp +++ b/lib-osc/src/client/oscclientparamsconst.cpp @@ -1,5 +1,5 @@ /** - * @file storeremoteconfig.cpp + * @file oscclientparamsconst.cpp * */ /* Copyright (C) 2019-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl @@ -23,20 +23,14 @@ * THE SOFTWARE. */ -#include +#include "oscclientparamsconst.h" -#include "storeremoteconfig.h" +const char OscClientParamsConst::FILE_NAME[] = "oscclnt.txt"; -#include "debug.h" +const char OscClientParamsConst::SERVER_IP[] = "server_ip"; -StoreRemoteConfig *StoreRemoteConfig::s_pThis = nullptr; +const char OscClientParamsConst::PING_DISABLE[] = "ping_disable"; +const char OscClientParamsConst::PING_DELAY[] = "ping_delay"; -StoreRemoteConfig::StoreRemoteConfig() { - DEBUG_ENTRY - - assert(s_pThis == nullptr); - s_pThis = this; - - DEBUG_PRINTF("%p", reinterpret_cast(s_pThis)); - DEBUG_EXIT -} +const char OscClientParamsConst::CMD[] = "cmd?"; +const char OscClientParamsConst::LED[] = "led?"; diff --git a/lib-configstore/src/storedmxsend.cpp b/lib-osc/src/client/oscclientsend.cpp old mode 100644 new mode 100755 similarity index 67% rename from lib-configstore/src/storedmxsend.cpp rename to lib-osc/src/client/oscclientsend.cpp index 66ff9fdc..33c4e626 --- a/lib-configstore/src/storedmxsend.cpp +++ b/lib-osc/src/client/oscclientsend.cpp @@ -1,8 +1,8 @@ /** - * @file storedmxsend.cpp + * @file oscclient.cpp * */ -/* Copyright (C) 2018-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,20 +23,35 @@ * THE SOFTWARE. */ +#include +#include #include -#include "storedmxsend.h" +#include "oscclient.h" +#include "oscsimplesend.h" +#include "osc.h" #include "debug.h" -StoreDmxSend *StoreDmxSend::s_pThis = nullptr; +void OscClient::Send(const char *pPath) { + DEBUG_ENTRY + + assert(pPath != nullptr); -StoreDmxSend::StoreDmxSend() { + if (*pPath != 0) { + OscSimpleSend MsgSend(m_nHandle, m_nServerIP, m_nPortOutgoing, pPath, nullptr); + } + + DEBUG_EXIT +} + +void OscClient::SendCmd(uint32_t nCmd) { DEBUG_ENTRY + DEBUG_PRINTF("nCmd=%d", nCmd); + + assert(nCmd < oscclient::max::CMD_COUNT); - assert(s_pThis == nullptr); - s_pThis = this; + Send(&m_pCmds[nCmd * oscclient::max::CMD_PATH_LENGTH]); - DEBUG_PRINTF("%p", reinterpret_cast(s_pThis)); DEBUG_EXIT } diff --git a/lib-osc/src/oscparamsconst.cpp b/lib-osc/src/oscparamsconst.cpp new file mode 100644 index 00000000..cb5db092 --- /dev/null +++ b/lib-osc/src/oscparamsconst.cpp @@ -0,0 +1,29 @@ +/** + * @file oscconst.cpp + * + */ +/* Copyright (C) 2020 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "oscparamsconst.h" + +const char OscParamsConst::INCOMING_PORT[] = "incoming_port"; +const char OscParamsConst::OUTGOING_PORT[] = "outgoing_port"; diff --git a/lib-osc/src/oscsimplemessage.cpp b/lib-osc/src/oscsimplemessage.cpp new file mode 100644 index 00000000..49737001 --- /dev/null +++ b/lib-osc/src/oscsimplemessage.cpp @@ -0,0 +1,106 @@ +/** + * @file oscsimplemessage.cpp + * + */ +/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "oscsimplemessage.h" +#include "osc.h" + +OscSimpleMessage::OscSimpleMessage(void *pData, unsigned nLength) : m_pOscMessage(reinterpret_cast(pData)), m_nLength(nLength) { + auto nResult = osc::string_validate(m_pOscMessage, m_nLength); + + if (nResult < 0) { + return; + } + + m_pArg = &m_pOscMessage[nResult]; + auto nDataOffset = static_cast(nResult); + + nResult = osc::string_validate(m_pArg, m_nLength - static_cast(nResult)); + + if ((nResult < 0) || (m_pArg[0] != ',')) { + return; + } + + // Support for 1 osc-string or blob only + if (((m_pArg[1] == 's') || (m_pArg[1] == 'b')) && (m_pArg[2] != '\0')) { + return; + } + + m_pArg++; // Skip ',' + m_nArgc = strlen(reinterpret_cast(m_pArg)); + + nDataOffset += static_cast(nResult); + + m_pOscMessageData = &m_pOscMessage[nDataOffset]; + m_nOscMessageDataLength = m_nLength - nDataOffset; + + m_bIsValid = true; +} + +float OscSimpleMessage::GetFloat(unsigned argc) { + union pcast32 { + int32_t i; + float f; + } osc_pcast32; + + if ((m_nOscMessageDataLength >= 4 * (1 + argc)) && (m_pArg[argc] == osc::type::FLOAT)) { + osc_pcast32.i = static_cast(__builtin_bswap32(*reinterpret_cast((4 * argc) + m_pOscMessageData))); + return osc_pcast32.f; + } + + return 0; +} + +int OscSimpleMessage::GetInt(unsigned argc) { + if ((m_nOscMessageDataLength >= 4 * (1 + argc)) && (m_pArg[argc] == osc::type::INT32)) { + return static_cast(__builtin_bswap32(*reinterpret_cast((4 * argc) + m_pOscMessageData))); + } + + return 0; +} + +char* OscSimpleMessage::GetString(__attribute__ ((unused)) unsigned argc) { + if ((m_pArg[0] == osc::type::STRING) && (m_nOscMessageDataLength == osc::string_size(reinterpret_cast(m_pOscMessageData)))) { + return reinterpret_cast(m_pOscMessageData); + } + + return nullptr; +} + +OSCBlob OscSimpleMessage::GetBlob(__attribute__ ((unused)) unsigned argc) { + if (m_pArg[0] == osc::type::BLOB) { + + const uint32_t nSize = __builtin_bswap32(*reinterpret_cast(m_pOscMessageData)); + const uint8_t *pData = reinterpret_cast(m_pOscMessageData) + 4; + + if ((nSize + 4) <= m_nOscMessageDataLength) { + return OSCBlob(pData, nSize); + } + } + + return OSCBlob(nullptr, 0); +} diff --git a/lib-osc/src/oscsimplesend.cpp b/lib-osc/src/oscsimplesend.cpp new file mode 100644 index 00000000..1b20a4e3 --- /dev/null +++ b/lib-osc/src/oscsimplesend.cpp @@ -0,0 +1,126 @@ +/** + * @file oscsimplesend.cpp + * + */ +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "oscsimplesend.h" +#include "osc.h" +#include "oscstring.h" + +#include "network.h" + +#include "debug.h" + +char OscSimpleSend::s_Message[osc::simple::send::BUFFER_SIZE]; + +// Support for path only +OscSimpleSend::OscSimpleSend(int32_t nHandle, uint32_t nIpAddress , uint16_t nPort, const char *pPath, const char *pType) { + if (pType == nullptr) { + const auto nPathLength = osc::string_size(pPath); + const auto nMessageLength = nPathLength + 4U; + + assert(nMessageLength < sizeof(s_Message)); + + UpdateMessage(pPath, nPathLength, 0); + Send(nMessageLength, nHandle, nIpAddress, nPort); + } +} + +// Support for 's' +OscSimpleSend::OscSimpleSend(int32_t nHandle, uint32_t nIpAddress , uint16_t nPort, const char *pPath, const char *pType, const char *pString) { + if ((pType != nullptr) && (*pType == 's')) { + const auto nPathLength = osc::string_size(pPath); + const auto nMessageLength = nPathLength + 4U + osc::string_size(pString); + + assert(nMessageLength < sizeof(s_Message)); + + UpdateMessage(pPath, nPathLength, 's'); + + memset(s_Message + nMessageLength - 4, 0, 4); + + assert((nPathLength + 4) < sizeof(s_Message)); + strncpy(&s_Message[nPathLength + 4], pString, sizeof(s_Message) - (nPathLength + 4)); + + Send(nMessageLength, nHandle, nIpAddress, nPort); + } +} + +// Support for type 'i' +OscSimpleSend::OscSimpleSend(int32_t nHandle, uint32_t nIpAddress , uint16_t nPort, const char *pPath, const char *pType, int nValue) { + if ((pType != nullptr) && (*pType == 'i')) { + const auto nPathLength = osc::string_size(pPath); + const auto nMessageLength = nPathLength + 4U + 4U; + + assert(nMessageLength < sizeof(s_Message)); + + UpdateMessage(pPath, nPathLength, 'i'); + + *reinterpret_cast(&s_Message[nMessageLength - 4]) = static_cast(__builtin_bswap32(static_cast(nValue))); + + Send(nMessageLength, nHandle, nIpAddress, nPort); + } +} + +// Support for type 'f' +OscSimpleSend::OscSimpleSend(int32_t nHandle, uint32_t nIpAddress , uint16_t nPort, const char *pPath, const char *pType, float fValue) { + if ((pType != nullptr) && (*pType == 'f')) { + const auto nPathLength = osc::string_size(pPath); + const auto nMessageLength = nPathLength + 4U + 4U; + + assert(nMessageLength < sizeof(s_Message)); + + UpdateMessage(pPath, nPathLength, 'f'); + + union pcast32 { + uint32_t u; + float f; + } osc_pcast32; + + osc_pcast32.f = fValue; + + *reinterpret_cast(&s_Message[nMessageLength - 4]) = static_cast(__builtin_bswap32(osc_pcast32.u)); + + Send(nMessageLength, nHandle, nIpAddress, nPort); + } +} + +void OscSimpleSend::UpdateMessage(const char *pPath, uint32_t nPathLength, char cType) { + memset(s_Message + nPathLength - 4, 0, 4); + strncpy(s_Message, pPath, sizeof(s_Message)); + + assert(nPathLength < sizeof(s_Message)); + + s_Message[nPathLength++] = ','; + s_Message[nPathLength++] = cType; + s_Message[nPathLength++] = '\0'; + s_Message[nPathLength++] = '\0'; +} + +void OscSimpleSend::Send(uint32_t nMessageLength, int32_t nHandle, uint32_t nIpAddress, uint16_t nPort) { + debug_dump(s_Message, nMessageLength); + + Network::Get()->SendTo(nHandle, s_Message, nMessageLength, nIpAddress, nPort); +} diff --git a/lib-osc/src/pattern_match.c b/lib-osc/src/pattern_match.c new file mode 100644 index 00000000..2cfe925e --- /dev/null +++ b/lib-osc/src/pattern_match.c @@ -0,0 +1,263 @@ +/* + * Copyright (C) 2014 Steve Harris et al. (see AUTHORS) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as + * published by the Free Software Foundation; either version 2.1 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * $Id$ + */ + +/* This code was originally forked from: */ + +/* Open SoundControl kit in C++ */ +/* Copyright (C) 2002-2004 libOSC++ contributors. See AUTHORS */ +/* */ +/* This library is free software; you can redistribute it and/or */ +/* modify it under the terms of the GNU Lesser General Public */ +/* License as published by the Free Software Foundation; either */ +/* version 2.1 of the License, or (at your option) any later version. */ +/* */ +/* This library is distributed in the hope that it will be useful, */ +/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */ +/* Lesser General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public */ +/* License along with this library; if not, write to the Free Software */ +/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +/* */ +/* For questions regarding this program contact */ +/* Daniel Holth or visit */ +/* http://wiretap.stetson.edu/ */ + +/* In the sprit of the public domain, my modifications to this file are also */ +/* dedicated to the public domain. Daniel Holth, Oct. 2004 */ + +/* ChangeLog: + * + * 2004-10-29 Import, convert to C++, begin OSC syntax changes. -dwh + * OSC syntax changes are now working, needs more testing. + * + */ + +// Original header and syntax: + +/* + * robust glob pattern matcher + * ozan s. yigit/dec 1994 + * public domain + * + * glob patterns: + * * matches zero or more characters + * ? matches any single character + * [set] matches any character in the set + * [^set] matches any character NOT in the set + * where a set is a group of characters or ranges. a range + * is written as two characters seperated with a hyphen: a-z denotes + * all characters between a to z inclusive. + * [-set] set matches a literal hypen and any character in the set + * []set] matches a literal close bracket and any character in the set + * + * char matches itself except where char is '*' or '?' or '[' + * \char matches char, including any pattern character + * + * examples: + * a*c ac abc abbc ... + * a?c acc abc aXc ... + * a[a-z]c aac abc acc ... + * a[-a-z]c a-c aac abc ... + * + * $Log$ + * Revision 1.1 2004/11/19 23:00:57 theno23 + * Added lo_send_timestamped + * + * Revision 1.3 1995/09/14 23:24:23 oz + * removed boring test/main code. + * + * Revision 1.2 94/12/11 10:38:15 oz + * cset code fixed. it is now robust and interprets all + * variations of cset [i think] correctly, including [z-a] etc. + * + * Revision 1.1 94/12/08 12:45:23 oz + * Initial revision + */ + +//#include "lo/lo.h" + +#ifndef NEGATE +#define NEGATE '!' +#endif + +#ifndef true +#define true 1 +#endif +#ifndef false +#define false 0 +#endif + +int lo_pattern_match(const char *str, const char *p) +{ + int negate; + int match; + char c; + + while (*p) { + if (!*str && *p != '*') + return false; + + switch (c = *p++) { + + case '*': + while (*p == '*' && *p != '/') + p++; + + if (!*p) + return true; + +// if (*p != '?' && *p != '[' && *p != '\\') + if (*p != '?' && *p != '[' && *p != '{') + while (*str && *p != *str) + str++; + + while (*str) { + if (lo_pattern_match(str, p)) + return true; + str++; + } + return false; + + case '?': + if (*str) + break; + return false; + /* + * set specification is inclusive, that is [a-z] is a, z and + * everything in between. this means [z-a] may be interpreted + * as a set that contains z, a and nothing in between. + */ + case '[': + if (*p != NEGATE) + negate = false; + else { + negate = true; + p++; + } + + match = false; + + while (!match && (c = *p++)) { + if (!*p) + return false; + if (*p == '-') { /* c-c */ + if (!*++p) + return false; + if (*p != ']') { + if (*str == c || *str == *p || + (*str > c && *str < *p)) + match = true; + } else { /* c-] */ + if (*str >= c) + match = true; + break; + } + } else { /* cc or c] */ + if (c == *str) + match = true; + if (*p != ']') { + if (*p == *str) + match = true; + } else + break; + } + } + + if (negate == match) + return false; + /* + * if there is a match, skip past the cset and continue on + */ + while (*p && *p != ']') + p++; + if (!*p++) /* oops! */ + return false; + break; + + /* + * {astring,bstring,cstring} + */ + case '{': + { + // *p is now first character in the {brace list} + const char *place = str; // to backtrack + const char *remainder = p; // to forwardtrack + + // find the end of the brace list + while (*remainder && *remainder != '}') + remainder++; + if (!*remainder++) /* oops! */ + return false; + + c = *p++; + + while (c) { + if (c == ',') { + if (lo_pattern_match(str, remainder)) { + return true; + } else { + // backtrack on test string + str = place; + // continue testing, + // skip comma + if (!*p++) // oops + return false; + } + } else if (c == '}') { + // continue normal pattern matching + if (!*p && !*str) + return true; + str--; // str is incremented again below + break; + } else if (c == *str) { + str++; + if (!*str && *remainder) + return false; + } else { // skip to next comma + str = place; + while (*p != ',' && *p != '}' && *p) + p++; + if (*p == ',') + p++; + else if (*p == '}') { + return false; + } + } + c = *p++; + } + } + + break; + + /* Not part of OSC pattern matching + case '\\': + if (*p) + c = *p++; + */ + + default: + if (c != *str) + return false; + break; + + } + str++; + } + + return !*str; +} diff --git a/lib-osc/src/server/oscserver.cpp b/lib-osc/src/server/oscserver.cpp new file mode 100755 index 00000000..e52041d4 --- /dev/null +++ b/lib-osc/src/server/oscserver.cpp @@ -0,0 +1,400 @@ +/** + * @file oscserver.cpp + * + */ +/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include +#include + +#include "oscserver.h" +#include "osc.h" +#include "oscsimplemessage.h" +#include "oscsimplesend.h" +#include "oscblob.h" + +#include "lightset.h" +#include "network.h" + +#include "hardware.h" + +#include "debug.h" + +#define OSCSERVER_DEFAULT_PATH_PRIMARY "/dmx1" +#define OSCSERVER_DEFAULT_PATH_SECONDARY OSCSERVER_DEFAULT_PATH_PRIMARY"/*" +#define OSCSERVER_DEFAULT_PATH_INFO "/2" +#define OSCSERVER_DEFAULT_PATH_BLACKOUT OSCSERVER_DEFAULT_PATH_PRIMARY "/blackout" + +#define SOFTWARE_VERSION "1.0" + +char OscServer::s_aPath[osc::server::Max::PATH_LENGTH]; +char OscServer::s_aPathSecond[osc::server::Max::PATH_LENGTH]; +char OscServer::s_aPathInfo[osc::server::Max::PATH_LENGTH]; +char OscServer::s_aPathBlackOut[osc::server::Max::PATH_LENGTH]; + +char *OscServer::s_pUdpBuffer; +uint8_t OscServer::s_pData[lightset::dmx::UNIVERSE_SIZE]; +uint8_t OscServer::s_pOsc[lightset::dmx::UNIVERSE_SIZE]; + +OscServer *OscServer::s_pThis; + +OscServer::OscServer() { + DEBUG_ENTRY + assert(s_pThis == nullptr); + s_pThis = this; + + memset(s_aPath, 0, sizeof(s_aPath)); + strcpy(s_aPath, OSCSERVER_DEFAULT_PATH_PRIMARY); + + memset(s_aPathSecond, 0, sizeof(s_aPathSecond)); + strcpy(s_aPathSecond, OSCSERVER_DEFAULT_PATH_SECONDARY); + + memset(s_aPathInfo, 0, sizeof(s_aPathInfo)); + strcpy(s_aPathInfo, OSCSERVER_DEFAULT_PATH_INFO); + + memset(s_aPathBlackOut, 0, sizeof(s_aPathBlackOut)); + strcpy(s_aPathBlackOut, OSCSERVER_DEFAULT_PATH_BLACKOUT); + + snprintf(m_Os, sizeof(m_Os) - 1, "[V%s] %s", SOFTWARE_VERSION, __DATE__); + + uint8_t nHwTextLength; + m_pModel = Hardware::Get()->GetBoardName(nHwTextLength); + m_pSoC = Hardware::Get()->GetSocName(nHwTextLength); + + if (m_pSoC[0] == '\0') { + m_pSoC = Hardware::Get()->GetCpuName(nHwTextLength); + } + + DEBUG_EXIT +} + +OscServer::~OscServer() { + DEBUG_ENTRY + + DEBUG_EXIT +} + +void OscServer::Start() { + DEBUG_ENTRY + + m_nHandle = Network::Get()->Begin(m_nPortIncoming); + assert(m_nHandle != -1); + + OscSimpleSend MsgSend(m_nHandle, Network::Get()->GetIp() | ~(Network::Get()->GetNetmask()), m_nPortIncoming, "/ping", nullptr); + + Hardware::Get()->SetMode(hardware::ledblink::Mode::NORMAL); + + DEBUG_EXIT +} + +void OscServer::Stop() { + if (m_pLightSet != nullptr) { + m_pLightSet->Stop(0); + } +} + +void OscServer::SetPath(const char* pPath) { + if (*pPath == '/') { + auto nLength = sizeof(s_aPath) - 3; // We need space for '\0' and "/*" + strncpy(s_aPath, pPath, nLength); + s_aPath[sizeof(s_aPath) - 1] = '\0'; + + nLength = strlen(s_aPath); + + if (s_aPath[nLength - 1] == '/') { + s_aPath[nLength - 1] = '\0'; + } + + strncpy(s_aPathSecond, s_aPath, sizeof(s_aPathSecond) - 3); + + nLength = strlen(s_aPathSecond); + assert(nLength < (sizeof(s_aPathSecond) - 3)); + + s_aPathSecond[nLength++] = '/'; + s_aPathSecond[nLength++] = '*'; + s_aPathSecond[nLength] = '\0'; + } + + DEBUG_PUTS(s_aPath); + DEBUG_PUTS(s_aPathSecond); +} + +void OscServer::SetPathInfo(const char* pPathInfo) { + if (*pPathInfo == '/') { + strncpy(s_aPathInfo, pPathInfo, sizeof(s_aPathInfo)); + s_aPathInfo[sizeof(s_aPathInfo) - 1] = '\0'; + + auto nLength = strlen(s_aPathInfo); + + if (s_aPathInfo[nLength - 1] == '/') { + s_aPathInfo[nLength - 1] = '\0'; + } + } + + DEBUG_PUTS(s_aPathInfo); +} + +void OscServer::SetPathBlackOut(const char* pPathBlackOut) { + if (*pPathBlackOut == '/') { + strncpy(s_aPathBlackOut, pPathBlackOut, sizeof(s_aPathInfo)); + s_aPathBlackOut[sizeof(s_aPathInfo) - 1] = '\0'; + + auto nLength = strlen(s_aPathBlackOut); + + if (s_aPathBlackOut[nLength - 1] == '/') { + s_aPathBlackOut[nLength - 1] = '\0'; + } + } + + DEBUG_PUTS(s_aPathBlackOut); +} + +int OscServer::GetChannel(const char* p) { + assert(p != nullptr); + + auto *s = const_cast(p) + strlen(s_aPath) + 1; + int nChannel = 0; + int i; + + for (i = 0; (i < 3) && (*s != '\0'); i++) { + int c = *s; + + if ((c < '0') || (c > '9')) { + return -1; + } + + nChannel = nChannel * 10 + c - '0'; + s++; + } + + if (nChannel > static_cast(lightset::dmx::UNIVERSE_SIZE)) { + return -1; + } + + return nChannel; +} + +bool OscServer::IsDmxDataChanged(const uint8_t* pData, uint16_t nStartChannel, uint32_t nLength) { + assert(pData != nullptr); + assert(nLength <= lightset::dmx::UNIVERSE_SIZE); + + auto isChanged = false; + const auto *src = pData; + auto *dst = &s_pData[--nStartChannel]; + const auto nEnd = nStartChannel + nLength; + + assert(nEnd <= lightset::dmx::UNIVERSE_SIZE); + + for (uint32_t i = nStartChannel; i < nEnd; i++) { + if (*dst != *src) { + *dst = *src; + isChanged = true; + } + dst++; + src++; + } + + return isChanged; +} + +void OscServer::Run() { + uint32_t nRemoteIp; + uint16_t nRemotePort; + + const auto nBytesReceived = Network::Get()->RecvFrom(m_nHandle, const_cast(reinterpret_cast(&s_pUdpBuffer)), &nRemoteIp, &nRemotePort); + + if (__builtin_expect((nBytesReceived == 0), 1)) { + return; + } + + auto bIsDmxDataChanged = false; + + OscSimpleMessage Msg(s_pUdpBuffer, nBytesReceived); + + debug_dump(s_pUdpBuffer, nBytesReceived); + + DEBUG_PRINTF("[%d] path : %s", nBytesReceived, osc::get_path(s_pUdpBuffer, nBytesReceived)); + + if (osc::is_match(s_pUdpBuffer, s_aPath)) { + const auto nArgc = Msg.GetArgc(); + + if ((nArgc == 1) && (Msg.GetType(0) == osc::type::BLOB)) { + DEBUG_PUTS("Blob received"); + + OSCBlob blob = Msg.GetBlob(0); + const auto size = static_cast(blob.GetDataSize()); + + if (size <= lightset::dmx::UNIVERSE_SIZE) { + const auto *ptr = blob.GetDataPtr(); + + bIsDmxDataChanged = IsDmxDataChanged(ptr, 1, size); + + if (bIsDmxDataChanged || m_bEnableNoChangeUpdate) { + if ((!m_bPartialTransmission) || (size == lightset::dmx::UNIVERSE_SIZE)) { + m_pLightSet->SetData(0, s_pData, lightset::dmx::UNIVERSE_SIZE); + } else { + m_nLastChannel = static_cast(size > m_nLastChannel ? size : m_nLastChannel); + m_pLightSet->SetData(0, s_pData, m_nLastChannel); + } + + if (!m_bIsRunning) { + m_bIsRunning = true; + m_pLightSet->Start(0); + } + } + } else { + DEBUG_PUTS("Too many channels"); + return; + } + } else if ((nArgc == 2) && (Msg.GetType(0) == osc::type::INT32)) { + auto nChannel = static_cast(1 + Msg.GetInt(0)); + + if ((nChannel < 1) || (nChannel > lightset::dmx::UNIVERSE_SIZE)) { + DEBUG_PRINTF("Invalid channel [%d]", nChannel); + return; + } + + uint8_t nData; + + if (Msg.GetType(1) == osc::type::INT32) { + DEBUG_PUTS("ii received"); + nData = static_cast(Msg.GetInt(1)); + } else if (Msg.GetType(1) == osc::type::FLOAT) { + DEBUG_PUTS("if received"); + nData = static_cast(Msg.GetFloat(1) * lightset::dmx::MAX_VALUE); + } else { + return; + } + + DEBUG_PRINTF("Channel = %d, Data = %.2x", nChannel, nData); + + bIsDmxDataChanged = IsDmxDataChanged(&nData, nChannel, 1); + + if (bIsDmxDataChanged || m_bEnableNoChangeUpdate) { + if (!m_bPartialTransmission) { + m_pLightSet->SetData(0, s_pData, lightset::dmx::UNIVERSE_SIZE); + } else { + m_nLastChannel = nChannel > m_nLastChannel ? nChannel : m_nLastChannel; + m_pLightSet->SetData(0, s_pData, m_nLastChannel); + } + + if (!m_bIsRunning) { + m_bIsRunning = true; + m_pLightSet->Start(0); + } + } + } + + return; + } + + if ((m_pOscServerHandler != nullptr) && (osc::is_match(s_pUdpBuffer, s_aPathBlackOut))) { + OscSimpleMessage Msg(s_pUdpBuffer, nBytesReceived); + + if (Msg.GetType(0) != osc::type::FLOAT) { + DEBUG_PUTS("No float"); + return; + } + + if (Msg.GetFloat(0) != 0) { + m_pOscServerHandler->Blackout(); + DEBUG_PUTS("Blackout"); + } else { + m_pOscServerHandler->Update(); + DEBUG_PUTS("Update"); + } + + return; + } + + if (osc::is_match(s_pUdpBuffer, s_aPathSecond)) { + const auto nArgc = Msg.GetArgc(); + + if (nArgc == 1) { // /path/N 'i' or 'f' + const auto nChannel = static_cast(GetChannel(s_pUdpBuffer)); + + if (nChannel >= 1 && nChannel <= lightset::dmx::UNIVERSE_SIZE) { + uint8_t nData; + + if (Msg.GetType(0) == osc::type::INT32) { + DEBUG_PUTS("i received"); + nData = static_cast(Msg.GetInt(0)); + } else if (Msg.GetType(0) == osc::type::FLOAT) { + DEBUG_PRINTF("f received %f", Msg.GetFloat(0)); + nData = static_cast(Msg.GetFloat(0) * lightset::dmx::MAX_VALUE); + } else { + return; + } + + DEBUG_PRINTF("Channel = %d, Data = %.2x", nChannel, nData); + + bIsDmxDataChanged = IsDmxDataChanged(&nData, nChannel, 1); + + if (bIsDmxDataChanged || m_bEnableNoChangeUpdate) { + if (!m_bPartialTransmission) { + m_pLightSet->SetData(0, s_pData, lightset::dmx::UNIVERSE_SIZE); + } else { + m_nLastChannel = nChannel > m_nLastChannel ? nChannel : m_nLastChannel; + m_pLightSet->SetData(0, s_pData, m_nLastChannel); + } + + if (!m_bIsRunning) { + m_bIsRunning = true; + m_pLightSet->Start(0); + } + } + } + } + + return; + } + + if (osc::is_match(s_pUdpBuffer, "/ping")) { + DEBUG_PUTS("ping received"); + OscSimpleSend MsgSend(m_nHandle, nRemoteIp, m_nPortOutgoing, "/pong", nullptr); + + return; + } + + if (osc::is_match(s_pUdpBuffer, s_aPathInfo)) { + OscSimpleSend MsgSendInfo(m_nHandle, nRemoteIp, m_nPortOutgoing, "/info/os", "s", m_Os); + OscSimpleSend MsgSendModel(m_nHandle, nRemoteIp, m_nPortOutgoing, "/info/model", "s", m_pModel); + OscSimpleSend MsgSendSoc(m_nHandle, nRemoteIp, m_nPortOutgoing, "/info/soc", "s", m_pSoC); + + if (m_pOscServerHandler != nullptr) { + m_pOscServerHandler->Info(m_nHandle, nRemoteIp, m_nPortOutgoing); + } + + return; + } +} + +void OscServer::Print() { + puts("OSC Server"); + printf(" Incoming Port : %d\n", m_nPortIncoming); + printf(" Outgoing Port : %d\n", m_nPortOutgoing); + printf(" DMX Path : [%s][%s]\n", s_aPath, s_aPathSecond); + printf(" Blackout Path : [%s]\n", s_aPathBlackOut); + printf(" Partial Transmission : %s\n", m_bPartialTransmission ? "Yes" : "No"); +} diff --git a/lib-lightset/src/lightsetgetslotinfo.cpp b/lib-osc/src/server/oscserverconst.cpp old mode 100644 new mode 100755 similarity index 76% rename from lib-lightset/src/lightsetgetslotinfo.cpp rename to lib-osc/src/server/oscserverconst.cpp index 392fa6cc..0e1e17ac --- a/lib-lightset/src/lightsetgetslotinfo.cpp +++ b/lib-osc/src/server/oscserverconst.cpp @@ -1,8 +1,8 @@ /** - * @file lightset.cpp + * @file oscserverconst.cpp * */ -/* Copyright (C) 2016-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,12 +23,8 @@ * THE SOFTWARE. */ -#include "lightset.h" +#include "oscserverconst.h" -using namespace lightset; - -bool LightSet::GetSlotInfo(__attribute__((unused)) uint16_t nSlot, SlotInfo &tSlotInfo) { - tSlotInfo.nType = 0x00; // ST_PRIMARY - tSlotInfo.nCategory = 0x0001; // SD_INTENSITY - return true; -} +const char OSCServerConst::MSG_BRIDGE_PARAMS[] = "Setting Bridge parameters"; +const char OSCServerConst::MSG_BRIDGE_START[] = "Starting the Bridge"; +const char OSCServerConst::MSG_BRIDGE_STARTED[] = "Bridge started"; diff --git a/lib-osc/src/server/oscservermsgconst.cpp b/lib-osc/src/server/oscservermsgconst.cpp new file mode 100755 index 00000000..457c606d --- /dev/null +++ b/lib-osc/src/server/oscservermsgconst.cpp @@ -0,0 +1,30 @@ +/** + * @file oscclientconst.h + * + */ +/* Copyright (C) 2019-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "oscservermsgconst.h" + +const char OscServerMsgConst::PARAMS[] = "Configuring OSC Server"; +const char OscServerMsgConst::START[] = "Starting the OSC Server"; +const char OscServerMsgConst::STARTED[] = "OSC Server started"; diff --git a/lib-osc/src/server/oscserverparams.cpp b/lib-osc/src/server/oscserverparams.cpp new file mode 100755 index 00000000..27d93b40 --- /dev/null +++ b/lib-osc/src/server/oscserverparams.cpp @@ -0,0 +1,241 @@ +/** + * @file oscserverparams.cpp + * + */ +/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#if !defined(__clang__) // Needed for compiling on MacOS +# pragma GCC push_options +# pragma GCC optimize ("Os") +#endif + +#include +#include +#ifndef NDEBUG +# include +#endif +#include + +#include "oscserverparams.h" +#include "oscserverparamsconst.h" +#include "osc.h" +#include "oscparamsconst.h" + +#include "lightsetparamsconst.h" + +#include "readconfigfile.h" +#include "sscan.h" +#include "propertiesbuilder.h" + +#include "debug.h" + +using namespace osc::server; + +OSCServerParams::OSCServerParams() { + DEBUG_ENTRY + + memset(&m_Params, 0, sizeof(struct Params)); + m_Params.nIncomingPort = osc::port::DEFAULT_INCOMING; + m_Params.nOutgoingPort = osc::port::DEFAULT_OUTGOING; + + DEBUG_EXIT +} + +void OSCServerParams::Load() { + DEBUG_ENTRY + + m_Params.nSetList = 0; + +#if !defined(DISABLE_FS) + ReadConfigFile configfile(OSCServerParams::staticCallbackFunction, this); + + if (configfile.Read(OscServerParamsConst::FILE_NAME)) { + StoreOscServer::Update(&m_Params); + } else +#endif + StoreOscServer::Copy(&m_Params); + +#ifndef NDEBUG + Dump(); +#endif + DEBUG_EXIT +} + +void OSCServerParams::Load(const char* pBuffer, uint32_t nLength) { + DEBUG_ENTRY + + assert(pBuffer != nullptr); + assert(nLength != 0); + + m_Params.nSetList = 0; + + ReadConfigFile config(OSCServerParams::staticCallbackFunction, this); + + config.Read(pBuffer, nLength); + + StoreOscServer::Update(&m_Params); + +#ifndef NDEBUG + Dump(); +#endif + DEBUG_EXIT +} + +void OSCServerParams::callbackFunction(const char *pLine) { + assert(pLine != nullptr); + + uint16_t nValue16; + + if (Sscan::Uint16(pLine, OscParamsConst::INCOMING_PORT, nValue16) == Sscan::OK) { + if (nValue16 > 1023) { + m_Params.nIncomingPort = nValue16; + m_Params.nSetList |= ParamsMask::INCOMING_PORT; + } else { + m_Params.nIncomingPort = osc::port::DEFAULT_INCOMING; + m_Params.nSetList &= ~ParamsMask::INCOMING_PORT; + } + return; + } + + if (Sscan::Uint16(pLine, OscParamsConst::OUTGOING_PORT, nValue16) == Sscan::OK) { + if (nValue16 > 1023) { + m_Params.nOutgoingPort = nValue16; + m_Params.nSetList |= ParamsMask::OUTGOING_PORT; + } else { + m_Params.nOutgoingPort = osc::port::DEFAULT_OUTGOING; + m_Params.nSetList &= ~ParamsMask::OUTGOING_PORT; + } + return; + } + + uint8_t nValue8; + + if (Sscan::Uint8(pLine, OscServerParamsConst::TRANSMISSION, nValue8) == Sscan::OK) { + if (nValue8 != 0) { + m_Params.nSetList |= ParamsMask::TRANSMISSION; + } else { + m_Params.nSetList &= ~ParamsMask::TRANSMISSION; + } + m_Params.bPartialTransmission = (nValue8 != 0); + return; + } + + uint32_t nLength = sizeof(m_Params.aPath) - 1; + if (Sscan::Char(pLine, OscServerParamsConst::PATH, m_Params.aPath, nLength) == Sscan::OK) { + m_Params.nSetList |= ParamsMask::PATH; + return; + } + + nLength = sizeof(m_Params.aPathInfo) - 1; + if (Sscan::Char(pLine, OscServerParamsConst::PATH_INFO, m_Params.aPathInfo, nLength) == Sscan::OK) { + m_Params.nSetList |= ParamsMask::PATH_INFO; + return; + } + + nLength = sizeof(m_Params.aPathBlackOut) - 1; + if (Sscan::Char(pLine, OscServerParamsConst::PATH_INFO, m_Params.aPathBlackOut, nLength) == Sscan::OK) { + m_Params.nSetList |= ParamsMask::PATH_BLACKOUT; + return; + } +} + +void OSCServerParams::Set(OscServer *pOscServer) { + assert(pOscServer != nullptr); + + if (isMaskSet(ParamsMask::INCOMING_PORT)) { + pOscServer->SetPortIncoming(m_Params.nIncomingPort); + } + + if (isMaskSet(ParamsMask::OUTGOING_PORT)) { + pOscServer->SetPortOutgoing(m_Params.nOutgoingPort); + } + + if (isMaskSet(ParamsMask::PATH)) { + pOscServer->SetPath(m_Params.aPath); + } + + if (isMaskSet(ParamsMask::PATH_INFO)) { + pOscServer->SetPathInfo(m_Params.aPathInfo); + } + + if (isMaskSet(ParamsMask::PATH_BLACKOUT)) { + pOscServer->SetPathBlackOut(m_Params.aPathBlackOut); + } + + if (isMaskSet(ParamsMask::TRANSMISSION)) { + pOscServer->SetPartialTransmission(m_Params.bPartialTransmission); + } +} + +void OSCServerParams::Builder(const osc::server::Params *ptOSCServerParams, char *pBuffer, uint32_t nLength, uint32_t& nSize) { + DEBUG_ENTRY + + assert(pBuffer != nullptr); + + if (ptOSCServerParams != nullptr) { + memcpy(&m_Params, ptOSCServerParams, sizeof(osc::server::Params)); + } else { + StoreOscServer::Copy(&m_Params); + } + + PropertiesBuilder builder(OscServerParamsConst::FILE_NAME, pBuffer, nLength); + + if (!isMaskSet(ParamsMask::PATH)) { + strncpy(m_Params.aPath, OscServer::Get()->GetPath(), sizeof(m_Params.aPath) - 1); + } + + if (!isMaskSet(ParamsMask::PATH_INFO)) { + strncpy(m_Params.aPathInfo, OscServer::Get()->GetPathInfo(), sizeof(m_Params.aPathInfo) - 1); + } + + if (!isMaskSet(ParamsMask::PATH_BLACKOUT)) { + strncpy(m_Params.aPathBlackOut, OscServer::Get()->GetPathBlackOut(), sizeof(m_Params.aPathBlackOut) - 1); + } + + builder.Add(OscParamsConst::INCOMING_PORT, m_Params.nIncomingPort, isMaskSet(ParamsMask::INCOMING_PORT)); + builder.Add(OscParamsConst::OUTGOING_PORT, m_Params.nOutgoingPort, isMaskSet(ParamsMask::OUTGOING_PORT)); + builder.Add(OscServerParamsConst::PATH, m_Params.aPath, isMaskSet(ParamsMask::PATH)); + builder.Add(OscServerParamsConst::PATH_INFO, m_Params.aPathInfo, isMaskSet(ParamsMask::PATH_INFO)); + builder.Add(OscServerParamsConst::PATH_BLACKOUT, m_Params.aPathBlackOut, isMaskSet(ParamsMask::PATH_BLACKOUT)); + builder.Add(OscServerParamsConst::TRANSMISSION, m_Params.bPartialTransmission, isMaskSet(ParamsMask::TRANSMISSION)); + + nSize = builder.GetSize(); + + DEBUG_EXIT +} + +void OSCServerParams::staticCallbackFunction(void *p, const char *s) { + assert(p != nullptr); + assert(s != nullptr); + + (static_cast(p))->callbackFunction(s); +} + +void OSCServerParams::Dump() { + printf("%s::%s \'%s\':\n", __FILE__, __FUNCTION__, OscServerParamsConst::FILE_NAME); + printf(" %s=%d\n", OscParamsConst::INCOMING_PORT, m_Params.nIncomingPort); + printf(" %s=%d\n", OscParamsConst::OUTGOING_PORT, m_Params.nOutgoingPort); + printf(" %s=%s\n", OscServerParamsConst::PATH, m_Params.aPath); + printf(" %s=%s\n", OscServerParamsConst::PATH_INFO, m_Params.aPathInfo); + printf(" %s=%s\n", OscServerParamsConst::PATH_BLACKOUT, m_Params.aPathBlackOut); + printf(" %s=%d\n", OscServerParamsConst::TRANSMISSION, m_Params.bPartialTransmission); +} diff --git a/lib-osc/src/server/oscserverparamsconst.cpp b/lib-osc/src/server/oscserverparamsconst.cpp new file mode 100755 index 00000000..e31ee24e --- /dev/null +++ b/lib-osc/src/server/oscserverparamsconst.cpp @@ -0,0 +1,34 @@ +/** + * @file oscserverparamsconst.cpp + * + */ +/* Copyright (C) 2022 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "oscserverparamsconst.h" + +const char OscServerParamsConst::FILE_NAME[] = "osc.txt"; + +const char OscServerParamsConst::PATH[] = "path"; +const char OscServerParamsConst::PATH_INFO[] = "path_info"; +const char OscServerParamsConst::PATH_BLACKOUT[] = "path_blackout"; + +const char OscServerParamsConst::TRANSMISSION[] = "partial_transmission"; diff --git a/lib-pp/.cproject b/lib-pp/.cproject index ef3f9a39..51a83123 100755 --- a/lib-pp/.cproject +++ b/lib-pp/.cproject @@ -33,11 +33,9 @@ - diff --git a/lib-pp/Rules.mk b/lib-pp/Rules.mk index a6be369d..5f30977a 100644 --- a/lib-pp/Rules.mk +++ b/lib-pp/Rules.mk @@ -6,5 +6,4 @@ else DEFINES+=LIGHTSET_PORTS=32 endif -EXTRA_INCLUDES =../lib-properties/include ../lib-hal/include ../lib-network/include -EXTRA_INCLUDES+=../lib-lightset/include +EXTRA_INCLUDES =../lib-properties/include ../lib-network/include ../lib-lightset/include diff --git a/lib-pp/src/pp.cpp b/lib-pp/src/pp.cpp index d255af4c..948e7810 100644 --- a/lib-pp/src/pp.cpp +++ b/lib-pp/src/pp.cpp @@ -195,7 +195,7 @@ void PixelPusher::Run() { #endif } -void PixelPusher::HandlePusherCommand(__attribute__((unused)) const uint8_t *pBuffer, __attribute__((unused)) uint32_t nSize) { +void PixelPusher::HandlePusherCommand([[maybe_unused]] const uint8_t *pBuffer, [[maybe_unused]] uint32_t nSize) { DEBUG_ENTRY DEBUG_PRINTF("pBuffer=%p, nSize=%u", reinterpret_cast(pBuffer), nSize); #if !defined(CONFIG_PP_16BITSTUFF) @@ -207,7 +207,7 @@ void PixelPusher::HandlePusherCommand(__attribute__((unused)) const uint8_t *pBu #include void PixelPusher::Print() { - puts("PixelPusher:"); + puts("PixelPusher"); printf(" Count : %u\n", m_nCount); printf(" Channels per pixel: %u\n", pp::configuration::CHANNELS_PER_PIXEL); printf(" Active ports : %u\n", m_nActivePorts); diff --git a/lib-properties/.cproject b/lib-properties/.cproject index d5f5c8c6..a24b26c9 100644 --- a/lib-properties/.cproject +++ b/lib-properties/.cproject @@ -30,11 +30,9 @@ - diff --git a/lib-properties/include/devicesparamsconst.h b/lib-properties/include/devicesparamsconst.h index 0d8059dc..2d65ff79 100644 --- a/lib-properties/include/devicesparamsconst.h +++ b/lib-properties/include/devicesparamsconst.h @@ -2,7 +2,7 @@ * @file devicesparamsconst.h * */ -/* Copyright (C) 2019-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -36,8 +36,6 @@ struct DevicesParamsConst { static const char LED_T1H[]; static const char COUNT[]; - - static const char GROUPING_ENABLED[]; static const char GROUPING_COUNT[]; static const char SPI_SPEED_HZ[]; diff --git a/lib-properties/include/propertiesbuilder.h b/lib-properties/include/propertiesbuilder.h index 0deb359f..79ca861b 100644 --- a/lib-properties/include/propertiesbuilder.h +++ b/lib-properties/include/propertiesbuilder.h @@ -2,7 +2,7 @@ * @file propertiesbuilder.h * */ -/* Copyright (C) 2019-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -38,7 +38,7 @@ class PropertiesBuilder { } template - bool Add(const char *pProperty, const T x, bool bIsSet, uint32_t nPrecision = 1) { + bool Add(const char *pProperty, const T x, bool bIsSet, int nPrecision = 1) { if (m_nSize >= m_nLength) { return false; } @@ -57,7 +57,7 @@ class PropertiesBuilder { return true; } - template int inline add_part(char *p, uint32_t nSize, const char *pProperty, const T x, bool bIsSet, __attribute__((unused)) uint32_t nPrecision) { + template int inline add_part(char *p, uint32_t nSize, const char *pProperty, const T x, bool bIsSet, [[maybe_unused]] int nPrecision) { if (bIsSet || m_bJson) { if (m_bJson) { return snprintf(p, nSize, "\"%s\":%d,", pProperty, static_cast(x)); @@ -88,8 +88,12 @@ class PropertiesBuilder { return AddHex(pProperty, nValue32, bIsSet, 6); } + bool AddUtcOffset(const char *pProperty, const int8_t nHours, const uint8_t nMinutes); + bool AddComment(const char *pComment); + bool AddRaw(const char *pRaw); + uint16_t GetSize() { if (m_bJson) { m_pBuffer[m_nSize - 1] = '}'; @@ -100,7 +104,7 @@ class PropertiesBuilder { } private: - bool AddHex(const char *pProperty, uint32_t nValue, const bool bIsSet, const uint32_t nWidth); + bool AddHex(const char *pProperty, uint32_t nValue, const bool bIsSet, const int nWidth); private: char *m_pBuffer; @@ -109,7 +113,7 @@ class PropertiesBuilder { bool m_bJson; }; -template<> int inline PropertiesBuilder::add_part(char *p, uint32_t nSize, const char *pProperty, const float x, bool bIsSet, uint32_t nPrecision) { +template<> int inline PropertiesBuilder::add_part(char *p, uint32_t nSize, const char *pProperty, const float x, bool bIsSet, int nPrecision) { if (bIsSet || m_bJson) { if (m_bJson) { return snprintf(p, nSize, "\"%s\":%.*f,", pProperty, nPrecision, x); @@ -121,7 +125,7 @@ template<> int inline PropertiesBuilder::add_part(char *p, uint32_t nSize return snprintf(p, nSize, "#%s=%.*f\n", pProperty, nPrecision, x); } -template<> int inline PropertiesBuilder::add_part(char *p, uint32_t nSize, const char *pProperty, char* x, bool bIsSet, __attribute__((unused)) uint32_t nPrecision) { +template<> int inline PropertiesBuilder::add_part(char *p, uint32_t nSize, const char *pProperty, char* x, bool bIsSet, [[maybe_unused]] int nPrecision) { if (bIsSet || m_bJson) { if (m_bJson) { return snprintf(p, nSize, "\"%s\":\"%s\",", pProperty, x); @@ -133,7 +137,7 @@ template<> int inline PropertiesBuilder::add_part(char *p, uint32_t nSize return snprintf(p, nSize, "#%s=%s\n", pProperty, x); } -template<> int inline PropertiesBuilder::add_part(char *p, uint32_t nSize, const char *pProperty, const char* x, bool bIsSet, uint32_t nPrecision) { +template<> int inline PropertiesBuilder::add_part(char *p, uint32_t nSize, const char *pProperty, const char* x, bool bIsSet, int nPrecision) { return PropertiesBuilder::add_part(p, nSize, pProperty, const_cast(x), bIsSet, nPrecision); } diff --git a/lib-properties/include/readconfigfile.h b/lib-properties/include/readconfigfile.h index 264c0906..76eeb645 100644 --- a/lib-properties/include/readconfigfile.h +++ b/lib-properties/include/readconfigfile.h @@ -1,7 +1,7 @@ /** * @file readconfigfile.h */ -/* Copyright (C) 2017-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-properties/include/sscan.h b/lib-properties/include/sscan.h index 6435a04c..928b73d2 100644 --- a/lib-properties/include/sscan.h +++ b/lib-properties/include/sscan.h @@ -2,7 +2,7 @@ * @file sscan.h * */ -/* Copyright (C) 2016-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2016-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -51,6 +51,7 @@ class Sscan { static ReturnCode I2c(const char *pBuffer, char *pName, uint8_t& nLength, uint8_t& nAddress, uint8_t& nReserved); static ReturnCode Spi(const char *pBuffer, char& nChipSelect, char *pName, uint8_t& nLength, uint8_t& nAddress, uint16_t &nDmxStartAddress, uint32_t &nSpeedHz); + static ReturnCode UtcOffset(const char *pBuffer, const char *pName, int8_t& nHours, uint8_t& nMinutes); private: static uint8_t fromHex(const char Hex[2]); static const char *checkName(const char *pBuffer, const char *pName); diff --git a/lib-properties/src/devicesparamsconst.cpp b/lib-properties/src/devicesparamsconst.cpp index d32e554a..039acff2 100644 --- a/lib-properties/src/devicesparamsconst.cpp +++ b/lib-properties/src/devicesparamsconst.cpp @@ -2,7 +2,7 @@ * @file devicesparamsconst.cpp * */ -/* Copyright (C) 2019-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -35,8 +35,6 @@ const char DevicesParamsConst::LED_T0H[] = "led_t0h"; const char DevicesParamsConst::LED_T1H[] = "led_t1h"; const char DevicesParamsConst::COUNT[] = "led_count"; - -const char DevicesParamsConst::GROUPING_ENABLED[] = "led_grouping"; const char DevicesParamsConst::GROUPING_COUNT[] = "led_group_count"; const char DevicesParamsConst::SPI_SPEED_HZ[] = "clock_speed_hz"; diff --git a/lib-properties/src/properties.cpp b/lib-properties/src/properties.cpp index 5aa4caa0..a9017b92 100644 --- a/lib-properties/src/properties.cpp +++ b/lib-properties/src/properties.cpp @@ -2,7 +2,7 @@ * @file properties.cpp * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -124,17 +124,17 @@ int convert_json_file(char *pBuffer, uint32_t nLength, const bool bSkipFileName) } if ((*pSrc == '"') || (*pSrc == ',') || (*pSrc == '}')) { - if (!bSkipFileName) { - *pDst++ = '\n'; - } else { - *pDst++ = '\0'; - } + *pDst++ = '\n'; nNewLength++; } pSrc++; } + if (bSkipFileName) { + nNewLength--; + } + debug_dump(pBuffer, static_cast(nNewLength)); DEBUG_EXIT return static_cast(nNewLength); diff --git a/lib-properties/src/propertiesbuilder.cpp b/lib-properties/src/propertiesbuilder.cpp index a2803a75..054f1c0c 100644 --- a/lib-properties/src/propertiesbuilder.cpp +++ b/lib-properties/src/propertiesbuilder.cpp @@ -100,6 +100,32 @@ bool PropertiesBuilder::AddIpAddress(const char *pProperty, uint32_t nValue, boo return true; } +bool PropertiesBuilder::AddUtcOffset(const char *pProperty, const int8_t nHours, const uint8_t nMinutes) { + if (m_nSize >= m_nLength) { + return false; + } + + auto *p = &m_pBuffer[m_nSize]; + const auto nSize = static_cast(m_nLength - m_nSize); + + int i; + + if (m_bJson) { + i = snprintf(p, nSize, "\"%s\":\"%s%.2d:%.2u\",", pProperty, nHours > 0 ? "+" : "", nHours, nMinutes); + } else { + i = snprintf(p, nSize, "%s=%s%.2d:%.2u", pProperty, nHours > 0 ? "+" : "", nHours, nMinutes); + } + + if (i > static_cast(nSize)) { + return false; + } + + m_nSize = static_cast(m_nSize + i); + + DEBUG_PRINTF("m_nLength=%d, m_nSize=%d", m_nLength, m_nSize); + return true; +} + bool PropertiesBuilder::AddComment(const char *pComment) { if (m_bJson) { return true; @@ -124,3 +150,28 @@ bool PropertiesBuilder::AddComment(const char *pComment) { return true; } + +bool PropertiesBuilder::AddRaw(const char *pRaw) { + if (m_bJson) { + return true; + } + + if (m_nSize >= m_nLength) { + return false; + } + + auto *p = &m_pBuffer[m_nSize]; + const auto nSize = static_cast(m_nLength - m_nSize); + + const auto i = snprintf(p, nSize, "%s\n", pRaw); + + if (i > static_cast(nSize)) { + return false; + } + + m_nSize = static_cast(m_nSize + i); + + DEBUG_PRINTF("pRaw=%s, m_nLength=%d, m_nSize=%d", pRaw, m_nLength, m_nSize); + + return true; +} diff --git a/lib-properties/src/propertiesbuilderaddhex.cpp b/lib-properties/src/propertiesbuilderaddhex.cpp index 1b30e950..da71d8fa 100644 --- a/lib-properties/src/propertiesbuilderaddhex.cpp +++ b/lib-properties/src/propertiesbuilderaddhex.cpp @@ -2,7 +2,7 @@ * @file propertiesbuilderaddhex.cpp * */ -/* Copyright (C) 2020-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -30,13 +30,14 @@ #include #include +#include #include #include "propertiesbuilder.h" #include "debug.h" -bool PropertiesBuilder::AddHex(const char *pProperty, uint32_t nValue, const bool bIsSet, const uint32_t nWidth) { +bool PropertiesBuilder::AddHex(const char *pProperty, uint32_t nValue, const bool bIsSet, const int nWidth) { if (m_nSize >= m_nLength) { return false; } @@ -48,12 +49,12 @@ bool PropertiesBuilder::AddHex(const char *pProperty, uint32_t nValue, const boo if (bIsSet || m_bJson) { if (m_bJson) { - i = snprintf(p, nSize, "\"%s\":\"%.*x\",", pProperty, nWidth, nValue); + i = snprintf(p, nSize, "\"%s\":\"%.*x\",", pProperty, static_cast(nWidth), static_cast(nValue)); } else { - i = snprintf(p, nSize, "%s=%.*x\n", pProperty, nWidth, nValue); + i = snprintf(p, nSize, "%s=%.*x\n", pProperty, static_cast(nWidth), static_cast(nValue)); } } else { - i = snprintf(p, nSize, "#%s=%.*x\n", pProperty, nWidth, nValue); + i = snprintf(p, nSize, "#%s=%.*x\n", pProperty, static_cast(nWidth), static_cast(nValue)); } if (i > static_cast(nSize)) { diff --git a/lib-properties/src/readconfigfile.cpp b/lib-properties/src/readconfigfile.cpp index a831c31d..2da2a35c 100644 --- a/lib-properties/src/readconfigfile.cpp +++ b/lib-properties/src/readconfigfile.cpp @@ -85,6 +85,8 @@ bool ReadConfigFile::Read(const char *pFileName) { #endif void ReadConfigFile::Read(const char *pBuffer, unsigned nLength) { + DEBUG_ENTRY + assert(pBuffer != nullptr); assert(nLength != 0); @@ -114,9 +116,12 @@ void ReadConfigFile::Read(const char *pBuffer, unsigned nLength) { nLength--; } - if (buffer[0] >= 'a') { + if (buffer[0] >= '0') { *pLine = '\0'; + DEBUG_PUTS(&buffer[0]); m_pCallBack(m_p, &buffer[0]); } } + + DEBUG_EXIT } diff --git a/lib-properties/src/sscanutcoffset.cpp b/lib-properties/src/sscanutcoffset.cpp new file mode 100755 index 00000000..ffd7c509 --- /dev/null +++ b/lib-properties/src/sscanutcoffset.cpp @@ -0,0 +1,101 @@ +/** + * @file sscanutcoffset.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#if !defined(__clang__) // Needed for compiling on MacOS +# pragma GCC push_options +# pragma GCC optimize ("Os") +#endif + +#include +#include +#include + +#include "sscan.h" + +Sscan::ReturnCode Sscan::UtcOffset(const char *pBuffer, const char *pName, int8_t& nHours, uint8_t& nMinutes) { + assert(pBuffer != nullptr); + assert(pName != nullptr); + + const char *p; + + if ((p = checkName(pBuffer, pName)) == nullptr) { + return Sscan::NAME_ERROR; + } + + auto bIsNegatieve = false; + + if (*p == '-') { + p++; + bIsNegatieve = true; + } else if (*p == '+') { + p++; + } + + if ((*p == ' ') || (*p == 0)) { + return Sscan::VALUE_ERROR; + } + + nHours = 0; + + if ((*p == '0') || (*p == '1')) { + if (*p == '1') { + nHours = 10; + } + p++; + } else { + return Sscan::VALUE_ERROR; + } + + if (isdigit(*p) == 0) { + return Sscan::VALUE_ERROR; + } + + nHours = static_cast(nHours + (*p - '0')); + + p++; + + if (*p != ':') { + return Sscan::VALUE_ERROR; + } + + p++; + + if ((isdigit(p[0]) == 0) || (isdigit(p[1]) == 0)) { + return Sscan::VALUE_ERROR; + } + + if ((p[2] == ' ') || (p[2] == 0)) { + nMinutes = static_cast((p[0] - '0') * 10); + nMinutes = static_cast(nMinutes + (p[1] - '0')); + + if (bIsNegatieve) { + nHours = -nHours; + } + + return Sscan::OK; + } + + return Sscan::VALUE_ERROR; +} diff --git a/lib-rdm/.cproject b/lib-rdm/.cproject index 16617ad6..3be66702 100644 --- a/lib-rdm/.cproject +++ b/lib-rdm/.cproject @@ -30,11 +30,9 @@ - diff --git a/lib-rdm/Rules.mk b/lib-rdm/Rules.mk index 65108ca7..b87e2d93 100644 --- a/lib-rdm/Rules.mk +++ b/lib-rdm/Rules.mk @@ -1,11 +1,38 @@ EXTRA_INCLUDES=../lib-rdmsensor/include ../lib-rdmsubdevice/include ../lib-dmx/include ../lib-properties/include ../lib-lightset/include -EXTRA_INCLUDES+=../lib-hal/include ../lib-network/include ../lib-display/include +EXTRA_INCLUDES+=../lib-network/include ../lib-display/include +EXTRA_INCLUDES+=../lib-e131/include ifneq ($(MAKE_FLAGS),) + ifeq (,$(findstring NODE_ARTNET,$(MAKE_FLAGS))) + ifeq ($(findstring RDM_RESPONDER,$(MAKE_FLAGS)), RDM_RESPONDER) + EXTRA_SRCDIR+=src/responder + EXTRA_INCLUDES+=../lib-dmxreceiver/include + endif + endif + + ifeq ($(findstring RDM_CONTROLLER,$(MAKE_FLAGS)), RDM_CONTROLLER) + EXTRA_SRCDIR+=src/controller + endif + ifneq (,$(findstring NODE_RDMNET_LLRP_ONLY,$(MAKE_FLAGS))) - EXTRA_SRCDIR += src/llrp + EXTRA_SRCDIR+=src/llrp + EXTRA_SRCDIR+=src/rdmnet + endif + ifneq (,$(findstring CONFIG_STORE_USE_ROM,$(MAKE_FLAGS))) + EXTRA_INCLUDES+=../lib-flashcode/include endif else - DEFINES+=ENABLE_RDM_MANUFACTURER_PIDS - EXTRA_SRCDIR += src/llrp + ifneq (, $(shell test -d '../lib-network/src/noemac' && echo -n yes)) + DEFINES+=NO_EMAC + else + EXTRA_SRCDIR+=src/llrp src/rdmnet + endif + + ifneq (, $(shell test -d '../lib-dmxreceiver' && echo -n yes)) + EXTRA_INCLUDES+=../lib-dmxreceiver/include + EXTRA_SRCDIR+=src/responder + endif + DEFINES+=CONFIG_RDM_ENABLE_SUBDEVICES CONFIG_RDM_SUBDEVICES_USE_I2C CONFIG_RDM_SUBDEVICES_USE_SPI + DEFINES+=CONFIG_RDM_ENABLE_MANUFACTURER_PIDS CONFIG_RDM_MANUFACTURER_PIDS_SET + DEFINES+=RDM_RESPONDER endif \ No newline at end of file diff --git a/lib-rdmnet/include/e133.h b/lib-rdm/include/e133.h old mode 100644 new mode 100755 similarity index 89% rename from lib-rdmnet/include/e133.h rename to lib-rdm/include/e133.h index b086dafc..38fc2a3a --- a/lib-rdmnet/include/e133.h +++ b/lib-rdm/include/e133.h @@ -2,7 +2,7 @@ * @file e133.h * */ -/* Copyright (C) 2019-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -54,6 +54,15 @@ */ #define VECTOR_RDM_CMD_RDM_DATA 0xCC +/** + * Table A.15 RDM Parameter ID + */ + +#define E133_COMPONENT_SCOPE 0x0800 +#define E133_SEARCH_DOMAIN 0x0801 +#define E133_TCP_COMMS_STATUS 0x0802 +#define E133_BROKER_STATUS 0x0803 + /** * Table A-23: LLRP Component Type Codes */ diff --git a/lib-rdmnet/include/llrp.h b/lib-rdm/include/llrp/llrp.h old mode 100644 new mode 100755 similarity index 100% rename from lib-rdmnet/include/llrp.h rename to lib-rdm/include/llrp/llrp.h diff --git a/lib-rdmnet/include/llrpdevice.h b/lib-rdm/include/llrp/llrpdevice.h old mode 100644 new mode 100755 similarity index 90% rename from lib-rdmnet/include/llrpdevice.h rename to lib-rdm/include/llrp/llrpdevice.h index b561563f..53dafb7a --- a/lib-rdmnet/include/llrpdevice.h +++ b/lib-rdm/include/llrp/llrpdevice.h @@ -30,8 +30,10 @@ #include #include -#include "llrppacket.h" +#include "llrp/llrppacket.h" #include "e133.h" +#include "rdmconst.h" +#include "rdmhandler.h" #include "network.h" @@ -49,16 +51,20 @@ class LLRPDevice { public: LLRPDevice() { DEBUG_ENTRY + s_nHandleLLRP = Network::Get()->Begin(llrp::device::LLRP_PORT); assert(s_nHandleLLRP != -1); Network::Get()->JoinGroup(s_nHandleLLRP, llrp::device::IPV4_LLRP_REQUEST); + DEBUG_EXIT } - virtual ~LLRPDevice() { + ~LLRPDevice() { DEBUG_ENTRY + Network::Get()->LeaveGroup(s_nHandleLLRP, llrp::device::IPV4_LLRP_REQUEST); Network::Get()->End(llrp::device::LLRP_PORT); + DEBUG_EXIT } @@ -108,21 +114,12 @@ class LLRPDevice { printf(" Multicast Response : " IPSTR "\n", IP2STR(llrp::device::IPV4_LLRP_RESPONSE)); } -protected: - virtual void CopyUID(__attribute__((unused)) uint8_t *pUID) { - // Override - } - - virtual void CopyCID(__attribute__((unused)) uint8_t *pCID) { - // Override - } - - virtual uint8_t *LLRPHandleRdmCommand(__attribute__((unused)) const uint8_t *pRDMCommand) { - // Override - return nullptr; +private: + uint8_t *LLRPHandleRdmCommand(const uint8_t *pRdmDataNoSC) { + m_RDMHandler.HandleData(pRdmDataNoSC, reinterpret_cast(&s_RdmCommand)); + return reinterpret_cast(&s_RdmCommand); } -private: void HandleRequestMessage(); void HandleRdmCommand(); // DEBUG subject for deletions @@ -131,9 +128,12 @@ class LLRPDevice { void DumpRdmMessageInNoSc(); private: + RDMHandler m_RDMHandler { false }; + static int32_t s_nHandleLLRP; static uint32_t s_nIpAddressFrom; static uint8_t *s_pLLRP; + static TRdmMessage s_RdmCommand; }; #endif /* LLRPDEVICE_H_ */ diff --git a/lib-rdmnet/include/llrppacket.h b/lib-rdm/include/llrp/llrppacket.h old mode 100644 new mode 100755 similarity index 98% rename from lib-rdmnet/include/llrppacket.h rename to lib-rdm/include/llrp/llrppacket.h index f9a1ec46..3be2b885 --- a/lib-rdmnet/include/llrppacket.h +++ b/lib-rdm/include/llrp/llrppacket.h @@ -2,7 +2,7 @@ * @file llrppacket.h * */ -/* Copyright (C) 2019-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-rdm/include/rdm.h b/lib-rdm/include/rdm.h index 49b81ba1..c760ec7b 100644 --- a/lib-rdm/include/rdm.h +++ b/lib-rdm/include/rdm.h @@ -27,131 +27,76 @@ #define RDM_H_ #include +#include -#define RDM_DATA_BUFFER_SIZE 512 ///< -#define RDM_DATA_BUFFER_INDEX_ENTRIES (1 << 4) ///< -#define RDM_DATA_BUFFER_INDEX_MASK (RDM_DATA_BUFFER_INDEX_ENTRIES - 1) ///< - -#define RDM_ROOT_DEVICE 0 ///< - -///< 3 Timing -#define RDM_TRANSMIT_BREAK_TIME 176 ///< Min 176us -#define RDM_TRANSMIT_MAB_TIME 12 ///< Min 12us - -///< 3.2.2 Responder Packet spacing -#define RDM_RESPONDER_PACKET_SPACING 200 ///< Min 176us, Max 2ms - -#define RDM_RESPONDER_DATA_DIRECTION_DELAY 4 ///< - -///< 5 Device Addressing -#define RDM_UID_SIZE 6 ///< 48-bit - -///< 6.2.3 Message Length -#define RDM_MESSAGE_MINIMUM_SIZE 24U ///< Minimum size of RDM message without the checksum -#define RDM_MESSAGE_CHECKSUM_SIZE 2U ///< Size of the checksum -#define RDM_MESSAGE_COUNT_MAX 255U ///< Message Count field for Responder Generated Messages - -///< 7.6 Discovery Mute/Un-Mute Messages -///< 7.6.1 Control Field -///< The Reserved bits (Bits 4-15) are reserved for future implementation and shall be set to 0. -#define RDM_CONTROL_FIELD_MANAGED_PROXY_FLAG (1 << 0) ///< The Managed Proxy Flag (Bit 0) shall be set to 1 when the responder is a Proxy device. -#define RDM_CONTROL_FIELD_SUB_DEVICE_FLAG (1 << 1) ///< The Sub-Device Flag (Bit 1) shall be set to 1 when the responder supports Sub-Devices. -#define RDM_CONTROL_FIELD_BOOTLOADER_FLAG (1 << 2) ///< The Boot-Loader Flag (Bit 2) shall only be set to 1 when the device is incapable of normal operation until receiving a firmware upload. -#define RDM_CONTROL_FIELD_PROXIED_DEVICE_FLAG (1 << 3) ///< The Proxied Device Flag (Bit 3) shall only be set to 1 when a Proxy is responding to Discovery on behalf of another device. This flag indicates that the response has come from a Proxy, rather than the actual device. - -#define RDM_DEVICE_MANUFACTURER_ID_LENGTH 2 ///< - -///< 10.5.4 Get Manufacturer Label (MANUFACTURER_LABEL) -#define RDM_MANUFACTURER_LABEL_MAX_LENGTH 32 ///< Manufacturer name for the device of up to 32 characters. - -///< 10.5.5 Get/Set Device Label (DEVICE_LABEL) -#define RDM_DEVICE_LABEL_MAX_LENGTH 32 - -///< 10.5.8 Get/Set Language (LANGUAGE) -#define RDM_DEVICE_SUPPORTED_LANGUAGE_LENGTH 2 ///< The Language Codes are 2 character alpha codes as defined by ISO 639-1. - -///< 10.5.9 Get Software Version Label (SOFTWARE_VERSION_LABEL) -#define RDM_SOFTWARE_VERSION_LABEL_MAX_LENGTH 32 - -///< 10.5.10 Get Boot Software Version ID (BOOT_SOFTWARE_VERSION_ID) -#define RDM_BOOT_SOFTWARE_VERSION_ID_LENGTH 4 ///< The Boot Software Version ID is a 32-bit value determined by the Manufacturer. - -///< 10.5.11 Get Boot Software Version Label (BOOT_SOFTWARE_VERSION_LABEL) -#define RDM_BOOT_SOFTWARE_VERSION_LABEL_MAX_LENGTH 32 - -///< 10.7.1 Get Sensor Definition (SENSOR_DEFINITION) -#define RDM_SENSORS_ALL 0xFF ///< The sensor number 0xFF is used to address all sensors. - -///< 10.8.1 Get/Set Device Hours (DEVICE_HOURS) -#define RDM_DEVICE_HOURS_SIZE 4 - -///< 10.11.1 Get/Set Identify Device (IDENTIFY_DEVICE) -#define RDM_IDENTIFY_STATE_OFF 0 -#define RDM_IDENTIFY_STATE_ON 1 - -#if ! defined (PACKED) -# define PACKED __attribute__((packed)) -#endif - -struct TRdmMessage { - uint8_t start_code; ///< 1 SC_RDM - uint8_t sub_start_code; ///< 2 SC_SUB_MESSAGE - uint8_t message_length; ///< 3 Range 24 to 255 - uint8_t destination_uid[RDM_UID_SIZE]; ///< 4,5,6,7,8,9 - uint8_t source_uid[RDM_UID_SIZE]; ///< 10,11,12,13,14,15 - uint8_t transaction_number; ///< 16 - union { - uint8_t port_id; ///< 17 - uint8_t response_type; ///< 17 - } slot16; - uint8_t message_count; ///< 18 - uint8_t sub_device[2]; ///< 19, 20 - uint8_t command_class; ///< 21 - uint8_t param_id[2]; ///< 22, 23 - uint8_t param_data_length; ///< 24 PDL Range 0 to 231 - uint8_t param_data[231]; ///< 25,,,, PD 6.2.3 Message Length - uint8_t checksum_filler[2]; -}PACKED; - -struct TRdmMessageNoSc { - uint8_t sub_start_code; ///< 2 SC_SUB_MESSAGE - uint8_t message_length; ///< 3 Range 24 to 255 - uint8_t destination_uid[RDM_UID_SIZE]; ///< 4,5,6,7,8,9 - uint8_t source_uid[RDM_UID_SIZE]; ///< 10,11,12,13,14,15 - uint8_t transaction_number; ///< 16 - union { - uint8_t port_id; ///< 17 - uint8_t response_type; ///< 17 - } slot16; - uint8_t message_count; ///< 18 - uint8_t sub_device[2]; ///< 19, 20 - uint8_t command_class; ///< 21 - uint8_t param_id[2]; ///< 22, 23 - uint8_t param_data_length; ///< 24 PDL Range 0 to 231 - uint8_t param_data[231]; ///< 25,,,, PD 6.2.3 Message Length - uint8_t checksum_filler[2]; -}PACKED; - -struct TRdmDiscoveryMsg { - uint8_t header_FE[7]; ///< - uint8_t header_AA; ///< - uint8_t masked_device_id[12]; ///< - uint8_t checksum[4]; ///< -}PACKED; - -// Unique identifier (UID) which consists of a 2 byte ESTA manufacturer ID, and a 4 byte device ID. -static const uint8_t UID_ALL[RDM_UID_SIZE] __attribute__((aligned(4))) = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; +#include "rdmconst.h" +#include "dmx.h" + +#include "hal_api.h" class Rdm { public: - static void Send(uint32_t nPortIndex, struct TRdmMessage *, uint32_t nSpacingMicros = 0); - static void SendRaw(uint32_t nPortIndex, const uint8_t *pRdmData, uint32_t nLength); + static void SendRaw(const uint32_t nPortIndex, const uint8_t *pRdmData, const uint32_t nLength) { + assert(pRdmData != nullptr); + assert(nLength != 0); + + Dmx::Get()->SetPortDirection(nPortIndex, dmx::PortDirection::OUTP, false); + + Dmx::Get()->RdmSendRaw(nPortIndex, pRdmData, nLength); + + udelay(RDM_RESPONDER_DATA_DIRECTION_DELAY); + + Dmx::Get()->SetPortDirection(nPortIndex, dmx::PortDirection::INP, true); + } + + static void Send(const uint32_t nPortIndex, struct TRdmMessage *pRdmCommand) { + assert(nPortIndex < dmx::config::max::PORTS); + assert(pRdmCommand != nullptr); + + auto *pData = reinterpret_cast(pRdmCommand); + uint32_t i; + uint16_t nChecksum = 0; + + pRdmCommand->transaction_number = s_TransactionNumber[nPortIndex]; + + for (i = 0; i < pRdmCommand->message_length; i++) { + nChecksum = static_cast(nChecksum + pData[i]); + } + + pData[i++] = static_cast(nChecksum >> 8); + pData[i] = static_cast(nChecksum & 0XFF); + + SendRaw(nPortIndex, reinterpret_cast(pRdmCommand), pRdmCommand->message_length + RDM_MESSAGE_CHECKSUM_SIZE); + + s_TransactionNumber[nPortIndex]++; + } + + static void SendRawRespondMessage(const uint32_t nPortIndex, const uint8_t *pRdmData, const uint32_t nLength) { + assert(nPortIndex < dmx::config::max::PORTS); + assert(pRdmData != nullptr); + assert(nLength != 0); + + extern volatile uint32_t gsv_RdmDataReceiveEnd; + // 3.2.2 Responder Packet spacing + udelay(RDM_RESPONDER_PACKET_SPACING, gsv_RdmDataReceiveEnd); + + SendRaw(nPortIndex, pRdmData, nLength); + } + + static void SendDiscoveryRespondMessage(const uint32_t nPortIndex, const uint8_t *pRdmData, const uint32_t nLength) { + Dmx::Get()->RdmSendDiscoveryRespondMessage(nPortIndex, pRdmData, nLength); + } + + static const uint8_t *Receive(const uint32_t nPortIndex) { + return Dmx::Get()->RdmReceive(nPortIndex); + } - static void SendRawRespondMessage(uint32_t nPortIndex, const uint8_t *pRdmData, uint32_t nLength); - static void SendDiscoveryRespondMessage(uint32_t nPortIndex, const uint8_t *pRdmData, uint32_t nLength); + static const uint8_t *ReceiveTimeOut(const uint32_t nPortIndex, const uint16_t nTimeOut) { + return Dmx::Get()->RdmReceiveTimeOut(nPortIndex, nTimeOut); + } - static const uint8_t *Receive(uint32_t nPortIndex); - static const uint8_t *ReceiveTimeOut(uint32_t nPortIndex, uint16_t nTimeOut); +private: + static uint8_t s_TransactionNumber[dmx::config::max::PORTS]; }; #endif /* RDM_H_ */ diff --git a/lib-rdm/include/rdm_manufacturer_pid.h b/lib-rdm/include/rdm_manufacturer_pid.h index 23b0614a..d9a1293e 100755 --- a/lib-rdm/include/rdm_manufacturer_pid.h +++ b/lib-rdm/include/rdm_manufacturer_pid.h @@ -1,5 +1,26 @@ -/* - * rdm_manufacturer_pid.h +/** + * @file rdm_manufacturer_pid.h + * + */ +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. */ #ifndef RDM_MANUFACTURER_PID_H_ @@ -41,7 +62,7 @@ struct ManufacturerPid { template struct Description { - static constexpr size_t size = N - 1; + static constexpr auto size = N - 1U; static_assert(size <= DEVICE_DESCRIPTION_MAX_LENGTH, "Description is too long"); static constexpr char const* value = T::description; }; @@ -54,7 +75,7 @@ struct ManufacturerParamData { }; bool handle_manufactureer_pid_get(const uint16_t nPid, const ManufacturerParamData *pIn, ManufacturerParamData *pOut, uint16_t& nReason); - +bool handle_manufactureer_pid_set(const bool isBroadcast, const uint16_t nPid, const rdm::ParameterDescription ¶meterDescription, const ManufacturerParamData *pIn, ManufacturerParamData *pOut, uint16_t& nReason); } // namespace rdm #endif /* RDM_MANUFACTURER_PID_H_ */ diff --git a/lib-rdm/include/rdm_message_print.h b/lib-rdm/include/rdm_message_print.h new file mode 100755 index 00000000..e20798be --- /dev/null +++ b/lib-rdm/include/rdm_message_print.h @@ -0,0 +1,36 @@ +/** + * @file rdm_message_print.h + * + */ +/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RDM_MESSAGE_PRINT_H_ +#define RDM_MESSAGE_PRINT_H_ + +#include + +namespace rdm { +void message_print(const uint8_t *pRdmData); +void message_print_no_sc(const uint8_t *pRdmDataNoSc); +} // namespace rdm + +#endif /* RDM_MESSAGE_PRINT_H_ */ diff --git a/lib-rdm/include/rdm_selftest.h b/lib-rdm/include/rdm_selftest.h index d3e76fe2..46ca352f 100644 --- a/lib-rdm/include/rdm_selftest.h +++ b/lib-rdm/include/rdm_selftest.h @@ -2,7 +2,7 @@ * @file rdm_selftest.h * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-rdm/include/rdmconst.h b/lib-rdm/include/rdmconst.h index 2813fb93..5ed73d7c 100644 --- a/lib-rdm/include/rdmconst.h +++ b/lib-rdm/include/rdmconst.h @@ -2,7 +2,7 @@ * @file rdmconst.h * */ -/* Copyright (C) 2019 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,6 +28,120 @@ #include +#define RDM_DATA_BUFFER_SIZE 512 ///< +#define RDM_DATA_BUFFER_INDEX_ENTRIES (1 << 4) ///< +#define RDM_DATA_BUFFER_INDEX_MASK (RDM_DATA_BUFFER_INDEX_ENTRIES - 1) ///< + +#define RDM_ROOT_DEVICE 0 ///< + +///< 3 Timing +#define RDM_TRANSMIT_BREAK_TIME 176 ///< Min 176us +#define RDM_TRANSMIT_MAB_TIME 12 ///< Min 12us + +///< 3.2.2 Responder Packet spacing +#define RDM_RESPONDER_PACKET_SPACING 200 ///< Min 176us, Max 2ms + +#define RDM_RESPONDER_DATA_DIRECTION_DELAY 4 ///< + +///< 5 Device Addressing +#define RDM_UID_SIZE 6 ///< 48-bit + +///< 6.2.3 Message Length +#define RDM_MESSAGE_MINIMUM_SIZE 24U ///< Minimum size of RDM message without the checksum +#define RDM_MESSAGE_CHECKSUM_SIZE 2U ///< Size of the checksum +#define RDM_MESSAGE_COUNT_MAX 255U ///< Message Count field for Responder Generated Messages + +///< 7.6 Discovery Mute/Un-Mute Messages +///< 7.6.1 Control Field +///< The Reserved bits (Bits 4-15) are reserved for future implementation and shall be set to 0. +#define RDM_CONTROL_FIELD_MANAGED_PROXY_FLAG (1 << 0) ///< The Managed Proxy Flag (Bit 0) shall be set to 1 when the responder is a Proxy device. +#define RDM_CONTROL_FIELD_SUB_DEVICE_FLAG (1 << 1) ///< The Sub-Device Flag (Bit 1) shall be set to 1 when the responder supports Sub-Devices. +#define RDM_CONTROL_FIELD_BOOTLOADER_FLAG (1 << 2) ///< The Boot-Loader Flag (Bit 2) shall only be set to 1 when the device is incapable of normal operation until receiving a firmware upload. +#define RDM_CONTROL_FIELD_PROXIED_DEVICE_FLAG (1 << 3) ///< The Proxied Device Flag (Bit 3) shall only be set to 1 when a Proxy is responding to Discovery on behalf of another device. This flag indicates that the response has come from a Proxy, rather than the actual device. + +#define RDM_DEVICE_MANUFACTURER_ID_LENGTH 2 ///< + +///< 10.5.4 Get Manufacturer Label (MANUFACTURER_LABEL) +#define RDM_MANUFACTURER_LABEL_MAX_LENGTH 32 ///< Manufacturer name for the device of up to 32 characters. + +///< 10.5.5 Get/Set Device Label (DEVICE_LABEL) +#define RDM_DEVICE_LABEL_MAX_LENGTH 32 + +///< 10.5.8 Get/Set Language (LANGUAGE) +#define RDM_DEVICE_SUPPORTED_LANGUAGE_LENGTH 2 ///< The Language Codes are 2 character alpha codes as defined by ISO 639-1. + +///< 10.5.9 Get Software Version Label (SOFTWARE_VERSION_LABEL) +#define RDM_SOFTWARE_VERSION_LABEL_MAX_LENGTH 32 + +///< 10.5.10 Get Boot Software Version ID (BOOT_SOFTWARE_VERSION_ID) +#define RDM_BOOT_SOFTWARE_VERSION_ID_LENGTH 4 ///< The Boot Software Version ID is a 32-bit value determined by the Manufacturer. + +///< 10.5.11 Get Boot Software Version Label (BOOT_SOFTWARE_VERSION_LABEL) +#define RDM_BOOT_SOFTWARE_VERSION_LABEL_MAX_LENGTH 32 + +///< 10.7.1 Get Sensor Definition (SENSOR_DEFINITION) +#define RDM_SENSORS_ALL 0xFF ///< The sensor number 0xFF is used to address all sensors. + +///< 10.8.1 Get/Set Device Hours (DEVICE_HOURS) +#define RDM_DEVICE_HOURS_SIZE 4 + +///< 10.11.1 Get/Set Identify Device (IDENTIFY_DEVICE) +#define RDM_IDENTIFY_STATE_OFF 0 +#define RDM_IDENTIFY_STATE_ON 1 + +#if ! defined (PACKED) +# define PACKED __attribute__((packed)) +#endif + +struct TRdmMessage { + uint8_t start_code; ///< 1 SC_RDM + uint8_t sub_start_code; ///< 2 SC_SUB_MESSAGE + uint8_t message_length; ///< 3 Range 24 to 255 + uint8_t destination_uid[RDM_UID_SIZE]; ///< 4,5,6,7,8,9 + uint8_t source_uid[RDM_UID_SIZE]; ///< 10,11,12,13,14,15 + uint8_t transaction_number; ///< 16 + union { + uint8_t port_id; ///< 17 + uint8_t response_type; ///< 17 + } slot16; + uint8_t message_count; ///< 18 + uint8_t sub_device[2]; ///< 19, 20 + uint8_t command_class; ///< 21 + uint8_t param_id[2]; ///< 22, 23 + uint8_t param_data_length; ///< 24 PDL Range 0 to 231 + uint8_t param_data[231]; ///< 25,,,, PD 6.2.3 Message Length + uint8_t checksum_filler[2]; +}PACKED; + +struct TRdmMessageNoSc { + uint8_t sub_start_code; ///< 2 SC_SUB_MESSAGE + uint8_t message_length; ///< 3 Range 24 to 255 + uint8_t destination_uid[RDM_UID_SIZE]; ///< 4,5,6,7,8,9 + uint8_t source_uid[RDM_UID_SIZE]; ///< 10,11,12,13,14,15 + uint8_t transaction_number; ///< 16 + union { + uint8_t port_id; ///< 17 + uint8_t response_type; ///< 17 + } slot16; + uint8_t message_count; ///< 18 + uint8_t sub_device[2]; ///< 19, 20 + uint8_t command_class; ///< 21 + uint8_t param_id[2]; ///< 22, 23 + uint8_t param_data_length; ///< 24 PDL Range 0 to 231 + uint8_t param_data[231]; ///< 25,,,, PD 6.2.3 Message Length + uint8_t checksum_filler[2]; +}PACKED; + +struct TRdmDiscoveryMsg { + uint8_t header_FE[7]; ///< + uint8_t header_AA; ///< + uint8_t masked_device_id[12]; ///< + uint8_t checksum[4]; ///< +}PACKED; + +// Unique identifier (UID) which consists of a 2 byte ESTA manufacturer ID, and a 4 byte device ID. +static constexpr uint8_t UID_ALL[RDM_UID_SIZE] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; + struct RDMConst { static const char MANUFACTURER_NAME[]; static const uint8_t MANUFACTURER_ID[]; diff --git a/lib-rdm/include/rdmdevice.h b/lib-rdm/include/rdmdevice.h index 6d5e50ba..e0906778 100644 --- a/lib-rdm/include/rdmdevice.h +++ b/lib-rdm/include/rdmdevice.h @@ -2,7 +2,7 @@ * @file rdmdevice.h * */ -/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -42,23 +42,6 @@ struct TRDMDeviceInfoData { uint8_t length; }; -///< http://rdm.openlighting.org/pid/display?manufacturer=0&pid=96 -struct TRDMDeviceInfo { - uint8_t protocol_major; ///< The response for this field shall always be same regardless of whether this message is directed to the Root Device or a Sub-Device. - uint8_t protocol_minor; ///< The response for this field shall always be same regardless of whether this message is directed to the Root Device or a Sub-Device. - uint8_t device_model[2]; ///< This field identifies the Device Model ID of the Root Device or the Sub-Device. The Manufacturer shall not use the same ID to represent more than one unique model type. - uint8_t product_category[2]; ///< Devices shall report a Product Category based on the products primary function. - uint8_t software_version[4]; ///< This field indicates the Software Version ID for the device. The Software Version ID is a 32-bit value determined by the Manufacturer. - uint8_t dmx_footprint[2]; ///< If the DEVICE_INFO message is directed to a Sub-Device, then the response for this field contains the DMX512 Footprint for that Sub-Device. If the message is sent to the Root Device, it is the Footprint for the Root Device itself. If the Device or Sub-Device does not utilize Null Start Code packets for any control or functionality then it shall report a Footprint of 0x0000. - uint8_t current_personality; ///< - uint8_t personality_count; ///< - uint8_t dmx_start_address[2]; ///< If the Device or Sub-Device that this message is directed to has a DMX512 Footprint of 0, then this field shall be set to 0xFFFF. - uint8_t sub_device_count[2]; ///< The response for this field shall always be same regardless of whether this message is directed to the Root Device or a Sub-Device. - uint8_t sensor_count; ///< This field indicates the number of available sensors in a Root Device or Sub-Device. When this parameter is directed to a Sub-Device, the reply shall be identical for any Sub-Device owned by a specific Root Device. -}; - -#include "rdm.h" - class RDMDevice { public: RDMDevice(); @@ -72,10 +55,6 @@ class RDMDevice { void Print(); - void SetRDMDeviceStore(RDMDeviceStore *pRDMDeviceStore) { - m_pRDMDeviceStore = pRDMDeviceStore; - } - void SetFactoryDefaults() { DEBUG_ENTRY TRDMDeviceInfoData info = {m_aFactoryRootLabel, m_nFactoryRootLabelLength}; @@ -91,10 +70,33 @@ class RDMDevice { } const uint8_t *GetUID() const { +#if defined (NO_EMAC) || !defined(CONFIG_RDMDEVICE_UUID_IP) +#else + const auto nIp = Network::Get()->GetIp(); +# if !defined(CONFIG_RDMDEVICE_REVERSE_UID) + m_aUID[5] = static_cast(nIp >> 24); + m_aUID[4] = (nIp >> 16) & 0xFF; + m_aUID[3] = (nIp >> 8) & 0xFF; + m_aUID[2] = nIp & 0xFF; +# else + m_aUID[2] = static_cast(nIp >> 24); + m_aUID[3] = (nIp >> 16) & 0xFF; + m_aUID[4] = (nIp >> 8) & 0xFF; + m_aUID[5] = nIp & 0xFF; +# endif +#endif return m_aUID; } const uint8_t *GetSN() const { +#if defined (NO_EMAC) || !defined(CONFIG_RDMDEVICE_UUID_IP) +#else + GetUID(); + m_aSN[0] = m_aUID[5]; + m_aSN[1] = m_aUID[4]; + m_aSN[2] = m_aUID[3]; + m_aSN[3] = m_aUID[2]; +#endif return m_aSN; } @@ -115,9 +117,7 @@ class RDMDevice { memcpy(m_aRootLabel, pInfo->data, nLength); m_nRootLabelLength = nLength; - if (m_pRDMDeviceStore != nullptr) { - m_pRDMDeviceStore->SaveLabel(m_aRootLabel, m_nRootLabelLength); - } + RDMDeviceStore::SaveLabel(m_aRootLabel, m_nRootLabelLength); } else { memcpy(m_aFactoryRootLabel, pInfo->data, nLength); m_nFactoryRootLabelLength = nLength; @@ -143,6 +143,10 @@ class RDMDevice { return m_nProductDetail; } + static RDMDevice *Get() { + return s_pThis; + } + private: uint16_t CalculateChecksum() { uint16_t nChecksum = m_nFactoryRootLabelLength; @@ -158,8 +162,6 @@ class RDMDevice { char m_aFactoryRootLabel[RDM_DEVICE_LABEL_MAX_LENGTH]; char m_aRootLabel[RDM_DEVICE_LABEL_MAX_LENGTH]; - RDMDeviceStore *m_pRDMDeviceStore { nullptr }; - uint16_t m_nProductCategory { E120_PRODUCT_CATEGORY_OTHER }; uint16_t m_nProductDetail { E120_PRODUCT_DETAIL_OTHER }; uint16_t m_nCheckSum { 0 }; @@ -171,6 +173,8 @@ class RDMDevice { uint8_t m_nFactoryRootLabelLength { 0 }; bool m_IsInit { false }; + + static RDMDevice *s_pThis; }; #endif /* RDMDEVICE_H_ */ diff --git a/lib-rdm/include/rdmdevicecontroller.h b/lib-rdm/include/rdmdevicecontroller.h index bd4a1d64..b7454eb3 100644 --- a/lib-rdm/include/rdmdevicecontroller.h +++ b/lib-rdm/include/rdmdevicecontroller.h @@ -2,7 +2,7 @@ * @file rdmdevicecontroller.h * */ -/* Copyright (C) 2017-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -37,10 +37,7 @@ class RDMDeviceController: public RDMDevice { DEBUG_EXIT } - ~RDMDeviceController() { - DEBUG_ENTRY - DEBUG_EXIT - } + ~RDMDeviceController() = default; }; #endif /* RDMDEVICECONTROLLER_H_ */ diff --git a/lib-rdm/include/rdmdeviceparams.h b/lib-rdm/include/rdmdeviceparams.h index cd9e762e..dff15621 100644 --- a/lib-rdm/include/rdmdeviceparams.h +++ b/lib-rdm/include/rdmdeviceparams.h @@ -28,8 +28,8 @@ #include -#include "rdmdevice.h" -#include "rdm.h" +#include "rdmconst.h" +#include "configstore.h" namespace rdm { namespace deviceparams { @@ -49,19 +49,24 @@ struct Mask { } // namespace rdmdevice } // namespace rdm +class RDMDevice; + class RDMDeviceParamsStore { public: - virtual ~RDMDeviceParamsStore() {} + static void Update(const struct rdm::deviceparams::Params *pParams) { + ConfigStore::Get()->Update(configstore::Store::RDMDEVICE, pParams, sizeof(struct rdm::deviceparams::Params)); + } - virtual void Update(const struct rdm::deviceparams::Params *pParams)=0; - virtual void Copy(struct rdm::deviceparams::Params *pParams)=0; + static void Copy(struct rdm::deviceparams::Params *pParams) { + ConfigStore::Get()->Copy(configstore::Store::RDMDEVICE, pParams, sizeof(struct rdm::deviceparams::Params)); + } }; class RDMDeviceParams { public: - RDMDeviceParams(RDMDeviceParamsStore *pRDMDeviceParamsStore); + RDMDeviceParams(); - bool Load(); + void Load(); void Load(const char *pBuffer, uint32_t nLength); void Builder(const struct rdm::deviceparams::Params *pParams, char *pBuffer, uint32_t nLength, uint32_t& nSize); @@ -71,19 +76,16 @@ class RDMDeviceParams { void Set(RDMDevice *pRDMDevice); - void Dump(); - -public: static void staticCallbackFunction(void *p, const char *s); private: + void Dump(); void callbackFunction(const char *s); bool isMaskSet(uint32_t nMask) const { return (m_Params.nSetList & nMask) == nMask; } private: - RDMDeviceParamsStore *m_pRDMDeviceParamsStore; rdm::deviceparams::Params m_Params; }; diff --git a/lib-rdm/include/rdmdeviceresponder.h b/lib-rdm/include/rdmdeviceresponder.h index 1345f907..ed36f5d7 100644 --- a/lib-rdm/include/rdmdeviceresponder.h +++ b/lib-rdm/include/rdmdeviceresponder.h @@ -2,7 +2,7 @@ * @file rdmdeviceresponder.h * */ -/* Copyright (C) 2018-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,7 +29,7 @@ #include #include -#include "rdm.h" +#include "rdmconst.h" #include "rdmdevice.h" #include "rdmidentify.h" #include "rdmpersonality.h" @@ -42,6 +42,22 @@ namespace rdm { namespace device { namespace responder { static constexpr uint8_t DEFAULT_CURRENT_PERSONALITY = 1; + +///< http://rdm.openlighting.org/pid/display?manufacturer=0&pid=96 +struct DeviceInfo { + uint8_t protocol_major; ///< The response for this field shall always be same regardless of whether this message is directed to the Root Device or a Sub-Device. + uint8_t protocol_minor; ///< The response for this field shall always be same regardless of whether this message is directed to the Root Device or a Sub-Device. + uint8_t device_model[2]; ///< This field identifies the Device Model ID of the Root Device or the Sub-Device. The Manufacturer shall not use the same ID to represent more than one unique model type. + uint8_t product_category[2]; ///< Devices shall report a Product Category based on the products primary function. + uint8_t software_version[4]; ///< This field indicates the Software Version ID for the device. The Software Version ID is a 32-bit value determined by the Manufacturer. + uint8_t dmx_footprint[2]; ///< If the DEVICE_INFO message is directed to a Sub-Device, then the response for this field contains the DMX512 Footprint for that Sub-Device. If the message is sent to the Root Device, it is the Footprint for the Root Device itself. If the Device or Sub-Device does not utilize Null Start Code packets for any control or functionality then it shall report a Footprint of 0x0000. + uint8_t current_personality; ///< + uint8_t personality_count; ///< + uint8_t dmx_start_address[2]; ///< If the Device or Sub-Device that this message is directed to has a DMX512 Footprint of 0, then this field shall be set to 0xFFFF. + uint8_t sub_device_count[2]; ///< The response for this field shall always be same regardless of whether this message is directed to the Root Device or a Sub-Device. + uint8_t sensor_count; ///< This field indicates the number of available sensors in a Root Device or Sub-Device. When this parameter is directed to a Sub-Device, the reply shall be identical for any Sub-Device owned by a specific Root Device. +}; + void factorydefaults(); } // namespace responder } // namespace device @@ -49,31 +65,36 @@ void factorydefaults(); class RDMDeviceResponder: public RDMDevice { public: - RDMDeviceResponder(RDMPersonality **pRDMPersonalities, uint32_t nPersonalityCount); - virtual ~RDMDeviceResponder() {} + RDMDeviceResponder(RDMPersonality **pRDMPersonalities, const uint32_t nPersonalityCount, const uint32_t nCurrentPersonality = rdm::device::responder::DEFAULT_CURRENT_PERSONALITY); + virtual ~RDMDeviceResponder() = default; void Init(); void Print(); // E120_DEVICE_INFO 0x0060 - struct TRDMDeviceInfo *GetDeviceInfo(uint16_t nSubDevice = RDM_ROOT_DEVICE) { + struct rdm::device::responder::DeviceInfo *GetDeviceInfo(uint16_t nSubDevice = RDM_ROOT_DEVICE) { if (nSubDevice != RDM_ROOT_DEVICE) { const auto *sub_device_info = m_RDMSubDevices.GetInfo(nSubDevice); if (sub_device_info != nullptr) { - m_tRDMSubDeviceInfo.dmx_footprint[0] = static_cast(sub_device_info->dmx_footprint >> 8); - m_tRDMSubDeviceInfo.dmx_footprint[1] = static_cast(sub_device_info->dmx_footprint); - m_tRDMSubDeviceInfo.current_personality = sub_device_info->current_personality; - m_tRDMSubDeviceInfo.personality_count = sub_device_info->personality_count; - m_tRDMSubDeviceInfo.dmx_start_address[0] = static_cast(sub_device_info->dmx_start_address >> 8); - m_tRDMSubDeviceInfo.dmx_start_address[1] = static_cast(sub_device_info->dmx_start_address); - m_tRDMSubDeviceInfo.sensor_count = sub_device_info->sensor_count; + m_SubDeviceInfo.dmx_footprint[0] = static_cast(sub_device_info->dmx_footprint >> 8); + m_SubDeviceInfo.dmx_footprint[1] = static_cast(sub_device_info->dmx_footprint); + m_SubDeviceInfo.current_personality = sub_device_info->current_personality; + m_SubDeviceInfo.personality_count = sub_device_info->personality_count; + m_SubDeviceInfo.dmx_start_address[0] = static_cast(sub_device_info->dmx_start_address >> 8); + m_SubDeviceInfo.dmx_start_address[1] = static_cast(sub_device_info->dmx_start_address); + m_SubDeviceInfo.sensor_count = sub_device_info->sensor_count; } - return &m_tRDMSubDeviceInfo; + return &m_SubDeviceInfo; } - return &m_tRDMDeviceInfo; + //TODO FIXME Quick fix + const auto nProductCategory = RDMDevice::GetProductCategory(); + m_DeviceInfo.product_category[0] =static_cast( nProductCategory >> 8); + m_DeviceInfo.product_category[1] = static_cast(nProductCategory); + + return &m_DeviceInfo; } // E120_DEVICE_LABEL 0x0082 @@ -113,7 +134,7 @@ class RDMDeviceResponder: public RDMDevice { SetPersonalityCurrent(RDM_ROOT_DEVICE, rdm::device::responder::DEFAULT_CURRENT_PERSONALITY); SetDmxStartAddress(RDM_ROOT_DEVICE, m_nDmxStartAddressFactoryDefault); - memcpy(&m_tRDMSubDeviceInfo, &m_tRDMDeviceInfo, sizeof(struct TRDMDeviceInfo)); + memcpy(&m_SubDeviceInfo, &m_DeviceInfo, sizeof(struct rdm::device::responder::DeviceInfo)); m_RDMSubDevices.SetFactoryDefaults(); @@ -173,15 +194,15 @@ class RDMDeviceResponder: public RDMDevice { return; } - const auto *pPersonality = m_pRDMPersonalities[m_tRDMDeviceInfo.current_personality - 1]; + const auto *pPersonality = m_pRDMPersonalities[m_DeviceInfo.current_personality - 1]; assert(pPersonality != nullptr); auto *pLightSet = pPersonality->GetLightSet(); if (pLightSet != nullptr) { if (pLightSet->SetDmxStartAddress(nDmxStartAddress)) { - m_tRDMDeviceInfo.dmx_start_address[0] = static_cast(nDmxStartAddress >> 8); - m_tRDMDeviceInfo.dmx_start_address[1] = static_cast(nDmxStartAddress); + m_DeviceInfo.dmx_start_address[0] = static_cast(nDmxStartAddress >> 8); + m_DeviceInfo.dmx_start_address[1] = static_cast(nDmxStartAddress); } DmxStartAddressUpdate(); @@ -195,7 +216,7 @@ class RDMDeviceResponder: public RDMDevice { return m_RDMSubDevices.GetDmxStartAddress(nSubDevice); } - return static_cast((m_tRDMDeviceInfo.dmx_start_address[0] << 8) + m_tRDMDeviceInfo.dmx_start_address[1]); + return static_cast((m_DeviceInfo.dmx_start_address[0] << 8) + m_DeviceInfo.dmx_start_address[1]); } // E120_SLOT_INFO 0x0120 @@ -204,7 +225,7 @@ class RDMDeviceResponder: public RDMDevice { return false; // TODO GetSlotInfo SubDevice } - const auto *pPersonality = m_pRDMPersonalities[m_tRDMDeviceInfo.current_personality - 1]; + const auto *pPersonality = m_pRDMPersonalities[m_DeviceInfo.current_personality - 1]; auto *pLightSet = pPersonality->GetLightSet(); return pLightSet->GetSlotInfo(nSlotOffset, tSlotInfo); @@ -215,7 +236,7 @@ class RDMDeviceResponder: public RDMDevice { return m_RDMSubDevices.GetDmxFootPrint(nSubDevice); } - return static_cast((m_tRDMDeviceInfo.dmx_footprint[0] << 8) + m_tRDMDeviceInfo.dmx_footprint[1]); + return static_cast((m_DeviceInfo.dmx_footprint[0] << 8) + m_DeviceInfo.dmx_footprint[1]); } // Personalities @@ -226,7 +247,7 @@ class RDMDeviceResponder: public RDMDevice { return m_RDMSubDevices.GetPersonality(nSubDevice, nPersonality); } - assert(nPersonality <= m_tRDMDeviceInfo.personality_count); + assert(nPersonality <= m_DeviceInfo.personality_count); return m_pRDMPersonalities[nPersonality - 1]; } @@ -236,7 +257,7 @@ class RDMDeviceResponder: public RDMDevice { return m_RDMSubDevices.GetPersonalityCount(nSubDevice); } - return m_tRDMDeviceInfo.personality_count; + return m_DeviceInfo.personality_count; } void SetPersonalityCurrent(uint16_t nSubDevice, uint8_t nPersonality) { @@ -247,9 +268,9 @@ class RDMDeviceResponder: public RDMDevice { return; } - m_tRDMDeviceInfo.current_personality = nPersonality; + m_DeviceInfo.current_personality = nPersonality; - assert(nPersonality <= m_tRDMDeviceInfo.personality_count); + assert(nPersonality <= m_DeviceInfo.personality_count); const auto *pPersonality = m_pRDMPersonalities[nPersonality - 1]; assert(pPersonality != nullptr); @@ -257,10 +278,10 @@ class RDMDeviceResponder: public RDMDevice { auto *pLightSet = pPersonality->GetLightSet(); if (pLightSet != nullptr) { - m_tRDMDeviceInfo.dmx_footprint[0] = static_cast(pLightSet->GetDmxFootprint() >> 8); - m_tRDMDeviceInfo.dmx_footprint[1] = static_cast(pLightSet->GetDmxFootprint()); - m_tRDMDeviceInfo.dmx_start_address[0] = static_cast(pLightSet->GetDmxStartAddress() >> 8); - m_tRDMDeviceInfo.dmx_start_address[1] = static_cast(pLightSet->GetDmxStartAddress()); + m_DeviceInfo.dmx_footprint[0] = static_cast(pLightSet->GetDmxFootprint() >> 8); + m_DeviceInfo.dmx_footprint[1] = static_cast(pLightSet->GetDmxFootprint()); + m_DeviceInfo.dmx_start_address[0] = static_cast(pLightSet->GetDmxStartAddress() >> 8); + m_DeviceInfo.dmx_start_address[1] = static_cast(pLightSet->GetDmxStartAddress()); PersonalityUpdate(pLightSet); } @@ -271,7 +292,7 @@ class RDMDeviceResponder: public RDMDevice { return m_RDMSubDevices.GetPersonalityCurrent(nSubDevice); } - return m_tRDMDeviceInfo.current_personality; + return m_DeviceInfo.current_personality; } static RDMDeviceResponder* Get() { @@ -280,8 +301,8 @@ class RDMDeviceResponder: public RDMDevice { private: uint16_t CalculateChecksum() { - auto nChecksum = static_cast((m_tRDMDeviceInfo.dmx_start_address[0] >> 8) + m_tRDMDeviceInfo.dmx_start_address[1]); - nChecksum = static_cast(nChecksum + m_tRDMDeviceInfo.current_personality); + auto nChecksum = static_cast((m_DeviceInfo.dmx_start_address[0] >> 8) + m_DeviceInfo.dmx_start_address[1]); + nChecksum = static_cast(nChecksum + m_DeviceInfo.current_personality); return nChecksum; } @@ -295,8 +316,8 @@ class RDMDeviceResponder: public RDMDevice { RDMPersonality **m_pRDMPersonalities; char *m_pSoftwareVersion; uint8_t m_nSoftwareVersionLength; - TRDMDeviceInfo m_tRDMDeviceInfo; - TRDMDeviceInfo m_tRDMSubDeviceInfo; + rdm::device::responder::DeviceInfo m_DeviceInfo; + rdm::device::responder::DeviceInfo m_SubDeviceInfo; char m_aLanguage[2]; // bool m_IsFactoryDefaults { true }; diff --git a/lib-rdm/include/rdmdevicestore.h b/lib-rdm/include/rdmdevicestore.h index 30d7b0ee..31af1a28 100644 --- a/lib-rdm/include/rdmdevicestore.h +++ b/lib-rdm/include/rdmdevicestore.h @@ -2,7 +2,7 @@ * @file rdmdevicestore.h * */ -/* Copyright (C) 2019-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,12 +27,17 @@ #define RDMDEVICESTORE_H_ #include +#include + +#include "rdmdeviceparams.h" +#include "configstore.h" class RDMDeviceStore { public: - virtual ~RDMDeviceStore() {} - - virtual void SaveLabel(const char *pLabel, uint8_t nLength)=0; + static void SaveLabel(const char *pLabel, uint8_t nLength) { + ConfigStore::Get()->Update(configstore::Store::RDMDEVICE, offsetof(struct rdm::deviceparams::Params, aDeviceRootLabel), pLabel, nLength, rdm::deviceparams::Mask::LABEL); + ConfigStore::Get()->Update(configstore::Store::RDMDEVICE, offsetof(struct rdm::deviceparams::Params, nDeviceRootLabelLength), &nLength, sizeof(uint8_t), rdm::deviceparams::Mask::LABEL); + } }; #endif /* RDMDEVICESTORE_H_ */ diff --git a/lib-rdm/include/rdmdiscovery.h b/lib-rdm/include/rdmdiscovery.h new file mode 100755 index 00000000..beac8fa6 --- /dev/null +++ b/lib-rdm/include/rdmdiscovery.h @@ -0,0 +1,220 @@ +/** + * @file rdmddiscovery.h + * + */ +/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RDMDDISCOVERY_H_ +#define RDMDDISCOVERY_H_ + +#include +#include +#include + +#include "rdmmessage.h" +#include "debug.h" + +namespace rdmdiscovery { +#ifndef NDEBUG + static constexpr uint32_t RECEIVE_TIME_OUT = 58000; + static constexpr uint32_t LATE_RESPONSE_TIME_OUT = 40000; +#else + static constexpr uint32_t RECEIVE_TIME_OUT = 5800; + static constexpr uint32_t LATE_RESPONSE_TIME_OUT = 1000; +#endif +static constexpr uint32_t UNMUTE_COUNTER = 3; +static constexpr uint32_t MUTE_COUNTER = 10; +static constexpr uint32_t DISCOVERY_STACK_SIZE = rdmtod::TOD_TABLE_SIZE; +static constexpr uint32_t DISCOVERY_COUNTER = 3; +static constexpr uint32_t QUIKFIND_COUNTER = 5; +static constexpr uint32_t QUIKFIND_DISCOVERY_COUNTER = 5; + +enum class State { + IDLE, + UNMUTE, + MUTE, + DISCOVERY, + DISCOVERY_SINGLE_DEVICE, + DUB, + QUICKFIND, + QUICKFIND_DISCOVERY, + LATE_RESPONSE, + FINISHED +}; +} // namespace rdmdiscovery + +class RDMDiscovery { +public: + RDMDiscovery(const uint8_t *pUid); + + bool Full(const uint32_t nPortIndex, RDMTod *pRDMTod); + bool Incremental(const uint32_t nPortIndex, RDMTod *pRDMTod); + + bool Stop(); + + bool IsRunning(uint32_t& nPortIndex, bool& bIsIncremental) const { + nPortIndex = m_nPortIndex; + bIsIncremental = m_doIncremental; + return (m_State != rdmdiscovery::State::IDLE); + } + + bool IsFinished(uint32_t& nPortIndex, bool& bIsIncremental) { + nPortIndex = m_nPortIndex; + bIsIncremental = m_doIncremental; + + if (m_bIsFinished) { + m_bIsFinished = false; + return true; + } + + return false; + } + + uint32_t CopyWorkingQueue(char *pOutBuffer, const uint32_t nOutBufferSize); + + void Run() { + if (__builtin_expect((m_State == rdmdiscovery::State::IDLE), 1)) { + return; + } + + Process(); + } + +private: + void Process(); + bool Start(const uint32_t nPortIndex, RDMTod *pRDMTod, const bool doIncremental); + bool IsValidDiscoveryResponse(uint8_t *pUid); + + void SavedState([[maybe_unused]] const uint32_t nLine); + void NewState(const rdmdiscovery::State state, const bool doStateLateResponse, [[maybe_unused]] const uint32_t nLine); + +private: + RDMMessage m_Message; + uint8_t *m_pResponse { nullptr }; + uint8_t m_Uid[RDM_UID_SIZE]; + uint32_t m_nPortIndex { 0 }; + RDMTod *m_pRDMTod { nullptr }; + + bool m_bIsFinished { false }; + bool m_doIncremental { false }; + rdmdiscovery::State m_State { rdmdiscovery::State::IDLE }; + rdmdiscovery::State m_SavedState { rdmdiscovery::State::IDLE }; + + struct { + uint32_t nMicros; + } m_LateResponse; + + struct { + uint32_t nCounter; + uint32_t nMicros; + bool bCommandRunning; + } m_UnMute; + + struct { + uint32_t nTodEntries; + uint32_t nCounter; + uint32_t nMicros; + uint8_t uid[RDM_UID_SIZE]; + bool bCommandRunning; + } m_Mute; + + struct { + struct { + bool push(const uint64_t nLowerBound, const uint64_t nUpperBound) { + if (nTop == rdmdiscovery::DISCOVERY_STACK_SIZE - 1) { + assert(0); + return false; + } + + nTop++; + items[nTop].nLowerBound = nLowerBound; + items[nTop].nUpperBound = nUpperBound; + + nDebugStackTopMax = std::max(nDebugStackTopMax, nTop); + return true; + } + + bool pop(uint64_t &nLowerBound, uint64_t &nUpperBound) { + if (nTop == -1) { + return false; + } + + nLowerBound = items[nTop].nLowerBound; + nUpperBound = items[nTop].nUpperBound; + nTop--; + + return true; + } + + int32_t nTop; + + struct { + uint64_t nLowerBound; + uint64_t nUpperBound; + } items[rdmdiscovery::DISCOVERY_STACK_SIZE]; + + int32_t nDebugStackTopMax; + } stack; + + uint64_t nLowerBound; + uint64_t nMidPosition; + uint64_t nUpperBound; + uint32_t nCounter; + uint32_t nMicros; + uint8_t uid[RDM_UID_SIZE]; + uint8_t pdl[2][RDM_UID_SIZE]; + bool bCommandRunning; + } m_Discovery; + + struct { + uint32_t nCounter; + uint32_t nMicros; + bool bCommandRunning; + } m_DiscoverySingleDevice; + + struct { + uint32_t nCounter; + uint32_t nMicros; + bool bCommandRunning; + uint8_t uid[RDM_UID_SIZE]; + } m_QuikFind; + + struct { + uint32_t nCounter; + uint32_t nMicros; + bool bCommandRunning; + uint8_t uid[RDM_UID_SIZE]; + } m_QuikFindDiscovery; + +#ifndef NDEBUG + struct { + struct { + uint64_t nLowerBound; + uint64_t nUpperBound; + } tree[1024]; + + uint32_t nTreeIndex; + } debug; +#endif +}; + +#endif /* RDMDDISCOVERY_H_ */ diff --git a/lib-rdm/include/rdmhandler.h b/lib-rdm/include/rdmhandler.h index d411428f..fb4c0f7b 100644 --- a/lib-rdm/include/rdmhandler.h +++ b/lib-rdm/include/rdmhandler.h @@ -2,7 +2,7 @@ * @file rdmhandler.h * */ -/* Copyright (C) 2018-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,17 +27,19 @@ #define RDMHANDLER_H_ #include +#include #if defined (NODE_RDMNET_LLRP_ONLY) -# if defined (ENABLE_RDM_MANUFACTURER_PIDS) -# undef ENABLE_RDM_MANUFACTURER_PIDS +# if defined (CONFIG_RDM_ENABLE_MANUFACTURER_PIDS) +# undef CONFIG_RDM_ENABLE_MANUFACTURER_PIDS # endif #endif -#include "rdmmessage.h" -#include "rdmqueuedmessage.h" +#if defined (ENABLE_RDM_QUEUED_MSG) +# include "rdmqueuedmessage.h" +#endif -#if defined (ENABLE_RDM_MANUFACTURER_PIDS) +#if defined (CONFIG_RDM_ENABLE_MANUFACTURER_PIDS) # include "rdm_manufacturer_pid.h" #endif @@ -48,10 +50,10 @@ class RDMHandler { void HandleData(const uint8_t *pRdmDataIn, uint8_t *pRdmDataOut); private: - void CreateRespondMessage(uint8_t nResponseType, uint16_t nReason = 0); + void CreateRespondMessage(const uint8_t nResponseType, const uint16_t nReason); void RespondMessageAck(); - void RespondMessageNack(uint16_t nReason); - void HandleString(const char *pString, uint32_t nLength); + void RespondMessageNack(const uint16_t nReason); + void HandleString(const char *pString, const uint32_t nLength); void Handlers(bool bIsBroadcast, uint8_t nCommandClass, uint16_t nParamId, uint8_t nParamDataLength, uint16_t nSubDevice); // Get @@ -59,7 +61,7 @@ class RDMHandler { void GetQueuedMessage(uint16_t nSubDevice); #endif void GetSupportedParameters(uint16_t nSubDevice); -#if defined (ENABLE_RDM_MANUFACTURER_PIDS) +#if defined (CONFIG_RDM_ENABLE_MANUFACTURER_PIDS) void GetParameterDescription(uint16_t nSubDevice); void GetManufacturerPid(uint16_t nSubDevice); #endif @@ -86,7 +88,7 @@ class RDMHandler { void GetIdentifyDevice(uint16_t nSubDevice); void GetRealTimeClock(uint16_t nSubDevice); void GetPowerState(uint16_t nSubDevice); -#if defined (ENABLE_RDM_SELF_TEST) +#if defined (CONFIG_RDM_ENABLE_SELF_TEST) void GetPerformSelfTest(uint16_t nSubDevice); void GetSelfTestDescription(uint16_t nSubDevice); #endif @@ -122,11 +124,14 @@ class RDMHandler { void SetRealTimeClock(bool IsBroadcast, uint16_t nSubDevice); void SetResetDevice(bool IsBroadcast, uint16_t nSubDevice); void SetPowerState(bool IsBroadcast, uint16_t nSubDevice); -#if defined (ENABLE_RDM_SELF_TEST) +#if defined (CONFIG_RDM_ENABLE_SELF_TEST) void SetPerformSelfTest(bool IsBroadcast, uint16_t nSubDevice); #endif #if defined (ENABLE_RDM_PRESET_PLAYBACK) void SetPresetPlayback(bool IsBroadcast, uint16_t nSubDevice); +#endif +#if defined (CONFIG_RDM_ENABLE_MANUFACTURER_PIDS) && defined (CONFIG_RDM_MANUFACTURER_PIDS_SET) + void SetManufacturerPid(bool IsBroadcast, uint16_t nSubDevice); #endif // ANSI E1.37-1 void SetIdentifyMode(bool IsBroadcast, uint16_t nSubDevice); @@ -163,7 +168,7 @@ class RDMHandler { static const PidDefinition PID_DEFINITIONS[]; static const PidDefinition PID_DEFINITIONS_SUB_DEVICES[]; -#if defined (ENABLE_RDM_MANUFACTURER_PIDS) +#if defined (CONFIG_RDM_ENABLE_MANUFACTURER_PIDS) static const PidDefinition PID_DEFINITION_MANUFACTURER_GENERAL; static const rdm::ParameterDescription PARAMETER_DESCRIPTIONS[]; diff --git a/lib-rdm/include/rdmidentify.h b/lib-rdm/include/rdmidentify.h index 7d1e3a45..6d9636e8 100644 --- a/lib-rdm/include/rdmidentify.h +++ b/lib-rdm/include/rdmidentify.h @@ -41,7 +41,7 @@ enum class Mode : uint8_t { class RDMIdentify { public: RDMIdentify(); - ~RDMIdentify() {} + ~RDMIdentify() = default; void On() { m_bIsEnabled = true; diff --git a/lib-rdm/include/rdmmessage.h b/lib-rdm/include/rdmmessage.h index 1492f7ec..970bb05e 100644 --- a/lib-rdm/include/rdmmessage.h +++ b/lib-rdm/include/rdmmessage.h @@ -29,6 +29,7 @@ #include #include +#include "rdm_message_print.h" #include "rdm.h" #include "rdm_e120.h" @@ -47,12 +48,10 @@ class RDMMessage final: public Rdm { m_message.param_data_length = 0; } -#if defined (RDM_CONTROLLER) void SetPortID(const uint8_t nPortID) { assert(nPortID > 0); m_message.slot16.port_id = nPortID; } -#endif void SetSrcUid(const uint8_t *SrcUid){ memcpy(m_message.source_uid, SrcUid, RDM_UID_SIZE); @@ -85,17 +84,13 @@ class RDMMessage final: public Rdm { m_message.message_length = static_cast(m_message.message_length + nLength); } - void Send(uint32_t nPortIndex, uint32_t nSpacingMicros = 0) { + void Send(const uint32_t nPortIndex) { #ifndef NDEBUG - RDMMessage::Print(reinterpret_cast(&m_message)); + rdm::message_print(reinterpret_cast(&m_message)); #endif - Rdm::Send(nPortIndex, &m_message, nSpacingMicros); + Rdm::Send(nPortIndex, &m_message); } -public: - static void Print(const uint8_t *pRdmData); - static void PrintNoSc(const uint8_t *pRdmDataNoSc); - private: TRdmMessage m_message; }; diff --git a/lib-rdmnet/include/rdmnet.h b/lib-rdm/include/rdmnet/rdmnet.h old mode 100644 new mode 100755 similarity index 100% rename from lib-rdmnet/include/rdmnet.h rename to lib-rdm/include/rdmnet/rdmnet.h diff --git a/lib-rdmnet/include/rdmnetconst.h b/lib-rdm/include/rdmnetconst.h old mode 100644 new mode 100755 similarity index 100% rename from lib-rdmnet/include/rdmnetconst.h rename to lib-rdm/include/rdmnetconst.h diff --git a/lib-rdmnet/include/rdmnetdevice.h b/lib-rdm/include/rdmnetdevice.h old mode 100644 new mode 100755 similarity index 70% rename from lib-rdmnet/include/rdmnetdevice.h rename to lib-rdm/include/rdmnetdevice.h index 6777fc26..42f572cb --- a/lib-rdmnet/include/rdmnetdevice.h +++ b/lib-rdm/include/rdmnetdevice.h @@ -2,7 +2,7 @@ * @file rdmnetdevice.h * */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -30,49 +30,52 @@ #include #include "rdmdeviceresponder.h" -#include "llrpdevice.h" +#include "llrp/llrpdevice.h" #include "rdmhandler.h" - #include "e131.h" #include "hardware.h" +#include "debug.h" + #if defined (RDM_RESPONDER) # error "Cannot be both RDMNet Device and RDM Responder" #endif -class RDMNetDevice: public RDMDeviceResponder, public LLRPDevice { +class RDMNetDevice final: public RDMDeviceResponder, public LLRPDevice { public: RDMNetDevice(RDMPersonality **pRDMPersonalities, uint32_t nPersonalityCount) : RDMDeviceResponder(pRDMPersonalities, nPersonalityCount) { - Hardware::Get()->GetUuid(s_Cid); - } - - ~RDMNetDevice() override {}; + DEBUG_ENTRY - void CopyUID(uint8_t *pUID) override { - memcpy(pUID, RDMDeviceResponder::GetUID(), RDM_UID_SIZE); - } - void CopyCID(uint8_t *pCID) override { - memcpy(pCID, s_Cid, sizeof(s_Cid)); + DEBUG_EXIT } - uint8_t *LLRPHandleRdmCommand(const uint8_t *pRdmDataNoSC) override { - m_RDMHandler.HandleData(pRdmDataNoSC, reinterpret_cast(&s_RdmCommand)); - return reinterpret_cast(&s_RdmCommand); - } + ~RDMNetDevice() { + DEBUG_ENTRY + + DEBUG_EXIT + }; void Run() { LLRPDevice::Run(); } - void Print(); + void Print() { + static constexpr auto UUID_STRING_LENGTH = 36; + char uuid_str[UUID_STRING_LENGTH + 1]; + uuid_str[UUID_STRING_LENGTH] = '\0'; -private: - RDMHandler m_RDMHandler { false }; + uint8_t s_Cid[e131::CID_LENGTH]; + Hardware::Get()->GetUuid(s_Cid); + uuid_unparse(s_Cid, uuid_str); - static TRdmMessage s_RdmCommand; - static uint8_t s_Cid[e131::CID_LENGTH]; + printf("RDMNet\n"); + printf(" CID : %s\n", uuid_str); + + LLRPDevice::Print(); + RDMDeviceResponder::Print(); + } }; #endif /* RDMNETDEVICE_H_ */ diff --git a/lib-rdmnet/include/rdmnetllrponly.h b/lib-rdm/include/rdmnetllrponly.h old mode 100644 new mode 100755 similarity index 100% rename from lib-rdmnet/include/rdmnetllrponly.h rename to lib-rdm/include/rdmnetllrponly.h diff --git a/lib-rdm/include/rdmpersonality.h b/lib-rdm/include/rdmpersonality.h index f53209a9..92f76406 100644 --- a/lib-rdm/include/rdmpersonality.h +++ b/lib-rdm/include/rdmpersonality.h @@ -2,7 +2,7 @@ * @file rdmpersonality.h * */ -/* Copyright (C) 2018-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-rdm/include/rdmqueuedmessage.h b/lib-rdm/include/rdmqueuedmessage.h index 3ce5fe17..b713a36b 100644 --- a/lib-rdm/include/rdmqueuedmessage.h +++ b/lib-rdm/include/rdmqueuedmessage.h @@ -28,8 +28,6 @@ #include -#include "rdmmessage.h" - struct TRdmQueuedMessage { uint8_t command_class; ///< 21 uint8_t param_id[2]; ///< 22, 23 diff --git a/lib-rdm/include/rdmresponder.h b/lib-rdm/include/rdmresponder.h new file mode 100644 index 00000000..b685dbdb --- /dev/null +++ b/lib-rdm/include/rdmresponder.h @@ -0,0 +1,192 @@ +/** + * @file rdmresponder.h + * + */ +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RDMRESPONDER_H_ +#define RDMRESPONDER_H_ + +#include +#include +#include + +#include "rdm.h" +#include "rdmhandler.h" +#include "rdmdeviceresponder.h" +#include "rdmpersonality.h" + +#include "dmxreceiver.h" + +#include "lightset.h" + +#include "debug.h" + +#if defined (NODE_RDMNET_LLRP_ONLY) +# error "Cannot be both RDMNet Device and RDM Responder" +#endif + +namespace rdm { +namespace responder { +static constexpr int NO_DATA = 0; +static constexpr int DISCOVERY_RESPONSE = -1; +static constexpr int INVALID_DATA_RECEIVED = -2; +static constexpr int INVALID_RESPONSE = -3; +} // namespace responder +} // namespace rdm + +namespace configstore { +void delay(); +} // namespace configstore + +class RDMResponder final : DMXReceiver, public RDMDeviceResponder, RDMHandler { +public: + RDMResponder(RDMPersonality **pRDMPersonalities, uint32_t nPersonalityCount, const uint32_t nCurrentPersonality = rdm::device::responder::DEFAULT_CURRENT_PERSONALITY) : + DMXReceiver(pRDMPersonalities[nCurrentPersonality - 1]->GetLightSet()), + RDMDeviceResponder(pRDMPersonalities, nPersonalityCount, nCurrentPersonality) + { + assert(s_pThis == nullptr); + s_pThis = this; + } + + ~RDMResponder() override = default; + + void Init() { + RDMDeviceResponder::Init(); + // There is no DMXReceiver::Init() + } + + int Run() { + int16_t nLength; + +#if !defined (CONFIG_RDM_ENABLE_SUBDEVICES) + DMXReceiver::Run(nLength); +#else + const auto *pDmxDataIn = DMXReceiver::Run(nLength); + + if (RDMSubDevices::Get()->GetCount() != 0) { + if (nLength == -1) { + if (m_IsSubDeviceActive) { + RDMSubDevices::Get()->Stop(); + m_IsSubDeviceActive = false; + } + } else if (pDmxDataIn != nullptr) { + RDMSubDevices::Get()->SetData(pDmxDataIn, static_cast(nLength)); + if (!m_IsSubDeviceActive) { + RDMSubDevices::Get()->Start(); + m_IsSubDeviceActive = true; + } + } + } +#endif + + const auto *pRdmDataIn = Rdm::Receive(0); + + if (pRdmDataIn == nullptr) { + return rdm::responder::NO_DATA; + } + +#ifndef NDEBUG + rdm::message_print(pRdmDataIn); +#endif + + if (pRdmDataIn[0] == E120_SC_RDM) { + const auto *pRdmCommand = reinterpret_cast(pRdmDataIn); + + switch (pRdmCommand->command_class) { + case E120_DISCOVERY_COMMAND: + case E120_GET_COMMAND: + case E120_SET_COMMAND: + HandleData(&pRdmDataIn[1], reinterpret_cast(&s_RdmCommand)); + return HandleResponse(reinterpret_cast(&s_RdmCommand)); + break; + default: + DEBUG_PUTS("RDM_RESPONDER_INVALID_DATA_RECEIVED"); + return rdm::responder::INVALID_DATA_RECEIVED; + break; + } + } + + DEBUG_PUTS("RDM_RESPONDER_DISCOVERY_RESPONSE"); + return rdm::responder::DISCOVERY_RESPONSE; + } + + void Print() { + RDMDeviceResponder::Print(); + DMXReceiver::Print(); + } + + void Start() { + // There is no RDMDeviceResponder::Start() + DMXReceiver::Start(); + } + + void DmxDisableOutput(const bool bDisable) { + DMXReceiver::SetDisableOutput(bDisable); + } + + static RDMResponder *Get() { + return s_pThis; + } + + void PersonalityUpdate(uint32_t nPersonality) __attribute__((weak)); + void DmxStartAddressUpdate(uint16_t nDmxStartAddress) __attribute__((weak)); + +private: + int HandleResponse(const uint8_t *pResponse) { + auto nLength = rdm::responder::INVALID_RESPONSE; + + if (pResponse[0] == E120_SC_RDM) { + const auto *p = reinterpret_cast(pResponse); + nLength = static_cast(p->message_length + RDM_MESSAGE_CHECKSUM_SIZE); + Rdm::SendRawRespondMessage(0, pResponse, static_cast(nLength)); + } else if (pResponse[0] == 0xFE) { + nLength = sizeof(struct TRdmDiscoveryMsg); + Rdm::SendDiscoveryRespondMessage(0, pResponse, static_cast(nLength)); + } + +#ifndef NDEBUG + if (nLength != INVALID_RESPONSE) { + rdm::message_print(pResponse); + } +#endif + + configstore::delay(); + return nLength; + } + + void PersonalityUpdate(LightSet *pLightSet) override { + DMXReceiver::SetLightSet(pLightSet); + PersonalityUpdate(static_cast(RDMDeviceResponder::GetPersonalityCurrent(RDM_ROOT_DEVICE))); + } + + void DmxStartAddressUpdate() override { + DmxStartAddressUpdate(RDMDeviceResponder::GetDmxStartAddress(RDM_ROOT_DEVICE)); + } + +private: + static RDMResponder *s_pThis; + static TRdmMessage s_RdmCommand; + static bool m_IsSubDeviceActive; +}; + +#endif /* RDMRESPONDER_H_ */ diff --git a/lib-rdm/include/rdmsensor.h b/lib-rdm/include/rdmsensor.h new file mode 100644 index 00000000..41cb1ea7 --- /dev/null +++ b/lib-rdm/include/rdmsensor.h @@ -0,0 +1,206 @@ +/** + * @file rdmsensor.h + * + */ +/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RDMSENSOR_H_ +#define RDMSENSOR_H_ + +#include +#include +#include +#include + +#include "debug.h" + +namespace rdm { +namespace sensor { +struct Defintion { + uint8_t sensor; + uint8_t type; + uint8_t unit; + uint8_t prefix; + int16_t range_min; + int16_t range_max; + int16_t normal_min; + int16_t normal_max; + char description[32]; + uint8_t nLength; + uint8_t recorded_supported; +}; + +struct Values { + int16_t present; + int16_t lowest_detected; + int16_t highest_detected; + int16_t recorded; + uint8_t sensor_requested; +}; + +static constexpr int16_t RANGE_MIN = -32768; +static constexpr int16_t RANGE_MAX = +32767; +static constexpr int16_t NORMAL_MIN = -32768; +static constexpr int16_t NORMAL_MAX = +32767; +static constexpr int16_t TEMPERATURE_ABS_ZERO = -273; + +static constexpr uint8_t RECORDED_SUPPORTED = (1U << 0); +static constexpr uint8_t LOW_HIGH_DETECT = (1U << 1); + +template +constexpr int16_t safe_range_max(const T &a) { + static_assert(sizeof(int16_t) <= sizeof(T), "T"); + return (a > static_cast(INT16_MAX)) ? INT16_MAX : static_cast(a); +} + +template +constexpr int16_t safe_range_min(const T &a) { + static_assert(sizeof(int16_t) <= sizeof(T), "T"); + return (a < static_cast(INT16_MIN)) ? INT16_MIN : static_cast(a); +} +} // namespace rdm +} // namespace sensor + + +class RDMSensor { +public: + RDMSensor(const uint8_t nSensor) : m_nSensor(nSensor) { + DEBUG_ENTRY + + m_tRDMSensorDefintion.sensor = m_nSensor; + m_tRDMSensorDefintion.recorded_supported = rdm::sensor::RECORDED_SUPPORTED | rdm::sensor::LOW_HIGH_DETECT; + + m_tRDMSensorValues.sensor_requested = m_nSensor; + m_tRDMSensorValues.lowest_detected = rdm::sensor::RANGE_MAX; + m_tRDMSensorValues.highest_detected = rdm::sensor::RANGE_MIN; + + DEBUG_EXIT + } + + virtual ~RDMSensor() = default; + +public: + void SetType(const uint8_t nType) { + m_tRDMSensorDefintion.type = nType; + } + + void SetUnit(const uint8_t nUnit) { + m_tRDMSensorDefintion.unit = nUnit; + } + + void SetPrefix(const uint8_t nPrefix) { + m_tRDMSensorDefintion.prefix = nPrefix; + } + + void SetRangeMin(const int16_t nRangeMin) { + m_tRDMSensorDefintion.range_min = nRangeMin; + } + + void SetRangeMax(const int16_t nRangeMax) { + m_tRDMSensorDefintion.range_max = nRangeMax; + } + + void SetNormalMin(const int16_t nNormalMin) { + m_tRDMSensorDefintion.normal_min = nNormalMin; + } + + void SetNormalMax(const int16_t nNormalMax) { + m_tRDMSensorDefintion.normal_max = nNormalMax; + } + + void SetDescription(const char *pDescription) { + DEBUG_ENTRY + + assert(pDescription != nullptr); + uint32_t i; + + for (i = 0; i < 32 && pDescription[i] != 0; i++) { + m_tRDMSensorDefintion.description[i] = pDescription[i]; + } + + m_tRDMSensorDefintion.nLength = static_cast(i); + + DEBUG_EXIT + } + + void Print() { + printf("%d [%.*s]\n", m_tRDMSensorDefintion.sensor, m_tRDMSensorDefintion.nLength, m_tRDMSensorDefintion.description); + printf(" RangeMin %d\n", m_tRDMSensorDefintion.range_min); + printf(" RangeMax %d\n", m_tRDMSensorDefintion.range_max); + printf(" NormalMin %d\n", m_tRDMSensorDefintion.normal_min); + printf(" NormalMax %d\n", m_tRDMSensorDefintion.normal_max); + } + + uint8_t GetSensor() const { + return m_nSensor; + } + + const struct rdm::sensor::Defintion* GetDefintion() { + return &m_tRDMSensorDefintion; + } + + const struct rdm::sensor::Values *GetValues() { + DEBUG_ENTRY + const auto nValue = this->GetValue(); + + m_tRDMSensorValues.present = nValue; + m_tRDMSensorValues.lowest_detected = std::min(m_tRDMSensorValues.lowest_detected, nValue); + m_tRDMSensorValues.highest_detected = std::max(m_tRDMSensorValues.highest_detected, nValue); + + DEBUG_EXIT + return &m_tRDMSensorValues; + } + + void SetValues() { + DEBUG_ENTRY + const auto nValue = this->GetValue(); + + m_tRDMSensorValues.present = nValue; + m_tRDMSensorValues.lowest_detected = nValue; + m_tRDMSensorValues.highest_detected = nValue; + m_tRDMSensorValues.recorded = nValue; + + DEBUG_EXIT + } + + void Record() { + DEBUG_ENTRY + const auto nValue = this->GetValue(); + + m_tRDMSensorValues.present = nValue; + m_tRDMSensorValues.recorded = nValue; + m_tRDMSensorValues.lowest_detected = std::min(m_tRDMSensorValues.lowest_detected, nValue); + m_tRDMSensorValues.highest_detected = std::max(m_tRDMSensorValues.highest_detected, nValue); + + DEBUG_EXIT + } + + virtual bool Initialize()=0; + virtual int16_t GetValue()=0; + +private: + uint8_t m_nSensor; + rdm::sensor::Defintion m_tRDMSensorDefintion; + rdm::sensor::Values m_tRDMSensorValues; +}; + +#endif /* RDMSENSOR_H_ */ diff --git a/lib-rdm/include/rdmsensors.h b/lib-rdm/include/rdmsensors.h new file mode 100644 index 00000000..cea2b084 --- /dev/null +++ b/lib-rdm/include/rdmsensors.h @@ -0,0 +1,170 @@ +/** + * @file rdmsensors.h + * + */ +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RDMSENSORS_H_ +#define RDMSENSORS_H_ + +#include +#include + +#include "rdmsensor.h" + +#include "debug.h" + +#if defined (__APPLE__) || (defined (__linux__) && !defined (RASPPI)) +#else +# define RDM_SENSORS_ENABLE +#endif + +#if !defined (__APPLE__) +# define RDMSENSOR_CPU_ENABLE +#endif + +#if defined (NODE_RDMNET_LLRP_ONLY) +# undef RDM_SENSORS_ENABLE +# undef RDMSENSOR_CPU_ENABLE +#endif + +#if defined (RDMSENSOR_CPU_ENABLE) +# include "sensor/cputemperature.h" +#endif + +namespace rdm { +namespace sensors { +static constexpr auto MAX = 16; +static constexpr auto STORE = 64; ///< Configuration store in bytes +namespace devices { +static constexpr auto MAX = 8; +} // namespace devices +} // namespace sensors +} // namespace rdm + +class RDMSensors { +public: + RDMSensors() { + DEBUG_ENTRY + assert(s_pThis == nullptr); + s_pThis = this; + +#if defined (RDM_SENSORS_ENABLE) || defined (RDMSENSOR_CPU_ENABLE) + m_pRDMSensor = new RDMSensor*[rdm::sensors::MAX]; + assert(m_pRDMSensor != nullptr); + +# if defined (RDMSENSOR_CPU_ENABLE) + Add(new CpuTemperature(m_nCount)); +# endif +#endif + DEBUG_EXIT + } + + ~RDMSensors() { + DEBUG_ENTRY + for (uint32_t i = 0; i < m_nCount; i++) { + if (m_pRDMSensor[i] != nullptr) { + delete m_pRDMSensor[i]; + m_pRDMSensor[i] = nullptr; + } + } + + delete [] m_pRDMSensor; + DEBUG_EXIT + } + + bool Add(RDMSensor *pRDMSensor) { + DEBUG_ENTRY + + assert(m_pRDMSensor != nullptr); + + if (m_pRDMSensor == nullptr) { + DEBUG_EXIT + return false; + } + + if (m_nCount == rdm::sensors::MAX) { + DEBUG_EXIT + return false; + } + + assert(pRDMSensor != nullptr); + m_pRDMSensor[m_nCount++] = pRDMSensor; + + DEBUG_PRINTF("m_nCount=%u", m_nCount); + DEBUG_EXIT + return true; + } + + uint8_t GetCount() const { + return m_nCount; + } + + const struct rdm::sensor::Defintion *GetDefintion(const uint8_t nSensor) { + assert(nSensor < m_nCount); + assert(m_pRDMSensor[nSensor] != nullptr); + return m_pRDMSensor[nSensor]->GetDefintion(); + } + + const struct rdm::sensor::Values *GetValues(const uint8_t nSensor) { + assert(nSensor < m_nCount); + + assert(m_pRDMSensor[nSensor] != nullptr); + return m_pRDMSensor[nSensor]->GetValues(); + } + + void SetValues(const uint8_t nSensor) { + if (nSensor == 0xFF) { + for (uint32_t i = 0; i < m_nCount; i++) { + m_pRDMSensor[i]->SetValues(); + } + } else { + m_pRDMSensor[nSensor]->SetValues(); + } + } + + void SetRecord(const uint8_t nSensor) { + if (nSensor == 0xFF) { + for (uint32_t i = 0; i < m_nCount; i++) { + m_pRDMSensor[i]->Record(); + } + } else { + m_pRDMSensor[nSensor]->Record(); + } + } + + RDMSensor *GetSensor(uint8_t nSensor) { + return m_pRDMSensor[nSensor]; + } + + static RDMSensors* Get() { + return s_pThis; + } + +private: + RDMSensor **m_pRDMSensor { nullptr }; + uint8_t m_nCount { 0 }; + + static RDMSensors *s_pThis; +}; + +#endif /* RDMSENSORS_H_ */ diff --git a/lib-rdm/include/rdmslotinfo.h b/lib-rdm/include/rdmslotinfo.h index 5c99e65b..5bbf0c08 100644 --- a/lib-rdm/include/rdmslotinfo.h +++ b/lib-rdm/include/rdmslotinfo.h @@ -2,7 +2,7 @@ * @file rdmslotinfo.h * */ -/* Copyright (C) 2018-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-rdm/include/rdmsubdevice.h b/lib-rdm/include/rdmsubdevice.h new file mode 100644 index 00000000..32c50bef --- /dev/null +++ b/lib-rdm/include/rdmsubdevice.h @@ -0,0 +1,200 @@ +/** + * @file rdmsubdevice.h + * + */ +/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RDMSUBDEVICE_H_ +#define RDMSUBDEVICE_H_ + +#include "rdmdevice.h" +#include "rdmpersonality.h" + +struct TRDMSubDevicesInfo { + uint16_t dmx_footprint; + uint16_t dmx_start_address; + uint8_t current_personality; + uint8_t personality_count; + char aLabel[RDM_DEVICE_LABEL_MAX_LENGTH]; + uint8_t nLabelLength; + uint8_t sensor_count; +}; + +enum TRDMSubDeviceUpdateEvent { + RDM_SUBDEVICE_UPDATE_EVENT_DMX_STARTADDRESS, + RDM_SUBDEVICE_UPDATE_EVENT_PERSONALITY +}; + +class RDMSubDevice { +public: + RDMSubDevice(const char* pLabel, uint16_t nDmxStartAddress = 1, uint8_t nPersonalityCurrent = 1): + m_nDmxStartAddressFactoryDefault(nDmxStartAddress), + m_nCurrentPersonalityFactoryDefault(nPersonalityCurrent) + { + for (uint32_t i = 0; (i < RDM_DEVICE_LABEL_MAX_LENGTH) && pLabel[i] != 0; i++) { + m_aLabelFactoryDefault[i] = pLabel[i]; + } + + SetLabel(pLabel); + + m_tSubDevicesInfo.dmx_start_address = nDmxStartAddress; + m_tSubDevicesInfo.current_personality = nPersonalityCurrent; + + m_tSubDevicesInfo.sensor_count = 0; + m_tSubDevicesInfo.personality_count = 0; + + m_nCheckSum = CalculateChecksum(); + } + + virtual ~RDMSubDevice() = default; + + void SetDmxStartAddress(uint16_t nDmxStartAddress) { + m_tSubDevicesInfo.dmx_start_address = nDmxStartAddress; + UpdateEvent(RDM_SUBDEVICE_UPDATE_EVENT_DMX_STARTADDRESS); + } + + uint16_t GetDmxStartAddress() const { + return m_tSubDevicesInfo.dmx_start_address; + } + + uint8_t GetPersonalityCurrent() const { + return m_tSubDevicesInfo.current_personality; + } + + void SetPersonalityCurrent(uint8_t nCurrent) { + m_tSubDevicesInfo.current_personality = nCurrent; + } + + void GetLabel(struct TRDMDeviceInfoData* pInfoData) { + assert(pInfoData != nullptr); + + pInfoData->data = m_tSubDevicesInfo.aLabel; + pInfoData->length = m_tSubDevicesInfo.nLabelLength; + } + + void SetLabel(const char *pLabel) { + assert(pLabel != nullptr); + uint32_t i; + + for (i = 0; (i < RDM_DEVICE_LABEL_MAX_LENGTH) && (pLabel[i] != 0); i++) { + m_tSubDevicesInfo.aLabel[i] = pLabel[i]; + } + + m_tSubDevicesInfo.nLabelLength = static_cast(i); + } + + void SetLabel(const char *pLabel, uint8_t nLabelLength) { + assert(pLabel != nullptr); + uint32_t i; + + for (i = 0; (i < RDM_DEVICE_LABEL_MAX_LENGTH) && (i < nLabelLength); i++) { + m_tSubDevicesInfo.aLabel[i] = pLabel[i]; + } + + m_tSubDevicesInfo.nLabelLength = static_cast(i); + } + + struct TRDMSubDevicesInfo* GetInfo() { + return &m_tSubDevicesInfo; + } + + RDMPersonality *GetPersonality(uint8_t nPersonality) { + assert(nPersonality != 0); + assert(nPersonality <= m_tSubDevicesInfo.personality_count); + + return m_pRDMPersonalities[nPersonality - 1]; + } + + uint8_t GetPersonalityCount() const { + return m_tSubDevicesInfo.personality_count; + } + + uint16_t GetDmxFootPrint() const { + return m_tSubDevicesInfo.dmx_footprint; + } + + bool GetFactoryDefaults() { + if (m_IsFactoryDefaults) { + if (m_nCheckSum != CalculateChecksum()) { + m_IsFactoryDefaults = false; + } + } + + return m_IsFactoryDefaults; + } + + void SetFactoryDefaults() { + if (m_IsFactoryDefaults) { + return; + } + + SetLabel(m_aLabelFactoryDefault); + + m_tSubDevicesInfo.dmx_start_address = m_nDmxStartAddressFactoryDefault; + m_tSubDevicesInfo.current_personality = m_nCurrentPersonalityFactoryDefault; + + m_IsFactoryDefaults = true; + } + + virtual bool Initialize()=0; + virtual void Start()= 0; + virtual void Stop()= 0; + virtual void Data(const uint8_t *pDdata, uint32_t nLength)=0; + +protected: + void SetDmxFootprint(uint16_t nDmxFootprint) { + m_tSubDevicesInfo.dmx_footprint = nDmxFootprint; + } + + void SetPersonalities(RDMPersonality **pRDMPersonalities, uint8_t nPersonalityCount) { + assert(pRDMPersonalities != nullptr); + + m_tSubDevicesInfo.personality_count = nPersonalityCount; + m_pRDMPersonalities = pRDMPersonalities; + + UpdateEvent(RDM_SUBDEVICE_UPDATE_EVENT_PERSONALITY); + } + +private: + virtual void UpdateEvent([[maybe_unused]] TRDMSubDeviceUpdateEvent tUpdateEvent) {} + uint16_t CalculateChecksum() { + uint16_t nChecksum = m_tSubDevicesInfo.dmx_start_address; + nChecksum = static_cast(nChecksum + m_tSubDevicesInfo.current_personality); + + for (uint32_t i = 0; i < m_tSubDevicesInfo.nLabelLength; i++) { + nChecksum = static_cast(nChecksum + m_tSubDevicesInfo.aLabel[i]); + } + + return nChecksum; + } + +private: + RDMPersonality **m_pRDMPersonalities { nullptr }; + bool m_IsFactoryDefaults { true }; + uint16_t m_nCheckSum { 0 }; + uint16_t m_nDmxStartAddressFactoryDefault; + uint8_t m_nCurrentPersonalityFactoryDefault; + TRDMSubDevicesInfo m_tSubDevicesInfo; + char m_aLabelFactoryDefault[RDM_DEVICE_LABEL_MAX_LENGTH]; +}; + +#endif /* RDMSUBDEVICE_H_ */ diff --git a/lib-rdm/include/rdmsubdevices.h b/lib-rdm/include/rdmsubdevices.h new file mode 100644 index 00000000..cb08b5dd --- /dev/null +++ b/lib-rdm/include/rdmsubdevices.h @@ -0,0 +1,248 @@ +/** + * @file rdmsubdevices.h + * + */ +/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RDMSUBDEVICES_H_ +#define RDMSUBDEVICES_H_ + +#include +#include + +#include "rdmsubdevice.h" + +#ifndef NDEBUG +# include "subdevice/rdmsubdevicedummy.h" +#endif + +#include "rdmpersonality.h" + +#include "debug.h" + +#if defined (NODE_RDMNET_LLRP_ONLY) +# undef CONFIG_RDM_ENABLE_SUBDEVICES +#endif + +namespace rdm { +namespace subdevices { +static constexpr auto MAX = 8; +static constexpr auto STORE = 96; ///< Configuration store in bytes +} // namespace subdevices +} // namespace rdm + +class RDMSubDevices { +public: + RDMSubDevices() { + DEBUG_ENTRY + assert(s_pThis == nullptr); + s_pThis = this; + +#if defined(CONFIG_RDM_ENABLE_SUBDEVICES) + m_pRDMSubDevice = new RDMSubDevice*[rdm::subdevices::MAX]; + assert(m_pRDMSubDevice != nullptr); + +# ifndef NDEBUG + Add(new RDMSubDeviceDummy); +# endif +#endif + DEBUG_EXIT + } + + ~RDMSubDevices() { + DEBUG_ENTRY + for (unsigned i = 0; i < m_nCount; i++) { + delete m_pRDMSubDevice[i]; + m_pRDMSubDevice[i] = nullptr; + } + + delete [] m_pRDMSubDevice; + + m_nCount = 0; + DEBUG_EXIT + } + +#undef UNUSED +#if defined (CONFIG_RDM_ENABLE_SUBDEVICES) +# define UNUSED +#else +# define UNUSED [[maybe_unused]] +#endif + + bool Add(UNUSED RDMSubDevice *pRDMSubDevice) { + DEBUG_ENTRY +#if defined(CONFIG_RDM_ENABLE_SUBDEVICES) + assert(m_pRDMSubDevice != nullptr); + + if (m_pRDMSubDevice == nullptr) { + return false; + } + + if (m_nCount == rdm::subdevices::MAX) { + DEBUG_EXIT + return false; + } + + assert(pRDMSubDevice != nullptr); + m_pRDMSubDevice[m_nCount++] = pRDMSubDevice; +#endif + DEBUG_EXIT + return true; + } + + uint16_t GetCount() const { + return m_nCount; + } + + struct TRDMSubDevicesInfo *GetInfo(const uint16_t nSubDevice) { + assert((nSubDevice != 0) && (nSubDevice <= m_nCount)); + assert(m_pRDMSubDevice[nSubDevice - 1] != nullptr); + return m_pRDMSubDevice[nSubDevice - 1]->GetInfo(); + } + + uint16_t GetDmxFootPrint(const uint16_t nSubDevice) { + assert((nSubDevice != 0) && (nSubDevice <= m_nCount)); + assert(m_pRDMSubDevice[nSubDevice - 1] != nullptr); + return m_pRDMSubDevice[nSubDevice - 1]->GetDmxFootPrint(); + } + + RDMPersonality *GetPersonality(const uint16_t nSubDevice, const uint8_t nPersonality) { + assert((nSubDevice != 0) && (nSubDevice <= m_nCount)); + assert(m_pRDMSubDevice[nSubDevice - 1] != nullptr); + return m_pRDMSubDevice[nSubDevice - 1]->GetPersonality(nPersonality); + } + + uint8_t GetPersonalityCount(const uint16_t nSubDevice) { + assert((nSubDevice != 0) && (nSubDevice <= m_nCount)); + assert(m_pRDMSubDevice[nSubDevice - 1] != nullptr); + return m_pRDMSubDevice[nSubDevice - 1]->GetPersonalityCount(); + } + + uint8_t GetPersonalityCurrent(const uint16_t nSubDevice) { + assert((nSubDevice != 0) && (nSubDevice <= m_nCount)); + assert(m_pRDMSubDevice[nSubDevice - 1] != nullptr); + return m_pRDMSubDevice[nSubDevice - 1]->GetPersonalityCurrent(); + } + + void SetPersonalityCurrent(const uint16_t nSubDevice, const uint8_t nPersonality) { + assert((nSubDevice != 0) && (nSubDevice <= m_nCount)); + assert(m_pRDMSubDevice[nSubDevice - 1] != nullptr); + m_pRDMSubDevice[nSubDevice - 1]->SetPersonalityCurrent(nPersonality); + } + + // E120_DEVICE_LABEL 0x0082 + void GetLabel(const uint16_t nSubDevice, struct TRDMDeviceInfoData* pInfoData) { + assert((nSubDevice != 0) && (nSubDevice <= m_nCount)); + assert(pInfoData != nullptr); + + assert(m_pRDMSubDevice[nSubDevice - 1] != nullptr); + m_pRDMSubDevice[nSubDevice - 1]->GetLabel(pInfoData); + } + + void SetLabel(const uint16_t nSubDevice, const char *pLabel, uint8_t nLabelLength) { + assert((nSubDevice != 0) && (nSubDevice <= m_nCount)); + assert(pLabel != nullptr); + + assert(m_pRDMSubDevice[nSubDevice - 1] != nullptr); + m_pRDMSubDevice[nSubDevice - 1]->SetLabel(pLabel,nLabelLength); + } + + // E120_FACTORY_DEFAULTS 0x0090 + bool GetFactoryDefaults() { + for (uint32_t i = 0; i < m_nCount; i++) { + if (m_pRDMSubDevice[i] != nullptr) { + if (!m_pRDMSubDevice[i]->GetFactoryDefaults()) { + return false; + } + } + } + + return true; + } + + void SetFactoryDefaults() { + for (uint32_t i = 0; i < m_nCount; i++) { + if (m_pRDMSubDevice[i] != nullptr) { + m_pRDMSubDevice[i]->SetFactoryDefaults(); + } + } + } + + // E120_DMX_START_ADDRESS 0x00F0 + uint16_t GetDmxStartAddress(const uint16_t nSubDevice) { + assert((nSubDevice != 0) && (nSubDevice <= m_nCount)); + assert(m_pRDMSubDevice[nSubDevice - 1] != nullptr); + return m_pRDMSubDevice[nSubDevice - 1]->GetDmxStartAddress(); + } + + void SetDmxStartAddress(const uint16_t nSubDevice, const uint16_t nDmxStartAddress) { + assert((nSubDevice != 0) && (nSubDevice <= m_nCount)); + assert(m_pRDMSubDevice[nSubDevice - 1] != nullptr); + m_pRDMSubDevice[nSubDevice - 1]->SetDmxStartAddress(nDmxStartAddress); + } + + + void Start() { + DEBUG_ENTRY + for (uint32_t i = 0; i < m_nCount; i++) { + if (m_pRDMSubDevice[i] != nullptr) { + m_pRDMSubDevice[i]->Start(); + } + } + DEBUG_EXIT + } + + void Stop() { + DEBUG_ENTRY + for (uint32_t i = 0; i < m_nCount; i++) { + if (m_pRDMSubDevice[i] != nullptr) { + m_pRDMSubDevice[i]->Stop(); + } + } + DEBUG_ENTRY + } + + void SetData(const uint8_t *pData, const uint32_t nLength) { + for (uint32_t i = 0; i < m_nCount; i++) { + if (m_pRDMSubDevice[i] != nullptr) { + if (nLength >= (static_cast(m_pRDMSubDevice[i]->GetDmxStartAddress() + m_pRDMSubDevice[i]->GetDmxFootPrint()) - 1U)) { + m_pRDMSubDevice[i]->Data(pData, nLength); + } + } + } + } + + static RDMSubDevices* Get() { + return s_pThis; + } + +private: + RDMSubDevice **m_pRDMSubDevice { nullptr }; + uint16_t m_nCount { 0 }; + + static RDMSubDevices *s_pThis; +}; + +#if defined (UNUSED) +# undef UNUSED +#endif +#endif /* RDMSUBDEVICES_H_ */ diff --git a/lib-rdmdiscovery/include/rdmtod.h b/lib-rdm/include/rdmtod.h similarity index 94% rename from lib-rdmdiscovery/include/rdmtod.h rename to lib-rdm/include/rdmtod.h index de0c09bb..04e1ecf3 100755 --- a/lib-rdmdiscovery/include/rdmtod.h +++ b/lib-rdm/include/rdmtod.h @@ -2,7 +2,7 @@ * @file rdmtod.h * */ -/* Copyright (C) 2017-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ # include #endif -#include "rdm.h" +#include "rdmconst.h" #include "debug.h" @@ -61,7 +61,7 @@ class RDMTod { } } - ~RDMTod() {} + ~RDMTod() = default; void Reset() { for (uint32_t i = 0; i < m_nEntries; i++) { @@ -105,7 +105,7 @@ class RDMTod { void Copy(uint8_t *pTable) { DEBUG_ENTRY - DEBUG_PRINTF("m_nEntries=%u", m_nEntries); + DEBUG_PRINTF("m_nEntries=%u", static_cast(m_nEntries)); assert(pTable != nullptr); const auto *pSrc = reinterpret_cast(m_Tod); @@ -208,13 +208,13 @@ class RDMTod { return (mutes & (1U << shift)) == (1U << shift); } - void Dump(__attribute__((unused)) uint32_t nCount) { + void Dump([[maybe_unused]] uint32_t nCount) { #ifndef NDEBUG if (nCount > rdmtod::TOD_TABLE_SIZE) { nCount = rdmtod::TOD_TABLE_SIZE; } - printf("[%u]\n", nCount); + printf("[%u]\n", static_cast(nCount)); for (uint32_t i = 0 ; i < nCount; i++) { printf("%.2x%.2x:%.2x%.2x%.2x%.2x\n", m_Tod[i].uid[0], m_Tod[i].uid[1], m_Tod[i].uid[2], m_Tod[i].uid[3], m_Tod[i].uid[4], m_Tod[i].uid[5]); } diff --git a/lib-rdmsensor/include/cputemperature.h b/lib-rdm/include/sensor/cputemperature.h old mode 100644 new mode 100755 similarity index 94% rename from lib-rdmsensor/include/cputemperature.h rename to lib-rdm/include/sensor/cputemperature.h index b25b3578..66e2aff9 --- a/lib-rdmsensor/include/cputemperature.h +++ b/lib-rdm/include/sensor/cputemperature.h @@ -2,7 +2,7 @@ * @file cputemperature.h * */ -/* Copyright (C) 2018-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -31,6 +31,7 @@ #include "rdmsensor.h" #include "rdm_e120.h" #include "hardware.h" + #include "debug.h" class CpuTemperature final: public RDMSensor { @@ -48,7 +49,7 @@ class CpuTemperature final: public RDMSensor { bool Initialize() override { DEBUG_ENTRY - #if defined (__CYGWIN__) || defined (__APPLE__) + #if defined (__APPLE__) DEBUG_EXIT return false; #else diff --git a/lib-rdmsubdevice/include/rdmsubdevicedummy.h b/lib-rdm/include/subdevice/rdmsubdevicedummy.h old mode 100644 new mode 100755 similarity index 100% rename from lib-rdmsubdevice/include/rdmsubdevicedummy.h rename to lib-rdm/include/subdevice/rdmsubdevicedummy.h diff --git a/lib-dmx/src/emac/dmxconfigudp.cpp b/lib-rdm/src/controller/rdm.cpp old mode 100644 new mode 100755 similarity index 84% rename from lib-dmx/src/emac/dmxconfigudp.cpp rename to lib-rdm/src/controller/rdm.cpp index aaf1e8ca..547bd02a --- a/lib-dmx/src/emac/dmxconfigudp.cpp +++ b/lib-rdm/src/controller/rdm.cpp @@ -1,8 +1,8 @@ /** - * @file dmxconfigudp.cpp + * @file rdm.cpp * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -25,7 +25,8 @@ #include -#include "dmxconfigudp.h" +#include "rdm.h" +#include "dmx.h" + +uint8_t Rdm::s_TransactionNumber[dmx::config::max::PORTS]; -int32_t DmxConfigUdp::s_nHandle = -1; -char *DmxConfigUdp::s_pUdpBuffer = nullptr; diff --git a/lib-rdm/src/controller/rdmdiscovery.cpp b/lib-rdm/src/controller/rdmdiscovery.cpp new file mode 100755 index 00000000..e1a3a466 --- /dev/null +++ b/lib-rdm/src/controller/rdmdiscovery.cpp @@ -0,0 +1,615 @@ +/** + * @file rdmddiscovery.cpp + * + */ +/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include +#include + +#include "rdmdiscovery.h" +#include "hardware.h" + +#include "debug.h" + +namespace rdmdiscovery { +#ifndef NDEBUG +const static char *StateName[] = { + "IDLE", + "UNMUTE", + "MUTE", + "DISCOVERY", + "DISCOVERY_SINGLE_DEVICE", + "DUB", + "QUICKFIND", + "QUICKFIND_DISCOVERY", + "LATE_RESPONSE", + "FINISHED" +}; +#endif + +typedef union cast { + uint64_t uint; + uint8_t uid[RDM_UID_SIZE]; +} _cast; + +static _cast uuid_cast; + +static const uint8_t *convert_uid(uint64_t nUid) { + uuid_cast.uint = __builtin_bswap64(nUid << 16); + return uuid_cast.uid; +} + +#ifndef NDEBUG +static void print_uid([[maybe_unused]] const uint8_t *pUid) { + printf("%.2x%.2x:%.2x%.2x%.2x%.2x", pUid[0], pUid[1], pUid[2], pUid[3], pUid[4], pUid[5]); +} + +static void print_uid([[maybe_unused]] uint64_t nUid) { + print_uid(convert_uid(nUid)); +} +#endif + +} // namespace rdmdiscovery + +#define NEW_STATE(state, late) NewState (state, late, __LINE__); +#define SAVED_STATE() SavedState (__LINE__); + +RDMDiscovery::RDMDiscovery(const uint8_t *pUid) { + memcpy(m_Uid, pUid, RDM_UID_SIZE); + m_Message.SetSrcUid(pUid); + +#ifndef NDEBUG + printf("Uid : "); + rdmdiscovery::print_uid(m_Uid); + puts(""); +#endif +} + +uint32_t RDMDiscovery::CopyWorkingQueue(char *pOutBuffer, const uint32_t nOutBufferSize) { + const auto nSize = static_cast(nOutBufferSize); + int32_t nIndex = 0; + int32_t nLength = 0; + uint8_t pLowerBound[RDM_UID_SIZE]; + uint8_t pUpperBound[RDM_UID_SIZE]; + + while (nIndex <= m_Discovery.stack.nTop) { + memcpy(pLowerBound, rdmdiscovery::convert_uid(m_Discovery.stack.items[nIndex].nLowerBound), RDM_UID_SIZE); + memcpy(pUpperBound, rdmdiscovery::convert_uid(m_Discovery.stack.items[nIndex].nUpperBound), RDM_UID_SIZE); + + nLength += snprintf(&pOutBuffer[nLength], static_cast(nSize - nLength), + "\"%.2x%.2x:%.2x%.2x%.2x%.2x-%.2x%.2x:%.2x%.2x%.2x%.2x\",", + pLowerBound[0], pLowerBound[1], pLowerBound[2], pLowerBound[3], pLowerBound[4], pLowerBound[5], + pUpperBound[0], pUpperBound[1], pUpperBound[2], pUpperBound[3], pUpperBound[4], pUpperBound[5]); + + nIndex++; + } + + if (nLength == 0) { + return 0; + } + + pOutBuffer[nLength - 1] = '\0'; + + return static_cast(nLength - 1); +} + +bool RDMDiscovery::Full(const uint32_t nPortIndex, RDMTod *pRDMTod) { + DEBUG_ENTRY + pRDMTod->Reset(); + const auto b = Start(nPortIndex, pRDMTod, false); + DEBUG_EXIT + return b; +} + +bool RDMDiscovery::Incremental(const uint32_t nPortIndex, RDMTod *pRDMTod) { + DEBUG_ENTRY + m_Mute.nTodEntries = pRDMTod->GetUidCount(); + const auto b = Start(nPortIndex, pRDMTod, true); + DEBUG_EXIT + return b; +} + +bool RDMDiscovery::Start(const uint32_t nPortIndex, RDMTod *pRDMTod, const bool doIncremental) { + DEBUG_ENTRY + + if (m_State != rdmdiscovery::State::IDLE) { + DEBUG_PUTS("Is already running."); + DEBUG_EXIT + return false; + } + + m_nPortIndex = nPortIndex; + m_pRDMTod = pRDMTod; + + m_doIncremental = doIncremental; + m_bIsFinished = false; + + m_UnMute.nCounter = rdmdiscovery::UNMUTE_COUNTER; + m_UnMute.bCommandRunning = false; + + m_Mute.nCounter = rdmdiscovery::MUTE_COUNTER; + m_Mute.bCommandRunning = false; + + m_Discovery.stack.nTop = -1; + m_Discovery.stack.push(0x000000000000, 0xfffffffffffe); + m_Discovery.nCounter = rdmdiscovery::DISCOVERY_COUNTER; + + m_Discovery.bCommandRunning = false; + + m_DiscoverySingleDevice.nCounter = rdmdiscovery::MUTE_COUNTER; + m_DiscoverySingleDevice.bCommandRunning = false; + + m_QuikFind.nCounter = rdmdiscovery::QUIKFIND_COUNTER; + m_QuikFind.bCommandRunning = false; + + m_QuikFindDiscovery.nCounter = rdmdiscovery::QUIKFIND_DISCOVERY_COUNTER; + m_QuikFindDiscovery.bCommandRunning = false; + + NEW_STATE(rdmdiscovery::State::UNMUTE, false); + +#ifndef NDEBUG + debug.nTreeIndex = 0; +#endif + DEBUG_EXIT + return true; +} + +bool RDMDiscovery::Stop() { + DEBUG_ENTRY + + if (m_State == rdmdiscovery::State::IDLE) { + DEBUG_PUTS("Not running."); + DEBUG_EXIT + return false; + } + + m_bIsFinished = false; + + NEW_STATE(rdmdiscovery::State::IDLE, true); + + DEBUG_EXIT + return true; +} + +bool RDMDiscovery::IsValidDiscoveryResponse(uint8_t *pUid) { + uint8_t checksum[2]; + uint16_t nRdmChecksum = 6 * 0xFF; + auto bIsValid = false; + + if (m_pResponse[0] == 0xFE) { + pUid[0] = m_pResponse[8] & m_pResponse[9]; + pUid[1] = m_pResponse[10] & m_pResponse[11]; + + pUid[2] = m_pResponse[12] & m_pResponse[13]; + pUid[3] = m_pResponse[14] & m_pResponse[15]; + pUid[4] = m_pResponse[16] & m_pResponse[17]; + pUid[5] = m_pResponse[18] & m_pResponse[19]; + + checksum[0] = m_pResponse[22] & m_pResponse[23]; + checksum[1] = m_pResponse[20] & m_pResponse[21]; + + for (uint32_t i = 0; i < 6; i++) { + nRdmChecksum = static_cast(nRdmChecksum + pUid[i]); + } + + if (((nRdmChecksum >> 8) == checksum[1]) && ((nRdmChecksum & 0xFF) == checksum[0])) { + bIsValid = true; + } + +#ifndef NDEBUG + rdmdiscovery::print_uid(pUid); + printf(", checksum %.2x%.2x -> %.4x {%c}\n", checksum[1], checksum[0], nRdmChecksum, bIsValid ? 'Y' : 'N'); +#endif + } + + return bIsValid; +} + +void RDMDiscovery::SavedState([[maybe_unused]] const uint32_t nLine) { + assert(m_SavedState != m_State); +#ifndef NDEBUG + printf("State %s->%s at line %u\n", rdmdiscovery::StateName[static_cast(m_State)], rdmdiscovery::StateName[static_cast(m_SavedState)], nLine); +#endif + m_State = m_SavedState; +} + +void RDMDiscovery::NewState(const rdmdiscovery::State state, const bool doStateLateResponse, [[maybe_unused]] const uint32_t nLine) { + assert(m_State != state); + + if (doStateLateResponse && (m_State != rdmdiscovery::State::LATE_RESPONSE)) { +#ifndef NDEBUG + assert(static_cast(state) < sizeof(rdmdiscovery::StateName) / sizeof(rdmdiscovery::StateName[0])); + printf("State %s->%s [%s] at line %u\n", rdmdiscovery::StateName[static_cast(m_State)], rdmdiscovery::StateName[static_cast(rdmdiscovery::State::LATE_RESPONSE)], rdmdiscovery::StateName[static_cast(state)], nLine); +#endif + m_LateResponse.nMicros = Hardware::Get()->Micros(); + m_SavedState = state; + m_State = rdmdiscovery::State::LATE_RESPONSE; + } else { +#ifndef NDEBUG + printf("State %s->%s at line %u\n", rdmdiscovery::StateName[static_cast(m_State)], rdmdiscovery::StateName[static_cast(state)], nLine); +#endif + m_State = state; + } +} + +void RDMDiscovery::Process() { + switch (m_State) { + case rdmdiscovery::State::LATE_RESPONSE: ///< LATE_RESPONSE + m_Message.Receive(m_nPortIndex); + + if ((Hardware::Get()->Micros() - m_LateResponse.nMicros) > rdmdiscovery::LATE_RESPONSE_TIME_OUT) { + SAVED_STATE(); + } + + return; + break; + case rdmdiscovery::State::UNMUTE: ///< UNMUTE + if (m_UnMute.nCounter == 0) { + m_UnMute.nCounter = rdmdiscovery::UNMUTE_COUNTER; + m_UnMute.bCommandRunning = false; + + if (m_doIncremental) { + NEW_STATE(rdmdiscovery::State::MUTE, false); + return; + } + + NEW_STATE(rdmdiscovery::State::DISCOVERY, false); + return; + } + + if (!m_UnMute.bCommandRunning) { + m_Message.SetPortID(static_cast(1 + m_nPortIndex)); + m_Message.SetDstUid(UID_ALL); + m_Message.SetCc(E120_DISCOVERY_COMMAND); + m_Message.SetPid(E120_DISC_UN_MUTE); + m_Message.SetPd(nullptr, 0); + m_Message.Send(m_nPortIndex); + + m_UnMute.nMicros = Hardware::Get()->Micros(); + m_UnMute.bCommandRunning = true; + return; + } + + m_Message.Receive(m_nPortIndex); + + if ((Hardware::Get()->Micros() - m_UnMute.nMicros) > rdmdiscovery::RECEIVE_TIME_OUT) { + assert(m_UnMute.nCounter > 0); + m_UnMute.nCounter--; + m_UnMute.bCommandRunning = false; + } + + return; + break; + case rdmdiscovery::State::MUTE: ///< MUTE + if (m_Mute.nTodEntries == 0) { + m_Mute.bCommandRunning = false; + NEW_STATE(rdmdiscovery::State::DISCOVERY, false); + return; + } + + if (m_Mute.nCounter == 0) { + m_Mute.nCounter = rdmdiscovery::MUTE_COUNTER; + m_Mute.bCommandRunning = false; +#ifndef NDEBUG + printf("Device is gone ");rdmdiscovery::print_uid(m_Mute.uid); puts(""); +#endif + m_pRDMTod->Delete(m_Mute.uid); + + if (m_Mute.nTodEntries > 0) { + m_Mute.nTodEntries--; + } + + return; + } + + if (!m_Mute.bCommandRunning) { + assert(m_Mute.nTodEntries > 0); + m_pRDMTod->CopyUidEntry(m_Mute.nTodEntries - 1, m_Mute.uid); + + m_Message.SetPortID(static_cast(1 + m_nPortIndex)); + m_Message.SetDstUid(m_Mute.uid); + m_Message.SetCc(E120_DISCOVERY_COMMAND); + m_Message.SetPid(E120_DISC_MUTE); + m_Message.SetPd(nullptr, 0); + m_Message.Send(m_nPortIndex); + + m_Mute.nMicros = Hardware::Get()->Micros(); + m_Mute.bCommandRunning = true; + return; + } + + m_pResponse = const_cast(m_Message.Receive(m_nPortIndex)); + + if (m_pResponse != nullptr) { + assert(m_Mute.nTodEntries > 0); + m_Mute.nTodEntries--; + m_Mute.bCommandRunning = false; + return; + } + + if ((Hardware::Get()->Micros() - m_Mute.nMicros) > rdmdiscovery::RECEIVE_TIME_OUT) { + assert(m_Mute.nCounter > 0); + m_Mute.nCounter--; + m_Message.Send(m_nPortIndex); + m_Mute.nMicros = Hardware::Get()->Micros(); + } + + return; + break; + case rdmdiscovery::State::DISCOVERY: ///< DISCOVERY + if (m_Discovery.bCommandRunning) { + m_pResponse = const_cast(m_Message.Receive(m_nPortIndex)); + + if ((m_pResponse != nullptr) || (m_Discovery.nCounter == 0)) { + m_Discovery.bCommandRunning = false; + NEW_STATE(rdmdiscovery::State::DUB, false); + return; + } + + if ((Hardware::Get()->Micros() - m_Discovery.nMicros) > rdmdiscovery::RECEIVE_TIME_OUT) { + assert(m_Discovery.nCounter > 0); + m_Discovery.nCounter--; + m_Message.Send(m_nPortIndex); + m_Discovery.nMicros = Hardware::Get()->Micros(); + } + + return; + } + + if (!m_Discovery.stack.pop(m_Discovery.nLowerBound, m_Discovery.nUpperBound)) { + m_Discovery.bCommandRunning = false; + NEW_STATE(rdmdiscovery::State::FINISHED, true); + return; + } + +#ifndef NDEBUG + debug.tree[debug.nTreeIndex].nLowerBound = m_Discovery.nLowerBound; + debug.tree[debug.nTreeIndex++].nUpperBound = m_Discovery.nUpperBound; +#endif + + if (m_Discovery.nLowerBound == m_Discovery.nUpperBound) { + m_QuikFindDiscovery.bCommandRunning = false; + NEW_STATE(rdmdiscovery::State::DISCOVERY_SINGLE_DEVICE, true); + return; + } + + memcpy(m_Discovery.pdl[0], rdmdiscovery::convert_uid(m_Discovery.nLowerBound), RDM_UID_SIZE); + memcpy(m_Discovery.pdl[1], rdmdiscovery::convert_uid(m_Discovery.nUpperBound), RDM_UID_SIZE); + +#ifndef NDEBUG + printf("DISC_UNIQUE_BRANCH -> "); rdmdiscovery::print_uid(m_Discovery.pdl[0]); printf(" "); rdmdiscovery::print_uid(m_Discovery.pdl[1]); puts(""); +#endif + + m_Message.SetDstUid(UID_ALL); + m_Message.SetCc(E120_DISCOVERY_COMMAND); + m_Message.SetPid(E120_DISC_UNIQUE_BRANCH); + m_Message.SetPd(reinterpret_cast(m_Discovery.pdl), 2 * RDM_UID_SIZE); + m_Message.Send(m_nPortIndex); + + m_Discovery.nCounter = rdmdiscovery::DISCOVERY_COUNTER; + m_Discovery.nMicros = Hardware::Get()->Micros(); + m_Discovery.bCommandRunning = true; + + return; + break; + case rdmdiscovery::State::DISCOVERY_SINGLE_DEVICE: ///< DISCOVERY_SINGLE_DEVICE + if (m_DiscoverySingleDevice.nCounter == 0) { + m_DiscoverySingleDevice.nCounter = rdmdiscovery::QUIKFIND_DISCOVERY_COUNTER; + m_DiscoverySingleDevice.bCommandRunning = false; + NEW_STATE(rdmdiscovery::State::DISCOVERY, true); + return; + } + + if (!m_DiscoverySingleDevice.bCommandRunning) { + memcpy(m_Discovery.uid, rdmdiscovery::convert_uid(m_Discovery.nLowerBound), RDM_UID_SIZE); + + m_Message.SetCc(E120_DISCOVERY_COMMAND); + m_Message.SetPid(E120_DISC_MUTE); + m_Message.SetDstUid(m_Discovery.uid); + m_Message.SetPd(nullptr, 0); + m_Message.Send(m_nPortIndex); + + m_DiscoverySingleDevice.nMicros = Hardware::Get()->Micros(); + m_DiscoverySingleDevice.bCommandRunning = true; + return; + } + + m_pResponse = const_cast(m_Message.Receive(m_nPortIndex)); + + if (m_pResponse != nullptr) { + const auto pResponse = reinterpret_cast(m_pResponse); + + if ((pResponse->command_class == E120_DISCOVERY_COMMAND_RESPONSE) && (memcmp(m_Discovery.uid, pResponse->source_uid, RDM_UID_SIZE) == 0)) { + m_pRDMTod->AddUid(m_Discovery.uid); +#ifndef NDEBUG + printf("AddUid : "); + rdmdiscovery::print_uid(m_Discovery.uid); + puts(""); +#endif + + m_DiscoverySingleDevice.nCounter = rdmdiscovery::QUIKFIND_DISCOVERY_COUNTER; + m_DiscoverySingleDevice.bCommandRunning = false; + NEW_STATE(rdmdiscovery::State::DISCOVERY, false); + } + + return; + } + + if ((Hardware::Get()->Micros() - m_DiscoverySingleDevice.nMicros) > rdmdiscovery::RECEIVE_TIME_OUT) { + assert(m_Mute.nCounter > 0); + m_DiscoverySingleDevice.nCounter--; + m_Message.Send(m_nPortIndex); + m_DiscoverySingleDevice.nMicros = Hardware::Get()->Micros(); + } + + return; + break; + case rdmdiscovery::State::DUB: ///< DUB + if (m_pResponse == nullptr) { +#ifndef NDEBUG + puts("No responses"); +#endif + NEW_STATE(rdmdiscovery::State::DISCOVERY, false); + return; + } + + if (IsValidDiscoveryResponse(m_QuikFind.uid)) { + NEW_STATE(rdmdiscovery::State::QUICKFIND, true); + return; + } + + m_Discovery.nMidPosition = ((m_Discovery.nLowerBound & (0x0000800000000000 - 1)) + (m_Discovery.nUpperBound & (0x0000800000000000 - 1))) / 2 + + (m_Discovery.nUpperBound & (0x0000800000000000) ? 0x0000400000000000 : 0 ) + + (m_Discovery.nLowerBound & (0x0000800000000000) ? 0x0000400000000000 : 0 ); + + + m_Discovery.stack.push(m_Discovery.nLowerBound, m_Discovery.nMidPosition); + m_Discovery.stack.push(m_Discovery.nMidPosition + 1, m_Discovery.nUpperBound); + + NEW_STATE(rdmdiscovery::State::DISCOVERY, true); + break; + case rdmdiscovery::State::QUICKFIND: ///< QUICKFIND + if (m_QuikFind.nCounter == 0) { + m_QuikFind.bCommandRunning = false; + NEW_STATE(rdmdiscovery::State::QUICKFIND_DISCOVERY, false); + return; + } + + if (!m_QuikFind.bCommandRunning) { +#ifndef NDEBUG + printf("QuickFind : "); + rdmdiscovery::print_uid(m_QuikFind.uid); + puts(""); +#endif + + m_Message.SetCc(E120_DISCOVERY_COMMAND); + m_Message.SetPid(E120_DISC_MUTE); + m_Message.SetDstUid(m_QuikFind.uid); + m_Message.SetPd(nullptr, 0); + m_Message.Send(m_nPortIndex); + + m_QuikFind.nCounter = rdmdiscovery::QUIKFIND_COUNTER; + m_QuikFind.nMicros = Hardware::Get()->Micros(); + m_QuikFind.bCommandRunning = true; + return; + } + + m_pResponse = const_cast(m_Message.Receive(m_nPortIndex)); + + if ((m_pResponse != nullptr)) { + const auto pResponse = reinterpret_cast(m_pResponse); + + if ((pResponse->command_class != E120_DISCOVERY_COMMAND_RESPONSE) || ((static_cast((pResponse->param_id[0] << 8) + pResponse->param_id[1])) != E120_DISC_MUTE)) { + puts("QUICKFIND invalid response"); + //assert(0); + return; + } + + if ((pResponse->command_class == E120_DISCOVERY_COMMAND_RESPONSE) && (memcmp(m_QuikFind.uid, pResponse->source_uid, RDM_UID_SIZE) == 0)) { + m_pRDMTod->AddUid(m_QuikFind.uid); +#ifndef NDEBUG + printf("AddUid : "); + rdmdiscovery::print_uid(m_QuikFind.uid); + puts(""); +#endif + } + + m_QuikFind.nCounter = rdmdiscovery::QUIKFIND_COUNTER; + m_QuikFind.bCommandRunning = false; + NEW_STATE(rdmdiscovery::State::QUICKFIND_DISCOVERY, false); + return; + } + + if ((Hardware::Get()->Micros() - m_QuikFind.nMicros) > rdmdiscovery::RECEIVE_TIME_OUT) { + assert(m_QuikFind.nCounter > 0); + m_QuikFind.nCounter--; + m_QuikFind.bCommandRunning = false; + } + + return; + break; + case rdmdiscovery::State::QUICKFIND_DISCOVERY: ///< QUICKFIND_DISCOVERY + if (m_QuikFindDiscovery.nCounter == 0) { + m_QuikFindDiscovery.nCounter = rdmdiscovery::QUIKFIND_DISCOVERY_COUNTER; + m_QuikFindDiscovery.bCommandRunning = false; + NEW_STATE(rdmdiscovery::State::DISCOVERY, true); + return; + } + + if (!m_QuikFindDiscovery.bCommandRunning) { + m_Message.SetDstUid(UID_ALL); + m_Message.SetCc(E120_DISCOVERY_COMMAND); + m_Message.SetPid(E120_DISC_UNIQUE_BRANCH); + m_Message.SetPd(reinterpret_cast(m_Discovery.pdl), 2 * RDM_UID_SIZE); + m_Message.Send(m_nPortIndex); + + m_QuikFindDiscovery.nMicros = Hardware::Get()->Micros(); + m_QuikFindDiscovery.bCommandRunning = true; + return; + } + + m_pResponse = const_cast(m_Message.Receive(m_nPortIndex)); + + if ((m_pResponse != nullptr) && (IsValidDiscoveryResponse(m_QuikFind.uid))) { + m_QuikFindDiscovery.nCounter = rdmdiscovery::QUIKFIND_DISCOVERY_COUNTER; + m_QuikFindDiscovery.bCommandRunning = false; + NEW_STATE(rdmdiscovery::State::QUICKFIND, true); + return; + } + + if ((m_pResponse != nullptr) && (!IsValidDiscoveryResponse(m_QuikFind.uid))) { + m_QuikFindDiscovery.nCounter = rdmdiscovery::QUIKFIND_DISCOVERY_COUNTER; + m_QuikFindDiscovery.bCommandRunning = false; + NEW_STATE(rdmdiscovery::State::DUB, false); + return; + } + + if ((Hardware::Get()->Micros() - m_QuikFindDiscovery.nMicros) > rdmdiscovery::RECEIVE_TIME_OUT) { + assert(m_QuikFind.nCounter > 0); + m_QuikFindDiscovery.nCounter--; + m_QuikFindDiscovery.bCommandRunning = false; + } + + return; + break; + case rdmdiscovery::State::FINISHED: ///< FINISHED + m_bIsFinished = true; + NEW_STATE(rdmdiscovery::State::IDLE, false); +#ifndef NDEBUG + m_pRDMTod->Dump(); + + printf("\nStack top %d\n\n", m_Discovery.stack.nDebugStackTopMax); + + for (uint32_t i = 0; i < debug.nTreeIndex; i++) { + rdmdiscovery::print_uid(debug.tree[i].nLowerBound); printf(" "); rdmdiscovery::print_uid(debug.tree[i].nUpperBound); puts(""); + } +#endif + break; + default: + assert(0); + __builtin_unreachable(); + break; + } +} diff --git a/lib-rdmnet/src/llrpdevice.cpp b/lib-rdm/src/llrp/llrpdevice.cpp old mode 100644 new mode 100755 similarity index 85% rename from lib-rdmnet/src/llrpdevice.cpp rename to lib-rdm/src/llrp/llrpdevice.cpp index 8825d1a1..e63664fb --- a/lib-rdmnet/src/llrpdevice.cpp +++ b/lib-rdm/src/llrp/llrpdevice.cpp @@ -2,7 +2,7 @@ * @file llrpdevice.cpp * */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,18 +28,20 @@ #include #include -#include "llrpdevice.h" +#include "hardware.h" -#include "llrppacket.h" - -#include "rdmmessage.h" +#include "llrp/llrpdevice.h" +#include "llrp/llrppacket.h" #include "e133.h" +#include "rdmconst.h" #include "rdm_e120.h" +#include "rdmdeviceresponder.h" +#include "rdm_message_print.h" #include "debug.h" -#if !defined(BARE_METAL) +#if defined(__linux__) || defined (__APPLE__) # define SHOW_LLRP_MESSAGE # define SHOW_RDM_MESSAGE #endif @@ -47,6 +49,7 @@ int32_t LLRPDevice::s_nHandleLLRP ; uint32_t LLRPDevice::s_nIpAddressFrom; uint8_t *LLRPDevice::s_pLLRP; +TRdmMessage LLRPDevice::s_RdmCommand; void LLRPDevice::HandleRequestMessage() { DEBUG_ENTRY @@ -56,7 +59,7 @@ void LLRPDevice::HandleRequestMessage() { const auto nLength = (static_cast((pPdu[0] & 0x0fu) << 16) | static_cast(pPdu[1] << 8) | pPdu[2]); uint8_t uid[RDM_UID_SIZE]; - CopyUID(uid); + memcpy(uid, RDMDeviceResponder::Get()->GetUID(), RDM_UID_SIZE); if (nLength > 18) { const auto nKnownUIDs = (nLength - 18) / RDM_UID_SIZE; @@ -86,7 +89,7 @@ void LLRPDevice::HandleRequestMessage() { // Root Layer PDU pReply->Common.RootLayerPDU.FlagsLength[2] = 67; - CopyCID(pReply->Common.RootLayerPDU.SenderCid); + Hardware::Get()->GetUuid(pReply->Common.RootLayerPDU.SenderCid); // LLRP PDU pReply->Common.LlrpPDU.FlagsLength[2] = 44; pReply->Common.LlrpPDU.Vector = __builtin_bswap32(VECTOR_LLRP_PROBE_REPLY); @@ -94,7 +97,7 @@ void LLRPDevice::HandleRequestMessage() { // Probe Reply PDU pReply->ProbeReplyPDU.FlagsLength[2] = 17; pReply->ProbeReplyPDU.Vector = VECTOR_PROBE_REPLY_DATA; - CopyUID(pReply->ProbeReplyPDU.UID); + memcpy(pReply->ProbeReplyPDU.UID, RDMDeviceResponder::Get()->GetUID(), RDM_UID_SIZE); Network::Get()->MacAddressCopyTo(pReply->ProbeReplyPDU.HardwareAddress); #if defined (NODE_RDMNET_LLRP_ONLY) pReply->ProbeReplyPDU.ComponentType = LLRP_COMPONENT_TYPE_NON_RDMNET; @@ -117,7 +120,7 @@ void LLRPDevice::HandleRdmCommand() { #ifdef SHOW_RDM_MESSAGE const auto *pRdmDataInNoSc = const_cast(pRDMCommand->RDMCommandPDU.RDMData); - RDMMessage::PrintNoSc(pRdmDataInNoSc); + rdm::message_print_no_sc(pRdmDataInNoSc); #endif const auto *pReply = LLRPHandleRdmCommand(pRDMCommand->RDMCommandPDU.RDMData); @@ -128,13 +131,13 @@ void LLRPDevice::HandleRdmCommand() { } uint8_t DestinationCid[16]; - memcpy(DestinationCid, pRDMCommand->Common.RootLayerPDU.SenderCid, 16); // TODO Optimize / cleanup + memcpy(DestinationCid, pRDMCommand->Common.RootLayerPDU.SenderCid, 16); const auto nMessageLength = static_cast(pReply[2] + 1); // RDM Command length without SC // Root Layer PDU pRDMCommand->Common.RootLayerPDU.FlagsLength[2] = RDM_ROOT_LAYER_LENGTH(nMessageLength); - CopyCID(pRDMCommand->Common.RootLayerPDU.SenderCid); + Hardware::Get()->GetUuid(pRDMCommand->Common.RootLayerPDU.SenderCid); // LLRP PDU pRDMCommand->Common.LlrpPDU.FlagsLength[2] = RDM_LLRP_PDU_LENGHT(nMessageLength); memcpy(pRDMCommand->Common.LlrpPDU.DestinationCid, DestinationCid, 16); @@ -145,10 +148,10 @@ void LLRPDevice::HandleRdmCommand() { const auto nLength = sizeof(struct TRootLayerPreAmble) + RDM_ROOT_LAYER_LENGTH(nMessageLength); - Network::Get()->SendTo(s_nHandleLLRP, pRDMCommand, static_cast(nLength) , llrp::device::IPV4_LLRP_RESPONSE, llrp::device::LLRP_PORT); + Network::Get()->SendTo(s_nHandleLLRP, pRDMCommand, nLength , llrp::device::IPV4_LLRP_RESPONSE, llrp::device::LLRP_PORT); #ifdef SHOW_RDM_MESSAGE - RDMMessage::Print(pReply); + rdm::message_print(pReply); #endif #ifndef NDEBUG diff --git a/lib-rdmnet/src/llrpdevicedump.cpp b/lib-rdm/src/llrp/llrpdevicedump.cpp old mode 100644 new mode 100755 similarity index 86% rename from lib-rdmnet/src/llrpdevicedump.cpp rename to lib-rdm/src/llrp/llrpdevicedump.cpp index 7bc2c360..e108d7a3 --- a/lib-rdmnet/src/llrpdevicedump.cpp +++ b/lib-rdm/src/llrp/llrpdevicedump.cpp @@ -2,7 +2,7 @@ * @file dump.cpp * */ -/* Copyright (C) 2019-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,12 +28,12 @@ #include #include -#include "llrpdevice.h" +#include "llrp/llrpdevice.h" #include "e133.h" -#include "rdm_e120.h" -#include "rdmmessage.h" +#include "rdm_e120.h" +#include "rdm_message_print.h" #include "debug.h" @@ -55,19 +55,19 @@ void LLRPDevice::DumpCommon() { for (uint32_t i = 0; i < sizeof(pCommon->RootLayerPDU.SenderCid); i++) { printf("%.02X", pCommon->RootLayerPDU.SenderCid[i]); } - printf("\n"); + puts(""); - pPdu = (uint8_t *)pCommon->LlrpPDU.FlagsLength; - nLength = ((uint32_t)((pPdu[0] & 0x0fu) << 16) | (uint32_t)(pPdu[1] << 8) | (uint32_t)pPdu[2]); + pPdu = reinterpret_cast(pCommon->LlrpPDU.FlagsLength); + nLength = (((pPdu[0] & 0x0fu) << 16) | static_cast((pPdu[1] << 8)) | static_cast(pPdu[2])); printf("LlrpPDU PDU length=%d, High 4 bits=0x%.1x\n", nLength, static_cast(pCommon->LlrpPDU.FlagsLength[0]) >> 4); printf("LlrpPDU.Vector=0x%.8x\n", __builtin_bswap32(pCommon->LlrpPDU.Vector)); printf("LlrpPDU.DestinationCid="); for (uint32_t i = 0; i < sizeof(pCommon->LlrpPDU.DestinationCid); i++) { - printf("%.02X", pCommon->LlrpPDU.DestinationCid[i]); + printf("%.02X", pCommon->LlrpPDU.DestinationCid[i]); } - printf("\n"); + puts(""); printf("LlrpPDU.TransactionNumber=0x%.4x\n", __builtin_bswap32(pCommon->LlrpPDU.TransactionNumber)); @@ -76,7 +76,7 @@ void LLRPDevice::DumpCommon() { auto *pRequest = reinterpret_cast(s_pLLRP); pPdu = reinterpret_cast(pRequest->ProbeRequestPDU.FlagsLength); - nLength = ((uint32_t) ((pPdu[0] & 0x0fu) << 16) | (uint32_t) (pPdu[1] << 8) | (uint32_t) pPdu[2]); + nLength = (((pPdu[0] & 0x0fu) << 16) | static_cast((pPdu[1] << 8)) | static_cast(pPdu[2])); printf("Probe Request PDU length=%d, High 4 bits=%.1x\n", nLength, static_cast(pRequest->ProbeRequestPDU.FlagsLength[0]) >> 4); printf("ProbeRequestPDU.Vector=0x%.2x\n", static_cast(pRequest->ProbeRequestPDU.Vector)); @@ -87,7 +87,7 @@ void LLRPDevice::DumpCommon() { auto *pReply = reinterpret_cast(s_pLLRP); pPdu = reinterpret_cast(pReply->ProbeReplyPDU.FlagsLength); - nLength = ((uint32_t) ((pPdu[0] & 0x0fu) << 16) | (uint32_t) (pPdu[1] << 8) | (uint32_t) pPdu[2]); + nLength = (((pPdu[0] & 0x0fu) << 16) | static_cast((pPdu[1] << 8)) | static_cast(pPdu[2])); printf("Probe Request PDU length=%d, High 4 bits=%.1x\n", nLength, static_cast(pReply->ProbeReplyPDU.FlagsLength[0]) >> 4); printf("ProbeRequestPDU.Vector=0x%.2x\n", static_cast(pReply->ProbeReplyPDU.Vector)); @@ -96,26 +96,26 @@ void LLRPDevice::DumpCommon() { for (uint32_t i = 0; i < sizeof(pReply->ProbeReplyPDU.UID); i++) { printf("%.02X", pReply->ProbeReplyPDU.UID[i]); } - printf("\n"); + puts(""); printf("ProbeReplyPDU.HardwareAddress="); for (uint32_t i = 0; i < sizeof(pReply->ProbeReplyPDU.HardwareAddress); i++) { printf("%.02X", pReply->ProbeReplyPDU.HardwareAddress[i]); } - printf("\n"); + puts(""); } break; case VECTOR_LLRP_RDM_CMD: { auto *pRDMCommand = reinterpret_cast(s_pLLRP); pPdu = reinterpret_cast(pRDMCommand->RDMCommandPDU.FlagsLength); - nLength = ((uint32_t) ((pPdu[0] & 0x0fu) << 16) | (uint32_t) (pPdu[1] << 8) | (uint32_t) pPdu[2]); + nLength = (((pPdu[0] & 0x0fu) << 16) | static_cast((pPdu[1] << 8)) | static_cast(pPdu[2])); printf("RDM Command PDU length=%d, High 4 bits=0x%.1x\n", nLength, pRDMCommand->RDMCommandPDU.FlagsLength[0] >> 4); printf("RDMCommandPDU.Vector=0x%.2x\n", pRDMCommand->RDMCommandPDU.Vector); } - break; + break; default: break; } @@ -137,5 +137,5 @@ void LLRPDevice::DumpLLRP() { printf("%.02X", pCommon->LlrpPDU.DestinationCid[i]); } - printf("\n"); + puts(""); } diff --git a/lib-rdm/src/llrp/rdmhandlere1372.cpp b/lib-rdm/src/llrp/rdmhandlere1372.cpp old mode 100644 new mode 100755 index 2882b713..b2fa97c6 --- a/lib-rdm/src/llrp/rdmhandlere1372.cpp +++ b/lib-rdm/src/llrp/rdmhandlere1372.cpp @@ -2,7 +2,7 @@ * @file rdmhandlere137.cpp * */ -/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,9 +23,14 @@ * THE SOFTWARE. */ +#if defined (DEBUG_RDM_LLRP) +# undef NDEBUG +#endif + #include #include "rdmhandler.h" +#include "rdmconst.h" #include "rdm_e120.h" #include "network.h" @@ -40,11 +45,11 @@ enum { * ANSI E1.37-2 */ -bool RDMHandler::CheckInterfaceID(__attribute__((unused)) const struct TRdmMessageNoSc *pRdmDataIn) { +bool RDMHandler::CheckInterfaceID([[maybe_unused]] const struct TRdmMessageNoSc *pRdmDataIn) { #if !defined(DMX_WORKSHOP_DEFECT) - const uint32_t nInterfaceID = (pRdmDataIn->param_data[0] << 24) + const auto nInterfaceID = static_cast((pRdmDataIn->param_data[0] << 24) + (pRdmDataIn->param_data[1] << 16) - + (pRdmDataIn->param_data[2] << 8) + pRdmDataIn->param_data[3]; + + (pRdmDataIn->param_data[2] << 8) + pRdmDataIn->param_data[3]); if (nInterfaceID != Network::Get()->GetIfIndex()) { RespondMessageNack(E120_NR_DATA_OUT_OF_RANGE); @@ -54,7 +59,7 @@ bool RDMHandler::CheckInterfaceID(__attribute__((unused)) const struct TRdmMessa return true; } -void RDMHandler::GetInterfaceList(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetInterfaceList([[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY // https://www.iana.org/assignments/arp-parameters/arp-parameters.xhtml const uint16_t nInterfaceHardwareType = 0x6; // IEEE 802 Networks @@ -77,10 +82,10 @@ void RDMHandler::GetInterfaceList(__attribute__((unused)) uint16_t nSubDevice) { DEBUG_EXIT } -void RDMHandler::GetInterfaceName(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetInterfaceName([[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY - const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); + const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (!CheckInterfaceID(pRdmDataIn)) { @@ -100,10 +105,10 @@ void RDMHandler::GetInterfaceName(__attribute__((unused)) uint16_t nSubDevice) { DEBUG_EXIT } -void RDMHandler::GetHardwareAddress(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetHardwareAddress([[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY - const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); + const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (!CheckInterfaceID(pRdmDataIn)) { @@ -123,10 +128,10 @@ void RDMHandler::GetHardwareAddress(__attribute__((unused)) uint16_t nSubDevice) DEBUG_EXIT } -void RDMHandler::GetDHCPMode(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetDHCPMode([[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY - const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); + const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (!CheckInterfaceID(pRdmDataIn)) { @@ -146,10 +151,10 @@ void RDMHandler::GetDHCPMode(__attribute__((unused)) uint16_t nSubDevice) { DEBUG_EXIT } -void RDMHandler::SetDHCPMode(__attribute__((unused)) bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::SetDHCPMode([[maybe_unused]] bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY - const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); + const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (!CheckInterfaceID(pRdmDataIn)) { @@ -164,16 +169,10 @@ void RDMHandler::SetDHCPMode(__attribute__((unused)) bool IsBroadcast, __attribu return; } - if (pRdmDataIn->param_data[4] == static_cast(network::dhcp::Mode::ACTIVE)) { - Network::Get()->SetQueuedDhcp(); - RespondMessageAck(); - - DEBUG_EXIT - return; - } + const auto mode = static_cast(pRdmDataIn->param_data[4]); - if (pRdmDataIn->param_data[4] == static_cast(network::dhcp::Mode::INACTIVE)) { - Network::Get()->SetQueuedStaticIp(); + if ((mode == network::dhcp::Mode::ACTIVE) || mode == network::dhcp::Mode::INACTIVE) { + Network::Get()->SetQueuedDhcp(mode); RespondMessageAck(); DEBUG_EXIT @@ -185,24 +184,26 @@ void RDMHandler::SetDHCPMode(__attribute__((unused)) bool IsBroadcast, __attribu DEBUG_EXIT } -void RDMHandler::GetNameServers(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetNameServers([[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY - const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); - const uint16_t nNameServerIndex = pRdmDataIn->param_data[0]; + const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); + const auto nNameServerIndex = pRdmDataIn->param_data[0]; - if (nNameServerIndex > 2) { + if ((nNameServerIndex >= Network::Get()->GetNameServers()) || (nNameServerIndex > 2)) { RespondMessageNack(E120_NR_DATA_OUT_OF_RANGE); DEBUG_EXIT return; } - // TODO The Network class does not have GetNameServers - auto *pRdmDataOut = reinterpret_cast(m_pRdmDataOut); - memset(&pRdmDataOut->param_data[1], 0, 4); + uint32_t nIpAddress = Network::Get()->GetNameServer(nNameServerIndex); + const auto *p = reinterpret_cast(&nIpAddress); + + pRdmDataOut->param_data[0] = nNameServerIndex; + memcpy(&pRdmDataOut->param_data[1], p, 4); pRdmDataOut->param_data_length = 5; @@ -211,10 +212,10 @@ void RDMHandler::GetNameServers(__attribute__((unused)) uint16_t nSubDevice) { DEBUG_EXIT } -void RDMHandler::GetZeroconf(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetZeroconf([[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY - const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); + const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (!CheckInterfaceID(pRdmDataIn)) { @@ -234,10 +235,10 @@ void RDMHandler::GetZeroconf(__attribute__((unused)) uint16_t nSubDevice) { DEBUG_EXIT } -void RDMHandler::SetZeroconf(__attribute__((unused)) bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::SetZeroconf([[maybe_unused]] bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY - const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); + const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (!CheckInterfaceID(pRdmDataIn)) { @@ -261,7 +262,7 @@ void RDMHandler::SetZeroconf(__attribute__((unused)) bool IsBroadcast, __attribu } if (pRdmDataIn->param_data[4] == 0) { - Network::Get()->SetQueuedStaticIp(); + Network::Get()->SetQueuedStaticIp(0, 0); RespondMessageAck(); DEBUG_EXIT @@ -273,10 +274,10 @@ void RDMHandler::SetZeroconf(__attribute__((unused)) bool IsBroadcast, __attribu DEBUG_EXIT } -void RDMHandler::RenewDhcp(__attribute__((unused)) bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::RenewDhcp([[maybe_unused]] bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY - const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); + const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (!CheckInterfaceID(pRdmDataIn)) { @@ -298,17 +299,17 @@ void RDMHandler::RenewDhcp(__attribute__((unused)) bool IsBroadcast, __attribute return; } - Network::Get()->EnableDhcp(); // TODO This will cause a time-out -> queued message + Network::Get()->EnableDhcp(); RespondMessageAck(); DEBUG_EXIT } -void RDMHandler::GetAddressNetmask(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetAddressNetmask([[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY - const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); + const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (!CheckInterfaceID(pRdmDataIn)) { @@ -333,10 +334,10 @@ void RDMHandler::GetAddressNetmask(__attribute__((unused)) uint16_t nSubDevice) DEBUG_EXIT } -void RDMHandler::GetStaticAddress(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetStaticAddress([[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY - const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); + const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (!CheckInterfaceID(pRdmDataIn)) { @@ -360,10 +361,10 @@ void RDMHandler::GetStaticAddress(__attribute__((unused)) uint16_t nSubDevice) { DEBUG_EXIT } -void RDMHandler::SetStaticAddress(__attribute__((unused)) bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::SetStaticAddress([[maybe_unused]] bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY - const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); + const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (pRdmDataIn->param_data_length != 9) { RespondMessageNack(E120_NR_FORMAT_ERROR); @@ -389,10 +390,10 @@ void RDMHandler::SetStaticAddress(__attribute__((unused)) bool IsBroadcast, __at DEBUG_EXIT } -void RDMHandler::ApplyConfiguration(__attribute__((unused)) bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::ApplyConfiguration([[maybe_unused]] bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY - const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); + const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (!CheckInterfaceID(pRdmDataIn)) { @@ -412,10 +413,10 @@ void RDMHandler::ApplyConfiguration(__attribute__((unused)) bool IsBroadcast, __ DEBUG_EXIT } -void RDMHandler::GetDefaultRoute(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetDefaultRoute([[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY - const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); + const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (!CheckInterfaceID(pRdmDataIn)) { @@ -438,24 +439,47 @@ void RDMHandler::GetDefaultRoute(__attribute__((unused)) uint16_t nSubDevice) { DEBUG_EXIT } -void RDMHandler::SetDefaultRoute(__attribute__((unused)) bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::SetDefaultRoute([[maybe_unused]] bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY - RespondMessageNack(E137_2_NR_ACTION_NOT_SUPPORTED); + const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); + + if (pRdmDataIn->param_data_length != 8) { + RespondMessageNack(E120_NR_FORMAT_ERROR); + + DEBUG_EXIT + return; + } + + if (!CheckInterfaceID(pRdmDataIn)) { + + DEBUG_EXIT + return; + } + + uint32_t nIpAddress; + auto *p = reinterpret_cast(&nIpAddress); + memcpy(p, &pRdmDataIn->param_data[4], 4); + + Network::Get()->SetQueuedDefaultRoute(nIpAddress); + + RespondMessageAck(); + + DEBUG_EXIT } -void RDMHandler::GetHostName(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetHostName([[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY const auto *pHostName = Network::Get()->GetHostName(); - HandleString(pHostName, static_cast(strlen(pHostName))); + HandleString(pHostName, static_cast(strlen(pHostName))); RespondMessageAck(); DEBUG_EXIT } -void RDMHandler::SetHostName(__attribute__((unused)) bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::SetHostName([[maybe_unused]] bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); @@ -476,18 +500,18 @@ void RDMHandler::SetHostName(__attribute__((unused)) bool IsBroadcast, __attribu DEBUG_EXIT } -void RDMHandler::GetDomainName(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetDomainName([[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY const auto *pDomainName = Network::Get()->GetDomainName(); - HandleString(pDomainName, static_cast(strlen(pDomainName))); + HandleString(pDomainName, static_cast(strlen(pDomainName))); RespondMessageAck(); DEBUG_EXIT } -void RDMHandler::SetDomainName(__attribute__((unused)) bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::SetDomainName([[maybe_unused]] bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY RespondMessageNack(E137_2_NR_ACTION_NOT_SUPPORTED); diff --git a/lib-rdm/src/rdmmessageprint.cpp b/lib-rdm/src/rdm_message_print.cpp similarity index 81% rename from lib-rdm/src/rdmmessageprint.cpp rename to lib-rdm/src/rdm_message_print.cpp index 83977827..a2071dc5 100644 --- a/lib-rdm/src/rdmmessageprint.cpp +++ b/lib-rdm/src/rdm_message_print.cpp @@ -1,5 +1,5 @@ /** - * @file rdmmessageprint.cpp + * @file rdm_message_print.cpp * */ /* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl @@ -26,28 +26,15 @@ #include #include #include +#include -#include "rdmmessage.h" - -#include "rdm.h" +#include "rdmconst.h" #include "rdm_e120.h" #include "debug.h" -void RDMMessage::PrintNoSc(const uint8_t *pRdmDataNoSc) { - assert(pRdmDataNoSc != nullptr); - - const auto *pData = reinterpret_cast(pRdmDataNoSc); - - uint8_t message[sizeof(struct TRdmMessage)]; - message[0] = E120_SC_RDM; - - memcpy(&message[1], pData, pData->message_length - 1U); - - Print(message); -} - -void RDMMessage::Print(const uint8_t *pRdmData) { +namespace rdm { +void message_print(const uint8_t *pRdmData) { if (pRdmData == nullptr) { DEBUG_PUTS("No RDM data"); return; @@ -87,13 +74,38 @@ void RDMMessage::Print(const uint8_t *pRdmData) { } const auto nSubDevice = static_cast((pRdmMessage->sub_device[0] << 8) + pRdmMessage->sub_device[1]); - printf(", sub-dev: %d, tn: %d, PID 0x%.2x%.2x, pdl: %d\n", nSubDevice, pRdmMessage->transaction_number, pRdmMessage->param_id[0], pRdmMessage->param_id[1], pRdmMessage->param_data_length); + printf(", sub-dev: %d, tn: %d, PID 0x%.2x%.2x, pdl: %d", nSubDevice, pRdmMessage->transaction_number, pRdmMessage->param_id[0], pRdmMessage->param_id[1], pRdmMessage->param_data_length); + + if (pRdmMessage->param_data_length != 0) { + printf(" -> "); + for (uint32_t i = 0 ; (i < 12) && (i < pRdmMessage->param_data_length) ; i++) { + printf("%.2x ", pRdmMessage->param_data[i]); + } + } + + puts(""); + } else if (pRdmData[0] == 0xFE) { for (uint32_t i = 0 ; i < 24; i++) { printf("%.2x ", pRdmData[i]); } - printf("\n"); + puts(""); } else { printf("Corrupted? RDM data [0-3]: %.2x:%.2x:%.2x:%.2x\n", pRdmData[0], pRdmData[1], pRdmData[2], pRdmData[3]); } } + +void message_print_no_sc(const uint8_t *pRdmDataNoSc) { + assert(pRdmDataNoSc != nullptr); + + const auto *pData = reinterpret_cast(pRdmDataNoSc); + + uint8_t message[sizeof(struct TRdmMessage)]; + message[0] = E120_SC_RDM; + + memcpy(&message[1], pData, pData->message_length - 1U); + + message_print(message); +} +} // namespace rdm + diff --git a/lib-rdm/src/rdmdevice.cpp b/lib-rdm/src/rdmdevice.cpp index 9df0cb0d..1b4d55a2 100644 --- a/lib-rdm/src/rdmdevice.cpp +++ b/lib-rdm/src/rdmdevice.cpp @@ -31,7 +31,6 @@ #include "rdmdevice.h" #include "rdmconst.h" -#include "rdm.h" #include "rdm_e120.h" #include "network.h" @@ -61,10 +60,17 @@ # endif #endif +RDMDevice *RDMDevice::s_pThis; + RDMDevice::RDMDevice() { DEBUG_ENTRY + assert(s_pThis == nullptr); + s_pThis = this; + + m_aUID[0] = RDMConst::MANUFACTURER_ID[0]; + m_aUID[1] = RDMConst::MANUFACTURER_ID[1]; -#if defined (NO_EMAC) +#if defined (NO_EMAC) || !defined(CONFIG_RDMDEVICE_UUID_IP) uint8_t aMacAddress[network::MAC_SIZE]; Network::Get()->MacAddressCopyTo(aMacAddress); @@ -72,28 +78,14 @@ RDMDevice::RDMDevice() { m_aUID[3] = aMacAddress[3]; m_aUID[4] = aMacAddress[4]; m_aUID[5] = aMacAddress[5]; -#else - const auto nIp = Network::Get()->GetIp(); -# if !defined(CONFIG_RDMDEVICE_REVERSE_UID) - m_aUID[5] = static_cast(nIp >> 24); - m_aUID[4] = (nIp >> 16) & 0xFF; - m_aUID[3] = (nIp >> 8) & 0xFF; - m_aUID[2] = nIp & 0xFF; -# else - m_aUID[2] = static_cast(nIp >> 24); - m_aUID[3] = (nIp >> 16) & 0xFF; - m_aUID[4] = (nIp >> 8) & 0xFF; - m_aUID[5] = nIp & 0xFF; -# endif -#endif - - m_aUID[0] = RDMConst::MANUFACTURER_ID[0]; - m_aUID[1] = RDMConst::MANUFACTURER_ID[1]; m_aSN[0] = m_aUID[5]; m_aSN[1] = m_aUID[4]; m_aSN[2] = m_aUID[3]; m_aSN[3] = m_aUID[2]; +#else + // Calculated with GetUID and GetSN +#endif m_nFactoryRootLabelLength = sizeof(DEVICE_LABEL) - 1; memcpy(m_aFactoryRootLabel, DEVICE_LABEL, m_nFactoryRootLabelLength); @@ -102,7 +94,7 @@ RDMDevice::RDMDevice() { } void RDMDevice::Print() { - printf("RDM Device configuration\n"); + puts("RDM Device configuration"); const auto nLength = static_cast(std::min(static_cast(RDM_MANUFACTURER_LABEL_MAX_LENGTH), strlen(RDMConst::MANUFACTURER_NAME))); printf(" Manufacturer Name : %.*s\n", nLength, const_cast(&RDMConst::MANUFACTURER_NAME[0])); printf(" Manufacturer ID : %.2X%.2X\n", m_aUID[0], m_aUID[1]); diff --git a/lib-rdm/src/rdmdeviceparams.cpp b/lib-rdm/src/rdmdeviceparams.cpp index 38485983..aa6644ff 100644 --- a/lib-rdm/src/rdmdeviceparams.cpp +++ b/lib-rdm/src/rdmdeviceparams.cpp @@ -2,7 +2,7 @@ * @file rdmdeviceparams.cpp * */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -30,13 +30,12 @@ #include #include -#ifndef NDEBUG -# include -#endif +#include #include #include "rdmdeviceparams.h" #include "rdmdeviceparamsconst.h" +#include "rdmdevice.h" #include "rdm_e120.h" @@ -45,12 +44,11 @@ #include "readconfigfile.h" #include "sscan.h" - #include "propertiesbuilder.h" #include "debug.h" -RDMDeviceParams::RDMDeviceParams(RDMDeviceParamsStore *pRDMDeviceParamsStore): m_pRDMDeviceParamsStore(pRDMDeviceParamsStore) { +RDMDeviceParams::RDMDeviceParams() { DEBUG_ENTRY memset(&m_Params, 0, sizeof(struct rdm::deviceparams::Params)); @@ -61,7 +59,7 @@ RDMDeviceParams::RDMDeviceParams(RDMDeviceParamsStore *pRDMDeviceParamsStore): m DEBUG_EXIT } -bool RDMDeviceParams::Load() { +void RDMDeviceParams::Load() { DEBUG_ENTRY #if !defined(DISABLE_FS) @@ -70,20 +68,15 @@ bool RDMDeviceParams::Load() { ReadConfigFile configfile(RDMDeviceParams::staticCallbackFunction, this); if (configfile.Read(RDMDeviceParamsConst::FILE_NAME)) { - if (m_pRDMDeviceParamsStore != nullptr) { - m_pRDMDeviceParamsStore->Update(&m_Params); - } + RDMDeviceParamsStore::Update(&m_Params); } else #endif - if (m_pRDMDeviceParamsStore != nullptr) { - m_pRDMDeviceParamsStore->Copy(&m_Params); - } else { - DEBUG_EXIT - return false; - } + RDMDeviceParamsStore::Copy(&m_Params); +#ifndef NDEBUG + Dump(); +#endif DEBUG_EXIT - return true; } void RDMDeviceParams::Load(const char *pBuffer, uint32_t nLength) { @@ -98,9 +91,11 @@ void RDMDeviceParams::Load(const char *pBuffer, uint32_t nLength) { config.Read(pBuffer, nLength); - assert(m_pRDMDeviceParamsStore != nullptr); - m_pRDMDeviceParamsStore->Update(&m_Params); + RDMDeviceParamsStore::Update(&m_Params); +#ifndef NDEBUG + Dump(); +#endif DEBUG_EXIT } @@ -163,31 +158,6 @@ void RDMDeviceParams::Set(RDMDevice *pRDMDevice) { } } -void RDMDeviceParams::Dump() { -#ifndef NDEBUG - printf("%s::%s \'%s\':\n", __FILE__, __FUNCTION__, RDMDeviceParamsConst::FILE_NAME); - - if (isMaskSet(rdm::deviceparams::Mask::LABEL)) { - printf(" %s=%.*s\n", RDMDeviceParamsConst::LABEL, m_Params.nDeviceRootLabelLength, m_Params.aDeviceRootLabel); - } - - if (isMaskSet(rdm::deviceparams::Mask::PRODUCT_CATEGORY)) { - printf(" %s=%.4x\n", RDMDeviceParamsConst::PRODUCT_CATEGORY, m_Params.nProductCategory); - } - - if (isMaskSet(rdm::deviceparams::Mask::PRODUCT_DETAIL)) { - printf(" %s=%.4x\n", RDMDeviceParamsConst::PRODUCT_DETAIL, m_Params.nProductDetail); - } -#endif -} - -void RDMDeviceParams::staticCallbackFunction(void *p, const char *s) { - assert(p != nullptr); - assert(s != nullptr); - - (static_cast(p))->callbackFunction(s); -} - void RDMDeviceParams::Builder(const struct rdm::deviceparams::Params *pParams, char *pBuffer, uint32_t nLength, uint32_t& nSize) { DEBUG_ENTRY @@ -196,17 +166,43 @@ void RDMDeviceParams::Builder(const struct rdm::deviceparams::Params *pParams, c if (pParams != nullptr) { memcpy(&m_Params, pParams, sizeof(struct rdm::deviceparams::Params)); } else { - assert(m_pRDMDeviceParamsStore != nullptr); - m_pRDMDeviceParamsStore->Copy(&m_Params); + RDMDeviceParamsStore::Copy(&m_Params); } PropertiesBuilder builder(RDMDeviceParamsConst::FILE_NAME, pBuffer, nLength); - builder.AddHex16(RDMDeviceParamsConst::PRODUCT_CATEGORY, m_Params.nProductCategory, isMaskSet(rdm::deviceparams::Mask::PRODUCT_CATEGORY)); - builder.AddHex16(RDMDeviceParamsConst::PRODUCT_DETAIL, m_Params.nProductDetail, isMaskSet(rdm::deviceparams::Mask::PRODUCT_DETAIL)); + const auto isProductCategory = isMaskSet(rdm::deviceparams::Mask::PRODUCT_CATEGORY); + + if (!isProductCategory) { + m_Params.nProductCategory = RDMDevice::Get()->GetProductCategory(); + } + + builder.AddHex16(RDMDeviceParamsConst::PRODUCT_CATEGORY, m_Params.nProductCategory, isProductCategory); + + const auto isProductDetail = isMaskSet(rdm::deviceparams::Mask::PRODUCT_DETAIL); + + if (!isProductDetail) { + m_Params.nProductDetail = RDMDevice::Get()->GetProductDetail(); + } + + builder.AddHex16(RDMDeviceParamsConst::PRODUCT_DETAIL, m_Params.nProductDetail, isProductDetail); nSize = builder.GetSize(); DEBUG_PRINTF("nSize=%d", nSize); DEBUG_EXIT } + +void RDMDeviceParams::staticCallbackFunction(void *p, const char *s) { + assert(p != nullptr); + assert(s != nullptr); + + (static_cast(p))->callbackFunction(s); +} + +void RDMDeviceParams::Dump() { + printf("%s::%s \'%s\':\n", __FILE__, __FUNCTION__, RDMDeviceParamsConst::FILE_NAME); + printf(" %s=%.*s\n", RDMDeviceParamsConst::LABEL, m_Params.nDeviceRootLabelLength, m_Params.aDeviceRootLabel); + printf(" %s=%.4x\n", RDMDeviceParamsConst::PRODUCT_CATEGORY, m_Params.nProductCategory); + printf(" %s=%.4x\n", RDMDeviceParamsConst::PRODUCT_DETAIL, m_Params.nProductDetail); +} diff --git a/lib-rdm/src/rdmdeviceresponder.cpp b/lib-rdm/src/rdmdeviceresponder.cpp index 9620eebf..de51f5bc 100644 --- a/lib-rdm/src/rdmdeviceresponder.cpp +++ b/lib-rdm/src/rdmdeviceresponder.cpp @@ -47,9 +47,9 @@ static constexpr char LANGUAGE[2] = { 'e', 'n' }; -RDMDeviceResponder *RDMDeviceResponder::s_pThis = nullptr; +RDMDeviceResponder *RDMDeviceResponder::s_pThis; -RDMDeviceResponder::RDMDeviceResponder(RDMPersonality **pRDMPersonalities, uint32_t nPersonalityCount) : +RDMDeviceResponder::RDMDeviceResponder(RDMPersonality **pRDMPersonalities, const uint32_t nPersonalityCount, const uint32_t nCurrentPersonality) : m_pRDMPersonalities(pRDMPersonalities) { DEBUG_ENTRY @@ -60,15 +60,18 @@ RDMDeviceResponder::RDMDeviceResponder(RDMPersonality **pRDMPersonalities, uint3 m_aLanguage[0] = LANGUAGE[0]; m_aLanguage[1] = LANGUAGE[1]; - memset(&m_tRDMDeviceInfo, 0, sizeof (struct TRDMDeviceInfo)); - memset(&m_tRDMSubDeviceInfo, 0, sizeof (struct TRDMDeviceInfo)); + memset(&m_DeviceInfo, 0, sizeof (struct rdm::device::responder::DeviceInfo)); + memset(&m_SubDeviceInfo, 0, sizeof (struct rdm::device::responder::DeviceInfo)); - m_tRDMDeviceInfo.personality_count = static_cast(nPersonalityCount); + m_DeviceInfo.personality_count = static_cast(nPersonalityCount); + m_DeviceInfo.current_personality = static_cast(nCurrentPersonality); m_pSoftwareVersion = const_cast(RDMSoftwareVersion::GetVersion()); m_nSoftwareVersionLength = static_cast(RDMSoftwareVersion::GetVersionLength()); - const auto *pLightSet = m_pRDMPersonalities[rdm::device::responder::DEFAULT_CURRENT_PERSONALITY - 1]->GetLightSet(); + assert(nCurrentPersonality != 0); + + const auto *pLightSet = m_pRDMPersonalities[nCurrentPersonality - 1]->GetLightSet(); if (pLightSet == nullptr) { m_nDmxStartAddressFactoryDefault = lightset::dmx::ADDRESS_INVALID; @@ -87,37 +90,37 @@ void RDMDeviceResponder::Init() { const auto nProductCategory = RDMDevice::GetProductCategory(); const auto nSubDevices = m_RDMSubDevices.GetCount(); - m_tRDMDeviceInfo.protocol_major = (E120_PROTOCOL_VERSION >> 8); - m_tRDMDeviceInfo.protocol_minor = static_cast(E120_PROTOCOL_VERSION); - m_tRDMDeviceInfo.device_model[0] = static_cast(nDeviceModel >> 8); - m_tRDMDeviceInfo.device_model[1] = static_cast(nDeviceModel); - m_tRDMDeviceInfo.product_category[0] =static_cast( nProductCategory >> 8); - m_tRDMDeviceInfo.product_category[1] = static_cast(nProductCategory); - m_tRDMDeviceInfo.software_version[0] = static_cast(nSoftwareVersionId >> 24); - m_tRDMDeviceInfo.software_version[1] = static_cast(nSoftwareVersionId >> 16); - m_tRDMDeviceInfo.software_version[2] = static_cast(nSoftwareVersionId >> 8); - m_tRDMDeviceInfo.software_version[3] = static_cast(nSoftwareVersionId); + m_DeviceInfo.protocol_major = (E120_PROTOCOL_VERSION >> 8); + m_DeviceInfo.protocol_minor = static_cast(E120_PROTOCOL_VERSION); + m_DeviceInfo.device_model[0] = static_cast(nDeviceModel >> 8); + m_DeviceInfo.device_model[1] = static_cast(nDeviceModel); + m_DeviceInfo.product_category[0] =static_cast( nProductCategory >> 8); + m_DeviceInfo.product_category[1] = static_cast(nProductCategory); + m_DeviceInfo.software_version[0] = static_cast(nSoftwareVersionId >> 24); + m_DeviceInfo.software_version[1] = static_cast(nSoftwareVersionId >> 16); + m_DeviceInfo.software_version[2] = static_cast(nSoftwareVersionId >> 8); + m_DeviceInfo.software_version[3] = static_cast(nSoftwareVersionId); - auto *pLightSet = m_pRDMPersonalities[rdm::device::responder::DEFAULT_CURRENT_PERSONALITY - 1]->GetLightSet(); + assert(m_DeviceInfo.current_personality != 0); + auto *pLightSet = m_pRDMPersonalities[m_DeviceInfo.current_personality - 1]->GetLightSet(); if (pLightSet == nullptr) { - m_tRDMDeviceInfo.dmx_footprint[0] = 0; - m_tRDMDeviceInfo.dmx_footprint[1] = 0; - m_tRDMDeviceInfo.dmx_start_address[0] = static_cast(m_nDmxStartAddressFactoryDefault >> 8); - m_tRDMDeviceInfo.dmx_start_address[1] = static_cast(m_nDmxStartAddressFactoryDefault); + m_DeviceInfo.dmx_footprint[0] = 0; + m_DeviceInfo.dmx_footprint[1] = 0; + m_DeviceInfo.dmx_start_address[0] = static_cast(m_nDmxStartAddressFactoryDefault >> 8); + m_DeviceInfo.dmx_start_address[1] = static_cast(m_nDmxStartAddressFactoryDefault); } else { - m_tRDMDeviceInfo.dmx_footprint[0] = static_cast(pLightSet->GetDmxFootprint() >> 8); - m_tRDMDeviceInfo.dmx_footprint[1] = static_cast(pLightSet->GetDmxFootprint()); - m_tRDMDeviceInfo.dmx_start_address[0] = static_cast(pLightSet->GetDmxStartAddress() >> 8); - m_tRDMDeviceInfo.dmx_start_address[1] = static_cast(pLightSet->GetDmxStartAddress()); + m_DeviceInfo.dmx_footprint[0] = static_cast(pLightSet->GetDmxFootprint() >> 8); + m_DeviceInfo.dmx_footprint[1] = static_cast(pLightSet->GetDmxFootprint()); + m_DeviceInfo.dmx_start_address[0] = static_cast(pLightSet->GetDmxStartAddress() >> 8); + m_DeviceInfo.dmx_start_address[1] = static_cast(pLightSet->GetDmxStartAddress()); } - m_tRDMDeviceInfo.current_personality = rdm::device::responder::DEFAULT_CURRENT_PERSONALITY; - m_tRDMDeviceInfo.sub_device_count[0] = static_cast(nSubDevices >> 8); - m_tRDMDeviceInfo.sub_device_count[1] = static_cast(nSubDevices); - m_tRDMDeviceInfo.sensor_count = m_RDMSensors.GetCount(); + m_DeviceInfo.sub_device_count[0] = static_cast(nSubDevices >> 8); + m_DeviceInfo.sub_device_count[1] = static_cast(nSubDevices); + m_DeviceInfo.sensor_count = m_RDMSensors.GetCount(); - memcpy(&m_tRDMSubDeviceInfo, &m_tRDMDeviceInfo, sizeof(struct TRDMDeviceInfo)); + memcpy(&m_SubDeviceInfo, &m_DeviceInfo, sizeof(struct rdm::device::responder::DeviceInfo)); m_nCheckSum = CalculateChecksum(); @@ -127,21 +130,22 @@ void RDMDeviceResponder::Init() { void RDMDeviceResponder::Print() { RDMDevice::Print(); - const TRDMDeviceInfo *pDeviceInfo = GetDeviceInfo(); - const auto *pPersonality = m_pRDMPersonalities[rdm::device::responder::DEFAULT_CURRENT_PERSONALITY - 1]; + assert(m_DeviceInfo.current_personality != 0); + const auto *pPersonality = m_pRDMPersonalities[m_DeviceInfo.current_personality - 1]; + assert(pPersonality != nullptr); const char *pPersonalityDescription = pPersonality->GetDescription(); - const uint8_t nPersonalityDescriptionLength =pPersonality->GetDescriptionLength(); - - printf("RDM Responder configuration\n"); - printf(" Protocol Version %d.%d\n", pDeviceInfo->protocol_major, pDeviceInfo->protocol_minor); - printf(" DMX Address : %d\n", (pDeviceInfo->dmx_start_address[0] << 8) + pDeviceInfo->dmx_start_address[1]); - printf(" DMX Footprint : %d\n", (pDeviceInfo->dmx_footprint[0] << 8) + pDeviceInfo->dmx_footprint[1]); - printf(" Personality %d of %d [%.*s]\n", pDeviceInfo->current_personality, pDeviceInfo->personality_count, nPersonalityDescriptionLength, pPersonalityDescription); - printf(" Sub Devices : %d\n", (pDeviceInfo->sub_device_count[0] << 8) + pDeviceInfo->sub_device_count[1]); - printf(" Sensors : %d\n", pDeviceInfo->sensor_count); + const auto nPersonalityDescriptionLength = pPersonality->GetDescriptionLength(); + + puts("RDM Responder configuration"); + printf(" Protocol Version %d.%d\n", m_DeviceInfo.protocol_major, m_DeviceInfo.protocol_minor); + printf(" DMX Address : %d\n", (m_DeviceInfo.dmx_start_address[0] << 8) + m_DeviceInfo.dmx_start_address[1]); + printf(" DMX Footprint : %d\n", (m_DeviceInfo.dmx_footprint[0] << 8) + m_DeviceInfo.dmx_footprint[1]); + printf(" Personality %d of %d [%.*s]\n", m_DeviceInfo.current_personality, m_DeviceInfo.personality_count, nPersonalityDescriptionLength, pPersonalityDescription); + printf(" Sub Devices : %d\n", (m_DeviceInfo.sub_device_count[0] << 8) + m_DeviceInfo.sub_device_count[1]); + printf(" Sensors : %d\n", m_DeviceInfo.sensor_count); } -void RDMDeviceResponder::PersonalityUpdate(__attribute__((unused)) LightSet *pLightSet) { +void RDMDeviceResponder::PersonalityUpdate([[maybe_unused]] LightSet *pLightSet) { } void RDMDeviceResponder::DmxStartAddressUpdate() { diff --git a/lib-rdm/src/rdmhandler.cpp b/lib-rdm/src/rdmhandler.cpp index a700911c..8fafa51e 100644 --- a/lib-rdm/src/rdmhandler.cpp +++ b/lib-rdm/src/rdmhandler.cpp @@ -2,7 +2,7 @@ * @file rdmhandler.cpp * */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -31,22 +31,18 @@ #include #include "rdmhandler.h" - #include "rdmdeviceresponder.h" #include "rdmsensors.h" #include "rdmsubdevices.h" - #include "rdmidentify.h" #include "rdmslotinfo.h" -#include "rdmmessage.h" - -#if defined (ENABLE_RDM_MANUFACTURER_PIDS) +#include "rdmconst.h" +#include "rdm_e120.h" +#include "rdm_message_print.h" +#if defined (CONFIG_RDM_ENABLE_MANUFACTURER_PIDS) # include "rdm_manufacturer_pid.h" #endif -#include "rdm.h" -#include "rdm_e120.h" - #include "hardware.h" #include "display.h" @@ -77,7 +73,7 @@ const RDMHandler::PidDefinition RDMHandler::PID_DEFINITIONS[] { {E120_QUEUED_MESSAGE, &RDMHandler::GetQueuedMessage, nullptr, 1, true , false}, #endif {E120_SUPPORTED_PARAMETERS, &RDMHandler::GetSupportedParameters, nullptr, 0, false, true , false}, -#if defined (ENABLE_RDM_MANUFACTURER_PIDS) +#if defined (CONFIG_RDM_ENABLE_MANUFACTURER_PIDS) {E120_PARAMETER_DESCRIPTION, &RDMHandler::GetParameterDescription, nullptr, 2, false, true , false}, #endif {E120_PRODUCT_DETAIL_ID_LIST, &RDMHandler::GetProductDetailIdList, nullptr, 0, true , true , false}, @@ -99,7 +95,7 @@ const RDMHandler::PidDefinition RDMHandler::PID_DEFINITIONS[] { {E120_DISPLAY_LEVEL, &RDMHandler::GetDisplayLevel, &RDMHandler::SetDisplayLevel, 0, true , true , false}, {E120_REAL_TIME_CLOCK, &RDMHandler::GetRealTimeClock, &RDMHandler::SetRealTimeClock, 0, true , true , false}, {E120_POWER_STATE, &RDMHandler::GetPowerState, &RDMHandler::SetPowerState, 0, true , true , false}, -#if defined (ENABLE_RDM_SELF_TEST) +#if defined (CONFIG_RDM_ENABLE_SELF_TEST) {E120_PERFORM_SELFTEST, &RDMHandler::GetPerformSelfTest, &RDMHandler::SetPerformSelfTest, 0, true , true , false}, {E120_SELF_TEST_DESCRIPTION, &RDMHandler::GetSelfTestDescription, nullptr, 1, true , true , false}, #endif @@ -138,23 +134,29 @@ const RDMHandler::PidDefinition RDMHandler::PID_DEFINITIONS_SUB_DEVICES[] { #endif }; -#if defined (ENABLE_RDM_MANUFACTURER_PIDS) -const RDMHandler::PidDefinition RDMHandler::PID_DEFINITION_MANUFACTURER_GENERAL { 0, &RDMHandler::GetManufacturerPid, nullptr, 0, false, true, false }; +#if defined (CONFIG_RDM_ENABLE_MANUFACTURER_PIDS) +# if defined (CONFIG_RDM_MANUFACTURER_PIDS_SET) +const RDMHandler::PidDefinition RDMHandler::PID_DEFINITION_MANUFACTURER_GENERAL { 0, &RDMHandler::GetManufacturerPid, &RDMHandler::SetManufacturerPid, 0, false, true, false }; +# else +const RDMHandler::PidDefinition RDMHandler::PID_DEFINITION_MANUFACTURER_GENERAL { 0, &RDMHandler::GetManufacturerPid, nullptr, 0, false, true, false }; +# endif #endif RDMHandler::RDMHandler(bool bIsRdm): m_bIsRDM(bIsRdm) { DEBUG_ENTRY -#if defined (ENABLE_RDM_MANUFACTURER_PIDS) +#if defined (CONFIG_RDM_ENABLE_MANUFACTURER_PIDS) +# ifndef NDEBUG for (uint32_t i = 0; i < GetParameterDescriptionCount(); i++) { printf("0x%.4x [%.*s]\n", __builtin_bswap16(PARAMETER_DESCRIPTIONS[i].pid), PARAMETER_DESCRIPTIONS[i].pdl-0x14, PARAMETER_DESCRIPTIONS[i].description); } +# endif #endif DEBUG_EXIT } -void RDMHandler::HandleString(const char *pString, uint32_t nLength) { +void RDMHandler::HandleString(const char *pString, const uint32_t nLength) { auto *RdmMessage = reinterpret_cast(m_pRdmDataOut); RdmMessage->param_data_length = static_cast(nLength); @@ -164,9 +166,7 @@ void RDMHandler::HandleString(const char *pString, uint32_t nLength) { } } -void RDMHandler::CreateRespondMessage(uint8_t nResponseType, uint16_t nReason) { - unsigned i; - +void RDMHandler::CreateRespondMessage(const uint8_t nResponseType, const uint16_t nReason) { auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); auto *pRdmDataOut = reinterpret_cast(m_pRdmDataOut); @@ -201,12 +201,13 @@ void RDMHandler::CreateRespondMessage(uint8_t nResponseType, uint16_t nReason) { const auto *pUID = RDMDeviceResponder::Get()->GetUID(); - for (i = 0; i < RDM_UID_SIZE; i++) { + for (uint32_t i = 0; i < RDM_UID_SIZE; i++) { pRdmDataOut->destination_uid[i] = pRdmDataIn->source_uid[i]; pRdmDataOut->source_uid[i] = pUID[i]; } uint16_t rdm_checksum = 0; + uint32_t i; for (i = 0; i < pRdmDataOut->message_length; i++) { rdm_checksum = static_cast(rdm_checksum + m_pRdmDataOut[i]); @@ -217,16 +218,10 @@ void RDMHandler::CreateRespondMessage(uint8_t nResponseType, uint16_t nReason) { } void RDMHandler::RespondMessageAck() { - auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); - - if(pRdmDataIn->param_data_length == 0) { - pRdmDataIn->message_length = RDM_MESSAGE_MINIMUM_SIZE; - } - - CreateRespondMessage(E120_RESPONSE_TYPE_ACK); + CreateRespondMessage(E120_RESPONSE_TYPE_ACK, 0); } -void RDMHandler::RespondMessageNack(uint16_t nReason) { +void RDMHandler::RespondMessageNack(const uint16_t nReason) { CreateRespondMessage(E120_RESPONSE_TYPE_NACK_REASON, nReason); } @@ -253,7 +248,7 @@ void RDMHandler::HandleData(const uint8_t *pRdmDataIn, uint8_t *pRdmDataOut) { } #ifndef NDEBUG - RDMMessage::PrintNoSc(pRdmDataIn); + rdm::message_print_no_sc(pRdmDataIn); #endif const auto *pUID = RDMDeviceResponder::Get()->GetUID(); @@ -274,7 +269,7 @@ void RDMHandler::HandleData(const uint8_t *pRdmDataIn, uint8_t *pRdmDataOut) { } } - DEBUG_PRINTF("bIsRdmPacketForMe=%d", bIsRdmPacketForMe); + DEBUG_PRINTF("ForMe=%d, Broadcast=%d, Muted=%d", bIsRdmPacketForMe, bIsRdmPacketBroadcast, m_IsMuted); const auto nCommandClass = pRdmRequest->command_class; const auto nParamId = static_cast((pRdmRequest->param_id[0] << 8) + pRdmRequest->param_id[1]); @@ -308,6 +303,7 @@ void RDMHandler::HandleData(const uint8_t *pRdmDataIn, uint8_t *pRdmDataOut) { p->checksum[2] = static_cast((rdm_checksum & 0xFF) | 0xAA); p->checksum[3] = static_cast((rdm_checksum & 0xFF) | 0x55); + DEBUG_EXIT return; } } @@ -375,11 +371,11 @@ void RDMHandler::HandleData(const uint8_t *pRdmDataIn, uint8_t *pRdmDataOut) { } void RDMHandler::Handlers(bool bIsBroadcast, uint8_t nCommandClass, uint16_t nParamId, uint8_t nParamDataLength, uint16_t nSubDevice) { - DEBUG1_ENTRY + DEBUG_ENTRY if (nCommandClass != E120_GET_COMMAND && nCommandClass != E120_SET_COMMAND) { RespondMessageNack(E120_NR_UNSUPPORTED_COMMAND_CLASS); - DEBUG1_EXIT + DEBUG_EXIT return; } @@ -387,7 +383,7 @@ void RDMHandler::Handlers(bool bIsBroadcast, uint8_t nCommandClass, uint16_t nPa if ((nSubDevice > sub_device_count) && (nSubDevice != E120_SUB_DEVICE_ALL_CALL)) { RespondMessageNack(E120_NR_SUB_DEVICE_OUT_OF_RANGE); - DEBUG1_EXIT + DEBUG_EXIT return; } @@ -404,7 +400,7 @@ void RDMHandler::Handlers(bool bIsBroadcast, uint8_t nCommandClass, uint16_t nPa } } -#if defined (ENABLE_RDM_MANUFACTURER_PIDS) +#if defined (CONFIG_RDM_ENABLE_MANUFACTURER_PIDS) if (!pid_handler) { for (uint32_t i = 0; i < GetParameterDescriptionCount(); i++) { if (PARAMETER_DESCRIPTIONS[i].pid == __builtin_bswap16(nParamId)) { @@ -419,45 +415,45 @@ void RDMHandler::Handlers(bool bIsBroadcast, uint8_t nCommandClass, uint16_t nPa if (!pid_handler) { RespondMessageNack(E120_NR_UNKNOWN_PID); - DEBUG1_EXIT + DEBUG_EXIT return; } if (m_bIsRDM) { if (!bRDM) { RespondMessageNack(E120_NR_UNKNOWN_PID); - DEBUG1_EXIT + DEBUG_EXIT return; } } else { if (!bRDMNet) { RespondMessageNack(E120_NR_UNKNOWN_PID); - DEBUG1_EXIT + DEBUG_EXIT return; } } if (nCommandClass == E120_GET_COMMAND) { if (bIsBroadcast) { - DEBUG1_EXIT + DEBUG_EXIT return; } if (nSubDevice == E120_SUB_DEVICE_ALL_CALL) { RespondMessageNack(E120_NR_SUB_DEVICE_OUT_OF_RANGE); - DEBUG1_EXIT + DEBUG_EXIT return; } if (!pid_handler->pGetHandler) { RespondMessageNack(E120_NR_UNSUPPORTED_COMMAND_CLASS); - DEBUG1_EXIT + DEBUG_EXIT return; } if (nParamDataLength != pid_handler->nGetArgumentSize) { RespondMessageNack(E120_NR_FORMAT_ERROR); - DEBUG1_EXIT + DEBUG_EXIT return; } @@ -466,18 +462,18 @@ void RDMHandler::Handlers(bool bIsBroadcast, uint8_t nCommandClass, uint16_t nPa if (!pid_handler->pSetHandler) { RespondMessageNack(E120_NR_UNSUPPORTED_COMMAND_CLASS); - DEBUG1_EXIT + DEBUG_EXIT return; } (this->*(pid_handler->pSetHandler))(bIsBroadcast, nSubDevice); } - DEBUG1_EXIT + DEBUG_EXIT } #if defined (ENABLE_RDM_QUEUED_MSG) -void RDMHandler::GetQueuedMessage(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetQueuedMessage([[maybe_unused]] uint16_t nSubDevice) { m_RDMQueuedMessage.Handler(m_pRdmDataOut); RespondMessageAck(); } @@ -490,10 +486,10 @@ void RDMHandler::GetSupportedParameters(uint16_t nSubDevice) { uint32_t nTableSize = 0; if (nSubDevice != 0) { - pPidDefinitions = const_cast(&PID_DEFINITIONS_SUB_DEVICES[0]); + pPidDefinitions = const_cast(&PID_DEFINITIONS_SUB_DEVICES[0]); nTableSize = sizeof(PID_DEFINITIONS_SUB_DEVICES) / sizeof(PID_DEFINITIONS_SUB_DEVICES[0]); } else { - pPidDefinitions = const_cast(&PID_DEFINITIONS[0]); + pPidDefinitions = const_cast(&PID_DEFINITIONS[0]); nTableSize = sizeof(PID_DEFINITIONS) / sizeof(PID_DEFINITIONS[0]); } @@ -509,13 +505,13 @@ void RDMHandler::GetSupportedParameters(uint16_t nSubDevice) { } } -#if defined (ENABLE_RDM_MANUFACTURER_PIDS) +#if defined (CONFIG_RDM_ENABLE_MANUFACTURER_PIDS) const auto nSupportedParamsManufacturer = GetParameterDescriptionCount(); nSupportedParams = static_cast(nSupportedParams + nSupportedParamsManufacturer); for (uint32_t i = 0; i < nSupportedParamsManufacturer; i++) { - pRdmDataOut->param_data[j + j] = static_cast(PARAMETER_DESCRIPTIONS[i].pid); + pRdmDataOut->param_data[j + j] = static_cast(PARAMETER_DESCRIPTIONS[i].pid); ///< The PIDs are swapped pRdmDataOut->param_data[j + j + 1] = static_cast(PARAMETER_DESCRIPTIONS[i].pid >> 8); j++; } @@ -526,12 +522,12 @@ void RDMHandler::GetSupportedParameters(uint16_t nSubDevice) { RespondMessageAck(); } -#if defined (ENABLE_RDM_MANUFACTURER_PIDS) -void RDMHandler::GetParameterDescription(__attribute__((unused)) uint16_t nSubDevice) { +# if defined (CONFIG_RDM_ENABLE_MANUFACTURER_PIDS) +void RDMHandler::GetParameterDescription([[maybe_unused]] uint16_t nSubDevice) { const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); - const auto nPid = static_cast((pRdmDataIn->param_data[0] << 8) + pRdmDataIn->param_data[1]); + const auto nPid = static_cast(pRdmDataIn->param_data[0] + (pRdmDataIn->param_data[1] << 8)); - if (!(nPid >= 0x8000 && nPid <= 0xFFDF)) { + if (!(nPid >= __builtin_bswap16(0x8000) && nPid <= __builtin_bswap16(0xFFDF))) { RespondMessageNack(E120_NR_DATA_OUT_OF_RANGE); return; } @@ -539,7 +535,7 @@ void RDMHandler::GetParameterDescription(__attribute__((unused)) uint16_t nSubDe const auto nSupportedParamsManufacturer = GetParameterDescriptionCount(); for (uint32_t i = 0; i < nSupportedParamsManufacturer; i++) { - if (PARAMETER_DESCRIPTIONS[i].pid == __builtin_bswap16(nPid)) { + if (PARAMETER_DESCRIPTIONS[i].pid == nPid) { auto *pRdmDataOut = reinterpret_cast(m_pRdmDataOut); pRdmDataOut->param_data_length = PARAMETER_DESCRIPTIONS[i].pdl; @@ -554,7 +550,7 @@ void RDMHandler::GetParameterDescription(__attribute__((unused)) uint16_t nSubDe } -void RDMHandler::GetManufacturerPid(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetManufacturerPid([[maybe_unused]] uint16_t nSubDevice) { const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); auto *pRdmDataOut = reinterpret_cast(m_pRdmDataOut); @@ -571,22 +567,45 @@ void RDMHandler::GetManufacturerPid(__attribute__((unused)) uint16_t nSubDevice RespondMessageNack(nReason); } -#endif +# if defined (CONFIG_RDM_MANUFACTURER_PIDS_SET) +void RDMHandler::SetManufacturerPid(bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { + const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); + auto *pRdmDataOut = reinterpret_cast(m_pRdmDataOut); + + const auto nPid = static_cast(pRdmDataIn->param_id[0] + (pRdmDataIn->param_id[1] << 8)); + const rdm::ManufacturerParamData pIn = { pRdmDataIn->param_data_length, const_cast(pRdmDataIn->param_data) }; + rdm::ManufacturerParamData pOut = { 0, pRdmDataOut->param_data }; + uint16_t nReason = E120_NR_UNKNOWN_PID; + + for (uint32_t nIndex = 0; nIndex < GetParameterDescriptionCount(); nIndex++) { + if (PARAMETER_DESCRIPTIONS[nIndex].pid == nPid) { + if (rdm::handle_manufactureer_pid_set(IsBroadcast, nPid, PARAMETER_DESCRIPTIONS[nIndex], &pIn, &pOut, nReason)) { + pRdmDataOut->param_data_length = pOut.nPdl; + RespondMessageAck(); + return; + } + } + } + + RespondMessageNack(nReason); +} +# endif // CONFIG_RDM_MANUFACTURER_PIDS_SET +# endif // CONFIG_RDM_ENABLE_MANUFACTURER_PIDS #endif void RDMHandler::GetDeviceInfo(uint16_t nSubDevice) { const auto *pRdmDeviceInfoRequested = RDMDeviceResponder::Get()->GetDeviceInfo(nSubDevice); auto *pRdmDataOut = reinterpret_cast(m_pRdmDataOut); - auto *pDeviceInfoOut = reinterpret_cast(pRdmDataOut->param_data); + auto *pDeviceInfoOut = reinterpret_cast(pRdmDataOut->param_data); - pRdmDataOut->param_data_length = sizeof(struct TRDMDeviceInfo); - memcpy(pDeviceInfoOut, pRdmDeviceInfoRequested, sizeof(struct TRDMDeviceInfo)); + pRdmDataOut->param_data_length = sizeof(struct rdm::device::responder::DeviceInfo); + memcpy(pDeviceInfoOut, pRdmDeviceInfoRequested, sizeof(struct rdm::device::responder::DeviceInfo)); RespondMessageAck(); } -void RDMHandler::GetFactoryDefaults(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetFactoryDefaults([[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataOut = reinterpret_cast(m_pRdmDataOut); pRdmDataOut->param_data_length = 1; @@ -595,7 +614,7 @@ void RDMHandler::GetFactoryDefaults(__attribute__((unused)) uint16_t nSubDevice) RespondMessageAck(); } -void RDMHandler::SetFactoryDefaults(bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::SetFactoryDefaults(bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (pRdmDataIn->param_data_length != 0) { @@ -616,7 +635,7 @@ void RDMHandler::SetFactoryDefaults(bool IsBroadcast, __attribute__((unused)) ui } #if !defined (NODE_RDMNET_LLRP_ONLY) -void RDMHandler::GetProductDetailIdList(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetProductDetailIdList([[maybe_unused]] uint16_t nSubDevice) { const auto nProductDetail = RDMDeviceResponder::Get()->GetProductDetail(); auto *pRdmDataOut = reinterpret_cast(m_pRdmDataOut); @@ -629,7 +648,7 @@ void RDMHandler::GetProductDetailIdList(__attribute__((unused)) uint16_t nSubDev } #endif -void RDMHandler::GetDeviceModelDescription(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetDeviceModelDescription([[maybe_unused]] uint16_t nSubDevice) { uint8_t nBoardNameLength; const char *pBoardModel = Hardware::Get()->GetBoardName(nBoardNameLength); @@ -637,7 +656,7 @@ void RDMHandler::GetDeviceModelDescription(__attribute__((unused)) uint16_t nSub RespondMessageAck(); } -void RDMHandler::GetManufacturerLabel(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetManufacturerLabel([[maybe_unused]] uint16_t nSubDevice) { TRDMDeviceInfoData label; RDMDeviceResponder::Get()->GetManufacturerName(&label); @@ -674,7 +693,7 @@ void RDMHandler::SetDeviceLabel(bool IsBroadcast, uint16_t nSubDevice) { RespondMessageAck(); } -void RDMHandler::GetSoftwareVersionLabel(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetSoftwareVersionLabel([[maybe_unused]] uint16_t nSubDevice) { const auto *pSoftwareVersion = RDMDeviceResponder::Get()->GetSoftwareVersion(); const auto nSoftwareVersionLength = RDMDeviceResponder::Get()->GetSoftwareVersionLength(); @@ -682,7 +701,7 @@ void RDMHandler::GetSoftwareVersionLabel(__attribute__((unused)) uint16_t nSubDe RespondMessageAck(); } -void RDMHandler::SetResetDevice(__attribute__((unused)) bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::SetResetDevice([[maybe_unused]] bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (pRdmDataIn->param_data_length != 1) { @@ -710,7 +729,7 @@ void RDMHandler::SetResetDevice(__attribute__((unused)) bool IsBroadcast, __attr } } -void RDMHandler::GetIdentifyDevice(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetIdentifyDevice([[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataOut = reinterpret_cast(m_pRdmDataOut); pRdmDataOut->param_data_length = 1; @@ -721,7 +740,7 @@ void RDMHandler::GetIdentifyDevice(__attribute__((unused)) uint16_t nSubDevice) RespondMessageAck(); } -void RDMHandler::SetIdentifyDevice(bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::SetIdentifyDevice(bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (pRdmDataIn->param_data_length != 1) { @@ -750,14 +769,14 @@ void RDMHandler::SetIdentifyDevice(bool IsBroadcast, __attribute__((unused)) uin } #if !defined (NODE_RDMNET_LLRP_ONLY) -void RDMHandler::GetLanguage(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetLanguage([[maybe_unused]] uint16_t nSubDevice) { const auto *pLanguage = RDMDeviceResponder::Get()->GetLanguage(); HandleString(pLanguage, RDM_DEVICE_SUPPORTED_LANGUAGE_LENGTH); RespondMessageAck(); } -void RDMHandler::SetLanguage(bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::SetLanguage(bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (pRdmDataIn->param_data_length != RDM_DEVICE_SUPPORTED_LANGUAGE_LENGTH) { @@ -782,7 +801,7 @@ void RDMHandler::SetLanguage(bool IsBroadcast, __attribute__((unused)) uint16_t RespondMessageAck(); } -void RDMHandler::GetBootSoftwareVersionId(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetBootSoftwareVersionId([[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (pRdmDataIn->param_data_length != 0) { @@ -803,7 +822,7 @@ void RDMHandler::GetBootSoftwareVersionId(__attribute__((unused)) uint16_t nSubD RespondMessageAck(); } -void RDMHandler::GetBootSoftwareVersionLabel(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetBootSoftwareVersionLabel([[maybe_unused]] uint16_t nSubDevice) { uint8_t nSysNameLength; const auto *pSysName = Hardware::Get()->GetSysName(nSysNameLength); @@ -824,7 +843,7 @@ void RDMHandler::GetPersonality(uint16_t nSubDevice) { RespondMessageAck(); } -void RDMHandler::SetPersonality(__attribute__((unused)) bool IsBroadcast, uint16_t nSubDevice) { +void RDMHandler::SetPersonality([[maybe_unused]] bool IsBroadcast, uint16_t nSubDevice) { auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (pRdmDataIn->param_data_length != 1) { @@ -915,7 +934,7 @@ void RDMHandler::SetDmxStartAddress(bool IsBroadcast, uint16_t nSubDevice) { RespondMessageAck(); } -void RDMHandler::GetSensorDefinition(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetSensorDefinition([[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); const auto nSensorRequested = pRdmDataIn->param_data[0]; @@ -958,7 +977,7 @@ void RDMHandler::GetSensorDefinition(__attribute__((unused)) uint16_t nSubDevice RespondMessageAck(); } -void RDMHandler::GetSensorValue(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetSensorValue([[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (pRdmDataIn->param_data_length != 1) { @@ -996,7 +1015,7 @@ void RDMHandler::GetSensorValue(__attribute__((unused)) uint16_t nSubDevice) { RespondMessageAck(); } -void RDMHandler::SetSensorValue(bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::SetSensorValue(bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (pRdmDataIn->param_data_length != 1) { @@ -1053,7 +1072,7 @@ void RDMHandler::SetSensorValue(bool IsBroadcast, __attribute__((unused)) uint16 RespondMessageAck(); } -void RDMHandler::SetRecordSensors(bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::SetRecordSensors(bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (pRdmDataIn->param_data_length != 1) { @@ -1085,7 +1104,7 @@ void RDMHandler::SetRecordSensors(bool IsBroadcast, __attribute__((unused)) uint RespondMessageAck(); } -void RDMHandler::GetDeviceHours(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetDeviceHours([[maybe_unused]] uint16_t nSubDevice) { uint64_t device_hours = Hardware::Get()->GetUpTime() / 3600; // The value for the Device Hours field shall be unsigned and not roll over when maximum value is reached. if (device_hours > UINT32_MAX) { @@ -1103,11 +1122,11 @@ void RDMHandler::GetDeviceHours(__attribute__((unused)) uint16_t nSubDevice) { RespondMessageAck(); } -void RDMHandler::SetDeviceHours(__attribute__((unused)) bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::SetDeviceHours([[maybe_unused]] bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { RespondMessageNack(E120_NR_WRITE_PROTECT); } -void RDMHandler::GetDisplayInvert(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetDisplayInvert([[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataOut = reinterpret_cast(m_pRdmDataOut); pRdmDataOut->param_data_length = 1; @@ -1118,7 +1137,7 @@ void RDMHandler::GetDisplayInvert(__attribute__((unused)) uint16_t nSubDevice) { RespondMessageAck(); } -void RDMHandler::SetDisplayInvert(__attribute__((unused)) bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::SetDisplayInvert([[maybe_unused]] bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (pRdmDataIn->param_data_length != 1) { @@ -1141,7 +1160,7 @@ void RDMHandler::SetDisplayInvert(__attribute__((unused)) bool IsBroadcast, __at RespondMessageAck(); } -void RDMHandler::GetDisplayLevel(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetDisplayLevel([[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataOut = reinterpret_cast(m_pRdmDataOut); pRdmDataOut->param_data_length = 1; @@ -1153,7 +1172,7 @@ void RDMHandler::GetDisplayLevel(__attribute__((unused)) uint16_t nSubDevice) { RespondMessageAck(); } -void RDMHandler::SetDisplayLevel(__attribute__((unused)) bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::SetDisplayLevel([[maybe_unused]] bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (pRdmDataIn->param_data_length != 1) { @@ -1179,28 +1198,27 @@ void RDMHandler::SetDisplayLevel(__attribute__((unused)) bool IsBroadcast, __att RespondMessageAck(); } -void RDMHandler::GetRealTimeClock(__attribute__((unused)) uint16_t nSubDevice) { - struct tm local_time; - Hardware::Get()->GetTime(&local_time); - - const auto year = static_cast(local_time.tm_year + 1900); +void RDMHandler::GetRealTimeClock([[maybe_unused]] uint16_t nSubDevice) { + const auto ltime = time(nullptr); + const auto *tm = localtime(<ime); + const auto year = static_cast(tm->tm_year + 1900); auto *pRdmDataOut = reinterpret_cast(m_pRdmDataOut); pRdmDataOut->param_data[0] = static_cast(year >> 8); pRdmDataOut->param_data[1] = static_cast(year); - pRdmDataOut->param_data[2] = static_cast(local_time.tm_mon + 1); // 0..11 - pRdmDataOut->param_data[3] = static_cast(local_time.tm_mday); - pRdmDataOut->param_data[4] = static_cast(local_time.tm_hour); - pRdmDataOut->param_data[5] = static_cast(local_time.tm_min); - pRdmDataOut->param_data[6] = static_cast(local_time.tm_sec); + pRdmDataOut->param_data[2] = static_cast(tm->tm_mon + 1); // 0..11 + pRdmDataOut->param_data[3] = static_cast(tm->tm_mday); + pRdmDataOut->param_data[4] = static_cast(tm->tm_hour); + pRdmDataOut->param_data[5] = static_cast(tm->tm_min); + pRdmDataOut->param_data[6] = static_cast(tm->tm_sec); pRdmDataOut->param_data_length = 7; RespondMessageAck(); } -void RDMHandler::SetRealTimeClock(bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::SetRealTimeClock(bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (pRdmDataIn->param_data_length != 7) { @@ -1231,7 +1249,7 @@ void RDMHandler::SetRealTimeClock(bool IsBroadcast, __attribute__((unused)) uint RespondMessageAck(); } -void RDMHandler::GetPowerState(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetPowerState([[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataOut = reinterpret_cast(m_pRdmDataOut); pRdmDataOut->param_data_length = 1; @@ -1240,7 +1258,7 @@ void RDMHandler::GetPowerState(__attribute__((unused)) uint16_t nSubDevice) { RespondMessageAck(); } -void RDMHandler::SetPowerState(__attribute__((unused)) bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::SetPowerState([[maybe_unused]] bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (pRdmDataIn->param_data_length != 1) { @@ -1276,10 +1294,10 @@ void RDMHandler::SetPowerState(__attribute__((unused)) bool IsBroadcast, __attri RespondMessageNack(E120_NR_WRITE_PROTECT); } -#if defined (ENABLE_RDM_SELF_TEST) +#if defined (CONFIG_RDM_ENABLE_SELF_TEST) #include "rdm_selftest.h" -void RDMHandler::GetPerformSelfTest(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetPerformSelfTest([[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataOut = reinterpret_cast(m_pRdmDataOut); pRdmDataOut->param_data_length = 1; @@ -1288,7 +1306,7 @@ void RDMHandler::GetPerformSelfTest(__attribute__((unused)) uint16_t nSubDevice) RespondMessageAck(); } -void RDMHandler::SetPerformSelfTest(__attribute__((unused)) bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::SetPerformSelfTest([[maybe_unused]] bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (pRdmDataIn->param_data_length != 1) { @@ -1307,7 +1325,7 @@ void RDMHandler::SetPerformSelfTest(__attribute__((unused)) bool IsBroadcast, __ RespondMessageAck(); } -void RDMHandler::GetSelfTestDescription(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetSelfTestDescription([[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); uint32_t nLength; const auto *pText = rdm::selftest::GetDescription(pRdmDataIn->param_data[0], nLength); @@ -1333,12 +1351,12 @@ void RDMHandler::GetSelfTestDescription(__attribute__((unused)) uint16_t nSubDev RespondMessageAck(); } -#endif +#endif // CONFIG_RDM_ENABLE_SELF_TEST #if defined (ENABLE_RDM_PRESET_PLAYBACK) #include "rdm_preset_playback.h" -void RDMHandler::GetPresetPlayback(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetPresetPlayback([[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataOut = reinterpret_cast(m_pRdmDataOut); uint16_t nMode; @@ -1354,7 +1372,7 @@ void RDMHandler::GetPresetPlayback(__attribute__((unused)) uint16_t nSubDevice) RespondMessageAck(); } -void RDMHandler::SetPresetPlayback(__attribute__((unused)) bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::SetPresetPlayback([[maybe_unused]] bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); if (pRdmDataIn->param_data_length != 3) { @@ -1375,7 +1393,7 @@ void RDMHandler::SetPresetPlayback(__attribute__((unused)) bool IsBroadcast, __a RespondMessageAck(); } -#endif +#endif // ENABLE_RDM_PRESET_PLAYBACK void RDMHandler::GetSlotInfo(uint16_t nSubDevice) { auto *pRdmDataOut = reinterpret_cast(m_pRdmDataOut); diff --git a/lib-rdm/src/rdmhandlere1371.cpp b/lib-rdm/src/rdmhandlere1371.cpp index 898f9224..892e1843 100644 --- a/lib-rdm/src/rdmhandlere1371.cpp +++ b/lib-rdm/src/rdmhandlere1371.cpp @@ -26,7 +26,7 @@ #include #include "rdmhandler.h" - +#include "rdmconst.h" #include "rdmidentify.h" #include "rdm_e120.h" @@ -36,7 +36,7 @@ * ANSI E1.37-1 */ -void RDMHandler::GetIdentifyMode(__attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::GetIdentifyMode([[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY auto *pRdmDataOut = reinterpret_cast(m_pRdmDataOut); @@ -49,7 +49,7 @@ void RDMHandler::GetIdentifyMode(__attribute__((unused)) uint16_t nSubDevice) { DEBUG_EXIT } -void RDMHandler::SetIdentifyMode(bool IsBroadcast, __attribute__((unused)) uint16_t nSubDevice) { +void RDMHandler::SetIdentifyMode(bool IsBroadcast, [[maybe_unused]] uint16_t nSubDevice) { DEBUG_ENTRY const auto *pRdmDataIn = reinterpret_cast(m_pRdmDataIn); diff --git a/lib-rdm/src/rdmidentify.cpp b/lib-rdm/src/rdmidentify.cpp index 70865455..aad55eb2 100644 --- a/lib-rdm/src/rdmidentify.cpp +++ b/lib-rdm/src/rdmidentify.cpp @@ -38,8 +38,8 @@ RDMIdentify::RDMIdentify() { s_pThis = this; } -void __attribute__((weak)) RDMIdentify::On(__attribute__((unused)) rdm::identify::Mode nMode) { +void __attribute__((weak)) RDMIdentify::On([[maybe_unused]] rdm::identify::Mode nMode) { } -void __attribute__((weak)) RDMIdentify::Off(__attribute__((unused)) rdm::identify::Mode nMode) { +void __attribute__((weak)) RDMIdentify::Off([[maybe_unused]] rdm::identify::Mode nMode) { } diff --git a/lib-rdmnet/src/rdmnetconst.cpp b/lib-rdm/src/rdmnet/rdmnetconst.cpp old mode 100644 new mode 100755 similarity index 100% rename from lib-rdmnet/src/rdmnetconst.cpp rename to lib-rdm/src/rdmnet/rdmnetconst.cpp diff --git a/lib-rdm/src/rdmqueuedmessage.cpp b/lib-rdm/src/rdmqueuedmessage.cpp index 43a60d4b..cd59cf63 100644 --- a/lib-rdm/src/rdmqueuedmessage.cpp +++ b/lib-rdm/src/rdmqueuedmessage.cpp @@ -2,7 +2,7 @@ * @file rdmqueuedmessage.cpp * */ -/* Copyright (C) 2017-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,13 +27,9 @@ #include #include "rdmqueuedmessage.h" - -#include "rdmmessage.h" - -#include "rdm.h" +#include "rdmconst.h" #include "rdm_e120.h" - RDMQueuedMessage::RDMQueuedMessage() { m_pQueue = new TRdmQueuedMessage[RDM_MESSAGE_COUNT_MAX]; assert(m_pQueue != nullptr); diff --git a/lib-network/src/net/tftp_internal.h b/lib-rdm/src/rdmsensors.cpp similarity index 83% rename from lib-network/src/net/tftp_internal.h rename to lib-rdm/src/rdmsensors.cpp index 13c9f056..24802710 100644 --- a/lib-network/src/net/tftp_internal.h +++ b/lib-rdm/src/rdmsensors.cpp @@ -1,8 +1,8 @@ /** - * @file tftp_internal.h + * @file rdmsensors.cpp * */ -/* Copyright (C) 2019-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,11 +23,7 @@ * THE SOFTWARE. */ -#ifndef TFTP_INTERNAL_H_ -#define TFTP_INTERNAL_H_ +#include "rdmsensors.h" -enum { - TFTP_PORT_SERVER = 69 -}; +RDMSensors *RDMSensors::s_pThis = nullptr; -#endif /* TFTP_INTERNAL_H_ */ diff --git a/lib-rdm/src/rdmslotinfo.cpp b/lib-rdm/src/rdmslotinfo.cpp index 6fe9eeaf..8d94a601 100644 --- a/lib-rdm/src/rdmslotinfo.cpp +++ b/lib-rdm/src/rdmslotinfo.cpp @@ -139,7 +139,7 @@ const char *RDMSlotInfo::GetCategoryText(uint16_t nSlotOffset, uint16_t nId, uin return s_tTableC2[nIndex].pDescription; } -const char *RDMSlotInfo::GetCategoryTextUndefined(__attribute__((unused)) uint16_t nSlotOffset, uint32_t& nLength) { +const char *RDMSlotInfo::GetCategoryTextUndefined([[maybe_unused]] uint16_t nSlotOffset, uint32_t& nLength) { const auto nIndex = TABLE_C2_SIZE - 1; nLength = static_cast(strlen(s_tTableC2[nIndex].pDescription)); return s_tTableC2[nIndex].pDescription; diff --git a/lib-rdmsubdevice/src/spi/rdmsubdevicedummy.cpp b/lib-rdm/src/rdmsubdevicedummy.cpp similarity index 81% rename from lib-rdmsubdevice/src/spi/rdmsubdevicedummy.cpp rename to lib-rdm/src/rdmsubdevicedummy.cpp index 7ae825aa..24fa07ab 100644 --- a/lib-rdmsubdevice/src/spi/rdmsubdevicedummy.cpp +++ b/lib-rdm/src/rdmsubdevicedummy.cpp @@ -2,7 +2,7 @@ * @file rdmsubdevicedummy.cpp * */ -/* Copyright (C) 2018-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,13 +27,13 @@ #include #include -#include "rdmsubdevicedummy.h" +#include "subdevice/rdmsubdevicedummy.h" #include "rdmpersonality.h" static constexpr uint32_t DMX_FOOTPRINT = 4; static RDMPersonality *s_RDMPersonalities[] = {new RDMPersonality("Dummy-H", DMX_FOOTPRINT), new RDMPersonality("Dummy-D", DMX_FOOTPRINT)}; -RDMSubDeviceDummy::RDMSubDeviceDummy(__attribute__((unused)) uint16_t nDmxStartAddress, __attribute__((unused)) char nChipSselect, __attribute__((unused)) uint8_t nSlaveAddress, __attribute__((unused)) uint32_t nSpiSpeed) : +RDMSubDeviceDummy::RDMSubDeviceDummy([[maybe_unused]] uint16_t nDmxStartAddress, [[maybe_unused]] char nChipSselect, [[maybe_unused]] uint8_t nSlaveAddress, [[maybe_unused]] uint32_t nSpiSpeed) : RDMSubDevice("SubDevice Dummy", nDmxStartAddress) { SetDmxFootprint(DMX_FOOTPRINT); @@ -58,8 +58,8 @@ void RDMSubDeviceDummy::Data(const uint8_t* pData, uint32_t nLength) { const auto nDmxStartAddress = GetDmxStartAddress(); - printf("RDMSubDeviceDummy::Data(*pData:%p, nLength:%d)\n", static_cast(pData), nLength); - printf("%d:%d:%d: ", nLength, DMX_FOOTPRINT, nDmxStartAddress); + printf("RDMSubDeviceDummy::Data(*pData:%p, nLength:%u)\n", static_cast(pData), static_cast(nLength)); + printf("%u:%u:%u: ", static_cast(nLength), static_cast(DMX_FOOTPRINT), static_cast(nDmxStartAddress)); for (uint32_t i = static_cast(nDmxStartAddress - 1), j = 0; (i < nLength) && (j < DMX_FOOTPRINT); i++, j++) { switch (GetPersonalityCurrent()) { @@ -74,7 +74,7 @@ void RDMSubDeviceDummy::Data(const uint8_t* pData, uint32_t nLength) { } } - printf("\n"); + puts(""); } void RDMSubDeviceDummy::UpdateEvent(TRDMSubDeviceUpdateEvent tUpdateEvent) { diff --git a/lib-rdm/src/rdmsubdevices.cpp b/lib-rdm/src/rdmsubdevices.cpp new file mode 100644 index 00000000..11887158 --- /dev/null +++ b/lib-rdm/src/rdmsubdevices.cpp @@ -0,0 +1,39 @@ +/** + * @file rdmsubdevices.cpp + * + */ +/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "rdmsubdevices.h" + +RDMSubDevices *RDMSubDevices::s_pThis; + + + + + + + + + + + diff --git a/lib-rdm/src/responder/rdmresponder.cpp b/lib-rdm/src/responder/rdmresponder.cpp new file mode 100644 index 00000000..543266d4 --- /dev/null +++ b/lib-rdm/src/responder/rdmresponder.cpp @@ -0,0 +1,38 @@ +/** + * @file rdmresponder.cpp + * + */ +/* Copyright (C) 2018-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#include "rdmresponder.h" + +RDMResponder *RDMResponder::s_pThis; +TRdmMessage RDMResponder::s_RdmCommand; +bool RDMResponder::m_IsSubDeviceActive; + +void __attribute__((weak)) RDMResponder::PersonalityUpdate([[maybe_unused]] uint32_t nPersonality) { +} + +void __attribute__((weak))DmxStartAddressUpdate([[maybe_unused]] uint16_t nDmxStartAddress) { +} diff --git a/lib-rdmdiscovery/.cproject b/lib-rdmdiscovery/.cproject deleted file mode 100644 index 46869eb5..00000000 --- a/lib-rdmdiscovery/.cproject +++ /dev/null @@ -1,146 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/lib-rdmdiscovery/.project b/lib-rdmdiscovery/.project deleted file mode 100644 index 86ac5f25..00000000 --- a/lib-rdmdiscovery/.project +++ /dev/null @@ -1,27 +0,0 @@ - - - lib-rdmdiscovery - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - diff --git a/lib-rdmdiscovery/.settings/org.eclipse.cdt.core.prefs b/lib-rdmdiscovery/.settings/org.eclipse.cdt.core.prefs deleted file mode 100644 index c8ec5df2..00000000 --- a/lib-rdmdiscovery/.settings/org.eclipse.cdt.core.prefs +++ /dev/null @@ -1,6 +0,0 @@ -doxygen/doxygen_new_line_after_brief=true -doxygen/doxygen_use_brief_tag=false -doxygen/doxygen_use_javadoc_tags=true -doxygen/doxygen_use_pre_tag=false -doxygen/doxygen_use_structural_commands=false -eclipse.preferences.version=1 diff --git a/lib-rdmdiscovery/.settings/org.eclipse.core.resources.prefs b/lib-rdmdiscovery/.settings/org.eclipse.core.resources.prefs deleted file mode 100644 index 99f26c02..00000000 --- a/lib-rdmdiscovery/.settings/org.eclipse.core.resources.prefs +++ /dev/null @@ -1,2 +0,0 @@ -eclipse.preferences.version=1 -encoding/=UTF-8 diff --git a/lib-rdmdiscovery/Makefile b/lib-rdmdiscovery/Makefile deleted file mode 100644 index cd3e668b..00000000 --- a/lib-rdmdiscovery/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -DEFINES=#NDEBUG -EXTRA_INCLUDES=../lib-dmx/include ../lib-rdm/include ../lib-artnet/include ../lib-lightset/include ../lib-hal/include - -include ../firmware-template-gd32/lib/Rules.mk diff --git a/lib-rdmdiscovery/Makefile.GD32 b/lib-rdmdiscovery/Makefile.GD32 deleted file mode 100644 index d414e5f3..00000000 --- a/lib-rdmdiscovery/Makefile.GD32 +++ /dev/null @@ -1,6 +0,0 @@ -DEFINES=#NDEBUG - -EXTRA_INCLUDES=../lib-dmx/include ../lib-rdm/include ../lib-artnet/include ../lib-lightset/include ../lib-hal/include - -include Rules.mk -include ../firmware-template-gd32/lib/Rules.mk diff --git a/lib-rdmdiscovery/Rules.mk b/lib-rdmdiscovery/Rules.mk deleted file mode 100644 index b856ee07..00000000 --- a/lib-rdmdiscovery/Rules.mk +++ /dev/null @@ -1,27 +0,0 @@ -EXTRA_INCLUDES+=../lib-rdm/include ../lib-lightset/include ../lib-hal/include ../lib-network/include - -ifneq ($(MAKE_FLAGS),) - ifeq ($(findstring NODE_ARTNET,$(MAKE_FLAGS)), NODE_ARTNET) - EXTRA_INCLUDES+=../lib-artnet/include - EXTRA_SRCDIR+=src/artnet - ifeq ($(findstring ARTNET_VERSION=4,$(MAKE_FLAGS)), ARTNET_VERSION=4) - EXTRA_INCLUDES+=../lib-e131/include - endif - endif - ifeq ($(findstring NODE_NODE,$(MAKE_FLAGS)), NODE_NODE) - EXTRA_INCLUDES+=../lib-artnet/include - EXTRA_SRCDIR+=src/artnet - ifeq ($(findstring ARTNET_VERSION=4,$(MAKE_FLAGS)), ARTNET_VERSION=4) - EXTRA_INCLUDES+=../lib-e131/include - endif - endif - ifeq ($(findstring RDM_CONTROLLER,$(MAKE_FLAGS)), RDM_CONTROLLER) - EXTRA_INCLUDES+= - EXTRA_SRCDIR+=src/rdm - endif -else - EXTRA_INCLUDES+=../lib-artnet/include - EXTRA_SRCDIR+=src/rdm src/artnet - DEFINES+=RDM_CONTROLLER - DEFINES+=LIGHTSET_PORTS=4 -endif \ No newline at end of file diff --git a/lib-rdmdiscovery/include/artnetrdmcontroller.h b/lib-rdmdiscovery/include/artnetrdmcontroller.h deleted file mode 100755 index eb706cf3..00000000 --- a/lib-rdmdiscovery/include/artnetrdmcontroller.h +++ /dev/null @@ -1,112 +0,0 @@ -/** - * @file artnetrdmcontroller.h - * - */ -/* Copyright (C) 2017-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef ARTNETRDMCONTROLLER_H_ -#define ARTNETRDMCONTROLLER_H_ - -#include -#include -#include - -#include "artnetrdm.h" - -#include "rdmdiscovery.h" -#include "rdmdevicecontroller.h" -#include "rdm.h" - -#include "debug.h" - -class ArtNetRdmController final: public RDMDeviceController, public ArtNetRdm, RDMDiscovery { -public: - ArtNetRdmController(); - - ~ArtNetRdmController() override { - DEBUG_ENTRY - DEBUG_EXIT - } - - void Print() { - RDMDeviceController::Print(); - } - - const uint8_t *Handler(uint32_t nPortIndex, const uint8_t *pRdmData) override; - - // Discovery - - void Full(uint32_t nPortIndex) override { - DEBUG_ENTRY - assert(nPortIndex < artnetnode::MAX_PORTS); - RDMDiscovery::Full(nPortIndex, &m_pRDMTod[nPortIndex]); - DEBUG_EXIT - } - - uint32_t GetUidCount(uint32_t nPortIndex) override { - assert(nPortIndex < artnetnode::MAX_PORTS); - return m_pRDMTod[nPortIndex].GetUidCount(); - } - - void TodCopy(uint32_t nPortIndex, uint8_t *pTod) override { - DEBUG_ENTRY - assert(nPortIndex < artnetnode::MAX_PORTS); - m_pRDMTod[nPortIndex].Copy(pTod); - DEBUG_EXIT - } - - // Gateway - - bool RdmReceive(uint32_t nPortIndex, uint8_t *pRdmData) override; - - void TodReset(uint32_t nPortIndex) override { - assert(nPortIndex < artnetnode::MAX_PORTS); - m_pRDMTod[nPortIndex].Reset(); - } - - bool TodAddUid(uint32_t nPortIndex, const uint8_t *pUid) override { - return m_pRDMTod[nPortIndex].AddUid(pUid); - } - - // class Node - - bool CopyTodEntry(uint32_t nPortIndex, uint32_t nIndex, uint8_t uid[RDM_UID_SIZE]) { - assert(nPortIndex < artnetnode::MAX_PORTS); - return m_pRDMTod[nPortIndex].CopyUidEntry(nIndex, uid); - } - - // Generic - - void TodDump(uint32_t nPortIndex) { - assert(nPortIndex < artnetnode::MAX_PORTS); - m_pRDMTod[nPortIndex].Dump(); - } - -private: - void RespondMessageAck(uint32_t nPortIndex, const uint8_t *pUid, const struct TRdmMessage *pRdmMessage); - -private: - static RDMTod m_pRDMTod[artnetnode::MAX_PORTS]; - static TRdmMessage s_rdmMessage; -}; - -#endif /* ARTNETRDMCONTROLLER_H_ */ diff --git a/lib-rdmdiscovery/src/artnet/rdm_send.cpp b/lib-rdmdiscovery/src/artnet/rdm_send.cpp deleted file mode 100644 index 3fd1f7dc..00000000 --- a/lib-rdmdiscovery/src/artnet/rdm_send.cpp +++ /dev/null @@ -1,72 +0,0 @@ -/** - * @file rdm_send.cpp - */ - -/* Copyright (C) 2022 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#include - -#include "artnetrdm.h" - -#include "rdm.h" -#include "rdmmessage.h" -#include "rdm_e120.h" - -#include "debug.h" - -namespace artnet { - -void rdm_send(uint32_t nPortIndex, const uint8_t *pRdmData) { - assert(pRdmData != nullptr); - - auto *pRdmMessage = reinterpret_cast(pRdmData); - - if ((pRdmMessage->command_class == E120_GET_COMMAND_RESPONSE) || (pRdmMessage->command_class == E120_SET_COMMAND_RESPONSE)) { - struct TRdmMessage rdmMessage; - - rdmMessage.start_code = E120_SC_RDM; - - auto *pData = reinterpret_cast(&rdmMessage); - - memcpy(&pData[1], pRdmData, pRdmMessage->message_length - 1U); - - uint32_t i; - uint16_t nChecksum = 0; - - for (i = 0; i < rdmMessage.message_length; i++) { - nChecksum = static_cast(nChecksum + pData[i]); - } - - pData[i++] = static_cast(nChecksum >> 8); - pData[i] = static_cast(nChecksum & 0XFF); - - Rdm::SendRaw(nPortIndex, reinterpret_cast(&rdmMessage), rdmMessage.message_length + RDM_MESSAGE_CHECKSUM_SIZE); - -#ifndef NDEBUG - RDMMessage::Print(reinterpret_cast(&rdmMessage)); -#endif - } -} - -} // namespace artnet diff --git a/lib-rdmdiscovery/src/rdm/rdmdiscovery.cpp b/lib-rdmdiscovery/src/rdm/rdmdiscovery.cpp deleted file mode 100755 index df8891d9..00000000 --- a/lib-rdmdiscovery/src/rdm/rdmdiscovery.cpp +++ /dev/null @@ -1,345 +0,0 @@ -/** - * @file rdmddiscovery.cpp - * - */ -/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#ifndef NDEBUG -# include -#endif - -#include "rdm.h" -#include "rdm_e120.h" -#include "rdmdiscovery.h" - -#include "hardware.h" - -typedef union cast { - uint64_t uint; - uint8_t uid[RDM_UID_SIZE]; -} _cast; - -static _cast uuid_cast; - -static constexpr auto RECEIVE_TIME_OUT = 2800U; - -RDMDiscovery::RDMDiscovery(const uint8_t *pUid) { - memcpy(m_Uid, pUid, RDM_UID_SIZE); - m_Message.SetSrcUid(pUid); - -#ifndef NDEBUG - printf("Uid : "); - PrintUid(m_Uid); - printf("\n"); -#endif -} - -void RDMDiscovery::Full(uint32_t nPortIndex, RDMTod *pRDMTod){ - DEBUG_ENTRY - - m_nPortIndex = nPortIndex; - - m_pRDMTod = pRDMTod; - m_pRDMTod->Reset(); - - Hardware::Get()->WatchdogFeed(); - - m_Message.SetPortID(static_cast(1 + nPortIndex)); - m_Message.SetDstUid(UID_ALL); - m_Message.SetCc(E120_DISCOVERY_COMMAND); - m_Message.SetPid(E120_DISC_UN_MUTE); - m_Message.SetPd(nullptr, 0); - m_Message.Send(m_nPortIndex); - m_Message.ReceiveTimeOut(m_nPortIndex, RECEIVE_TIME_OUT); - - Hardware::Get()->WatchdogFeed(); - udelay(RECEIVE_TIME_OUT); - Hardware::Get()->WatchdogFeed(); - - m_Message.Send(m_nPortIndex); - m_Message.ReceiveTimeOut(m_nPortIndex, RECEIVE_TIME_OUT); - - Hardware::Get()->WatchdogFeed(); - udelay(RECEIVE_TIME_OUT); - Hardware::Get()->WatchdogFeed(); - - FindDevices(0x000000000000, 0xfffffffffffe); - - m_pRDMTod->Dump(); - DEBUG_EXIT -} - -bool RDMDiscovery::FindDevices(uint64_t LowerBound, uint64_t UpperBound) { - Hardware::Get()->WatchdogFeed(); - - auto *pLateResponse __attribute__((unused)) = m_Message.Receive(m_nPortIndex); -#ifndef NDEBUG - if (pLateResponse != nullptr) { - printf("%d ", __LINE__); - RDMMessage::Print(pLateResponse); - } -#endif - -#ifndef NDEBUG - printf("FindDevices : "); - PrintUid(LowerBound); - printf(" - "); - PrintUid(UpperBound); - printf("\n"); -#endif - - uint8_t uid[RDM_UID_SIZE]; - struct TRdmMessage *pResponse; - - if (LowerBound == UpperBound) { - memcpy(uid, ConvertUid(LowerBound), RDM_UID_SIZE); - - m_Message.SetCc(E120_DISCOVERY_COMMAND); - m_Message.SetPid(E120_DISC_MUTE); - m_Message.SetDstUid(uid); - m_Message.SetPd(nullptr, 0); - - auto nRetry = 0; - - do { - if (++nRetry == 10) { - break; - } - - Hardware::Get()->WatchdogFeed(); - - m_Message.Send(m_nPortIndex, 5800); - pResponse = reinterpret_cast(const_cast(m_Message.ReceiveTimeOut(m_nPortIndex, RECEIVE_TIME_OUT))); - - if (pResponse != nullptr) { - if ((pResponse->command_class != E120_DISCOVERY_COMMAND_RESPONSE) || ((static_cast((pResponse->param_id[0] << 8) + pResponse->param_id[1])) != E120_DISC_MUTE)) { - continue; - } - } - } while (pResponse == nullptr); - - if (pResponse != nullptr) { -#ifndef NDEBUG - RDMMessage::Print(reinterpret_cast(pResponse)); -#endif - if ((pResponse->command_class == E120_DISCOVERY_COMMAND_RESPONSE) && (memcmp(uid, pResponse->source_uid, RDM_UID_SIZE) == 0)) { - m_pRDMTod->AddUid(uid); - } else { - #ifndef NDEBUG - printf("%d ", __LINE__); - PrintUid(uid); - printf("\n"); - #endif - } - } else { - return true; - } - } else { - memcpy(m_Pdl[0], ConvertUid(LowerBound), RDM_UID_SIZE); - memcpy(m_Pdl[1], ConvertUid(UpperBound), RDM_UID_SIZE); - - m_Message.SetDstUid(UID_ALL); - m_Message.SetCc(E120_DISCOVERY_COMMAND); - m_Message.SetPid(E120_DISC_UNIQUE_BRANCH); - m_Message.SetPd(reinterpret_cast(m_Pdl), 2 * RDM_UID_SIZE); - - auto nRetry = 0; - - do { - if (++nRetry == 3) { - break; - } - - Hardware::Get()->WatchdogFeed(); - - m_Message.Send(m_nPortIndex, 5800); - pResponse = reinterpret_cast(const_cast(m_Message.ReceiveTimeOut(m_nPortIndex, RECEIVE_TIME_OUT))); - - } while (pResponse == nullptr); - - if (pResponse != nullptr) { - auto bDeviceFound = true; - - if (IsValidDiscoveryResponse(reinterpret_cast(pResponse), uid)) { - bDeviceFound = QuickFind(uid); - } - - if (bDeviceFound) { - const uint64_t MidPosition = ((LowerBound & (0x0000800000000000 - 1)) + (UpperBound & (0x0000800000000000 - 1))) / 2 - + (UpperBound & (0x0000800000000000) ? 0x0000400000000000 : 0 ) - + (LowerBound & (0x0000800000000000) ? 0x0000400000000000 : 0 ); - - bDeviceFound = FindDevices(LowerBound, MidPosition); - bDeviceFound |= FindDevices(MidPosition + 1, UpperBound); - - if (bDeviceFound) { - return true; - } - } - } - } - - return false; -} - -const uint8_t *RDMDiscovery::ConvertUid(uint64_t nUid) { - uuid_cast.uint = __builtin_bswap64(nUid << 16); - return uuid_cast.uid; -} - -uint64_t RDMDiscovery::ConvertUid(const uint8_t *pUid) { - memcpy(uuid_cast.uid, pUid, RDM_UID_SIZE); - return __builtin_bswap64(uuid_cast.uint << 16); -} - -void RDMDiscovery::PrintUid(__attribute__((unused)) uint64_t nUid) { -#ifndef NDEBUG - PrintUid(ConvertUid(nUid)); -#endif -} - -void RDMDiscovery::PrintUid(__attribute__((unused)) const uint8_t *pUid) { -#ifndef NDEBUG - printf("%.2x%.2x:%.2x%.2x%.2x%.2x", pUid[0], pUid[1], pUid[2], pUid[3], pUid[4], pUid[5]); -#endif -} - -bool RDMDiscovery::IsValidDiscoveryResponse(const uint8_t *pDiscResponse, uint8_t *pUid) { - uint8_t checksum[2]; - uint16_t nRdmChecksum = 6 * 0xFF; - auto bIsValid = false; - - if (pDiscResponse[0] == 0xFE) { - pUid[0] = pDiscResponse[8] & pDiscResponse[9]; - pUid[1] = pDiscResponse[10] & pDiscResponse[11]; - - pUid[2] = pDiscResponse[12] & pDiscResponse[13]; - pUid[3] = pDiscResponse[14] & pDiscResponse[15]; - pUid[4] = pDiscResponse[16] & pDiscResponse[17]; - pUid[5] = pDiscResponse[18] & pDiscResponse[19]; - - checksum[0] = pDiscResponse[22] & pDiscResponse[23]; - checksum[1] = pDiscResponse[20] & pDiscResponse[21]; - - for (uint32_t i = 0; i < 6; i++) { - nRdmChecksum = static_cast(nRdmChecksum + pUid[i]); - } - - if (((nRdmChecksum >> 8) == checksum[1]) && ((nRdmChecksum & 0xFF) == checksum[0])) { - bIsValid = true; - } - -#ifndef NDEBUG - PrintUid(pUid); - printf(", checksum %.2x%.2x -> %.4x {%c}\n", checksum[1], checksum[0], nRdmChecksum, bIsValid ? 'Y' : 'N'); -#endif - - } else { -#ifndef NDEBUG - printf("%d ", __LINE__); - RDMMessage::Print(pDiscResponse); -#endif - } - - return bIsValid; -} - -bool RDMDiscovery::QuickFind(const uint8_t *uid) { - uint8_t r_uid[RDM_UID_SIZE]; - -#ifndef NDEBUG - printf("QuickFind : "); - PrintUid(uid); - printf("\n"); -#endif - - m_Message.SetCc(E120_DISCOVERY_COMMAND); - m_Message.SetPid(E120_DISC_MUTE); - m_Message.SetDstUid(uid); - m_Message.SetPd(nullptr, 0); - - TRdmMessage *pResponse; - - auto nRetry = 0; - - do { - if (++nRetry == 10) { - break; - } - - Hardware::Get()->WatchdogFeed(); - - m_Message.Send(m_nPortIndex, 5800); - pResponse = reinterpret_cast(const_cast(m_Message.ReceiveTimeOut(m_nPortIndex, RECEIVE_TIME_OUT))); - - if (pResponse != nullptr) { - if ((pResponse->command_class != E120_DISCOVERY_COMMAND_RESPONSE) || ((static_cast((pResponse->param_id[0] << 8) + pResponse->param_id[1])) != E120_DISC_MUTE)) { - continue; - } - } - } while (pResponse == nullptr); - - if (pResponse != nullptr) { -#ifndef NDEBUG - RDMMessage::Print(reinterpret_cast(pResponse)); -#endif - if ((pResponse->command_class == E120_DISCOVERY_COMMAND_RESPONSE) && (memcmp(uid, pResponse->source_uid, RDM_UID_SIZE) == 0)) { - m_pRDMTod->AddUid(uid); - } else { -#ifndef NDEBUG - printf("%d ", __LINE__); - PrintUid(uid); - printf("\n"); -#endif - } - } - - m_Message.SetDstUid(UID_ALL); - m_Message.SetCc(E120_DISCOVERY_COMMAND); - m_Message.SetPid(E120_DISC_UNIQUE_BRANCH); - m_Message.SetPd(reinterpret_cast(m_Pdl), 2 * RDM_UID_SIZE); - - nRetry = 0; - - do { - if (++nRetry == 3) { - break; - } - - Hardware::Get()->WatchdogFeed(); - - m_Message.Send(m_nPortIndex, 5800); - pResponse = reinterpret_cast(const_cast(m_Message.ReceiveTimeOut(m_nPortIndex, RECEIVE_TIME_OUT))); - - } while (pResponse == nullptr); - - - if ((pResponse != nullptr) && (IsValidDiscoveryResponse(reinterpret_cast(pResponse), r_uid))) { - QuickFind(r_uid); - } else if ((pResponse != nullptr) && (!IsValidDiscoveryResponse(reinterpret_cast(pResponse), r_uid))) { - return true; - } - - return false; -} diff --git a/lib-rdmnet/.cproject b/lib-rdmnet/.cproject deleted file mode 100644 index e870192a..00000000 --- a/lib-rdmnet/.cproject +++ /dev/null @@ -1,154 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/lib-rdmnet/.project b/lib-rdmnet/.project deleted file mode 100644 index cd6d5119..00000000 --- a/lib-rdmnet/.project +++ /dev/null @@ -1,27 +0,0 @@ - - - lib-rdmnet - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - diff --git a/lib-rdmnet/.settings/language.settings.xml b/lib-rdmnet/.settings/language.settings.xml deleted file mode 100644 index 0a846f1f..00000000 --- a/lib-rdmnet/.settings/language.settings.xml +++ /dev/null @@ -1,12 +0,0 @@ - - - - - - - - - - - - \ No newline at end of file diff --git a/lib-rdmnet/.settings/org.eclipse.cdt.core.prefs b/lib-rdmnet/.settings/org.eclipse.cdt.core.prefs deleted file mode 100644 index c8ec5df2..00000000 --- a/lib-rdmnet/.settings/org.eclipse.cdt.core.prefs +++ /dev/null @@ -1,6 +0,0 @@ -doxygen/doxygen_new_line_after_brief=true -doxygen/doxygen_use_brief_tag=false -doxygen/doxygen_use_javadoc_tags=true -doxygen/doxygen_use_pre_tag=false -doxygen/doxygen_use_structural_commands=false -eclipse.preferences.version=1 diff --git a/lib-rdmnet/.settings/org.eclipse.core.resources.prefs b/lib-rdmnet/.settings/org.eclipse.core.resources.prefs deleted file mode 100644 index 99f26c02..00000000 --- a/lib-rdmnet/.settings/org.eclipse.core.resources.prefs +++ /dev/null @@ -1,2 +0,0 @@ -eclipse.preferences.version=1 -encoding/=UTF-8 diff --git a/lib-rdmnet/Makefile.GD32 b/lib-rdmnet/Makefile.GD32 deleted file mode 100644 index b4683029..00000000 --- a/lib-rdmnet/Makefile.GD32 +++ /dev/null @@ -1,7 +0,0 @@ -DEFINES=NODE_RDMNET_LLRP_ONLY -DEFINES+=NDEBUG - - -EXTRA_INCLUDES=../lib-rdm/include ../lib-rdmsensor/include ../lib-rdmsubdevice/include ../lib-e131/include ../lib-network/include ../lib-lightset/include - -include ../firmware-template-gd32/lib/Rules.mk diff --git a/lib-rdmresponder/.cproject b/lib-rdmresponder/.cproject deleted file mode 100644 index 0fc7f3ce..00000000 --- a/lib-rdmresponder/.cproject +++ /dev/null @@ -1,150 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/lib-rdmresponder/.project b/lib-rdmresponder/.project deleted file mode 100644 index d5025250..00000000 --- a/lib-rdmresponder/.project +++ /dev/null @@ -1,27 +0,0 @@ - - - lib-rdmresponder - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - diff --git a/lib-rdmresponder/.settings/org.eclipse.cdt.core.prefs b/lib-rdmresponder/.settings/org.eclipse.cdt.core.prefs deleted file mode 100644 index c8ec5df2..00000000 --- a/lib-rdmresponder/.settings/org.eclipse.cdt.core.prefs +++ /dev/null @@ -1,6 +0,0 @@ -doxygen/doxygen_new_line_after_brief=true -doxygen/doxygen_use_brief_tag=false -doxygen/doxygen_use_javadoc_tags=true -doxygen/doxygen_use_pre_tag=false -doxygen/doxygen_use_structural_commands=false -eclipse.preferences.version=1 diff --git a/lib-rdmresponder/.settings/org.eclipse.core.resources.prefs b/lib-rdmresponder/.settings/org.eclipse.core.resources.prefs deleted file mode 100644 index 99f26c02..00000000 --- a/lib-rdmresponder/.settings/org.eclipse.core.resources.prefs +++ /dev/null @@ -1,2 +0,0 @@ -eclipse.preferences.version=1 -encoding/=UTF-8 diff --git a/lib-rdmresponder/Rules.mk b/lib-rdmresponder/Rules.mk deleted file mode 100644 index 19d62872..00000000 --- a/lib-rdmresponder/Rules.mk +++ /dev/null @@ -1,14 +0,0 @@ -EXTRA_INCLUDES+=../lib-rdm/include ../lib-rdmsensor/include ../lib-rdmsubdevice/include ../lib-lightset/include - -ifneq ($(MAKE_FLAGS),) - ifneq (,$(findstring NODE_ARTNET,$(MAKE_FLAGS))) - EXTRA_INCLUDES+=../lib-artnet/include - EXTRA_SRCDIR+=src/artnet - else - EXTRA_INCLUDES+=../lib-dmx/include ../lib-dmxreceiver/include - EXTRA_SRCDIR+=src/rdm - endif -else - EXTRA_INCLUDES+=../lib-dmx/include ../lib-dmxreceiver/include ../lib-artnet/include - EXTRA_SRCDIR+=src/rdm src/artnet -endif \ No newline at end of file diff --git a/lib-rdmresponder/include/rdmresponder.h b/lib-rdmresponder/include/rdmresponder.h deleted file mode 100644 index 03181e01..00000000 --- a/lib-rdmresponder/include/rdmresponder.h +++ /dev/null @@ -1,119 +0,0 @@ -/** - * @file rdmresponder.h - * - */ -/* Copyright (C) 2018-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef RDMRESPONDER_H_ -#define RDMRESPONDER_H_ - -#include -#include - -#include "dmxreceiver.h" - -#include "rdmhandler.h" -#include "rdmdeviceresponder.h" -#include "rdmpersonality.h" - -#include "lightset.h" - -#if defined (NODE_RDMNET_LLRP_ONLY) -# error "Cannot be both RDMNet Device and RDM Responder" -#endif - -namespace rdm { -namespace responder { -static constexpr auto NO_DATA = 0; -static constexpr auto DISCOVERY_RESPONSE = -1; -static constexpr auto INVALID_DATA_RECEIVED = -2; -static constexpr auto INVALID_RESPONSE = -3; -} // namespace responder -} // namespace rdm - -class RDMResponder final : DMXReceiver, public RDMDeviceResponder, RDMHandler { -public: - RDMResponder(RDMPersonality **pRDMPersonalities, uint32_t nPersonalityCount) : - DMXReceiver(pRDMPersonalities[rdm::device::responder::DEFAULT_CURRENT_PERSONALITY - 1]->GetLightSet()), - RDMDeviceResponder(pRDMPersonalities, nPersonalityCount) - { - assert(s_pThis == nullptr); - s_pThis = this; - } - - ~RDMResponder() override {} - - void Init() { - RDMDeviceResponder::Init(); - // There is no DMXReceiver::Init() - } - - int Run(); - - void Print() { - RDMDeviceResponder::Print(); - DMXReceiver::Print(); - } - - void Start() { - // There is no RDMDeviceResponder::Start() - DMXReceiver::Start(); - } - - void DmxDisableOutput(bool bDisable) { - DMXReceiver::SetDisableOutput(bDisable); - } - - uint16_t GetDmxStartAddress(uint16_t nSubDevice = RDM_ROOT_DEVICE) { - return RDMDeviceResponder::GetDmxStartAddress(nSubDevice); - } - - uint16_t GetDmxFootPrint(uint16_t nSubDevice = RDM_ROOT_DEVICE) { - return RDMDeviceResponder::GetDmxFootPrint(nSubDevice); - } - - static RDMResponder* Get() { - return s_pThis; - } - - void PersonalityUpdate(uint32_t nPersonality) __attribute__((weak)); - void DmxStartAddressUpdate(uint16_t nDmxStartAddress) __attribute__((weak)); - -private: - int HandleResponse(uint8_t *pResponse); - - void PersonalityUpdate(LightSet *pLightSet) override { - DMXReceiver::SetLightSet(pLightSet); - PersonalityUpdate(static_cast(RDMDeviceResponder::GetPersonalityCurrent(RDM_ROOT_DEVICE))); - } - - void DmxStartAddressUpdate() override { - DmxStartAddressUpdate(RDMDeviceResponder::GetDmxStartAddress(RDM_ROOT_DEVICE)); - } - -private: - static RDMResponder *s_pThis; - static TRdmMessage s_RdmCommand; - static bool m_IsSubDeviceActive; -}; - -#endif /* RDMRESPONDER_H_ */ diff --git a/lib-rdmresponder/src/artnet/artnetrdmresponder.cpp b/lib-rdmresponder/src/artnet/artnetrdmresponder.cpp deleted file mode 100644 index b8676b1b..00000000 --- a/lib-rdmresponder/src/artnet/artnetrdmresponder.cpp +++ /dev/null @@ -1,96 +0,0 @@ -/** - * @file artnetrdmresponder.cpp - * - */ -/* Copyright (C) 2018-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include - -#include "artnetrdmresponder.h" - -#include "rdmdeviceresponder.h" -#include "rdmhandler.h" -#include "rdmmessage.h" - -#include "lightset.h" - -#include "rdm.h" -#include "rdm_e120.h" - -#include "debug.h" - -namespace configstore { -void delay(); -} // namespace configstore - -ArtNetRdmResponder *ArtNetRdmResponder::s_pThis; -TRdmMessage ArtNetRdmResponder::s_RdmCommand; - -ArtNetRdmResponder::ArtNetRdmResponder(RDMPersonality **pRDMPersonalities, uint32_t nPersonalityCount) : - RDMDeviceResponder(pRDMPersonalities, nPersonalityCount) -{ - DEBUG_ENTRY - - assert(s_pThis == nullptr); - s_pThis = this; - - DEBUG_EXIT -} - -ArtNetRdmResponder::~ArtNetRdmResponder() { - DEBUG_ENTRY - - DEBUG_EXIT -} - -const uint8_t *ArtNetRdmResponder::Handler(uint32_t nPortIndex, const uint8_t *pRdmDataNoSC) { - DEBUG_ENTRY - - if (nPortIndex != 0) { - DEBUG_EXIT - return nullptr; - } - - if (pRdmDataNoSC == nullptr) { - DEBUG_EXIT - return nullptr; - } - -#ifndef NDEBUG - RDMMessage::PrintNoSc(pRdmDataNoSC); -#endif - - HandleData(pRdmDataNoSC, reinterpret_cast(&s_RdmCommand)); - - if (s_RdmCommand.start_code != E120_SC_RDM) { - DEBUG_EXIT - return nullptr; - } - -#ifndef NDEBUG - RDMMessage::Print(reinterpret_cast(&s_RdmCommand)); -#endif - - DEBUG_EXIT - return reinterpret_cast(&s_RdmCommand); -} diff --git a/lib-rdmresponder/src/rdm/rdmresponder.cpp b/lib-rdmresponder/src/rdm/rdmresponder.cpp deleted file mode 100644 index bd90fc6c..00000000 --- a/lib-rdmresponder/src/rdm/rdmresponder.cpp +++ /dev/null @@ -1,128 +0,0 @@ -/** - * @file rdmresponder.cpp - * - */ -/* Copyright (C) 2018-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include - -#include "rdmresponder.h" -#include "rdmdeviceresponder.h" -#include "rdmsubdevices.h" - -#include "dmxreceiver.h" - -#include "lightset.h" - -#include "rdm.h" -#include "rdm_e120.h" - -#include "debug.h" - -namespace configstore { -void delay(); -} // namespace configstore - -RDMResponder *RDMResponder::s_pThis; -TRdmMessage RDMResponder::s_RdmCommand; -bool RDMResponder::m_IsSubDeviceActive; - -using namespace rdm::responder; - -int RDMResponder::HandleResponse(uint8_t *pResponse) { - auto nLength = INVALID_RESPONSE; - - if (pResponse[0] == E120_SC_RDM) { - const auto *p = reinterpret_cast(pResponse); - nLength = static_cast(p->message_length + RDM_MESSAGE_CHECKSUM_SIZE); - Rdm::SendRawRespondMessage(0, pResponse, static_cast(nLength)); - } else if (pResponse[0] == 0xFE) { - nLength = sizeof(struct TRdmDiscoveryMsg); - Rdm::SendDiscoveryRespondMessage(0, pResponse, static_cast(nLength)); - } - -#ifndef NDEBUG - if (nLength != INVALID_RESPONSE) { - RDMMessage::Print(pResponse); - } -#endif - - configstore::delay(); - return nLength; -} - -int RDMResponder::Run() { - int16_t nLength; - - const auto *pDmxDataIn = DMXReceiver::Run(nLength); - - if (RDMSubDevices::Get()->GetCount() != 0) { - if (nLength == -1) { - if (m_IsSubDeviceActive) { - RDMSubDevices::Get()->Stop(); - m_IsSubDeviceActive = false; - } - } else if (pDmxDataIn != nullptr) { - RDMSubDevices::Get()->SetData(pDmxDataIn, static_cast(nLength)); - if (!m_IsSubDeviceActive) { - RDMSubDevices::Get()->Start(); - m_IsSubDeviceActive = true; - } - } - } - - const auto *pRdmDataIn = Rdm::Receive(0); - - if (pRdmDataIn == nullptr) { - return NO_DATA; - } - -#ifndef NDEBUG - RDMMessage::Print(pRdmDataIn); -#endif - - if (pRdmDataIn[0] == E120_SC_RDM) { - const auto *pRdmCommand = reinterpret_cast(pRdmDataIn); - - switch (pRdmCommand->command_class) { - case E120_DISCOVERY_COMMAND: - case E120_GET_COMMAND: - case E120_SET_COMMAND: - HandleData(&pRdmDataIn[1], reinterpret_cast(&s_RdmCommand)); - return HandleResponse(reinterpret_cast(&s_RdmCommand)); - break; - default: - DEBUG_PUTS("RDM_RESPONDER_INVALID_DATA_RECEIVED"); - return INVALID_DATA_RECEIVED; - break; - } - } - - DEBUG_PUTS("RDM_RESPONDER_DISCOVERY_RESPONSE"); - return DISCOVERY_RESPONSE; -} - -void __attribute__((weak)) RDMResponder::PersonalityUpdate(__attribute__((unused)) uint32_t nPersonality) { -} - -void __attribute__((weak))DmxStartAddressUpdate(__attribute__((unused)) uint16_t nDmxStartAddress) { -} diff --git a/lib-rdmsensor/.cproject b/lib-rdmsensor/.cproject index c5c68dc2..ea59a5fa 100644 --- a/lib-rdmsensor/.cproject +++ b/lib-rdmsensor/.cproject @@ -30,11 +30,9 @@ - diff --git a/lib-rdmsensor/Makefile.GD32 b/lib-rdmsensor/Makefile.GD32 index 38e2e7b6..5f6d2d93 100644 --- a/lib-rdmsensor/Makefile.GD32 +++ b/lib-rdmsensor/Makefile.GD32 @@ -1,5 +1,6 @@ DEFINES=NDEBUG -EXTRA_INCLUDES=../lib-rdm/include ../lib-properties/include ../lib-hal/include ../lib-device/include +EXTRA_INCLUDES= +include Rules.mk include ../firmware-template-gd32/lib/Rules.mk \ No newline at end of file diff --git a/lib-rdmsensor/Rules.mk b/lib-rdmsensor/Rules.mk new file mode 100755 index 00000000..fbe77089 --- /dev/null +++ b/lib-rdmsensor/Rules.mk @@ -0,0 +1,7 @@ +EXTRA_INCLUDES+=../lib-rdm/include ../lib-properties/include + +ifneq ($(MAKE_FLAGS),) + ifneq (,$(findstring CONFIG_STORE_USE_ROM,$(MAKE_FLAGS))) + EXTRA_INCLUDES+=../lib-flashcode/include + endif +endif \ No newline at end of file diff --git a/lib-ws28xxdmx/include/pixeldmxhandler.h b/lib-rdmsensor/include/rdm_sensors.h old mode 100644 new mode 100755 similarity index 71% rename from lib-ws28xxdmx/include/pixeldmxhandler.h rename to lib-rdmsensor/include/rdm_sensors.h index eed24e81..5bf8b044 --- a/lib-ws28xxdmx/include/pixeldmxhandler.h +++ b/lib-rdmsensor/include/rdm_sensors.h @@ -1,8 +1,8 @@ /** - * @file pixeldmxhandler.h + * @file rdm_sensors.h * */ -/* Copyright (C) 2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,16 +23,18 @@ * THE SOFTWARE. */ -#ifndef PIXELDMXHANDLER_H_ -#define PIXELDMXHANDLER_H_ +#ifndef RDM_SENSORS_H_ +#define RDM_SENSORS_H_ -class PixelDmxHandler { -public: - PixelDmxHandler() {} - virtual ~PixelDmxHandler() {} - - virtual void Start()=0; - virtual void Stop()=0; +namespace rdm { +namespace sensors { +enum class Types { + BH170, HTU21D, INA219, MCP9808, SI7021, MCP3424, UNDEFINED }; -#endif /* PIXELDMXHANDLER_H_ */ +const char *get_type_string(rdm::sensors::Types type); +rdm::sensors::Types get_type_string(const char *pValue); +} // namespace sensors +} // namespace rdm + +#endif /* RDM_SENSORS_H_ */ diff --git a/lib-rdmsensor/include/rdmsensor.h b/lib-rdmsensor/include/rdmsensor.h deleted file mode 100644 index 19fd433e..00000000 --- a/lib-rdmsensor/include/rdmsensor.h +++ /dev/null @@ -1,141 +0,0 @@ -/** - * @file rdmsensor.h - * - */ -/* Copyright (C) 2018-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef RDMSENSOR_H_ -#define RDMSENSOR_H_ - -#include - -namespace rdm { -namespace sensor { -struct Defintion { - uint8_t sensor; - uint8_t type; - uint8_t unit; - uint8_t prefix; - int16_t range_min; - int16_t range_max; - int16_t normal_min; - int16_t normal_max; - char description[32]; - uint8_t nLength; - uint8_t recorded_supported; -}; - -struct Values { - int16_t present; - int16_t lowest_detected; - int16_t highest_detected; - int16_t recorded; - uint8_t sensor_requested; -}; -static constexpr int16_t RANGE_MIN = -32768; -static constexpr int16_t RANGE_MAX = +32767; -static constexpr int16_t NORMAL_MIN = -32768; -static constexpr int16_t NORMAL_MAX = +32767; -static constexpr int16_t TEMPERATURE_ABS_ZERO = -273; - -template -constexpr int16_t safe_range_max(const T& a) -{ - static_assert(sizeof(int16_t) <= sizeof(T), "T"); - - return (a > static_cast(INT16_MAX)) ? INT16_MAX : static_cast(a); -} - -template -constexpr int16_t safe_range_min(const T& a) -{ - static_assert(sizeof(int16_t) <= sizeof(T), "T"); - - return (a < static_cast(INT16_MIN)) ? INT16_MIN : static_cast(a); -} - -} // namespace rdm -} // namespace sensor - - -class RDMSensor { -public: - RDMSensor(uint8_t nSensor); - virtual ~RDMSensor() {} - -public: - void SetType(uint8_t nType) { - m_tRDMSensorDefintion.type = nType; - } - - void SetUnit(uint8_t nUnit) { - m_tRDMSensorDefintion.unit = nUnit; - } - - void SetPrefix(uint8_t nPrefix) { - m_tRDMSensorDefintion.prefix = nPrefix; - } - - void SetRangeMin(int16_t nRangeMin) { - m_tRDMSensorDefintion.range_min = nRangeMin; - } - - void SetRangeMax(int16_t nRangeMax) { - m_tRDMSensorDefintion.range_max = nRangeMax; - } - - void SetNormalMin(int16_t nNormalMin) { - m_tRDMSensorDefintion.normal_min = nNormalMin; - } - - void SetNormalMax(int16_t nNormalMax) { - m_tRDMSensorDefintion.normal_max = nNormalMax; - } - - void SetDescription(const char *pDescription); - - void Print(); - - uint8_t GetSensor() const { - return m_nSensor; - } - - const struct rdm::sensor::Defintion* GetDefintion() { - return &m_tRDMSensorDefintion; - } - - const struct rdm::sensor::Values* GetValues(); - - void SetValues(); - - void Record(); - - virtual bool Initialize()=0; - virtual int16_t GetValue()=0; - -private: - uint8_t m_nSensor; - rdm::sensor::Defintion m_tRDMSensorDefintion; - rdm::sensor::Values m_tRDMSensorValues; -}; - -#endif /* RDMSENSOR_H_ */ diff --git a/lib-rdmsensor/include/rdmsensors.h b/lib-rdmsensor/include/rdmsensors.h deleted file mode 100644 index cdd1489a..00000000 --- a/lib-rdmsensor/include/rdmsensors.h +++ /dev/null @@ -1,91 +0,0 @@ -/** - * @file rdmsensors.h - * - */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef RDMSENSORS_H_ -#define RDMSENSORS_H_ - -#include - -#include "rdmsensor.h" -#include "rdmsensorsconst.h" - -#if defined (RASPPI) || defined(BARE_METAL) -# define RDM_SENSORS_ENABLE -#endif - -#if !defined (__CYGWIN__) && !defined (__APPLE__) -# define RDMSENSOR_CPU_ENABLE -#endif - -#if defined (NODE_RDMNET_LLRP_ONLY) -# undef RDM_SENSORS_ENABLE -# undef RDMSENSOR_CPU_ENABLE -#endif - -namespace rdm { -namespace sensors { -static constexpr auto MAX = 16; -static constexpr auto STORE = 64; ///< Configuration store in bytes -namespace devices { -static constexpr auto MAX = 8; -} // namespace devices -} // namespace sensors -} // namespace rdm - -class RDMSensors { -public: - RDMSensors(); - ~RDMSensors(); - - bool Add(RDMSensor *pRDMSensor); - - uint8_t GetCount() const { - return m_nCount; - } - - const struct rdm::sensor::Defintion* GetDefintion(uint8_t nSensor); - const struct rdm::sensor::Values* GetValues(uint8_t nSensor); - void SetValues(uint8_t nSensor); - void SetRecord(uint8_t nSensor); - - RDMSensor *GetSensor(uint8_t nSensor) { - return m_pRDMSensor[nSensor]; - } - - static const char *GetTypeString(rdm::sensors::Types type); - static rdm::sensors::Types GetTypeString(const char *pValue); - - static RDMSensors* Get() { - return s_pThis; - } - -private: - RDMSensor **m_pRDMSensor { nullptr }; - uint8_t m_nCount { 0 }; - - static RDMSensors *s_pThis; -}; - -#endif /* RDMSENSORS_H_ */ diff --git a/lib-rdmsensor/include/rdmsensorsconst.h b/lib-rdmsensor/include/rdmsensorsconst.h old mode 100644 new mode 100755 index eb3ef03f..436b6ebf --- a/lib-rdmsensor/include/rdmsensorsconst.h +++ b/lib-rdmsensor/include/rdmsensorsconst.h @@ -26,19 +26,8 @@ #ifndef RDMSENSORSCONST_H_ #define RDMSENSORSCONST_H_ -#include - -namespace rdm { -namespace sensors { -enum class Types { - BH170, HTU21D, INA219, MCP9808, SI7021, MCP3424, UNDEFINED -}; -} // namespace sensors -} // namespace rdmsensors - struct RDMSensorsConst { static const char PARAMS_FILE_NAME[]; - static const char TYPE[static_cast(rdm::sensors::Types::UNDEFINED)][8]; }; #endif /* RDMSENSORSCONST_H_ */ diff --git a/lib-rdmsensor/include/rdmsensorsparams.h b/lib-rdmsensor/include/rdmsensorsparams.h index c9a81b0a..1b117466 100644 --- a/lib-rdmsensor/include/rdmsensorsparams.h +++ b/lib-rdmsensor/include/rdmsensorsparams.h @@ -29,7 +29,7 @@ #include #include "rdmsensors.h" -#include "rdmsensorstore.h" +#include "configstore.h" namespace rdm { namespace sensorsparams { @@ -50,41 +50,37 @@ static_assert(sizeof(struct Params) <= rdm::sensors::STORE, "struct Params is to class RDMSensorsParamsStore { public: - virtual ~RDMSensorsParamsStore() {} + static void Update(const rdm::sensorsparams::Params *pParams) { + ConfigStore::Get()->Update(configstore::Store::RDMSENSORS, pParams, sizeof(struct rdm::sensorsparams::Params)); + } - virtual void Update(const rdm::sensorsparams::Params *pParams)=0; - virtual void Copy(rdm::sensorsparams::Params *pParams)=0; + static void Copy(rdm::sensorsparams::Params *pParams) { + ConfigStore::Get()->Copy(configstore::Store::RDMSENSORS, pParams, sizeof(struct rdm::sensorsparams::Params)); + } }; class RDMSensorsParams { public: - RDMSensorsParams(RDMSensorsParamsStore *pRDMSensorsParamsStore); + RDMSensorsParams(); - bool Load(); + void Load(); void Load(const char *pBuffer, uint32_t nLength); void Builder(const rdm::sensorsparams::Params *pParams, char *pBuffer, uint32_t nLength, uint32_t& nSize); void Save(char *pBuffer, uint32_t nLength, uint32_t& nSize) { - if (m_pRDMSensorsParamsStore == nullptr) { - nSize = 0; - return; - } - Builder(nullptr, pBuffer, nLength, nSize); } - void Dump(); - - void Set(RDMSensorStore *pRDMSensorStore = nullptr); + void Set(); static void staticCallbackFunction(void *p, const char *s); private: + void Dump(); void callbackFunction(const char *pLine); bool Add(RDMSensor *pRDMSensor); private: - RDMSensorsParamsStore *m_pRDMSensorsParamsStore; rdm::sensorsparams::Params m_Params; }; diff --git a/lib-configstore/include/storemidi.h b/lib-rdmsensor/include/rdmsensorsstore.h old mode 100644 new mode 100755 similarity index 63% rename from lib-configstore/include/storemidi.h rename to lib-rdmsensor/include/rdmsensorsstore.h index 96709bb3..4f45732a --- a/lib-configstore/include/storemidi.h +++ b/lib-rdmsensor/include/rdmsensorsstore.h @@ -1,8 +1,8 @@ /** - * @file storemidi.h + * @file rdmsensorsstore.h * */ -/* Copyright (C) 2019-2020 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,31 +23,24 @@ * THE SOFTWARE. */ -#ifndef STOREMIDI_H_ -#define STOREMIDI_H_ +#ifndef RDMSENSORSSTORE_H_ +#define RDMSENSORSSTORE_H_ -#include "midiparams.h" +#include +#include +#include +#include "rdmsensorsparams.h" +#include "rdmsensors.h" #include "configstore.h" -class StoreMidi final: public MidiParamsStore { +class RDMSensorsStore { public: - StoreMidi(); - - void Update(const struct TMidiParams *pMidiParams) override { - ConfigStore::Get()->Update(configstore::Store::MIDI, pMidiParams, sizeof(struct TMidiParams)); - } - - void Copy(struct TMidiParams *pMidiParams) override { - ConfigStore::Get()->Copy(configstore::Store::MIDI, pMidiParams, sizeof(struct TMidiParams)); + static void SaveCalibration(const uint32_t nSensor, const int32_t nCalibration) { + assert(nSensor < rdm::sensors::MAX); + auto c = static_cast(nCalibration); + ConfigStore::Get()->Update(configstore::Store::RDMSENSORS, (nSensor * sizeof(int16_t)) + offsetof(struct rdm::sensorsparams::Params, nCalibrate), &c, sizeof(int16_t)); } - - static StoreMidi *Get() { - return s_pThis; - } - -private: - static StoreMidi *s_pThis; }; -#endif /* STOREMIDI_H_ */ +#endif /* RDMSENSORSSTORE_H_ */ diff --git a/lib-rdmsensor/include/rdmsensorthermistor.h b/lib-rdmsensor/include/rdmsensorthermistor.h index b9f528d0..b0b4ade4 100644 --- a/lib-rdmsensor/include/rdmsensorthermistor.h +++ b/lib-rdmsensor/include/rdmsensorthermistor.h @@ -29,25 +29,24 @@ #include #include "rdmsensor.h" -#include "rdmsensorstore.h" +#include "rdmsensorsstore.h" +#include "rdm_e120.h" + #include "mcp3424.h" #include "thermistor.h" -#include "rdm_e120.h" - #include "debug.h" class RDMSensorThermistor final: public RDMSensor, MCP3424 { public: - RDMSensorThermistor(uint8_t nSensor, uint8_t nAddress = 0, uint8_t nChannel = 0, int32_t nCalibration = 0, RDMSensorStore *pRDMSensorStore = nullptr) : + RDMSensorThermistor(uint8_t nSensor, uint8_t nAddress = 0, uint8_t nChannel = 0, int32_t nCalibration = 0) : RDMSensor(nSensor), MCP3424(nAddress), m_nCalibration(nCalibration), - m_pRDMSensorStore(pRDMSensorStore), m_nChannel(nChannel) { DEBUG_ENTRY - DEBUG_PRINTF("nSensor=%u, nAddress=0x%.2x, nChannel=%u, nCalibration=%d, pRDMSensorStore=%p", nSensor, nAddress, nChannel, nCalibration, reinterpret_cast(pRDMSensorStore)); + DEBUG_PRINTF("nSensor=%u, nAddress=0x%.2x, nChannel=%u, nCalibration=%d", nSensor, nAddress, nChannel, nCalibration); SetType(E120_SENS_TEMPERATURE); SetUnit(E120_UNITS_CENTIGRADE); @@ -87,9 +86,7 @@ class RDMSensorThermistor final: public RDMSensor, MCP3424 { const auto iMeasure = static_cast(GetValue(nResistor) * 10); DEBUG_PRINTF("iCalibrate=%d, iMeasure=%d, m_nOffset=%d, nResistor=%u", iCalibrate, iMeasure, m_nCalibration, nResistor); if (iCalibrate == iMeasure) { - if (m_pRDMSensorStore != nullptr) { - m_pRDMSensorStore->SaveCalibration(RDMSensor::GetSensor(), m_nCalibration); - } + RDMSensorsStore::SaveCalibration(RDMSensor::GetSensor(), m_nCalibration); return true; } } @@ -99,9 +96,7 @@ class RDMSensorThermistor final: public RDMSensor, MCP3424 { void ResetCalibration() { m_nCalibration = 0; - if (m_pRDMSensorStore != nullptr) { - m_pRDMSensorStore->SaveCalibration(RDMSensor::GetSensor(), m_nCalibration); - } + RDMSensorsStore::SaveCalibration(RDMSensor::GetSensor(), m_nCalibration); } int32_t GetCalibration() const { @@ -129,7 +124,6 @@ class RDMSensorThermistor final: public RDMSensor, MCP3424 { private: int32_t m_nCalibration; - RDMSensorStore *m_pRDMSensorStore; uint8_t m_nChannel; /* diff --git a/lib-rdmsensor/src/rdm_sensors.cpp b/lib-rdmsensor/src/rdm_sensors.cpp new file mode 100755 index 00000000..49613690 --- /dev/null +++ b/lib-rdmsensor/src/rdm_sensors.cpp @@ -0,0 +1,58 @@ +/** + * @file rdm_sensors.cpp + * + */ +/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include + +#include "rdm_sensors.h" + +namespace rdm { +namespace sensors { +static constexpr char TYPE[static_cast(rdm::sensors::Types::UNDEFINED)][8] = { + "bh1750", "htu21d", "ina219", "mcp9808", "si7021", "mcp3424" }; + +const char *get_type_string(rdm::sensors::Types type) { + if (type < rdm::sensors::Types::UNDEFINED) { + return TYPE[static_cast(type)]; + } + + return "Unknown"; +} + +rdm::sensors::Types get_type_string(const char *pValue) { + assert(pValue != nullptr); + + for (uint32_t i = 0; i < static_cast(rdm::sensors::Types::UNDEFINED); i++) { + if (strcasecmp(pValue, TYPE[i]) == 0) { + return static_cast(i); + } + } + + return rdm::sensors::Types::UNDEFINED; +} +} // namespace sensors +} // namespace rdm + diff --git a/lib-rdmsensor/src/rdmsensor.cpp b/lib-rdmsensor/src/rdmsensor.cpp deleted file mode 100644 index d3e940c3..00000000 --- a/lib-rdmsensor/src/rdmsensor.cpp +++ /dev/null @@ -1,103 +0,0 @@ -/** - * @file rdmsensor.cpp - * - */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#include - -#include "rdmsensor.h" - -#include "debug.h" - -static constexpr uint8_t RDM_SENSOR_RECORDED_SUPPORTED = (1U << 0); -static constexpr uint8_t RDM_SENSOR_LOW_HIGH_DETECT = (1U << 1); - -RDMSensor::RDMSensor(uint8_t nSensor) : m_nSensor(nSensor) { - DEBUG_ENTRY - - m_tRDMSensorDefintion.sensor = m_nSensor; - m_tRDMSensorDefintion.recorded_supported = RDM_SENSOR_RECORDED_SUPPORTED | RDM_SENSOR_LOW_HIGH_DETECT; - - m_tRDMSensorValues.sensor_requested = m_nSensor; - m_tRDMSensorValues.lowest_detected = rdm::sensor::RANGE_MAX; - m_tRDMSensorValues.highest_detected = rdm::sensor::RANGE_MIN; - - DEBUG_EXIT -} - -void RDMSensor::SetDescription(const char *pDescription) { - DEBUG_ENTRY - - assert(pDescription != nullptr); - uint32_t i; - - for (i = 0; i < 32 && pDescription[i] != 0; i++) { - m_tRDMSensorDefintion.description[i] = pDescription[i]; - } - - m_tRDMSensorDefintion.nLength = static_cast(i); - - DEBUG_EXIT -} - -const struct rdm::sensor::Values* RDMSensor::GetValues() { - DEBUG_ENTRY - - const auto nValue = this->GetValue(); - - m_tRDMSensorValues.present = nValue; - m_tRDMSensorValues.lowest_detected = std::min(m_tRDMSensorValues.lowest_detected, nValue); - m_tRDMSensorValues.highest_detected = std::max(m_tRDMSensorValues.highest_detected, nValue); - - DEBUG_EXIT - - return &m_tRDMSensorValues; -} - -void RDMSensor::SetValues() { - DEBUG_ENTRY - - const auto nValue = this->GetValue(); - - m_tRDMSensorValues.present = nValue; - m_tRDMSensorValues.lowest_detected = nValue; - m_tRDMSensorValues.highest_detected = nValue; - m_tRDMSensorValues.recorded = nValue; - - DEBUG_EXIT -} - -void RDMSensor::Record() { - DEBUG_ENTRY - - const auto nValue = this->GetValue(); - - m_tRDMSensorValues.present = nValue; - m_tRDMSensorValues.recorded = nValue; - m_tRDMSensorValues.lowest_detected = std::min(m_tRDMSensorValues.lowest_detected, nValue); - m_tRDMSensorValues.highest_detected = std::max(m_tRDMSensorValues.highest_detected, nValue); - - DEBUG_EXIT -} diff --git a/lib-rdmsensor/src/rdmsensors.cpp b/lib-rdmsensor/src/rdmsensors.cpp deleted file mode 100644 index 86cd1a46..00000000 --- a/lib-rdmsensor/src/rdmsensors.cpp +++ /dev/null @@ -1,149 +0,0 @@ -/** - * @file rdmsensors.cpp - * - */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#include - -#include "rdmsensors.h" - -#include "debug.h" - -#if defined (RDMSENSOR_CPU_ENABLE) -# include "cputemperature.h" -#endif - -RDMSensors *RDMSensors::s_pThis = nullptr; - -RDMSensors::RDMSensors() { - DEBUG_ENTRY - - assert(s_pThis == nullptr); - s_pThis = this; - -#if defined (RDM_SENSORS_ENABLE) || defined (RDMSENSOR_CPU_ENABLE) - m_pRDMSensor = new RDMSensor*[rdm::sensors::MAX]; - assert(m_pRDMSensor != nullptr); - -# if defined (RDMSENSOR_CPU_ENABLE) - Add(new CpuTemperature(m_nCount)); -# endif -#endif - DEBUG_EXIT -} - -RDMSensors::~RDMSensors() { - DEBUG_ENTRY - - for (unsigned i = 0; i < m_nCount; i++) { - if (m_pRDMSensor[i] != nullptr) { - delete m_pRDMSensor[i]; - m_pRDMSensor[i] = nullptr; - } - } - - delete [] m_pRDMSensor; - - DEBUG_EXIT -} - -const struct rdm::sensor::Defintion* RDMSensors::GetDefintion(uint8_t nSensor) { - assert(nSensor < m_nCount); - - assert(m_pRDMSensor[nSensor] != nullptr); - return m_pRDMSensor[nSensor]->GetDefintion(); -} - -const struct rdm::sensor::Values* RDMSensors::GetValues(uint8_t nSensor) { - assert(nSensor < m_nCount); - - assert(m_pRDMSensor[nSensor] != nullptr); - return m_pRDMSensor[nSensor]->GetValues(); -} - -void RDMSensors::SetValues(uint8_t nSensor) { - if (nSensor == 0xFF) { - for (uint32_t i = 0; i < m_nCount; i++) { - m_pRDMSensor[i]->SetValues(); - } - } else { - m_pRDMSensor[nSensor]->SetValues(); - } -} - -void RDMSensors::SetRecord(uint8_t nSensor) { - if (nSensor == 0xFF) { - for (uint32_t i = 0; i < m_nCount; i++) { - m_pRDMSensor[i]->Record(); - } - } else { - m_pRDMSensor[nSensor]->Record(); - } -} - -bool RDMSensors::Add(RDMSensor *pRDMSensor) { - DEBUG_ENTRY - - assert(m_pRDMSensor != nullptr); - - if (m_pRDMSensor == nullptr) { - DEBUG_EXIT - return false; - } - - if (m_nCount == rdm::sensors::MAX) { - DEBUG_EXIT - return false; - } - - assert(pRDMSensor != nullptr); - m_pRDMSensor[m_nCount++] = pRDMSensor; - - DEBUG_PRINTF("m_nCount=%u", m_nCount); - DEBUG_EXIT - return true; -} - -// Static - -const char* RDMSensors::GetTypeString(rdm::sensors::Types type) { - if (type < rdm::sensors::Types::UNDEFINED) { - return RDMSensorsConst::TYPE[static_cast(type)]; - } - - return "Unknown"; -} - -rdm::sensors::Types RDMSensors::GetTypeString(const char *pValue) { - assert(pValue != nullptr); - - for (uint32_t i = 0; i < static_cast(rdm::sensors::Types::UNDEFINED); i++) { - if (strcasecmp(pValue, RDMSensorsConst::TYPE[i]) == 0) { - return static_cast(i); - } - } - - return rdm::sensors::Types::UNDEFINED; -} diff --git a/lib-rdmsensor/src/rdmsensorsconst.cpp b/lib-rdmsensor/src/rdmsensorsconst.cpp index 99b023c0..34c2bdcf 100644 --- a/lib-rdmsensor/src/rdmsensorsconst.cpp +++ b/lib-rdmsensor/src/rdmsensorsconst.cpp @@ -28,6 +28,3 @@ #include "rdmsensorsconst.h" const char RDMSensorsConst::PARAMS_FILE_NAME[] = "sensors.txt"; - -const char RDMSensorsConst::TYPE[static_cast(rdm::sensors::Types::UNDEFINED)][8] = { - "bh1750", "htu21d", "ina219", "mcp9808", "si7021", "mcp3424" }; diff --git a/lib-rdmsensor/src/rdmsensorsparams.cpp b/lib-rdmsensor/src/rdmsensorsparams.cpp index 9db6abc1..0c63adf0 100644 --- a/lib-rdmsensor/src/rdmsensorsparams.cpp +++ b/lib-rdmsensor/src/rdmsensorsparams.cpp @@ -2,7 +2,7 @@ * @file rdmsensorsparams.cpp * */ -/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -35,28 +35,41 @@ #include "rdmsensorsparams.h" #include "rdmsensors.h" -#include "rdmsensorstore.h" +#include "rdmsensorsconst.h" +#include "rdm_sensors.h" #include "readconfigfile.h" #include "sscan.h" #include "propertiesbuilder.h" #if defined (RDM_SENSORS_ENABLE) -# include "rdmsensorbh1750.h" -# include "rdmsensormcp9808.h" -# include "rdmsensorhtu21dhumidity.h" -# include "rdmsensorhtu21dtemperature.h" -# include "rdmsensorina219current.h" -# include "rdmsensorina219power.h" -# include "rdmsensorina219voltage.h" -# include "rdmsensorsi7021humidity.h" -# include "rdmsensorsi7021temperature.h" -# include "rdmsensorthermistor.h" +# if !defined (CONFIG_RDM_SENSORS_DISABLE_BH170) +# include "rdmsensorbh1750.h" +# endif +# if !defined (CONFIG_RDM_SENSORS_DISABLE_MCP9808) +# include "rdmsensormcp9808.h" +# endif +# if !defined (CONFIG_RDM_SENSORS_DISABLE_HTU21D) +# include "rdmsensorhtu21dhumidity.h" +# include "rdmsensorhtu21dtemperature.h" +# endif +# if !defined (CONFIG_RDM_SENSORS_DISABLE_INA219) +# include "rdmsensorina219current.h" +# include "rdmsensorina219power.h" +# include "rdmsensorina219voltage.h" +# endif +# if !defined (CONFIG_RDM_SENSORS_DISABLE_SI7021) +# include "rdmsensorsi7021humidity.h" +# include "rdmsensorsi7021temperature.h" +# endif +# if !defined (CONFIG_RDM_SENSORS_DISABLE_THERMISTOR) +# include "rdmsensorthermistor.h" +# endif #endif #include "debug.h" -RDMSensorsParams::RDMSensorsParams(RDMSensorsParamsStore *pRDMSensorsParamsStore): m_pRDMSensorsParamsStore(pRDMSensorsParamsStore) { +RDMSensorsParams::RDMSensorsParams() { DEBUG_ENTRY memset(&m_Params, 0, sizeof(struct rdm::sensorsparams::Params)); @@ -64,7 +77,7 @@ RDMSensorsParams::RDMSensorsParams(RDMSensorsParamsStore *pRDMSensorsParamsStore DEBUG_EXIT } -bool RDMSensorsParams::Load() { +void RDMSensorsParams::Load() { DEBUG_ENTRY m_Params.nDevices = 0; @@ -73,24 +86,20 @@ bool RDMSensorsParams::Load() { ReadConfigFile configfile(RDMSensorsParams::staticCallbackFunction, this); if (configfile.Read(RDMSensorsConst::PARAMS_FILE_NAME)) { - if (m_pRDMSensorsParamsStore != nullptr) { - m_pRDMSensorsParamsStore->Update(&m_Params); - } + RDMSensorsParamsStore::Update(&m_Params); } else #endif - if (m_pRDMSensorsParamsStore != nullptr) { - m_pRDMSensorsParamsStore->Copy(&m_Params); - // Sanity check - if (m_Params.nDevices >= rdm::sensors::devices::MAX) { - memset(&m_Params, 0, sizeof(struct rdm::sensorsparams::Params)); - } - } else { - DEBUG_EXIT - return false; + RDMSensorsParamsStore::Copy(&m_Params); + + // Sanity check + if (m_Params.nDevices >= rdm::sensors::devices::MAX) { + memset(&m_Params, 0, sizeof(struct rdm::sensorsparams::Params)); } +#ifndef NDEBUG + Dump(); +#endif DEBUG_EXIT - return true; } void RDMSensorsParams::Load(const char *pBuffer, uint32_t nLength) { @@ -98,12 +107,6 @@ void RDMSensorsParams::Load(const char *pBuffer, uint32_t nLength) { assert(pBuffer != nullptr); assert(nLength != 0); - assert(m_pRDMSensorsParamsStore != nullptr); - - if (m_pRDMSensorsParamsStore == nullptr) { - DEBUG_EXIT - return; - } m_Params.nDevices = 0; @@ -111,8 +114,11 @@ void RDMSensorsParams::Load(const char *pBuffer, uint32_t nLength) { config.Read(pBuffer, nLength); - m_pRDMSensorsParamsStore->Update(&m_Params); + RDMSensorsParamsStore::Update(&m_Params); +#ifndef NDEBUG + Dump(); +#endif DEBUG_EXIT } @@ -124,20 +130,19 @@ void RDMSensorsParams::Builder(const rdm::sensorsparams::Params *pParams, char * if (pParams != nullptr) { memcpy(&m_Params, pParams, sizeof(struct rdm::sensorsparams::Params)); } else { - assert(m_pRDMSensorsParamsStore != nullptr); - m_pRDMSensorsParamsStore->Copy(&m_Params); + RDMSensorsParamsStore::Copy(&m_Params); } PropertiesBuilder builder(RDMSensorsConst::PARAMS_FILE_NAME, pBuffer, nLength); for (uint32_t i = 0; i < static_cast(rdm::sensors::Types::UNDEFINED); i++) { - builder.AddHex8(RDMSensors::GetTypeString(static_cast(i)), 0xFF, false); + builder.AddHex8(rdm::sensors::get_type_string(static_cast(i)), 0xFF, false); } for (uint32_t i = 0; i < m_Params.nDevices; i++) { const auto type = static_cast(m_Params.Entry[i].nType); if (type < rdm::sensors::Types::UNDEFINED) { - builder.AddHex8(RDMSensors::GetTypeString(type), m_Params.Entry[i].nAddress, true); + builder.AddHex8(rdm::sensors::get_type_string(type), m_Params.Entry[i].nAddress, true); } } @@ -147,20 +152,6 @@ void RDMSensorsParams::Builder(const rdm::sensorsparams::Params *pParams, char * DEBUG_EXIT } -void RDMSensorsParams::Dump() { -#ifndef NDEBUG - printf("%s::%s \'%s\':\n", __FILE__, __FUNCTION__, RDMSensorsConst::PARAMS_FILE_NAME); - - for (uint32_t i = 0; i < m_Params.nDevices; i++) { - printf(" %s 0x%.2x\n", RDMSensors::GetTypeString(static_cast(m_Params.Entry[i].nType)), m_Params.Entry[i].nAddress); - } - - for (uint32_t i = 0; i < rdm::sensors::MAX; i++) { - printf("%2d %d\n", i, m_Params.nCalibrate[i]); - } -#endif -} - bool RDMSensorsParams::Add(RDMSensor *pRDMSensor) { DEBUG_ENTRY @@ -176,7 +167,7 @@ bool RDMSensorsParams::Add(RDMSensor *pRDMSensor) { return false; } -void RDMSensorsParams::Set(__attribute__((unused)) RDMSensorStore *pRDMSensorStore) { +void RDMSensorsParams::Set() { #if defined (RDM_SENSORS_ENABLE) DEBUG_ENTRY @@ -185,15 +176,20 @@ void RDMSensorsParams::Set(__attribute__((unused)) RDMSensorStore *pRDMSensorSto const auto nAddress = m_Params.Entry[i].nAddress; switch (static_cast(m_Params.Entry[i].nType)) { +#if !defined (CONFIG_RDM_SENSORS_DISABLE_BH170) case rdm::sensors::Types::BH170: Add(new RDMSensorBH170(nSensorNumber, nAddress)); break; +#endif +#if !defined (CONFIG_RDM_SENSORS_DISABLE_HTU21D) case rdm::sensors::Types::HTU21D: if (!Add(new RDMSensorHTU21DHumidity(nSensorNumber++, nAddress))) { continue; } Add(new RDMSensorHTU21DTemperature(nSensorNumber, nAddress)); break; +#endif +#if !defined (CONFIG_RDM_SENSORS_DISABLE_INA219) case rdm::sensors::Types::INA219: if (!Add(new RDMSensorINA219Current(nSensorNumber++, nAddress))) { continue; @@ -203,30 +199,37 @@ void RDMSensorsParams::Set(__attribute__((unused)) RDMSensorStore *pRDMSensorSto } Add(new RDMSensorINA219Voltage(nSensorNumber, nAddress)); break; +#endif +#if !defined (CONFIG_RDM_SENSORS_DISABLE_MCP9808) case rdm::sensors::Types::MCP9808: Add(new RDMSensorMCP9808(nSensorNumber, nAddress)); break; +#endif +#if !defined (CONFIG_RDM_SENSORS_DISABLE_SI7021) case rdm::sensors::Types::SI7021: if (!Add(new RDMSensorSI7021Humidity(nSensorNumber++, nAddress))) { continue; } Add(new RDMSensorSI7021Temperature(nSensorNumber, nAddress)); break; +#endif +#if !defined (CONFIG_RDM_SENSORS_DISABLE_THERMISTOR) case rdm::sensors::Types::MCP3424: - if (!Add(new RDMSensorThermistor(nSensorNumber, nAddress, 0, m_Params.nCalibrate[nSensorNumber], pRDMSensorStore))) { + if (!Add(new RDMSensorThermistor(nSensorNumber, nAddress, 0, m_Params.nCalibrate[nSensorNumber]))) { continue; } nSensorNumber++; - if (!Add(new RDMSensorThermistor(nSensorNumber, nAddress, 1, m_Params.nCalibrate[nSensorNumber], pRDMSensorStore))) { + if (!Add(new RDMSensorThermistor(nSensorNumber, nAddress, 1, m_Params.nCalibrate[nSensorNumber]))) { continue; } nSensorNumber++; - if (!Add(new RDMSensorThermistor(nSensorNumber, nAddress, 2, m_Params.nCalibrate[nSensorNumber], pRDMSensorStore))) { + if (!Add(new RDMSensorThermistor(nSensorNumber, nAddress, 2, m_Params.nCalibrate[nSensorNumber]))) { continue; } nSensorNumber++; - Add(new RDMSensorThermistor(nSensorNumber, nAddress, 3, m_Params.nCalibrate[nSensorNumber], pRDMSensorStore)); + Add(new RDMSensorThermistor(nSensorNumber, nAddress, 3, m_Params.nCalibrate[nSensorNumber])); break; +#endif default: break; } @@ -257,7 +260,7 @@ void RDMSensorsParams::callbackFunction(const char *pLine) { rdm::sensors::Types sensorType; - if ((sensorType = RDMSensors::GetTypeString(aSensorName)) == rdm::sensors::Types::UNDEFINED) { + if ((sensorType = rdm::sensors::get_type_string(aSensorName)) == rdm::sensors::Types::UNDEFINED) { return; } @@ -285,3 +288,15 @@ void RDMSensorsParams::staticCallbackFunction(void *p, const char *s) { (static_cast(p))->callbackFunction(s); } + +void RDMSensorsParams::Dump() { + printf("%s::%s \'%s\':\n", __FILE__, __FUNCTION__, RDMSensorsConst::PARAMS_FILE_NAME); + + for (uint32_t i = 0; i < m_Params.nDevices; i++) { + printf(" %s 0x%.2x\n", rdm::sensors::get_type_string(static_cast(m_Params.Entry[i].nType)), m_Params.Entry[i].nAddress); + } + + for (uint32_t i = 0; i < rdm::sensors::MAX; i++) { + printf("%2u %u\n", static_cast(i), static_cast(m_Params.nCalibrate[i])); + } +} diff --git a/lib-rdmsubdevice/.cproject b/lib-rdmsubdevice/.cproject index fd0bdca1..ea7fb6f9 100644 --- a/lib-rdmsubdevice/.cproject +++ b/lib-rdmsubdevice/.cproject @@ -30,11 +30,9 @@ - diff --git a/lib-rdmsubdevice/Makefile.GD32 b/lib-rdmsubdevice/Makefile.GD32 index 09035619..d190dcc0 100644 --- a/lib-rdmsubdevice/Makefile.GD32 +++ b/lib-rdmsubdevice/Makefile.GD32 @@ -1,7 +1,8 @@ DEFINES=NDEBUG -EXTRA_INCLUDES=../lib-rdm/include ../lib-lightset/include ../lib-properties/include +EXTRA_INCLUDES= EXTRA_SRCDIR= +include Rules.mk include ../firmware-template-gd32/lib/Rules.mk diff --git a/lib-rdmsubdevice/Rules.mk b/lib-rdmsubdevice/Rules.mk new file mode 100755 index 00000000..9b5ba69b --- /dev/null +++ b/lib-rdmsubdevice/Rules.mk @@ -0,0 +1,18 @@ +EXTRA_INCLUDES+=../lib-rdm/include ../lib-lightset/include ../lib-properties/include + +ifneq ($(MAKE_FLAGS),) + ifeq ($(findstring CONFIG_RDM_ENABLE_SUBDEVICES,$(MAKE_FLAGS)), CONFIG_RDM_ENABLE_SUBDEVICES) + ifeq ($(findstring CONFIG_RDM_SUBDEVICES_USE_SPI,$(MAKE_FLAGS)), CONFIG_RDM_SUBDEVICES_USE_SPI) + EXTRA_SRCDIR+=src/spi + endif + ifeq ($(findstring CONFIG_RDM_SUBDEVICES_USE_I2C,$(MAKE_FLAGS)), CONFIG_RDM_SUBDEVICES_USE_I2C) + EXTRA_SRCDIR+=src/i2c + endif + endif + ifneq (,$(findstring CONFIG_STORE_USE_ROM,$(MAKE_FLAGS))) + EXTRA_INCLUDES+=../lib-flashcode/include + endif +else + DEFINES+=CONFIG_RDM_ENABLE_SUBDEVICES CONFIG_RDM_SUBDEVICES_USE_I2C CONFIG_RDM_SUBDEVICES_USE_SPI + EXTRA_SRCDIR+=src/i2c src/spi +endif \ No newline at end of file diff --git a/lib-rdmsubdevice/include/rdm _subdevices.h b/lib-rdmsubdevice/include/rdm _subdevices.h new file mode 100755 index 00000000..4dfe27f3 --- /dev/null +++ b/lib-rdmsubdevice/include/rdm _subdevices.h @@ -0,0 +1,43 @@ +/** + * @file rdm_subdevices.h + * + */ +/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RDM_SUBDEVICES_H_ +#define RDM_SUBDEVICES_H_ + +namespace rdm { +namespace subdevices { +enum class Types { + BW7FETS, BWDIMMER, BWDIO, BWLCD, BWRELAY, // BitWizard + MCP23S08, MCP23S17, // GPIO + MCP4822, MCP4902, // DAC + UNDEFINED +}; + +const char* get_type_string(rdm::subdevices::Types type); +rdm::subdevices::Types get_type_string(const char *pValue); +} // namespace subdevices +} // namespace rdm + +#endif /* RDM_SUBDEVICES_H_ */ diff --git a/lib-rdmsubdevice/include/rdmsubdevice.h b/lib-rdmsubdevice/include/rdmsubdevice.h deleted file mode 100644 index fd76abd0..00000000 --- a/lib-rdmsubdevice/include/rdmsubdevice.h +++ /dev/null @@ -1,108 +0,0 @@ -/** - * @file rdmsubdevice.h - * - */ -/* Copyright (C) 2018-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef RDMSUBDEVICE_H_ -#define RDMSUBDEVICE_H_ - -#include "rdmdevice.h" -#include "rdmpersonality.h" - -struct TRDMSubDevicesInfo { - uint16_t dmx_footprint; - uint16_t dmx_start_address; - uint8_t current_personality; - uint8_t personality_count; - char aLabel[RDM_DEVICE_LABEL_MAX_LENGTH]; - uint8_t nLabelLength; - uint8_t sensor_count; -}; - -enum TRDMSubDeviceUpdateEvent { - RDM_SUBDEVICE_UPDATE_EVENT_DMX_STARTADDRESS, - RDM_SUBDEVICE_UPDATE_EVENT_PERSONALITY -}; - -class RDMSubDevice { -public: - RDMSubDevice(const char* pLabel, uint16_t nDmxStartAddress = 1, uint8_t PersonalitynCurrent = 1); - virtual ~RDMSubDevice(); - - void SetDmxStartAddress(uint16_t nDmxStartAddress); - - uint16_t GetDmxStartAddress() const { - return m_tSubDevicesInfo.dmx_start_address; - } - - uint8_t GetPersonalityCurrent() const { - return m_tSubDevicesInfo.current_personality; - } - void SetPersonalityCurrent(uint8_t nCurrent); - - void GetLabel(struct TRDMDeviceInfoData *pInfoData); - void SetLabel(const char *pLabel); - void SetLabel(const char *pLabel, uint8_t nLabelLength); - - struct TRDMSubDevicesInfo* GetInfo() { - return &m_tSubDevicesInfo; - } - - RDMPersonality* GetPersonality(uint8_t nPersonality); - - uint8_t GetPersonalityCount() const { - return m_tSubDevicesInfo.personality_count; - } - - uint16_t GetDmxFootPrint() const { - return m_tSubDevicesInfo.dmx_footprint; - } - - bool GetFactoryDefaults(); - void SetFactoryDefaults(); - - virtual bool Initialize()=0; - - virtual void Start()= 0; - virtual void Stop()= 0; - virtual void Data(const uint8_t *pDdata, uint32_t nLength)=0; - -protected: - void SetDmxFootprint(uint16_t nDmxFootprint); - void SetPersonalities(RDMPersonality **pRDMPersonalities, uint8_t nPersonalityCount); - -private: - virtual void UpdateEvent(TRDMSubDeviceUpdateEvent tUpdateEvent); - uint16_t CalculateChecksum(); - -private: - RDMPersonality **m_pRDMPersonalities { nullptr }; - bool m_IsFactoryDefaults { true }; - uint16_t m_nCheckSum { 0 }; - uint16_t m_nDmxStartAddressFactoryDefault; - uint8_t m_nCurrentPersonalityFactoryDefault; - TRDMSubDevicesInfo m_tSubDevicesInfo; - char m_aLabelFactoryDefault[RDM_DEVICE_LABEL_MAX_LENGTH]; -}; - -#endif /* RDMSUBDEVICE_H_ */ diff --git a/lib-rdmsubdevice/include/rdmsubdevices.h b/lib-rdmsubdevice/include/rdmsubdevices.h deleted file mode 100644 index e080bfd4..00000000 --- a/lib-rdmsubdevice/include/rdmsubdevices.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - * @file rdmsubdevices.h - * - */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef RDMSUBDEVICES_H_ -#define RDMSUBDEVICES_H_ - -#include - -#include "rdmsubdevice.h" -#include "rdmsubdevicesconst.h" - -#include "rdmpersonality.h" - -#if defined (NODE_RDMNET_LLRP_ONLY) -# undef ENABLE_RDM_SUBDEVICES -#endif - -namespace rdm { -namespace subdevices { -static constexpr auto MAX = 8; -static constexpr auto STORE = 96; ///< Configuration store in bytes -} // namespace subdevices -} // namespace rdm - -class RDMSubDevices { -public: - RDMSubDevices(); - ~RDMSubDevices(); - - bool Add(RDMSubDevice *pRDMSubDevice); - - uint16_t GetCount() const { - return m_nCount; - } - - TRDMSubDevicesInfo *GetInfo(uint16_t nSubDevice); - - uint16_t GetDmxFootPrint(uint16_t nSubDevice); - - RDMPersonality* GetPersonality(uint16_t nSubDevice , uint8_t nPersonality); - uint8_t GetPersonalityCount(uint16_t nSubDevice); - uint8_t GetPersonalityCurrent(uint16_t nSubDevice); - void SetPersonalityCurrent(uint16_t nSubDevice, uint8_t nPersonality); - - // E120_DEVICE_LABEL 0x0082 - void GetLabel(uint16_t nSubDevice, TRDMDeviceInfoData *pInfoData); - void SetLabel(uint16_t nSubDevice, const char *pLabel, uint8_t nLabelLength); - - // E120_FACTORY_DEFAULTS 0x0090 - bool GetFactoryDefaults(); - void SetFactoryDefaults(); - - // E120_DMX_START_ADDRESS 0x00F0 - uint16_t GetDmxStartAddress(uint16_t nSubDevice); - void SetDmxStartAddress(uint16_t nSubDevice, uint16_t nDmxStartAddress); - - void Start(); - void Stop(); - void SetData(const uint8_t *pData, uint32_t nLength); - - static const char *GetTypeString(rdm::subdevices::Types tType); - static rdm::subdevices::Types GetTypeString(const char *pValue); - - static RDMSubDevices* Get() { - return s_pThis; - } - -private: - RDMSubDevice **m_pRDMSubDevice { nullptr }; - uint16_t m_nCount { 0 }; - - static RDMSubDevices *s_pThis; -}; - -#endif /* RDMSUBDEVICES_H_ */ diff --git a/lib-rdmsubdevice/include/rdmsubdevicesconst.h b/lib-rdmsubdevice/include/rdmsubdevicesconst.h old mode 100644 new mode 100755 index 847e1e9a..3a234529 --- a/lib-rdmsubdevice/include/rdmsubdevicesconst.h +++ b/lib-rdmsubdevice/include/rdmsubdevicesconst.h @@ -26,22 +26,8 @@ #ifndef RDMSUBDEVICESCONST_H_ #define RDMSUBDEVICESCONST_H_ -#include - -namespace rdm { -namespace subdevices { -enum class Types { - BW7FETS, BWDIMMER, BWDIO, BWLCD, BWRELAY, // BitWizard - MCP23S08, MCP23S17, // GPIO - MCP4822, MCP4902, // DAC - UNDEFINED -}; -} // namespace subdevices -} // namespace rdm - struct RDMSubDevicesConst { static const char PARAMS_FILE_NAME[]; - static const char TYPE[static_cast(rdm::subdevices::Types::UNDEFINED)][9]; }; #endif /* RDMSUBDEVICESCONST_H_ */ diff --git a/lib-rdmsubdevice/include/rdmsubdevicesparams.h b/lib-rdmsubdevice/include/rdmsubdevicesparams.h index 92d3f30f..4906ee86 100644 --- a/lib-rdmsubdevice/include/rdmsubdevicesparams.h +++ b/lib-rdmsubdevice/include/rdmsubdevicesparams.h @@ -29,6 +29,7 @@ #include #include "rdmsubdevices.h" +#include "configstore.h" namespace rdm { namespace subdevicesparams { @@ -50,41 +51,37 @@ static_assert(sizeof(struct Params) <= rdm::subdevices::STORE, "struct Params is class RDMSubDevicesParamsStore { public: - virtual ~RDMSubDevicesParamsStore() {} + static void Update(const rdm::subdevicesparams::Params *pParams) { + ConfigStore::Get()->Update(configstore::Store::RDMSUBDEVICES, pParams, sizeof(struct rdm::subdevicesparams::Params)); + } - virtual void Update(const rdm::subdevicesparams::Params *pParams)=0; - virtual void Copy(rdm::subdevicesparams::Params *pParams)=0; + static void Copy(rdm::subdevicesparams::Params *pParams) { + ConfigStore::Get()->Copy(configstore::Store::RDMSUBDEVICES, pParams, sizeof(struct rdm::subdevicesparams::Params)); + } }; class RDMSubDevicesParams { public: - RDMSubDevicesParams(RDMSubDevicesParamsStore *pRDMSubDevicesParamsStore); + RDMSubDevicesParams(); - bool Load(); + void Load(); void Load(const char *pBuffer, uint32_t nLength); void Builder(const rdm::subdevicesparams::Params *pParams, char *pBuffer, uint32_t nLength, uint32_t& nSize); void Save(char *pBuffer, uint32_t nLength, uint32_t& nSize) { - if (m_pRDMSubDevicesParamsStore == nullptr) { - nSize = 0; - return; - } - Builder(nullptr, pBuffer, nLength, nSize); } - void Dump(); - void Set(); static void staticCallbackFunction(void *p, const char *s); private: + void Dump(); void callbackFunction(const char *pLine); bool Add(RDMSubDevice *pRDMSubDevice); private: - RDMSubDevicesParamsStore *m_pRDMSubDevicesParamsStore; rdm::subdevicesparams::Params m_Params; }; diff --git a/lib-rdmsubdevice/include/rdmsubdevicebw7fets.h b/lib-rdmsubdevice/include/spi/rdmsubdevicebw7fets.h similarity index 100% rename from lib-rdmsubdevice/include/rdmsubdevicebw7fets.h rename to lib-rdmsubdevice/include/spi/rdmsubdevicebw7fets.h diff --git a/lib-rdmsubdevice/include/rdmsubdevicebwdimmer.h b/lib-rdmsubdevice/include/spi/rdmsubdevicebwdimmer.h similarity index 100% rename from lib-rdmsubdevice/include/rdmsubdevicebwdimmer.h rename to lib-rdmsubdevice/include/spi/rdmsubdevicebwdimmer.h diff --git a/lib-rdmsubdevice/include/rdmsubdevicebwdio.h b/lib-rdmsubdevice/include/spi/rdmsubdevicebwdio.h similarity index 100% rename from lib-rdmsubdevice/include/rdmsubdevicebwdio.h rename to lib-rdmsubdevice/include/spi/rdmsubdevicebwdio.h diff --git a/lib-rdmsubdevice/include/rdmsubdevicebwlcd.h b/lib-rdmsubdevice/include/spi/rdmsubdevicebwlcd.h similarity index 97% rename from lib-rdmsubdevice/include/rdmsubdevicebwlcd.h rename to lib-rdmsubdevice/include/spi/rdmsubdevicebwlcd.h index 9e16a2c4..62bb4676 100644 --- a/lib-rdmsubdevice/include/rdmsubdevicebwlcd.h +++ b/lib-rdmsubdevice/include/spi/rdmsubdevicebwlcd.h @@ -2,7 +2,7 @@ * @file rdmsubdevicebwlcd.h * */ -/* Copyright (C) 2018-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-rdmsubdevice/include/rdmsubdevicebwrelay.h b/lib-rdmsubdevice/include/spi/rdmsubdevicebwrelay.h similarity index 100% rename from lib-rdmsubdevice/include/rdmsubdevicebwrelay.h rename to lib-rdmsubdevice/include/spi/rdmsubdevicebwrelay.h diff --git a/lib-rdmsubdevice/include/rdmsubdevicemcp23s08.h b/lib-rdmsubdevice/include/spi/rdmsubdevicemcp23s08.h similarity index 100% rename from lib-rdmsubdevice/include/rdmsubdevicemcp23s08.h rename to lib-rdmsubdevice/include/spi/rdmsubdevicemcp23s08.h diff --git a/lib-rdmsubdevice/include/rdmsubdevicemcp23s17.h b/lib-rdmsubdevice/include/spi/rdmsubdevicemcp23s17.h similarity index 100% rename from lib-rdmsubdevice/include/rdmsubdevicemcp23s17.h rename to lib-rdmsubdevice/include/spi/rdmsubdevicemcp23s17.h diff --git a/lib-rdmsubdevice/include/rdmsubdevicemcp4822.h b/lib-rdmsubdevice/include/spi/rdmsubdevicemcp4822.h similarity index 96% rename from lib-rdmsubdevice/include/rdmsubdevicemcp4822.h rename to lib-rdmsubdevice/include/spi/rdmsubdevicemcp4822.h index 7b4ef6b7..08690386 100644 --- a/lib-rdmsubdevice/include/rdmsubdevicemcp4822.h +++ b/lib-rdmsubdevice/include/spi/rdmsubdevicemcp4822.h @@ -2,7 +2,7 @@ * @file rdmsubdevicemcp4822.h * */ -/* Copyright (C) 2020-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-rdmsubdevice/include/rdmsubdevicemcp4902.h b/lib-rdmsubdevice/include/spi/rdmsubdevicemcp4902.h similarity index 96% rename from lib-rdmsubdevice/include/rdmsubdevicemcp4902.h rename to lib-rdmsubdevice/include/spi/rdmsubdevicemcp4902.h index d11ef53c..b81a79e7 100644 --- a/lib-rdmsubdevice/include/rdmsubdevicemcp4902.h +++ b/lib-rdmsubdevice/include/spi/rdmsubdevicemcp4902.h @@ -2,7 +2,7 @@ * @file rdmsubdevicemcp4902.h * */ -/* Copyright (C) 2018-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-rdmsubdevice/src/rdm_subdevices.cpp b/lib-rdmsubdevice/src/rdm_subdevices.cpp new file mode 100755 index 00000000..dfe423dd --- /dev/null +++ b/lib-rdmsubdevice/src/rdm_subdevices.cpp @@ -0,0 +1,61 @@ +/** + * @file rdm_subdevices.cpp + * + */ +/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include + +#include "rdm _subdevices.h" + +namespace rdm { +namespace subdevices { +static constexpr char TYPE[static_cast(rdm::subdevices::Types::UNDEFINED)][9] = { + "bw7fets", "bwdimmer", "bwdio", "bwlcd", "bwrelay", + "mcp23s08", "mcp23s17", + "mcp4822", "mcp4902" }; + + +const char* get_type_string(rdm::subdevices::Types type) { + if (type < rdm::subdevices::Types::UNDEFINED) { + return TYPE[static_cast(type)]; + } + + return "Unknown"; +} + +rdm::subdevices::Types get_type_string(const char *pValue) { + assert(pValue != nullptr); + + for (uint32_t i = 0; i < static_cast(rdm::subdevices::Types::UNDEFINED); i++) { + if (strcasecmp(pValue, TYPE[i]) == 0) { + return static_cast(i); + } + } + + return rdm::subdevices::Types::UNDEFINED; +} +} // namespace subdevices +} // namespace rdm + diff --git a/lib-rdmsubdevice/src/rdmsubdevice.cpp b/lib-rdmsubdevice/src/rdmsubdevice.cpp deleted file mode 100644 index 829eed5c..00000000 --- a/lib-rdmsubdevice/src/rdmsubdevice.cpp +++ /dev/null @@ -1,148 +0,0 @@ -/** - * @file rdmsubdevice.cpp - * - */ -/* Copyright (C) 2018-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include - -#include "rdmsubdevice.h" - -RDMSubDevice::RDMSubDevice(const char* pLabel, uint16_t nDmxStartAddress, uint8_t nPersonalityCurrent): - - m_nDmxStartAddressFactoryDefault(nDmxStartAddress), - m_nCurrentPersonalityFactoryDefault(nPersonalityCurrent) -{ - for (uint32_t i = 0; (i < RDM_DEVICE_LABEL_MAX_LENGTH) && pLabel[i] != 0; i++) { - m_aLabelFactoryDefault[i] = pLabel[i]; - } - - SetLabel(pLabel); - - m_tSubDevicesInfo.dmx_start_address = nDmxStartAddress; - m_tSubDevicesInfo.current_personality = nPersonalityCurrent; - - m_tSubDevicesInfo.sensor_count = 0; - m_tSubDevicesInfo.personality_count = 0; - - m_nCheckSum = CalculateChecksum(); -} - -RDMSubDevice::~RDMSubDevice() { -} - -void RDMSubDevice::SetDmxStartAddress(uint16_t nDmxStartAddress) { - m_tSubDevicesInfo.dmx_start_address = nDmxStartAddress; - UpdateEvent(RDM_SUBDEVICE_UPDATE_EVENT_DMX_STARTADDRESS); -} - -void RDMSubDevice::SetDmxFootprint(uint16_t nDmxFootprint) { - m_tSubDevicesInfo.dmx_footprint = nDmxFootprint; -} - -void RDMSubDevice::SetPersonalities(RDMPersonality **pRDMPersonalities, uint8_t nPersonalityCount) { - assert(pRDMPersonalities != nullptr); - - m_tSubDevicesInfo.personality_count = nPersonalityCount; - m_pRDMPersonalities = pRDMPersonalities; - - UpdateEvent(RDM_SUBDEVICE_UPDATE_EVENT_PERSONALITY); -} - -RDMPersonality* RDMSubDevice::GetPersonality(uint8_t nPersonality) { - assert(nPersonality != 0); - assert(nPersonality <= m_tSubDevicesInfo.personality_count); - - return m_pRDMPersonalities[nPersonality - 1]; -} - -void RDMSubDevice::GetLabel(struct TRDMDeviceInfoData* pInfoData) { - assert(pInfoData != nullptr); - - pInfoData->data = m_tSubDevicesInfo.aLabel; - pInfoData->length = m_tSubDevicesInfo.nLabelLength; -} - -void RDMSubDevice::SetLabel(const char *pLabel) { - assert(pLabel != nullptr); - uint32_t i; - - for (i = 0; (i < RDM_DEVICE_LABEL_MAX_LENGTH) && (pLabel[i] != 0); i++) { - m_tSubDevicesInfo.aLabel[i] = pLabel[i]; - } - - m_tSubDevicesInfo.nLabelLength = static_cast(i); -} - -void RDMSubDevice::SetLabel(const char *pLabel, uint8_t nLabelLength) { - assert(pLabel != nullptr); - uint32_t i; - - for (i = 0; (i < RDM_DEVICE_LABEL_MAX_LENGTH) && (i < nLabelLength); i++) { - m_tSubDevicesInfo.aLabel[i] = pLabel[i]; - } - - m_tSubDevicesInfo.nLabelLength = static_cast(i); -} - -void RDMSubDevice::SetPersonalityCurrent(uint8_t nCurrent) { - m_tSubDevicesInfo.current_personality = nCurrent; -} - -bool RDMSubDevice::GetFactoryDefaults() { - if (m_IsFactoryDefaults) { - if (m_nCheckSum != CalculateChecksum()) { - m_IsFactoryDefaults = false; - } - } - - return m_IsFactoryDefaults; -} - -void RDMSubDevice::SetFactoryDefaults() { - if (m_IsFactoryDefaults) { - return; - } - - SetLabel(m_aLabelFactoryDefault); - - m_tSubDevicesInfo.dmx_start_address = m_nDmxStartAddressFactoryDefault; - m_tSubDevicesInfo.current_personality = m_nCurrentPersonalityFactoryDefault; - - m_IsFactoryDefaults = true; -} - -uint16_t RDMSubDevice::CalculateChecksum() { - uint16_t nChecksum = m_tSubDevicesInfo.dmx_start_address; - nChecksum = static_cast(nChecksum + m_tSubDevicesInfo.current_personality); - - for (uint32_t i = 0; i < m_tSubDevicesInfo.nLabelLength; i++) { - nChecksum = static_cast(nChecksum + m_tSubDevicesInfo.aLabel[i]); - } - - return nChecksum; -} - -void RDMSubDevice::UpdateEvent(__attribute__((unused)) TRDMSubDeviceUpdateEvent tUpdateEvent) { - // override -} diff --git a/lib-rdmsubdevice/src/rdmsubdevices.cpp b/lib-rdmsubdevice/src/rdmsubdevices.cpp deleted file mode 100644 index 180cb1c0..00000000 --- a/lib-rdmsubdevice/src/rdmsubdevices.cpp +++ /dev/null @@ -1,217 +0,0 @@ -/** - * @file rdmsubdevices.cpp - * - */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include - -#include "rdmsubdevices.h" -#include "rdmsubdevice.h" - -#include "rdmsubdevicedummy.h" - -#include "debug.h" - -RDMSubDevices *RDMSubDevices::s_pThis = nullptr; - -RDMSubDevices::RDMSubDevices() { - DEBUG_ENTRY - - assert(s_pThis == nullptr); - s_pThis = this; - -#if defined(ENABLE_RDM_SUBDEVICES) - m_pRDMSubDevice = new RDMSubDevice*[rdm::subdevices::MAX]; - assert(m_pRDMSubDevice != nullptr); - -# ifndef NDEBUG - Add(new RDMSubDeviceDummy); -# endif -#endif - - DEBUG_EXIT -} - -RDMSubDevices::~RDMSubDevices() { - DEBUG_ENTRY - - - for (unsigned i = 0; i < m_nCount; i++) { - delete m_pRDMSubDevice[i]; - m_pRDMSubDevice[i] = nullptr; - } - - delete [] m_pRDMSubDevice; - - m_nCount = 0; - - DEBUG_EXIT -} - -struct TRDMSubDevicesInfo* RDMSubDevices::GetInfo(uint16_t nSubDevice) { - assert((nSubDevice != 0) && (nSubDevice <= m_nCount)); - - assert(m_pRDMSubDevice[nSubDevice - 1] != nullptr); - return m_pRDMSubDevice[nSubDevice - 1]->GetInfo(); -} - -void RDMSubDevices::GetLabel(uint16_t nSubDevice, struct TRDMDeviceInfoData* pInfoData) { - assert((nSubDevice != 0) && (nSubDevice <= m_nCount)); - assert(pInfoData != nullptr); - - assert(m_pRDMSubDevice[nSubDevice - 1] != nullptr); - m_pRDMSubDevice[nSubDevice - 1]->GetLabel(pInfoData); -} - -void RDMSubDevices::SetLabel(uint16_t nSubDevice, const char *pLabel, uint8_t nLabelLength) { - assert((nSubDevice != 0) && (nSubDevice <= m_nCount)); - assert(pLabel != nullptr); - - assert(m_pRDMSubDevice[nSubDevice - 1] != nullptr); - m_pRDMSubDevice[nSubDevice - 1]->SetLabel(pLabel,nLabelLength); -} - - -uint16_t RDMSubDevices::GetDmxStartAddress(uint16_t nSubDevice) { - assert((nSubDevice != 0) && (nSubDevice <= m_nCount)); - - assert(m_pRDMSubDevice[nSubDevice - 1] != nullptr); - return m_pRDMSubDevice[nSubDevice - 1]->GetDmxStartAddress(); -} - -void RDMSubDevices::SetDmxStartAddress(uint16_t nSubDevice, uint16_t nDmxStartAddress) { - assert((nSubDevice != 0) && (nSubDevice <= m_nCount)); - - assert(m_pRDMSubDevice[nSubDevice - 1] != nullptr); - m_pRDMSubDevice[nSubDevice - 1]->SetDmxStartAddress(nDmxStartAddress); -} - -uint16_t RDMSubDevices::GetDmxFootPrint(uint16_t nSubDevice) { - assert((nSubDevice != 0) && (nSubDevice <= m_nCount)); - - assert(m_pRDMSubDevice[nSubDevice - 1] != nullptr); - return m_pRDMSubDevice[nSubDevice - 1]->GetDmxFootPrint(); -} - -uint8_t RDMSubDevices::GetPersonalityCurrent(uint16_t nSubDevice) { - assert((nSubDevice != 0) && (nSubDevice <= m_nCount)); - - assert(m_pRDMSubDevice[nSubDevice - 1] != nullptr); - return m_pRDMSubDevice[nSubDevice - 1]->GetPersonalityCurrent(); -} - -void RDMSubDevices::SetPersonalityCurrent(uint16_t nSubDevice, uint8_t nPersonality) { - assert((nSubDevice != 0) && (nSubDevice <= m_nCount)); - - assert(m_pRDMSubDevice[nSubDevice - 1] != nullptr); - m_pRDMSubDevice[nSubDevice - 1]->SetPersonalityCurrent(nPersonality); -} - -uint8_t RDMSubDevices::GetPersonalityCount(uint16_t nSubDevice) { - assert((nSubDevice != 0) && (nSubDevice <= m_nCount)); - - assert(m_pRDMSubDevice[nSubDevice - 1] != nullptr); - return m_pRDMSubDevice[nSubDevice - 1]->GetPersonalityCount(); -} - -RDMPersonality* RDMSubDevices::GetPersonality(uint16_t nSubDevice, uint8_t nPersonality) { - assert((nSubDevice != 0) && (nSubDevice <= m_nCount)); - - assert(m_pRDMSubDevice[nSubDevice - 1] != nullptr); - return m_pRDMSubDevice[nSubDevice - 1]->GetPersonality(nPersonality); -} - -void RDMSubDevices::Start() { - DEBUG_ENTRY - - for (uint32_t i = 0; i < m_nCount; i++) { - if (m_pRDMSubDevice[i] != nullptr) { - m_pRDMSubDevice[i]->Start(); - } - } - - DEBUG_EXIT -} - -void RDMSubDevices::Stop() { - DEBUG_ENTRY - - for (uint32_t i = 0; i < m_nCount; i++) { - if (m_pRDMSubDevice[i] != nullptr) { - m_pRDMSubDevice[i]->Stop(); - } - } - - DEBUG_ENTRY -} - -void RDMSubDevices::SetData(const uint8_t* pData, uint32_t nLength) { - for (unsigned i = 0; i < m_nCount; i++) { - if (m_pRDMSubDevice[i] != nullptr) { - if (nLength >= (static_cast(m_pRDMSubDevice[i]->GetDmxStartAddress() + m_pRDMSubDevice[i]->GetDmxFootPrint()) - 1U)) { - m_pRDMSubDevice[i]->Data(pData, nLength); - } - } - } -} - -bool RDMSubDevices::GetFactoryDefaults() { - for (uint32_t i = 0; i < m_nCount; i++) { - if (m_pRDMSubDevice[i] != nullptr) { - if (!m_pRDMSubDevice[i]->GetFactoryDefaults()) { - return false; - } - } - } - - return true; -} - -void RDMSubDevices::SetFactoryDefaults() { - for (uint32_t i = 0; i < m_nCount; i++) { - if (m_pRDMSubDevice[i] != nullptr) { - m_pRDMSubDevice[i]->SetFactoryDefaults(); - } - } -} - -const char* RDMSubDevices::GetTypeString(rdm::subdevices::Types type) { - if (type < rdm::subdevices::Types::UNDEFINED) { - return RDMSubDevicesConst::TYPE[static_cast(type)]; - } - - return "Unknown"; -} - -rdm::subdevices::Types RDMSubDevices::GetTypeString(const char *pValue) { - assert(pValue != nullptr); - - for (uint32_t i = 0; i < static_cast(rdm::subdevices::Types::UNDEFINED); i++) { - if (strcasecmp(pValue, RDMSubDevicesConst::TYPE[i]) == 0) { - return static_cast(i); - } - } - - return rdm::subdevices::Types::UNDEFINED; -} diff --git a/lib-rdmsubdevice/src/rdmsubdevicesconst.cpp b/lib-rdmsubdevice/src/rdmsubdevicesconst.cpp index 8fded33f..0890ef36 100644 --- a/lib-rdmsubdevice/src/rdmsubdevicesconst.cpp +++ b/lib-rdmsubdevice/src/rdmsubdevicesconst.cpp @@ -29,8 +29,5 @@ const char RDMSubDevicesConst::PARAMS_FILE_NAME[] = "subdev.txt"; -const char RDMSubDevicesConst::TYPE[static_cast(rdm::subdevices::Types::UNDEFINED)][9] = { - "bw7fets", "bwdimmer", "bwdio", "bwlcd", "bwrelay", - "mcp23s08", "mcp23s17", - "mcp4822", "mcp4902" }; + diff --git a/lib-rdmsubdevice/src/rdmsubdevicesparams.cpp b/lib-rdmsubdevice/src/rdmsubdevicesparams.cpp index 96ac9167..82bdb0e9 100644 --- a/lib-rdmsubdevice/src/rdmsubdevicesparams.cpp +++ b/lib-rdmsubdevice/src/rdmsubdevicesparams.cpp @@ -2,7 +2,7 @@ * @file rdmsubdevicesparams.cpp * */ -/* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -35,30 +35,34 @@ #include "rdmsubdevicesparams.h" #include "rdmsubdevices.h" +#include "rdmsubdevicesconst.h" +#include "rdm _subdevices.h" #include "readconfigfile.h" #include "sscan.h" #include "propertiesbuilder.h" -#if defined(ENABLE_RDM_SUBDEVICES) -# include "rdmsubdevicebw7fets.h" -# include "rdmsubdevicebwdimmer.h" -# include "rdmsubdevicebwdio.h" -# include "rdmsubdevicebwlcd.h" -# include "rdmsubdevicebwrelay.h" -// -# include "rdmsubdevicemcp23s08.h" -# include "rdmsubdevicemcp23s17.h" -// -# include "rdmsubdevicemcp4822.h" -# include "rdmsubdevicemcp4902.h" +#if defined(CONFIG_RDM_ENABLE_SUBDEVICES) +# if defined(CONFIG_RDM_SUBDEVICES_USE_SPI) +# include "spi/rdmsubdevicebw7fets.h" +# include "spi/rdmsubdevicebwdimmer.h" +# include "spi/rdmsubdevicebwdio.h" +# include "spi/rdmsubdevicebwlcd.h" +# include "spi/rdmsubdevicebwrelay.h" +# include "spi/rdmsubdevicemcp23s08.h" +# include "spi/rdmsubdevicemcp23s17.h" +# include "spi/rdmsubdevicemcp4822.h" +# include "spi/rdmsubdevicemcp4902.h" +# endif +# if defined(CONFIG_RDM_SUBDEVICES_USE_I2C) +# endif #endif #include "debug.h" using namespace rdm::subdevices; -RDMSubDevicesParams::RDMSubDevicesParams(RDMSubDevicesParamsStore *pRDMSubDevicesParamsStore): m_pRDMSubDevicesParamsStore(pRDMSubDevicesParamsStore) { +RDMSubDevicesParams::RDMSubDevicesParams() { DEBUG_ENTRY memset(&m_Params, 0, sizeof(struct rdm::subdevicesparams::Params)); @@ -66,7 +70,7 @@ RDMSubDevicesParams::RDMSubDevicesParams(RDMSubDevicesParamsStore *pRDMSubDevice DEBUG_EXIT } -bool RDMSubDevicesParams::Load() { +void RDMSubDevicesParams::Load() { DEBUG_ENTRY m_Params.nCount = 0; @@ -75,24 +79,21 @@ bool RDMSubDevicesParams::Load() { ReadConfigFile configfile(RDMSubDevicesParams::staticCallbackFunction, this); if (configfile.Read(RDMSubDevicesConst::PARAMS_FILE_NAME)) { - if (m_pRDMSubDevicesParamsStore != nullptr) { - m_pRDMSubDevicesParamsStore->Update(&m_Params); - } + RDMSubDevicesParamsStore::Update(&m_Params); + } else #endif - if (m_pRDMSubDevicesParamsStore != nullptr) { - m_pRDMSubDevicesParamsStore->Copy(&m_Params); - // Sanity check - if (m_Params.nCount >= rdm::subdevices::MAX) { - memset(&m_Params, 0, sizeof(struct rdm::subdevicesparams::Params)); - } - } else { - DEBUG_EXIT - return false; + RDMSubDevicesParamsStore::Copy(&m_Params); + + // Sanity check + if (m_Params.nCount >= rdm::subdevices::MAX) { + memset(&m_Params, 0, sizeof(struct rdm::subdevicesparams::Params)); } +#ifndef NDEBUG + Dump(); +#endif DEBUG_EXIT - return true; } void RDMSubDevicesParams::Load(const char *pBuffer, uint32_t nLength) { @@ -100,12 +101,8 @@ void RDMSubDevicesParams::Load(const char *pBuffer, uint32_t nLength) { assert(pBuffer != nullptr); assert(nLength != 0); - assert(m_pRDMSubDevicesParamsStore != nullptr); - if (m_pRDMSubDevicesParamsStore == nullptr) { - DEBUG_EXIT - return; - } + debug_dump(pBuffer, nLength); m_Params.nCount = 0; @@ -113,8 +110,11 @@ void RDMSubDevicesParams::Load(const char *pBuffer, uint32_t nLength) { config.Read(pBuffer, nLength); - m_pRDMSubDevicesParamsStore->Update(&m_Params); + RDMSubDevicesParamsStore::Update(&m_Params); +#ifndef NDEBUG + Dump(); +#endif DEBUG_EXIT } @@ -126,28 +126,24 @@ void RDMSubDevicesParams::Builder(const rdm::subdevicesparams::Params *pParams, if (pParams != nullptr) { memcpy(&m_Params, pParams, sizeof(struct rdm::subdevicesparams::Params)); } else { - assert(m_pRDMSubDevicesParamsStore != nullptr); - m_pRDMSubDevicesParamsStore->Copy(&m_Params); + RDMSubDevicesParamsStore::Copy(&m_Params); } PropertiesBuilder builder(RDMSubDevicesConst::PARAMS_FILE_NAME, pBuffer, nLength); + for (uint32_t nCount = 0; nCount < m_Params.nCount; nCount++) { + char buffer[32]; + const auto *p = &m_Params.Entry[nCount]; + snprintf(buffer, sizeof(buffer) - 1, "%u,%s,%u,%u,%u", p->nChipSelect, rdm::subdevices::get_type_string(static_cast(p->nType)), p->nAddress, p->nDmxStartAddress, static_cast(p->nSpeedHz)); + builder.AddRaw(buffer); + } + nSize = builder.GetSize(); DEBUG_PRINTF("nSize=%d", nSize); DEBUG_EXIT } -void RDMSubDevicesParams::Dump() { -#ifndef NDEBUG - printf("%s::%s \'%s\':\n", __FILE__, __FUNCTION__, RDMSubDevicesConst::PARAMS_FILE_NAME); - - for (uint32_t i = 0; i < m_Params.nCount; i++) { - printf(" %s 0x%.2x\n", RDMSubDevices::GetTypeString(static_cast(m_Params.Entry[i].nType)), m_Params.Entry[i].nAddress); - } -#endif -} - bool RDMSubDevicesParams::Add(RDMSubDevice *pRDMSubDevice) { DEBUG_ENTRY @@ -164,14 +160,16 @@ bool RDMSubDevicesParams::Add(RDMSubDevice *pRDMSubDevice) { } void RDMSubDevicesParams::Set() { -#if defined(ENABLE_RDM_SUBDEVICES) +#if defined(CONFIG_RDM_ENABLE_SUBDEVICES) for (uint32_t i = 0; i < m_Params.nCount; i++) { +# if defined(CONFIG_RDM_SUBDEVICES_USE_SPI) || defined(CONFIG_RDM_SUBDEVICES_USE_I2C) const auto nChipSelect = m_Params.Entry[i].nChipSelect; const auto nAddress = m_Params.Entry[i].nAddress; const auto nDmxStartAddress = m_Params.Entry[i].nDmxStartAddress; const auto nSpeedHz = m_Params.Entry[i].nSpeedHz; - +# endif switch (static_cast(m_Params.Entry[i].nType)) { +# if defined(CONFIG_RDM_SUBDEVICES_USE_SPI) case Types::BW7FETS: Add(new RDMSubDeviceBw7fets(nDmxStartAddress, nChipSelect, nAddress, nSpeedHz)); break; @@ -199,6 +197,9 @@ void RDMSubDevicesParams::Set() { case Types::MCP4902: Add(new RDMSubDeviceMCP4902(nDmxStartAddress, nChipSelect, nAddress, nSpeedHz)); break; +# endif +# if defined(CONFIG_RDM_SUBDEVICES_USE_I2C) +# endif default: break; } @@ -209,6 +210,8 @@ void RDMSubDevicesParams::Set() { void RDMSubDevicesParams::callbackFunction(const char *pLine) { assert(pLine != nullptr); + DEBUG_PUTS(pLine); + char aSubDeviceName[32]; memset(aSubDeviceName, 0, sizeof(aSubDeviceName)); @@ -220,12 +223,14 @@ void RDMSubDevicesParams::callbackFunction(const char *pLine) { const auto nReturnCode = Sscan::Spi(pLine, nChipSelect, aSubDeviceName, nLength, nAddress, nDmxStartAddress, nSpeedHz); + DEBUG_PRINTF("nReturnCode=%u", static_cast(nReturnCode)); + if ((nReturnCode == Sscan::OK) && (aSubDeviceName[0] != 0) && (nLength != 0)) { DEBUG_PRINTF("{%.*s}:%d, nChipSelect=%d, nAddress=%d, nDmxStartAddress=%d, nSpeedHz=%d", nLength, aSubDeviceName, static_cast(nLength), nChipSelect, nAddress, nDmxStartAddress, nSpeedHz); Types subDeviceType; - if ((subDeviceType = RDMSubDevices::GetTypeString(aSubDeviceName)) == Types::UNDEFINED) { + if ((subDeviceType = rdm::subdevices::get_type_string(aSubDeviceName)) == Types::UNDEFINED) { return; } @@ -258,3 +263,11 @@ void RDMSubDevicesParams::staticCallbackFunction(void *p, const char *s) { (static_cast(p))->callbackFunction(s); } + +void RDMSubDevicesParams::Dump() { + printf("%s::%s \'%s\':\n", __FILE__, __FUNCTION__, RDMSubDevicesConst::PARAMS_FILE_NAME); + + for (uint32_t i = 0; i < m_Params.nCount; i++) { + printf(" %s 0x%.2x\n", rdm::subdevices::get_type_string(static_cast(m_Params.Entry[i].nType)), m_Params.Entry[i].nAddress); + } +} diff --git a/lib-rdmsubdevice/src/spi/rdmsubdevicebw7fets.cpp b/lib-rdmsubdevice/src/spi/rdmsubdevicebw7fets.cpp index 5bb41654..28f25b90 100644 --- a/lib-rdmsubdevice/src/spi/rdmsubdevicebw7fets.cpp +++ b/lib-rdmsubdevice/src/spi/rdmsubdevicebw7fets.cpp @@ -26,14 +26,14 @@ #include #include -#include "rdmsubdevicebw7fets.h" +#include "spi/rdmsubdevicebw7fets.h" #include "bwspi7fets.h" static constexpr uint32_t DMX_FOOTPRINT = 7; static RDMPersonality *s_RDMPersonalities[] = {new RDMPersonality("Digital output 7-lines", DMX_FOOTPRINT)}; -RDMSubDeviceBw7fets::RDMSubDeviceBw7fets(uint16_t nDmxStartAddress, char nChipSselect, uint8_t nSlaveAddress, __attribute__((unused)) uint32_t nSpiSpeed) : +RDMSubDeviceBw7fets::RDMSubDeviceBw7fets(uint16_t nDmxStartAddress, char nChipSselect, uint8_t nSlaveAddress, [[maybe_unused]] uint32_t nSpiSpeed) : RDMSubDevice("bw_spi_7fets", nDmxStartAddress), m_BwSpi7fets(nChipSselect, nSlaveAddress) { SetDmxFootprint(DMX_FOOTPRINT); diff --git a/lib-rdmsubdevice/src/spi/rdmsubdevicebwdimmer.cpp b/lib-rdmsubdevice/src/spi/rdmsubdevicebwdimmer.cpp index 1bb886c5..bf752946 100644 --- a/lib-rdmsubdevice/src/spi/rdmsubdevicebwdimmer.cpp +++ b/lib-rdmsubdevice/src/spi/rdmsubdevicebwdimmer.cpp @@ -26,14 +26,14 @@ #include #include -#include "rdmsubdevicebwdimmer.h" +#include "spi/rdmsubdevicebwdimmer.h" #include "bwspidimmer.h" static constexpr uint32_t DMX_FOOTPRINT = 1; static RDMPersonality *s_RDMPersonalities[] = {new RDMPersonality("Dimmer", DMX_FOOTPRINT)}; -RDMSubDeviceBwDimmer::RDMSubDeviceBwDimmer(uint16_t nDmxStartAddress, char nChipSselect, uint8_t nSlaveAddress, __attribute__((unused)) uint32_t nSpiSpeed) : +RDMSubDeviceBwDimmer::RDMSubDeviceBwDimmer(uint16_t nDmxStartAddress, char nChipSselect, uint8_t nSlaveAddress, [[maybe_unused]] uint32_t nSpiSpeed) : RDMSubDevice("bw_spi_dimmer", nDmxStartAddress), m_BwSpiDimmer(nChipSselect, nSlaveAddress) { SetDmxFootprint(DMX_FOOTPRINT); diff --git a/lib-rdmsubdevice/src/spi/rdmsubdevicebwdio.cpp b/lib-rdmsubdevice/src/spi/rdmsubdevicebwdio.cpp index d7319a5f..9e8c7e74 100644 --- a/lib-rdmsubdevice/src/spi/rdmsubdevicebwdio.cpp +++ b/lib-rdmsubdevice/src/spi/rdmsubdevicebwdio.cpp @@ -1,4 +1,3 @@ -#if defined (BARE_METAL) || defined (RASPPI) /** * @file rdmsubdevicebwdio.cpp * @@ -27,14 +26,14 @@ #include #include -#include "rdmsubdevicebwdio.h" +#include "spi/rdmsubdevicebwdio.h" #include "bwspidio.h" static constexpr uint32_t DMX_FOOTPRINT = 7; static RDMPersonality *s_RDMPersonalities[] = {new RDMPersonality("Digital output 7-lines", DMX_FOOTPRINT)}; -RDMSubDeviceBwDio::RDMSubDeviceBwDio(uint16_t nDmxStartAddress, char nChipSselect, uint8_t nSlaveAddress, __attribute__((unused)) uint32_t nSpiSpeed) : +RDMSubDeviceBwDio::RDMSubDeviceBwDio(uint16_t nDmxStartAddress, char nChipSselect, uint8_t nSlaveAddress, [[maybe_unused]] uint32_t nSpiSpeed) : RDMSubDevice("bw_spi_dio", nDmxStartAddress), m_BwSpiDio(nChipSselect, nSlaveAddress) { SetDmxFootprint(DMX_FOOTPRINT); @@ -62,4 +61,3 @@ void RDMSubDeviceBwDio::UpdateEvent(TRDMSubDeviceUpdateEvent tUpdateEvent) { Stop(); } } -#endif diff --git a/lib-rdmsubdevice/src/spi/rdmsubdevicebwlcd.cpp b/lib-rdmsubdevice/src/spi/rdmsubdevicebwlcd.cpp index 19af5bd1..f5350b66 100644 --- a/lib-rdmsubdevice/src/spi/rdmsubdevicebwlcd.cpp +++ b/lib-rdmsubdevice/src/spi/rdmsubdevicebwlcd.cpp @@ -1,4 +1,3 @@ -#if defined (BARE_METAL) || defined (RASPPI) /** * @file rdmsubdevicebwlcd.cpp * @@ -30,7 +29,7 @@ #include "cstdio" -#include "rdmsubdevicebwlcd.h" +#include "spi/rdmsubdevicebwlcd.h" #include "bwspilcd.h" @@ -42,7 +41,7 @@ static constexpr uint32_t DMX_FOOTPRINT = 4; static RDMPersonality *s_RDMPersonalities[] = {new RDMPersonality("LCD 4-slots H", DMX_FOOTPRINT), new RDMPersonality("LCD 4-slots D", DMX_FOOTPRINT), new RDMPersonality("LCD 4-slots %%", DMX_FOOTPRINT)}; static constexpr char s_aLine[bw::lcd::max_characters + 1] = "--- --- --- --- "; -RDMSubDeviceBwLcd::RDMSubDeviceBwLcd(uint16_t nDmxStartAddress, char nChipSselect, uint8_t nSlaveAddress, __attribute__((unused)) uint32_t nSpiSpeed): +RDMSubDeviceBwLcd::RDMSubDeviceBwLcd(uint16_t nDmxStartAddress, char nChipSselect, uint8_t nSlaveAddress, [[maybe_unused]] uint32_t nSpiSpeed): RDMSubDevice("bw_spi_lcd", nDmxStartAddress), m_BwSpiLcd(nChipSselect, nSlaveAddress) { SetDmxFootprint(DMX_FOOTPRINT); @@ -271,4 +270,3 @@ void RDMSubDeviceBwLcd::DisplayUpdatePersonality() { break; } } -#endif diff --git a/lib-rdmsubdevice/src/spi/rdmsubdevicebwrelay.cpp b/lib-rdmsubdevice/src/spi/rdmsubdevicebwrelay.cpp index 795c2a1a..26416bf4 100644 --- a/lib-rdmsubdevice/src/spi/rdmsubdevicebwrelay.cpp +++ b/lib-rdmsubdevice/src/spi/rdmsubdevicebwrelay.cpp @@ -1,4 +1,3 @@ -#if defined (BARE_METAL) || defined (RASPPI) /** * @file rdmsubdevicebwrelay.cpp * @@ -27,14 +26,14 @@ #include #include -#include "rdmsubdevicebwrelay.h" +#include "spi/rdmsubdevicebwrelay.h" #include "bwspirelay.h" static constexpr uint32_t DMX_FOOTPRINT = 2; static RDMPersonality *s_RDMPersonalities[] = {new RDMPersonality("Relays", DMX_FOOTPRINT)}; -RDMSubDeviceBwRelay::RDMSubDeviceBwRelay(uint16_t nDmxStartAddress, char nChipSselect, uint8_t nSlaveAddress, __attribute__((unused)) uint32_t nSpiSpeed) : +RDMSubDeviceBwRelay::RDMSubDeviceBwRelay(uint16_t nDmxStartAddress, char nChipSselect, uint8_t nSlaveAddress, [[maybe_unused]] uint32_t nSpiSpeed) : RDMSubDevice("bw_spi_relay", nDmxStartAddress), m_BwSpiRelay(nChipSselect, nSlaveAddress) { SetDmxFootprint(DMX_FOOTPRINT); @@ -62,4 +61,3 @@ void RDMSubDeviceBwRelay::UpdateEvent(TRDMSubDeviceUpdateEvent tUpdateEvent) { Stop(); } } -#endif diff --git a/lib-rdmsubdevice/src/spi/rdmsubdevicemcp23s08.cpp b/lib-rdmsubdevice/src/spi/rdmsubdevicemcp23s08.cpp index 98d5c295..976b41b6 100644 --- a/lib-rdmsubdevice/src/spi/rdmsubdevicemcp23s08.cpp +++ b/lib-rdmsubdevice/src/spi/rdmsubdevicemcp23s08.cpp @@ -26,7 +26,7 @@ #include #include -#include "rdmsubdevicemcp23s08.h" +#include "spi/rdmsubdevicemcp23s08.h" #include "mcp23s08.h" diff --git a/lib-rdmsubdevice/src/spi/rdmsubdevicemcp23s17.cpp b/lib-rdmsubdevice/src/spi/rdmsubdevicemcp23s17.cpp index 4e225906..127485a1 100644 --- a/lib-rdmsubdevice/src/spi/rdmsubdevicemcp23s17.cpp +++ b/lib-rdmsubdevice/src/spi/rdmsubdevicemcp23s17.cpp @@ -26,7 +26,7 @@ #include #include -#include "rdmsubdevicemcp23s17.h" +#include "spi/rdmsubdevicemcp23s17.h" #include "mcp23s17.h" diff --git a/lib-rdmsubdevice/src/spi/rdmsubdevicemcp4822.cpp b/lib-rdmsubdevice/src/spi/rdmsubdevicemcp4822.cpp index 2813bfd8..20a1e33c 100644 --- a/lib-rdmsubdevice/src/spi/rdmsubdevicemcp4822.cpp +++ b/lib-rdmsubdevice/src/spi/rdmsubdevicemcp4822.cpp @@ -30,14 +30,14 @@ * MCP4822: Dual 12-Bit Voltage Output DAC */ -#include "rdmsubdevicemcp4822.h" +#include "spi/rdmsubdevicemcp4822.h" #include "mcp48x2.h" static constexpr uint32_t DMX_FOOTPRINT = 2; static RDMPersonality *s_RDMPersonalities[] = {new RDMPersonality("Analog output 2-lines", DMX_FOOTPRINT)}; -RDMSubDeviceMCP4822::RDMSubDeviceMCP4822(uint16_t nDmxStartAddress, char nChipSselect, __attribute__((unused)) uint8_t nSlaveAddress, uint32_t nSpiSpeed): +RDMSubDeviceMCP4822::RDMSubDeviceMCP4822(uint16_t nDmxStartAddress, char nChipSselect, [[maybe_unused]] uint8_t nSlaveAddress, uint32_t nSpiSpeed): RDMSubDevice("mcp4822", nDmxStartAddress), m_MCP4822(nChipSselect, nSpiSpeed) { SetDmxFootprint(DMX_FOOTPRINT); diff --git a/lib-rdmsubdevice/src/spi/rdmsubdevicemcp4902.cpp b/lib-rdmsubdevice/src/spi/rdmsubdevicemcp4902.cpp index 3a8ab478..811e5de7 100644 --- a/lib-rdmsubdevice/src/spi/rdmsubdevicemcp4902.cpp +++ b/lib-rdmsubdevice/src/spi/rdmsubdevicemcp4902.cpp @@ -30,14 +30,14 @@ * MCP4902: Dual 8-Bit Voltage Output DAC */ -#include "rdmsubdevicemcp4902.h" +#include "spi/rdmsubdevicemcp4902.h" #include "mcp49x2.h" static constexpr uint32_t DMX_FOOTPRINT = 2; static RDMPersonality *s_RDMPersonalities[] = {new RDMPersonality("Analog output 2-lines", DMX_FOOTPRINT)}; -RDMSubDeviceMCP4902::RDMSubDeviceMCP4902(uint16_t nDmxStartAddress, char nChipSselect, __attribute__((unused)) uint8_t nSlaveAddress, uint32_t nSpiSpeed) : +RDMSubDeviceMCP4902::RDMSubDeviceMCP4902(uint16_t nDmxStartAddress, char nChipSselect, [[maybe_unused]] uint8_t nSlaveAddress, uint32_t nSpiSpeed) : RDMSubDevice("mcp4902",nDmxStartAddress), m_MCP4902(nChipSselect, nSpiSpeed) { SetDmxFootprint(DMX_FOOTPRINT); diff --git a/lib-remoteconfig/.cproject b/lib-remoteconfig/.cproject index b232e775..51fcd4cb 100644 --- a/lib-remoteconfig/.cproject +++ b/lib-remoteconfig/.cproject @@ -30,11 +30,9 @@ - diff --git a/lib-remoteconfig/Makefile.GD32 b/lib-remoteconfig/Makefile.GD32 index 2761a3d3..0a3f2559 100644 --- a/lib-remoteconfig/Makefile.GD32 +++ b/lib-remoteconfig/Makefile.GD32 @@ -1,5 +1,6 @@ DEFINES =DISABLE_FS DEFINES+=DISABLE_TFTP + DEFINES+=NDEBUG ifneq ($(MAKE_FLAGS),) diff --git a/lib-remoteconfig/Rules.mk b/lib-remoteconfig/Rules.mk old mode 100644 new mode 100755 index feb51f0f..edf9ee70 --- a/lib-remoteconfig/Rules.mk +++ b/lib-remoteconfig/Rules.mk @@ -1,13 +1,17 @@ $(info $$MAKE_FLAGS [${MAKE_FLAGS}]) -EXTRA_INCLUDES=../lib-hal/include ../lib-network/include ../lib-properties/include ../lib-display/include ../lib-lightset/include ../lib-configstore/include -EXTRA_INCLUDES+=../lib-flash/include ../lib-flashcode/include ../lib-flashcodeinstall/include +EXTRA_INCLUDES=../lib-network/include ../lib-properties/include ../lib-display/include ../lib-lightset/include +EXTRA_INCLUDES+=../lib-flashcode/include ../lib-flashcodeinstall/include ifneq ($(MAKE_FLAGS),) ifneq (,$(findstring ENABLE_HTTPD,$(MAKE_FLAGS))) EXTRA_SRCDIR+=src/httpd endif + ifneq (,$(findstring ENABLE_SHELL,$(MAKE_FLAGS))) + EXTRA_SRCDIR+=src/shell src/uart + endif + ifeq ($(findstring NODE_ARTNET,$(MAKE_FLAGS)), NODE_ARTNET) EXTRA_INCLUDES+=../lib-artnet/include ifeq ($(findstring ARTNET_VERSION=4,$(MAKE_FLAGS)), ARTNET_VERSION=4) @@ -25,13 +29,28 @@ ifneq ($(MAKE_FLAGS),) ifeq ($(findstring NODE_LTC_SMPTE,$(MAKE_FLAGS)), NODE_LTC_SMPTE) EXTRA_INCLUDES+=../lib-ltc/include ../lib-tcnet/include ../lib-gps/include ../lib-midi/include EXTRA_INCLUDES+=../lib-rgbpanel/include ../lib-ws28xx/include - EXTRA_INCLUDES+=../lib-device/include endif ifeq ($(findstring NODE_OSC_CLIENT,$(MAKE_FLAGS)), NODE_OSC_CLIENT) - EXTRA_INCLUDES+=../lib-oscclient/include + EXTRA_INCLUDES+=../lib-osc/include endif ifeq ($(findstring NODE_OSC_SERVER,$(MAKE_FLAGS)), NODE_OSC_SERVER) - EXTRA_INCLUDES+=../lib-oscserver/include + EXTRA_INCLUDES+=../lib-osc/include + endif + ifeq ($(findstring NODE_SHOWFILE,$(MAKE_FLAGS)), NODE_SHOWFILE) + EXTRA_INCLUDES+=../lib-showfile/include + ifeq ($(findstring CONFIG_SHOWFILE_ENABLE_OSC,$(MAKE_FLAGS)), CONFIG_SHOWFILE_ENABLE_OSC) + EXTRA_INCLUDES+=../lib-osc/include + endif + ifeq ($(findstring CONFIG_SHOWFILE_PROTOCOL_E131,$(MAKE_FLAGS)), CONFIG_SHOWFILE_PROTOCOL_E131) + EXTRA_INCLUDES+=../lib-e131/include + endif + ifeq ($(findstring CONFIG_SHOWFILE_PROTOCOL_ARTNET,$(MAKE_FLAGS)), CONFIG_SHOWFILE_PROTOCOL_ARTNET) + EXTRA_INCLUDES+=../lib-artnet/include + endif + endif + + ifeq ($(findstring RDM_CONTROLLER,$(MAKE_FLAGS)), RDM_CONTROLLER) + EXTRA_INCLUDES+=../lib-rdm/include ../lib-dmx/include endif ifeq ($(findstring RDM_RESPONDER,$(MAKE_FLAGS)), RDM_RESPONDER) @@ -67,8 +86,12 @@ ifneq ($(MAKE_FLAGS),) ifeq ($(findstring OUTPUT_DMX_SHOWFILE,$(MAKE_FLAGS)), OUTPUT_DMX_SHOWFILE) EXTRA_INCLUDES+=../lib-showfile/include endif + ifeq ($(findstring OUTPUT_DMX_PCA9685,$(MAKE_FLAGS)), OUTPUT_DMX_PCA9685) + EXTRA_INCLUDES+=../lib-pca9685dmx/include ../lib-pca9685/include + endif else EXTRA_SRCDIR+=src/httpd + DEFINES+=ENABLE_CONTENT EXTRA_INCLUDES+=../lib-artnet/include ../lib-e131/include EXTRA_INCLUDES+=../lib-rdmdiscovery/include @@ -82,11 +105,15 @@ else EXTRA_INCLUDES+=../lib-ws28xxdmx/include ../lib-ws28xx/include EXTRA_INCLUDES+=../lib-tlc59711dmx/include ../lib-tlc59711/include EXTRA_INCLUDES+=../lib-dmxserial/include + EXTRA_INCLUDES+=../lib-pca9685dmx/include ../lib-pca9685/include EXTRA_INCLUDES+=../lib-midi/include EXTRA_INCLUDES+=../lib-rdmresponder/include ../lib-rdm/include EXTRA_INCLUDES+=../lib-rdmsensor/include ../lib-rdmsubdevice/include EXTRA_INCLUDES+=../lib-showfile/include EXTRA_INCLUDES+=../lib-dmxmonitor/include - EXTRA_INCLUDES+=../lib-device/include - EXTRA_INCLUDES+=../lib-oscclient/include ../lib-oscserver/include + EXTRA_INCLUDES+=../lib-osc/include + + DEFINES+=ARTNET_VERSION=4 + DEFINES+=RDM_CONTROLLER ENABLE_NET_PHYSTATUS CONFIG_USB_HOST_MSC ENABLE_PHY_SWITCH + DEFINES+=NODE_SHOWFILE CONFIG_SHOWFILE_FORMAT_OLA CONFIG_SHOWFILE_PROTOCOL_E131 endif diff --git a/lib-remoteconfig/http/content/Makefile b/lib-remoteconfig/http/content/Makefile index 38f00e4e..e13be575 100755 --- a/lib-remoteconfig/http/content/Makefile +++ b/lib-remoteconfig/http/content/Makefile @@ -7,15 +7,15 @@ LD = $(PREFIX)ld AR = $(PREFIX)ar ROOT = ./../../.. -INCLUDES := -I$(ROOT)/lib-network/include -I$(ROOT)/lib-remoteconfig/include +INCLUDES := -I$(ROOT)/lib-hal/include -I$(ROOT)/lib-network/include -I$(ROOT)/lib-remoteconfig/include -I$(ROOT)/lib-configstore/include -I$(ROOT)/lib-debug/include COPS := -std=c++11 -Wall -Werror all : content generate_json_switch clean : - rm generate_content - rm generate_json_switch - rm *.h + rm -rf generate_content + rm -rf generate_json_switch + rm -rf *.h generate_content : Makefile generate_content.cpp $(CPP) generate_content.cpp $(INCLUDES) $(COPS) -o generate_content diff --git a/lib-remoteconfig/http/content/content.h b/lib-remoteconfig/http/content/content.h index ed189abe..6625a8bc 100644 --- a/lib-remoteconfig/http/content/content.h +++ b/lib-remoteconfig/http/content/content.h @@ -5,16 +5,47 @@ #include "httpd/httpd.h" +#if !defined (CONFIG_HTTP_HTML_NO_DMX) && (defined(OUTPUT_DMX_SEND) || defined(OUTPUT_DMX_SEND_MULTI)) +# include "dmx.js.h" +#endif /* !defined (CONFIG_HTTP_HTML_NO_DMX) && (defined(OUTPUT_DMX_SEND) || defined(OUTPUT_DMX_SEND_MULTI)) */ +#if !defined (CONFIG_HTTP_HTML_NO_RTC) && !defined (DISABLE_RTC) +# include "rtc.html.h" +#endif /* !defined (CONFIG_HTTP_HTML_NO_RTC) && !defined (DISABLE_RTC) */ #include "static.js.h" #include "styles.css.h" #include "index.js.h" +#include "date.js.h" #if defined (ENABLE_PHY_SWITCH) -#include "dsa.js.h" +# include "dsa.js.h" #endif /* (ENABLE_PHY_SWITCH) */ +#if defined (NODE_SHOWFILE) +# include "showfile.html.h" +#endif /* (NODE_SHOWFILE) */ #include "default.js.h" +#if !defined (CONFIG_HTTP_HTML_NO_RTC) && !defined (DISABLE_RTC) +# include "rtc.js.h" +#endif /* !defined (CONFIG_HTTP_HTML_NO_RTC) && !defined (DISABLE_RTC) */ +#if !defined (CONFIG_HTTP_HTML_NO_RDM) && defined (RDM_CONTROLLER) +# include "rdm.js.h" +#endif /* !defined (CONFIG_HTTP_HTML_NO_RDM) && defined (RDM_CONTROLLER) */ +#if !defined (CONFIG_HTTP_HTML_NO_TIME) +# include "time.js.h" +#endif /* !defined (CONFIG_HTTP_HTML_NO_TIME) */ +#if !defined (CONFIG_HTTP_HTML_NO_RDM) && defined (RDM_CONTROLLER) +# include "rdm.html.h" +#endif /* !defined (CONFIG_HTTP_HTML_NO_RDM) && defined (RDM_CONTROLLER) */ #include "index.html.h" +#if defined (NODE_SHOWFILE) +# include "showfile.js.h" +#endif /* (NODE_SHOWFILE) */ +#if !defined (CONFIG_HTTP_HTML_NO_TIME) +# include "time.html.h" +#endif /* !defined (CONFIG_HTTP_HTML_NO_TIME) */ +#if !defined (CONFIG_HTTP_HTML_NO_DMX) && (defined(OUTPUT_DMX_SEND) || defined(OUTPUT_DMX_SEND_MULTI)) +# include "dmx.html.h" +#endif /* !defined (CONFIG_HTTP_HTML_NO_DMX) && (defined(OUTPUT_DMX_SEND) || defined(OUTPUT_DMX_SEND_MULTI)) */ #if defined (ENABLE_PHY_SWITCH) -#include "dsa.html.h" +# include "dsa.html.h" #endif /* (ENABLE_PHY_SWITCH) */ struct FilesContent { @@ -25,14 +56,45 @@ struct FilesContent { }; static constexpr struct FilesContent HttpContent[] = { - { "static.js", static_js, 1065, static_cast(2) }, +#if !defined (CONFIG_HTTP_HTML_NO_DMX) && (defined(OUTPUT_DMX_SEND) || defined(OUTPUT_DMX_SEND_MULTI)) + { "dmx.js", dmx_js, 1361, static_cast(2) }, +#endif /* !defined (CONFIG_HTTP_HTML_NO_DMX) && (defined(OUTPUT_DMX_SEND) || defined(OUTPUT_DMX_SEND_MULTI)) */ +#if !defined (CONFIG_HTTP_HTML_NO_RTC) && !defined (DISABLE_RTC) + { "rtc.html", rtc_html, 1013, static_cast(0) }, +#endif /* !defined (CONFIG_HTTP_HTML_NO_RTC) && !defined (DISABLE_RTC) */ + { "static.js", static_js, 1219, static_cast(2) }, { "styles.css", styles_css, 409, static_cast(1) }, { "index.js", index_js, 1140, static_cast(2) }, + { "date.js", date_js, 716, static_cast(2) }, #if defined (ENABLE_PHY_SWITCH) - { "dsa.js", dsa_js, 405, static_cast(2) }, + { "dsa.js", dsa_js, 613, static_cast(2) }, #endif /* (ENABLE_PHY_SWITCH) */ +#if defined (NODE_SHOWFILE) + { "showfile.html", showfile_html, 1305, static_cast(0) }, +#endif /* (NODE_SHOWFILE) */ { "default.js", default_js, 254, static_cast(2) }, +#if !defined (CONFIG_HTTP_HTML_NO_RTC) && !defined (DISABLE_RTC) + { "rtc.js", rtc_js, 843, static_cast(2) }, +#endif /* !defined (CONFIG_HTTP_HTML_NO_RTC) && !defined (DISABLE_RTC) */ +#if !defined (CONFIG_HTTP_HTML_NO_RDM) && defined (RDM_CONTROLLER) + { "rdm.js", rdm_js, 991, static_cast(2) }, +#endif /* !defined (CONFIG_HTTP_HTML_NO_RDM) && defined (RDM_CONTROLLER) */ +#if !defined (CONFIG_HTTP_HTML_NO_TIME) + { "time.js", time_js, 390, static_cast(2) }, +#endif /* !defined (CONFIG_HTTP_HTML_NO_TIME) */ +#if !defined (CONFIG_HTTP_HTML_NO_RDM) && defined (RDM_CONTROLLER) + { "rdm.html", rdm_html, 1142, static_cast(0) }, +#endif /* !defined (CONFIG_HTTP_HTML_NO_RDM) && defined (RDM_CONTROLLER) */ { "index.html", index_html, 669, static_cast(0) }, +#if defined (NODE_SHOWFILE) + { "showfile.js", showfile_js, 1425, static_cast(2) }, +#endif /* (NODE_SHOWFILE) */ +#if !defined (CONFIG_HTTP_HTML_NO_TIME) + { "time.html", time_html, 599, static_cast(0) }, +#endif /* !defined (CONFIG_HTTP_HTML_NO_TIME) */ +#if !defined (CONFIG_HTTP_HTML_NO_DMX) && (defined(OUTPUT_DMX_SEND) || defined(OUTPUT_DMX_SEND_MULTI)) + { "dmx.html", dmx_html, 538, static_cast(0) }, +#endif /* !defined (CONFIG_HTTP_HTML_NO_DMX) && (defined(OUTPUT_DMX_SEND) || defined(OUTPUT_DMX_SEND_MULTI)) */ #if defined (ENABLE_PHY_SWITCH) { "dsa.html", dsa_html, 447, static_cast(0) }, #endif /* (ENABLE_PHY_SWITCH) */ diff --git a/lib-remoteconfig/http/content/date.js b/lib-remoteconfig/http/content/date.js new file mode 100755 index 00000000..2c1ede40 --- /dev/null +++ b/lib-remoteconfig/http/content/date.js @@ -0,0 +1,18 @@ +function formatDateTime(date) { + const year = date.getFullYear(); + const mon = ('0' + (date.getMonth() + 1)).slice(-2); + const day = ('0' + date.getDate()).slice(-2); + const hour = ('0' + date.getHours()).slice(-2); + const min = ('0' + date.getMinutes()).slice(-2); + const sec = ('0' + date.getSeconds()).slice(-2); + const offset = date.getTimezoneOffset(); + const offsetHour = ('0' + Math.floor(Math.abs(offset) / 60)).slice(-2); + const offsetMin = ('0' + Math.abs(offset) % 60).slice(-2); + const sign = offset <= 0 ? '+' : '-'; + + if ((offsetHour == 0) && (offsetMin == 0)) { + return `${year}-${mon}-${day}T${hour}:${min}:${sec}Z`; + } + + return `${year}-${mon}-${day}T${hour}:${min}:${sec}${sign}${offsetHour}:${offsetMin}`; +} \ No newline at end of file diff --git a/lib-remoteconfig/http/content/date.js.h b/lib-remoteconfig/http/content/date.js.h new file mode 100644 index 00000000..47b9c51b --- /dev/null +++ b/lib-remoteconfig/http/content/date.js.h @@ -0,0 +1,47 @@ +static constexpr char date_js[] = { +0x66, 0x75, 0x6E, 0x63, 0x74, 0x69, 0x6F, 0x6E, 0x20, 0x66, 0x6F, 0x72, 0x6D, 0x61, 0x74, 0x44, +0x61, 0x74, 0x65, 0x54, 0x69, 0x6D, 0x65, 0x28, 0x64, 0x61, 0x74, 0x65, 0x29, 0x20, 0x7B, 0x0A, +0x63, 0x6F, 0x6E, 0x73, 0x74, 0x20, 0x79, 0x65, 0x61, 0x72, 0x20, 0x3D, 0x20, 0x64, 0x61, 0x74, +0x65, 0x2E, 0x67, 0x65, 0x74, 0x46, 0x75, 0x6C, 0x6C, 0x59, 0x65, 0x61, 0x72, 0x28, 0x29, 0x3B, +0x0A, 0x63, 0x6F, 0x6E, 0x73, 0x74, 0x20, 0x6D, 0x6F, 0x6E, 0x20, 0x3D, 0x20, 0x28, 0x27, 0x30, +0x27, 0x20, 0x2B, 0x20, 0x28, 0x64, 0x61, 0x74, 0x65, 0x2E, 0x67, 0x65, 0x74, 0x4D, 0x6F, 0x6E, +0x74, 0x68, 0x28, 0x29, 0x20, 0x2B, 0x20, 0x31, 0x29, 0x29, 0x2E, 0x73, 0x6C, 0x69, 0x63, 0x65, +0x28, 0x2D, 0x32, 0x29, 0x3B, 0x0A, 0x63, 0x6F, 0x6E, 0x73, 0x74, 0x20, 0x64, 0x61, 0x79, 0x20, +0x3D, 0x20, 0x28, 0x27, 0x30, 0x27, 0x20, 0x2B, 0x20, 0x64, 0x61, 0x74, 0x65, 0x2E, 0x67, 0x65, +0x74, 0x44, 0x61, 0x74, 0x65, 0x28, 0x29, 0x29, 0x2E, 0x73, 0x6C, 0x69, 0x63, 0x65, 0x28, 0x2D, +0x32, 0x29, 0x3B, 0x0A, 0x63, 0x6F, 0x6E, 0x73, 0x74, 0x20, 0x68, 0x6F, 0x75, 0x72, 0x20, 0x3D, +0x20, 0x28, 0x27, 0x30, 0x27, 0x20, 0x2B, 0x20, 0x64, 0x61, 0x74, 0x65, 0x2E, 0x67, 0x65, 0x74, +0x48, 0x6F, 0x75, 0x72, 0x73, 0x28, 0x29, 0x29, 0x2E, 0x73, 0x6C, 0x69, 0x63, 0x65, 0x28, 0x2D, +0x32, 0x29, 0x3B, 0x0A, 0x63, 0x6F, 0x6E, 0x73, 0x74, 0x20, 0x6D, 0x69, 0x6E, 0x20, 0x3D, 0x20, +0x28, 0x27, 0x30, 0x27, 0x20, 0x2B, 0x20, 0x64, 0x61, 0x74, 0x65, 0x2E, 0x67, 0x65, 0x74, 0x4D, +0x69, 0x6E, 0x75, 0x74, 0x65, 0x73, 0x28, 0x29, 0x29, 0x2E, 0x73, 0x6C, 0x69, 0x63, 0x65, 0x28, +0x2D, 0x32, 0x29, 0x3B, 0x0A, 0x63, 0x6F, 0x6E, 0x73, 0x74, 0x20, 0x73, 0x65, 0x63, 0x20, 0x3D, +0x20, 0x28, 0x27, 0x30, 0x27, 0x20, 0x2B, 0x20, 0x64, 0x61, 0x74, 0x65, 0x2E, 0x67, 0x65, 0x74, +0x53, 0x65, 0x63, 0x6F, 0x6E, 0x64, 0x73, 0x28, 0x29, 0x29, 0x2E, 0x73, 0x6C, 0x69, 0x63, 0x65, +0x28, 0x2D, 0x32, 0x29, 0x3B, 0x0A, 0x63, 0x6F, 0x6E, 0x73, 0x74, 0x20, 0x6F, 0x66, 0x66, 0x73, +0x65, 0x74, 0x20, 0x3D, 0x20, 0x64, 0x61, 0x74, 0x65, 0x2E, 0x67, 0x65, 0x74, 0x54, 0x69, 0x6D, +0x65, 0x7A, 0x6F, 0x6E, 0x65, 0x4F, 0x66, 0x66, 0x73, 0x65, 0x74, 0x28, 0x29, 0x3B, 0x0A, 0x63, +0x6F, 0x6E, 0x73, 0x74, 0x20, 0x6F, 0x66, 0x66, 0x73, 0x65, 0x74, 0x48, 0x6F, 0x75, 0x72, 0x20, +0x3D, 0x20, 0x28, 0x27, 0x30, 0x27, 0x20, 0x2B, 0x20, 0x4D, 0x61, 0x74, 0x68, 0x2E, 0x66, 0x6C, +0x6F, 0x6F, 0x72, 0x28, 0x4D, 0x61, 0x74, 0x68, 0x2E, 0x61, 0x62, 0x73, 0x28, 0x6F, 0x66, 0x66, +0x73, 0x65, 0x74, 0x29, 0x20, 0x2F, 0x20, 0x36, 0x30, 0x29, 0x29, 0x2E, 0x73, 0x6C, 0x69, 0x63, +0x65, 0x28, 0x2D, 0x32, 0x29, 0x3B, 0x0A, 0x63, 0x6F, 0x6E, 0x73, 0x74, 0x20, 0x6F, 0x66, 0x66, +0x73, 0x65, 0x74, 0x4D, 0x69, 0x6E, 0x20, 0x3D, 0x20, 0x28, 0x27, 0x30, 0x27, 0x20, 0x2B, 0x20, +0x4D, 0x61, 0x74, 0x68, 0x2E, 0x61, 0x62, 0x73, 0x28, 0x6F, 0x66, 0x66, 0x73, 0x65, 0x74, 0x29, +0x20, 0x25, 0x20, 0x36, 0x30, 0x29, 0x2E, 0x73, 0x6C, 0x69, 0x63, 0x65, 0x28, 0x2D, 0x32, 0x29, +0x3B, 0x0A, 0x63, 0x6F, 0x6E, 0x73, 0x74, 0x20, 0x73, 0x69, 0x67, 0x6E, 0x20, 0x3D, 0x20, 0x6F, +0x66, 0x66, 0x73, 0x65, 0x74, 0x20, 0x3C, 0x3D, 0x20, 0x30, 0x20, 0x3F, 0x20, 0x27, 0x2B, 0x27, +0x20, 0x3A, 0x20, 0x27, 0x2D, 0x27, 0x3B, 0x0A, 0x69, 0x66, 0x20, 0x28, 0x28, 0x6F, 0x66, 0x66, +0x73, 0x65, 0x74, 0x48, 0x6F, 0x75, 0x72, 0x20, 0x3D, 0x3D, 0x20, 0x30, 0x29, 0x20, 0x26, 0x26, +0x20, 0x28, 0x6F, 0x66, 0x66, 0x73, 0x65, 0x74, 0x4D, 0x69, 0x6E, 0x20, 0x3D, 0x3D, 0x20, 0x30, +0x29, 0x29, 0x20, 0x7B, 0x0A, 0x72, 0x65, 0x74, 0x75, 0x72, 0x6E, 0x20, 0x60, 0x24, 0x7B, 0x79, +0x65, 0x61, 0x72, 0x7D, 0x2D, 0x24, 0x7B, 0x6D, 0x6F, 0x6E, 0x7D, 0x2D, 0x24, 0x7B, 0x64, 0x61, +0x79, 0x7D, 0x54, 0x24, 0x7B, 0x68, 0x6F, 0x75, 0x72, 0x7D, 0x3A, 0x24, 0x7B, 0x6D, 0x69, 0x6E, +0x7D, 0x3A, 0x24, 0x7B, 0x73, 0x65, 0x63, 0x7D, 0x5A, 0x60, 0x3B, 0x20, 0x20, 0x0A, 0x7D, 0x20, +0x0A, 0x72, 0x65, 0x74, 0x75, 0x72, 0x6E, 0x20, 0x60, 0x24, 0x7B, 0x79, 0x65, 0x61, 0x72, 0x7D, +0x2D, 0x24, 0x7B, 0x6D, 0x6F, 0x6E, 0x7D, 0x2D, 0x24, 0x7B, 0x64, 0x61, 0x79, 0x7D, 0x54, 0x24, +0x7B, 0x68, 0x6F, 0x75, 0x72, 0x7D, 0x3A, 0x24, 0x7B, 0x6D, 0x69, 0x6E, 0x7D, 0x3A, 0x24, 0x7B, +0x73, 0x65, 0x63, 0x7D, 0x24, 0x7B, 0x73, 0x69, 0x67, 0x6E, 0x7D, 0x24, 0x7B, 0x6F, 0x66, 0x66, +0x73, 0x65, 0x74, 0x48, 0x6F, 0x75, 0x72, 0x7D, 0x3A, 0x24, 0x7B, 0x6F, 0x66, 0x66, 0x73, 0x65, +0x74, 0x4D, 0x69, 0x6E, 0x7D, 0x60, 0x3B, 0x20, 0x20, 0x20, 0x0A, 0x7D, 0x00 +}; diff --git a/lib-remoteconfig/http/content/dmx.html b/lib-remoteconfig/http/content/dmx.html new file mode 100755 index 00000000..86a3a0fe --- /dev/null +++ b/lib-remoteconfig/http/content/dmx.html @@ -0,0 +1,14 @@ + + +DMX + +
    +

    +
    +
    +
      + + + + + \ No newline at end of file diff --git a/lib-remoteconfig/http/content/dmx.html.h b/lib-remoteconfig/http/content/dmx.html.h new file mode 100644 index 00000000..e8f84a88 --- /dev/null +++ b/lib-remoteconfig/http/content/dmx.html.h @@ -0,0 +1,36 @@ +static constexpr char dmx_html[] = { +0x3C, 0x21, 0x44, 0x4F, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, 0x68, 0x74, 0x6D, 0x6C, 0x3E, 0x0A, +0x3C, 0x68, 0x74, 0x6D, 0x6C, 0x3E, 0x0A, 0x3C, 0x68, 0x65, 0x61, 0x64, 0x3E, 0x3C, 0x6C, 0x69, +0x6E, 0x6B, 0x20, 0x72, 0x65, 0x6C, 0x3D, 0x22, 0x73, 0x74, 0x79, 0x6C, 0x65, 0x73, 0x68, 0x65, +0x65, 0x74, 0x22, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3D, 0x22, 0x73, 0x74, 0x79, 0x6C, 0x65, 0x73, +0x2E, 0x63, 0x73, 0x73, 0x22, 0x20, 0x2F, 0x3E, 0x3C, 0x74, 0x69, 0x74, 0x6C, 0x65, 0x3E, 0x44, +0x4D, 0x58, 0x3C, 0x2F, 0x74, 0x69, 0x74, 0x6C, 0x65, 0x3E, 0x3C, 0x2F, 0x68, 0x65, 0x61, 0x64, +0x3E, 0x0A, 0x3C, 0x62, 0x6F, 0x64, 0x79, 0x3E, 0x0A, 0x3C, 0x68, 0x65, 0x61, 0x64, 0x65, 0x72, +0x3E, 0x3C, 0x75, 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document.getElementById("idStats").innerHTML=hdrs+''+tdd+'' + + let tr = await Promise.all( + d.map(item => getJSON('dmx/status?' + item.port).then(resp => ({ + port: item.port, + d: { sent: resp.dmx.sent, received: resp.dmx.received }, + r: { + sent: { class: resp.rdm.sent.class, discovery: resp.rdm.sent.discovery }, + received: { good: resp.rdm.received.good, bad: resp.rdm.received.bad, discovery: resp.rdm.received.discovery + }}})))); + + tr.sort((a, b) => { + return d.findIndex(item => item.port === a.port) - d.findIndex(item => item.port === b.port) + }); + + hdrs='PortDMXRDMSentReceivedSentReceivedClassDiscoveryGoodBadDiscovery' + tdd='' + + tr.forEach(p => { + tdd+=`${p.port}${p.d.sent}${p.d.received}${p.r.sent.class}${p.r.sent.discovery}${p.r.received.good}${p.r.received.bad}${p.r.received.discovery}`; + }); + + document.getElementById("idPorts").innerHTML=hdrs+tdd + + } catch (error){} +} \ No newline at end of file diff --git a/lib-remoteconfig/http/content/dmx.js.h b/lib-remoteconfig/http/content/dmx.js.h new file mode 100644 index 00000000..546000ec --- /dev/null +++ b/lib-remoteconfig/http/content/dmx.js.h @@ -0,0 +1,88 @@ +static constexpr char dmx_js[] = { +0x61, 0x73, 0x79, 0x6E, 0x63, 0x20, 0x66, 0x75, 0x6E, 0x63, 0x74, 0x69, 0x6F, 0x6E, 0x20, 0x72, +0x65, 0x66, 0x72, 0x65, 0x73, 0x68, 0x28, 0x29, 0x20, 0x7B, 0x0A, 0x74, 0x72, 0x79, 0x20, 0x7B, +0x0A, 0x6C, 0x65, 0x74, 0x20, 0x64, 0x3D, 0x61, 0x77, 0x61, 0x69, 0x74, 0x20, 0x67, 0x65, 0x74, +0x4A, 0x53, 0x4F, 0x4E, 0x28, 0x27, 0x64, 0x6D, 0x78, 0x2F, 0x70, 0x6F, 0x72, 0x74, 0x73, 0x74, +0x61, 0x74, 0x75, 0x73, 0x27, 0x29, 0x0A, 0x6C, 0x65, 0x74, 0x20, 0x68, 0x64, 0x72, 0x73, 0x3D, +0x27, 0x3C, 0x74, 0x72, 0x3E, 0x27, 0x0A, 0x6C, 0x65, 0x74, 0x20, 0x74, 0x64, 0x64, 0x3D, 0x27, +0x3C, 0x74, 0x72, 0x3E, 0x27, 0x0A, 0x64, 0x2E, 0x66, 0x6F, 0x72, 0x45, 0x61, 0x63, 0x68, 0x28, +0x69, 0x74, 0x65, 0x6D, 0x20, 0x3D, 0x3E, 0x20, 0x7B, 0x0A, 0x68, 0x64, 0x72, 0x73, 0x2B, 0x3D, +0x60, 0x3C, 0x74, 0x68, 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this software and associated documentation files (the "Software"), to deal @@ -51,6 +51,21 @@ static constexpr char content_header[] = static constexpr char HAVE_DSA_BEGIN[] = "#if defined (ENABLE_PHY_SWITCH)\n"; static constexpr char HAVE_DSA_END[] = "#endif /* (ENABLE_PHY_SWITCH) */\n"; +static constexpr char HAVE_DMX_BEGIN[] = "#if !defined (CONFIG_HTTP_HTML_NO_DMX) && (defined(OUTPUT_DMX_SEND) || defined(OUTPUT_DMX_SEND_MULTI))\n"; +static constexpr char HAVE_DMX_END[] = "#endif /* !defined (CONFIG_HTTP_HTML_NO_DMX) && (defined(OUTPUT_DMX_SEND) || defined(OUTPUT_DMX_SEND_MULTI)) */\n"; + +static constexpr char HAVE_RDM_BEGIN[] = "#if !defined (CONFIG_HTTP_HTML_NO_RDM) && defined (RDM_CONTROLLER)\n"; +static constexpr char HAVE_RDM_END[] = "#endif /* !defined (CONFIG_HTTP_HTML_NO_RDM) && defined (RDM_CONTROLLER) */\n"; + +static constexpr char HAVE_SHOWFILE_BEGIN[] = "#if defined (NODE_SHOWFILE)\n"; +static constexpr char HAVE_SHOWFILE_END[] = "#endif /* (NODE_SHOWFILE) */\n"; + +static constexpr char HAVE_TIME_BEGIN[] = "#if !defined (CONFIG_HTTP_HTML_NO_TIME)\n"; +static constexpr char HAVE_TIME_END[] = "#endif /* !defined (CONFIG_HTTP_HTML_NO_TIME) */\n"; + +static constexpr char HAVE_RTC_BEGIN[] = "#if !defined (CONFIG_HTTP_HTML_NO_RTC) && !defined (DISABLE_RTC)\n"; +static constexpr char HAVE_RTC_END[] = "#endif /* !defined (CONFIG_HTTP_HTML_NO_RTC) && !defined (DISABLE_RTC) */\n"; + static FILE *pFileContent; static FILE *pFileIncludes; @@ -105,7 +120,37 @@ static int convert_to_h(const char *pFileName) { fwrite(HAVE_DSA_BEGIN, sizeof(char),sizeof(HAVE_DSA_BEGIN) - 1, pFileIncludes); } - auto i = snprintf(buffer, sizeof(buffer) - 1, "#include \"%s\"\n", pFileNameOut); + const auto bHasDMX = (strstr(pFileNameOut, "dmx") != nullptr); + + if (bHasDMX) { + fwrite(HAVE_DMX_BEGIN, sizeof(char),sizeof(HAVE_DMX_BEGIN) - 1, pFileIncludes); + } + + const auto bHasRDM = (strstr(pFileNameOut, "rdm") != nullptr); + + if (bHasRDM) { + fwrite(HAVE_RDM_BEGIN, sizeof(char),sizeof(HAVE_RDM_BEGIN) - 1, pFileIncludes); + } + + const auto bHasSHOWFILE = (strstr(pFileNameOut, "showfile") != nullptr); + + if (bHasSHOWFILE) { + fwrite(HAVE_SHOWFILE_BEGIN, sizeof(char),sizeof(HAVE_SHOWFILE_BEGIN) - 1, pFileIncludes); + } + + const auto bHasTIME = (strstr(pFileNameOut, "time") != nullptr); + + if (bHasTIME) { + fwrite(HAVE_TIME_BEGIN, sizeof(char),sizeof(HAVE_TIME_BEGIN) - 1, pFileIncludes); + } + + const auto bHasRTC = (strstr(pFileNameOut, "rtc") != nullptr); + + if (bHasRTC) { + fwrite(HAVE_RTC_BEGIN, sizeof(char),sizeof(HAVE_RTC_BEGIN) - 1, pFileIncludes); + } + + auto i = snprintf(buffer, sizeof(buffer) - 1, "#%sinclude \"%s\"\n", (bHasDSA || bHasDMX || bHasRDM || bHasSHOWFILE || bHasTIME || bHasRTC) ? " " : "" , pFileNameOut); assert(i < static_cast(sizeof(buffer))); fwrite(buffer, sizeof(char), i, pFileIncludes); @@ -114,6 +159,26 @@ static int convert_to_h(const char *pFileName) { fwrite(HAVE_DSA_END, sizeof(char),sizeof(HAVE_DSA_END) - 1, pFileIncludes); } + if (bHasDMX) { + fwrite(HAVE_DMX_END, sizeof(char),sizeof(HAVE_DMX_END) - 1, pFileIncludes); + } + + if (bHasRDM) { + fwrite(HAVE_RDM_END, sizeof(char),sizeof(HAVE_RDM_END) - 1, pFileIncludes); + } + + if (bHasSHOWFILE) { + fwrite(HAVE_SHOWFILE_END, sizeof(char),sizeof(HAVE_SHOWFILE_END) - 1, pFileIncludes); + } + + if (bHasTIME) { + fwrite(HAVE_TIME_END, sizeof(char),sizeof(HAVE_TIME_END) - 1, pFileIncludes); + } + + if (bHasRTC) { + fwrite(HAVE_RTC_END, sizeof(char),sizeof(HAVE_RTC_END) - 1, pFileIncludes); + } + fwrite("static constexpr char ", sizeof(char), 22, pFileOut); char *pConstantName = new char[nFileNameLength + 1]; @@ -200,11 +265,36 @@ int main() { assert(pFileName != nullptr); const auto bHasDSA = (strstr(pDirEntry->d_name, "dsa") != nullptr); + const auto bHasDMX = (strstr(pDirEntry->d_name, "dmx") != nullptr); + const auto bHasRDM = (strstr(pDirEntry->d_name, "rdm") != nullptr); + const auto bHasSHOWFILE = (strstr(pDirEntry->d_name, "showfile") != nullptr); + const auto bHasTIME = (strstr(pDirEntry->d_name, "time") != nullptr); + const auto bHasRTC = (strstr(pDirEntry->d_name, "rtc") != nullptr); if (bHasDSA) { fwrite(HAVE_DSA_BEGIN, sizeof(char),sizeof(HAVE_DSA_BEGIN) - 1, pFileContent); } + if (bHasDMX) { + fwrite(HAVE_DMX_BEGIN, sizeof(char),sizeof(HAVE_DMX_BEGIN) - 1, pFileContent); + } + + if (bHasRDM) { + fwrite(HAVE_RDM_BEGIN, sizeof(char),sizeof(HAVE_RDM_BEGIN) - 1, pFileContent); + } + + if (bHasSHOWFILE) { + fwrite(HAVE_SHOWFILE_BEGIN, sizeof(char),sizeof(HAVE_SHOWFILE_BEGIN) - 1, pFileContent); + } + + if (bHasTIME) { + fwrite(HAVE_TIME_BEGIN, sizeof(char),sizeof(HAVE_TIME_BEGIN) - 1, pFileContent); + } + + if (bHasRTC) { + fwrite(HAVE_RTC_BEGIN, sizeof(char),sizeof(HAVE_RTC_BEGIN) - 1, pFileContent); + } + auto i = snprintf(pFileName, strlen(pDirEntry->d_name) + 8, "\t{ \"%s\", ", pDirEntry->d_name); fwrite(pFileName, sizeof(char), i, pFileContent); delete[] pFileName; @@ -221,6 +311,26 @@ int main() { if (bHasDSA) { fwrite(HAVE_DSA_END, sizeof(char),sizeof(HAVE_DSA_END) - 1, pFileContent); } + + if (bHasDMX) { + fwrite(HAVE_DMX_END, sizeof(char),sizeof(HAVE_DMX_END) - 1, pFileContent); + } + + if (bHasRDM) { + fwrite(HAVE_RDM_END, sizeof(char),sizeof(HAVE_RDM_END) - 1, pFileContent); + } + + if (bHasSHOWFILE) { + fwrite(HAVE_SHOWFILE_END, sizeof(char),sizeof(HAVE_SHOWFILE_END) - 1, pFileContent); + } + + if (bHasTIME) { + fwrite(HAVE_TIME_END, sizeof(char),sizeof(HAVE_TIME_END) - 1, pFileContent); + } + + if (bHasRTC) { + fwrite(HAVE_RTC_END, sizeof(char),sizeof(HAVE_RTC_END) - 1, pFileContent); + } } } diff --git a/lib-remoteconfig/http/content/generate_json_switch b/lib-remoteconfig/http/content/generate_json_switch index 2a98dbc2..5972656a 100755 Binary files a/lib-remoteconfig/http/content/generate_json_switch and b/lib-remoteconfig/http/content/generate_json_switch differ diff --git a/lib-remoteconfig/http/content/generate_json_switch.cpp b/lib-remoteconfig/http/content/generate_json_switch.cpp index e23c4e95..7aad04b4 100755 --- a/lib-remoteconfig/http/content/generate_json_switch.cpp +++ b/lib-remoteconfig/http/content/generate_json_switch.cpp @@ -2,7 +2,7 @@ * @file generate_json_switch.cpp * */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -38,8 +38,17 @@ static constexpr char JSON_ENDPOINTS[][MAX_LENGTH] = { "uptime", "display", "directory", + "rdm", + "queue", + "tod", "phystatus", - "portstatus" + "portstatus", + "vlantable", + "status", + "timedate", + "rtcalarm", + "polltable", + "types" }; inline uint16_t get_uint(const char *pString) { /* djb2 */ diff --git a/lib-remoteconfig/http/content/includes.h b/lib-remoteconfig/http/content/includes.h index c9e3453e..5b942c2f 100644 --- a/lib-remoteconfig/http/content/includes.h +++ b/lib-remoteconfig/http/content/includes.h @@ -1,11 +1,42 @@ +#if !defined (CONFIG_HTTP_HTML_NO_DMX) && (defined(OUTPUT_DMX_SEND) || defined(OUTPUT_DMX_SEND_MULTI)) +# include "dmx.js.h" +#endif /* !defined (CONFIG_HTTP_HTML_NO_DMX) && (defined(OUTPUT_DMX_SEND) || defined(OUTPUT_DMX_SEND_MULTI)) */ +#if !defined (CONFIG_HTTP_HTML_NO_RTC) && !defined (DISABLE_RTC) +# include "rtc.html.h" +#endif /* !defined (CONFIG_HTTP_HTML_NO_RTC) && !defined (DISABLE_RTC) */ #include "static.js.h" #include "styles.css.h" #include "index.js.h" +#include "date.js.h" #if defined (ENABLE_PHY_SWITCH) -#include "dsa.js.h" +# include "dsa.js.h" #endif /* (ENABLE_PHY_SWITCH) */ +#if defined (NODE_SHOWFILE) +# include "showfile.html.h" +#endif /* (NODE_SHOWFILE) */ #include "default.js.h" +#if !defined (CONFIG_HTTP_HTML_NO_RTC) && !defined (DISABLE_RTC) +# include "rtc.js.h" +#endif /* !defined (CONFIG_HTTP_HTML_NO_RTC) && !defined (DISABLE_RTC) */ +#if !defined (CONFIG_HTTP_HTML_NO_RDM) && defined (RDM_CONTROLLER) +# include "rdm.js.h" +#endif /* !defined (CONFIG_HTTP_HTML_NO_RDM) && defined (RDM_CONTROLLER) */ +#if !defined (CONFIG_HTTP_HTML_NO_TIME) +# include "time.js.h" +#endif /* !defined (CONFIG_HTTP_HTML_NO_TIME) */ +#if !defined (CONFIG_HTTP_HTML_NO_RDM) && defined (RDM_CONTROLLER) +# include "rdm.html.h" +#endif /* !defined (CONFIG_HTTP_HTML_NO_RDM) && defined (RDM_CONTROLLER) */ #include "index.html.h" +#if defined (NODE_SHOWFILE) +# include "showfile.js.h" +#endif /* (NODE_SHOWFILE) */ +#if !defined (CONFIG_HTTP_HTML_NO_TIME) +# include "time.html.h" +#endif /* !defined (CONFIG_HTTP_HTML_NO_TIME) */ +#if !defined (CONFIG_HTTP_HTML_NO_DMX) && (defined(OUTPUT_DMX_SEND) || defined(OUTPUT_DMX_SEND_MULTI)) +# include "dmx.html.h" +#endif /* !defined (CONFIG_HTTP_HTML_NO_DMX) && (defined(OUTPUT_DMX_SEND) || defined(OUTPUT_DMX_SEND_MULTI)) */ #if defined (ENABLE_PHY_SWITCH) -#include "dsa.html.h" +# include "dsa.html.h" #endif /* (ENABLE_PHY_SWITCH) */ diff --git a/lib-remoteconfig/http/content/json_switch.h b/lib-remoteconfig/http/content/json_switch.h index 50fffbbb..8c33b28d 100644 --- a/lib-remoteconfig/http/content/json_switch.h +++ b/lib-remoteconfig/http/content/json_switch.h @@ -11,8 +11,17 @@ static constexpr uint16_t VERSION = 0x6c4b; static constexpr uint16_t UPTIME = 0xb7d9; static constexpr uint16_t DISPLAY = 0x479b; static constexpr uint16_t DIRECTORY = 0x11fa; +static constexpr uint16_t RDM = 0xa528; +static constexpr uint16_t QUEUE = 0xb68a; +static constexpr uint16_t TOD = 0xaf0c; static constexpr uint16_t PHYSTATUS = 0xb63a; static constexpr uint16_t PORTSTATUS = 0x394e; +static constexpr uint16_t VLANTABLE = 0xe4be; +static constexpr uint16_t STATUS = 0x8d49; +static constexpr uint16_t TIMEDATE = 0x2472; +static constexpr uint16_t RTCALARM = 0x817b; +static constexpr uint16_t POLLTABLE = 0x0864; +static constexpr uint16_t TYPES = 0x5e5a; } } } diff --git a/lib-remoteconfig/http/content/rdm.html b/lib-remoteconfig/http/content/rdm.html new file mode 100755 index 00000000..258a016e --- /dev/null +++ b/lib-remoteconfig/http/content/rdm.html @@ -0,0 +1,34 @@ + + +RDM + +
        +

        +
        +
        Working Queue
        +
        +
        +
        Discovered devices
        +
          + + + + + + \ No newline at end of file diff --git a/lib-remoteconfig/http/content/rdm.html.h b/lib-remoteconfig/http/content/rdm.html.h new file mode 100644 index 00000000..1427ab82 --- /dev/null +++ b/lib-remoteconfig/http/content/rdm.html.h @@ -0,0 +1,74 @@ +static constexpr char rdm_html[] = { +0x3C, 0x21, 0x44, 0x4F, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, 0x68, 0x74, 0x6D, 0x6C, 0x3E, 0x0A, +0x3C, 0x68, 0x74, 0x6D, 0x6C, 0x3E, 0x0A, 0x3C, 0x68, 0x65, 0x61, 0x64, 0x3E, 0x3C, 0x6C, 0x69, +0x6E, 0x6B, 0x20, 0x72, 0x65, 0x6C, 0x3D, 0x22, 0x73, 0x74, 0x79, 0x6C, 0x65, 0x73, 0x68, 0x65, +0x65, 0x74, 0x22, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3D, 0x22, 0x73, 0x74, 0x79, 0x6C, 0x65, 0x73, +0x2E, 0x63, 0x73, 0x73, 0x22, 0x20, 0x2F, 0x3E, 0x3C, 0x74, 0x69, 0x74, 0x6C, 0x65, 0x3E, 0x52, +0x44, 0x4D, 0x3C, 0x2F, 0x74, 0x69, 0x74, 0x6C, 0x65, 0x3E, 0x3C, 0x2F, 0x68, 0x65, 0x61, 0x64, +0x3E, 0x0A, 0x3C, 0x62, 0x6F, 0x64, 0x79, 0x3E, 0x0A, 0x3C, 0x68, 0x65, 0x61, 0x64, 0x65, 0x72, +0x3E, 0x3C, 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document.getElementById("idQue").innerHTML=h + + tr.sort((a, b) => { + return data.findIndex(item => item.port === a.port) - data.findIndex(item => item.port === b.port); + }); + + let hdrs='' + let tdd='' + + tr.forEach(r => { + hdrs+=`${r.port}`; + tdd+=''; + r.tod.forEach(tod => { + tdd+=`${tod}
          ` + }); + tdd+='' + }); + + hdrs+='' + tdd+='' + document.getElementById("idDis").innerHTML=hdrs + tdd + } catch (error){} +} \ No newline at end of file diff --git a/lib-remoteconfig/http/content/rdm.js.h b/lib-remoteconfig/http/content/rdm.js.h new file mode 100644 index 00000000..b0adbfda --- /dev/null +++ b/lib-remoteconfig/http/content/rdm.js.h @@ -0,0 +1,64 @@ +static constexpr char rdm_js[] = { +0x61, 0x73, 0x79, 0x6E, 0x63, 0x20, 0x66, 0x75, 0x6E, 0x63, 0x74, 0x69, 0x6F, 0x6E, 0x20, 0x72, +0x65, 0x66, 0x72, 0x65, 0x73, 0x68, 0x28, 0x29, 0x20, 0x7B, 0x0A, 0x74, 0x72, 0x79, 0x20, 0x7B, +0x0A, 0x6C, 0x65, 0x74, 0x20, 0x64, 0x61, 0x74, 0x61, 0x3D, 0x61, 0x77, 0x61, 0x69, 0x74, 0x20, +0x67, 0x65, 0x74, 0x4A, 0x53, 0x4F, 0x4E, 0x28, 0x27, 0x72, 0x64, 0x6D, 0x2F, 0x70, 0x6F, 0x72, +0x74, 0x73, 0x74, 0x61, 0x74, 0x75, 0x73, 0x27, 0x29, 0x0A, 0x6C, 0x65, 0x74, 0x20, 0x68, 0x3D, +0x27, 0x3C, 0x74, 0x72, 0x3E, 0x3C, 0x74, 0x68, 0x3E, 0x50, 0x6F, 0x72, 0x74, 0x3C, 0x2F, 0x74, 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            +

            +

            Node time will be displayed here

            +

            RTC time will be displayed here

            +
            + + +
            +

            +

            + + + + + +
            +
              + + + + + + \ No newline at end of file diff --git a/lib-remoteconfig/http/content/rtc.html.h b/lib-remoteconfig/http/content/rtc.html.h new file mode 100644 index 00000000..de317f42 --- /dev/null +++ b/lib-remoteconfig/http/content/rtc.html.h @@ -0,0 +1,66 @@ +static constexpr char rtc_html[] = { +0x3C, 0x21, 0x44, 0x4F, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, 0x68, 0x74, 0x6D, 0x6C, 0x3E, 0x0A, +0x3C, 0x68, 0x74, 0x6D, 0x6C, 0x3E, 0x0A, 0x3C, 0x68, 0x65, 0x61, 0x64, 0x3E, 0x3C, 0x6C, 0x69, +0x6E, 0x6B, 0x20, 0x72, 0x65, 0x6C, 0x3D, 0x22, 0x73, 0x74, 0x79, 0x6C, 0x65, 0x73, 0x68, 0x65, +0x65, 0x74, 0x22, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3D, 0x22, 0x73, 0x74, 0x79, 0x6C, 0x65, 0x73, +0x2E, 0x63, 0x73, 0x73, 0x22, 0x20, 0x2F, 0x3E, 0x3C, 0x74, 0x69, 0x74, 0x6C, 0x65, 0x3E, 0x52, +0x65, 0x61, 0x6C, 0x2D, 0x74, 0x69, 0x6D, 0x65, 0x20, 0x63, 0x6C, 0x6F, 0x63, 0x6B, 0x3C, 0x2F, +0x74, 0x69, 0x74, 0x6C, 0x65, 0x3E, 0x3C, 0x2F, 0x68, 0x65, 0x61, 0x64, 0x3E, 0x0A, 0x3C, 0x62, +0x6F, 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Time: ${rtc}` + document.getElementById('alarmInput').value = formatDateTime(new Date(d2.alarm)) + document.getElementById('chkbox').checked = (d2.enabled === "1") +} + +async function hcToSys() { + await post({ rtc: "", action: "hctosys" }); + refresh(); +} + +async function sysToHc() { + await post({ rtc: "", action: "systohc" }); + refresh(); +} + +async function alarm() { + const a = document.getElementById('alarmInput').value; + const b = document.getElementById('chkbox').checked ? "1" : "0"; + await post({ rtc:"", alarm: a, enable: b }); + refresh(); +} diff --git a/lib-remoteconfig/http/content/rtc.js.h b/lib-remoteconfig/http/content/rtc.js.h new file mode 100644 index 00000000..8a80190b --- /dev/null +++ b/lib-remoteconfig/http/content/rtc.js.h @@ -0,0 +1,55 @@ +static constexpr char rtc_js[] = { +0x61, 0x73, 0x79, 0x6E, 0x63, 0x20, 0x66, 0x75, 0x6E, 0x63, 0x74, 0x69, 0x6F, 0x6E, 0x20, 0x72, +0x65, 0x66, 0x72, 0x65, 0x73, 0x68, 0x28, 0x29, 0x20, 0x7B, 0x0A, 0x6C, 0x65, 0x74, 0x20, 0x64, +0x31, 0x3D, 0x61, 0x77, 0x61, 0x69, 0x74, 0x20, 0x67, 0x65, 0x74, 0x4A, 0x53, 0x4F, 0x4E, 0x28, +0x27, 0x74, 0x69, 0x6D, 0x65, 0x64, 0x61, 0x74, 0x65, 0x27, 0x29, 0x0A, 0x63, 0x6F, 0x6E, 0x73, +0x74, 0x20, 0x6E, 0x6F, 0x64, 0x65, 0x20, 0x3D, 0x20, 0x66, 0x6F, 0x72, 0x6D, 0x61, 0x74, 0x44, +0x61, 0x74, 0x65, 0x54, 0x69, 0x6D, 0x65, 0x28, 0x6E, 0x65, 0x77, 0x20, 0x44, 0x61, 0x74, 0x65, +0x28, 0x64, 0x31, 0x2E, 0x64, 0x61, 0x74, 0x65, 0x29, 0x29, 0x0A, 0x64, 0x6F, 0x63, 0x75, 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                +

                +
                +
                + + + + +
                +
                + +
                +

                Player Show

                +

                Set new recorder file

                +

                Delete Show

                +
                  + + + + + + \ No newline at end of file diff --git a/lib-remoteconfig/http/content/showfile.html.h b/lib-remoteconfig/http/content/showfile.html.h new file mode 100644 index 00000000..5dcd4b35 --- /dev/null +++ b/lib-remoteconfig/http/content/showfile.html.h @@ -0,0 +1,84 @@ +static constexpr char showfile_html[] = { +0x3C, 0x21, 0x44, 0x4F, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, 0x68, 0x74, 0x6D, 0x6C, 0x3E, 0x0A, +0x3C, 0x68, 0x74, 0x6D, 0x6C, 0x3E, 0x0A, 0x3C, 0x68, 0x65, 0x61, 0x64, 0x3E, 0x0A, 0x3C, 0x6C, +0x69, 0x6E, 0x6B, 0x20, 0x72, 0x65, 0x6C, 0x3D, 0x22, 0x73, 0x74, 0x79, 0x6C, 0x65, 0x73, 0x68, +0x65, 0x65, 0x74, 0x22, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3D, 0x22, 0x73, 0x74, 0x79, 0x6C, 0x65, +0x73, 0x2E, 0x63, 0x73, 0x73, 0x22, 0x20, 0x2F, 0x3E, 0x0A, 0x3C, 0x74, 0x69, 0x74, 0x6C, 0x65, +0x3E, 0x3C, 0x2F, 0x74, 0x69, 0x74, 0x6C, 0x65, 0x3E, 0x0A, 0x3C, 0x2F, 0x68, 0x65, 0x61, 0x64, +0x3E, 0x0A, 0x3C, 0x62, 0x6F, 0x64, 0x79, 0x3E, 0x0A, 0x3C, 0x68, 0x65, 0x61, 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"Yes" : "No" + h=`Mode${d.mode} ` + h+=`Show${s} ` + h+=`Status${d.status}` + h+=`Looping${loop}` + document.getElementById("idStatus").innerHTML=''+h+'
                  ' + let b=d.loop === "1" ? "No loop" : "Looping" + document.getElementById("id4").innerHTML=b + } catch (error){} +} + +async function sel() { + const v=document.getElementById("id1").value + await post({ show:`${v}` }) + refresh() +} + +async function rec() { + const v=document.getElementById("id3").innerHTML + await post({ show:"",recorder:`${v}` }) + refresh() +} + +async function del() { + const v=document.getElementById("id2").value + await delet({ show:`${v}` }) + refresh() +} + +function ff(d) { + const s = d.shows.map(show => show.show) + let e = 0; + for (let n of s) { + if (n !== e) { return e;} + e++; + } + return e +} + +async function directory() { + try { + let d=await getJSON('showfile/directory') + let h="" + let f=Object.keys(d["shows"]) + f.forEach(function(key) { + var v = d["shows"][key] + h += "" + }); + document.getElementById("id1").innerHTML = h + document.getElementById("id2").innerHTML = h + document.getElementById("id3").innerHTML = ff(d) + } catch (error){} +} \ No newline at end of file diff --git a/lib-remoteconfig/http/content/showfile.js.h b/lib-remoteconfig/http/content/showfile.js.h new file mode 100644 index 00000000..73fa6ee1 --- /dev/null +++ b/lib-remoteconfig/http/content/showfile.js.h @@ -0,0 +1,92 @@ +static constexpr char showfile_js[] = { +0x61, 0x73, 0x79, 0x6E, 0x63, 0x20, 0x66, 0x75, 0x6E, 0x63, 0x74, 0x69, 0x6F, 0x6E, 0x20, 0x72, +0x65, 0x66, 0x72, 0x65, 0x73, 0x68, 0x28, 0x29, 0x20, 0x7B, 0x0A, 0x74, 0x72, 0x79, 0x20, 0x7B, +0x0A, 0x64, 0x69, 0x72, 0x65, 0x63, 0x74, 0x6F, 0x72, 0x79, 0x28, 0x29, 0x0A, 0x6C, 0x65, 0x74, +0x20, 0x64, 0x3D, 0x61, 0x77, 0x61, 0x69, 0x74, 0x20, 0x67, 0x65, 0x74, 0x4A, 0x53, 0x4F, 0x4E, +0x28, 0x27, 0x73, 0x68, 0x6F, 0x77, 0x66, 0x69, 0x6C, 0x65, 0x2F, 0x73, 0x74, 0x61, 0x74, 0x75, +0x73, 0x27, 0x29, 0x0A, 0x6C, 0x65, 0x74, 0x20, 0x73, 0x3D, 0x28, 0x70, 0x61, 0x72, 0x73, 0x65, +0x49, 0x6E, 0x74, 0x28, 0x64, 0x2E, 0x73, 0x68, 0x6F, 0x77, 0x29, 0x20, 0x3E, 0x3D, 0x20, 0x30, +0x20, 0x26, 0x26, 0x20, 0x70, 0x61, 0x72, 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b/lib-remoteconfig/http/content/static.js index 1856a910..d1665383 100644 --- a/lib-remoteconfig/http/content/static.js +++ b/lib-remoteconfig/http/content/static.js @@ -19,7 +19,7 @@ async function version() { } function post(s) { - fetch('/json/action', { + return fetch('/json/action', { method: 'POST', headers: { 'Content-Type': 'application/json' @@ -28,6 +28,16 @@ function post(s) { }) } +function delet(s) { + return fetch('/json/action', { + method: 'DELETE', + headers: { + 'Content-Type': 'application/json' + }, + body: JSON.stringify(s) + }) +} + function reboot() { post({ reboot: 1 }) } diff --git a/lib-remoteconfig/http/content/static.js.h b/lib-remoteconfig/http/content/static.js.h index 245a4e4f..e0aea984 100644 --- a/lib-remoteconfig/http/content/static.js.h +++ b/lib-remoteconfig/http/content/static.js.h @@ -34,36 +34,46 @@ static constexpr char static_js[] = { 0x2E, 0x62, 0x75, 0x69, 0x6C, 0x64, 0x2E, 0x74, 0x69, 0x6D, 0x65, 0x2B, 0x22, 0x3C, 0x2F, 0x6C, 0x69, 0x3E, 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                    +

                    +

                    Node time will be displayed here

                    +

                    +
                      + + + + + + \ No newline at end of file diff --git a/lib-remoteconfig/http/content/time.html.h b/lib-remoteconfig/http/content/time.html.h new file mode 100644 index 00000000..9e886ce7 --- /dev/null +++ b/lib-remoteconfig/http/content/time.html.h @@ -0,0 +1,40 @@ +static constexpr char time_html[] = { +0x3C, 0x21, 0x44, 0x4F, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, 0x68, 0x74, 0x6D, 0x6C, 0x3E, 0x0A, +0x3C, 0x68, 0x74, 0x6D, 0x6C, 0x3E, 0x0A, 0x3C, 0x68, 0x65, 0x61, 0x64, 0x3E, 0x3C, 0x6C, 0x69, +0x6E, 0x6B, 0x20, 0x72, 0x65, 0x6C, 0x3D, 0x22, 0x73, 0x74, 0x79, 0x6C, 0x65, 0x73, 0x68, 0x65, +0x65, 0x74, 0x22, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3D, 0x22, 0x73, 0x74, 0x79, 0x6C, 0x65, 0x73, +0x2E, 0x63, 0x73, 0x73, 0x22, 0x20, 0x2F, 0x3E, 0x3C, 0x74, 0x69, 0x74, 0x6C, 0x65, 0x3E, 0x4E, +0x6F, 0x64, 0x65, 0x20, 0x54, 0x69, 0x6D, 0x65, 0x3C, 0x2F, 0x74, 0x69, 0x74, 0x6C, 0x65, 0x3E, +0x3C, 0x2F, 0x68, 0x65, 0x61, 0x64, 0x3E, 0x0A, 0x3C, 0x62, 0x6F, 0x64, 0x79, 0x3E, 0x0A, 0x3C, +0x68, 0x65, 0x61, 0x64, 0x65, 0x72, 0x3E, 0x3C, 0x75, 0x6C, 0x20, 0x69, 0x64, 0x3D, 0x22, 0x69, +0x64, 0x4C, 0x69, 0x73, 0x74, 0x22, 0x3E, 0x3C, 0x2F, 0x75, 0x6C, 0x3E, 0x3C, 0x2F, 0x68, 0x65, +0x61, 0x64, 0x65, 0x72, 0x3E, 0x0A, 0x3C, 0x70, 0x3E, 0x3C, 0x62, 0x75, 0x74, 0x74, 0x6F, 0x6E, +0x20, 0x6F, 0x6E, 0x63, 0x6C, 0x69, 0x63, 0x6B, 0x3D, 0x22, 0x72, 0x65, 0x66, 0x72, 0x65, 0x73, +0x68, 0x28, 0x29, 0x22, 0x3E, 0x52, 0x65, 0x66, 0x72, 0x65, 0x73, 0x68, 0x3C, 0x2F, 0x62, 0x75, +0x74, 0x74, 0x6F, 0x6E, 0x3E, 0x3C, 0x2F, 0x70, 0x3E, 0x0A, 0x3C, 0x70, 0x20, 0x69, 0x64, 0x3D, +0x22, 0x6E, 0x6F, 0x64, 0x65, 0x54, 0x69, 0x6D, 0x65, 0x22, 0x3E, 0x4E, 0x6F, 0x64, 0x65, 0x20, +0x74, 0x69, 0x6D, 0x65, 0x20, 0x77, 0x69, 0x6C, 0x6C, 0x20, 0x62, 0x65, 0x20, 0x64, 0x69, 0x73, +0x70, 0x6C, 0x61, 0x79, 0x65, 0x64, 0x20, 0x68, 0x65, 0x72, 0x65, 0x3C, 0x2F, 0x70, 0x3E, 0x0A, +0x3C, 0x70, 0x3E, 0x3C, 0x62, 0x75, 0x74, 0x74, 0x6F, 0x6E, 0x20, 0x6F, 0x6E, 0x63, 0x6C, 0x69, +0x63, 0x6B, 0x3D, 0x22, 0x73, 0x79, 0x6E, 0x63, 0x57, 0x69, 0x74, 0x68, 0x4C, 0x6F, 0x63, 0x61, +0x6C, 0x54, 0x69, 0x6D, 0x65, 0x28, 0x29, 0x22, 0x3E, 0x53, 0x79, 0x6E, 0x63, 0x20, 0x77, 0x69, +0x74, 0x68, 0x20, 0x4C, 0x6F, 0x63, 0x61, 0x6C, 0x20, 0x54, 0x69, 0x6D, 0x65, 0x3C, 0x2F, 0x62, +0x75, 0x74, 0x74, 0x6F, 0x6E, 0x3E, 0x3C, 0x2F, 0x70, 0x3E, 0x0A, 0x3C, 0x66, 0x6F, 0x6F, 0x74, +0x65, 0x72, 0x3E, 0x3C, 0x75, 0x6C, 0x20, 0x69, 0x64, 0x3D, 0x22, 0x69, 0x64, 0x56, 0x65, 0x72, +0x73, 0x69, 0x6F, 0x6E, 0x22, 0x3E, 0x3C, 0x2F, 0x75, 0x6C, 0x3E, 0x3C, 0x2F, 0x66, 0x6F, 0x6F, +0x74, 0x65, 0x72, 0x3E, 0x0A, 0x3C, 0x73, 0x63, 0x72, 0x69, 0x70, 0x74, 0x20, 0x73, 0x72, 0x63, +0x3D, 0x22, 0x73, 0x74, 0x61, 0x74, 0x69, 0x63, 0x2E, 0x6A, 0x73, 0x22, 0x20, 0x74, 0x79, 0x70, +0x65, 0x3D, 0x22, 0x74, 0x65, 0x78, 0x74, 0x2F, 0x6A, 0x61, 0x76, 0x61, 0x73, 0x63, 0x72, 0x69, +0x70, 0x74, 0x22, 0x3E, 0x3C, 0x2F, 0x73, 0x63, 0x72, 0x69, 0x70, 0x74, 0x3E, 0x0A, 0x3C, 0x73, +0x63, 0x72, 0x69, 0x70, 0x74, 0x20, 0x73, 0x72, 0x63, 0x3D, 0x22, 0x64, 0x61, 0x74, 0x65, 0x2E, +0x6A, 0x73, 0x22, 0x20, 0x74, 0x79, 0x70, 0x65, 0x3D, 0x22, 0x74, 0x65, 0x78, 0x74, 0x2F, 0x6A, +0x61, 0x76, 0x61, 0x73, 0x63, 0x72, 0x69, 0x70, 0x74, 0x22, 0x3E, 0x3C, 0x2F, 0x73, 0x63, 0x72, +0x69, 0x70, 0x74, 0x3E, 0x0A, 0x3C, 0x73, 0x63, 0x72, 0x69, 0x70, 0x74, 0x20, 0x73, 0x72, 0x63, +0x3D, 0x22, 0x74, 0x69, 0x6D, 0x65, 0x2E, 0x6A, 0x73, 0x22, 0x20, 0x74, 0x79, 0x70, 0x65, 0x3D, +0x22, 0x74, 0x65, 0x78, 0x74, 0x2F, 0x6A, 0x61, 0x76, 0x61, 0x73, 0x63, 0x72, 0x69, 0x70, 0x74, +0x22, 0x3E, 0x3C, 0x2F, 0x73, 0x63, 0x72, 0x69, 0x70, 0x74, 0x3E, 0x0A, 0x3C, 0x73, 0x63, 0x72, +0x69, 0x70, 0x74, 0x3E, 0x6C, 0x69, 0x73, 0x74, 0x28, 0x29, 0x3B, 0x76, 0x65, 0x72, 0x73, 0x69, +0x6F, 0x6E, 0x28, 0x29, 0x3B, 0x72, 0x65, 0x66, 0x72, 0x65, 0x73, 0x68, 0x28, 0x29, 0x3C, 0x2F, +0x73, 0x63, 0x72, 0x69, 0x70, 0x74, 0x3E, 0x0A, 0x3C, 0x2F, 0x62, 0x6F, 0x64, 0x79, 0x3E, 0x0A, +0x3C, 0x2F, 0x68, 0x74, 0x6D, 0x6C, 0x3E, 0x00 +}; diff --git a/lib-remoteconfig/http/content/time.js b/lib-remoteconfig/http/content/time.js new file mode 100755 index 00000000..bfc584b2 --- /dev/null +++ b/lib-remoteconfig/http/content/time.js @@ -0,0 +1,13 @@ +async function refresh() { + let data = await getJSON('timedate') + const node = formatDateTime(new Date(data.date)) + document.getElementById('nodeTime').textContent = `Node Time: ${node}` +} + +async function syncWithLocalTime() { + const node = formatDateTime(new Date()) + document.getElementById('nodeTime').textContent = `Node Time: ${node}` + const data = { date: node } + await post(data) + refresh() +} \ No newline at end of file diff --git a/lib-remoteconfig/http/content/time.js.h b/lib-remoteconfig/http/content/time.js.h new file mode 100644 index 00000000..c372882e --- /dev/null +++ b/lib-remoteconfig/http/content/time.js.h @@ -0,0 +1,27 @@ +static constexpr char time_js[] = { +0x61, 0x73, 0x79, 0x6E, 0x63, 0x20, 0x66, 0x75, 0x6E, 0x63, 0x74, 0x69, 0x6F, 0x6E, 0x20, 0x72, +0x65, 0x66, 0x72, 0x65, 0x73, 0x68, 0x28, 0x29, 0x20, 0x7B, 0x0A, 0x6C, 0x65, 0x74, 0x20, 0x64, +0x61, 0x74, 0x61, 0x20, 0x3D, 0x20, 0x61, 0x77, 0x61, 0x69, 0x74, 0x20, 0x67, 0x65, 0x74, 0x4A, +0x53, 0x4F, 0x4E, 0x28, 0x27, 0x74, 0x69, 0x6D, 0x65, 0x64, 0x61, 0x74, 0x65, 0x27, 0x29, 0x0A, +0x63, 0x6F, 0x6E, 0x73, 0x74, 0x20, 0x6E, 0x6F, 0x64, 0x65, 0x20, 0x3D, 0x20, 0x66, 0x6F, 0x72, +0x6D, 0x61, 0x74, 0x44, 0x61, 0x74, 0x65, 0x54, 0x69, 0x6D, 0x65, 0x28, 0x6E, 0x65, 0x77, 0x20, +0x44, 0x61, 0x74, 0x65, 0x28, 0x64, 0x61, 0x74, 0x61, 0x2E, 0x64, 0x61, 0x74, 0x65, 0x29, 0x29, +0x0A, 0x64, 0x6F, 0x63, 0x75, 0x6D, 0x65, 0x6E, 0x74, 0x2E, 0x67, 0x65, 0x74, 0x45, 0x6C, 0x65, +0x6D, 0x65, 0x6E, 0x74, 0x42, 0x79, 0x49, 0x64, 0x28, 0x27, 0x6E, 0x6F, 0x64, 0x65, 0x54, 0x69, +0x6D, 0x65, 0x27, 0x29, 0x2E, 0x74, 0x65, 0x78, 0x74, 0x43, 0x6F, 0x6E, 0x74, 0x65, 0x6E, 0x74, +0x20, 0x3D, 0x20, 0x60, 0x4E, 0x6F, 0x64, 0x65, 0x20, 0x54, 0x69, 0x6D, 0x65, 0x3A, 0x20, 0x24, +0x7B, 0x6E, 0x6F, 0x64, 0x65, 0x7D, 0x60, 0x0A, 0x7D, 0x0A, 0x61, 0x73, 0x79, 0x6E, 0x63, 0x20, +0x66, 0x75, 0x6E, 0x63, 0x74, 0x69, 0x6F, 0x6E, 0x20, 0x73, 0x79, 0x6E, 0x63, 0x57, 0x69, 0x74, +0x68, 0x4C, 0x6F, 0x63, 0x61, 0x6C, 0x54, 0x69, 0x6D, 0x65, 0x28, 0x29, 0x20, 0x7B, 0x0A, 0x63, +0x6F, 0x6E, 0x73, 0x74, 0x20, 0x6E, 0x6F, 0x64, 0x65, 0x20, 0x3D, 0x20, 0x66, 0x6F, 0x72, 0x6D, +0x61, 0x74, 0x44, 0x61, 0x74, 0x65, 0x54, 0x69, 0x6D, 0x65, 0x28, 0x6E, 0x65, 0x77, 0x20, 0x44, +0x61, 0x74, 0x65, 0x28, 0x29, 0x29, 0x0A, 0x64, 0x6F, 0x63, 0x75, 0x6D, 0x65, 0x6E, 0x74, 0x2E, +0x67, 0x65, 0x74, 0x45, 0x6C, 0x65, 0x6D, 0x65, 0x6E, 0x74, 0x42, 0x79, 0x49, 0x64, 0x28, 0x27, +0x6E, 0x6F, 0x64, 0x65, 0x54, 0x69, 0x6D, 0x65, 0x27, 0x29, 0x2E, 0x74, 0x65, 0x78, 0x74, 0x43, +0x6F, 0x6E, 0x74, 0x65, 0x6E, 0x74, 0x20, 0x3D, 0x20, 0x60, 0x4E, 0x6F, 0x64, 0x65, 0x20, 0x54, +0x69, 0x6D, 0x65, 0x3A, 0x20, 0x24, 0x7B, 0x6E, 0x6F, 0x64, 0x65, 0x7D, 0x60, 0x0A, 0x63, 0x6F, +0x6E, 0x73, 0x74, 0x20, 0x64, 0x61, 0x74, 0x61, 0x20, 0x3D, 0x20, 0x7B, 0x20, 0x64, 0x61, 0x74, +0x65, 0x3A, 0x20, 0x6E, 0x6F, 0x64, 0x65, 0x20, 0x7D, 0x0A, 0x61, 0x77, 0x61, 0x69, 0x74, 0x20, +0x70, 0x6F, 0x73, 0x74, 0x28, 0x64, 0x61, 0x74, 0x61, 0x29, 0x0A, 0x72, 0x65, 0x66, 0x72, 0x65, +0x73, 0x68, 0x28, 0x29, 0x0A, 0x7D, 0x00 +}; diff --git a/gd32_emac_e131_pixel_multi/include/pixeldmxstartstop.h b/lib-remoteconfig/include/httpd/http.h old mode 100644 new mode 100755 similarity index 60% rename from gd32_emac_e131_pixel_multi/include/pixeldmxstartstop.h rename to lib-remoteconfig/include/httpd/http.h index bca3ee30..1e59cac9 --- a/gd32_emac_e131_pixel_multi/include/pixeldmxstartstop.h +++ b/lib-remoteconfig/include/httpd/http.h @@ -1,8 +1,8 @@ /** - * @file pixeldmxstartstop.h + * @file http.h * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,31 +23,30 @@ * THE SOFTWARE. */ -#ifndef PIXELDMXSTARTSTOP_H_ -#define PIXELDMXSTARTSTOP_H_ - -#include "pixeldmxhandler.h" - -#include "gd32.h" -#include "gd32_gpio.h" - -class PixelDmxStartStop final: public PixelDmxHandler { -public: - PixelDmxStartStop() { - gd32_gpio_fsel(GD32_BOARD_LED2, GPIO_FSEL_OUTPUT); - gd32_gpio_clr(GD32_BOARD_LED2); - } - - ~PixelDmxStartStop() override { - } - - void Start() override { - gd32_gpio_set(GD32_BOARD_LED2); - } +#ifndef HTTPD_HTTP_H_ +#define HTTPD_HTTP_H_ + +namespace http { +static constexpr uint32_t BUFSIZE = 1440; //TODO We need the TCP max segment size here +enum class Status { + OK = 200, + BAD_REQUEST = 400, + NOT_FOUND = 404, + REQUEST_TIMEOUT = 408, + REQUEST_ENTITY_TOO_LARGE = 413, + REQUEST_URI_TOO_LONG = 414, + INTERNAL_SERVER_ERROR = 500, + METHOD_NOT_IMPLEMENTED = 501, + VERSION_NOT_SUPPORTED = 505, + UNKNOWN_ERROR = 520 +}; +enum class RequestMethod { + GET, POST, DELETE, UNKNOWN +}; - void Stop() override { - gd32_gpio_clr(GD32_BOARD_LED2); - } +enum class contentTypes { + TEXT_HTML, TEXT_CSS, TEXT_JS, APPLICATION_JSON, APPLICATION_OCTET_STREAM, NOT_DEFINED }; +} // namespace http -#endif /* PIXELDMXSTARTSTOP_H_ */ +#endif /* HTTPD_HTTP_H_ */ diff --git a/lib-remoteconfig/include/httpd/httpd.h b/lib-remoteconfig/include/httpd/httpd.h index dee20a58..80517f3a 100755 --- a/lib-remoteconfig/include/httpd/httpd.h +++ b/lib-remoteconfig/include/httpd/httpd.h @@ -2,7 +2,7 @@ * @file httpd.h * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,79 +23,40 @@ * THE SOFTWARE. */ -#ifndef HTTPD_H_ -#define HTTPD_H_ +#ifndef HTTPD_HTTPD_H_ +#define HTTPD_HTTPD_H_ #include -#include "network.h" +#include "http.h" +#include "httpdhandlerequest.h" -namespace http { -static constexpr uint32_t BUFSIZE = 1440; -enum class Status { - OK = 200, - BAD_REQUEST = 400, - NOT_FOUND = 404, - REQUEST_TIMEOUT = 408, - REQUEST_ENTITY_TOO_LARGE = 413, - REQUEST_URI_TOO_LONG = 414, - INTERNAL_SERVER_ERROR = 500, - METHOD_NOT_IMPLEMENTED = 501, - VERSION_NOT_SUPPORTED = 505, - UNKNOWN_ERROR = 520 -}; -enum class RequestMethod { - GET, POST, UNKNOWN -}; +#include "network.h" -enum class contentTypes { - TEXT_HTML, TEXT_CSS, TEXT_JS, APPLICATION_JSON, NOT_DEFINED -}; -} // namespace http +#include "../../lib-network/config/net_config.h" class HttpDaemon { public: HttpDaemon(); + ~HttpDaemon(); + void Run() { uint32_t nConnectionHandle; - m_nBytesReceived = Network::Get()->TcpRead(m_nHandle, const_cast(reinterpret_cast(&m_RequestHeaderResponse)), nConnectionHandle); + const auto nBytesReceived = Network::Get()->TcpRead(m_nHandle, const_cast(reinterpret_cast(&m_RequestHeaderResponse)), nConnectionHandle); - if (__builtin_expect((m_nBytesReceived == 0), 1)) { + if (__builtin_expect((nBytesReceived == 0), 1)) { return; } - HandleRequest(nConnectionHandle); - } + DEBUG_PRINTF("nConnectionHandle=%u", nConnectionHandle); -private: - void HandleRequest(const uint32_t nConnectionHandle); - http::Status ParseRequest(); - http::Status ParseMethod(char *pLine); - http::Status ParseHeaderField(char *pLine); - http::Status HandleGet(); - http::Status HandlePost(bool hasDataOnly); - http::Status HandleGetTxt(); + pHandleRequest[nConnectionHandle]->HandleRequest(nBytesReceived, m_RequestHeaderResponse); + } private: - const char *m_pContentType; - char *m_pUri { nullptr }; - char *m_pFileData { nullptr }; - char *m_RequestHeaderResponse { nullptr }; - - uint32_t m_nContentLength { 0 }; - uint32_t m_nFileDataLength { 0 }; - uint32_t m_nRequestContentLength { 0 }; + HttpDeamonHandleRequest *pHandleRequest[TCP_MAX_TCBS_ALLOWED]; int32_t m_nHandle { -1 }; - - uint32_t m_nBytesReceived { 0 }; - - http::Status m_Status { http::Status::UNKNOWN_ERROR }; - http::RequestMethod m_RequestMethod { http::RequestMethod::UNKNOWN }; - - bool m_bContentTypeJson { false }; - bool m_IsAction { false }; - - static char m_Content[http::BUFSIZE]; + char *m_RequestHeaderResponse { nullptr }; }; -#endif /* HTTPD_H_ */ +#endif /* HTTPD_HTTPD_H_ */ diff --git a/lib-remoteconfig/include/httpd/httpdhandlerequest.h b/lib-remoteconfig/include/httpd/httpdhandlerequest.h new file mode 100755 index 00000000..ee1d7c1f --- /dev/null +++ b/lib-remoteconfig/include/httpd/httpdhandlerequest.h @@ -0,0 +1,77 @@ +/** + * @file httpdhandlerequest.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HTTPD_HTTPDHANDLEREQUEST_H_ +#define HTTPD_HTTPDHANDLEREQUEST_H_ + +#include + +#include "http.h" + +#include "debug.h" + +class HttpDeamonHandleRequest { +public: + HttpDeamonHandleRequest(uint32_t nConnectionHandle, int32_t nHandle) : m_nConnectionHandle(nConnectionHandle), m_nHandle(nHandle) { + DEBUG_ENTRY + DEBUG_PRINTF("m_nConnectionHandle=%u", m_nConnectionHandle); + DEBUG_EXIT + } + + void HandleRequest(const uint32_t nBytesReceived, char *pRequestHeaderResponse); + +private: + http::Status ParseRequest(); + http::Status ParseMethod(char *pLine); + http::Status ParseHeaderField(char *pLine); + http::Status HandleGet(); + http::Status HandleGetTxt(); + http::Status HandlePost(const bool hasDataOnly); + http::Status HandleDelete(const bool hasDataOnly); + +private: + uint32_t m_nConnectionHandle; + int32_t m_nHandle; + uint32_t m_nContentSize { 0 }; + uint32_t m_nFileDataLength { 0 }; + uint32_t m_nRequestContentSize { 0 }; + uint32_t m_nBytesReceived { 0 }; + + char *m_pUri { nullptr }; + char *m_pFileData { nullptr }; + const char *m_pContent { nullptr }; + char *m_RequestHeaderResponse { nullptr }; + + http::Status m_Status { http::Status::UNKNOWN_ERROR }; + http::RequestMethod m_RequestMethod { http::RequestMethod::UNKNOWN }; + http::contentTypes m_ContentType { http::contentTypes::NOT_DEFINED }; + + bool m_IsAction { false }; + + static char m_DynamicContent[http::BUFSIZE]; +}; + + +#endif /* HTTPD_HTTPDHANDLEREQUEST_H_ */ diff --git a/lib-remoteconfig/include/remoteconfig.h b/lib-remoteconfig/include/remoteconfig.h index 25d76f50..b851f56c 100644 --- a/lib-remoteconfig/include/remoteconfig.h +++ b/lib-remoteconfig/include/remoteconfig.h @@ -2,7 +2,7 @@ * @file remoteconfig.h * */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,6 +27,7 @@ #define REMOTECONFIG_H_ #include +#include #if defined (NODE_ARTNET_MULTI) # define NODE_ARTNET @@ -48,17 +49,20 @@ # include "node.h" #endif -#include "configstore.h" - #if defined(ENABLE_TFTP_SERVER) # include "tftp/tftpfileserver.h" #endif +#if defined (ENABLE_HTTPD) +# include "httpd/httpd.h" +#endif + +#include "configstore.h" #include "network.h" namespace remoteconfig { namespace udp { -static constexpr auto BUFFER_SIZE = 1024; +static constexpr auto BUFFER_SIZE = 1420; } // namespace udp enum class Node { @@ -77,6 +81,7 @@ enum class Node { RDMRESPONDER, LAST }; + enum class Output { DMX, RDM, @@ -90,14 +95,10 @@ enum class Output { ARTNET, SERIAL, RGBPANEL, + PWM, LAST }; -enum { - DISPLAY_NAME_LENGTH = 24, - ID_LENGTH = (32 + remoteconfig::DISPLAY_NAME_LENGTH + 2) // +2, comma and \n -}; - enum class TxtFile { RCONFIG, NETWORK, @@ -127,13 +128,19 @@ enum class TxtFile { RGBPANEL, LTCETC, NODE, + ENV, LAST }; + +enum { + DISPLAY_NAME_LENGTH = 24, + ID_LENGTH = (32 + remoteconfig::DISPLAY_NAME_LENGTH + 2) // +2, comma and \n +}; } // namespace remoteconfig class RemoteConfig { public: - RemoteConfig(remoteconfig::Node tType, remoteconfig::Output tMode, uint32_t nOutputs = 0); + RemoteConfig(const remoteconfig::Node node, const remoteconfig::Output output, const uint32_t nActiveOutputs = 0); ~RemoteConfig(); const char *GetStringNode() const; @@ -209,6 +216,10 @@ class RemoteConfig { } #endif +#if defined (ENABLE_HTTPD) + m_pHttpDaemon->Run(); +#endif + uint16_t nForeignPort; m_nBytesReceived = Network::Get()->RecvFrom(m_nHandle, const_cast(reinterpret_cast(&s_pUdpBuffer)), &m_nIPAddressFrom, &nForeignPort); @@ -228,7 +239,9 @@ class RemoteConfig { void HandleReboot(); void HandleFactory(); void HandleList(); +#if !defined (CONFIG_REMOTECONFIG_MINIMUM) void HandleUptime(); +#endif void HandleVersion(); void HandleGetNoParams() { @@ -236,6 +249,7 @@ class RemoteConfig { } void HandleGetRconfigTxt(uint32_t& nSize); + void HandleGetEnvTxt(uint32_t& nSize); void HandleGetNetworkTxt(uint32_t& nSize); #if defined (DISPLAY_UDF) @@ -286,7 +300,7 @@ class RemoteConfig { #if defined (RDM_RESPONDER) void HandleGetRdmDeviceTxt(uint32_t& nSize); void HandleGetRdmSensorsTxt(uint32_t& nSize); -# if defined (ENABLE_RDM_SUBDEVICES) +# if defined (CONFIG_RDM_ENABLE_SUBDEVICES) void HandleGetRdmSubdevTxt(uint32_t& nSize); # endif #endif @@ -340,7 +354,12 @@ class RemoteConfig { void HandleGetRgbPanelTxt(uint32_t& nSize); #endif - void HandleSetRconfig(); +#if defined (OUTPUT_DMX_PCA9685) + void HandleGetPca9685Txt(uint32_t& nSize); +#endif + + void HandleSetRconfigTxt(); + void HandleSetEnvTxt(); void HandleSetNetworkTxt(); #if defined (DISPLAY_UDF) @@ -391,7 +410,7 @@ class RemoteConfig { #if defined (RDM_RESPONDER) void HandleSetRdmDeviceTxt(); void HandleSetRdmSensorsTxt(); -# if defined (ENABLE_RDM_SUBDEVICES) +# if defined (CONFIG_RDM_ENABLE_SUBDEVICES) void HandleSetRdmSubdevTxt(); # endif #endif @@ -416,6 +435,10 @@ class RemoteConfig { void HandleSetRgbPanelTxt(); #endif +#if defined (OUTPUT_DMX_PCA9685) + void HandleSetPca9685Txt(); +#endif + #if defined (OUTPUT_DMX_STEPPER) void HandleSetSparkFunTxt(); void HandleSetMotorTxt(uint32_t nMotorIndex); @@ -449,6 +472,8 @@ class RemoteConfig { void HandleDisplayGet(); void HandleTftpSet(); void HandleTftpGet(); + void HandleRdmSet(); + void HandleRdmGet(); void PlatformHandleTftpSet(); void PlatformHandleTftpGet(); @@ -473,7 +498,6 @@ class RemoteConfig { void (RemoteConfig::*SetHandler)(); const char *pFileName; const uint8_t nFileNameLength; - const configstore::Store nStore; }; static const Txt s_TXT[]; @@ -505,6 +529,10 @@ class RemoteConfig { #endif bool m_bEnableTFTP { false }; +#if defined (ENABLE_HTTPD) + HttpDaemon *m_pHttpDaemon { nullptr }; +#endif + static char *s_pUdpBuffer; static RemoteConfig *s_pThis; diff --git a/lib-remoteconfig/include/remoteconfigconst.h b/lib-remoteconfig/include/remoteconfigconst.h index 553d5ec6..9a3da1d4 100644 --- a/lib-remoteconfig/include/remoteconfigconst.h +++ b/lib-remoteconfig/include/remoteconfigconst.h @@ -2,7 +2,7 @@ * @file remoteconfigconst.h * */ -/* Copyright (C) 2019-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-remoteconfig/include/remoteconfigjson.h b/lib-remoteconfig/include/remoteconfigjson.h index d959dbe0..1e9f99ea 100644 --- a/lib-remoteconfig/include/remoteconfigjson.h +++ b/lib-remoteconfig/include/remoteconfigjson.h @@ -2,7 +2,7 @@ * @file remoteconfig.h * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,17 +29,54 @@ #include namespace remoteconfig { -uint16_t json_get_list(char *pOutBuffer, const uint16_t nOutBufferSize); -uint16_t json_get_version(char *pOutBuffer, const uint16_t nOutBufferSize); -uint16_t json_get_uptime(char *pOutBuffer, const uint16_t nOutBufferSize); -uint16_t json_get_display(char *pOutBuffer, const uint16_t nOutBufferSize); -uint16_t json_get_directory(char *pOutBuffer, const uint16_t nOutBufferSize); +uint32_t json_get_list(char *pOutBuffer, const uint32_t nOutBufferSize); +uint32_t json_get_version(char *pOutBuffer, const uint32_t nOutBufferSize); +uint32_t json_get_uptime(char *pOutBuffer, const uint32_t nOutBufferSize); +uint32_t json_get_display(char *pOutBuffer, const uint32_t nOutBufferSize); +uint32_t json_get_directory(char *pOutBuffer, const uint32_t nOutBufferSize); namespace net { -uint16_t json_get_phystatus(char *pOutBuffer, const uint16_t nOutBufferSize); +uint32_t json_get_phystatus(char *pOutBuffer, const uint32_t nOutBufferSize); } // namespace net +namespace dmx { +uint32_t json_get_ports(char *pOutBuffer, const uint32_t nOutBufferSize); +uint32_t json_get_portstatus(const char cPort, char *pOutBuffer, const uint32_t nOutBufferSize); +} // namespace dmx +namespace rdm { +uint32_t json_get_rdm(char *pOutBuffer, const uint32_t nOutBufferSize); +uint32_t json_get_queue(char *pOutBuffer, const uint32_t nOutBufferSize); +uint32_t json_get_portstatus(char *pOutBuffer, const uint32_t nOutBufferSize); +uint32_t json_get_tod(const char cPort, char *pOutBuffer, const uint32_t nOutBufferSize); +} // namespace rdm +namespace storage { +uint32_t json_get_directory(char *pOutBuffer, const uint32_t nOutBufferSize); +} // namespace storage namespace dsa { -uint16_t json_get_portstatus(char *pOutBuffer, const uint16_t nOutBufferSize); +uint32_t json_get_portstatus(char *pOutBuffer, const uint32_t nOutBufferSize); +uint32_t json_get_vlantable(char *pOutBuffer, const uint32_t nOutBufferSize); } // namespace dsa +namespace showfile { +uint32_t json_get_status(char *pOutBuffer, const uint32_t nOutBufferSize); +uint32_t json_get_directory(char *pOutBuffer, const uint32_t nOutBufferSize); +void json_set_status(const char *pBuffer, const uint32_t nBufferSize); +void json_delete(const char *pBuffer, const uint32_t nBufferSize); +} // namespace showfile +namespace timedate { +uint32_t json_get_timeofday(char *pOutBuffer, const uint32_t nOutBufferSize); +void json_set_timeofday(const char *pBuffer, const uint32_t nBufferSize); +} // namespace timedate +namespace rtc { +uint32_t json_get_rtc(char *pOutBuffer, const uint32_t nOutBufferSize); +void json_set_rtc(const char *pBuffer, const uint32_t nBufferSize); +} // namespace rtc +namespace artnet { +namespace controller { +uint32_t json_get_polltable(char *pOutBuffer, const uint32_t nOutBufferSize); +} // namespace controller +} // namespace artnet +namespace pixel { +uint32_t json_get_types(char *pOutBuffer, const uint32_t nOutBufferSize); +uint32_t json_get_status(char *pOutBuffer, const uint32_t nOutBufferSize); +} // namespace pixel } // namespace remoteconfig #endif /* REMOTECONFIGJSON_H_ */ diff --git a/lib-remoteconfig/include/remoteconfigparams.h b/lib-remoteconfig/include/remoteconfigparams.h index ea161ed6..58ce482b 100644 --- a/lib-remoteconfig/include/remoteconfigparams.h +++ b/lib-remoteconfig/include/remoteconfigparams.h @@ -2,7 +2,7 @@ * @file remoteconfigparams.h * */ -/* Copyright (C) 2019-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,8 +29,10 @@ #include #include "remoteconfig.h" +#include "configstore.h" -struct TRemoteConfigParams { +namespace remoteconfigparams { +struct Params { uint32_t nSetList; uint8_t NotUsed0; uint8_t NotUsed1; @@ -39,34 +41,37 @@ struct TRemoteConfigParams { char aDisplayName[remoteconfig::DISPLAY_NAME_LENGTH]; } __attribute__((packed)); -static_assert(sizeof(struct TRemoteConfigParams) <= 48, "struct TRemoteConfigParams is too large"); +static_assert(sizeof(struct Params) <= 48, "struct Params is too large"); -struct RemoteConfigParamsMask { - static constexpr auto DISABLE = (1U << 0); - static constexpr auto DISABLE_WRITE = (1U << 1); - static constexpr auto ENABLE_REBOOT = (1U << 2); - static constexpr auto ENABLE_UPTIME = (1U << 3); - static constexpr auto DISPLAY_NAME = (1U << 4); - static constexpr auto ENABLE_FACTORY = (1U << 5); +struct Mask { + static constexpr uint32_t DISABLE = (1U << 0); + static constexpr uint32_t DISABLE_WRITE = (1U << 1); + static constexpr uint32_t ENABLE_REBOOT = (1U << 2); + static constexpr uint32_t ENABLE_UPTIME = (1U << 3); + static constexpr uint32_t DISPLAY_NAME = (1U << 4); + static constexpr uint32_t ENABLE_FACTORY = (1U << 5); }; +} // namespace remoteconfigparams class RemoteConfigParamsStore { public: - virtual ~RemoteConfigParamsStore() { + static void Update(const struct remoteconfigparams::Params *pParams) { + ConfigStore::Get()->Update(configstore::Store::RCONFIG, pParams, sizeof(struct remoteconfigparams::Params)); } - virtual void Update(const struct TRemoteConfigParams *pRemoteConfigParams)=0; - virtual void Copy(struct TRemoteConfigParams *pRemoteConfigParams)=0; + static void Copy(struct remoteconfigparams::Params *pParams) { + ConfigStore::Get()->Copy(configstore::Store::RCONFIG, pParams, sizeof(struct remoteconfigparams::Params)); + } }; class RemoteConfigParams { public: - RemoteConfigParams(RemoteConfigParamsStore *pRemoteConfigParamsStore); + RemoteConfigParams(); - bool Load(); + void Load(); void Load(const char *pBuffer, uint32_t nLength); - void Builder(const struct TRemoteConfigParams *pRemoteConfigParams, char *pBuffer, uint32_t nLength, uint32_t& nSize); + void Builder(const struct remoteconfigparams::Params *pRemoteConfigParams, char *pBuffer, uint32_t nLength, uint32_t& nSize); void Save(char *pBuffer, uint32_t nLength, uint32_t& nSize) { Builder(nullptr, pBuffer, nLength, nSize); } @@ -74,23 +79,21 @@ class RemoteConfigParams { void Set(RemoteConfig *); const char *GetDisplayName() const { - return m_tRemoteConfigParams.aDisplayName; + return m_Params.aDisplayName; } - void Dump(); - static void staticCallbackFunction(void *p, const char *s); private: + void Dump(); void callbackFunction(const char *pLine); void SetBool(const uint8_t nValue, const uint32_t nMask); bool isMaskSet(uint32_t nMask) const { - return (m_tRemoteConfigParams.nSetList & nMask) == nMask; + return (m_Params.nSetList & nMask) == nMask; } private: - RemoteConfigParamsStore *m_pRemoteConfigParamsStore; - TRemoteConfigParams m_tRemoteConfigParams; + remoteconfigparams::Params m_Params; }; #endif /* REMOTECONFIGPARAMS_H_ */ diff --git a/lib-remoteconfig/include/shell/shell.h b/lib-remoteconfig/include/shell/shell.h old mode 100644 new mode 100755 index c3fd3b3f..c8a5247c --- a/lib-remoteconfig/include/shell/shell.h +++ b/lib-remoteconfig/include/shell/shell.h @@ -3,7 +3,7 @@ * */ /* Copyright (C) 2020 by hippy mailto:dmxout@gmail.com - * Copyright (C) 2020-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl + * Copyright (C) 2020-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -44,18 +44,35 @@ enum class CmdIndex: uint32_t { GET, DHCP, DATE, + PHY, +#if !defined (DISABLE_RTC) HWCLOCK, -#ifndef NDEBUG +#endif +#if defined (DEBUG_I2C) I2CDETECT, +#endif DUMP, MEM, +#if defined (ENABLE_NTP_CLIENT) NTP, +#endif +#if defined (CONFIG_SHELL_GPS) GPS, +#endif +#if (PHY_TYPE == RTL8201F) + PHY_TYPE_RTL8201F, #endif HELP }; static constexpr auto BUFLEN = 196; static constexpr auto MAXARG = 4; + +namespace msg { +namespace error { +static constexpr char INVALID[] = "Invalid command.\n"; +static constexpr char INTERNAL[] = "Internal error.\n"; +} // namespace error +} // namespace msg } // namespace shell class Shell { @@ -75,34 +92,33 @@ class Shell { int Printf(const char* fmt, ...); // shell.cpp const char *ReadLine(uint32_t& nLength); - uint16_t ValidateCmd(uint32_t nLength, shell::CmdIndex &nCmdIndex); - void ValidateArg(uint16_t nOffset, uint32_t nLength); + uint32_t ValidateCmd(const uint32_t nLength, shell::CmdIndex &nCmdIndex); + void ValidateArg(uint32_t nOffset, const uint32_t nLength); // shellcmd.cpp - uint32_t hexadecimalToDecimal(const char *pHexValue, uint32_t nLength); void CmdReboot(); void CmdInfo(); void CmdSet(); void CmdGet(); void CmdDhcp(); void CmdDate(); + void CmdPhy(); void CmdHwClock(); -#ifndef NDEBUG void CmdI2cDetect(); void CmdDump(); void CmdMem(); void CmdNtp(); void CmdGps(); -#endif + void CmdPhyTypeRTL8201F(); void CmdHelp(); private: - bool m_bIsEndOfLine { false }; - uint16_t m_nLength { 0 }; char m_Buffer[shell::BUFLEN]; uint32_t m_Argc { 0 }; + uint32_t m_nLength { 0 }; char *m_Argv[shell::MAXARG] { nullptr }; uint16_t m_nArgvLength[shell::MAXARG]; bool m_bShownPrompt { false }; + bool m_bIsEndOfLine { false }; // Firmware specific BEGIN #if defined (LTC_READER) diff --git a/lib-remoteconfig/include/tftp/tftpfileserver.h b/lib-remoteconfig/include/tftp/tftpfileserver.h old mode 100644 new mode 100755 index e5c5e407..16a4c7d3 --- a/lib-remoteconfig/include/tftp/tftpfileserver.h +++ b/lib-remoteconfig/include/tftp/tftpfileserver.h @@ -2,7 +2,7 @@ * @file tftpfileserver.h * */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,7 +29,7 @@ #include #include -#include "tftpdaemon.h" +#include "net/apps/tftpdaemon.h" #if defined (GD32) # include "gd32.h" @@ -37,7 +37,8 @@ namespace tftpfileserver { bool is_valid(const void *pBuffer); -#if defined (BARE_METAL) +#if defined(__linux__) || defined (__APPLE__) +#else # if defined (H3) # if defined(ORANGE_PI) static constexpr char FILE_NAME[] = "orangepi_zero.uImage"; @@ -51,8 +52,10 @@ namespace tftpfileserver { static constexpr char FILE_NAME[] = "gd32f207.bin"; # elif defined (GD32F4XX) static constexpr char FILE_NAME[] = "gd32f4xx.bin"; +# elif defined (GD32H7XX) + static constexpr char FILE_NAME[] = "gd32h7xx.bin"; # else -# error MCU is not defined +# error FAMILY is not defined # endif # endif #endif diff --git a/lib-remoteconfig/src/gd32/remoteconfig.cpp b/lib-remoteconfig/src/gd32/remoteconfig.cpp index 741a69bf..a6682792 100644 --- a/lib-remoteconfig/src/gd32/remoteconfig.cpp +++ b/lib-remoteconfig/src/gd32/remoteconfig.cpp @@ -35,10 +35,10 @@ void RemoteConfig::PlatformHandleTftpSet() { if (m_bEnableTFTP) { bkp_data_write(BKP_DATA_1, 0xA5A5); - Display::Get()->TextStatus("TFTP On ", Display7SegmentMessage::INFO_TFTP_ON, CONSOLE_GREEN); + Display::Get()->TextStatus("TFTP On ", CONSOLE_GREEN); } else { bkp_data_write(BKP_DATA_1, 0x0); - Display::Get()->TextStatus("TFTP Off", Display7SegmentMessage::INFO_TFTP_OFF, CONSOLE_GREEN); + Display::Get()->TextStatus("TFTP Off", CONSOLE_GREEN); } DEBUG_EXIT diff --git a/lib-remoteconfig/src/gd32/shellcmd.cpp b/lib-remoteconfig/src/gd32/shellcmd.cpp new file mode 100644 index 00000000..9fac3ea3 --- /dev/null +++ b/lib-remoteconfig/src/gd32/shellcmd.cpp @@ -0,0 +1,31 @@ +/** + * @file shellcmd.cpp + * + */ +/* Copyright (C) 2020 by hippy mailto:dmxout@gmail.com + * Copyright (C) 2020-2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "shell/shell.h" + +void Shell::CmdDump() { + Puts(shell::msg::error::INVALID); +} diff --git a/lib-remoteconfig/src/gd32/tftpfileserver.cpp b/lib-remoteconfig/src/gd32/tftpfileserver.cpp index 639f7280..9c2c2886 100644 --- a/lib-remoteconfig/src/gd32/tftpfileserver.cpp +++ b/lib-remoteconfig/src/gd32/tftpfileserver.cpp @@ -31,7 +31,7 @@ #include "debug.h" namespace tftpfileserver { -bool is_valid(__attribute__((unused)) const void *pBuffer) { +bool is_valid([[maybe_unused]] const void *pBuffer) { return true; } } // namespace tftpfileserver diff --git a/lib-remoteconfig/src/httpd/get_file_content.cpp b/lib-remoteconfig/src/httpd/get_file_content.cpp index 47b03edb..75ad6413 100755 --- a/lib-remoteconfig/src/httpd/get_file_content.cpp +++ b/lib-remoteconfig/src/httpd/get_file_content.cpp @@ -2,7 +2,7 @@ * @file get_file_content.cpp * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -59,12 +59,12 @@ static http::contentTypes getContentType(const char *pFileName) { return http::contentTypes::NOT_DEFINED; } -int get_file_content(const char *fileName, char *pDst, http::contentTypes& contentType) { +uint32_t get_file_content(const char *fileName, char *pDst, http::contentTypes& contentType) { auto *pFile = fopen(fileName, "r"); if (pFile == nullptr) { DEBUG_EXIT - return -1; + return 0; } contentType = getContentType(fileName); @@ -72,7 +72,7 @@ int get_file_content(const char *fileName, char *pDst, http::contentTypes& conte if (contentType == http::contentTypes::NOT_DEFINED) { DEBUG_EXIT fclose(pFile); - return -2; + return 0; } auto doRemoveWhiteSpaces = true; @@ -81,7 +81,7 @@ int get_file_content(const char *fileName, char *pDst, http::contentTypes& conte while ((c = fgetc(pFile)) != EOF) { if (doRemoveWhiteSpaces) { - if (c < ' ') { + if (c <= ' ') { continue; } else { doRemoveWhiteSpaces = false; @@ -101,22 +101,41 @@ int get_file_content(const char *fileName, char *pDst, http::contentTypes& conte fclose(pFile); DEBUG_PRINTF("%s -> %d", fileName, static_cast(p - pDst)); - return static_cast(p - pDst); + return static_cast(p - pDst); +} + +static char s_StaticContent[http::BUFSIZE]; + +const char *get_file_content(const char *pFileName, uint32_t& nSize, http::contentTypes& contentType) { + DEBUG_ENTRY + DEBUG_PUTS(pFileName); + + nSize = get_file_content(pFileName, s_StaticContent, contentType); + + if (nSize != 0) { + return s_StaticContent; + } + + DEBUG_EXIT + return nullptr; } #else -int get_file_content(const char *pFileName, char *pDst, http::contentTypes& contentType) { +const char *get_file_content(const char *pFileName, uint32_t& nSize, http::contentTypes& contentType) { + DEBUG_ENTRY + DEBUG_PUTS(pFileName); + for (auto& content : HttpContent) { if (strcmp(pFileName, content.pFileName) == 0) { - assert(content.nContentLength < http::BUFSIZE); - memcpy(pDst, content.pContent, content.nContentLength); - - DEBUG_PRINTF("%s -> %d", content.pFileName, content.nContentLength); + nSize = content.nContentLength; contentType = content.contentType; - return static_cast(content.nContentLength); + return content.pContent; } } + nSize = 0; + contentType = http::contentTypes::NOT_DEFINED; + DEBUG_EXIT - return -1; + return nullptr; } #endif diff --git a/lib-remoteconfig/src/httpd/httd.cpp b/lib-remoteconfig/src/httpd/httd.cpp deleted file mode 100755 index 9ef81762..00000000 --- a/lib-remoteconfig/src/httpd/httd.cpp +++ /dev/null @@ -1,471 +0,0 @@ -/** - * @file httd.cpp - * - */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include -#include - -#include "httpd/httpd.h" -#include "remoteconfig.h" -#include "remoteconfigjson.h" -#include "properties.h" -#include "sscan.h" -#include "propertiesconfig.h" -#include "../http/content/json_switch.h" - -#include "network.h" -#include "hardware.h" -#include "display.h" - -#include "debug.h" - -#if defined ENABLE_CONTENT -extern int get_file_content(const char *fileName, char *pDst, http::contentTypes& contentType); -#endif - -char HttpDaemon::m_Content[http::BUFSIZE]; - -using namespace http; - -static constexpr char s_contentType[static_cast(contentTypes::NOT_DEFINED)][32] = - { "text/html", "text/css", "text/javascript", "application/json" }; - -HttpDaemon::HttpDaemon() : m_pContentType(s_contentType[static_cast(contentTypes::TEXT_HTML)]) { - DEBUG_ENTRY - - assert(m_nHandle == -1); - m_nHandle = Network::Get()->TcpBegin(80); - assert(m_nHandle != -1); - - DEBUG_EXIT -} - -void HttpDaemon::HandleRequest(const uint32_t nConnectionHandle) { - const char *pStatusMsg = "OK"; - - DEBUG_PRINTF("%u: m_Status=%u, m_RequestMethod=%u", nConnectionHandle, static_cast(m_Status), static_cast(m_RequestMethod)); - - if (m_Status == Status::UNKNOWN_ERROR) { - m_Status = ParseRequest(); - if (m_Status == Status::OK) { - if (m_RequestMethod == RequestMethod::GET) { - m_Status = HandleGet(); - } else if (m_RequestMethod == RequestMethod::POST) { - m_Status = HandlePost(false); - if ((m_Status == Status::OK) && (m_nFileDataLength == 0)) { - DEBUG_PUTS("There is a POST header only -> no data"); - return; - } - } - } - } else if ((m_Status == Status::OK) && (m_RequestMethod == RequestMethod::POST)) { - m_Status = HandlePost(true); - } - - if (m_Status != Status::OK) { - switch (m_Status) { - case Status::BAD_REQUEST: - pStatusMsg = "Bad Request"; - break; - case Status::NOT_FOUND: - pStatusMsg = "Not Found"; - break; - case Status::REQUEST_ENTITY_TOO_LARGE: - pStatusMsg = "Request Entity Too Large"; - break; - case Status::REQUEST_URI_TOO_LONG: - pStatusMsg = "Request-URI Too Long"; - break; - case Status::INTERNAL_SERVER_ERROR: - pStatusMsg = "Internal Server Error"; - break; - case Status::METHOD_NOT_IMPLEMENTED: - pStatusMsg = "Method Not Implemented"; - break; - case Status::VERSION_NOT_SUPPORTED: - pStatusMsg = "Version Not Supported"; - break; - default: - pStatusMsg = "Unknown Error"; - break; - } - - m_pContentType = s_contentType[static_cast(contentTypes::TEXT_HTML)]; - m_nContentLength = static_cast(snprintf(m_Content, BUFSIZE - 1U, - "\n" - "\n" - "%u %s\n" - "

                      %s

                      \n" - "\n", static_cast(m_Status), pStatusMsg, pStatusMsg)); - } - - uint8_t nLength; - const int nHeaderLength = snprintf(m_RequestHeaderResponse, BUFSIZE - 1U, - "HTTP/1.1 %u %s\r\n" - "Server: %s\r\n" - "Content-Type: %s\r\n" - "Content-Length: %u\r\n" - "Connection: close\r\n" - "\r\n", static_cast(m_Status), pStatusMsg, Hardware::Get()->GetBoardName(nLength), m_pContentType, m_nContentLength); - - Network::Get()->TcpWrite(m_nHandle, reinterpret_cast(m_RequestHeaderResponse), static_cast(nHeaderLength), nConnectionHandle); - Network::Get()->TcpWrite(m_nHandle, reinterpret_cast(m_Content), static_cast(m_nContentLength), nConnectionHandle); - DEBUG_PRINTF("m_nContentLength=%u", m_nContentLength); - - m_Status = Status::UNKNOWN_ERROR; - m_RequestMethod = RequestMethod::UNKNOWN; -} - -Status HttpDaemon::ParseRequest() { - char *pLine = m_RequestHeaderResponse; - uint32_t nLine = 0; - Status status = Status::UNKNOWN_ERROR; - m_bContentTypeJson = false; - m_nRequestContentLength = 0; - m_nFileDataLength = 0; - - for (uint32_t i = 0; i < m_nBytesReceived; i++) { - if (m_RequestHeaderResponse[i] == '\n') { - assert(i > 1); - m_RequestHeaderResponse[i - 1] = '\0'; - - if (nLine++ == 0) { - status = ParseMethod(pLine); - } else { - if (pLine[0] == '\0') { - assert((i + 1) <= m_nBytesReceived); - m_nFileDataLength = static_cast(m_nBytesReceived - 1 - i); - if (m_nFileDataLength > 0) { - m_pFileData = &m_RequestHeaderResponse[i + 1]; - m_pFileData[m_nFileDataLength] = '\0'; - } - return Status::OK; - } - status = ParseHeaderField(pLine); - } - - if (status != Status::OK) { - return status; - } - - pLine = &m_RequestHeaderResponse[++i]; - } - } - - return Status::OK; -} - -/** - * Supported: "METHOD uri HTTP/1.1" - * Where METHOD is "GET" or "POST" - */ - -Status HttpDaemon::ParseMethod(char *pLine) { - assert(pLine != nullptr); - char *pToken; - - if ((pToken = strtok(pLine, " ")) == nullptr) { - return Status::METHOD_NOT_IMPLEMENTED; - } - - if (strcmp(pToken, "GET") == 0) { - m_RequestMethod = RequestMethod::GET; - } else if (strcmp(pToken, "POST") == 0) { - m_RequestMethod = RequestMethod::POST; - } else { - return Status::METHOD_NOT_IMPLEMENTED; - } - - if ((pToken = strtok(nullptr, " ")) == nullptr) { - return Status::BAD_REQUEST; - } - - m_pUri = pToken; - - if ((pToken = strtok(nullptr, "/")) == nullptr || strcmp(pToken, "HTTP") != 0) { - return Status::BAD_REQUEST; - } - - if ((pToken = strtok(nullptr, " \n")) == nullptr) { - return Status::BAD_REQUEST; - } - - if (strcmp(pToken, "1.1") != 0) { - return Status::VERSION_NOT_SUPPORTED; - } - - return Status::OK; -} - -/** - * Only interested in "Content-Type" and - * "Content-Length" - * Where we check for "Content-Type: application/json" - */ - -Status HttpDaemon::ParseHeaderField(char *pLine) { - char *pToken; - - assert(pLine != 0); - if ((pToken = strtok(pLine, ":")) == nullptr) { - return Status::BAD_REQUEST; - } - - if (strcasecmp(pToken, "Content-Type") == 0) { - if ((pToken = strtok(nullptr, " ;")) == nullptr) { - return Status::BAD_REQUEST; - } - if (strcmp(pToken, "application/json") == 0) { - m_bContentTypeJson = true; - } - } else if (strcasecmp(pToken, "Content-Length") == 0) { - if ((pToken = strtok(nullptr, " ")) == nullptr) { - return Status::BAD_REQUEST; - } - - uint32_t nTmp = 0; - while (*pToken != '\0') { - auto nDigit = static_cast(*pToken++ - '0'); - if (nDigit > 9) { - return Status::BAD_REQUEST; - } - - nTmp *= 10; - nTmp += nDigit; - - if (nTmp > BUFSIZE) { - return Status::REQUEST_ENTITY_TOO_LARGE; - } - } - - m_nRequestContentLength = nTmp; - } - - DEBUG_EXIT - return Status::OK; -} - -/** - * GET - */ - -Status HttpDaemon::HandleGet() { - int nLength = 0; - - if (memcmp(m_pUri, "/json/", 6) == 0) { - m_pContentType = s_contentType[static_cast(contentTypes::APPLICATION_JSON)]; - const auto *pGet = &m_pUri[6]; - switch (http::get_uint(pGet)) { - case http::json::get::LIST: - nLength = remoteconfig::json_get_list(m_Content, sizeof(m_Content)); - break; - case http::json::get::VERSION: - nLength = remoteconfig::json_get_version(m_Content, sizeof(m_Content)); - break; - case http::json::get::UPTIME: - if (!RemoteConfig::Get()->IsEnableUptime()) { - DEBUG_PUTS("Status::BAD_REQUEST"); - return Status::BAD_REQUEST; - } - nLength = remoteconfig::json_get_uptime(m_Content, sizeof(m_Content)); - break; - case http::json::get::DISPLAY: - nLength = remoteconfig::json_get_display(m_Content, sizeof(m_Content)); - break; - case http::json::get::DIRECTORY: - nLength = remoteconfig::json_get_directory(m_Content, sizeof(m_Content)); - break; -#if defined (ENABLE_NET_PHYSTATUS) - case http::json::get::PHYSTATUS: - nLength = remoteconfig::net::json_get_phystatus(m_Content, sizeof(m_Content)); - break; -#endif - default: -#if defined (ENABLE_PHY_SWITCH) - if (memcmp(pGet, "dsa/", 4) == 0) { - const auto *pDsa = &pGet[4]; - switch (http::get_uint(pDsa)) { - case http::json::get::PORTSTATUS: - nLength = remoteconfig::dsa::json_get_portstatus(m_Content, sizeof(m_Content)); - break; - default: - break; - } - } else { -#endif - return HandleGetTxt(); -#if defined (ENABLE_PHY_SWITCH) - } -#endif - break; - } - } -#if defined (ENABLE_CONTENT) - else if (strcmp(m_pUri, "/") == 0) { - http::contentTypes contentType; - nLength = get_file_content("index.html", m_Content, contentType); - m_pContentType = s_contentType[static_cast(contentType)]; - } -#if defined (ENABLE_PHY_SWITCH) - else if (strcmp(m_pUri, "/dsa") == 0) { - http::contentTypes contentType; - nLength = get_file_content("dsa.html", m_Content, contentType); - m_pContentType = s_contentType[static_cast(contentType)]; - } -#endif - else { - http::contentTypes contentType; - nLength = get_file_content(&m_pUri[1], m_Content, contentType); - m_pContentType = s_contentType[static_cast(contentType)]; - } -#endif - - if (nLength <= 0) { - DEBUG_EXIT - return Status::NOT_FOUND; - } - - m_nContentLength = static_cast(nLength); - - DEBUG_EXIT - return Status::OK; -} - -Status HttpDaemon::HandleGetTxt() { - auto *pFileName = &m_pUri[6]; - const auto nLength = strlen(pFileName); - - if (nLength <= 4) { - return Status::BAD_REQUEST; - } - - if (strcmp(&pFileName[nLength - 4], ".txt") != 0) { - return Status::BAD_REQUEST; - } - - const auto bIsJSON = PropertiesConfig::IsJSON(); - - PropertiesConfig::EnableJSON(true); - const auto nBytes = RemoteConfig::Get()->HandleGet(reinterpret_cast(pFileName), BUFSIZE - 5U); - - PropertiesConfig::EnableJSON(bIsJSON); - - DEBUG_PRINTF("nBytes=%d", nBytes); - - if (nBytes <= 0) { - return Status::BAD_REQUEST; - } - - m_nContentLength = static_cast(nBytes); - memcpy(m_Content, reinterpret_cast(pFileName), nBytes); - - return Status::OK; -} - -/** - * POST - */ - -Status HttpDaemon::HandlePost(bool hasDataOnly) { - DEBUG_PRINTF("m_nBytesReceived=%d, m_nFileDataLength=%u, m_nRequestContentLength=%u -> hasDataOnly=%c", m_nBytesReceived, m_nFileDataLength, m_nRequestContentLength, hasDataOnly ? 'Y' : 'N'); - - if (!hasDataOnly) { - if (!m_bContentTypeJson) { - return Status::BAD_REQUEST; - } - - m_IsAction = (strcmp(m_pUri, "/json/action") == 0); - - if (!m_IsAction && (strcmp(m_pUri, "/json") != 0)) { - return Status::NOT_FOUND; - } - } - - const auto hasHeadersOnly = (!hasDataOnly && ((m_nBytesReceived < m_nRequestContentLength) || m_nFileDataLength == 0)); - - if (hasHeadersOnly) { - DEBUG_PUTS("hasHeadersOnly"); - return Status::OK; - } - - - if (hasDataOnly) { - m_pFileData = m_RequestHeaderResponse; - m_nFileDataLength = static_cast(m_nBytesReceived); - } - - DEBUG_PRINTF("%d|%.*s|->%d", m_nFileDataLength, m_nFileDataLength, m_pFileData, m_IsAction); - - if (m_IsAction) { - if (properties::convert_json_file(m_pFileData, m_nFileDataLength, true) <= 0) { - DEBUG_PUTS("Status::BAD_REQUEST"); - return Status::BAD_REQUEST; - } - - uint8_t value8; - - if (Sscan::Uint8(m_pFileData, "reboot", value8) == Sscan::OK) { - if (value8 != 0) { - if (!RemoteConfig::Get()->IsEnableReboot()) { - DEBUG_PUTS("Status::BAD_REQUEST"); - return Status::BAD_REQUEST; - } - DEBUG_PUTS("Reboot!"); - RemoteConfig::Get()->Reboot(); - __builtin_unreachable(); - } - } else if (Sscan::Uint8(m_pFileData, "display", value8) == Sscan::OK) { - Display::Get()->SetSleep(value8 == 0); - DEBUG_PRINTF("Display::Get()->SetSleep(%d)", value8 == 0); - } else if (Sscan::Uint8(m_pFileData, "identify", value8) == Sscan::OK) { - if (value8 != 0) { - Hardware::Get()->SetMode(hardware::ledblink::Mode::FAST); - } else { - Hardware::Get()->SetMode(hardware::ledblink::Mode::NORMAL); - } - DEBUG_PRINTF("identify=%d", value8 != 0); - } else { - DEBUG_PUTS("Status::BAD_REQUEST"); - return Status::BAD_REQUEST; - } - } else { - const auto bIsJSON = PropertiesConfig::IsJSON(); - - PropertiesConfig::EnableJSON(true); - RemoteConfig::Get()->HandleSet(m_pFileData, m_nFileDataLength); - - PropertiesConfig::EnableJSON(bIsJSON); - } - - m_pContentType = s_contentType[static_cast(contentTypes::TEXT_HTML)]; - m_nContentLength = static_cast(snprintf(m_Content, BUFSIZE - 1U, - "\n" - "\n" - "Submit\n" - "

                      OK

                      \n" - "\n")); - - return Status::OK; -} diff --git a/gd32_rdm_responder/lib/rdmidentify.cpp b/lib-remoteconfig/src/httpd/httpd.cpp old mode 100644 new mode 100755 similarity index 54% rename from gd32_rdm_responder/lib/rdmidentify.cpp rename to lib-remoteconfig/src/httpd/httpd.cpp index 3d6eba71..a3f64361 --- a/gd32_rdm_responder/lib/rdmidentify.cpp +++ b/lib-remoteconfig/src/httpd/httpd.cpp @@ -1,8 +1,8 @@ /** - * @file rdmidentify.cpp + * @file httpd.cpp * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,40 +23,48 @@ * THE SOFTWARE. */ -#include "rdmidentify.h" -#include "rdmresponder.h" -#include "pixeltestpattern.h" +#include +#include +#include +#include -#include "debug.h" +#include "httpd/httpd.h" -static bool s_isOn = false; -static pixelpatterns::Pattern s_Pattern; +#include "network.h" +#include "net/apps/mdns.h" -using namespace rdm::identify; +#include "../../lib-network/config/net_config.h" -void RDMIdentify::On(rdm::identify::Mode nMode) { +HttpDaemon::HttpDaemon() { DEBUG_ENTRY - DEBUG_PRINTF("Mode=%u, s_isOn=%d", static_cast(nMode), s_isOn); - if ((nMode == rdm::identify::Mode::LOUD) && (!s_isOn)) { - s_isOn = true; - s_Pattern = PixelTestPattern::Get()->GetPattern(); - PixelTestPattern::Get()->SetPattern(pixelpatterns::Pattern::FADE); - RDMResponder::Get()->DmxDisableOutput(true); + assert(m_nHandle == -1); + m_nHandle = Network::Get()->TcpBegin(80); + assert(m_nHandle != -1); + + for (uint32_t nIndex = 0; nIndex < TCP_MAX_TCBS_ALLOWED; nIndex++) { + pHandleRequest[nIndex] = new HttpDeamonHandleRequest(nIndex, m_nHandle); + assert(pHandleRequest[nIndex] != nullptr); } + assert(MDNS::Get() != nullptr); + MDNS::Get()->ServiceRecordAdd(nullptr, mdns::Services::HTTP); + DEBUG_EXIT } -void RDMIdentify::Off(__attribute__((unused)) rdm::identify::Mode nMode) { +HttpDaemon::~HttpDaemon() { DEBUG_ENTRY - DEBUG_PRINTF("Mode=%u, s_isOn=%d", static_cast(nMode), s_isOn); - if (s_isOn) { - s_isOn = false; - PixelTestPattern::Get()->SetPattern(s_Pattern); - RDMResponder::Get()->DmxDisableOutput(pixelpatterns::Pattern::NONE != s_Pattern); + MDNS::Get()->ServiceRecordDelete(mdns::Services::HTTP); + + for (uint32_t nIndex = 0; nIndex < TCP_MAX_TCBS_ALLOWED; nIndex++) { + if (pHandleRequest[nIndex] != nullptr) { + delete pHandleRequest[nIndex]; + } } + Network::Get()->TcpEnd(m_nHandle); + DEBUG_EXIT } diff --git a/lib-remoteconfig/src/httpd/httpdhandlerequest.cpp b/lib-remoteconfig/src/httpd/httpdhandlerequest.cpp new file mode 100755 index 00000000..8e92aef1 --- /dev/null +++ b/lib-remoteconfig/src/httpd/httpdhandlerequest.cpp @@ -0,0 +1,758 @@ +/** + * @file httpdhandlerequest.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#if !defined(__clang__) +# pragma GCC push_options +# pragma GCC optimize ("O2") +#endif + +#include +#include +#include +#include +#include + +#include "httpd/httpdhandlerequest.h" + +#include "../http/content/json_switch.h" + +#include "remoteconfig.h" +#include "remoteconfigjson.h" +#include "properties.h" +#include "sscan.h" +#include "propertiesconfig.h" + +#include "hardware.h" +#include "network.h" +#include "net/apps/mdns.h" +#include "display.h" + +#if defined(RDM_CONTROLLER) +# include "artnetnode.h" +#endif + +#if !defined (CONFIG_HTTP_HTML_NO_DMX) +# if defined(OUTPUT_DMX_SEND) || defined(OUTPUT_DMX_SEND_MULTI) +# define HAVE_DMX +# endif +# if defined(OUTPUT_DMX_PIXEL) || defined(OUTPUT_DMX_PIXEL_MULTI) +# define HAVE_PIXEL +# endif +#endif + +#if defined (NODE_SHOWFILE) +# define ENABLE_METHOD_DELETE +#endif + +#include "debug.h" + +#if defined ENABLE_CONTENT +//uint32_t get_file_content(const char *fileName, char *pDst, http::contentTypes& contentType); +const char *get_file_content(const char *fileName, uint32_t& nSize, http::contentTypes& contentType); +#endif + +char HttpDeamonHandleRequest::m_DynamicContent[http::BUFSIZE]; + +#ifndef NDEBUG +static constexpr char s_request_method[][8] = {"GET", "POST", "DELETE", "UNKNOWN" }; +#endif + +static constexpr char s_contentType[static_cast(http::contentTypes::NOT_DEFINED)][32] = +{ "text/html", "text/css", "text/javascript", "application/json", "application/octet-stream" }; + +void HttpDeamonHandleRequest::HandleRequest(const uint32_t nBytesReceived, char *pRequestHeaderResponse) { + DEBUG_ENTRY + + m_nBytesReceived = nBytesReceived; + m_RequestHeaderResponse = pRequestHeaderResponse; + + const char *pStatusMsg = "OK"; + + DEBUG_PRINTF("%u: m_Status=%u", m_nConnectionHandle, static_cast(m_Status)); + + if (m_Status == http::Status::UNKNOWN_ERROR) { + // This is an initial incoming HTTP request + m_Status = ParseRequest(); + + DEBUG_PRINTF("%s %s", s_request_method[static_cast(m_RequestMethod)], s_contentType[static_cast(m_ContentType)]); + + if (m_Status == http::Status::OK) { + // It is a supported request + + if (m_RequestMethod == http::RequestMethod::GET) { + m_Status = HandleGet(); + } else if (m_RequestMethod == http::RequestMethod::POST) { + m_Status = HandlePost(false); + + if ((m_Status == http::Status::OK) && (m_nFileDataLength == 0)) { + DEBUG_PUTS("There is a POST header only -> no data"); + DEBUG_EXIT + return; + } + } +#if defined (ENABLE_METHOD_DELETE) + else if (m_RequestMethod == http::RequestMethod::DELETE) { + m_Status = HandleDelete(false); + + if ((m_Status == http::Status::OK) && (m_nFileDataLength == 0)) { + DEBUG_PUTS("There is a DELETE header only -> no data"); + DEBUG_EXIT + return; + } + } +#endif + } + } else if ((m_Status == http::Status::OK) && (m_RequestMethod == http::RequestMethod::POST)) { + m_Status = HandlePost(true); + } +#if defined (ENABLE_METHOD_DELETE) + else if ((m_Status == http::Status::OK) && (m_RequestMethod == http::RequestMethod::DELETE)) { + m_Status = HandleDelete(true); + } +#endif + + if (m_Status != http::Status::OK) { + switch (m_Status) { + case http::Status::BAD_REQUEST: + pStatusMsg = "Bad Request"; + break; + case http::Status::NOT_FOUND: + pStatusMsg = "Not Found"; + break; + case http::Status::REQUEST_ENTITY_TOO_LARGE: + pStatusMsg = "Request Entity Too Large"; + break; + case http::Status::REQUEST_URI_TOO_LONG: + pStatusMsg = "Request-URI Too Long"; + break; + case http::Status::INTERNAL_SERVER_ERROR: + pStatusMsg = "Internal Server Error"; + break; + case http::Status::METHOD_NOT_IMPLEMENTED: + pStatusMsg = "Method Not Implemented"; + break; + case http::Status::VERSION_NOT_SUPPORTED: + pStatusMsg = "Version Not Supported"; + break; + default: + pStatusMsg = "Unknown Error"; + break; + } + + m_ContentType = http::contentTypes::TEXT_HTML; + m_pContent = m_DynamicContent; + m_nContentSize = static_cast(snprintf(m_DynamicContent, http::BUFSIZE - 1U, + "\n" + "\n" + "%u %s\n" + "

                      %s

                      \n" + "\n", static_cast(m_Status), pStatusMsg, pStatusMsg)); + } + + const auto nHeaderLength = snprintf(m_RequestHeaderResponse, http::BUFSIZE - 1U, + "HTTP/1.1 %u %s\r\n" + "Server: %s\r\n" + "Content-Type: %s\r\n" + "Content-Length: %u\r\n" + "Connection: close\r\n" + "\r\n", static_cast(m_Status), pStatusMsg, Network::Get()->GetHostName(), s_contentType[static_cast(m_ContentType)], static_cast(m_nContentSize)); + + Network::Get()->TcpWrite(m_nHandle, reinterpret_cast(m_RequestHeaderResponse), nHeaderLength, m_nConnectionHandle); + Network::Get()->TcpWrite(m_nHandle, reinterpret_cast(m_pContent), m_nContentSize, m_nConnectionHandle); + DEBUG_PRINTF("m_nContentLength=%u", m_nContentSize); + + m_Status = http::Status::UNKNOWN_ERROR; + m_RequestMethod = http::RequestMethod::UNKNOWN; + + DEBUG_EXIT +} + +http::Status HttpDeamonHandleRequest::ParseRequest() { + char *pLine = m_RequestHeaderResponse; + uint32_t nLine = 0; + http::Status status = http::Status::UNKNOWN_ERROR; + m_ContentType = http::contentTypes::NOT_DEFINED; + m_nRequestContentSize = 0; + m_nFileDataLength = 0; + + for (uint32_t i = 0; i < m_nBytesReceived; i++) { + if (m_RequestHeaderResponse[i] == '\n') { + assert(i > 1); + m_RequestHeaderResponse[i - 1] = '\0'; + + if (nLine++ == 0) { + status = ParseMethod(pLine); + } else { + if (pLine[0] == '\0') { + assert((i + 1) <= m_nBytesReceived); + m_nFileDataLength = static_cast(m_nBytesReceived - 1 - i); + if (m_nFileDataLength > 0) { + m_pFileData = &m_RequestHeaderResponse[i + 1]; + m_pFileData[m_nFileDataLength] = '\0'; + } + return http::Status::OK; + } + status = ParseHeaderField(pLine); + } + + if (status != http::Status::OK) { + return status; + } + + pLine = &m_RequestHeaderResponse[++i]; + } + } + + return http::Status::OK; +} + +/** + * Supported: "METHOD uri HTTP/1.1" + * Where METHOD is "GET", "POST" or "DELETE" + */ + +http::Status HttpDeamonHandleRequest::ParseMethod(char *pLine) { + assert(pLine != nullptr); + char *pToken; + + if ((pToken = strtok(pLine, " ")) == nullptr) { + return http::Status::METHOD_NOT_IMPLEMENTED; + } + + if (strcmp(pToken, "GET") == 0) { + m_RequestMethod = http::RequestMethod::GET; + } else if (strcmp(pToken, "POST") == 0) { + m_RequestMethod = http::RequestMethod::POST; + } +#if defined (ENABLE_METHOD_DELETE) + else if (strcmp(pToken, "DELETE") == 0) { + m_RequestMethod = http::RequestMethod::DELETE; + } +#endif + else { + return http::Status::METHOD_NOT_IMPLEMENTED; + } + + if ((pToken = strtok(nullptr, " ")) == nullptr) { + return http::Status::BAD_REQUEST; + } + + m_pUri = pToken; + + if ((pToken = strtok(nullptr, "/")) == nullptr || strcmp(pToken, "HTTP") != 0) { + return http::Status::BAD_REQUEST; + } + + if ((pToken = strtok(nullptr, " \n")) == nullptr) { + return http::Status::BAD_REQUEST; + } + + if (strcmp(pToken, "1.1") != 0) { + return http::Status::VERSION_NOT_SUPPORTED; + } + + return http::Status::OK; +} + +/** + * Only interested in "Content-Type" and "Content-Length" + * Where we check for "Content-Type: application/json" and "Content-Type: application/octet-stream" + */ + +http::Status HttpDeamonHandleRequest::ParseHeaderField(char *pLine) { + DEBUG_ENTRY + char *pToken; + + assert(pLine != nullptr); + + if ((pToken = strtok(pLine, ":")) == nullptr) { + return http::Status::BAD_REQUEST; + } + + if (strcasecmp(pToken, "Content-Type") == 0) { + if ((pToken = strtok(nullptr, " ;")) == nullptr) { + return http::Status::BAD_REQUEST; + } + if (memcmp(pToken, "application/", 12) == 0) { + if (strcmp(&pToken[12], "json") == 0) { + m_ContentType = http::contentTypes::APPLICATION_JSON; + DEBUG_ENTRY + return http::Status::OK; + } + if (strcmp(&pToken[12], "octet-stream") == 0) { + m_ContentType = http::contentTypes::APPLICATION_OCTET_STREAM; + DEBUG_ENTRY + return http::Status::OK; + } + } + } else if (strcasecmp(pToken, "Content-Length") == 0) { + if ((pToken = strtok(nullptr, " ")) == nullptr) { + return http::Status::BAD_REQUEST; + } + + uint32_t nTmp = 0; + while (*pToken != '\0') { + auto nDigit = static_cast(*pToken++ - '0'); + if (nDigit > 9) { + return http::Status::BAD_REQUEST; + } + + nTmp *= 10; + nTmp += nDigit; + } + + m_nRequestContentSize = nTmp; + } + + DEBUG_EXIT + return http::Status::OK; +} + +/** + * GET + */ + +http::Status HttpDeamonHandleRequest::HandleGet() { + DEBUG_ENTRY + + uint32_t nLength = 0; + m_pContent = &m_DynamicContent[0]; + + if (memcmp(m_pUri, "/json/", 6) == 0) { + m_ContentType = http::contentTypes::APPLICATION_JSON; + const auto *pGet = &m_pUri[6]; + switch (http::get_uint(pGet)) { + case http::json::get::LIST: + nLength = remoteconfig::json_get_list(m_DynamicContent, sizeof(m_DynamicContent)); + break; + case http::json::get::VERSION: + nLength = remoteconfig::json_get_version(m_DynamicContent, sizeof(m_DynamicContent)); + break; + case http::json::get::UPTIME: + if (!RemoteConfig::Get()->IsEnableUptime()) { + DEBUG_PUTS("Status::BAD_REQUEST"); + return http::Status::BAD_REQUEST; + } + nLength = remoteconfig::json_get_uptime(m_DynamicContent, sizeof(m_DynamicContent)); + break; + case http::json::get::DISPLAY: + nLength = remoteconfig::json_get_display(m_DynamicContent, sizeof(m_DynamicContent)); + break; + case http::json::get::DIRECTORY: + nLength = remoteconfig::json_get_directory(m_DynamicContent, sizeof(m_DynamicContent)); + break; + case http::json::get::TIMEDATE: + nLength = remoteconfig::timedate::json_get_timeofday(m_DynamicContent, sizeof(m_DynamicContent)); + break; +#if !defined (DISABLE_RTC) + case http::json::get::RTCALARM: + nLength = remoteconfig::rtc::json_get_rtc(m_DynamicContent, sizeof(m_DynamicContent)); + break; +#endif +#if defined (RDM_CONTROLLER) && !defined (CONFIG_HTTP_HTML_NO_RDM) + case http::json::get::RDM: + nLength = remoteconfig::rdm::json_get_rdm(m_DynamicContent, sizeof(m_DynamicContent)); + break; +#endif +#if defined (ARTNET_CONTROLLER) + case http::json::get::POLLTABLE: + nLength = remoteconfig::artnet::controller::json_get_polltable(m_DynamicContent, sizeof(m_DynamicContent)); + break; +#endif +#if defined (ENABLE_NET_PHYSTATUS) + case http::json::get::PHYSTATUS: + nLength = remoteconfig::net::json_get_phystatus(m_DynamicContent, sizeof(m_DynamicContent)); + break; +#endif + default: +#if defined (HAVE_DMX) + if (memcmp(pGet, "dmx/", 4) == 0) { + const auto *pDmx = &pGet[4]; + const bool isQuestionMark = (pDmx[6] == '?'); // Handle /dmx/status?X + if (isQuestionMark) { + auto *p = const_cast(pDmx); + p[6] = '\0'; + } + DEBUG_PRINTF("pDmx=[%s]", pDmx); + switch (http::get_uint(pDmx)) { + case http::json::get::PORTSTATUS: + nLength = remoteconfig::dmx::json_get_ports(m_DynamicContent, sizeof(m_DynamicContent)); + break; + case http::json::get::STATUS: { + const auto *pStatus = &pDmx[7]; + if (isQuestionMark && isalpha(static_cast(pStatus[0]))) { + nLength = remoteconfig::dmx::json_get_portstatus(pStatus[0], m_DynamicContent, sizeof(m_DynamicContent)); + } + } + default: + break; + } + } else +#endif +#if defined (HAVE_PIXEL) + if (memcmp(pGet, "pixel/", 6) == 0) { + const auto *pPixel = &pGet[6]; + switch (http::get_uint(pPixel)) { + case http::json::get::TYPES: + nLength = remoteconfig::pixel::json_get_types(m_DynamicContent, sizeof(m_DynamicContent)); + break; + case http::json::get::STATUS: + nLength = remoteconfig::pixel::json_get_status(m_DynamicContent, sizeof(m_DynamicContent)); + break; + default: + break; + } + } else +#endif +#if defined (RDM_CONTROLLER) && !defined (CONFIG_HTTP_HTML_NO_RDM) + if (memcmp(pGet, "rdm/", 4) == 0) { + const auto *pRdm = &pGet[4]; + const bool isQuestionMark = (pRdm[3] == '?'); // Handle /rdm/tod?X + if (isQuestionMark) { + auto *p = const_cast(pRdm); + p[3] = '\0'; + } + switch (http::get_uint(pRdm)) { + case http::json::get::QUEUE: + nLength = remoteconfig::rdm::json_get_queue(m_DynamicContent, sizeof(m_DynamicContent)); + break; + case http::json::get::PORTSTATUS: + nLength = remoteconfig::rdm::json_get_portstatus(m_DynamicContent, sizeof(m_DynamicContent)); + break; + case http::json::get::TOD: { + const auto *pTod = &pRdm[4]; + if (isQuestionMark && isalpha(static_cast(pTod[0]))) { + nLength = remoteconfig::rdm::json_get_tod(pTod[0], m_DynamicContent, sizeof(m_DynamicContent)); + } + } + break; + default: + break; + } + } else +#endif +#if !defined(DISABLE_FS) || defined (CONFIG_USB_HOST_MSC) + if (memcmp(pGet, "storage/", 8) == 0) { + const auto *pStorage = &pGet[8]; + switch (http::get_uint(pStorage)) { + case http::json::get::DIRECTORY: + nLength = remoteconfig::storage::json_get_directory(m_DynamicContent, sizeof(m_DynamicContent)); + break; + default: + break; + } + } else +#endif +#if defined (ENABLE_PHY_SWITCH) + if (memcmp(pGet, "dsa/", 4) == 0) { + const auto *pDsa = &pGet[4]; + switch (http::get_uint(pDsa)) { + case http::json::get::PORTSTATUS: + nLength = remoteconfig::dsa::json_get_portstatus(m_DynamicContent, sizeof(m_DynamicContent)); + break; + case http::json::get::VLANTABLE: + nLength = remoteconfig::dsa::json_get_vlantable(m_DynamicContent, sizeof(m_DynamicContent)); + break; + default: + break; + } + } else +#endif +#if defined (NODE_SHOWFILE) + if (memcmp(pGet, "showfile/", 9) == 0) { + const auto *pShowfile = &pGet[9]; + switch (http::get_uint(pShowfile)) { + case http::json::get::STATUS: + nLength = remoteconfig::showfile::json_get_status(m_DynamicContent, sizeof(m_DynamicContent)); + break; + case http::json::get::DIRECTORY: + nLength = remoteconfig::showfile::json_get_directory(m_DynamicContent, sizeof(m_DynamicContent)); + break; + default: + break; + } + } else +#endif + { + return HandleGetTxt(); + + } + break; + } + } +#if defined (ENABLE_CONTENT) + else if (strcmp(m_pUri, "/") == 0) { + m_pContent = get_file_content("index.html", nLength, m_ContentType); + } +#if defined (HAVE_DMX) + else if (strcmp(m_pUri, "/dmx") == 0) { + m_pContent = get_file_content("dmx.html", nLength, m_ContentType); + } +#endif +#if defined (RDM_CONTROLLER) && !defined (CONFIG_HTTP_HTML_NO_RDM) + else if (strcmp(m_pUri, "/rdm") == 0) { + m_pContent = get_file_content("rdm.html", nLength, m_ContentType); + } +#endif +#if defined (NODE_SHOWFILE) + else if (strcmp(m_pUri, "/showfile") == 0) { + m_pContent = get_file_content("showfile.html", nLength, m_ContentType); + } +#endif +#if defined (ENABLE_PHY_SWITCH) + else if (strcmp(m_pUri, "/dsa") == 0) { + m_pContent = get_file_content("dsa.html", nLength, m_ContentType); + } +#endif +#if !defined (CONFIG_HTTP_HTML_NO_TIME) + else if (strcmp(m_pUri, "/time") == 0) { + m_pContent = get_file_content("time.html", nLength, m_ContentType); + } +#endif +#if !defined (CONFIG_HTTP_HTML_NO_RTC) && !defined (DISABLE_RTC) + else if (strcmp(m_pUri, "/rtc") == 0) { + m_pContent = get_file_content("rtc.html", nLength, m_ContentType); + } +#endif + else { + m_pContent = get_file_content(&m_pUri[1], nLength, m_ContentType); + } +#endif + + if (nLength == 0) { + DEBUG_EXIT + return http::Status::NOT_FOUND; + } + + m_nContentSize = nLength; + + DEBUG_EXIT + return http::Status::OK; +} + +http::Status HttpDeamonHandleRequest::HandleGetTxt() { + auto *pFileName = &m_pUri[6]; + const auto nLength = strlen(pFileName); + + if (nLength <= 4) { + return http::Status::BAD_REQUEST; + } + + if (strcmp(&pFileName[nLength - 4], ".txt") != 0) { + return http::Status::BAD_REQUEST; + } + + const auto bIsJSON = PropertiesConfig::IsJSON(); + PropertiesConfig::EnableJSON(true); + + strncpy(m_DynamicContent, pFileName, nLength); + m_nContentSize = RemoteConfig::Get()->HandleGet(reinterpret_cast(m_DynamicContent), sizeof(m_DynamicContent)); + + PropertiesConfig::EnableJSON(bIsJSON); + + return http::Status::OK; +} + +/** + * POST + */ + +http::Status HttpDeamonHandleRequest::HandlePost(const bool hasDataOnly) { + DEBUG_ENTRY + DEBUG_PRINTF("m_nBytesReceived=%d, m_nFileDataLength=%u, m_nRequestContentLength=%u -> hasDataOnly=%c", m_nBytesReceived, m_nFileDataLength, m_nRequestContentSize, hasDataOnly ? 'Y' : 'N'); + + if (!hasDataOnly) { + if (m_ContentType != http::contentTypes::APPLICATION_JSON) { + DEBUG_EXIT + return http::Status::BAD_REQUEST; + } + + m_IsAction = (strcmp(m_pUri, "/json/action") == 0); + + if (!m_IsAction && (strcmp(m_pUri, "/json") != 0)) { + DEBUG_EXIT + return http::Status::NOT_FOUND; + } + } + + const auto hasHeadersOnly = (!hasDataOnly && ((m_nBytesReceived < m_nRequestContentSize) || m_nFileDataLength == 0)); + + if (hasHeadersOnly) { + DEBUG_PUTS("hasHeadersOnly"); + DEBUG_EXIT + return http::Status::OK; + } + + if (hasDataOnly) { + m_pFileData = m_RequestHeaderResponse; + m_nFileDataLength = static_cast(m_nBytesReceived); + } + + DEBUG_PRINTF("%d|%.*s|->%c", m_nFileDataLength, m_nFileDataLength, m_pFileData, m_IsAction ? 'Y' : 'N'); + + if (m_IsAction) { + auto const nJsonLength = properties::convert_json_file(m_pFileData, m_nFileDataLength, true); + + if (nJsonLength <= 0) { + DEBUG_PUTS("Status::BAD_REQUEST"); + DEBUG_EXIT + return http::Status::BAD_REQUEST; + } + + m_pFileData[nJsonLength - 1] = '\0'; + debug_dump(m_pFileData, nJsonLength); + + uint8_t value8; + + if (Sscan::Uint8(m_pFileData, "reboot", value8) == Sscan::OK) { + if (value8 != 0) { + if (!RemoteConfig::Get()->IsEnableReboot()) { + DEBUG_PUTS("Status::BAD_REQUEST"); + DEBUG_EXIT + return http::Status::BAD_REQUEST; + } + DEBUG_PUTS("Reboot!"); + RemoteConfig::Get()->Reboot(); + __builtin_unreachable(); + } + } else if (Sscan::Uint8(m_pFileData, "display", value8) == Sscan::OK) { + Display::Get()->SetSleep(value8 == 0); + DEBUG_PRINTF("Display::Get()->SetSleep(%d)", value8 == 0); + } else if (Sscan::Uint8(m_pFileData, "identify", value8) == Sscan::OK) { + if (value8 != 0) { + Hardware::Get()->SetMode(hardware::ledblink::Mode::FAST); + } else { + Hardware::Get()->SetMode(hardware::ledblink::Mode::NORMAL); + } + DEBUG_PRINTF("identify=%d", value8 != 0); + } else if (memcmp(m_pFileData, "date=", 5) == 0) { + remoteconfig::timedate::json_set_timeofday(m_pFileData, nJsonLength); + } +#if !defined (DISABLE_RTC) + else if (memcmp(m_pFileData, "rtc=", 4) == 0) { + remoteconfig::rtc::json_set_rtc(m_pFileData, nJsonLength); + } +#endif +#if defined (RDM_CONTROLLER) + else if (Sscan::Uint8(m_pFileData, "rdm", value8) == Sscan::OK) { + ArtNetNode::Get()->SetRdm(!(value8 != 1)); + DEBUG_PRINTF("rdm=%d", ArtNetNode::Get()->GetRdm()); + } +#endif +#if defined (NODE_SHOWFILE) + else if (memcmp(m_pFileData, "show=", 5) == 0) { + remoteconfig::showfile::json_set_status(m_pFileData, nJsonLength); + } +#endif + else { + DEBUG_PUTS("Status::BAD_REQUEST"); + DEBUG_EXIT + return http::Status::BAD_REQUEST; + } + } else { + const auto bIsJSON = PropertiesConfig::IsJSON(); + + PropertiesConfig::EnableJSON(true); + RemoteConfig::Get()->HandleSet(m_pFileData, m_nFileDataLength); + PropertiesConfig::EnableJSON(bIsJSON); + } + + m_ContentType = http::contentTypes::TEXT_HTML; + m_nContentSize = static_cast(snprintf(m_DynamicContent, http::BUFSIZE - 1U, + "\n" + "\n" + "Submit\n" + "

                      OK

                      \n" + "\n")); + + DEBUG_EXIT + return http::Status::OK; +} + +http::Status HttpDeamonHandleRequest::HandleDelete(const bool hasDataOnly) { + DEBUG_PRINTF("m_nBytesReceived=%d, m_nFileDataLength=%u, m_nRequestContentLength=%u -> hasDataOnly=%c", m_nBytesReceived, m_nFileDataLength, m_nRequestContentSize, hasDataOnly ? 'Y' : 'N'); + + if (!hasDataOnly) { + if (m_ContentType != http::contentTypes::APPLICATION_JSON) { + DEBUG_EXIT + return http::Status::BAD_REQUEST; + } + + m_IsAction = (strcmp(m_pUri, "/json/action") == 0); + + if (!m_IsAction) { + DEBUG_EXIT + return http::Status::NOT_FOUND; + } + } + + const auto hasHeadersOnly = (!hasDataOnly && ((m_nBytesReceived < m_nRequestContentSize) || m_nFileDataLength == 0)); + + if (hasHeadersOnly) { + DEBUG_PUTS("hasHeadersOnly"); + DEBUG_EXIT + return http::Status::OK; + } + + if (hasDataOnly) { + m_pFileData = m_RequestHeaderResponse; + m_nFileDataLength = static_cast(m_nBytesReceived); + } + + DEBUG_PRINTF("%d|%.*s|->%d", m_nFileDataLength, m_nFileDataLength, m_pFileData, m_IsAction); + + auto const nJsonLength = properties::convert_json_file(m_pFileData, m_nFileDataLength, true); + + if (nJsonLength <= 0) { + DEBUG_PUTS("Status::BAD_REQUEST"); + DEBUG_EXIT + return http::Status::BAD_REQUEST; + } + + m_pFileData[nJsonLength - 1] = '\0'; + debug_dump(m_pFileData, nJsonLength); + +#if defined (NODE_SHOWFILE) + if (memcmp(m_pFileData, "show=", 5) == 0) { + remoteconfig::showfile::json_delete(m_pFileData, nJsonLength); + } else +#endif + { + DEBUG_PUTS("Status::BAD_REQUEST"); + DEBUG_EXIT + return http::Status::BAD_REQUEST; + } + + m_ContentType = http::contentTypes::TEXT_HTML; + m_nContentSize = static_cast(snprintf(m_DynamicContent, http::BUFSIZE - 1U, + "\n" + "\n" + "Submit\n" + "

                      OK

                      \n" + "\n")); + + DEBUG_EXIT + return http::Status::OK; +} diff --git a/lib-remoteconfig/src/linux/tftpfileserver.cpp b/lib-remoteconfig/src/linux/tftpfileserver.cpp index 038aa344..00fcca79 100644 --- a/lib-remoteconfig/src/linux/tftpfileserver.cpp +++ b/lib-remoteconfig/src/linux/tftpfileserver.cpp @@ -41,13 +41,13 @@ void TFTPFileServer::Exit() { DEBUG_EXIT } -bool TFTPFileServer::FileOpen(__attribute__((unused)) const char* pFileName, __attribute__((unused)) tftp::Mode mode) { +bool TFTPFileServer::FileOpen([[maybe_unused]] const char* pFileName, [[maybe_unused]] tftp::Mode mode) { DEBUG_ENTRY DEBUG_EXIT return false; } -bool TFTPFileServer::FileCreate(__attribute__((unused)) const char* pFileName, __attribute__((unused)) tftp::Mode mode) { +bool TFTPFileServer::FileCreate([[maybe_unused]] const char* pFileName, [[maybe_unused]] tftp::Mode mode) { DEBUG_ENTRY DEBUG_EXIT return false; @@ -59,13 +59,13 @@ bool TFTPFileServer::FileClose() { return false; } -size_t TFTPFileServer::FileRead(__attribute__((unused)) void* pBuffer, __attribute__((unused)) size_t nCount, __attribute__((unused)) unsigned nBlockNumber) { +size_t TFTPFileServer::FileRead([[maybe_unused]] void* pBuffer, [[maybe_unused]] size_t nCount, [[maybe_unused]] unsigned nBlockNumber) { DEBUG_ENTRY DEBUG_EXIT return 0; } -size_t TFTPFileServer::FileWrite(__attribute__((unused)) const void *pBuffer, __attribute__((unused)) size_t nCount, __attribute__((unused)) unsigned nBlockNumber) { +size_t TFTPFileServer::FileWrite([[maybe_unused]] const void *pBuffer, [[maybe_unused]] size_t nCount, [[maybe_unused]] unsigned nBlockNumber) { DEBUG_ENTRY DEBUG_EXIT return 0; diff --git a/lib-remoteconfig/src/remoteconfig.cpp b/lib-remoteconfig/src/remoteconfig.cpp index b3f96859..dfa594cc 100644 --- a/lib-remoteconfig/src/remoteconfig.cpp +++ b/lib-remoteconfig/src/remoteconfig.cpp @@ -2,7 +2,7 @@ * @file remoteconfig.cpp * */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -40,6 +40,9 @@ #include "hardware.h" #include "network.h" +#if !defined (CONFIG_REMOTECONFIG_MINIMUM) +# include "net/apps/mdns.h" +#endif #include "display.h" #include "properties.h" @@ -51,15 +54,14 @@ /* rconfig.txt */ #include "remoteconfigparams.h" -#include "storeremoteconfig.h" +/* env.txt */ +#include "envparams.h" /* network.txt */ #include "networkparams.h" -#include "storenetwork.h" #if defined(DISPLAY_UDF) /* display.txt */ # include "displayudfparams.h" -# include "storedisplayudf.h" #endif /** @@ -68,57 +70,47 @@ #if defined (NODE_ARTNET) /* artnet.txt */ +# include "artnetnode.h" # include "artnetparams.h" -# include "storeartnet.h" #endif #if defined (NODE_E131) /* e131.txt */ # include "e131params.h" -# include "storee131.h" #endif #if defined (NODE_OSC_CLIENT) /* oscclnt.txt */ # include "oscclientparams.h" -# include "storeoscclient.h" #endif #if defined (NODE_OSC_SERVER) /* osc.txt */ # include "oscserverparams.h" -# include "storeoscserver.h" #endif #if defined (NODE_LTC_SMPTE) /* ltc.txt */ # include "ltcparams.h" -# include "storeltc.h" /* ldisplay.txt */ # include "ltcdisplayparams.h" -# include "storeltcdisplay.h" /* tcnet.txt */ # include "tcnetparams.h" -# include "storetcnet.h" /* gps.txt */ # include "gpsparams.h" -# include "storegps.h" /* etc.txt */ # include "ltcetcparams.h" -# include "storeltcetc.h" #endif #if defined(NODE_SHOWFILE) /* show.txt */ # include "showfileparams.h" -# include "storeshowfile.h" #endif #if defined(NODE_NODE) /* node.txt */ # include "node.h" # include "nodeparams.h" -# include "storenode.h" #endif /** @@ -128,47 +120,44 @@ #if defined (OUTPUT_DMX_SEND) /* params.txt */ # include "dmxparams.h" -# include "storedmxsend.h" #endif #if defined (OUTPUT_DMX_PIXEL) /* devices.txt */ # include "pixeldmxparams.h" -# include "storepixeldmx.h" #endif #if defined (OUTPUT_DMX_TLC59711) /* devices.txt */ # include "tlc59711dmxparams.h" -# include "storetlc59711.h" #endif #if defined (OUTPUT_DMX_MONITOR) /* mon.txt */ # include "dmxmonitorparams.h" -# include "storemonitor.h" #endif #if defined(OUTPUT_DMX_STEPPER) /* sparkfun.txt */ # include "sparkfundmxparams.h" -# include "storesparkfundmx.h" /* motor%.txt */ # include "modeparams.h" # include "motorparams.h" # include "l6470params.h" -# include "storemotors.h" #endif #if defined (OUTPUT_DMX_SERIAL) /* serial.txt */ # include "dmxserialparams.h" -# include "storedmxserial.h" #endif #if defined (OUTPUT_RGB_PANEL) /* rgbpanel.txt */ # include "rgbpanelparams.h" -# include "storergbpanel.h" +#endif + +#if defined (OUTPUT_DMX_PCA9685) +/* pca9685.txt */ +# include "pca9685dmxparams.h" #endif /** @@ -178,14 +167,11 @@ #if defined (RDM_RESPONDER) /* rdm_device.txt */ # include "rdmdeviceparams.h" -# include "storerdmdevice.h" /* sensors.txt */ # include "rdmsensorsparams.h" -# include "storerdmsensors.h" /* "subdev.txt" */ -# if defined (ENABLE_RDM_SUBDEVICES) +# if defined (CONFIG_RDM_ENABLE_SUBDEVICES) # include "rdmsubdevicesparams.h" -# include "storerdmsubdevices.h" # endif #endif @@ -198,10 +184,13 @@ namespace get { enum class Command { REBOOT, LIST, - UPTIME, VERSION, DISPLAY, #if !defined (CONFIG_REMOTECONFIG_MINIMUM) + UPTIME, +# if (defined (NODE_ARTNET) || defined (NODE_NODE)) && (defined (RDM_CONTROLLER) || defined (RDM_RESPONDER)) + RDM, +# endif GET, #endif TFTP, @@ -210,38 +199,52 @@ enum class Command { } // namespace get namespace set { enum class Command { - TFTP, DISPLAY +#if !defined (CONFIG_REMOTECONFIG_MINIMUM) +# if (defined (NODE_ARTNET) || defined (NODE_NODE)) && (defined (RDM_CONTROLLER) || defined (RDM_RESPONDER)) + RDM, +# endif +#endif + TFTP, + DISPLAY }; } // namespace set } // namespace udp } // namespace remoteconfig -const struct RemoteConfig::Commands RemoteConfig::s_GET[] = { +constexpr struct RemoteConfig::Commands RemoteConfig::s_GET[] = { { &RemoteConfig::HandleReboot, "reboot##", 8, false }, { &RemoteConfig::HandleList, "list#", 5, false }, - { &RemoteConfig::HandleUptime, "uptime#", 7, false }, { &RemoteConfig::HandleVersion, "version#", 8, false }, { &RemoteConfig::HandleDisplayGet, "display#", 8, false }, #if !defined (CONFIG_REMOTECONFIG_MINIMUM) + { &RemoteConfig::HandleUptime, "uptime#", 7, false }, +# if (defined (NODE_ARTNET) || defined (NODE_NODE)) && (defined (RDM_CONTROLLER) || defined (RDM_RESPONDER)) + { &RemoteConfig::HandleRdmGet, "rdm#", 4, false }, +# endif { &RemoteConfig::HandleGetNoParams, "get#", 4, true }, #endif { &RemoteConfig::HandleTftpGet, "tftp#", 5, false }, { &RemoteConfig::HandleFactory, "factory##", 9, false } }; -const struct RemoteConfig::Commands RemoteConfig::s_SET[] = { +constexpr struct RemoteConfig::Commands RemoteConfig::s_SET[] = { +#if !defined (CONFIG_REMOTECONFIG_MINIMUM) +# if (defined (NODE_ARTNET) || defined (NODE_NODE)) && (defined (RDM_CONTROLLER) || defined (RDM_RESPONDER)) + { &RemoteConfig::HandleRdmSet, "rdm#", 4, true }, +# endif +#endif { &RemoteConfig::HandleTftpSet, "tftp#", 5, true }, { &RemoteConfig::HandleDisplaySet, "display#", 8, true } }; static constexpr char s_Node[static_cast(remoteconfig::Node::LAST)][18] = { "Art-Net", "sACN E1.31", "OSC Server", "LTC", "OSC Client", "RDMNet LLRP Only", "Showfile", "MIDI", "DDP", "PixelPusher", "Node", "Bootloader TFTP", "RDM Responder" }; -static constexpr char s_Output[static_cast(remoteconfig::Output::LAST)][12] = { "DMX", "RDM", "Monitor", "Pixel", "TimeCode", "OSC", "Config", "Stepper", "Player", "Art-Net", "Serial", "RGB Panel" }; +static constexpr char s_Output[static_cast(remoteconfig::Output::LAST)][12] = { "DMX", "RDM", "Monitor", "Pixel", "TimeCode", "OSC", "Config", "Stepper", "Player", "Art-Net", "Serial", "RGB Panel", "PWM" }; RemoteConfig *RemoteConfig::s_pThis; RemoteConfig::ListBin RemoteConfig::s_RemoteConfigListBin; char *RemoteConfig::s_pUdpBuffer; -RemoteConfig::RemoteConfig(remoteconfig::Node node, remoteconfig::Output output, uint32_t nActiveOutputs): +RemoteConfig::RemoteConfig(const remoteconfig::Node node, const remoteconfig::Output output, const uint32_t nActiveOutputs): m_tNode(node), m_tOutput(output), m_nActiveOutputs(nActiveOutputs) @@ -263,12 +266,36 @@ RemoteConfig::RemoteConfig(remoteconfig::Node node, remoteconfig::Output output, m_nHandle = Network::Get()->Begin(remoteconfig::udp::PORT); assert(m_nHandle != -1); +#if !defined (CONFIG_REMOTECONFIG_MINIMUM) + assert(MDNS::Get() != nullptr); + MDNS::Get()->ServiceRecordAdd(nullptr, mdns::Services::CONFIG); + +# if defined(ENABLE_TFTP_SERVER) + MDNS::Get()->ServiceRecordAdd(nullptr, mdns::Services::TFTP); +# endif + +# if defined (ENABLE_HTTPD) + m_pHttpDaemon = new HttpDaemon; + assert(m_pHttpDaemon != nullptr); +# endif +#endif + DEBUG_EXIT } RemoteConfig::~RemoteConfig() { DEBUG_ENTRY +#if !defined (CONFIG_REMOTECONFIG_MINIMUM) +# if defined (ENABLE_HTTPD) + if (m_pHttpDaemon != nullptr) { + delete m_pHttpDaemon; + } +# endif + + MDNS::Get()->ServiceRecordDelete(mdns::Services::CONFIG); +#endif + Network::Get()->End(remoteconfig::udp::PORT); m_nHandle = -1; @@ -289,10 +316,16 @@ void RemoteConfig::SetDisable(bool bDisable) { if (bDisable && !m_bDisable) { Network::Get()->End(remoteconfig::udp::PORT); m_nHandle = -1; +#if !defined (CONFIG_REMOTECONFIG_MINIMUM) + MDNS::Get()->ServiceRecordDelete(mdns::Services::CONFIG); +#endif m_bDisable = true; } else if (!bDisable && m_bDisable) { m_nHandle = Network::Get()->Begin(remoteconfig::udp::PORT); assert(m_nHandle != -1); +#if !defined (CONFIG_REMOTECONFIG_MINIMUM) + MDNS::Get()->ServiceRecordAdd(nullptr, mdns::Services::CONFIG); +#endif m_bDisable = false; } @@ -380,6 +413,7 @@ void RemoteConfig::HandleRequest() { } } +#if !defined (CONFIG_REMOTECONFIG_MINIMUM) void RemoteConfig::HandleUptime() { DEBUG_ENTRY @@ -389,29 +423,20 @@ void RemoteConfig::HandleUptime() { } const auto nUptime = Hardware::Get()->GetUpTime(); - const auto nCmdLength = s_GET[static_cast(remoteconfig::udp::get::Command::UPTIME)].nLength; + const auto nLength = snprintf(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE - 1, "uptime: %us\n", static_cast(nUptime)); - if (m_nBytesReceived == nCmdLength) { - const auto nLength = snprintf(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE - 1, "uptime: %us\n", nUptime); - Network::Get()->SendTo(m_nHandle, s_pUdpBuffer, static_cast(nLength), m_nIPAddressFrom, remoteconfig::udp::PORT); - DEBUG_EXIT - return; - } + Network::Get()->SendTo(m_nHandle, s_pUdpBuffer, static_cast(nLength), m_nIPAddressFrom, remoteconfig::udp::PORT); DEBUG_EXIT } +#endif void RemoteConfig::HandleVersion() { DEBUG_ENTRY - const auto nCmdLength = s_GET[static_cast(remoteconfig::udp::get::Command::VERSION)].nLength; - if (m_nBytesReceived == nCmdLength) { - const auto *p = FirmwareVersion::Get()->GetPrint(); - const auto nLength = snprintf(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE - 1, "version:%s", p); - Network::Get()->SendTo(m_nHandle, s_pUdpBuffer, static_cast(nLength), m_nIPAddressFrom, remoteconfig::udp::PORT); - DEBUG_EXIT - return; - } + const auto *p = FirmwareVersion::Get()->GetPrint(); + const auto nLength = snprintf(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE - 1, "version:%s", p); + Network::Get()->SendTo(m_nHandle, s_pUdpBuffer, static_cast(nLength), m_nIPAddressFrom, remoteconfig::udp::PORT); DEBUG_EXIT } @@ -419,33 +444,27 @@ void RemoteConfig::HandleVersion() { void RemoteConfig::HandleList() { DEBUG_ENTRY - const auto nCmdLength = s_GET[static_cast(remoteconfig::udp::get::Command::LIST)].nLength; - - if (m_nBytesReceived != nCmdLength) { - DEBUG_EXIT - return; - } - + constexpr auto nCmdLength = s_GET[static_cast(remoteconfig::udp::get::Command::LIST)].nLength; auto *pListResponse = &s_pUdpBuffer[nCmdLength + 2U]; const auto nListResponseBufferLength = remoteconfig::udp::BUFFER_SIZE - (nCmdLength + 2U); int32_t nListLength; if (s_RemoteConfigListBin.aDisplayName[0] != '\0') { - nListLength = snprintf(pListResponse, nListResponseBufferLength - 1, "" IPSTR ",%s,%s,%d,%s\n", + nListLength = snprintf(pListResponse, nListResponseBufferLength - 1, "" IPSTR ",%s,%s,%u,%s\n", IP2STR(Network::Get()->GetIp()), s_Node[static_cast(m_tNode)], s_Output[static_cast(m_tOutput)], - m_nActiveOutputs, + static_cast(m_nActiveOutputs), s_RemoteConfigListBin.aDisplayName); } else { - nListLength = snprintf(pListResponse, nListResponseBufferLength - 1, "" IPSTR ",%s,%s,%d\n", + nListLength = snprintf(pListResponse, nListResponseBufferLength - 1, "" IPSTR ",%s,%s,%u\n", IP2STR(Network::Get()->GetIp()), s_Node[static_cast(m_tNode)], s_Output[static_cast(m_tOutput)], - m_nActiveOutputs); + static_cast(m_nActiveOutputs)); } - Network::Get()->SendTo(m_nHandle, pListResponse, static_cast(nListLength), m_nIPAddressFrom, remoteconfig::udp::PORT); + Network::Get()->SendTo(m_nHandle, pListResponse, static_cast(nListLength), m_nIPAddressFrom, remoteconfig::udp::PORT); DEBUG_EXIT } @@ -453,14 +472,14 @@ void RemoteConfig::HandleList() { void RemoteConfig::HandleDisplaySet() { DEBUG_ENTRY - const auto nCmdLength = s_SET[static_cast(remoteconfig::udp::set::Command::DISPLAY)].nLength; + constexpr auto nCmdLength = s_SET[static_cast(remoteconfig::udp::set::Command::DISPLAY)].nLength; - if (m_nBytesReceived != (nCmdLength + 1)) { + if (m_nBytesReceived != (nCmdLength + 1U)) { DEBUG_EXIT return; } - Display::Get()->SetSleep(s_pUdpBuffer[nCmdLength + 1] == '0'); + Display::Get()->SetSleep(s_pUdpBuffer[nCmdLength + 1U] == '0'); DEBUG_PRINTF("%c", s_pUdpBuffer[nCmdLength + 1]); DEBUG_EXIT @@ -469,18 +488,43 @@ void RemoteConfig::HandleDisplaySet() { void RemoteConfig::HandleDisplayGet() { DEBUG_ENTRY - const auto nCmdLength = s_GET[static_cast(remoteconfig::udp::get::Command::DISPLAY)].nLength; const bool isOn = !(Display::Get()->isSleep()); + const auto nLength = snprintf(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE - 1, "display:%s\n", isOn ? "On" : "Off"); - if (m_nBytesReceived == nCmdLength) { - const auto nLength = snprintf(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE - 1, "display:%s\n", isOn ? "On" : "Off"); - Network::Get()->SendTo(m_nHandle, s_pUdpBuffer, static_cast(nLength), m_nIPAddressFrom, remoteconfig::udp::PORT); - } + Network::Get()->SendTo(m_nHandle, s_pUdpBuffer, static_cast(nLength), m_nIPAddressFrom, remoteconfig::udp::PORT); DEBUG_EXIT } #if !defined (CONFIG_REMOTECONFIG_MINIMUM) +#if (defined (NODE_ARTNET) || defined (NODE_NODE)) && (defined (RDM_CONTROLLER) || defined (RDM_RESPONDER)) +void RemoteConfig::HandleRdmSet() { + DEBUG_ENTRY + + const auto nCmdLength = s_SET[static_cast(remoteconfig::udp::set::Command::RDM)].nLength; + + if (m_nBytesReceived != (nCmdLength + 1U)) { + DEBUG_EXIT + return; + } + + ArtNetNode::Get()->SetRdm(s_pUdpBuffer[nCmdLength + 1U] != '0'); + + DEBUG_PRINTF("%c", s_pUdpBuffer[nCmdLength + 1U]); + DEBUG_EXIT +} + +void RemoteConfig::HandleRdmGet() { + DEBUG_ENTRY + + const bool isOn = ArtNetNode::Get()->GetRdm(); + const auto nLength = snprintf(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE - 1, "rdm:%s\n", isOn ? "On" : "Off"); + + Network::Get()->SendTo(m_nHandle, s_pUdpBuffer, static_cast(nLength), m_nIPAddressFrom, remoteconfig::udp::PORT); + + DEBUG_EXIT +} +#endif /** * GET */ @@ -492,7 +536,7 @@ uint32_t RemoteConfig::HandleGet(void *pBuffer, uint32_t nBufferLength) { uint32_t nSize; int32_t nIndex; - const auto nCmdLength = s_GET[static_cast(remoteconfig::udp::get::Command::GET)].nLength; + constexpr auto nCmdLength = s_GET[static_cast(remoteconfig::udp::get::Command::GET)].nLength; if (pBuffer == nullptr) { nSize = remoteconfig::udp::BUFFER_SIZE - nCmdLength; @@ -518,7 +562,7 @@ uint32_t RemoteConfig::HandleGet(void *pBuffer, uint32_t nBufferLength) { (this->*(handler->GetHandler))(nSize); if (pBuffer == nullptr) { - Network::Get()->SendTo(m_nHandle, s_pUdpBuffer, static_cast(nSize), m_nIPAddressFrom, remoteconfig::udp::PORT); + Network::Get()->SendTo(m_nHandle, s_pUdpBuffer, nSize, m_nIPAddressFrom, remoteconfig::udp::PORT); } else { memcpy(pBuffer, s_pUdpBuffer, std::min(nSize, nBufferLength)); } @@ -530,16 +574,25 @@ uint32_t RemoteConfig::HandleGet(void *pBuffer, uint32_t nBufferLength) { void RemoteConfig::HandleGetRconfigTxt(uint32_t& nSize) { DEBUG_ENTRY - RemoteConfigParams remoteConfigParams(StoreRemoteConfig::Get()); + RemoteConfigParams remoteConfigParams; remoteConfigParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT } +void RemoteConfig::HandleGetEnvTxt(uint32_t& nSize) { + DEBUG_ENTRY + + EnvParams envParams; + envParams.Builder(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); + + DEBUG_EXIT +} + void RemoteConfig::HandleGetNetworkTxt(uint32_t& nSize) { DEBUG_ENTRY - NetworkParams networkParams(StoreNetwork::Get()); + NetworkParams networkParams; networkParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT @@ -549,8 +602,7 @@ void RemoteConfig::HandleGetNetworkTxt(uint32_t& nSize) { void RemoteConfig::HandleGetArtnetTxt(uint32_t& nSize) { DEBUG_ENTRY - assert(StoreArtNet::Get() != nullptr); - ArtNetParams artnetParams(StoreArtNet::Get()); + ArtNetParams artnetParams; artnetParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT @@ -561,8 +613,7 @@ void RemoteConfig::HandleGetArtnetTxt(uint32_t& nSize) { void RemoteConfig::HandleGetE131Txt(uint32_t& nSize) { DEBUG_ENTRY - assert(StoreE131::Get() != nullptr); - E131Params e131params(StoreE131::Get()); + E131Params e131params; e131params.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT @@ -573,7 +624,7 @@ void RemoteConfig::HandleGetE131Txt(uint32_t& nSize) { void RemoteConfig::HandleGetOscTxt(uint32_t& nSize) { DEBUG_ENTRY - OSCServerParams oscServerParams(StoreOscServer::Get()); + OSCServerParams oscServerParams; oscServerParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT @@ -584,7 +635,7 @@ void RemoteConfig::HandleGetOscTxt(uint32_t& nSize) { void RemoteConfig::HandleGetOscClntTxt(uint32_t& nSize) { DEBUG_ENTRY - OscClientParams oscClientParams(StoreOscClient::Get()); + OscClientParams oscClientParams; oscClientParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT @@ -595,7 +646,7 @@ void RemoteConfig::HandleGetOscClntTxt(uint32_t& nSize) { void RemoteConfig::HandleGetRdmDeviceTxt(uint32_t& nSize) { DEBUG_ENTRY - RDMDeviceParams rdmDeviceParams(StoreRDMDevice::Get()); + RDMDeviceParams rdmDeviceParams; rdmDeviceParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT @@ -604,17 +655,17 @@ void RemoteConfig::HandleGetRdmDeviceTxt(uint32_t& nSize) { void RemoteConfig::HandleGetRdmSensorsTxt(uint32_t& nSize) { DEBUG_ENTRY - RDMSensorsParams rdmSensorsParams(StoreRDMSensors::Get()); + RDMSensorsParams rdmSensorsParams; rdmSensorsParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT } -# if defined (ENABLE_RDM_SUBDEVICES) +# if defined (CONFIG_RDM_ENABLE_SUBDEVICES) void RemoteConfig::HandleGetRdmSubdevTxt(uint32_t& nSize) { DEBUG_ENTRY - RDMSubDevicesParams rdmSubDevicesParams(StoreRDMSubDevices::Get()); + RDMSubDevicesParams rdmSubDevicesParams; rdmSubDevicesParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT @@ -626,7 +677,7 @@ void RemoteConfig::HandleGetRdmSubdevTxt(uint32_t& nSize) { void RemoteConfig::HandleGetParamsTxt(uint32_t& nSize) { DEBUG_ENTRY - DmxParams dmxparams(StoreDmxSend::Get()); + DmxParams dmxparams; dmxparams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT @@ -640,22 +691,20 @@ void RemoteConfig::HandleGetDevicesTxt(uint32_t& nSize) { # if defined (OUTPUT_DMX_TLC59711) bool bIsSetLedType = false; - TLC59711DmxParams tlc5911params(StoreTLC59711::Get()); - - if (tlc5911params.Load()) { + TLC59711DmxParams tlc5911params; + tlc5911params.Load(); # if defined (OUTPUT_DMX_PIXEL) - if ((bIsSetLedType = tlc5911params.IsSetLedType()) == true) { + if ((bIsSetLedType = tlc5911params.IsSetLedType()) == true) { # endif - tlc5911params.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); + tlc5911params.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); # if defined (OUTPUT_DMX_PIXEL) - } -# endif } +# endif if (!bIsSetLedType) { # endif #if defined (OUTPUT_DMX_PIXEL) - PixelDmxParams pixelDmxParams(StorePixelDmx::Get()); + PixelDmxParams pixelDmxParams; pixelDmxParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); #endif # if defined (OUTPUT_DMX_TLC59711) @@ -670,7 +719,7 @@ void RemoteConfig::HandleGetDevicesTxt(uint32_t& nSize) { void RemoteConfig::HandleGetLtcTxt(uint32_t& nSize) { DEBUG_ENTRY - LtcParams ltcParams(StoreLtc::Get()); + LtcParams ltcParams; ltcParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT @@ -679,7 +728,7 @@ void RemoteConfig::HandleGetLtcTxt(uint32_t& nSize) { void RemoteConfig::HandleGetLdisplayTxt(uint32_t& nSize) { DEBUG_ENTRY - LtcDisplayParams ltcDisplayParams(StoreLtcDisplay::Get()); + LtcDisplayParams ltcDisplayParams; ltcDisplayParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT @@ -688,7 +737,7 @@ void RemoteConfig::HandleGetLdisplayTxt(uint32_t& nSize) { void RemoteConfig::HandleGetTCNetTxt(uint32_t& nSize) { DEBUG_ENTRY - TCNetParams tcnetParams(StoreTCNet::Get()); + TCNetParams tcnetParams; tcnetParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT @@ -697,7 +746,7 @@ void RemoteConfig::HandleGetTCNetTxt(uint32_t& nSize) { void RemoteConfig::HandleGetGpsTxt(uint32_t& nSize) { DEBUG_ENTRY - GPSParams gpsParams(StoreGPS::Get()); + GPSParams gpsParams; gpsParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT @@ -706,7 +755,7 @@ void RemoteConfig::HandleGetGpsTxt(uint32_t& nSize) { void RemoteConfig::HandleGetLtcEtcTxt(uint32_t& nSize) { DEBUG_ENTRY - LtcEtcParams ltcEtcParams(StoreLtcEtc::Get()); + LtcEtcParams ltcEtcParams; ltcEtcParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT @@ -717,7 +766,7 @@ void RemoteConfig::HandleGetLtcEtcTxt(uint32_t& nSize) { void RemoteConfig::HandleGetMonTxt(uint32_t& nSize) { DEBUG_ENTRY - DMXMonitorParams monitorParams(StoreMonitor::Get()); + DMXMonitorParams monitorParams; monitorParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT @@ -728,7 +777,7 @@ void RemoteConfig::HandleGetMonTxt(uint32_t& nSize) { void RemoteConfig::HandleGetDisplayTxt(uint32_t& nSize) { DEBUG_ENTRY - DisplayUdfParams displayParams(StoreDisplayUdf::Get()); + DisplayUdfParams displayParams; displayParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT @@ -739,7 +788,7 @@ void RemoteConfig::HandleGetDisplayTxt(uint32_t& nSize) { void RemoteConfig::HandleGetSparkFunTxt(uint32_t& nSize) { DEBUG_ENTRY - SparkFunDmxParams sparkFunParams(StoreSparkFunDmx::Get()); + SparkFunDmxParams sparkFunParams; sparkFunParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT @@ -751,28 +800,28 @@ void RemoteConfig::HandleGetMotorTxt(uint32_t nMotorIndex, uint32_t& nSize) { uint32_t nSizeSparkFun = 0; - SparkFunDmxParams sparkFunParams(StoreSparkFunDmx::Get()); + SparkFunDmxParams sparkFunParams; sparkFunParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSizeSparkFun, nMotorIndex); DEBUG_PRINTF("nSizeSparkFun=%d", nSizeSparkFun); uint32_t nSizeMode = 0; - ModeParams modeParams(StoreMotors::Get()); + ModeParams modeParams; modeParams.Save(nMotorIndex, s_pUdpBuffer + nSizeSparkFun, remoteconfig::udp::BUFFER_SIZE - nSizeSparkFun, nSizeMode); DEBUG_PRINTF("nSizeMode=%d", nSizeMode); uint32_t nSizeMotor = 0; - MotorParams motorParams(StoreMotors::Get()); + MotorParams motorParams; motorParams.Save(nMotorIndex, s_pUdpBuffer + nSizeSparkFun + nSizeMode, remoteconfig::udp::BUFFER_SIZE - nSizeSparkFun - nSizeMode, nSizeMotor); DEBUG_PRINTF("nSizeMotor=%d", nSizeMotor); uint32_t nSizeL6470 = 0; - L6470Params l6470Params(StoreMotors::Get()); + L6470Params l6470Params; l6470Params.Save(nMotorIndex, s_pUdpBuffer + nSizeSparkFun + nSizeMode + nSizeMotor, remoteconfig::udp::BUFFER_SIZE - nSizeSparkFun - nSizeMode - nSizeMotor, nSizeL6470); DEBUG_PRINTF("nSizeL6470=%d", nSizeL6470); @@ -787,7 +836,7 @@ void RemoteConfig::HandleGetMotorTxt(uint32_t nMotorIndex, uint32_t& nSize) { void RemoteConfig::HandleGetShowTxt(uint32_t& nSize) { DEBUG_ENTRY - ShowFileParams showFileParams(StoreShowFile::Get()); + ShowFileParams showFileParams; showFileParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT @@ -798,7 +847,7 @@ void RemoteConfig::HandleGetShowTxt(uint32_t& nSize) { void RemoteConfig::HandleGetNodeTxt(const node::Personality personality, uint32_t& nSize) { DEBUG_ENTRY - NodeParams nodeParams(StoreNode::Get(), personality); + NodeParams nodeParams(personality); nodeParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT @@ -809,7 +858,7 @@ void RemoteConfig::HandleGetNodeTxt(const node::Personality personality, uint32_ void RemoteConfig::HandleGetSerialTxt(uint32_t& nSize) { DEBUG_ENTRY - DmxSerialParams dmxSerialParams(StoreDmxSerial::Get()); + DmxSerialParams dmxSerialParams; dmxSerialParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT @@ -820,13 +869,24 @@ void RemoteConfig::HandleGetSerialTxt(uint32_t& nSize) { void RemoteConfig::HandleGetRgbPanelTxt(uint32_t& nSize) { DEBUG_ENTRY - RgbPanelParams rgbPanelParams(StoreRgbPanel::Get()); + RgbPanelParams rgbPanelParams; rgbPanelParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); DEBUG_EXIT } #endif +#if defined (OUTPUT_DMX_PCA9685) +void RemoteConfig::HandleGetPca9685Txt(uint32_t& nSize) { + DEBUG_ENTRY + + PCA9685DmxParams pca9685DmxParams; + pca9685DmxParams.Save(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE, nSize); + + DEBUG_EXIT +} +#endif + #endif /** @@ -872,31 +932,30 @@ void RemoteConfig::HandleSet(void *pBuffer, uint32_t nBufferLength) { DEBUG_EXIT } -void RemoteConfig::HandleSetRconfig() { +void RemoteConfig::HandleSetRconfigTxt() { DEBUG_ENTRY - assert(StoreRemoteConfig::Get() != nullptr); - RemoteConfigParams remoteConfigParams(StoreRemoteConfig::Get()); - + RemoteConfigParams remoteConfigParams; remoteConfigParams.Load(s_pUdpBuffer, m_nBytesReceived); remoteConfigParams.Set(this); -#ifndef NDEBUG - remoteConfigParams.Dump(); -#endif DEBUG_EXIT } -void RemoteConfig::HandleSetNetworkTxt() { +void RemoteConfig::HandleSetEnvTxt() { DEBUG_ENTRY - assert(StoreNetwork::Get() != nullptr); - NetworkParams params(StoreNetwork::Get()); + EnvParams params; + params.LoadAndSet(s_pUdpBuffer, m_nBytesReceived); + DEBUG_EXIT +} + +void RemoteConfig::HandleSetNetworkTxt() { + DEBUG_ENTRY + + NetworkParams params; params.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - params.Dump(); -#endif DEBUG_EXIT } @@ -905,13 +964,8 @@ void RemoteConfig::HandleSetNetworkTxt() { void RemoteConfig::HandleSetArtnetTxt() { DEBUG_ENTRY - assert(StoreArtNet::Get() != nullptr); - ArtNetParams artnetParams(StoreArtNet::Get()); - + ArtNetParams artnetParams; artnetParams.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - artnetParams.Dump(); -#endif DEBUG_EXIT } @@ -921,13 +975,9 @@ void RemoteConfig::HandleSetArtnetTxt() { void RemoteConfig::HandleSetE131Txt() { DEBUG_ENTRY - assert(StoreE131::Get() != nullptr); - E131Params e131params(StoreE131::Get()); - + E131Params e131params; e131params.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - e131params.Dump(); -#endif + DEBUG_EXIT } #endif @@ -936,13 +986,8 @@ void RemoteConfig::HandleSetE131Txt() { void RemoteConfig::HandleSetOscTxt() { DEBUG_ENTRY - assert(StoreOscServer::Get() != nullptr); - OSCServerParams oscServerParams(StoreOscServer::Get()); - + OSCServerParams oscServerParams; oscServerParams.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - oscServerParams.Dump(); -#endif DEBUG_EXIT } @@ -952,13 +997,8 @@ void RemoteConfig::HandleSetOscTxt() { void RemoteConfig::HandleSetOscClientTxt() { DEBUG_ENTRY - assert(StoreOscClient::Get() != nullptr); - OscClientParams oscClientParams(StoreOscClient::Get()); - + OscClientParams oscClientParams; oscClientParams.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - oscClientParams.Dump(); -#endif DEBUG_EXIT } @@ -968,13 +1008,8 @@ void RemoteConfig::HandleSetOscClientTxt() { void RemoteConfig::HandleSetParamsTxt() { DEBUG_ENTRY - assert(StoreDmxSend::Get() != nullptr); - DmxParams dmxparams(StoreDmxSend::Get()); - + DmxParams dmxparams; dmxparams.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - dmxparams.Dump(); -#endif DEBUG_EXIT } @@ -985,25 +1020,16 @@ void RemoteConfig::HandleSetDevicesTxt() { DEBUG_ENTRY # if defined (OUTPUT_DMX_TLC59711) - assert(StoreTLC59711::Get() != nullptr); - TLC59711DmxParams tlc59711params(StoreTLC59711::Get()); - + TLC59711DmxParams tlc59711params; tlc59711params.Load(s_pUdpBuffer, m_nBytesReceived); -# ifndef NDEBUG - tlc59711params.Dump(); -# endif + DEBUG_PRINTF("tlc5911params.IsSetLedType()=%d", tlc59711params.IsSetLedType()); if (!tlc59711params.IsSetLedType()) { # endif #if defined (OUTPUT_DMX_PIXEL) - assert(StorePixelDmx::Get() != nullptr); - PixelDmxParams pixelDmxParams(StorePixelDmx::Get()); - + PixelDmxParams pixelDmxParams; pixelDmxParams.Load(s_pUdpBuffer, m_nBytesReceived); -# ifndef NDEBUG - pixelDmxParams.Dump(); -# endif # endif # if defined (OUTPUT_DMX_TLC59711) } @@ -1017,13 +1043,8 @@ void RemoteConfig::HandleSetDevicesTxt() { void RemoteConfig::HandleSetLtcTxt() { DEBUG_ENTRY - assert(StoreLtc::Get() != nullptr); - LtcParams ltcParams(StoreLtc::Get()); - + LtcParams ltcParams; ltcParams.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - ltcParams.Dump(); -#endif DEBUG_EXIT } @@ -1031,13 +1052,8 @@ void RemoteConfig::HandleSetLtcTxt() { void RemoteConfig::HandleSetLdisplayTxt() { DEBUG_ENTRY - assert(StoreLtcDisplay::Get() != nullptr); - LtcDisplayParams ltcDisplayParams(StoreLtcDisplay::Get()); - + LtcDisplayParams ltcDisplayParams; ltcDisplayParams.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - ltcDisplayParams.Dump(); -#endif DEBUG_EXIT } @@ -1045,13 +1061,8 @@ void RemoteConfig::HandleSetLdisplayTxt() { void RemoteConfig::HandleSetTCNetTxt() { DEBUG_ENTRY - assert(StoreTCNet::Get() != nullptr); - TCNetParams tcnetParams(StoreTCNet::Get()); - + TCNetParams tcnetParams; tcnetParams.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - tcnetParams.Dump(); -#endif DEBUG_EXIT } @@ -1059,13 +1070,8 @@ void RemoteConfig::HandleSetTCNetTxt() { void RemoteConfig::HandleSetGpsTxt() { DEBUG_ENTRY - assert(StoreGPS::Get() != nullptr); - GPSParams gpsParams(StoreGPS::Get()); - + GPSParams gpsParams; gpsParams.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - gpsParams.Dump(); -#endif DEBUG_EXIT } @@ -1073,13 +1079,8 @@ void RemoteConfig::HandleSetGpsTxt() { void RemoteConfig::HandleSetLtcEtcTxt() { DEBUG_ENTRY - assert(StoreLtcEtc::Get() != nullptr); - LtcEtcParams ltcEtcParams(StoreLtcEtc::Get()); - + LtcEtcParams ltcEtcParams; ltcEtcParams.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - ltcEtcParams.Dump(); -#endif DEBUG_EXIT } @@ -1089,13 +1090,8 @@ void RemoteConfig::HandleSetLtcEtcTxt() { void RemoteConfig::HandleSetMonTxt() { DEBUG_ENTRY - assert(StoreMonitor::Get() != nullptr); - DMXMonitorParams monitorParams(StoreMonitor::Get()); - + DMXMonitorParams monitorParams; monitorParams.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - monitorParams.Dump(); -#endif DEBUG_EXIT } @@ -1105,13 +1101,8 @@ void RemoteConfig::HandleSetMonTxt() { void RemoteConfig::HandleSetDisplayTxt() { DEBUG_ENTRY - assert(StoreDisplayUdf::Get() != nullptr); - DisplayUdfParams displayParams(StoreDisplayUdf::Get()); - + DisplayUdfParams displayParams; displayParams.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - displayParams.Dump(); -#endif DEBUG_EXIT } @@ -1121,13 +1112,8 @@ void RemoteConfig::HandleSetDisplayTxt() { void RemoteConfig::HandleSetSparkFunTxt() { DEBUG_ENTRY - assert(StoreSparkFunDmx::Get() != nullptr); - SparkFunDmxParams sparkFunDmxParams(StoreSparkFunDmx::Get()); - + SparkFunDmxParams sparkFunDmxParams; sparkFunDmxParams.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - sparkFunDmxParams.Dump(); -#endif DEBUG_EXIT } @@ -1136,35 +1122,17 @@ void RemoteConfig::HandleSetMotorTxt(uint32_t nMotorIndex) { DEBUG_ENTRY DEBUG_PRINTF("nMotorIndex=%d", nMotorIndex); - assert(StoreSparkFunDmx::Get() != nullptr); - SparkFunDmxParams sparkFunDmxParams(StoreSparkFunDmx::Get()); - + SparkFunDmxParams sparkFunDmxParams; sparkFunDmxParams.Load(nMotorIndex, s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - sparkFunDmxParams.Dump(); -#endif - - assert(StoreMotors::Get() != nullptr); - ModeParams modeParams(StoreMotors::Get()); + ModeParams modeParams; modeParams.Load(nMotorIndex, s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - modeParams.Dump(); -#endif - - MotorParams motorParams(StoreMotors::Get()); + MotorParams motorParams; motorParams.Load(nMotorIndex, s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - motorParams.Dump(); -#endif - - L6470Params l6470Params(StoreMotors::Get()); + L6470Params l6470Params; l6470Params.Load(nMotorIndex, s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - l6470Params.Dump(); -#endif DEBUG_EXIT } @@ -1174,13 +1142,8 @@ void RemoteConfig::HandleSetMotorTxt(uint32_t nMotorIndex) { void RemoteConfig::HandleSetShowTxt() { DEBUG_ENTRY - assert(StoreShowFile::Get() != nullptr); - ShowFileParams showFileParams(StoreShowFile::Get()); - + ShowFileParams showFileParams; showFileParams.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - showFileParams.Dump(); -#endif DEBUG_EXIT } @@ -1190,13 +1153,8 @@ void RemoteConfig::HandleSetShowTxt() { void RemoteConfig::HandleSetNodeTxt(const node::Personality personality) { DEBUG_ENTRY - assert(StoreNode::Get() != nullptr); - NodeParams nodeParams(StoreNode::Get(), personality); - + NodeParams nodeParams(personality); nodeParams.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - nodeParams.Dump(); -#endif DEBUG_EXIT } @@ -1206,13 +1164,8 @@ void RemoteConfig::HandleSetNodeTxt(const node::Personality personality) { void RemoteConfig::HandleSetRdmDeviceTxt() { DEBUG_ENTRY - assert(StoreRDMDevice::Get() != nullptr); - RDMDeviceParams rdmDeviceParams(StoreRDMDevice::Get()); - + RDMDeviceParams rdmDeviceParams; rdmDeviceParams.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - rdmDeviceParams.Dump(); -#endif DEBUG_EXIT } @@ -1220,28 +1173,18 @@ void RemoteConfig::HandleSetRdmDeviceTxt() { void RemoteConfig::HandleSetRdmSensorsTxt() { DEBUG_ENTRY - assert(StoreRDMSensors::Get() != nullptr); - RDMSensorsParams rdmSensorsParams(StoreRDMSensors::Get()); - + RDMSensorsParams rdmSensorsParams; rdmSensorsParams.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - rdmSensorsParams.Dump(); -#endif DEBUG_EXIT } -# if defined (ENABLE_RDM_SUBDEVICES) +# if defined (CONFIG_RDM_ENABLE_SUBDEVICES) void RemoteConfig::HandleSetRdmSubdevTxt() { DEBUG_ENTRY - assert(StoreRDMSubDevices::Get() != nullptr); - RDMSubDevicesParams rdmSubDevicesParams(StoreRDMSubDevices::Get()); - + RDMSubDevicesParams rdmSubDevicesParams; rdmSubDevicesParams.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - rdmSubDevicesParams.Dump(); -#endif DEBUG_EXIT } @@ -1252,13 +1195,8 @@ void RemoteConfig::HandleSetRdmSubdevTxt() { void RemoteConfig::HandleSetSerialTxt() { DEBUG_ENTRY - assert(StoreDmxSerial::Get() != nullptr); - DmxSerialParams dmxSerialParams(StoreDmxSerial::Get()); - + DmxSerialParams dmxSerialParams; dmxSerialParams.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - dmxSerialParams.Dump(); -#endif DEBUG_EXIT } @@ -1268,14 +1206,20 @@ void RemoteConfig::HandleSetSerialTxt() { void RemoteConfig::HandleSetRgbPanelTxt() { DEBUG_ENTRY - assert(StoreRgbPanel::Get() != nullptr); - RgbPanelParams rgbPanelParams(StoreRgbPanel::Get()); - + RgbPanelParams rgbPanelParams; rgbPanelParams.Load(s_pUdpBuffer, m_nBytesReceived); -#ifndef NDEBUG - rgbPanelParams.Dump(); + + DEBUG_EXIT +} #endif +#if defined (OUTPUT_DMX_PCA9685) +void RemoteConfig::HandleSetPca9685Txt() { + DEBUG_ENTRY + + PCA9685DmxParams pca9685DmxParams; + pca9685DmxParams.Load(s_pUdpBuffer, m_nBytesReceived); + DEBUG_EXIT } #endif @@ -1296,14 +1240,14 @@ void RemoteConfig::TftpExit() { void RemoteConfig::HandleTftpSet() { DEBUG_ENTRY - const auto nCmdLength = s_SET[static_cast(remoteconfig::udp::set::Command::TFTP)].nLength; + constexpr auto nCmdLength = s_SET[static_cast(remoteconfig::udp::set::Command::TFTP)].nLength; - if (m_nBytesReceived != (nCmdLength + 1)) { + if (m_nBytesReceived != (nCmdLength + 1U)) { DEBUG_EXIT return; } - m_bEnableTFTP = (s_pUdpBuffer[nCmdLength + 1] != '0'); + m_bEnableTFTP = (s_pUdpBuffer[nCmdLength + 1U] != '0'); if (m_bEnableTFTP) { Display::Get()->SetSleep(false); @@ -1319,14 +1263,8 @@ void RemoteConfig::HandleTftpGet() { PlatformHandleTftpGet(); - const auto nCmdLength = s_GET[static_cast(remoteconfig::udp::get::Command::TFTP)].nLength; - - if (m_nBytesReceived == nCmdLength) { - const auto nLength = snprintf(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE - 1, "tftp:%s\n", m_bEnableTFTP ? "On" : "Off"); - Network::Get()->SendTo(m_nHandle, s_pUdpBuffer, static_cast(nLength), m_nIPAddressFrom, remoteconfig::udp::PORT); - DEBUG_EXIT - return; - } + const auto nLength = snprintf(s_pUdpBuffer, remoteconfig::udp::BUFFER_SIZE - 1, "tftp:%s\n", m_bEnableTFTP ? "On" : "Off"); + Network::Get()->SendTo(m_nHandle, s_pUdpBuffer, static_cast(nLength), m_nIPAddressFrom, remoteconfig::udp::PORT); DEBUG_EXIT } diff --git a/lib-remoteconfig/src/remoteconfigfactory.cpp b/lib-remoteconfig/src/remoteconfigfactory.cpp index 0d70db95..1aa0d9b4 100644 --- a/lib-remoteconfig/src/remoteconfigfactory.cpp +++ b/lib-remoteconfig/src/remoteconfigfactory.cpp @@ -2,7 +2,7 @@ * @file remoteconfigfactory.cpp * */ -/* Copyright (C) 2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,9 +32,7 @@ void RemoteConfig::HandleFactory() { DEBUG_ENTRY - for (uint32_t i = 0; i < static_cast(configstore::Store::LAST); i++) { - ConfigStore::Get()->ResetSetList(static_cast(i)); - } + ConfigStore::Get()->ResetSetListAll(); DEBUG_EXIT } diff --git a/lib-remoteconfig/src/remoteconfigjson.cpp b/lib-remoteconfig/src/remoteconfigjson.cpp index 88103914..16a3d179 100644 --- a/lib-remoteconfig/src/remoteconfigjson.cpp +++ b/lib-remoteconfig/src/remoteconfigjson.cpp @@ -2,7 +2,7 @@ * @file remoteconfigjson.cpp * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,8 +34,8 @@ namespace remoteconfig { -uint16_t json_get_list(char *pOutBuffer, const uint16_t nOutBufferSize) { - const auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, +uint32_t json_get_list(char *pOutBuffer, const uint32_t nOutBufferSize) { + const auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, "{\"list\":{\"ip\":\"" IPSTR "\",\"name\":\"%s\",\"node\":{\"type\":\"%s\",\"port\":{\"type\":\"%s\",\"count\":%d}}}}", IP2STR(Network::Get()->GetIp()), RemoteConfig::Get()->GetDisplayName(), @@ -46,11 +46,11 @@ uint16_t json_get_list(char *pOutBuffer, const uint16_t nOutBufferSize) { return nLength; } -uint16_t json_get_version(char *pOutBuffer, const uint16_t nOutBufferSize) { +uint32_t json_get_version(char *pOutBuffer, const uint32_t nOutBufferSize) { const auto *pVersion = FirmwareVersion::Get()->GetVersion(); uint8_t nHwTextLength; - const auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, + const auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, "{\"version\":\"%.*s\",\"board\":\"%s\",\"build\":{\"date\":\"%.*s\",\"time\":\"%.*s\"}}", firmwareversion::length::SOFTWARE_VERSION, pVersion->SoftwareVersion, Hardware::Get()->GetBoardName(nHwTextLength), @@ -59,20 +59,20 @@ uint16_t json_get_version(char *pOutBuffer, const uint16_t nOutBufferSize) { return nLength; } -uint16_t json_get_uptime(char *pOutBuffer, const uint16_t nOutBufferSize) { +uint32_t json_get_uptime(char *pOutBuffer, const uint32_t nOutBufferSize) { const auto nUptime = Hardware::Get()->GetUpTime(); - const auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, "{\"uptime\":%u}\n", nUptime)); + const auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, "{\"uptime\":%u}\n", static_cast(nUptime))); return nLength; } -uint16_t json_get_display(char *pOutBuffer, const uint16_t nOutBufferSize) { +uint32_t json_get_display(char *pOutBuffer, const uint32_t nOutBufferSize) { const bool isOn = !(Display::Get()->isSleep()); - const auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, "{\"display\":%d}", isOn)); + const auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, "{\"display\":%d}", isOn)); return nLength; } -uint16_t json_get_directory(char *pOutBuffer, const uint16_t nOutBufferSize) { - const auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, +uint32_t json_get_directory(char *pOutBuffer, const uint32_t nOutBufferSize) { + const auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, "{\"files\":{" #if defined (NODE_ARTNET) "\"artnet.txt\":\"Art-Net\"," @@ -110,6 +110,9 @@ uint16_t json_get_directory(char *pOutBuffer, const uint16_t nOutBufferSize) { #if defined (OUTPUT_DMX_TLC59711) "\"devices.txt\":\"DMX TLC59711\"," #endif +#if defined (OUTPUT_DMX_PCA9685) + "\"pca9685.txt\":\"DMX PCA9685\"," +#endif #if defined (OUTPUT_DMX_MONITOR) "\"mon.txt\":\"DMX Monitor\"," #endif @@ -138,6 +141,7 @@ uint16_t json_get_directory(char *pOutBuffer, const uint16_t nOutBufferSize) { "\"display.txt\":\"Display UDF\"," #endif "\"network.txt\":\"Network\"," + "\"env.txt\":\"Environment\"," "\"rconfig.txt\":\"Remote configuration\"" "}}" )); diff --git a/lib-remoteconfig/src/remoteconfigparams.cpp b/lib-remoteconfig/src/remoteconfigparams.cpp index 89945d72..b78b2138 100644 --- a/lib-remoteconfig/src/remoteconfigparams.cpp +++ b/lib-remoteconfig/src/remoteconfigparams.cpp @@ -2,7 +2,7 @@ * @file remoteconfigparams.cpp * */ -/* Copyright (C) 2019-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -30,6 +30,7 @@ #include #include +#include #include #include "remoteconfigparams.h" @@ -42,117 +43,124 @@ #include "debug.h" -RemoteConfigParams::RemoteConfigParams(RemoteConfigParamsStore* pTRemoteConfigParamsStore): m_pRemoteConfigParamsStore(pTRemoteConfigParamsStore) { - memset(&m_tRemoteConfigParams, 0, sizeof(struct TRemoteConfigParams)); +struct ParamMask { + const char *pParam; + uint32_t nMask; +}; + +// Array of structs: parameter and corresponding mask +constexpr ParamMask paramMasks[] = { + { RemoteConfigConst::PARAMS_DISABLE, remoteconfigparams::Mask::DISABLE }, + { RemoteConfigConst::PARAMS_DISABLE_WRITE, remoteconfigparams::Mask::DISABLE_WRITE }, + { RemoteConfigConst::PARAMS_ENABLE_REBOOT, remoteconfigparams::Mask::ENABLE_REBOOT }, + { RemoteConfigConst::PARAMS_ENABLE_UPTIME, remoteconfigparams::Mask::ENABLE_UPTIME }, + { RemoteConfigConst::PARAMS_ENABLE_FACTORY, remoteconfigparams::Mask::ENABLE_FACTORY }, +}; + +RemoteConfigParams::RemoteConfigParams() { + DEBUG_ENTRY + + memset(&m_Params, 0, sizeof(struct remoteconfigparams::Params)); + + DEBUG_EXIT } -bool RemoteConfigParams::Load() { - m_tRemoteConfigParams.nSetList = 0; +void RemoteConfigParams::Load() { + DEBUG_ENTRY + + m_Params.nSetList = 0; #if !defined(DISABLE_FS) ReadConfigFile configfile(RemoteConfigParams::staticCallbackFunction, this); if (configfile.Read(RemoteConfigConst::PARAMS_FILE_NAME)) { - // There is a configuration file - if (m_pRemoteConfigParamsStore != nullptr) { - m_pRemoteConfigParamsStore->Update(&m_tRemoteConfigParams); - } + RemoteConfigParamsStore::Update(&m_Params); } else #endif - if (m_pRemoteConfigParamsStore != nullptr) { - m_pRemoteConfigParamsStore->Copy(&m_tRemoteConfigParams); - } else { - return false; - } + RemoteConfigParamsStore::Copy(&m_Params); - return true; +#ifndef NDEBUG + Dump(); +#endif + DEBUG_EXIT } -void RemoteConfigParams::Load(const char* pBuffer, uint32_t nLength) { +void RemoteConfigParams::Load(const char *pBuffer, uint32_t nLength) { DEBUG_ENTRY assert(pBuffer != nullptr); assert(nLength != 0); - m_tRemoteConfigParams.nSetList = 0; + m_Params.nSetList = 0; ReadConfigFile config(RemoteConfigParams::staticCallbackFunction, this); config.Read(pBuffer, nLength); - assert(m_pRemoteConfigParamsStore != nullptr); - m_pRemoteConfigParamsStore->Update(&m_tRemoteConfigParams); + RemoteConfigParamsStore::Update(&m_Params); +#ifndef NDEBUG + Dump(); +#endif DEBUG_EXIT } void RemoteConfigParams::SetBool(const uint8_t nValue, const uint32_t nMask) { if (nValue != 0) { - m_tRemoteConfigParams.nSetList |= nMask; + m_Params.nSetList |= nMask; } else { - m_tRemoteConfigParams.nSetList &= ~nMask; + m_Params.nSetList &= ~nMask; } } void RemoteConfigParams::callbackFunction(const char *pLine) { assert(pLine != nullptr); - uint8_t nValue8; - - if (Sscan::Uint8(pLine, RemoteConfigConst::PARAMS_DISABLE, nValue8) == Sscan::OK) { - SetBool(nValue8, RemoteConfigParamsMask::DISABLE); - return; - } - - if (Sscan::Uint8(pLine, RemoteConfigConst::PARAMS_DISABLE_WRITE, nValue8) == Sscan::OK) { - SetBool(nValue8, RemoteConfigParamsMask::DISABLE_WRITE); - return; - } - - if (Sscan::Uint8(pLine, RemoteConfigConst::PARAMS_ENABLE_REBOOT, nValue8) == Sscan::OK) { - SetBool(nValue8, RemoteConfigParamsMask::ENABLE_REBOOT); - return; - } - - if (Sscan::Uint8(pLine, RemoteConfigConst::PARAMS_ENABLE_UPTIME, nValue8) == Sscan::OK) { - SetBool(nValue8, RemoteConfigParamsMask::ENABLE_UPTIME); - return; - } - - if (Sscan::Uint8(pLine, RemoteConfigConst::PARAMS_ENABLE_FACTORY, nValue8) == Sscan::OK) { - SetBool(nValue8, RemoteConfigParamsMask::ENABLE_FACTORY); - return; - } + // Helper lambda for setting masks + auto trySetMask = [&](const char* param, const uint32_t mask) { + uint8_t nValue8; + if (Sscan::Uint8(pLine, param, nValue8) == Sscan::OK) { + SetBool(nValue8, mask); + return true; + } + return false; + }; + + // Loop through parameters and masks + for (const auto& paramMask : paramMasks) { + if (trySetMask(paramMask.pParam, paramMask.nMask)) { + return; + } + } uint32_t nLength = remoteconfig::DISPLAY_NAME_LENGTH - 1; - if (Sscan::Char(pLine, RemoteConfigConst::PARAMS_DISPLAY_NAME, m_tRemoteConfigParams.aDisplayName, nLength) == Sscan::OK) { - m_tRemoteConfigParams.aDisplayName[nLength] = '\0'; - m_tRemoteConfigParams.nSetList |= RemoteConfigParamsMask::DISPLAY_NAME; + + if (Sscan::Char(pLine, RemoteConfigConst::PARAMS_DISPLAY_NAME, m_Params.aDisplayName, nLength) == Sscan::OK) { + m_Params.aDisplayName[nLength] = '\0'; + m_Params.nSetList |= remoteconfigparams::Mask::DISPLAY_NAME; return; } } -void RemoteConfigParams::Builder(const struct TRemoteConfigParams *pRemoteConfigParams, char *pBuffer, uint32_t nLength, uint32_t& nSize) { +void RemoteConfigParams::Builder(const struct remoteconfigparams::Params *pRemoteConfigParams, char *pBuffer, uint32_t nLength, uint32_t& nSize) { DEBUG_ENTRY assert(pBuffer != nullptr); if (pRemoteConfigParams != nullptr) { - memcpy(&m_tRemoteConfigParams, pRemoteConfigParams, sizeof(struct TRemoteConfigParams)); + memcpy(&m_Params, pRemoteConfigParams, sizeof(struct remoteconfigparams::Params)); } else { - assert(m_pRemoteConfigParamsStore != nullptr); - m_pRemoteConfigParamsStore->Copy(&m_tRemoteConfigParams); + RemoteConfigParamsStore::Copy(&m_Params); } PropertiesBuilder builder(RemoteConfigConst::PARAMS_FILE_NAME, pBuffer, nLength); - builder.Add(RemoteConfigConst::PARAMS_DISABLE, isMaskSet(RemoteConfigParamsMask::DISABLE)); - builder.Add(RemoteConfigConst::PARAMS_DISABLE_WRITE, isMaskSet(RemoteConfigParamsMask::DISABLE_WRITE)); - builder.Add(RemoteConfigConst::PARAMS_ENABLE_REBOOT, isMaskSet(RemoteConfigParamsMask::ENABLE_REBOOT)); - builder.Add(RemoteConfigConst::PARAMS_ENABLE_UPTIME, isMaskSet(RemoteConfigParamsMask::ENABLE_UPTIME)); - builder.Add(RemoteConfigConst::PARAMS_ENABLE_FACTORY, isMaskSet(RemoteConfigParamsMask::ENABLE_FACTORY)); + // Loop through parameters and masks for building properties + for (const auto& paramMask : paramMasks) { + builder.Add(paramMask.pParam, isMaskSet(paramMask.nMask)); + } - builder.Add(RemoteConfigConst::PARAMS_DISPLAY_NAME, m_tRemoteConfigParams.aDisplayName, isMaskSet(RemoteConfigParamsMask::DISPLAY_NAME)); + builder.Add(RemoteConfigConst::PARAMS_DISPLAY_NAME, m_Params.aDisplayName, isMaskSet(remoteconfigparams::Mask::DISPLAY_NAME)); nSize = builder.GetSize(); @@ -160,17 +168,17 @@ void RemoteConfigParams::Builder(const struct TRemoteConfigParams *pRemoteConfig return; } -void RemoteConfigParams::Set(RemoteConfig* pRemoteConfig) { +void RemoteConfigParams::Set(RemoteConfig *pRemoteConfig) { assert(pRemoteConfig != nullptr); - pRemoteConfig->SetDisable(isMaskSet(RemoteConfigParamsMask::DISABLE)); - pRemoteConfig->SetDisableWrite(isMaskSet(RemoteConfigParamsMask::DISABLE_WRITE)); - pRemoteConfig->SetEnableReboot(isMaskSet(RemoteConfigParamsMask::ENABLE_REBOOT)); - pRemoteConfig->SetEnableUptime(isMaskSet(RemoteConfigParamsMask::ENABLE_UPTIME)); - pRemoteConfig->SetEnableFactory(isMaskSet(RemoteConfigParamsMask::ENABLE_FACTORY)); + pRemoteConfig->SetDisable(isMaskSet(remoteconfigparams::Mask::DISABLE)); + pRemoteConfig->SetDisableWrite(isMaskSet(remoteconfigparams::Mask::DISABLE_WRITE)); + pRemoteConfig->SetEnableReboot(isMaskSet(remoteconfigparams::Mask::ENABLE_REBOOT)); + pRemoteConfig->SetEnableUptime(isMaskSet(remoteconfigparams::Mask::ENABLE_UPTIME)); + pRemoteConfig->SetEnableFactory(isMaskSet(remoteconfigparams::Mask::ENABLE_FACTORY)); - if (isMaskSet(RemoteConfigParamsMask::DISPLAY_NAME)) { - pRemoteConfig->SetDisplayName(m_tRemoteConfigParams.aDisplayName); + if (isMaskSet(remoteconfigparams::Mask::DISPLAY_NAME)) { + pRemoteConfig->SetDisplayName(m_Params.aDisplayName); } } @@ -180,3 +188,13 @@ void RemoteConfigParams::staticCallbackFunction(void *p, const char *s) { (static_cast(p))->callbackFunction(s); } + +void RemoteConfigParams::Dump() { + printf("%s::%s \'%s\':\n", __FILE__, __FUNCTION__, RemoteConfigConst::PARAMS_FILE_NAME); + + for (const auto& paramMask : paramMasks) { + printf(" %s=%d\n", paramMask.pParam, isMaskSet(paramMask.nMask)); + } + + printf(" %s=%s\n", RemoteConfigConst::PARAMS_DISPLAY_NAME, m_Params.aDisplayName); +} diff --git a/lib-remoteconfig/src/remoteconfigparamsdump.cpp b/lib-remoteconfig/src/remoteconfigparamsdump.cpp deleted file mode 100644 index c2bfee36..00000000 --- a/lib-remoteconfig/src/remoteconfigparamsdump.cpp +++ /dev/null @@ -1,66 +0,0 @@ -/** - * @file remoteconfigparamsdump.cpp - * - */ -/* Copyright (C) 2020-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#if !defined(__clang__) // Needed for compiling on MacOS -# pragma GCC push_options -# pragma GCC optimize ("Os") -#endif - -#include - -#include "remoteconfigparams.h" -#include "remoteconfigconst.h" - -#include "debug.h" - -void RemoteConfigParams::Dump() { -#ifndef NDEBUG - printf("%s::%s \'%s\':\n", __FILE__, __FUNCTION__, RemoteConfigConst::PARAMS_FILE_NAME); - - if (isMaskSet(RemoteConfigParamsMask::DISABLE)) { - printf(" %s=1 [Yes]\n", RemoteConfigConst::PARAMS_DISABLE); - } - - if (isMaskSet(RemoteConfigParamsMask::DISABLE_WRITE)) { - printf(" %s=1 [Yes]\n", RemoteConfigConst::PARAMS_DISABLE_WRITE); - } - - if (isMaskSet(RemoteConfigParamsMask::ENABLE_REBOOT)) { - printf(" %s=1 [Yes]\n", RemoteConfigConst::PARAMS_ENABLE_REBOOT); - } - - if (isMaskSet(RemoteConfigParamsMask::ENABLE_UPTIME)) { - printf(" %s=1 [Yes]\n", RemoteConfigConst::PARAMS_ENABLE_UPTIME); - } - - if (isMaskSet(RemoteConfigParamsMask::ENABLE_FACTORY)) { - printf(" %s=1 [Yes]\n", RemoteConfigConst::PARAMS_ENABLE_FACTORY); - } - - if (isMaskSet(RemoteConfigParamsMask::DISPLAY_NAME)) { - printf(" %s=%s\n", RemoteConfigConst::PARAMS_DISPLAY_NAME, m_tRemoteConfigParams.aDisplayName); - } -#endif -} diff --git a/lib-remoteconfig/src/remoteconfigreboot.cpp b/lib-remoteconfig/src/remoteconfigreboot.cpp index 4df71bc5..643f72b6 100644 --- a/lib-remoteconfig/src/remoteconfigreboot.cpp +++ b/lib-remoteconfig/src/remoteconfigreboot.cpp @@ -51,10 +51,8 @@ void RemoteConfig::HandleReboot() { while (ConfigStore::Get()->Flash()) ; - Network::Get()->Shutdown(); - Display::Get()->Cls(); - Display::Get()->TextStatus("Rebooting ...", Display7SegmentMessage::INFO_REBOOTING); + Display::Get()->TextStatus("Rebooting ..."); Hardware::Get()->Reboot(); __builtin_unreachable() ; diff --git a/lib-remoteconfig/src/remoteconfigstatic.cpp b/lib-remoteconfig/src/remoteconfigstatic.cpp index 8323572d..d3356fe6 100644 --- a/lib-remoteconfig/src/remoteconfigstatic.cpp +++ b/lib-remoteconfig/src/remoteconfigstatic.cpp @@ -2,7 +2,7 @@ * @file remoteconfigstatic.cpp * */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -38,71 +38,75 @@ using namespace remoteconfig; #if !defined (CONFIG_REMOTECONFIG_MINIMUM) -const RemoteConfig::Txt RemoteConfig::s_TXT[] = { - { &RemoteConfig::HandleGetRconfigTxt, &RemoteConfig::HandleSetRconfig, "rconfig.txt", 11, Store::RCONFIG }, - { &RemoteConfig::HandleGetNetworkTxt, &RemoteConfig::HandleSetNetworkTxt, "network.txt", 11, Store::NETWORK }, +constexpr RemoteConfig::Txt RemoteConfig::s_TXT[] = { + { &RemoteConfig::HandleGetRconfigTxt, &RemoteConfig::HandleSetRconfigTxt, "rconfig.txt", 11}, + { &RemoteConfig::HandleGetEnvTxt, &RemoteConfig::HandleSetEnvTxt, "env.txt", 7 }, + { &RemoteConfig::HandleGetNetworkTxt, &RemoteConfig::HandleSetNetworkTxt, "network.txt", 11}, #if defined (DISPLAY_UDF) - { &RemoteConfig::HandleGetDisplayTxt, &RemoteConfig::HandleSetDisplayTxt, "display.txt", 11, Store::DISPLAYUDF }, + { &RemoteConfig::HandleGetDisplayTxt, &RemoteConfig::HandleSetDisplayTxt, "display.txt", 11}, #endif #if defined (NODE_ARTNET) - { &RemoteConfig::HandleGetArtnetTxt, &RemoteConfig::HandleSetArtnetTxt, "artnet.txt", 10, Store::NODE }, + { &RemoteConfig::HandleGetArtnetTxt, &RemoteConfig::HandleSetArtnetTxt, "artnet.txt", 10}, #endif #if defined (NODE_E131) - { &RemoteConfig::HandleGetE131Txt, &RemoteConfig::HandleSetE131Txt, "e131.txt", 8, Store::NODE }, + { &RemoteConfig::HandleGetE131Txt, &RemoteConfig::HandleSetE131Txt, "e131.txt", 8 }, #endif #if defined (NODE_LTC_SMPTE) - { &RemoteConfig::HandleGetLtcTxt, &RemoteConfig::HandleSetLtcTxt, "ltc.txt", 7, Store::LTC }, - { &RemoteConfig::HandleGetLdisplayTxt, &RemoteConfig::HandleSetLdisplayTxt, "ldisplay.txt", 12, Store::LTCDISPLAY }, - { &RemoteConfig::HandleGetTCNetTxt, &RemoteConfig::HandleSetTCNetTxt, "tcnet.txt", 9, Store::TCNET }, - { &RemoteConfig::HandleGetGpsTxt, &RemoteConfig::HandleSetGpsTxt, "gps.txt", 7, Store::GPS }, - { &RemoteConfig::HandleGetLtcEtcTxt, &RemoteConfig::HandleSetLtcEtcTxt, "etc.txt", 7, Store::LTCETC }, + { &RemoteConfig::HandleGetLtcTxt, &RemoteConfig::HandleSetLtcTxt, "ltc.txt", 7 }, + { &RemoteConfig::HandleGetLdisplayTxt, &RemoteConfig::HandleSetLdisplayTxt, "ldisplay.txt", 12}, + { &RemoteConfig::HandleGetTCNetTxt, &RemoteConfig::HandleSetTCNetTxt, "tcnet.txt", 9 }, + { &RemoteConfig::HandleGetGpsTxt, &RemoteConfig::HandleSetGpsTxt, "gps.txt", 7 }, + { &RemoteConfig::HandleGetLtcEtcTxt, &RemoteConfig::HandleSetLtcEtcTxt, "etc.txt", 7 }, #endif #if defined (NODE_OSC_SERVER) - { &RemoteConfig::HandleGetOscTxt, &RemoteConfig::HandleSetOscTxt, "osc.txt", 7, Store::OSC }, + { &RemoteConfig::HandleGetOscTxt, &RemoteConfig::HandleSetOscTxt, "osc.txt", 7 }, #endif #if defined (NODE_OSC_CLIENT) - { &RemoteConfig::HandleGetOscClntTxt, &RemoteConfig::HandleSetOscClientTxt, "oscclnt.txt", 11, Store::OSC_CLIENT }, + { &RemoteConfig::HandleGetOscClntTxt, &RemoteConfig::HandleSetOscClientTxt, "oscclnt.txt", 11}, #endif #if defined (NODE_SHOWFILE) - { &RemoteConfig::HandleGetShowTxt, &RemoteConfig::HandleSetShowTxt, "show.txt", 8, Store::SHOW }, + { &RemoteConfig::HandleGetShowTxt, &RemoteConfig::HandleSetShowTxt, "show.txt", 8 }, #endif #if defined (NODE_NODE) - { &RemoteConfig::HandleGetNodeNodeTxt, &RemoteConfig::HandleSetNodeNodeTxt, "node.txt", 8, Store::NODE }, - { &RemoteConfig::HandleGetNodeArtNetTxt, &RemoteConfig::HandleSetNodeArtNetTxt, "artnet.txt", 10, Store::NODE }, - { &RemoteConfig::HandleGetNodeE131Txt, &RemoteConfig::HandleSetNodeE131Txt, "e131.txt", 8, Store::NODE }, + { &RemoteConfig::HandleGetNodeNodeTxt, &RemoteConfig::HandleSetNodeNodeTxt, "node.txt", 8 }, + { &RemoteConfig::HandleGetNodeArtNetTxt, &RemoteConfig::HandleSetNodeArtNetTxt, "artnet.txt", 10}, + { &RemoteConfig::HandleGetNodeE131Txt, &RemoteConfig::HandleSetNodeE131Txt, "e131.txt", 8 }, #endif #if defined (RDM_RESPONDER) - { &RemoteConfig::HandleGetRdmDeviceTxt, &RemoteConfig::HandleSetRdmDeviceTxt, "rdm_device.txt", 14, Store::RDMDEVICE }, - { &RemoteConfig::HandleGetRdmSensorsTxt, &RemoteConfig::HandleSetRdmSensorsTxt, "sensors.txt", 11, Store::RDMSENSORS }, -# if defined (ENABLE_RDM_SUBDEVICES) - { &RemoteConfig::HandleGetRdmSubdevTxt, &RemoteConfig::HandleSetRdmSubdevTxt, "subdev.txt", 10, Store::RDMSUBDEVICES }, + { &RemoteConfig::HandleGetRdmDeviceTxt, &RemoteConfig::HandleSetRdmDeviceTxt, "rdm_device.txt", 14}, + { &RemoteConfig::HandleGetRdmSensorsTxt, &RemoteConfig::HandleSetRdmSensorsTxt, "sensors.txt", 11}, +# if defined (CONFIG_RDM_ENABLE_SUBDEVICES) + { &RemoteConfig::HandleGetRdmSubdevTxt, &RemoteConfig::HandleSetRdmSubdevTxt, "subdev.txt", 10}, # endif #endif #if defined (OUTPUT_DMX_SEND) - { &RemoteConfig::HandleGetParamsTxt, &RemoteConfig::HandleSetParamsTxt, "params.txt", 10, Store::DMXSEND }, + { &RemoteConfig::HandleGetParamsTxt, &RemoteConfig::HandleSetParamsTxt, "params.txt", 10}, #endif #if defined (OUTPUT_DMX_PIXEL) || defined(OUTPUT_DMX_TLC59711) - { &RemoteConfig::HandleGetDevicesTxt, &RemoteConfig::HandleSetDevicesTxt, "devices.txt", 11, Store::WS28XXDMX }, + { &RemoteConfig::HandleGetDevicesTxt, &RemoteConfig::HandleSetDevicesTxt, "devices.txt", 11}, #endif #if defined (OUTPUT_DMX_MONITOR) - { &RemoteConfig::HandleGetMonTxt, &RemoteConfig::HandleSetMonTxt, "mon.txt", 7, Store::MONITOR }, + { &RemoteConfig::HandleGetMonTxt, &RemoteConfig::HandleSetMonTxt, "mon.txt", 7 }, #endif #if defined (OUTPUT_DMX_SERIAL) - { &RemoteConfig::HandleGetSerialTxt, &RemoteConfig::HandleSetSerialTxt, "serial.txt", 10, Store::SERIAL }, + { &RemoteConfig::HandleGetSerialTxt, &RemoteConfig::HandleSetSerialTxt, "serial.txt", 10}, #endif #if defined (OUTPUT_RGB_PANEL) - { &RemoteConfig::HandleGetRgbPanelTxt, &RemoteConfig::HandleSetRgbPanelTxt, "rgbpanel.txt", 12, Store::RGBPANEL }, + { &RemoteConfig::HandleGetRgbPanelTxt, &RemoteConfig::HandleSetRgbPanelTxt, "rgbpanel.txt", 12}, +#endif +#if defined (OUTPUT_DMX_PCA9685) + { &RemoteConfig::HandleGetPca9685Txt, &RemoteConfig::HandleSetPca9685Txt, "pca9685.txt", 11}, #endif #if defined(OUTPUT_DMX_STEPPER) - { &RemoteConfig::HandleGetSparkFunTxt, &RemoteConfig::HandleSetSparkFunTxt, "sparkfun.txt", 12, Store::SPARKFUN }, - { &RemoteConfig::HandleGetMotor0Txt, &RemoteConfig::HandleSetMotor0Txt, "motor0.txt", 10, Store::MOTORS }, - { &RemoteConfig::HandleGetMotor1Txt, &RemoteConfig::HandleSetMotor1Txt, "motor1.txt", 10, Store::MOTORS }, - { &RemoteConfig::HandleGetMotor2Txt, &RemoteConfig::HandleSetMotor2Txt, "motor2.txt", 10, Store::MOTORS }, - { &RemoteConfig::HandleGetMotor3Txt, &RemoteConfig::HandleSetMotor3Txt, "motor3.txt", 10, Store::MOTORS }, - { &RemoteConfig::HandleGetMotor4Txt, &RemoteConfig::HandleSetMotor4Txt, "motor4.txt", 10, Store::MOTORS }, - { &RemoteConfig::HandleGetMotor5Txt, &RemoteConfig::HandleSetMotor5Txt, "motor5.txt", 10, Store::MOTORS }, - { &RemoteConfig::HandleGetMotor6Txt, &RemoteConfig::HandleSetMotor6Txt, "motor6.txt", 10, Store::MOTORS }, - { &RemoteConfig::HandleGetMotor7Txt, &RemoteConfig::HandleSetMotor7Txt, "motor7.txt", 10, Store::MOTORS } + { &RemoteConfig::HandleGetSparkFunTxt, &RemoteConfig::HandleSetSparkFunTxt, "sparkfun.txt", 12}, + { &RemoteConfig::HandleGetMotor0Txt, &RemoteConfig::HandleSetMotor0Txt, "motor0.txt", 10}, + { &RemoteConfig::HandleGetMotor1Txt, &RemoteConfig::HandleSetMotor1Txt, "motor1.txt", 10}, + { &RemoteConfig::HandleGetMotor2Txt, &RemoteConfig::HandleSetMotor2Txt, "motor2.txt", 10}, + { &RemoteConfig::HandleGetMotor3Txt, &RemoteConfig::HandleSetMotor3Txt, "motor3.txt", 10}, + { &RemoteConfig::HandleGetMotor4Txt, &RemoteConfig::HandleSetMotor4Txt, "motor4.txt", 10}, + { &RemoteConfig::HandleGetMotor5Txt, &RemoteConfig::HandleSetMotor5Txt, "motor5.txt", 10}, + { &RemoteConfig::HandleGetMotor6Txt, &RemoteConfig::HandleSetMotor6Txt, "motor6.txt", 10}, + { &RemoteConfig::HandleGetMotor7Txt, &RemoteConfig::HandleSetMotor7Txt, "motor7.txt", 10} #endif }; diff --git a/lib-remoteconfig/src/shell/shell.cpp b/lib-remoteconfig/src/shell/shell.cpp old mode 100644 new mode 100755 index 238e7adb..845b27ed --- a/lib-remoteconfig/src/shell/shell.cpp +++ b/lib-remoteconfig/src/shell/shell.cpp @@ -3,7 +3,7 @@ * */ /* Copyright (C) 2020 by hippy mailto:dmxout@gmail.com - * Copyright (C) 2020-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl + * Copyright (C) 2020-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -31,30 +31,43 @@ #include "shell/shell.h" +#if defined (GD32) // PHY_TYPE is defined here +# include "gd32.h" +#endif + #include "debug.h" -struct TCommands { +struct ShellCommands { const char *pName; const uint32_t nArgc; }; -static constexpr TCommands cmd_table[] = { +static constexpr ShellCommands cmd_table[] = { { "reboot", 0 }, { "info", 0 }, - { "set", 2}, - { "get", 2}, - { "dhcp", 0}, - { "date", 0}, - { "hwclock", 1}, -#ifndef NDEBUG - { "i2cdetect" , 0}, - { "dump" , 1}, - { "mem" , 2}, - { "ntp" , 1}, - { "gps" , 1}, + { "set", 2 }, + { "get", 2 }, + { "dhcp", 0 }, + { "date", 0 }, + { "phy", 0 }, +#if !defined (DISABLE_RTC) + { "hwclock", 1 }, #endif - { "?", 0 } -}; +#if defined (DEBUG_I2C) + { "i2cdetect", 0 }, +#endif + { "dump", 1 }, + { "mem", 2 }, +#if defined (ENABLE_NTP_CLIENT) + { "ntp", 1 }, +#endif +#if defined (CONFIG_SHELL_GPS) + { "gps", 1 }, +#endif +#if (PHY_TYPE == RTL8201F) + { "rtl8201f" , 2}, +#endif + { "?", 0 } }; namespace shell { static constexpr auto TABLE_SIZE = sizeof(cmd_table) / sizeof(cmd_table[0]); @@ -65,10 +78,8 @@ static constexpr char CMD_WRONG_ARGUMENTS[] = "Wrong arguments\n"; } // namespace msg } // namespace shell -using namespace shell; - Shell::Shell() { - DEBUG_PRINTF("TABLE_SIZE=%d", TABLE_SIZE); + DEBUG_PRINTF("TABLE_SIZE=%d", shell::TABLE_SIZE); } int Shell::Printf(const char* fmt, ...) { @@ -86,8 +97,8 @@ int Shell::Printf(const char* fmt, ...) { return i; } -uint16_t Shell::ValidateCmd(uint32_t nLength, CmdIndex &nCmdIndex) { - uint16_t i; +uint32_t Shell::ValidateCmd(const uint32_t nLength, shell::CmdIndex &nCmdIndex) { + uint32_t i; m_Argc = 0; @@ -98,17 +109,17 @@ uint16_t Shell::ValidateCmd(uint32_t nLength, CmdIndex &nCmdIndex) { } } - for (uint32_t j = 0; j < TABLE_SIZE; j++) { + for (uint32_t j = 0; j < shell::TABLE_SIZE; j++) { if (0 == strcmp(m_Buffer, cmd_table[j].pName)) { - nCmdIndex = static_cast(j); - return static_cast(i + 1); + nCmdIndex = static_cast< shell::CmdIndex>(j); + return i + 1; } } return 0; } -void Shell::ValidateArg(uint16_t nOffset, uint32_t nLength) { +void Shell::ValidateArg(uint32_t nOffset, const uint32_t nLength) { if (nOffset > nLength) { return; } @@ -121,11 +132,11 @@ void Shell::ValidateArg(uint16_t nOffset, uint32_t nLength) { return; } - uint16_t nArgvStart = nOffset; + auto nArgvStart = nOffset; m_Argv[0] = &m_Buffer[nOffset++]; m_Argc = 1; - uint16_t i, j = 1; + uint32_t i, j = 1; for (i = nOffset; i < nLength; i++) { if ((m_Buffer[i] > ' ') && (m_Buffer[i] < 127)) { @@ -133,13 +144,13 @@ void Shell::ValidateArg(uint16_t nOffset, uint32_t nLength) { } if ((m_Buffer[i] == ' ') || (m_Buffer[i] == '\t')) { - if (j < MAXARG) { + if (j < shell::MAXARG) { m_nArgvLength[j - 1] = static_cast(i - nArgvStart); } while (i < nLength && ((m_Buffer[i] == ' ') || (m_Buffer[i] == '\t'))) { m_Buffer[i++] = '\0'; } - if (j < MAXARG) { + if (j < shell::MAXARG) { nArgvStart = i; m_Argv[j++] = &m_Buffer[i]; } @@ -147,7 +158,7 @@ void Shell::ValidateArg(uint16_t nOffset, uint32_t nLength) { } } - if (j < MAXARG) { + if (j < shell::MAXARG) { m_nArgvLength[j - 1] = static_cast(i - nArgvStart); } @@ -161,11 +172,18 @@ void Shell::ValidateArg(uint16_t nOffset, uint32_t nLength) { void Shell::CmdHelp() { Puts("http://www.orangepi-dmx.org/orange-pi-dmx512-rdm/uart0-shell\n"); + + uint32_t i = 0; + for (auto& cmd : cmd_table) { + Printf("%2u: %s <%u>\n", i++, cmd.pName, cmd.nArgc); + } + + Puts(""); } void Shell::Run() { if (__builtin_expect((!m_bShownPrompt), 1)) { - Puts(msg::CMD_PROMPT); + Puts(shell::msg::CMD_PROMPT); m_bShownPrompt = true; } @@ -179,64 +197,78 @@ void Shell::Run() { m_bShownPrompt = false; // next time round, we show the prompt. - uint16_t nOffset; - CmdIndex nCmdIndex; + uint32_t nOffset; + shell::CmdIndex nCmdIndex; if ((nOffset = ValidateCmd(nLength, nCmdIndex)) == 0) { - Printf("%s %s\n", msg::CMD_NOT_FOUND, m_Buffer); + Printf("%s %s\n", shell::msg::CMD_NOT_FOUND, m_Buffer); return; } ValidateArg(nOffset, nLength); if (m_Argc != cmd_table[static_cast(nCmdIndex)].nArgc) { - Puts(msg::CMD_WRONG_ARGUMENTS); + Puts( shell::msg::CMD_WRONG_ARGUMENTS); return; } switch (nCmdIndex) { - case CmdIndex::REBOOT: - CmdReboot(); - break; - case CmdIndex::INFO: - CmdInfo(); - break; - case CmdIndex::SET: - CmdSet(); - break; - case CmdIndex::GET: - CmdGet(); - break; - case CmdIndex::DHCP: - CmdDhcp(); - break; - case CmdIndex::DATE: - CmdDate(); - break; - case CmdIndex::HWCLOCK: - CmdHwClock(); - break; -#ifndef NDEBUG - case CmdIndex::I2CDETECT: - CmdI2cDetect(); - break; - case CmdIndex::DUMP: - CmdDump(); - break; - case CmdIndex::MEM: - CmdMem(); - break; - case CmdIndex::NTP: - CmdNtp(); - break; - case CmdIndex::GPS: - CmdGps(); - break; + case shell::CmdIndex::REBOOT: + CmdReboot(); + break; + case shell::CmdIndex::INFO: + CmdInfo(); + break; + case shell::CmdIndex::SET: + CmdSet(); + break; + case shell::CmdIndex::GET: + CmdGet(); + break; + case shell::CmdIndex::DHCP: + CmdDhcp(); + break; + case shell::CmdIndex::DATE: + CmdDate(); + break; + case shell::CmdIndex::PHY: + CmdPhy(); + break; +#if !defined(DISABLE_RTC) + case shell::CmdIndex::HWCLOCK: + CmdHwClock(); + break; #endif - case CmdIndex::HELP: - CmdHelp(); - break; - default: - break; +#if defined (DEBUG_I2C) + case shell::CmdIndex::I2CDETECT: + CmdI2cDetect(); + break; +#endif + case shell::CmdIndex::DUMP: + CmdDump(); + break; + case shell::CmdIndex::MEM: + CmdMem(); + break; +#if defined (ENABLE_NTP_CLIENT) + case shell::CmdIndex::NTP: + CmdNtp(); + break; +#endif +#if defined (CONFIG_SHELL_GPS) + case shell::CmdIndex::GPS: + CmdGps(); + break; +#endif +#if (PHY_TYPE == RTL8201F) + case shell::CmdIndex::PHY_TYPE_RTL8201F: + CmdPhyTypeRTL8201F(); + break; +#endif + case shell::CmdIndex::HELP: + CmdHelp(); + break; + default: + break; } } diff --git a/lib-remoteconfig/src/shell/shellcmd.cpp b/lib-remoteconfig/src/shell/shellcmd.cpp old mode 100644 new mode 100755 index 723353a3..f82b55cd --- a/lib-remoteconfig/src/shell/shellcmd.cpp +++ b/lib-remoteconfig/src/shell/shellcmd.cpp @@ -3,7 +3,7 @@ * */ /* Copyright (C) 2020 by hippy mailto:dmxout@gmail.com - * Copyright (C) 2020-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl + * Copyright (C) 2020-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -35,6 +35,7 @@ #include "remoteconfig.h" #include "network.h" +#include "emac/phy.h" #include "hardware.h" #include "firmwareversion.h" @@ -49,87 +50,118 @@ #endif // Firmware specific BEGIN -#include "debug.h" +#if defined (DEBUG_I2C) +# include "../lib-hal/debug/i2c/i2cdetect.h" +#endif -#ifndef NDEBUG -# include "../debug/i2cdetect.h" -# include "ntpclient.h" +#if defined (ENABLE_NTP_CLIENT) +# include "net/apps/ntpclient.h" +#endif + +#if defined (CONFIG_SHELL_GPS) # include "gps.h" -extern "C" { -void h3_board_dump(void); -void h3_dump_memory_mapping(void); -void h3_ccu_pll_dump(void); -void arm_dump_memmap(void); -void arm_dump_page_table(void); -} #endif -// TODO We can reshuffle namespaces here for removing duplicates? +#if (PHY_TYPE == RTL8201F) +# include "emac/phy/rtl8201f.h" +#endif + +#if defined (GD32) // PHY_TYPE is defined here +# include "gd32.h" +#endif + +#include "debug.h" namespace shell { +// Centralize common arguments and lengths +namespace common_args { +static constexpr char PRINT[] = "print"; +} // namespace common_args + +namespace common_lengths { +static constexpr auto PRINT = sizeof(common_args::PRINT) - 1; +} // namespace common_lengths namespace set { namespace arg { static constexpr char IP[] = "ip"; static constexpr char HOSTNAME[] = "hostname"; +#if defined (LTC_READER) static constexpr char LTC[] = "ltc"; +#endif } // namespace arg namespace length { static constexpr auto IP = sizeof(arg::IP) - 1; static constexpr auto HOSTNAME = sizeof(arg::HOSTNAME) - 1; +#if defined (LTC_READER) static constexpr auto LTC = sizeof(arg::LTC) - 1; +#endif } // namespace length } // namespace set -namespace dump { -namespace arg { -static constexpr char BOARD[] = "board"; -static constexpr char MMAP[] = "mmap"; -static constexpr char PLL[] = "pll"; -static constexpr char LINKER[] = "linker"; -} // namespace arg -namespace length { -static constexpr auto BOARD = sizeof(arg::BOARD) - 1; -static constexpr auto MMAP = sizeof(arg::MMAP) - 1; -static constexpr auto PLL = sizeof(arg::PLL) - 1; -static constexpr auto LINKER = sizeof(arg::LINKER) - 1; -} // namespace length -} // namespace dump - namespace networktime { namespace arg { -static constexpr char PRINT[] = "print"; +// Reuse common_args::PRINT +using common_args::PRINT; } // namespace arg namespace length { -static constexpr auto PRINT = sizeof(arg::PRINT) - 1; +// Reuse common_lengths::PRINT +using common_lengths::PRINT; } // namespace length } // namespace networktime +#if !defined(DISABLE_RTC) namespace hwclock { namespace arg { -static constexpr char HCTOSYS[] = "hctosys"; // Set the System Clock from the Hardware Clock -static constexpr char SYSTOHC[] = "systohc"; // Set the Hardware Clock from the System Clock -static constexpr char PRINT[] = "print"; +static constexpr char HCTOSYS[] = "hctosys"; // Set the System Clock from the Hardware Clock +static constexpr char SYSTOHC[] = "systohc"; // Set the Hardware Clock from the System Clock +// Reuse common_args::PRINT +using common_args::PRINT; } // namespace arg namespace length { static constexpr auto HCTOSYS = sizeof(arg::HCTOSYS) - 1; static constexpr auto SYSTOHC = sizeof(arg::SYSTOHC) - 1; -static constexpr auto PRINT = sizeof(arg::PRINT) - 1; +// Reuse common_lengths::PRINT +using common_lengths::PRINT; } // namespace length } // namespace hwclock +#endif +#if defined (CONFIG_SHELL_GPS) namespace gps { namespace arg { static constexpr char DATE[] = "date"; static constexpr char LOCALTIME[] = "localtime"; -static constexpr char PRINT[] = "print"; +// Reuse common_args::PRINT +using common_args::PRINT; } // namespace arg namespace length { static constexpr auto DATE = sizeof(arg::DATE) - 1; static constexpr auto LOCALTIME = sizeof(arg::LOCALTIME) - 1; -static constexpr auto PRINT = sizeof(arg::PRINT) - 1; +// Reuse common_lengths::PRINT +using common_lengths::PRINT; } // namespace length } // namespace gps +#endif + +#if (PHY_TYPE == RTL8201F) +namespace rtl8201f { +namespace arg { +static constexpr char RXTIMING[] = "rxtiming"; +static constexpr char TXTIMING[] = "txtiming"; +static constexpr char TIMING[] = "timing"; +// Reuse common_args::PRINT +using common_args::PRINT; +} // namespace arg +namespace length { +static constexpr auto RXTIMING = sizeof(arg::RXTIMING) - 1; +static constexpr auto TXTIMING = sizeof(arg::TXTIMING) - 1; +static constexpr auto TIMING = sizeof(arg::TIMING) - 1; +// Reuse common_lengths::PRINT +using common_lengths::PRINT; +} // namespace length +} // namespace rtl8201f +#endif namespace file { static constexpr char EXT[] = ".txt"; @@ -148,38 +180,17 @@ static constexpr char DHCP[] = "DHCP enabled\n"; static constexpr char STORED[] = "Stored\n"; } // namespace info namespace error { -static constexpr char INVALID[] = "Invalid command.\n"; -static constexpr char INTERNAL[] = "Internal error.\n"; -static constexpr char DHCP[] = "DHCP failed.\n"; static constexpr char TXT[] = ".txt not found\n"; static constexpr char PROPERTY[] = "Property not found.\n"; +#if defined (LTC_READER) static constexpr char LTC[] = "This source does not support the set command.\n"; +#endif } // namespace error } // namespace msg - } // namespace shell using namespace shell; -uint32_t Shell::hexadecimalToDecimal(const char *pHexValue, uint32_t nLength) { - const auto *pSrc = pHexValue; - uint32_t nValue = 0; - - while (nLength-- > 0) { - const auto c = *pSrc; - - if (isxdigit(c) == 0) { - break; - } - - const auto nNibble = c > '9' ? static_cast((c | 0x20) - 'a' + 10) : static_cast(c - '0'); - nValue = (nValue << 4) | nNibble; - pSrc++; - } - - return nValue; -} - void Shell::CmdReboot() { RemoteConfig::Get()->Reboot(); } @@ -336,11 +347,8 @@ void Shell::CmdGet() { } void Shell::CmdDhcp() { - if (Network::Get()->EnableDhcp()) { - Puts(msg::info::DHCP); - } else { - Puts(msg::error::DHCP); - } + Network::Get()->EnableDhcp(); + Puts(msg::info::DHCP); } void Shell::CmdDate() { @@ -350,69 +358,76 @@ void Shell::CmdDate() { Puts(asctime(localtime(&rawtime))); } -void Shell::CmdHwClock() { - const auto nArgv0Length = m_nArgvLength[0]; +void Shell::CmdPhy() { + net::PhyStatus phyStatus; + phy_customized_status(phyStatus); - if ((nArgv0Length == hwclock::length::HCTOSYS) && (memcmp(m_Argv[0], hwclock::arg::HCTOSYS, hwclock::length::HCTOSYS) == 0)) { - HwClock::Get()->HcToSys(); - return; - } + Printf("Link %s, %d, %s\n", + phyStatus.link == net::Link::STATE_UP ? "Up" : "Down", + phyStatus.speed == net::Speed::SPEED10 ? 10 : 100, + phyStatus.duplex == net::Duplex::DUPLEX_HALF ? "HALF" : "FULL"); +} - if ((nArgv0Length == hwclock::length::SYSTOHC) && (memcmp(m_Argv[0], hwclock::arg::SYSTOHC, hwclock::length::SYSTOHC) == 0)) { - HwClock::Get()->SysToHc(); - return; - } +#ifndef NDEBUG +static uint32_t hexadecimal_to_decimal(const char *pHexValue, uint32_t nLength) { + const auto *pSrc = pHexValue; + uint32_t nValue = 0; - if ((nArgv0Length == hwclock::length::PRINT) && (memcmp(m_Argv[0], hwclock::arg::PRINT, hwclock::length::PRINT) == 0)) { - HwClock::Get()->Print(); - return; + while (nLength-- > 0) { + const auto c = *pSrc; + + if (isxdigit(c) == 0) { + break; + } + + const auto nNibble = c > '9' ? static_cast((c | 0x20) - 'a' + 10) : static_cast(c - '0'); + nValue = (nValue << 4) | nNibble; + pSrc++; } - Puts(msg::error::INVALID); + return nValue; } +#endif -/* - * Debug commands - */ - +void Shell::CmdMem() { #ifndef NDEBUG -void Shell::CmdI2cDetect() { - I2cDetect i2cdetect; + const auto pAddress = reinterpret_cast(hexadecimal_to_decimal(m_Argv[0], m_nArgvLength[0])); + const auto nSize = hexadecimal_to_decimal(m_Argv[1], m_nArgvLength[1]); + + debug_dump(pAddress, nSize); +#endif } -void Shell::CmdDump() { +#if !defined(DISABLE_RTC) +void Shell::CmdHwClock() { const auto nArgv0Length = m_nArgvLength[0]; - if ((nArgv0Length == dump::length::BOARD) && (memcmp(m_Argv[0], dump::arg::BOARD, dump::length::BOARD) == 0)) { - h3_board_dump(); - return; - } - - if ((nArgv0Length == dump::length::MMAP) && (memcmp(m_Argv[0], dump::arg::MMAP, dump::length::MMAP) == 0)) { - h3_dump_memory_mapping(); + if ((nArgv0Length == hwclock::length::HCTOSYS) && (memcmp(m_Argv[0], hwclock::arg::HCTOSYS, hwclock::length::HCTOSYS) == 0)) { + HwClock::Get()->HcToSys(); return; } - if ((nArgv0Length == dump::length::PLL) && (memcmp(m_Argv[0], dump::arg::PLL, dump::length::PLL) == 0)) { - h3_ccu_pll_dump(); + if ((nArgv0Length == hwclock::length::SYSTOHC) && (memcmp(m_Argv[0], hwclock::arg::SYSTOHC, hwclock::length::SYSTOHC) == 0)) { + HwClock::Get()->SysToHc(); return; } - if ((nArgv0Length == dump::length::LINKER) && (memcmp(m_Argv[0], dump::arg::LINKER, dump::length::LINKER) == 0)) { - arm_dump_memmap(); + if ((nArgv0Length == hwclock::length::PRINT) && (memcmp(m_Argv[0], hwclock::arg::PRINT, hwclock::length::PRINT) == 0)) { + HwClock::Get()->Print(); return; } Puts(msg::error::INVALID); } +#endif -void Shell::CmdMem() { - const auto pAddress = reinterpret_cast(hexadecimalToDecimal(m_Argv[0], m_nArgvLength[0])); - const auto nSize = hexadecimalToDecimal(m_Argv[1], m_nArgvLength[1]); - - debug_dump(pAddress, static_cast(nSize)); +#if defined (DEBUG_I2C) +void Shell::CmdI2cDetect() { + I2cDetect i2cdetect; } +#endif +#if defined (ENABLE_NTP_CLIENT) void Shell::CmdNtp() { const auto nArgv0Length = m_nArgvLength[0]; @@ -423,7 +438,9 @@ void Shell::CmdNtp() { Puts(msg::error::INVALID); } +#endif +#if defined (CONFIG_SHELL_GPS) void Shell::CmdGps() { const auto nArgv0Length = m_nArgvLength[0]; @@ -447,3 +464,43 @@ void Shell::CmdGps() { Puts(msg::error::INVALID); } #endif + +#if (PHY_TYPE == RTL8201F) +void Shell::CmdPhyTypeRTL8201F() { + const auto nArgv0Length = m_nArgvLength[0]; + + if ((nArgv0Length == rtl8201f::length::RXTIMING) && (memcmp(m_Argv[0], rtl8201f::arg::RXTIMING, rtl8201f::length::RXTIMING) == 0)) { + if (m_nArgvLength[1] == 1) { + const auto c = m_Argv[1][0]; + if (isxdigit(c) != 0) { + const uint32_t nRxTiming = c > '9' ? ((c | 0x20) - 'a' + 10) : (c - '0'); + net::phy::rtl8201f_set_rxtiming(nRxTiming); + return; + } + } + } + + if ((nArgv0Length == rtl8201f::length::TXTIMING) && (memcmp(m_Argv[0], rtl8201f::arg::TXTIMING, rtl8201f::length::TXTIMING) == 0)) { + if (m_nArgvLength[1] == 1) { + const auto c = m_Argv[1][0]; + if (isxdigit(c) != 0) { + const uint32_t nTxTiming = c > '9' ? ((c | 0x20) - 'a' + 10) : (c - '0'); + net::phy::rtl8201f_set_txtiming(nTxTiming); + return; + } + } + } + + if ((nArgv0Length == rtl8201f::length::PRINT) && (memcmp(m_Argv[0], rtl8201f::arg::PRINT, rtl8201f::length::PRINT) == 0)) { + if ((m_nArgvLength[1] == rtl8201f::length::TIMING) && (memcmp(m_Argv[1], rtl8201f::arg::TIMING, rtl8201f::length::TIMING) == 0)) { + uint32_t nRxTiming; + uint32_t nTxTiming; + net::phy::rtl8201f_get_timings(nRxTiming, nTxTiming); + Printf("RX: 0x%X, TX: 0x%X\n", nRxTiming, nTxTiming); + return; + } + } + + Puts(msg::error::INVALID); +} +#endif diff --git a/lib-remoteconfig/src/tftp/remoteconfig.cpp b/lib-remoteconfig/src/tftp/remoteconfig.cpp index 57c3a0ec..eee8894f 100644 --- a/lib-remoteconfig/src/tftp/remoteconfig.cpp +++ b/lib-remoteconfig/src/tftp/remoteconfig.cpp @@ -52,7 +52,7 @@ void RemoteConfig::PlatformHandleTftpSet() { if (m_bEnableTFTP && (m_pTFTPFileServer == nullptr)) { m_pTFTPFileServer = new TFTPFileServer(s_TFTPBuffer, FIRMWARE_MAX_SIZE); assert(m_pTFTPFileServer != nullptr); - Display::Get()->TextStatus("TFTP On", Display7SegmentMessage::INFO_TFTP_ON, CONSOLE_GREEN); + Display::Get()->TextStatus("TFTP On", CONSOLE_GREEN); } else if (!m_bEnableTFTP && (m_pTFTPFileServer != nullptr)) { const uint32_t nFileSize = m_pTFTPFileServer->GetFileSize(); DEBUG_PRINTF("nFileSize=%d, %d", nFileSize, m_pTFTPFileServer->isDone()); @@ -63,7 +63,7 @@ void RemoteConfig::PlatformHandleTftpSet() { bSucces = FlashCodeInstall::Get()->WriteFirmware(s_TFTPBuffer, nFileSize); if (!bSucces) { - Display::Get()->TextStatus("Error: TFTP", Display7SegmentMessage::ERROR_TFTP, CONSOLE_RED); + Display::Get()->TextStatus("Error: TFTP", CONSOLE_RED); } } @@ -71,7 +71,7 @@ void RemoteConfig::PlatformHandleTftpSet() { m_pTFTPFileServer = nullptr; if (bSucces) { // Keep error message - Display::Get()->TextStatus("TFTP Off", Display7SegmentMessage::INFO_TFTP_OFF, CONSOLE_GREEN); + Display::Get()->TextStatus("TFTP Off", CONSOLE_GREEN); } } diff --git a/lib-remoteconfig/src/tftp/tftpfileserver.cpp b/lib-remoteconfig/src/tftp/tftpfileserver.cpp index 75d9b540..ccc09447 100644 --- a/lib-remoteconfig/src/tftp/tftpfileserver.cpp +++ b/lib-remoteconfig/src/tftp/tftpfileserver.cpp @@ -56,7 +56,7 @@ void TFTPFileServer::Exit() { } -bool TFTPFileServer::FileOpen(__attribute__((unused)) const char* pFileName, __attribute__((unused)) tftp::Mode tMode) { +bool TFTPFileServer::FileOpen([[maybe_unused]] const char *pFileName, [[maybe_unused]] tftp::Mode tMode) { DEBUG_ENTRY DEBUG_EXIT @@ -78,7 +78,7 @@ bool TFTPFileServer::FileCreate(const char* pFileName, tftp::Mode mode) { return false; } - Display::Get()->TextStatus("TFTP Started", Display7SegmentMessage::INFO_TFTP_STARTED, CONSOLE_GREEN); + Display::Get()->TextStatus("TFTP Started", CONSOLE_GREEN); m_nFileSize = 0; @@ -91,13 +91,13 @@ bool TFTPFileServer::FileClose() { m_bDone = true; - Display::Get()->TextStatus("TFTP Ended", Display7SegmentMessage::INFO_TFTP_ENDED, CONSOLE_GREEN); + Display::Get()->TextStatus("TFTP Ended", CONSOLE_GREEN); DEBUG_EXIT return true; } -size_t TFTPFileServer::FileRead(__attribute__((unused)) void* pBuffer, __attribute__((unused)) size_t nCount, __attribute__((unused)) unsigned nBlockNumber) { +size_t TFTPFileServer::FileRead([[maybe_unused]] void* pBuffer, [[maybe_unused]] size_t nCount, [[maybe_unused]] unsigned nBlockNumber) { DEBUG_ENTRY DEBUG_EXIT diff --git a/lib-remoteconfig/src/uart/shell.cpp b/lib-remoteconfig/src/uart/shell.cpp index af803365..c14ade80 100644 --- a/lib-remoteconfig/src/uart/shell.cpp +++ b/lib-remoteconfig/src/uart/shell.cpp @@ -3,7 +3,7 @@ * */ /* Copyright (C) 2020 by hippy mailto:dmxout@gmail.com - * Copyright (C) 2020-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl + * Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-showfile/.cproject b/lib-showfile/.cproject new file mode 100755 index 00000000..a6cabe01 --- /dev/null +++ b/lib-showfile/.cproject @@ -0,0 +1,208 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/lib-debug/.project b/lib-showfile/.project old mode 100644 new mode 100755 similarity index 96% rename from lib-debug/.project rename to lib-showfile/.project index fbef8b1f..0a5805fc --- a/lib-debug/.project +++ b/lib-showfile/.project @@ -1,6 +1,6 @@ - lib-debug + lib-showfile diff --git a/lib-rdmresponder/.settings/language.settings.xml b/lib-showfile/.settings/language.settings.xml old mode 100644 new mode 100755 similarity index 87% rename from lib-rdmresponder/.settings/language.settings.xml rename to lib-showfile/.settings/language.settings.xml index 0af5aaae..46128a64 --- a/lib-rdmresponder/.settings/language.settings.xml +++ b/lib-showfile/.settings/language.settings.xml @@ -1,12 +1,12 @@ - - - - - - - - - - - + + + + + + + + + + + \ No newline at end of file diff --git a/lib-showfile/.settings/org.eclipse.cdt.codan.core.prefs b/lib-showfile/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100755 index 00000000..300bb148 --- /dev/null +++ b/lib-showfile/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,107 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.codan.checkers.errnoreturn=Warning +org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false} +org.eclipse.cdt.codan.checkers.errreturnvalue=Error +org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"} +org.eclipse.cdt.codan.checkers.localvarreturn=Warning +org.eclipse.cdt.codan.checkers.localvarreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Returning the address of a local variable\\")"} +org.eclipse.cdt.codan.checkers.nocommentinside=Error +org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"} +org.eclipse.cdt.codan.checkers.nolinecomment=Error +org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"} +org.eclipse.cdt.codan.checkers.noreturn=Error +org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false} +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"} +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous problem\\")"} +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment in condition\\")"} +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment to itself\\")"} +org.eclipse.cdt.codan.internal.checkers.BlacklistProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.BlacklistProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function or method is blacklisted\\")",blacklist\=>()} +org.eclipse.cdt.codan.internal.checkers.CStyleCastProblem=Warning +org.eclipse.cdt.codan.internal.checkers.CStyleCastProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"C-Style cast instead of C++ cast\\")",checkMacro\=>true} +org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning +org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No break at end of case\\")",no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false,enable_fallthrough_quickfix_param\=>false} +org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning +org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Catching by reference is recommended\\")",unknown\=>false,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Circular inheritance\\")"} +org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization=Warning +org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class members should be properly initialized\\")",skip\=>true} +org.eclipse.cdt.codan.internal.checkers.CopyrightProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.CopyrightProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Lack of copyright information\\")",regex\=>".*Copyright.*"} +org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem=Error +org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid 'decltype(auto)' specifier\\")"} +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Field cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.FloatCompareProblem=Warning +org.eclipse.cdt.codan.internal.checkers.FloatCompareProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Direct float comparison\\")"} +org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem=Warning +org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Goto statement used\\")"} +org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error +org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid arguments\\")"} +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"} +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"} +org.eclipse.cdt.codan.internal.checkers.MagicNumberProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MagicNumberProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Avoid magic numbers\\")",checkArray\=>true,checkOperatorParen\=>true,exceptions\=>(1,0,-1,2,1.0,0.0,-1.0)} +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Member declaration not found\\")"} +org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Method cannot be resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.MissCaseProblem=Warning +org.eclipse.cdt.codan.internal.checkers.MissCaseProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing cases in switch\\")"} +org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem=Warning +org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing default in switch\\")",defaultWithAllEnums\=>false} +org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem=Warning +org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing reference return value in assignment operator\\")"} +org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem=Warning +org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing self check in assignment operator\\")"} +org.eclipse.cdt.codan.internal.checkers.MultipleDeclarationsProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MultipleDeclarationsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Multiple variable declaration\\")"} +org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker=-Info +org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Name convention for function\\")",pattern\=>"^[a-z]",macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem=Warning +org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class has a virtual method and non-virtual destructor\\")"} +org.eclipse.cdt.codan.internal.checkers.OverloadProblem=Error +org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid overload\\")"} +org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem=Error +org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redeclaration\\")"} +org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem=Error +org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redefinition\\")"} +org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"} +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=Warning +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"} +org.eclipse.cdt.codan.internal.checkers.ShallowCopyProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ShallowCopyProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Miss copy constructor or assignment operator\\")",onlynew\=>false} +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning 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+org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")} +org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Using directive in header\\")"} +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem=Error +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Virtual method call in constructor/destructor\\")"} diff --git a/lib-c++/.settings/org.eclipse.cdt.core.prefs b/lib-showfile/.settings/org.eclipse.cdt.core.prefs old mode 100644 new mode 100755 similarity index 100% rename from lib-c++/.settings/org.eclipse.cdt.core.prefs rename to lib-showfile/.settings/org.eclipse.cdt.core.prefs diff --git a/lib-dmxreceiver/.settings/org.eclipse.core.resources.prefs b/lib-showfile/.settings/org.eclipse.core.resources.prefs old mode 100644 new mode 100755 similarity index 100% rename from lib-dmxreceiver/.settings/org.eclipse.core.resources.prefs rename to lib-showfile/.settings/org.eclipse.core.resources.prefs diff --git a/lib-showfile/Makefile.GD32 b/lib-showfile/Makefile.GD32 new file mode 100644 index 00000000..93df14ad --- /dev/null +++ b/lib-showfile/Makefile.GD32 @@ -0,0 +1,7 @@ +DEFINES=NDEBUG + +EXTRA_INCLUDES= + +include Rules.mk +include ../firmware-template-gd32/lib/Rules.mk + diff --git a/lib-showfile/Rules.mk b/lib-showfile/Rules.mk new file mode 100755 index 00000000..21bb2b9f --- /dev/null +++ b/lib-showfile/Rules.mk @@ -0,0 +1,57 @@ +$(info [${CURDIR}]) +$(info $$MAKE_FLAGS [${MAKE_FLAGS}]) + +EXTRA_INCLUDES+=../lib-properties/include ../lib-lightset/include ../lib-network/include + +ifneq ($(MAKE_FLAGS),) + ifeq (,$(findstring CONFIG_SHOWFILE_USE_CUSTOM_DISPLAY,$(MAKE_FLAGS))) + EXTRA_SRCDIR+=src/display + EXTRA_INCLUDES+=../lib-display/include + endif + ifneq (,$(findstring CONFIG_SHOWFILE_ENABLE_OSC,$(MAKE_FLAGS))) + EXTRA_SRCDIR+=src/osc + EXTRA_INCLUDES+=../lib-osc/include + endif + ifneq (,$(findstring CONFIG_SHOWFILE_FORMAT_OLA,$(MAKE_FLAGS))) + EXTRA_SRCDIR+=src/formats/ola + endif + ifneq (,$(findstring CONFIG_SHOWFILE_PROTOCOL_E131,$(MAKE_FLAGS))) + E131=1 + endif + ifneq (,$(findstring CONFIG_SHOWFILE_PROTOCOL_NODE_E131,$(MAKE_FLAGS))) + E131=1 + endif + ifneq (,$(findstring CONFIG_SHOWFILE_PROTOCOL_ARTNET,$(MAKE_FLAGS))) + ARTNET=1 + endif + ifneq (,$(findstring CONFIG_SHOWFILE_PROTOCOL_NODE_ARTNET,$(MAKE_FLAGS))) + ARTNET=1 + endif + ifdef E131 + EXTRA_INCLUDES+=../lib-e131/include + EXTRA_INCLUDES+=../lib-dmx/include + endif + ifdef ARTNET + EXTRA_SRCDIR+=src/protocols/artnet + EXTRA_INCLUDES+=../lib-artnet/include ../lib-e131/include + ifneq (,$(findstring RDM,$(MAKE_FLAGS))) + EXTRA_INCLUDES+=../lib-rdm/include ../lib-dmx/include + endif + endif +else + EXTRA_SRCDIR+=src/display + EXTRA_SRCDIR+=src/formats/ola + EXTRA_SRCDIR+=src/protocols/artnet + EXTRA_INCLUDES+=../lib-display/include + EXTRA_INCLUDES+=../lib-osc/include + EXTRA_INCLUDES+=../lib-e131/include + EXTRA_INCLUDES+=../lib-artnet/include + DEFINES+=NODE_SHOWFILE + DEFINES+=CONFIG_SHOWFILE_FORMAT_OLA +# DEFINES+=CONFIG_SHOWFILE_PROTOCOL_E131 + DEFINES+=CONFIG_SHOWFILE_PROTOCOL_NODE_E131 + DEFINES+=CONFIG_SHOWFILE_ENABLE_OSC +endif + +$(info $$EXTRA_SRCDIR [${EXTRA_SRCDIR}]) +$(info $$EXTRA_INCLUDES [${EXTRA_INCLUDES}]) \ No newline at end of file diff --git a/lib-showfile/include/formats/showfileformatola.h b/lib-showfile/include/formats/showfileformatola.h new file mode 100755 index 00000000..3290d9b1 --- /dev/null +++ b/lib-showfile/include/formats/showfileformatola.h @@ -0,0 +1,311 @@ +/** + * @file showfileformatola.h + * + */ +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef FORMATS_SHOWFILEFORMATOLA_H_ +#define FORMATS_SHOWFILEFORMATOLA_H_ + +#if !defined(__clang__) +# pragma GCC push_options +# pragma GCC optimize ("O2") +#endif + +#include +#include + +#include "showfileprotocol.h" +#include "showfileconst.h" + +#include "debug.h" + +#define SHOWFILE_PREFIX "show" +#define SHOWFILE_SUFFIX ".txt" + +namespace showfile { +static constexpr uint32_t FILE_NAME_LENGTH = sizeof(SHOWFILE_PREFIX "NN" SHOWFILE_SUFFIX) - 1U; +static constexpr uint32_t FILE_MAX_NUMBER = 99; +} // namespace showfile + +class ShowFileFormat: ShowFileProtocol { +public: + ShowFileFormat() { + DEBUG_ENTRY + + assert(s_pThis == nullptr); + s_pThis = this; + + for (uint32_t nIndex = 0; nIndex < sizeof(m_digitsTable); nIndex = nIndex + 2) { + const auto nValue = nIndex / 2; + m_digitsTable[nIndex] = '0' + static_cast(nValue / 10U); + m_digitsTable[nIndex + 1] = '0' + static_cast(nValue % 10U); + } + + ShowFileProtocol::Start(); + + DEBUG_EXIT + } + + void ShowFileStart() { + DEBUG_ENTRY + + m_nDelayMillis = 0; + m_nLastMillis = 0; + + fseek(m_pShowFile, 0L, SEEK_SET); + + m_OlaState = OlaState::IDLE; + + DEBUG_EXIT + } + + void ShowFileStop() { + DEBUG_ENTRY + + DEBUG_EXIT + } + + void ShowFileResume() { + DEBUG_ENTRY + + m_nDelayMillis = 0; + m_nLastMillis = 0; + + DEBUG_EXIT + } + + void ShowFileRecord() { + DEBUG_ENTRY + DEBUG_PRINTF("m_pShowFile%snullptr", m_pShowFile != nullptr ? "!=" : "=="); + + if (m_pShowFile != nullptr) { + fputs("OLA Show\n", m_pShowFile); +#ifndef NDEBUG + perror("fputs"); +#endif + m_OlaState = OlaState::RECORD_FIRST; + } else { + m_OlaState = OlaState::IDLE; + } + + ShowFileProtocol::Record(); + + DEBUG_EXIT + } + + void ShowFilePrint() { + puts(" Format: OLA"); + ShowFileProtocol::Print(); + } + + void ShowFileRun(const bool doRun) { + if (doRun) { + Run(); + } + + ShowFileProtocol::Run(); + } + + void DoRunCleanupProcess(const bool bDoRun) { + ShowFileProtocol::DoRunCleanupProcess(bDoRun); + } + + void ShowfileWrite(const uint8_t *pDmxData,const uint32_t nSize, const uint32_t nUniverse, const uint32_t nMillis) { + if (m_OlaState == OlaState::RECORD_FIRST) { + m_OlaState = OlaState::RECORDING; + } else { + auto *p = m_buffer; + p += fast_itoa_universe(nMillis - m_nLastMillis, p); + *p++ = '\n'; + *p = '\0'; + fputs(m_buffer, m_pShowFile); +#ifndef NDEBUG + perror("fputs"); + printf("[%s]", m_buffer); +#endif + } + + m_nLastMillis = nMillis; + + auto *p = m_buffer; + + p += fast_itoa_universe(nUniverse & 0xFFFF, p); + *p++ = ' '; + + for (uint32_t nIndex = 0; nIndex < nSize; nIndex++) { + p += fast_itoa_dmx(pDmxData[nIndex] & 0xFF, p); + *p++ = ','; + } + + *--p = '\n'; + *++p = '\0'; + + fputs(m_buffer, m_pShowFile); +#ifndef NDEBUG + perror("fputs"); + printf("[%s]", m_buffer); +#endif + } + + void BlackOut() { +#if defined (CONFIG_SHOWFILE_ENABLE_MASTER) + ShowFileProtocol::DmxBlackout(); +#endif + } + + void SetMaster([[maybe_unused]] const uint32_t nMaster) { +#if defined (CONFIG_SHOWFILE_ENABLE_MASTER) + ShowFileProtocol::DmxMaster(nMaster); +#endif + } + + bool IsSyncDisabled() { + return ShowFileProtocol::IsSyncDisabled(); + } + + static ShowFileFormat *Get() { + return s_pThis; + } + +private: + void Run(); + /* + * Using a lookup table to convert binary numbers from 0 to 99 + * into ascii characters as described by Andrei Alexandrescu in + * https://www.facebook.com/notes/facebook-engineering/three-optimization-tips-for-c/10151361643253920/ + */ + uint32_t fast_itoa_universe(uint32_t nUniverse, char *pDestination) { + uint32_t n = 0; + + if (nUniverse >= 10000) { + const auto nIndex = (nUniverse % 100) * 2; + pDestination[3] = m_digitsTable[nIndex]; + pDestination[4] = m_digitsTable[nIndex + 1]; + nUniverse /= 100; + n = 5; + } else if (nUniverse >= 1000) { + const auto nIndex = (nUniverse % 100) * 2; + pDestination[2] = m_digitsTable[nIndex]; + pDestination[3] = m_digitsTable[nIndex + 1]; + nUniverse /= 100; + n = 4; + } + + if (nUniverse >= 100) { + const auto nIndex = (nUniverse % 100) * 2; + pDestination[1] = m_digitsTable[nIndex]; + pDestination[2] = m_digitsTable[nIndex + 1]; + nUniverse /= 100; + if (n == 0) { + n = 2; + } + } + + if (nUniverse < 10) { + pDestination[0] = '0' + static_cast(nUniverse); + n++; + } else { + const auto nIndex = nUniverse * 2; + pDestination[0] = m_digitsTable[nIndex]; + pDestination[1] = m_digitsTable[nIndex + 1]; + if (n == 0) { + n = 2; + } + } + + return n; + } + + uint32_t fast_itoa_dmx(uint32_t nDmxValue, char *pDestination) { + uint32_t n = 0; + + if (nDmxValue >= 100) { + const auto nIndex = (nDmxValue % 100) * 2; + pDestination[1] = m_digitsTable[nIndex]; + pDestination[2] = m_digitsTable[nIndex + 1]; + nDmxValue /= 100; + n = 2; + } + + if (nDmxValue < 10) { + pDestination[0] = '0' + static_cast(nDmxValue); + n++; + } else { + const auto nIndex = nDmxValue * 2; + pDestination[0] = m_digitsTable[nIndex]; + pDestination[1] = m_digitsTable[nIndex + 1]; + n = 2; + } + + return n; + } + +#define UINT_DIGITS 12 + char *itoa_with_linefeed(uint32_t i) { + m_buffer[UINT_DIGITS + 1] = '\n'; + m_buffer[UINT_DIGITS + 2] = '\0'; + char *p = m_buffer + UINT_DIGITS; + do { + *--p = '0' + static_cast(i % 10); + i /= 10; + } while (i != 0); + return p; + } + +protected: + uint32_t m_nShowFileCurrent { showfile::FILE_MAX_NUMBER + 1 }; + bool m_bDoLoop { false }; + FILE *m_pShowFile { nullptr }; + +private: + enum class OlaState { + IDLE, PARSING_DMX, TIME_WAITING, RECORD_FIRST, RECORDING + }; + + enum class OlaParseCode { + FAILED, TIME, DMX, NONE, EOFILE + }; + + OlaParseCode GetNextLine(); + OlaParseCode ParseLine(const char *pLine); + OlaParseCode ParseDmxData(const char *pLine); + +private: + OlaParseCode m_OlaParseCode { OlaParseCode::FAILED }; + OlaState m_OlaState { OlaState::IDLE }; + char m_buffer[2048]; + char m_digitsTable[200]; + uint32_t m_nDelayMillis { 0 }; + uint32_t m_nLastMillis { 0 }; + uint32_t m_nDmxDataLength { 0 }; + uint16_t m_nUniverse { 0 }; + uint8_t m_DmxData[512]; + + static ShowFileFormat *s_pThis; +}; + +#if !defined(__clang__) +# pragma GCC pop_options +#endif + +#endif /* FORMATS_SHOWFILEFORMATOLA_H_ */ diff --git a/lib-showfile/include/protocols/showfileprotocolartnet.h b/lib-showfile/include/protocols/showfileprotocolartnet.h new file mode 100755 index 00000000..174bfadd --- /dev/null +++ b/lib-showfile/include/protocols/showfileprotocolartnet.h @@ -0,0 +1,110 @@ +/** + * @file showfileprotocolartnet.h + * + */ +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef PROTOCOLS_SHOWFILEPROTOCOLARTNET_H_ +#define PROTOCOLS_SHOWFILEPROTOCOLARTNET_H_ + +#include +#include + +#include "artnetcontroller.h" +#include "showfileprotocolartnettrigger.h" + +#include "debug.h" + +class ShowFileProtocol { +public: + ShowFileProtocol() { + DEBUG_ENTRY + + DEBUG_EXIT + } + + ~ShowFileProtocol() { + m_ArtNetController.Stop(); + } + + void Start() { + DEBUG_ENTRY + + m_ArtNetController.Start(); + + DEBUG_EXIT + } + + void Stop() { + DEBUG_ENTRY + + m_ArtNetController.Stop(); + + DEBUG_EXIT + } + + void Record() { + DEBUG_ENTRY + + DEBUG_EXIT + } + + void DmxOut(uint16_t nUniverse, const uint8_t *pDmxData, uint32_t nLength) { + m_ArtNetController.HandleDmxOut(nUniverse, pDmxData, nLength); + } + + void DmxSync() { + m_ArtNetController.HandleSync(); + } + + void DmxBlackout() { + m_ArtNetController.HandleBlackout(); + } + + void DmxMaster([[maybe_unused]] const uint32_t nMaster) { +#if defined(CONFIG_ARTNET_CONTROLLER_ENABLE_MASTER) + m_ArtNetController.SetMaster(nMaster); +#endif + } + + void DoRunCleanupProcess(const bool bDoRun) { + m_ArtNetController.SetRunTableCleanup(bDoRun); + } + + void Run() { + m_ArtNetController.Run(); + } + + bool IsSyncDisabled() { + return !m_ArtNetController.GetSynchronization(); + } + + void Print() { + m_ArtNetController.Print(); + } + +private: + ArtNetController m_ArtNetController; + ShowFileProtocolArtNetTrigger m_ShowFileProtocolArtNetTrigger; +}; + +#endif /* PROTOCOLS_SHOWFILEPROTOCOLARTNET_H_ */ diff --git a/lib-showfile/include/protocols/showfileprotocolartnettrigger.h b/lib-showfile/include/protocols/showfileprotocolartnettrigger.h new file mode 100755 index 00000000..9f655a8c --- /dev/null +++ b/lib-showfile/include/protocols/showfileprotocolartnettrigger.h @@ -0,0 +1,50 @@ +/** + * @file showfileprotocolartnettrigger.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef PROTOCOLS_SHOWFILEPROTOCOLARTNETTRIGGER_H_ +#define PROTOCOLS_SHOWFILEPROTOCOLARTNETTRIGGER_H_ + +#include +#include + +#include "artnetcontroller.h" +#include "artnettrigger.h" + +#include "debug.h" + +class ShowFileProtocolArtNetTrigger: public ArtNetTrigger { +public: + ShowFileProtocolArtNetTrigger() { + DEBUG_ENTRY + + ArtNetController::Get()->SetArtNetTrigger(this); + + DEBUG_EXIT + } + + void Handler(const struct TArtNetTrigger *ptArtNetTrigger) override; +}; + +#endif /* PROTOCOLS_SHOWFILEPROTOCOLARTNETTRIGGER_H_ */ diff --git a/lib-showfile/include/protocols/showfileprotocole131.h b/lib-showfile/include/protocols/showfileprotocole131.h new file mode 100755 index 00000000..975ac7fb --- /dev/null +++ b/lib-showfile/include/protocols/showfileprotocole131.h @@ -0,0 +1,105 @@ +/** + * @file showfileprotocole131.h + * + */ +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef PROTOCOLS_SHOWFILEPROTOCOLE131_H_ +#define PROTOCOLS_SHOWFILEPROTOCOLE131_H_ + +#include +#include + +#include "e131controller.h" + +#include "debug.h" + +class ShowFileProtocol { +public: + ShowFileProtocol() { + DEBUG_ENTRY + + DEBUG_EXIT + } + + void SetSynchronizationAddress(const uint16_t SynchronizationAddress) { + m_E131Controller.SetSynchronizationAddress(SynchronizationAddress); + } + + void Start() { + DEBUG_ENTRY + + m_E131Controller.Start(); + + DEBUG_EXIT + } + + void Stop() { + DEBUG_ENTRY + + m_E131Controller.Stop(); + + DEBUG_EXIT + } + + void Record() { + DEBUG_ENTRY + + DEBUG_EXIT + } + + void DmxOut(const uint16_t nUniverse, const uint8_t *pDmxData, const uint32_t nLength) { + m_E131Controller.HandleDmxOut(nUniverse, pDmxData, nLength); + } + + void DmxSync() { + m_E131Controller.HandleSync(); + } + + void DmxBlackout() { + m_E131Controller.HandleBlackout(); + } + + void DmxMaster(const uint32_t nMaster) { + m_E131Controller.SetMaster(nMaster); + } + + void DoRunCleanupProcess([[maybe_unused]] bool bDoRun) { + } + + void Run() { + m_E131Controller.Run(); + } + + bool IsSyncDisabled() { + return (m_E131Controller.GetSynchronizationAddress() == 0); + } + + void Print() { + m_E131Controller.Print(); + } + +private: + E131Controller m_E131Controller; +}; + +#endif /* PROTOCOLS_SHOWFILEPROTOCOLE131_H_ */ diff --git a/lib-showfile/include/protocols/showfileprotocolnodeartnet.h b/lib-showfile/include/protocols/showfileprotocolnodeartnet.h new file mode 100755 index 00000000..004f58fc --- /dev/null +++ b/lib-showfile/include/protocols/showfileprotocolnodeartnet.h @@ -0,0 +1,118 @@ +/** + * @file showfileprotocolnodeartnet.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef PROTOCOLS_SHOWFILEPROTOCOLNODEARTNET_H_ +#define PROTOCOLS_SHOWFILEPROTOCOLNODEARTNET_H_ + +#include +#include + +#include "artnetnode.h" +#include "artnet.h" + +#include "debug.h" + +class ShowFileProtocol { +public: + ShowFileProtocol() { + DEBUG_ENTRY + + memcpy(m_ArtDmx.Id, artnet::NODE_ID, sizeof(m_ArtDmx.Id)); + m_ArtDmx.OpCode = static_cast(artnet::OpCodes::OP_DMX); + m_ArtDmx.ProtVerHi = 0; + m_ArtDmx.ProtVerLo = artnet::PROTOCOL_REVISION; + + DEBUG_EXIT + } + + void SetSynchronizationAddress([[maybe_unused]] const uint16_t SynchronizationAddress) { + } + + void Start() { + DEBUG_ENTRY + + DEBUG_EXIT + } + + void Stop() { + DEBUG_ENTRY + + ArtNetNode::Get()->SetRecordShowfile(false); + + DEBUG_EXIT + } + + void Record() { + DEBUG_ENTRY + + ArtNetNode::Get()->SetRecordShowfile(true); + + DEBUG_EXIT + } + + void DmxOut(const uint16_t nUniverse, const uint8_t *pDmxData, uint32_t nLength) { + memcpy(m_ArtDmx.Data, pDmxData, nLength); + + if ((nLength & 0x1) == 0x1) { + m_ArtDmx.Data[nLength] = 0x00; + nLength++; + } + + m_ArtDmx.Sequence = m_nSequence++; + m_ArtDmx.Physical = static_cast(artnetnode::MAX_PORTS + 1U); + m_ArtDmx.PortAddress = nUniverse; + m_ArtDmx.LengthHi = static_cast((nLength & 0xFF00) >> 8); + m_ArtDmx.Length = static_cast(nLength & 0xFF); + + ArtNetNode::Get()->HandleShowFile(&m_ArtDmx); + } + + void DmxSync() { + } + + void DmxBlackout() { + } + + void DmxMaster([[maybe_unused]] const uint32_t nMaster) { + } + + void DoRunCleanupProcess([[maybe_unused]] bool bDoRun) { + } + + void Run() { + } + + bool IsSyncDisabled() { + return false; + } + + void Print() {} + +private: + artnet::ArtDmx m_ArtDmx; + uint8_t m_nSequence { 0 }; +}; + +#endif /* PROTOCOLS_SHOWFILEPROTOCOLNODEARTNET_H_ */ diff --git a/lib-showfile/include/protocols/showfileprotocolnodee131.h b/lib-showfile/include/protocols/showfileprotocolnodee131.h new file mode 100755 index 00000000..491325bd --- /dev/null +++ b/lib-showfile/include/protocols/showfileprotocolnodee131.h @@ -0,0 +1,129 @@ +/** + * @file showfileprotocolnodee131.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef PROTOCOLS_SHOWFILEPROTOCOLNODEE131_H_ +#define PROTOCOLS_SHOWFILEPROTOCOLNODEE131_H_ + +#include +#include + +#include "e131bridge.h" +#include "e131.h" +#include "e117const.h" + +#include "hardware.h" + +#include "debug.h" + +class ShowFileProtocol { +public: + ShowFileProtocol() { + DEBUG_ENTRY + // Root Layer (See Section 5) + m_E131DataPacket.RootLayer.PreAmbleSize = __builtin_bswap16(0x0010); + m_E131DataPacket.RootLayer.PostAmbleSize = __builtin_bswap16(0x0000); + memcpy(m_E131DataPacket.RootLayer.ACNPacketIdentifier, E117Const::ACN_PACKET_IDENTIFIER, e117::PACKET_IDENTIFIER_LENGTH); + m_E131DataPacket.RootLayer.Vector = __builtin_bswap32(e131::vector::root::DATA); + Hardware::Get()->GetUuid(m_E131DataPacket.RootLayer.Cid); + // E1.31 Framing Layer (See Section 6) + m_E131DataPacket.FrameLayer.Vector = __builtin_bswap32(e131::vector::data::PACKET); + memcpy(m_E131DataPacket.FrameLayer.SourceName, E131Bridge::Get()->GetSourceName(), e131::SOURCE_NAME_LENGTH); + m_E131DataPacket.FrameLayer.SynchronizationAddress = __builtin_bswap16(0); + m_E131DataPacket.FrameLayer.Priority = e131::priority::DEFAULT; + m_E131DataPacket.FrameLayer.Options = 0; + // Data Layer + m_E131DataPacket.DMPLayer.Vector = e131::vector::dmp::SET_PROPERTY; + m_E131DataPacket.DMPLayer.Type = 0xa1; + m_E131DataPacket.DMPLayer.FirstAddressProperty = __builtin_bswap16(0x0000); + m_E131DataPacket.DMPLayer.AddressIncrement = __builtin_bswap16(0x0001); + m_E131DataPacket.DMPLayer.PropertyValues[0] = 0; + + DEBUG_EXIT + } + + void SetSynchronizationAddress([[maybe_unused]] const uint16_t SynchronizationAddress) { + } + + void Start() { + DEBUG_ENTRY + + DEBUG_EXIT + } + + void Stop() { + DEBUG_ENTRY + + DEBUG_EXIT + } + + void Record() { + DEBUG_ENTRY + + DEBUG_EXIT + } + + void DmxOut(const uint16_t nUniverse, const uint8_t *pDmxData, uint32_t nLength) { + nLength++; // Add 1 for SC + // Root Layer (See Section 5) + m_E131DataPacket.RootLayer.FlagsLength = __builtin_bswap16(static_cast((0x07 << 12) | (DATA_ROOT_LAYER_LENGTH(nLength)))); + // E1.31 Framing Layer (See Section 6) + m_E131DataPacket.FrameLayer.FLagsLength = __builtin_bswap16(static_cast((0x07 << 12) | (DATA_FRAME_LAYER_LENGTH(nLength)))); + m_E131DataPacket.FrameLayer.SequenceNumber = m_nSequenceNumber++; + m_E131DataPacket.FrameLayer.Universe = __builtin_bswap16(nUniverse); + // Data Layer + m_E131DataPacket.DMPLayer.FlagsLength = __builtin_bswap16(static_cast((0x07 << 12) | (DATA_LAYER_LENGTH(nLength)))); + memcpy(m_E131DataPacket.DMPLayer.PropertyValues, &pDmxData[1], nLength - 1); + m_E131DataPacket.DMPLayer.PropertyValueCount = __builtin_bswap16(static_cast(nLength)); + + E131Bridge::Get()->HandleShowFile(&m_E131DataPacket); + } + + void DmxSync() { + } + + void DmxBlackout() { + } + + void DmxMaster([[maybe_unused]] const uint32_t nMaster) { + } + + void DoRunCleanupProcess([[maybe_unused]] bool bDoRun) { + } + + void Run() { + } + + bool IsSyncDisabled() { + return false; + } + + void Print() {} + +private: + TE131DataPacket m_E131DataPacket; + uint8_t m_nSequenceNumber { 0 }; +}; + +#endif /* PROTOCOLS_SHOWFILEPROTOCOLNODEE131_H_ */ diff --git a/lib-showfile/include/showfile.h b/lib-showfile/include/showfile.h new file mode 100644 index 00000000..834a8a44 --- /dev/null +++ b/lib-showfile/include/showfile.h @@ -0,0 +1,312 @@ +/** + * @file showfile.h + * + */ +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef SHOWFILE_H_ +#define SHOWFILE_H_ + +#include + +#include "showfileconst.h" +#include "showfiletftp.h" +#include "showfileformat.h" +#include "showfileprotocol.h" + +#if defined (CONFIG_SHOWFILE_ENABLE_OSC) +# include "showfileosc.h" +#endif + +#if defined (OUTPUT_DMX_PIXEL) || defined (OUTPUT_DMX_PIXEL_MULTI) +# define CONFIG_SHOWFILE_ENABLE_MASTER +#endif + +#include "debug.h" + +namespace showfile { +bool filename_copyto(char *pShowFileName, const uint32_t nLength, const uint32_t nShowFileNumber); +bool filename_check(const char *pShowFileName, uint32_t &nShowFileNumber); +} // namespace showfile + +class ShowFile final: public ShowFileFormat { +public: +#if defined (CONFIG_SHOWFILE_ENABLE_OSC) + ShowFile(uint16_t nPortIncoming = osc::port::DEFAULT_INCOMING, uint16_t nPortOutgoing = osc::port::DEFAULT_OUTGOING); +#else + ShowFile(); +#endif + + void Play() { + DEBUG_ENTRY + + if ((m_Mode == showfile::Mode::RECORDER) || (m_Status == showfile::Status::PLAYING) || (m_Status == showfile::Status::RECORDING)) { + DEBUG_EXIT + return; + } + + EnableTFTP(false); + + if (m_pShowFile != nullptr) { + ShowFileFormat::ShowFileStart(); + SetStatus(showfile::Status::PLAYING); + } else { + SetStatus(showfile::Status::IDLE); + } + + DEBUG_EXIT + } + + void Stop() { + DEBUG_ENTRY + + if (m_pShowFile != nullptr) { + ShowFileFormat::ShowFileStop(); + + if ((m_Status == showfile::Status::STOPPED) || (m_Status == showfile::Status::RECORDING)) { + if (m_Status == showfile::Status::RECORDING) { + fclose(m_pShowFile); + } + SetStatus(showfile::Status::IDLE); + } else { + SetStatus(showfile::Status::STOPPED); + } + } + + DEBUG_EXIT + } + + void Resume() { + DEBUG_ENTRY + + if (m_Status != showfile::Status::STOPPED) { + DEBUG_EXIT + return; + } + + if (m_pShowFile != nullptr) { + ShowFileFormat::ShowFileResume(); + SetStatus(showfile::Status::PLAYING); + } + + DEBUG_EXIT + } + +#if !defined (CONFIG_SHOWFILE_DISABLE_RECORD) + void Record() { + DEBUG_ENTRY + + if ((m_Mode == showfile::Mode::PLAYER) || (m_Status != showfile::Status::IDLE)) { + DEBUG_EXIT + return; + } + + if (m_pShowFile != nullptr) { + ShowFileFormat::ShowFileRecord(); + SetStatus(showfile::Status::RECORDING); + } else { + SetStatus(showfile::Status::IDLE); + } + + DEBUG_EXIT + } +#endif + + void Run() { + ShowFileFormat::ShowFileRun(m_Status == showfile::Status::PLAYING); +#if defined (CONFIG_SHOWFILE_ENABLE_OSC) + m_showFileOSC.Run(); +#endif +#if !defined(CONFIG_SHOWFILE_DISABLE_TFTP) + if (m_pShowFileTFTP != nullptr) { + m_pShowFileTFTP->Run(); + } +#endif + } + + void Print() { + puts("Showfile"); + if (m_aShowFileNameCurrent[0] != '\0') { + printf(" %s\n", m_aShowFileNameCurrent); + } + if (m_bAutoPlay) { + puts(" Auto play"); + } + printf(" %s\n", m_bDoLoop ? "Looping" : "Not looping"); +#if defined (CONFIG_SHOWFILE_DISABLE_RECORD) + puts(" Recorder is disabled."); +#endif + ShowFileFormat::ShowFilePrint(); +#if defined (CONFIG_SHOWFILE_ENABLE_OSC) + m_showFileOSC.Print(); +#endif + } + + showfile::Mode GetMode() const { + return m_Mode; + } + + void SetStatus(const showfile::Status Status); + + showfile::Status GetStatus() const { + return m_Status; + } + + void LoadShows(); + + void UnloadShows() { + m_nShows = 0; + + for (auto &FileIndex : m_nShowFileNumber) { + FileIndex = -1; + } + + m_nShowFileCurrent = showfile::FILE_MAX_NUMBER + 1U; + } + + void SetPlayerShowFileCurrent(const uint32_t nShowFileNumber); + +#if !defined (CONFIG_SHOWFILE_DISABLE_RECORD) + void SetRecorderShowFileCurrent(const uint32_t nShowFileNumber); +#endif + + const char *GetShowFileNameCurrent() const { + return static_cast(m_aShowFileNameCurrent); + } + + uint32_t GetShowFileCurrent() const { + return m_nShowFileCurrent; + } + + uint32_t GetShows() { + if (m_nShows == 0) { + LoadShows(); + } + return m_nShows; + } + + int32_t GetPlayerShowFile(const uint32_t nIndex) const { + if (nIndex < sizeof(m_nShowFileNumber) / sizeof(m_nShowFileNumber[0]) ) { + return m_nShowFileNumber[nIndex]; + } + + return -1; + } + + bool DeleteShowFile(const uint32_t nShowFileNumber); + + bool GetShowFileSize(const uint32_t nShowFileNumber, uint32_t &nSize); + + void DoLoop(const bool bDoLoop) { + m_bDoLoop = bDoLoop; + } + + bool GetDoLoop() const { + return m_bDoLoop; + } + + void SetAutoStart(const bool bAutoPlay) { + m_bAutoPlay = bAutoPlay; + } + + bool IsAutoStart() const { + return m_bAutoPlay; + } + + bool IsSyncDisabled() { + return ShowFileFormat::IsSyncDisabled(); + } + + void BlackOut() { +#if defined (CONFIG_SHOWFILE_ENABLE_MASTER) + Stop(); + ShowFileFormat::BlackOut(); +#endif + } + + void SetMaster([[maybe_unused]] const uint32_t nMaster) { +#if defined (CONFIG_SHOWFILE_ENABLE_MASTER) + ShowFileFormat::SetMaster(nMaster); +#endif + } + + /* + * TFTP + */ + + void EnableTFTP(bool bEnableTFTP); + + bool IsTFTPEnabled() const { +#if !defined(CONFIG_SHOWFILE_DISABLE_TFTP) + return m_bEnableTFTP; +#else + return false; +#endif + } + + /* + * OSC + */ + +#if defined (CONFIG_SHOWFILE_ENABLE_OSC) + void SetOscPortIncoming(const uint16_t nPortIncoming) { + m_showFileOSC.SetPortIncoming(nPortIncoming); + } + uint16_t GetOscPortIncoming() const { + return m_showFileOSC.GetPortIncoming(); + } + + void SetOscPortOutgoing(const uint16_t nPortOutgoing) { + m_showFileOSC.SetPortOutgoing(nPortOutgoing); + } + + uint16_t GetOscPortOutgoing() const { + return m_showFileOSC.GetPortOutgoing(); + } +#endif + + static ShowFile *Get() { + return s_pThis; + } + +private: + void OpenFile(const showfile::Mode mode, const uint32_t nShowFileNumber); + bool AddShow(const uint32_t nShowFileNumber); + +private: +#if defined (CONFIG_SHOWFILE_ENABLE_OSC) + ShowFileOSC m_showFileOSC; +#endif + showfile::Mode m_Mode {showfile::Mode::PLAYER }; + showfile::Status m_Status { showfile::Status::IDLE }; + char m_aShowFileNameCurrent[showfile::FILE_NAME_LENGTH + 1]; // Including '\0' + uint32_t m_nShows { 0 }; + int32_t m_nShowFileNumber[showfile::FILE_MAX_NUMBER + 1]; + bool m_bAutoPlay { false }; +#if !defined(CONFIG_SHOWFILE_DISABLE_TFTP) + bool m_bEnableTFTP { false }; + ShowFileTFTP *m_pShowFileTFTP { nullptr }; +#endif + static ShowFile *s_pThis; +}; + +#endif /* SHOWFILE_H_ */ diff --git a/lib-network/src/net/net_timers.cpp b/lib-showfile/include/showfileconst.h old mode 100644 new mode 100755 similarity index 65% rename from lib-network/src/net/net_timers.cpp rename to lib-showfile/include/showfileconst.h index ef8a35c7..fab1f111 --- a/lib-network/src/net/net_timers.cpp +++ b/lib-showfile/include/showfileconst.h @@ -1,8 +1,8 @@ /** - * @file net_timers.cpp + * @file showfileconst.h * */ -/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,30 +23,23 @@ * THE SOFTWARE. */ -#include - -#include "net_private.h" +#ifndef SHOWFILECONST_H_ +#define SHOWFILECONST_H_ -#include "hardware.h" - -#include "../../config/net_config.h" +#include -#ifndef NDEBUG - extern void arp_cache_timer(void); -#endif +namespace showfile { +enum class Status { + IDLE, PLAYING, STOPPED, ENDED, RECORDING, UNDEFINED +}; -static volatile uint32_t s_ticker; +static constexpr char STATUS[static_cast(showfile::Status::UNDEFINED)][12] = { "Idle", "Playing", "Stopped", "Ended", "Recording" }; -#define INTERVAL_MS (100) // 100 msec, 1/10 second +enum class Mode { + PLAYER, RECORDER, UNDEFINED +}; -void net_timers_run() { - const auto nMillis = Hardware::Get()->Millis(); +static constexpr char MODE[static_cast(showfile::Mode::UNDEFINED)][10] = { "Player", "Recorder" }; +} // namespace showfile - if (__builtin_expect((nMillis >= s_ticker), 0)) { - s_ticker = nMillis + INTERVAL_MS; - igmp_timer(); -#ifndef NDEBUG - arp_cache_timer(); -#endif - } -} +#endif /* SHOWFILECONST_H_ */ diff --git a/lib-showfile/include/showfiledisplay.h b/lib-showfile/include/showfiledisplay.h new file mode 100644 index 00000000..977230b3 --- /dev/null +++ b/lib-showfile/include/showfiledisplay.h @@ -0,0 +1,36 @@ +/** + * @file showfiledisplay.h + * + */ +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef SHOWFILEDISPLAY_H_ +#define SHOWFILEDISPLAY_H_ + +#include + +namespace showfile { +void display_filename(const char *pFileName, const uint32_t nShow); +void display_status(); +} // namespace showfile + +#endif /* SHOWFILEDISPLAY_H_ */ diff --git a/lib-showfile/include/showfileformat.h b/lib-showfile/include/showfileformat.h new file mode 100755 index 00000000..8e5737f0 --- /dev/null +++ b/lib-showfile/include/showfileformat.h @@ -0,0 +1,35 @@ +/** + * @file showfileformat.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef SHOWFILEFORMAT_H_ +#define SHOWFILEFORMAT_H_ + +#if defined (CONFIG_SHOWFILE_FORMAT_OLA) +# include "formats/showfileformatola.h" +#else +# error Format is not supported +#endif + +#endif /* SHOWFILEFORMAT_H_ */ diff --git a/lib-showfile/include/showfileosc.h b/lib-showfile/include/showfileosc.h new file mode 100644 index 00000000..66056394 --- /dev/null +++ b/lib-showfile/include/showfileosc.h @@ -0,0 +1,108 @@ +/** + * @file showfileosc.h + * + */ +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef SHOWFILEOSC_H_ +#define SHOWFILEOSC_H_ + +#if !defined (CONFIG_SHOWFILE_ENABLE_OSC) +# error This file should not be included +#endif + +#include +#include +#include + +#include "showfiledisplay.h" +#include "osc.h" + +#include "network.h" + +namespace cmd { +static constexpr char PATH[] = "/showfile/"; +} +namespace length { +static constexpr uint32_t PATH = sizeof(cmd::PATH) - 1; +} // namespace length + +struct ShowFileOSCMax { + static constexpr auto CMD_LENGTH = 128; + static constexpr auto FILES_ENTRIES = 10; +}; + +class ShowFileOSC { +public: + ShowFileOSC(uint16_t nPortIncoming = osc::port::DEFAULT_INCOMING, uint16_t nPortOutgoing = osc::port::DEFAULT_OUTGOING); + ~ShowFileOSC(); + + void Run() { + m_nBytesReceived = Network::Get()->RecvFrom(m_nHandle, const_cast(reinterpret_cast(&m_pBuffer)), &m_nRemoteIp, &m_nRemotePort); + + if (__builtin_expect((m_nBytesReceived <= length::PATH), 1)) { + return; + } + + if (memcmp(m_pBuffer, cmd::PATH, length::PATH) == 0) { + Process(); + } + } + + void Print() { + puts("OSC Server"); + printf(" Path : [%s]\n", cmd::PATH); + printf(" Incoming port : %u\n", m_nPortIncoming); + printf(" Outgoing port : %u\n", m_nPortOutgoing); + } + + void SetPortIncoming(const uint16_t nPortIncoming) { + m_nPortIncoming = nPortIncoming; + } + uint16_t GetPortIncoming() const { + return m_nPortIncoming; + } + + void SetPortOutgoing(const uint16_t nPortOutgoing) { + m_nPortOutgoing = nPortOutgoing; + } + + uint16_t GetPortOutgoing() const { + return m_nPortOutgoing; + } + +private: + void Process(); + void SendStatus(); + void ShowFiles(); + +private: + int32_t m_nHandle { -1 }; + char *m_pBuffer { nullptr }; + uint32_t m_nRemoteIp { 0 }; + uint32_t m_nBytesReceived; + uint16_t m_nRemotePort { 0 }; + uint16_t m_nPortIncoming; + uint16_t m_nPortOutgoing; +}; + +#endif /* SHOWFILEOSC_H_ */ diff --git a/lib-showfile/include/showfileparams.h b/lib-showfile/include/showfileparams.h new file mode 100644 index 00000000..e4a0bb87 --- /dev/null +++ b/lib-showfile/include/showfileparams.h @@ -0,0 +1,103 @@ +/** + * @file showfileparams.h + * + */ +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef SHOWFILEPARAMS_H_ +#define SHOWFILEPARAMS_H_ + +#include + +#include "showfile.h" +#include "configstore.h" + +namespace showfileparams { +struct Params { + uint32_t nSetList; + uint8_t nShow; + uint16_t nOscPortIncoming; + uint16_t nOscPortOutgoing; + uint16_t nUniverse; + uint8_t nDisableUnicast; + uint8_t nDmxMaster; +} __attribute__((packed)); + +struct Mask { + static constexpr uint32_t SHOW = (1U << 0); + static constexpr uint32_t OSC_PORT_INCOMING = (1U << 1); + static constexpr uint32_t OSC_PORT_OUTGOING = (1U << 2); + static constexpr uint32_t PROTOCOL = (1U << 3); + static constexpr uint32_t SACN_UNIVERSE = (1U << 4); + static constexpr uint32_t ARTNET_UNICAST_DISABLED = (1U << 5); + static constexpr uint32_t DMX_MASTER = (1U << 6); + static constexpr uint32_t OPTION_AUTO_PLAY = (1U << 7); + static constexpr uint32_t OPTION_LOOP = (1U << 8); + static constexpr uint32_t OPTION_DISABLE_SYNC = (1U << 9); +}; +} // namespace showfileparams + +class ShowFileParamsStore { +public: + static void Update(const struct showfileparams::Params *ptShowFileParams) { + ConfigStore::Get()->Update(configstore::Store::SHOW, ptShowFileParams, sizeof(struct showfileparams::Params)); + } + + static void Copy(struct showfileparams::Params *ptShowFileParams) { + ConfigStore::Get()->Copy(configstore::Store::SHOW, ptShowFileParams, sizeof(struct showfileparams::Params)); + } +}; + +class ShowFileParams { +public: + ShowFileParams(); + + void Load(); + void Load(const char *pBuffer, uint32_t nLength); + + void Builder(const struct TShowFileParams *ptShowFileParamss, char *pBuffer, uint32_t nLength, uint32_t& nSize); + void Save(char *pBuffer, uint32_t nLength, uint32_t& nSize) { + Builder(nullptr, pBuffer, nLength, nSize); + } + + void Set(); + + bool IsArtNetBroadcast() const { + return isMaskSet(showfileparams::Mask::ARTNET_UNICAST_DISABLED); + } + + static void staticCallbackFunction(void *p, const char *s); + +private: + void Dump(); + void HandleOptions(const char *pLine, const char *pKeyword, uint16_t nMask); + void callbackFunction(const char *s); + bool isMaskSet(uint32_t nMask) const { + return (m_Params.nSetList & nMask) == nMask; + } + void SetBool(const uint8_t nValue, const uint32_t nMask); + +private: + showfileparams::Params m_Params; +}; + +#endif /* SHOWFILEPARAMS_H_ */ diff --git a/lib-rdmsensor/src/rmdsensorprint.cpp b/lib-showfile/include/showfileparamsconst.h similarity index 71% rename from lib-rdmsensor/src/rmdsensorprint.cpp rename to lib-showfile/include/showfileparamsconst.h index 369ea0dc..f403b9d1 100644 --- a/lib-rdmsensor/src/rmdsensorprint.cpp +++ b/lib-showfile/include/showfileparamsconst.h @@ -1,5 +1,5 @@ /** - * @file rdmsensorprint.cpp + * @file showfileparamsconst.h * */ /* Copyright (C) 2020 by Arjan van Vught mailto:info@orangepi-dmx.nl @@ -23,14 +23,22 @@ * THE SOFTWARE. */ -#include +#ifndef SHOWFILEPARAMSCONST_H_ +#define SHOWFILEPARAMSCONST_H_ -#include "rdmsensor.h" +struct ShowFileParamsConst { + static const char FILE_NAME[]; -void RDMSensor::Print() { - printf("%d [%.*s]\n", m_tRDMSensorDefintion.sensor, m_tRDMSensorDefintion.nLength, m_tRDMSensorDefintion.description); - printf(" RangeMin %d\n", m_tRDMSensorDefintion.range_min); - printf(" RangeMax %d\n", m_tRDMSensorDefintion.range_max); - printf(" NormalMin %d\n", m_tRDMSensorDefintion.normal_min); - printf(" NormalMax %d\n", m_tRDMSensorDefintion.normal_max); -} + static const char SHOW[]; + + static const char DMX_MASTER[]; + + static const char OPTION_AUTO_PLAY[]; + static const char OPTION_LOOP[]; + static const char OPTION_DISABLE_SYNC[]; + + static const char SACN_SYNC_UNIVERSE[]; + static const char ARTNET_DISABLE_UNICAST[]; +}; + +#endif /* SHOWFILEPARAMSCONST_H_ */ diff --git a/lib-showfile/include/showfileprotocol.h b/lib-showfile/include/showfileprotocol.h new file mode 100755 index 00000000..feba3cc2 --- /dev/null +++ b/lib-showfile/include/showfileprotocol.h @@ -0,0 +1,51 @@ +/** + * @file showfileprotocol.h + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef SHOWFILEPROTOCOL_H_ +#define SHOWFILEPROTOCOL_H_ + +#if defined (CONFIG_SHOWFILE_PROTOCOL_E131) +# include "protocols/showfileprotocole131.h" +#elif defined (CONFIG_SHOWFILE_PROTOCOL_ARTNET) +# include "protocols/showfileprotocolartnet.h" +#elif defined (CONFIG_SHOWFILE_PROTOCOL_NODE_E131) +# define CONFIG_SHOWFILE_PROTOCOL_INTERNAL +# include "protocols/showfileprotocolnodee131.h" +#elif defined (CONFIG_SHOWFILE_PROTOCOL_NODE_ARTNET) +# define CONFIG_SHOWFILE_PROTOCOL_INTERNAL +# include "protocols/showfileprotocolnodeartnet.h" +#else +# error Protocol is not supported +#endif + +#if defined(CONFIG_SHOWFILE_PROTOCOL_E131) && defined(CONFIG_SHOWFILE_PROTOCOL_ARTNET) +# error Protocol configuration error +#endif + +#if defined(CONFIG_SHOWFILE_PROTOCOL_NODE_E131) && defined(CONFIG_SHOWFILE_PROTOCOL_NODE_ARTNET) +# error Protocol node configuration error +#endif + +#endif /* SHOWFILEPROTOCOL_H_ */ diff --git a/lib-configstore/include/storerdmsubdevices.h b/lib-showfile/include/showfiletftp.h similarity index 57% rename from lib-configstore/include/storerdmsubdevices.h rename to lib-showfile/include/showfiletftp.h index cdd4c1c6..95467850 100644 --- a/lib-configstore/include/storerdmsubdevices.h +++ b/lib-showfile/include/showfiletftp.h @@ -1,5 +1,5 @@ /** - * @file storerdmsubdevices.h + * @file showfiletftp.h * */ /* Copyright (C) 2020-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl @@ -23,31 +23,50 @@ * THE SOFTWARE. */ -#ifndef STORERDMSUBDEVICES_H_ -#define STORERDMSUBDEVICES_H_ +#ifndef SHOWFILETFTP_H_ +#define SHOWFILETFTP_H_ -#include "rdmsubdevicesparams.h" +#include -#include "configstore.h" +#include "net/apps/tftpdaemon.h" -class StoreRDMSubDevices final: public RDMSubDevicesParamsStore { +#include "debug.h" + +class ShowFileTFTP final: public TFTPDaemon { public: - StoreRDMSubDevices(); + ShowFileTFTP() { + DEBUG_ENTRY - void Update(const rdm::subdevicesparams::Params *pParams) override { - ConfigStore::Get()->Update(configstore::Store::RDMSUBDEVICES, pParams, sizeof(struct rdm::subdevicesparams::Params)); + DEBUG_EXIT } - void Copy(rdm::subdevicesparams::Params *pParams) override { - ConfigStore::Get()->Copy(configstore::Store::RDMSUBDEVICES, pParams, sizeof(struct rdm::subdevicesparams::Params)); + bool FileOpen(const char *pFileName, tftp::Mode mode) override; + bool FileCreate(const char *pFileName, tftp::Mode mode) override; + + bool FileClose() override { + DEBUG_ENTRY + + if (m_pFile != nullptr) { + fclose(m_pFile); + m_pFile = nullptr; + } + + DEBUG_EXIT + return true; } - static StoreRDMSubDevices *Get() { - return s_pThis; + size_t FileRead(void *pBuffer, size_t nCount, [[maybe_unused]] unsigned nBlockNumber) override { + return fread(pBuffer, 1, nCount, m_pFile); } + size_t FileWrite(const void *pBuffer, size_t nCount, [[maybe_unused]] unsigned nBlockNumber) override { + return fwrite(pBuffer, 1, nCount, m_pFile); + } + + void Exit() override; + private: - static StoreRDMSubDevices *s_pThis; + FILE *m_pFile { nullptr }; }; -#endif /* STORERDMSUBDEVICES_H_ */ +#endif /* SHOWFILETFTP_H_ */ diff --git a/lib-showfile/src/display/showfiledisplay.cpp b/lib-showfile/src/display/showfiledisplay.cpp new file mode 100755 index 00000000..88300534 --- /dev/null +++ b/lib-showfile/src/display/showfiledisplay.cpp @@ -0,0 +1,88 @@ +/** + * @file showfiledisplay.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "showfile.h" +#include "showfiledisplay.h" + +#include "display.h" + +namespace showfile { +void display_filename(const char *pFileName, const uint32_t nShow) { + assert(pFileName != nullptr); + + if (pFileName[0] != 0) { + Display::Get()->TextStatus(pFileName, static_cast(nShow)); + } else { + Display::Get()->TextStatus("No showfile"); + } +} + +void display_status() { + Display::Get()->SetCursorPos(0, 6); + + switch (ShowFile::Get()->GetStatus()) { + case showfile::Status::IDLE: + Display::Get()->PutString("Idle "); + break; + case showfile::Status::PLAYING: + Display::Get()->PutString("Running "); + break; + case showfile::Status::STOPPED: + Display::Get()->PutString("Stopped "); + break; + case showfile::Status::ENDED: + Display::Get()->PutString("Ended "); + break; + case showfile::Status::RECORDING: + Display::Get()->PutString("Recording "); + break; + case showfile::Status::UNDEFINED: + default: + Display::Get()->PutString("No Status"); + break; + } + + Display::Get()->SetCursorPos(11, 7); + + if (ShowFile::Get()->IsTFTPEnabled()) { + Display::Get()->PutString("[TFTP On]"); + } else if (ShowFile::Get()->GetDoLoop()) { + Display::Get()->PutString("[Looping]"); + } else { + Display::Get()->PutString(" "); + } +} +} // namespace showfile + + + + + + + + diff --git a/lib-showfile/src/formats/ola/showfile_record.cpp b/lib-showfile/src/formats/ola/showfile_record.cpp new file mode 100755 index 00000000..263540ce --- /dev/null +++ b/lib-showfile/src/formats/ola/showfile_record.cpp @@ -0,0 +1,64 @@ +/** + * @file showfile_record.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#if !defined(__clang__) +# pragma GCC push_options +# pragma GCC optimize ("O2") +#endif + +#include +#include "formats/showfileformatola.h" + +#if defined (CONFIG_SHOWFILE_PROTOCOL_NODE_ARTNET) +#include "artnet.h" + +namespace showfile { +void record(const struct artnet::ArtDmx *pArtDmx, const uint32_t nMillis) { + const auto nDmxSlots = static_cast(((pArtDmx->LengthHi << 8) & 0xff00) | pArtDmx->Length); + ShowFileFormat::Get()->ShowfileWrite(pArtDmx->Data, nDmxSlots, pArtDmx->PortAddress, nMillis); +} + +void record([[maybe_unused]] const struct artnet::ArtSync *pArtSync, [[maybe_unused]] const uint32_t nMillis) { + // Nothng to do here +} +} // namespace showfile +#endif + +#if defined (CONFIG_SHOWFILE_PROTOCOL_NODE_E131) +#include "e131packets.h" + +namespace showfile { +void record(const struct TE131DataPacket *pE131DataPacket, const uint32_t nMillis) { + const auto *const pDmxData = &pE131DataPacket->DMPLayer.PropertyValues[1]; + const auto nLength = __builtin_bswap16(pE131DataPacket->DMPLayer.PropertyValueCount) - 1U; + const auto Universe = __builtin_bswap16(pE131DataPacket->FrameLayer.Universe); + ShowFileFormat::Get()->ShowfileWrite(pDmxData, nLength, Universe, nMillis); +} + +void record([[maybe_unused]] const struct TE131SynchronizationPacket *pE131SynchronizationPacke, [[maybe_unused]] const uint32_t nMillis) { + // Nothing to do here +} +} // namespace showfile +#endif diff --git a/lib-showfile/src/formats/ola/showfileformatola.cpp b/lib-showfile/src/formats/ola/showfileformatola.cpp new file mode 100644 index 00000000..63b91f83 --- /dev/null +++ b/lib-showfile/src/formats/ola/showfileformatola.cpp @@ -0,0 +1,143 @@ +/** + * @file showfileformatola.cpp + * + */ +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include +#include + +#include "formats/showfileformatola.h" +#include "showfile.h" + +#include "hardware.h" + +#include "debug.h" + +ShowFileFormat *ShowFileFormat::s_pThis; + +void ShowFileFormat::Run() { + if (m_OlaState != OlaState::TIME_WAITING) { + m_OlaParseCode = GetNextLine(); + + if (m_OlaParseCode == OlaParseCode::DMX) { + if (m_nDmxDataLength != 0) { + ShowFileProtocol::DmxOut(m_nUniverse, m_DmxData, m_nDmxDataLength); + } + } else if (m_OlaParseCode == OlaParseCode::TIME) { + if (m_nDelayMillis != 0) { + if (m_nDmxDataLength != 0) { + ShowFileProtocol::DmxSync(); + } + } + m_OlaState = OlaState::TIME_WAITING; + } else if (m_OlaParseCode == OlaParseCode::EOFILE) { + if (m_bDoLoop) { + fseek(m_pShowFile, 0L, SEEK_SET); + } else { + ShowFile::Get()->SetStatus(showfile::Status::ENDED); + } + } + } + + const auto nMillis = Hardware::Get()->Millis(); + + if ((nMillis - m_nLastMillis) >= m_nDelayMillis) { + m_nLastMillis = nMillis; + m_OlaState = OlaState::PARSING_DMX; + } +} + +ShowFileFormat::OlaParseCode ShowFileFormat::ParseDmxData(const char *pLine) { + char *p = const_cast(pLine); + int64_t k = 0; + uint32_t nLength = 0; + + while (isdigit(*p) == 1) { + k = k * 10 + *p - '0'; + + if (k > 255) { + DEBUG_EXIT + return OlaParseCode::FAILED; + } + + p++; + + if (*p == ',' || (isdigit(*p) == 0)) { + + if (nLength > 512) { + DEBUG_EXIT + return OlaParseCode::FAILED; + } + + m_DmxData[nLength] = static_cast(k); + + k = 0; + nLength++; + p++; + } + } + + m_nDmxDataLength = nLength; + + return OlaParseCode::DMX; +} + +ShowFileFormat::OlaParseCode ShowFileFormat::ParseLine(const char *pLine) { + char *p = const_cast(pLine); + int32_t k = 0; + + while (isdigit(*p) == 1) { + k = k * 10 + *p - '0'; + p++; + } + + if (k > static_cast((static_cast(~0)))) { + return OlaParseCode::FAILED; + } + + if (*p++ == ' ') { + m_nDelayMillis = 0; + m_nUniverse = static_cast(k); + return ParseDmxData(p); + } + + m_nDelayMillis = static_cast(k); + + return OlaParseCode::TIME; +} + +ShowFileFormat::OlaParseCode ShowFileFormat::GetNextLine() { + if (m_pShowFile != nullptr) { + if (fgets(m_buffer, (sizeof(m_buffer) - 1), m_pShowFile) != m_buffer) { + return OlaParseCode::EOFILE; + } + + if (isdigit(m_buffer[0])) { + return ParseLine(m_buffer); + } + } + + return OlaParseCode::FAILED; +} diff --git a/lib-showfile/src/json_delete.cpp b/lib-showfile/src/json_delete.cpp new file mode 100755 index 00000000..86700064 --- /dev/null +++ b/lib-showfile/src/json_delete.cpp @@ -0,0 +1,65 @@ +/** + * @file json_delete.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include + +#include "showfile.h" +#include "showfileconst.h" +#include "showfileparamsconst.h" + +#include "sscan.h" + +#include "debug.h" + +namespace remoteconfig { +namespace showfile { +void json_delete(const char *pBuffer, const uint32_t nBufferSize) { + DEBUG_ENTRY + + if (nBufferSize < sizeof("show=x")) { + DEBUG_EXIT + return; + } + + uint8_t nValue8; + + if (Sscan::Uint8(pBuffer, ShowFileParamsConst::SHOW, nValue8) == Sscan::OK) { + if (nValue8 <= ::showfile::FILE_MAX_NUMBER) { + ShowFile::Get()->DeleteShowFile(nValue8); + + DEBUG_EXIT + return; + } + + DEBUG_EXIT + return; + } + + DEBUG_EXIT +} +} // namespace showfile +} // namespace remoteconfig diff --git a/lib-showfile/src/json_get_directory.cpp b/lib-showfile/src/json_get_directory.cpp new file mode 100755 index 00000000..6d174c14 --- /dev/null +++ b/lib-showfile/src/json_get_directory.cpp @@ -0,0 +1,72 @@ +/** + * @file json_get_directory.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include +#include + +#include "showfile.h" + +namespace remoteconfig { +namespace showfile { + +uint32_t json_get_directory(char *pOutBuffer, const uint32_t nOutBufferSize) { + const auto nBufferSize = nOutBufferSize - 2U; + auto nLength = static_cast(snprintf(pOutBuffer, nBufferSize, "{\"shows\":[")); + + for (uint32_t nShowIndex = 0; nShowIndex < ShowFile::Get()->GetShows(); nShowIndex++) { + const auto nShow = ShowFile::Get()->GetPlayerShowFile(nShowIndex); + if (nShow >= 0) { + uint32_t nFileSize; + if (ShowFile::Get()->GetShowFileSize(static_cast(nShow), nFileSize)) { + const auto nSize = nBufferSize - nLength; + const auto nCharacters = static_cast(snprintf(&pOutBuffer[nLength], nSize, "{\"show\":%d,\"size\":%u},", nShow, nFileSize)); + + if (nCharacters > nSize) { + break; + } + + nLength+=nCharacters; + + if (nLength >= nBufferSize) { + break; + } + } + } + } + + if (pOutBuffer[nLength - 1] == ',') { + nLength--; + } + + pOutBuffer[nLength++] = ']'; + pOutBuffer[nLength++] = '}'; + + assert(nLength <= nOutBufferSize); + return nLength; +} +} // namespace showfile +} // namespace remoteconfig diff --git a/lib-showfile/src/json_status.cpp b/lib-showfile/src/json_status.cpp new file mode 100755 index 00000000..0eec9c86 --- /dev/null +++ b/lib-showfile/src/json_status.cpp @@ -0,0 +1,118 @@ +/** + * @file json_status.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include + +#include "showfile.h" +#include "showfileconst.h" +#include "showfileparamsconst.h" +#include "showfiledisplay.h" + +#include "readconfigfile.h" +#include "sscan.h" + +static void staticCallbackFunction([[maybe_unused]] void *p, const char *s) { + assert(p == nullptr); + assert(s != nullptr); + + uint8_t nValue8; + + if (Sscan::Uint8(s, ShowFileParamsConst::SHOW, nValue8) == Sscan::OK) { + if (nValue8 <= showfile::FILE_MAX_NUMBER) { + ShowFile::Get()->SetPlayerShowFileCurrent(nValue8); + } + return; + } + +#if !defined (CONFIG_SHOWFILE_DISABLE_RECORD) + if (Sscan::Uint8(s, "recorder", nValue8) == Sscan::OK) { + if (nValue8 <= showfile::FILE_MAX_NUMBER) { + ShowFile::Get()->SetRecorderShowFileCurrent(nValue8); + } + return; + } +#endif + + if (Sscan::Uint8(s, ShowFileParamsConst::OPTION_LOOP, nValue8) == Sscan::OK) { + ShowFile::Get()->DoLoop(nValue8 != 0); + return; + } + + char action[8]; + uint32_t nLength = sizeof(action) - 1; + + if (Sscan::Char(s, "status" , action, nLength) == Sscan::OK) { + if (strncmp(action, "play", nLength) == 0) { + ShowFile::Get()->Play(); + return; + } + + if (strncmp(action, "stop", nLength) == 0) { + ShowFile::Get()->Stop(); + return; + } + + if (strncmp(action, "resume", nLength) == 0) { + ShowFile::Get()->Resume(); + return; + } + +#if !defined (CONFIG_SHOWFILE_DISABLE_RECORD) + if (strncmp(action, "record", nLength) == 0) { + ShowFile::Get()->Record(); + return; + } +#endif + + return; + } +} + +namespace remoteconfig { +namespace showfile { +uint32_t json_get_status(char *pOutBuffer, const uint32_t nOutBufferSize) { + const auto status = ShowFile::Get()->GetStatus(); + assert(status != ::showfile::Status::UNDEFINED); + + const auto nLength = static_cast(snprintf(pOutBuffer, nOutBufferSize, + "{\"mode\":\"%s\",\"%s\":\"%u\",\"status\":\"%s\",\"%s\":\"%s\"}", + ShowFile::Get()->GetMode() == ::showfile::Mode::RECORDER ? "Recorder" : "Player", + ShowFileParamsConst::SHOW, + static_cast(ShowFile::Get()->GetShowFileCurrent()), + ::showfile::STATUS[static_cast(status)], + ShowFileParamsConst::OPTION_LOOP, + ShowFile::Get()->GetDoLoop() ? "1" : "0")); + return nLength; +} + +void json_set_status(const char *pBuffer, const uint32_t nBufferSize) { + ReadConfigFile config(staticCallbackFunction, nullptr); + config.Read(pBuffer, nBufferSize); + ::showfile::display_status(); +} +} // namespace showfile +} // namespace remoteconfig diff --git a/lib-showfile/src/osc/showfileosc.cpp b/lib-showfile/src/osc/showfileosc.cpp new file mode 100644 index 00000000..4e597bbc --- /dev/null +++ b/lib-showfile/src/osc/showfileosc.cpp @@ -0,0 +1,296 @@ +/** + * @file showfileosc.cpp + * + */ +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include +#include +#include + +#include "showfileosc.h" +#include "showfile.h" + +#include "oscsimplemessage.h" +#include "oscsimplesend.h" + +#include "network.h" + +#include "debug.h" + +namespace cmd { + static constexpr char START[] = "start"; + static constexpr char STOP[] = "stop"; + static constexpr char RESUME[] = "resume"; + static constexpr char SHOW[] = "show"; + static constexpr char LOOP[] = "loop"; + static constexpr char BO[] = "blackout"; +#if defined (CONFIG_SHOWFILE_ENABLE_MASTER) + static constexpr char MASTER[] = "master"; +#endif + static constexpr char TFTP[] = "tftp"; + static constexpr char DELETE[] = "delete"; + // TouchOSC specific + static constexpr char RELOAD[] = "reload"; + static constexpr char INDEX[] = "index"; +} + +namespace length { + static constexpr uint32_t START = sizeof(cmd::START) - 1; + static constexpr uint32_t STOP = sizeof(cmd::STOP) - 1; + static constexpr uint32_t RESUME = sizeof(cmd::RESUME) - 1; + static constexpr uint32_t SHOW = sizeof(cmd::SHOW) - 1; + static constexpr uint32_t LOOP = sizeof(cmd::LOOP) - 1; + static constexpr uint32_t BO = sizeof(cmd::BO) - 1; +#if defined (CONFIG_SHOWFILE_ENABLE_MASTER) + static constexpr uint32_t MASTER = sizeof(cmd::MASTER) - 1; +#endif + static constexpr uint32_t TFTP = sizeof(cmd::TFTP) - 1; + static constexpr uint32_t DELETE = sizeof(cmd::DELETE) - 1; + // TouchOSC specific + static constexpr uint32_t RELOAD = sizeof(cmd::RELOAD) - 1; + static constexpr uint32_t INDEX = sizeof(cmd::INDEX) - 1; +} + +ShowFileOSC::ShowFileOSC(uint16_t nPortIncoming, uint16_t nPortOutgoing) : m_nPortIncoming(nPortIncoming), m_nPortOutgoing(nPortOutgoing) { + DEBUG_ENTRY + + m_nHandle = Network::Get()->Begin(m_nPortIncoming); + assert(m_nHandle != -1); + + DEBUG_EXIT +} + +ShowFileOSC::~ShowFileOSC() { + DEBUG_ENTRY + + Network::Get()->End(m_nPortIncoming); + + DEBUG_EXIT +} + +void ShowFileOSC::Process() { + DEBUG_PRINTF("[%s] %d,%d %s", m_pBuffer, static_cast(strlen(m_pBuffer)), static_cast(length::PATH), &m_pBuffer[length::PATH]); + + if (memcmp(&m_pBuffer[length::PATH], cmd::START, length::START) == 0) { + ShowFile::Get()->Play(); + SendStatus(); + DEBUG_PUTS("ActionStart"); + return; + } + + if (memcmp(&m_pBuffer[length::PATH], cmd::STOP, length::STOP) == 0){ + ShowFile::Get()->Stop(); + SendStatus(); + DEBUG_PUTS("ActionStop"); + return; + } + + if (memcmp(&m_pBuffer[length::PATH], cmd::RESUME, length::RESUME) == 0) { + ShowFile::Get()->Resume(); + SendStatus(); + DEBUG_PUTS("ActionResume"); + return; + } + + if (memcmp(&m_pBuffer[length::PATH], cmd::SHOW, length::SHOW) == 0) { + OscSimpleMessage Msg(m_pBuffer, m_nBytesReceived); + + const auto nValue = static_cast(Msg.GetInt(0)); + + if (nValue <= showfile::FILE_MAX_NUMBER) { + ShowFile::Get()->SetPlayerShowFileCurrent(nValue); + SendStatus(); + } + + DEBUG_PRINTF("Show %d", nValue); + return; + } + + if (memcmp(&m_pBuffer[length::PATH], cmd::LOOP, length::LOOP) == 0) { + OscSimpleMessage Msg(m_pBuffer, m_nBytesReceived); + + int nValue; + + if (Msg.GetType(0) == osc::type::INT32) { + nValue = Msg.GetInt(0); + } else if (Msg.GetType(0) == osc::type::FLOAT) { // TouchOSC + nValue = static_cast(Msg.GetFloat(0)); + } else { + return; + } + + ShowFile::Get()->DoLoop(nValue != 0); + SendStatus(); + showfile::display_status(); + + DEBUG_PRINTF("Loop %d", nValue != 0); + return; + } + + if (memcmp(&m_pBuffer[length::PATH], cmd::BO, length::BO) == 0) { + ShowFile::Get()->BlackOut(); + SendStatus(); + DEBUG_PUTS("Blackout"); + return; + } + +#if defined (CONFIG_SHOWFILE_ENABLE_MASTER) + if (memcmp(&m_pBuffer[length::PATH], cmd::MASTER, length::MASTER) == 0) { + OscSimpleMessage Msg(m_pBuffer, m_nBytesReceived); + + int nValue; + + if (Msg.GetType(0) == osc::type::INT32) { + nValue = Msg.GetInt(0); + } else if (Msg.GetType(0) == osc::type::FLOAT) { // TouchOSC + nValue = static_cast(Msg.GetFloat(0)); + } else { + return; + } + + if ((nValue >= 0) && (nValue <= 255)) { + ShowFile::Get()->SetMaster(static_cast(nValue)); + } + + DEBUG_PRINTF("Master %d", nValue); + return; + } +#endif + + if (memcmp(&m_pBuffer[length::PATH], cmd::TFTP, length::TFTP) == 0) { + OscSimpleMessage Msg(m_pBuffer, m_nBytesReceived); + + int nValue; + + if (Msg.GetType(0) == osc::type::INT32) { + nValue = Msg.GetInt(0); + } else if (Msg.GetType(0) == osc::type::FLOAT) { // TouchOSC + nValue = static_cast(Msg.GetFloat(0)); + } else { + return; + } + + ShowFile::Get()->EnableTFTP(nValue != 0); + SendStatus(); + + DEBUG_PRINTF("TFTP %d", nValue != 0); + return; + } + + + if (memcmp(&m_pBuffer[length::PATH], cmd::DELETE, length::DELETE) == 0) { + OscSimpleMessage Msg(m_pBuffer, m_nBytesReceived); + + uint32_t nValue = 255; + + if (Msg.GetType(0) == osc::type::INT32){ + nValue = static_cast(Msg.GetInt(0)); + } else { + return; + } + + DEBUG_PRINTF("nValue=%d", nValue); + + if (nValue <= showfile::FILE_MAX_NUMBER) { + char aShowFileName[showfile::FILE_NAME_LENGTH + 1]; + + showfile::filename_copyto(aShowFileName, sizeof(aShowFileName), nValue); + + OscSimpleSend MsgName(m_nHandle, m_nRemoteIp, m_nPortOutgoing, "/showfile/name", "s", aShowFileName); + + if (ShowFile::Get()->DeleteShowFile(nValue)) { + OscSimpleSend MsgStatus(m_nHandle, m_nRemoteIp, m_nPortOutgoing, "/showfile/status", "s", "Deleted"); + } else { + OscSimpleSend MsgStatus(m_nHandle, m_nRemoteIp, m_nPortOutgoing, "/showfile/status", "s", "Not deleted"); + } + } + + DEBUG_PRINTF("Delete %d", nValue); + return; + } + + if (memcmp(&m_pBuffer[length::PATH], cmd::INDEX, length::INDEX) == 0) { + OscSimpleMessage Msg(m_pBuffer, m_nBytesReceived); + + if (Msg.GetType(0) != osc::type::FLOAT){ + return; + } + + const auto nIndex = static_cast(Msg.GetFloat(0)); + + DEBUG_PRINTF("Index %u", nIndex); + + const auto nShow = ShowFile::Get()->GetPlayerShowFile(nIndex); + + if (nShow < 0) { + return; + } + + DEBUG_PRINTF("nShow %d", nShow); + + ShowFile::Get()->SetPlayerShowFileCurrent(static_cast(nShow)); + SendStatus(); + + return; + } + + // TouchOSC + if (memcmp(&m_pBuffer[length::PATH], cmd::RELOAD, length::RELOAD) == 0) { + ShowFiles(); + DEBUG_PUTS("Reload"); + return; + } +} + +// TouchOSC +void ShowFileOSC::SendStatus() { + OscSimpleSend MsgName(m_nHandle, m_nRemoteIp, m_nPortOutgoing, "/showfile/name", "s", ShowFile::Get()->GetShowFileNameCurrent()); + + const auto status = ShowFile::Get()->GetStatus(); + assert(status != showfile::Status::UNDEFINED); + + OscSimpleSend MsgStatus(m_nHandle, m_nRemoteIp, m_nPortOutgoing, "/showfile/status", "s", showfile::STATUS[static_cast(status)]); +} + +// TouchOSC +void ShowFileOSC::ShowFiles() { + char aPath[64]; + char aValue[4]; + + uint32_t i; + + for (i = 0; i < ShowFile::Get()->GetShows(); i++) { + snprintf(aPath, sizeof(aPath) - 1, "/showfile/%u/show", static_cast(i)); + snprintf(aValue, sizeof(aValue) - 1, "%.2u", static_cast(ShowFile::Get()->GetPlayerShowFile(i))); + OscSimpleSend MsgStatus(m_nHandle, m_nRemoteIp, m_nPortOutgoing, aPath, "s", aValue); + } + + for (; i < ShowFileOSCMax::FILES_ENTRIES; i++) { + snprintf(aPath, sizeof(aPath) - 1, "/showfile/%u/show", static_cast(i)); + OscSimpleSend MsgStatus(m_nHandle, m_nRemoteIp, m_nPortOutgoing, aPath, "s", " "); + } + + SendStatus(); +} diff --git a/lib-showfile/src/protocols/artnet/showfileprotocolartnettrigger.cpp b/lib-showfile/src/protocols/artnet/showfileprotocolartnettrigger.cpp new file mode 100755 index 00000000..845df047 --- /dev/null +++ b/lib-showfile/src/protocols/artnet/showfileprotocolartnettrigger.cpp @@ -0,0 +1,59 @@ +/** + * @file showfileprotocolartnettrigger.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "protocols/showfileprotocolartnettrigger.h" +#include "showfile.h" + +#include "debug.h" + +void ShowFileProtocolArtNetTrigger::Handler(const struct TArtNetTrigger *ptArtNetTrigger) { + DEBUG_ENTRY + DEBUG_PRINTF("Key=%d, SubKey=%d", ptArtNetTrigger->Key, ptArtNetTrigger->SubKey); + + if (ptArtNetTrigger->Key == ART_TRIGGER_KEY_SOFT) { + switch (ptArtNetTrigger->SubKey) { + case 'B': + ShowFile::Get()->BlackOut(); + break; + case 'G': + ShowFile::Get()->Play(); + break; + case 'R': + ShowFile::Get()->Resume(); + break; + case 'S': + ShowFile::Get()->Stop(); + break; + default: + break; + } + } + + if (ptArtNetTrigger->Key == ART_TRIGGER_KEY_SHOW) { + ShowFile::Get()->SetPlayerShowFileCurrent(ptArtNetTrigger->SubKey); + } + + DEBUG_EXIT +} diff --git a/lib-showfile/src/showfile.cpp b/lib-showfile/src/showfile.cpp new file mode 100644 index 00000000..af0af912 --- /dev/null +++ b/lib-showfile/src/showfile.cpp @@ -0,0 +1,338 @@ +/** + * @file showfile.cpp + * + */ +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include +#include + +#include "showfile.h" +#include "showfiletftp.h" +#include "showfiledisplay.h" + +#if defined CONFIG_USB_HOST_MSC +# include "device/usb/host.h" +#endif + +#include "hardware.h" + +#include "debug.h" + +ShowFile *ShowFile::s_pThis; + +#if defined (CONFIG_SHOWFILE_ENABLE_OSC) +ShowFile::ShowFile(uint16_t nPortIncoming, uint16_t nPortOutgoing): m_showFileOSC(nPortIncoming, nPortOutgoing) { +#else +ShowFile::ShowFile() { +#endif + DEBUG_ENTRY + + assert(s_pThis == nullptr); + s_pThis = this; + + m_aShowFileNameCurrent[0] = '\0'; + + DEBUG_EXIT +} + +void ShowFile::OpenFile(const showfile::Mode mode, const uint32_t nShowFileNumber) { + DEBUG_ENTRY + + if (showfile::filename_copyto(m_aShowFileNameCurrent, sizeof(m_aShowFileNameCurrent), nShowFileNumber)) { +#if defined CONFIG_USB_HOST_MSC + if (usb::host::get_status() != usb::host::Status::READY) { + DEBUG_EXIT + return; + } +#endif + + if (m_pShowFile != nullptr) { + if (fclose(m_pShowFile) != 0) { + perror("fclose()"); + } + m_pShowFile = nullptr; + } + + m_pShowFile = fopen(m_aShowFileNameCurrent, mode == showfile::Mode::RECORDER ? "w" : "r"); + + if (m_pShowFile == nullptr) { + perror(const_cast(m_aShowFileNameCurrent)); + m_aShowFileNameCurrent[0] = '\0'; + } else { + m_nShowFileCurrent = nShowFileNumber; + m_Mode = mode; + } + + showfile::display_filename(m_aShowFileNameCurrent, m_nShowFileCurrent); + showfile::display_status(); + + DEBUG_EXIT + return; + } + + DEBUG_EXIT + return; +} + +void ShowFile::SetPlayerShowFileCurrent(const uint32_t nShowFileNumber) { + DEBUG_ENTRY + if (m_Status != showfile::Status::IDLE) { + DEBUG_EXIT + return; + } + + DEBUG_PRINTF("nShowFileNumber=%u", nShowFileNumber); + + OpenFile(showfile::Mode::PLAYER, nShowFileNumber); + + DEBUG_EXIT +} + +#if !defined (CONFIG_SHOWFILE_DISABLE_RECORD) +void ShowFile::SetRecorderShowFileCurrent(const uint32_t nShowFileNumber) { + DEBUG_ENTRY + + if (m_Status != showfile::Status::IDLE) { + DEBUG_EXIT + return; + } + + DEBUG_PRINTF("nShowFileNumber=%u", nShowFileNumber); + + if (AddShow(nShowFileNumber)) { + OpenFile(showfile::Mode::RECORDER, nShowFileNumber); + + DEBUG_EXIT + return; + } + + DEBUG_EXIT +} +#endif + +bool ShowFile::DeleteShowFile(const uint32_t nShowFileNumber) { + DEBUG_ENTRY + DEBUG_PRINTF("nShowFileNumber=%u", nShowFileNumber); + + char aFileName[showfile::FILE_NAME_LENGTH + 1U]; + + if (showfile::filename_copyto(aFileName, sizeof(aFileName), nShowFileNumber)) { + if (nShowFileNumber == m_nShowFileCurrent) { + if (fclose(m_pShowFile) != 0) { + perror("fclose()"); + } + m_pShowFile = nullptr; + m_nShowFileCurrent = -1; + } + const auto nResult = unlink(aFileName); + DEBUG_PRINTF("nResult=%d", nResult); + DEBUG_EXIT + return (nResult == 0); + } + + DEBUG_EXIT + return false; +} + +bool ShowFile::GetShowFileSize(const uint32_t nShowFileNumber, uint32_t &nSize) { + DEBUG_ENTRY + DEBUG_PRINTF("nShowFileNumber=%u", nShowFileNumber); + + char aFileName[showfile::FILE_NAME_LENGTH + 1U]; + + if (showfile::filename_copyto(aFileName, sizeof(aFileName), nShowFileNumber)) { + auto *pFile = fopen(aFileName, "r"); + if (pFile != nullptr) { + if (fseek(pFile, 0L, SEEK_END) == 0) { + nSize = ftell(pFile); + fclose(pFile); + DEBUG_PRINTF("nSize=%u", nSize); + DEBUG_EXIT + return true; + } + } else { + perror("fopen()"); + } + } + + DEBUG_EXIT + return false; +} + +bool ShowFile::AddShow(const uint32_t nShowFileNumber) { + DEBUG_ENTRY + + if (m_nShows == (showfile::FILE_MAX_NUMBER)) { + DEBUG_EXIT + return false; + } + + if (m_nShows == 0) { + m_nShowFileNumber[0] = static_cast(nShowFileNumber); + } else { + for (auto &Show : m_nShowFileNumber) { + if (Show == static_cast(nShowFileNumber)) { + DEBUG_EXIT + return true; + } + } + + int32_t i = m_nShows - 1; + while ((static_cast(nShowFileNumber) < m_nShowFileNumber[i]) && i >= 0) { + m_nShowFileNumber[i + 1] = m_nShowFileNumber[i]; + i--; + } + + m_nShowFileNumber[i + 1] = static_cast(nShowFileNumber); + } + + m_nShows++; + + DEBUG_EXIT + return true; +} + +void ShowFile::LoadShows() { + DEBUG_ENTRY + +#if defined (CONFIG_USB_HOST_MSC) + auto *dirp = opendir("0:/"); +#else + auto *dirp = opendir("."); +#endif + + if (dirp == nullptr) { + perror("opendir"); + DEBUG_EXIT + return; + } + + for (auto &FileIndex : m_nShowFileNumber) { + FileIndex = -1; + } + + m_nShows = 0; + + struct dirent *dp; + + do { + if ((dp = readdir(dirp)) != nullptr) { + if (dp->d_type == DT_DIR) { + continue; + } + + uint32_t nShowFileNumber; + if (!showfile::filename_check(dp->d_name, nShowFileNumber)) { + continue; + } + + DEBUG_PRINTF("Found %s", dp->d_name); + + if (!AddShow(nShowFileNumber)) { + break; + } + } + } while (dp != nullptr); + + closedir(dirp); + + DEBUG_EXIT +} + +void ShowFile::EnableTFTP([[maybe_unused]] bool bEnableTFTP) { + DEBUG_ENTRY + +#if !defined(CONFIG_SHOWFILE_DISABLE_TFTP) + if (bEnableTFTP == m_bEnableTFTP) { + DEBUG_EXIT + return; + } + + m_bEnableTFTP = bEnableTFTP; + + if (m_bEnableTFTP) { + assert(m_pShowFileTFTP == nullptr); + + Stop(); + + if (m_pShowFile != nullptr) { + if (fclose(m_pShowFile) != 0) { + perror("fclose(m_pShowFile)"); + } + m_pShowFile = nullptr; + } + + m_pShowFileTFTP = new ShowFileTFTP; + assert(m_pShowFileTFTP != nullptr); + } else { + assert(m_pShowFileTFTP != nullptr); + + delete m_pShowFileTFTP; + m_pShowFileTFTP = nullptr; + + LoadShows(); + SetPlayerShowFileCurrent(m_nShowFileCurrent); + SetStatus(showfile::Status::IDLE); + } + + showfile::display_status(); +#endif + + DEBUG_EXIT +} + +void ShowFile::SetStatus(const showfile::Status Status) { + DEBUG_ENTRY + + if (Status == m_Status) { + DEBUG_EXIT + return; + } + + m_Status = Status; + + switch (m_Status) { + case showfile::Status::IDLE: + ShowFileFormat::DoRunCleanupProcess(true); + Hardware::Get()->SetMode(hardware::ledblink::Mode::NORMAL); + break; + case showfile::Status::PLAYING: + case showfile::Status::RECORDING: + ShowFileFormat::DoRunCleanupProcess(false); + Hardware::Get()->SetMode(hardware::ledblink::Mode::DATA); + break; + case showfile::Status::STOPPED: + case showfile::Status::ENDED: + ShowFileFormat::DoRunCleanupProcess(true); + Hardware::Get()->SetMode(hardware::ledblink::Mode::NORMAL); + break; + default: + break; + } + + showfile::display_status(); + + DEBUG_EXIT +} diff --git a/lib-showfile/src/showfile_filename.cpp b/lib-showfile/src/showfile_filename.cpp new file mode 100755 index 00000000..7059402b --- /dev/null +++ b/lib-showfile/src/showfile_filename.cpp @@ -0,0 +1,91 @@ +/** + * @file showfile_filename.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include +#include +#include +#include + +#include "showfile.h" + +#include "debug.h" + +namespace showfile { +bool filename_copyto(char *pShowFileName, const uint32_t nLength, const uint32_t nShowFileNumber) { + assert(nLength == showfile::FILE_NAME_LENGTH + 1); + + if (nShowFileNumber <= showfile::FILE_MAX_NUMBER) { + snprintf(pShowFileName, nLength, "show%.2u.txt", static_cast(nShowFileNumber)); + return true; + } + + return false; +} + +bool filename_check(const char *pShowFileName, uint32_t &nShowFileNumber) { + DEBUG_PRINTF("pShowFileName=[%s]", pShowFileName); + + if ((pShowFileName == nullptr) || (strlen(pShowFileName) != showfile::FILE_NAME_LENGTH)) { + DEBUG_EXIT + return false; + } + + if (memcmp(pShowFileName, SHOWFILE_PREFIX, sizeof(SHOWFILE_PREFIX) - 1) != 0) { + DEBUG_EXIT + return false; + } + + if (memcmp(&pShowFileName[showfile::FILE_NAME_LENGTH - sizeof(SHOWFILE_SUFFIX) + 1], SHOWFILE_SUFFIX, sizeof(SHOWFILE_SUFFIX) - 1) != 0) { + DEBUG_EXIT + return false; + } + + char cDigit = pShowFileName[sizeof(SHOWFILE_PREFIX) - 1]; + DEBUG_PRINTF("cDigit=%c", cDigit); + + if (!isdigit(cDigit)) { + DEBUG_EXIT + return false; + } + + nShowFileNumber = static_cast(10 * (cDigit - '0')); + + cDigit = pShowFileName[sizeof(SHOWFILE_PREFIX)]; + DEBUG_PRINTF("cDigit=%c", cDigit); + + if (!isdigit(cDigit)) { + DEBUG_EXIT + return false; + } + + nShowFileNumber += static_cast(cDigit - '0'); + + DEBUG_EXIT + return true; +} + + +} // namespace showfile diff --git a/lib-showfile/src/showfileparams.cpp b/lib-showfile/src/showfileparams.cpp new file mode 100644 index 00000000..c4b73eb8 --- /dev/null +++ b/lib-showfile/src/showfileparams.cpp @@ -0,0 +1,389 @@ +/** + * @file showfileparams.cpp + * + */ +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#if !defined(__clang__) // Needed for compiling on MacOS + #pragma GCC push_options + #pragma GCC optimize ("Os") +#endif + +#include +#include +#ifndef NDEBUG +# include +#endif +#include + +#include "showfileparams.h" +#include "showfileparamsconst.h" +#include "showfile.h" +#if defined (CONFIG_SHOWFILE_ENABLE_OSC) +# include "showfileosc.h" +# include "osc.h" +# include "oscparamsconst.h" +#endif + +#include "readconfigfile.h" +#include "sscan.h" +#include "propertiesbuilder.h" + +// Protocols +#if !defined (CONFIG_SHOWFILE_PROTOCOL_INTERNAL) +# if defined (CONFIG_SHOWFILE_PROTOCOL_E131) +# include "e131controller.h" +# endif +# if defined (CONFIG_SHOWFILE_PROTOCOL_ARTNET) +# include "artnetcontroller.h" +# endif +#endif + +#include "debug.h" + +ShowFileParams::ShowFileParams() { + DEBUG_ENTRY + + memset(&m_Params, 0, sizeof(m_Params)); + +#if defined (CONFIG_SHOWFILE_ENABLE_OSC) + m_Params.nOscPortIncoming = osc::port::DEFAULT_INCOMING; + m_Params.nOscPortOutgoing = osc::port::DEFAULT_OUTGOING; +#endif +#if !defined (CONFIG_SHOWFILE_PROTOCOL_INTERNAL) +# if defined (CONFIG_SHOWFILE_PROTOCOL_E131) + m_Params.nUniverse = DEFAULT_SYNCHRONIZATION_ADDRESS; +# else +# endif +#else +#endif + m_Params.nDmxMaster = UINT8_MAX; + + DEBUG_EXIT +} + +void ShowFileParams::Load() { + DEBUG_ENTRY + + m_Params.nSetList = 0; + +#if !defined(DISABLE_FS) + ReadConfigFile configfile(ShowFileParams::staticCallbackFunction, this); + + if (configfile.Read(ShowFileParamsConst::FILE_NAME)) { + ShowFileParamsStore::Update(&m_Params); + } else +#endif + ShowFileParamsStore::Copy(&m_Params); + +#ifndef NDEBUG + Dump(); +#endif + DEBUG_EXIT +} + +void ShowFileParams::Load(const char *pBuffer, uint32_t nLength) { + DEBUG_ENTRY + + assert(pBuffer != nullptr); + assert(nLength != 0); + + m_Params.nSetList = 0; + + ReadConfigFile config(ShowFileParams::staticCallbackFunction, this); + + config.Read(pBuffer, nLength); + + ShowFileParamsStore::Update(&m_Params); + +#ifndef NDEBUG + Dump(); +#endif + DEBUG_EXIT +} + +void ShowFileParams::SetBool(const uint8_t nValue, const uint32_t nMask) { + if (nValue != 0) { + m_Params.nSetList |= nMask; + } else { + m_Params.nSetList &= ~nMask; + } +} + +void ShowFileParams::callbackFunction(const char *pLine) { + assert(pLine != nullptr); + +#if defined (CONFIG_SHOWFILE_ENABLE_OSC) + uint16_t nValue16; + + if (Sscan::Uint16(pLine, OscParamsConst::INCOMING_PORT, nValue16) == Sscan::OK) { + if ((nValue16 != osc::port::DEFAULT_INCOMING) && (nValue16 > 1023)) { + m_Params.nOscPortIncoming = nValue16; + m_Params.nSetList |= showfileparams::Mask::OSC_PORT_INCOMING; + } else { + m_Params.nOscPortIncoming = osc::port::DEFAULT_INCOMING; + m_Params.nSetList &= ~showfileparams::Mask::OSC_PORT_INCOMING; + } + return; + } + + if (Sscan::Uint16(pLine, OscParamsConst::OUTGOING_PORT, nValue16) == Sscan::OK) { + if ((nValue16 != osc::port::DEFAULT_OUTGOING) && (nValue16 > 1023)) { + m_Params.nOscPortOutgoing = nValue16; + m_Params.nSetList |= showfileparams::Mask::OSC_PORT_OUTGOING; + } else { + m_Params.nOscPortOutgoing = osc::port::DEFAULT_OUTGOING; + m_Params.nSetList &= ~showfileparams::Mask::OSC_PORT_OUTGOING; + } + return; + } +#endif + + uint8_t nValue8; + + if (Sscan::Uint8(pLine, ShowFileParamsConst::SHOW, nValue8) == Sscan::OK) { + if (nValue8 < showfile::FILE_MAX_NUMBER) { + m_Params.nShow = nValue8; + m_Params.nSetList |= showfileparams::Mask::SHOW; + } else { + m_Params.nShow = 0; + m_Params.nSetList &= ~showfileparams::Mask::SHOW; + } + return; + } + +#if !defined (CONFIG_SHOWFILE_PROTOCOL_INTERNAL) +# if defined (CONFIG_SHOWFILE_PROTOCOL_E131) + if (Sscan::Uint16(pLine, ShowFileParamsConst::SACN_SYNC_UNIVERSE, nValue16) == Sscan::OK) { + if (nValue16 > e131::universe::MAX) { + m_Params.nUniverse = DEFAULT_SYNCHRONIZATION_ADDRESS; + m_Params.nSetList &= ~showfileparams::Mask::SACN_UNIVERSE; + } else { + m_Params.nUniverse = nValue16; + m_Params.nSetList |= showfileparams::Mask::SACN_UNIVERSE; + } + return; + } +# endif +# if defined (CONFIG_SHOWFILE_PROTOCOL_ARTNET) + if (Sscan::Uint8(pLine, ShowFileParamsConst::ARTNET_DISABLE_UNICAST, nValue8) == Sscan::OK) { + if (nValue8 != 0) { + m_Params.nDisableUnicast = 1; + m_Params.nSetList |= showfileparams::Mask::ARTNET_UNICAST_DISABLED; + } else { + m_Params.nDisableUnicast = 0; + m_Params.nSetList &= ~showfileparams::Mask::ARTNET_UNICAST_DISABLED; + } + return; + } +# endif +#endif + +#if defined (CONFIG_SHOWFILE_ENABLE_MASTER) + if (Sscan::Uint8(pLine, ShowFileParamsConst::DMX_MASTER, nValue8) == Sscan::OK) { + if (nValue8 < UINT8_MAX) { + m_Params.nDmxMaster = nValue8; + m_Params.nSetList |= showfileparams::Mask::DMX_MASTER; + } else { + m_Params.nDmxMaster = UINT8_MAX; + m_Params.nSetList &= ~showfileparams::Mask::DMX_MASTER; + } + return; + } +#endif + + if (Sscan::Uint8(pLine, ShowFileParamsConst::OPTION_AUTO_PLAY, nValue8) == Sscan::OK) { + SetBool(nValue8, showfileparams::Mask::OPTION_AUTO_PLAY); + return; + } + + if (Sscan::Uint8(pLine, ShowFileParamsConst::OPTION_LOOP, nValue8) == Sscan::OK) { + SetBool(nValue8, showfileparams::Mask::OPTION_LOOP); + return; + } + + if (Sscan::Uint8(pLine, ShowFileParamsConst::OPTION_DISABLE_SYNC, nValue8) == Sscan::OK) { + SetBool(nValue8, showfileparams::Mask::OPTION_DISABLE_SYNC); + return; + } +} + +void ShowFileParams::Builder(const struct TShowFileParams *ptShowFileParamss, char *pBuffer, uint32_t nLength, uint32_t& nSize) { + DEBUG_ENTRY + + if (ptShowFileParamss != nullptr) { + memcpy(&m_Params, ptShowFileParamss, sizeof(struct showfileparams::Params)); + } else { + ShowFileParamsStore::Copy(&m_Params); + } + + PropertiesBuilder builder(ShowFileParamsConst::FILE_NAME, pBuffer, nLength); + + builder.Add(ShowFileParamsConst::SHOW, static_cast(m_Params.nShow), isMaskSet(showfileparams::Mask::SHOW)); + +#if defined (CONFIG_SHOWFILE_ENABLE_MASTER) + builder.AddComment("Pixel"); + builder.Add(ShowFileParamsConst::DMX_MASTER, static_cast(m_Params.nDmxMaster), isMaskSet(showfileparams::Mask::DMX_MASTER)); +#endif + +#if !defined (CONFIG_SHOWFILE_PROTOCOL_INTERNAL) +# if defined (CONFIG_SHOWFILE_PROTOCOL_E131) + builder.AddComment("sACN"); + builder.Add(ShowFileParamsConst::SACN_SYNC_UNIVERSE, static_cast(m_Params.nUniverse), isMaskSet(showfileparams::Mask::SACN_UNIVERSE)); +# endif +# if defined (CONFIG_SHOWFILE_PROTOCOL_ARTNET) + builder.AddComment("Art-Net"); + builder.Add(ShowFileParamsConst::ARTNET_DISABLE_UNICAST, static_cast(m_Params.nDisableUnicast), isMaskSet(showfileparams::Mask::ARTNET_UNICAST_DISABLED)); +# endif +#endif + + builder.AddComment("Options"); + builder.Add(ShowFileParamsConst::OPTION_AUTO_PLAY, isMaskSet(showfileparams::Mask::OPTION_AUTO_PLAY), isMaskSet(showfileparams::Mask::OPTION_AUTO_PLAY)); + builder.Add(ShowFileParamsConst::OPTION_LOOP, isMaskSet(showfileparams::Mask::OPTION_LOOP), isMaskSet(showfileparams::Mask::OPTION_LOOP)); +#if !defined (CONFIG_SHOWFILE_PROTOCOL_INTERNAL) + builder.Add(ShowFileParamsConst::OPTION_DISABLE_SYNC, isMaskSet(showfileparams::Mask::OPTION_DISABLE_SYNC), isMaskSet(showfileparams::Mask::OPTION_DISABLE_SYNC)); +#endif + +#if defined (CONFIG_SHOWFILE_ENABLE_OSC) + builder.AddComment("OSC Server"); + builder.Add(OscParamsConst::INCOMING_PORT, static_cast(m_Params.nOscPortIncoming), isMaskSet(showfileparams::Mask::OSC_PORT_INCOMING)); + builder.Add(OscParamsConst::OUTGOING_PORT, static_cast(m_Params.nOscPortOutgoing), isMaskSet(showfileparams::Mask::OSC_PORT_OUTGOING)); +#endif + + nSize = builder.GetSize(); + + DEBUG_EXIT +} + +void ShowFileParams::Set() { + DEBUG_ENTRY + + if (isMaskSet(showfileparams::Mask::SHOW)) { + ShowFile::Get()->SetPlayerShowFileCurrent(m_Params.nShow); + } + +#if defined (CONFIG_SHOWFILE_ENABLE_MASTER) + if (isMaskSet(showfileparams::Mask::DMX_MASTER)) { + ShowFile::Get()->SetMaster(m_Params.nDmxMaster); + } +#endif + +#if defined (CONFIG_SHOWFILE_ENABLE_OSC) + if (isMaskSet(showfileparams::Mask::OSC_PORT_INCOMING)) { + ShowFile::Get()->SetOscPortIncoming(m_Params.nOscPortIncoming); + } + + if (isMaskSet(showfileparams::Mask::OSC_PORT_OUTGOING)) { + ShowFile::Get()->SetOscPortOutgoing(m_Params.nOscPortOutgoing); + } +#endif + +#if !defined (CONFIG_SHOWFILE_PROTOCOL_INTERNAL) +# if defined (CONFIG_SHOWFILE_PROTOCOL_E131) + if (isMaskSet(showfileparams::Mask::SACN_UNIVERSE)) { + if (E131Controller::Get() != nullptr) { + E131Controller::Get()->SetSynchronizationAddress(m_Params.nUniverse); + } + } +# endif +# if defined (CONFIG_SHOWFILE_PROTOCOL_ARTNET) + if (isMaskSet(showfileparams::Mask::ARTNET_UNICAST_DISABLED)) { + if (ArtNetController::Get() != nullptr) { + ArtNetController::Get()->SetUnicast(false); + } + } +# endif +#endif + + // Options + + if (isMaskSet(showfileparams::Mask::OPTION_AUTO_PLAY)) { + ShowFile::Get()->SetAutoStart(true); + } + + if (isMaskSet(showfileparams::Mask::OPTION_LOOP)) { + ShowFile::Get()->DoLoop(true); + } + +#if !defined (CONFIG_SHOWFILE_PROTOCOL_INTERNAL) + if (isMaskSet(showfileparams::Mask::OPTION_DISABLE_SYNC)) { +# if defined (CONFIG_SHOWFILE_PROTOCOL_E131) + if (E131Controller::Get() != nullptr) { + E131Controller::Get()->SetSynchronizationAddress(0); + } +# endif +# if defined (CONFIG_SHOWFILE_PROTOCOL_ARTNET) + if (ArtNetController::Get() != nullptr) { + ArtNetController::Get()->SetSynchronization(false); + } +# endif + } +#endif + + DEBUG_EXIT +} + +void ShowFileParams::staticCallbackFunction(void *p, const char *s) { + assert(p != nullptr); + assert(s != nullptr); + + (static_cast(p))->callbackFunction(s); +} + +void ShowFileParams::Dump() { + printf("%s::%s \'%s\':\n", __FILE__, __FUNCTION__, ShowFileParamsConst::FILE_NAME); + printf(" %s=%u\n", ShowFileParamsConst::SHOW, m_Params.nShow); + +#if defined (CONFIG_SHOWFILE_ENABLE_MASTER) + printf(" %s=%u\n", ShowFileParamsConst::DMX_MASTER, m_Params.nDmxMaster); +#endif + +#if !defined (CONFIG_SHOWFILE_PROTOCOL_INTERNAL) +# if defined (CONFIG_SHOWFILE_PROTOCOL_E131) + if (isMaskSet(showfileparams::Mask::SACN_UNIVERSE)) { + printf(" %s=%u\n", ShowFileParamsConst::SACN_SYNC_UNIVERSE, m_Params.nUniverse); + } +# endif +# if defined (CONFIG_SHOWFILE_PROTOCOL_ARTNET) + if (isMaskSet(showfileparams::Mask::ARTNET_UNICAST_DISABLED)) { + printf(" %s=%u [%s]\n", ShowFileParamsConst::ARTNET_DISABLE_UNICAST, m_Params.nDisableUnicast, m_Params.nDisableUnicast == 0 ? "No" : "Yes"); + } +# endif +#endif + + if (isMaskSet(showfileparams::Mask::OPTION_AUTO_PLAY)) { + printf(" Auto start is enabled\n"); + } + + if (isMaskSet(showfileparams::Mask::OPTION_LOOP)) { + printf(" Loop is enabled\n"); + } +#if !defined (CONFIG_SHOWFILE_PROTOCOL_INTERNAL) + if (isMaskSet(showfileparams::Mask::OPTION_DISABLE_SYNC)) { + printf(" Synchronization is disabled\n"); + } +#endif +#if defined (CONFIG_SHOWFILE_ENABLE_OSC) + printf(" %s=%u\n", OscParamsConst::INCOMING_PORT, m_Params.nOscPortIncoming); + printf(" %s=%u\n", OscParamsConst::OUTGOING_PORT, m_Params.nOscPortOutgoing); +#endif +} diff --git a/lib-configstore/src/e131/storee131.cpp b/lib-showfile/src/showfileparamsconst.cpp similarity index 63% rename from lib-configstore/src/e131/storee131.cpp rename to lib-showfile/src/showfileparamsconst.cpp index 718153d5..00c17a47 100644 --- a/lib-configstore/src/e131/storee131.cpp +++ b/lib-showfile/src/showfileparamsconst.cpp @@ -1,8 +1,8 @@ /** - * @file storee131.cpp + * @file showfileparamsconst.cpp * */ -/* Copyright (C) 2018-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,19 +23,17 @@ * THE SOFTWARE. */ -#include +#include "showfileparamsconst.h" -#include "storee131.h" -#include "debug.h" +const char ShowFileParamsConst::FILE_NAME[] = "show.txt"; -StoreE131 *StoreE131::s_pThis; +const char ShowFileParamsConst::SHOW[] = "show"; -StoreE131::StoreE131() { - DEBUG_ENTRY +const char ShowFileParamsConst::DMX_MASTER[] = "dmx_master"; - assert(s_pThis == nullptr); - s_pThis = this; +const char ShowFileParamsConst::OPTION_AUTO_PLAY[] = "auto_play"; +const char ShowFileParamsConst::OPTION_LOOP[] = "loop"; +const char ShowFileParamsConst::OPTION_DISABLE_SYNC[] = "disable_sync"; - DEBUG_PRINTF("%p", reinterpret_cast(s_pThis)); - DEBUG_EXIT -} +const char ShowFileParamsConst::SACN_SYNC_UNIVERSE[] = "sync_universe"; +const char ShowFileParamsConst::ARTNET_DISABLE_UNICAST[] = "disable_unicast"; diff --git a/lib-showfile/src/showfiletftp.cpp b/lib-showfile/src/showfiletftp.cpp new file mode 100644 index 00000000..ddb4f377 --- /dev/null +++ b/lib-showfile/src/showfiletftp.cpp @@ -0,0 +1,65 @@ +/** + * @file showfiletftp.cpp + * + */ +/* Copyright (C) 2020-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#include "showfiletftp.h" +#include "showfile.h" + +#include "debug.h" + +void ShowFileTFTP::Exit() { + DEBUG_ENTRY + + ShowFile::Get()->EnableTFTP(false); + + DEBUG_EXIT +} + +bool ShowFileTFTP::FileOpen(const char *pFileName, [[maybe_unused]] tftp::Mode mode) { + DEBUG_PRINTF("pFileName=%s, mode=%d", pFileName, static_cast(mode)); + + uint32_t nShowFileNumber; + if (!showfile::filename_check(pFileName, nShowFileNumber)) { + DEBUG_EXIT + return false; + } + + m_pFile = fopen(pFileName, "r"); + return (m_pFile != nullptr); +} + +bool ShowFileTFTP::FileCreate(const char *pFileName, [[maybe_unused]] tftp::Mode mode) { + DEBUG_PRINTF("pFileName=%s, mode=%d", pFileName, static_cast(mode)); + + uint32_t nShowFileNumber; + if (!showfile::filename_check(pFileName, nShowFileNumber)) { + DEBUG_EXIT + return false; + } + + m_pFile = fopen(pFileName, "w+"); + return (m_pFile != nullptr); +} diff --git a/lib-uuid/.cproject b/lib-uuid/.cproject deleted file mode 100644 index 679fa1fe..00000000 --- a/lib-uuid/.cproject +++ /dev/null @@ -1,126 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/lib-uuid/.settings/language.settings.xml b/lib-uuid/.settings/language.settings.xml deleted file mode 100644 index d37297d8..00000000 --- a/lib-uuid/.settings/language.settings.xml +++ /dev/null @@ -1,12 +0,0 @@ - - - - - - - - - - - - \ No newline at end of file diff --git a/lib-uuid/.settings/org.eclipse.core.resources.prefs b/lib-uuid/.settings/org.eclipse.core.resources.prefs deleted file mode 100644 index 99f26c02..00000000 --- a/lib-uuid/.settings/org.eclipse.core.resources.prefs +++ /dev/null @@ -1,2 +0,0 @@ -eclipse.preferences.version=1 -encoding/=UTF-8 diff --git a/lib-uuid/Makefile.GD32 b/lib-uuid/Makefile.GD32 deleted file mode 100644 index 61d90bdb..00000000 --- a/lib-uuid/Makefile.GD32 +++ /dev/null @@ -1,4 +0,0 @@ -DEFINES=NDEBUG -EXTRA_INCLUDES= - -include ../firmware-template-gd32/lib/Rules.mk \ No newline at end of file diff --git a/lib-ws28xx/.cproject b/lib-ws28xx/.cproject index 2161333a..7a474aa2 100644 --- a/lib-ws28xx/.cproject +++ b/lib-ws28xx/.cproject @@ -5,7 +5,7 @@ - + @@ -14,15 +14,87 @@ - + - - - + + + + + @@ -113,6 +196,7 @@ + @@ -125,28 +209,34 @@ - + - + - + - + - + - + - + + + + + + + diff --git a/lib-ws28xx/Makefile.GD32 b/lib-ws28xx/Makefile.GD32 index 25d2acc4..de713c39 100644 --- a/lib-ws28xx/Makefile.GD32 +++ b/lib-ws28xx/Makefile.GD32 @@ -1,8 +1,17 @@ -DEFINES=USE_SPI_DMA -DEFINES+=NDEBUG +#DEFINES=NDEBUG -EXTRA_INCLUDES=../lib-device/include ../lib-hal/include +EXTRA_INCLUDES= -EXTRA_SRCDIR=src/patterns src/pixel src/gpio src/i2s +EXTRA_SRCDIR=src/patterns src/pixel + +ifneq ($(MAKE_FLAGS),) + ifeq ($(findstring OUTPUT_DMX_PIXEL_MULTI,$(MAKE_FLAGS)), OUTPUT_DMX_PIXEL_MULTI) + EXTRA_SRCDIR+=src/gd32/gpio + else + EXTRA_SRCDIR+=src/gd32/i2s + endif +else + EXTRA_SRCDIR+=src/gd32/gpio src/gd32/i2s +endif include ../firmware-template-gd32/lib/Rules.mk diff --git a/lib-ws28xx/Rules.mk b/lib-ws28xx/Rules.mk old mode 100755 new mode 100644 index 7c4c20d3..3263c056 --- a/lib-ws28xx/Rules.mk +++ b/lib-ws28xx/Rules.mk @@ -1 +1 @@ -EXTRA_INCLUDES+=../lib-hal/include \ No newline at end of file +EXTRA_INCLUDES+= \ No newline at end of file diff --git a/lib-ws28xx/include/gpio/board_gd32f207rg.h b/lib-ws28xx/include/gd32/gpio/board_gd32f207rg.h similarity index 100% rename from lib-ws28xx/include/gpio/board_gd32f207rg.h rename to lib-ws28xx/include/gd32/gpio/board_gd32f207rg.h diff --git a/lib-ws28xx/include/gpio/pixelmulti_config.h b/lib-ws28xx/include/gd32/gpio/pixelmulti_config.h similarity index 88% rename from lib-ws28xx/include/gpio/pixelmulti_config.h rename to lib-ws28xx/include/gd32/gpio/pixelmulti_config.h index 2ec4316d..a6bf29c1 100644 --- a/lib-ws28xx/include/gpio/pixelmulti_config.h +++ b/lib-ws28xx/include/gd32/gpio/pixelmulti_config.h @@ -2,7 +2,7 @@ * @file pixelmulti_config.h * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,14 +28,18 @@ #if defined (BOARD_GD32F207RG) # include "board_gd32f207rg.h" -#elif defined (BOARD_GD32F207C_EVAL) -# include "board_gd32f207c_eval.h" #elif defined (BOARD_GD32F407RE) # include "board_gd32f407re.h" #elif defined (BOARD_GD32F450VI) # include "board_gd32f450vi.h" #elif defined (BOARD_16X4U_PIXEL) # include "board_gd32f450vi.h" +#elif defined (BOARD_GD32F470VG) +# include "board_gd32f470vg.h" +#elif defined (BOARD_GD32F207C_EVAL) +# include "board_gd32f207c_eval.h" +#elif defined (BOARD_GD32F470Z_EVAL) +# include "board_gd32f470z_eval.h" #else # error Board is not supported #endif diff --git a/lib-ws28xx/include/gpio/ws28xxmulti.h b/lib-ws28xx/include/gd32/gpio/ws28xxmulti.h similarity index 76% rename from lib-ws28xx/include/gpio/ws28xxmulti.h rename to lib-ws28xx/include/gd32/gpio/ws28xxmulti.h index 91a532f9..444d5744 100644 --- a/lib-ws28xx/include/gpio/ws28xxmulti.h +++ b/lib-ws28xx/include/gd32/gpio/ws28xxmulti.h @@ -2,7 +2,7 @@ * @file ws28xxmulti.h * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,13 +32,13 @@ class WS28xxMulti { public: - WS28xxMulti(PixelConfiguration& pixelConfiguration); + WS28xxMulti(); ~WS28xxMulti(); - void Print(); - - void SetPixel(const uint32_t nPortIndex, const uint32_t nPixelIndex, uint8_t nRed, uint8_t nGreen, uint8_t nBlue); - void SetPixel(const uint32_t nPortIndex, const uint32_t nPixelIndex, uint8_t nRed, uint8_t nGreen, uint8_t nBlue, uint8_t nWhite); + void SetColourRTZ(const uint32_t nPortIndex, const uint32_t nPixelIndex, const uint8_t nColour1, const uint8_t nColour2, const uint8_t nColour3); + void SetColourRTZ(const uint32_t nPortIndex, const uint32_t nPixelIndex, const uint8_t nRed, const uint8_t nGreen, const uint8_t nBlue, const uint8_t nWhite); + void SetColourWS2801(const uint32_t nPortIndex, const uint32_t nPixelIndex, const uint8_t nColour1, const uint8_t nColour2, const uint8_t nColour3); + void SetPixel4Bytes(const uint32_t nPortIndex, const uint32_t nPixelIndex, const uint8_t nCtrl, const uint8_t nColour1, const uint8_t nColour2, const uint8_t nColour3); bool IsUpdating(); @@ -46,17 +46,7 @@ class WS28xxMulti { void Blackout(); void FullOn(); - pixel::Type GetType() const { - return m_PixelConfiguration.GetType(); - } - - uint32_t GetCount() const { - return m_PixelConfiguration.GetCount(); - } - - pixel::Map GetMap() const { - return m_PixelConfiguration.GetMap(); - } + void Print(); static WS28xxMulti *Get() { return s_pThis; @@ -65,12 +55,8 @@ class WS28xxMulti { private: void Setup(uint8_t nLowCode, uint8_t nHighCode); void Setup(uint32_t nFrequency); - void SetColourRTZ(const uint32_t nPortIndex, const uint32_t nPixelIndex, const uint8_t nColour1, const uint8_t nColour2, const uint8_t nColour3); - void SetColourWS2801(const uint32_t nPortIndex, const uint32_t nPixelIndex, const uint8_t nColour1, const uint8_t nColour2, const uint8_t nColour3); - void SetPixel4Bytes(const uint32_t nPortIndex, const uint32_t nPixelIndex, const uint8_t nCtrl, const uint8_t nColour1, const uint8_t nColour2, const uint8_t nColour3); private: - PixelConfiguration m_PixelConfiguration; uint32_t m_nBufSize { 0 }; static WS28xxMulti *s_pThis; diff --git a/lib-ws28xx/include/pixelconfiguration.h b/lib-ws28xx/include/pixelconfiguration.h old mode 100644 new mode 100755 index 25ecdda4..044db4ab --- a/lib-ws28xx/include/pixelconfiguration.h +++ b/lib-ws28xx/include/pixelconfiguration.h @@ -2,7 +2,7 @@ * @file pixelconfiguration.h * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -22,18 +22,40 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ +/** + * Static Local Variables: + * Since C++11, the initialization of function-local static variables, is guaranteed to be thread-safe. + * This means that even if multiple threads attempt to access Get() simultaneously, + * the C++ runtime ensures that the instance is initialized only once. + */ #ifndef PIXELCONFIGURATION_H_ #define PIXELCONFIGURATION_H_ #include +#include +#include #include "pixeltype.h" -#include "gamma/gamma_tables.h" + +#if defined (CONFIG_PIXELDMX_ENABLE_GAMMATABLE) +# include "gamma/gamma_tables.h" +#endif + +#include "debug.h" class PixelConfiguration { public: - void SetType(pixel::Type Type) { + PixelConfiguration() { + DEBUG_ENTRY + + assert(s_pThis == nullptr); + s_pThis = this; + + DEBUG_EXIT + } + + void SetType(const pixel::Type Type) { m_type = Type; } @@ -41,15 +63,15 @@ class PixelConfiguration { return m_type; } - void SetCount(uint32_t nCount) { - m_nCount = nCount == 0 ? pixel::defaults::COUNT : nCount; + void SetCount(const uint32_t nCount) { + m_nCount = (nCount == 0 ? pixel::defaults::COUNT : nCount); } uint32_t GetCount() const { return m_nCount; } - void SetMap(pixel::Map tMap) { + void SetMap(const pixel::Map tMap) { m_map = tMap; } @@ -57,7 +79,7 @@ class PixelConfiguration { return m_map; } - void SetLowCode(uint8_t nLowCode) { + void SetLowCode(const uint8_t nLowCode) { m_nLowCode = nLowCode; } @@ -65,7 +87,7 @@ class PixelConfiguration { return m_nLowCode; } - void SetHighCode(uint8_t nHighCode) { + void SetHighCode(const uint8_t nHighCode) { m_nHighCode = nHighCode; } @@ -73,7 +95,7 @@ class PixelConfiguration { return m_nHighCode; } - void SetClockSpeedHz(uint32_t nClockSpeedHz) { + void SetClockSpeedHz(const uint32_t nClockSpeedHz) { m_nClockSpeedHz = nClockSpeedHz; } @@ -81,7 +103,7 @@ class PixelConfiguration { return m_nClockSpeedHz; } - void SetGlobalBrightness(uint8_t nGlobalBrightness) { + void SetGlobalBrightness(const uint8_t nGlobalBrightness) { m_nGlobalBrightness = nGlobalBrightness; } @@ -93,7 +115,16 @@ class PixelConfiguration { return m_bIsRTZProtocol; } - void SetEnableGammaCorrection(bool doEnable) { + uint32_t GetLedsPerPixel() const { + return m_nLedsPerPixel; + } + + uint32_t GetRefreshRate() const { + return m_nRefreshRate; + } + +#if defined (CONFIG_PIXELDMX_ENABLE_GAMMATABLE) + void SetEnableGammaCorrection(const bool doEnable) { m_bEnableGammaCorrection = doEnable; } @@ -101,38 +132,162 @@ class PixelConfiguration { return m_bEnableGammaCorrection; } - void SetGammaTable(uint32_t nValue) { + void SetGammaTable(const uint32_t nValue) { m_nGammaValue = static_cast(nValue); } const uint8_t *GetGammaTable() const { return m_pGammaTable; } +#endif + + void GetTxH(const pixel::Type type, uint8_t &nLowCode, uint8_t &nHighCode) { + nLowCode = 0xC0; + nHighCode = (type == pixel::Type::WS2812B ? 0xF8 : + (((type == pixel::Type::UCS1903) || (type == pixel::Type::UCS2903) || (type == pixel::Type::CS8812)) ? 0xFC : 0xF0)); + } + + void Validate() { + DEBUG_ENTRY + + if (m_type == pixel::Type::SK6812W) { + m_nCount = m_nCount <= static_cast(pixel::max::ledcount::RGBW) ? m_nCount : static_cast(pixel::max::ledcount::RGBW); + m_nLedsPerPixel = 4; + } else { + m_nCount = m_nCount <= static_cast(pixel::max::ledcount::RGB) ? m_nCount : static_cast(pixel::max::ledcount::RGB); + m_nLedsPerPixel = 3; + } + + if ((m_type == pixel::Type::APA102) || (m_type == pixel::Type::SK9822)){ + if (m_nGlobalBrightness > 0x1F) { + m_nGlobalBrightness = 0xFF; + } else { + m_nGlobalBrightness = 0xE0 | (m_nGlobalBrightness & 0x1F); + } + } + + if ((m_type == pixel::Type::WS2801) || (m_type == pixel::Type::APA102) || (m_type == pixel::Type::SK9822) || (m_type == pixel::Type::P9813)) { + m_bIsRTZProtocol = false; + + if (m_map == pixel::Map::UNDEFINED) { + m_map = pixel::Map::RGB; + } + + if (m_type == pixel::Type::P9813) { + if (m_nClockSpeedHz == 0) { + m_nClockSpeedHz = pixel::spi::speed::p9813::default_hz; + } else if (m_nClockSpeedHz > pixel::spi::speed::p9813::max_hz) { + m_nClockSpeedHz = pixel::spi::speed::p9813::max_hz; + } + } else { + if (m_nClockSpeedHz == 0) { + m_nClockSpeedHz = pixel::spi::speed::ws2801::default_hz; + } else if (m_nClockSpeedHz > pixel::spi::speed::ws2801::max_hz) { + m_nClockSpeedHz = pixel::spi::speed::ws2801::max_hz; + } + } + + const auto nLedTime = (8U * 1000000U) / m_nClockSpeedHz; + const auto nLedsTime = nLedTime * m_nCount * m_nLedsPerPixel; + m_nRefreshRate = 1000000U / nLedsTime; + } else { + m_bIsRTZProtocol = true; + + if (m_type == pixel::Type::UNDEFINED) { + m_type = pixel::Type::WS2812B; + } - void Validate(uint32_t& nLedsPerPixel); + if (m_map == pixel::Map::UNDEFINED) { + m_map = pixel::pixel_get_map(m_type); + } - void Print(); + if (m_nLowCode >= m_nHighCode) { + m_nLowCode = 0; + m_nHighCode = 0; + } - void Dump() { -#ifndef NDEBUG - Print(); + uint8_t nLowCode, nHighCode; + + GetTxH(m_type, nLowCode, nHighCode); + + if (m_nLowCode == 0) { + m_nLowCode = nLowCode; + } + + if (m_nHighCode == 0) { + m_nHighCode = nHighCode; + } + + m_nClockSpeedHz = 6400000; // 6.4MHz / 8 bits = 800Hz + + // 8 * 1000.000 + // led time (us) = ------------ * 8 = 10 us + // 6.400.000 + const auto nLedsTime = 10U * m_nCount * m_nLedsPerPixel; + m_nRefreshRate = 1000000U / nLedsTime; + } + +#if defined (CONFIG_PIXELDMX_ENABLE_GAMMATABLE) + if (m_bEnableGammaCorrection) { + if (m_nGammaValue == 0) { + m_pGammaTable = gamma::get_table_default(m_type); + } else { + m_pGammaTable = gamma::get_table(m_nGammaValue); + } + } else { + m_pGammaTable = gamma10_0; + } +#endif + + DEBUG_EXIT + } + + void Print() { + puts("Pixel configuration"); + printf(" Type : %s [%d] <%d leds/pixel>\n", pixel::pixel_get_type(m_type), static_cast(m_type), static_cast(m_nLedsPerPixel)); + printf(" Count : %d\n", m_nCount); + + if (m_bIsRTZProtocol) { + printf(" Mapping : %s [%d]\n", pixel::pixel_get_map(m_map), static_cast(m_map)); + printf(" T0H : %.2f [0x%X]\n", pixel::pixel_convert_TxH(m_nLowCode), m_nLowCode); + printf(" T1H : %.2f [0x%X]\n", pixel::pixel_convert_TxH(m_nHighCode), m_nHighCode); + } else { + if ((m_type == pixel::Type::APA102) || (m_type == pixel::Type::SK9822)){ + printf(" GlobalBrightness: %u\n", m_nGlobalBrightness); + } + } + + printf(" Clock : %u Hz\n", static_cast(m_nClockSpeedHz)); + printf(" Refresh : %u Hz\n", static_cast(m_nRefreshRate)); + +#if defined (CONFIG_PIXELDMX_ENABLE_GAMMATABLE) + printf(" Gamma correction %s\n", m_bEnableGammaCorrection ? "Yes" : "No"); #endif } - static void GetTxH(pixel::Type tType, uint8_t &nLowCode, uint8_t &nHighCode); + static PixelConfiguration& Get() { + assert(s_pThis != nullptr); // Ensure that s_pThis is valid + return *s_pThis; + } private: - pixel::Type m_type { pixel::defaults::TYPE }; uint32_t m_nCount { pixel::defaults::COUNT }; - pixel::Map m_map { pixel::Map::UNDEFINED }; uint32_t m_nClockSpeedHz { 0 }; + uint32_t m_nLedsPerPixel { 3 }; + pixel::Type m_type { pixel::defaults::TYPE }; + pixel::Map m_map { pixel::Map::UNDEFINED }; + bool m_bIsRTZProtocol { true }; uint8_t m_nLowCode { 0 }; uint8_t m_nHighCode { 0 }; uint8_t m_nGlobalBrightness { 0xFF }; + uint32_t m_nRefreshRate { 0 }; +#if defined (CONFIG_PIXELDMX_ENABLE_GAMMATABLE) uint8_t m_nGammaValue { 0 }; bool m_bEnableGammaCorrection { false }; - bool m_bIsRTZProtocol { true }; const uint8_t *m_pGammaTable { gamma10_0 }; +#endif + + static inline PixelConfiguration *s_pThis { nullptr }; }; #endif /* PIXELCONFIGURATION_H_ */ diff --git a/lib-ws28xx/include/pixelpatterns.h b/lib-ws28xx/include/pixelpatterns.h index 5fe2558d..a100e991 100644 --- a/lib-ws28xx/include/pixelpatterns.h +++ b/lib-ws28xx/include/pixelpatterns.h @@ -2,7 +2,7 @@ * @file pixelpatterns.h * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -56,8 +56,8 @@ enum class Direction { class PixelPatterns { public: - PixelPatterns(uint32_t nActivePorts); - ~PixelPatterns() {} + PixelPatterns(const uint32_t nActivePorts); + ~PixelPatterns() = default; static const char* GetName(pixelpatterns::Pattern pattern); @@ -66,16 +66,31 @@ class PixelPatterns { void ColourWipe(uint32_t nPortIndex, uint32_t nColour, uint32_t nInterval, pixelpatterns::Direction dir = pixelpatterns::Direction::FORWARD); void Scanner(uint32_t nPortIndex, uint32_t nColour1, uint32_t nInterval) ; void Fade(uint32_t nPortIndex, uint32_t nColour1, uint32_t nColour2, uint32_t nSteps, uint32_t nInterval, pixelpatterns::Direction dir = pixelpatterns::Direction::FORWARD); - void None(uint32_t nPortIndex) { - m_PortConfig[nPortIndex].ActivePattern = pixelpatterns::Pattern::NONE; + void None(const uint32_t nPortIndex) { + s_PortConfig[nPortIndex].ActivePattern = pixelpatterns::Pattern::NONE; Clear(nPortIndex); - while (m_pOutput->IsUpdating()) { + while (s_pOutput->IsUpdating()) { } - m_pOutput->Update(); + s_pOutput->Update(); } - void Run(); + void Run() { + if (s_pOutput->IsUpdating()) { + return; + } + + auto bIsUpdated = false; + const auto nMillis = Hardware::Get()->Millis(); + + for (uint32_t i = 0; i < s_nActivePorts; i++) { + bIsUpdated |= PortUpdate(i, nMillis); + } + + if (bIsUpdated) { + s_pOutput->Update(); + } + } uint32_t Colour(uint8_t nRed, uint8_t nGreen, uint8_t nBlue) { return static_cast(nRed << 16) | static_cast(nGreen << 8) | nBlue; @@ -94,67 +109,84 @@ class PixelPatterns { void Increment(uint32_t nPortIndex); void Reverse(uint32_t nPortIndex); - void SetPixelColour(__attribute__((unused)) uint32_t nPortIndex, uint32_t nPixelIndex, uint32_t nColour) { + void SetPixelColour([[maybe_unused]] uint32_t nPortIndex, const uint32_t nPixelIndex, const uint32_t nColour) { const auto nRed = Red(nColour); const auto nGreen = Green(nColour); const auto nBlue = Blue(nColour); #if defined (PIXELPATTERNS_MULTI) - if (m_pOutput->GetType() != pixel::Type::SK6812W) { - m_pOutput->SetPixel(nPortIndex, nPixelIndex, nRed, nGreen, nBlue); - } else { + switch (PixelConfiguration::Get().GetType()) { + case pixel::Type::WS2801: + s_pOutput->SetColourWS2801(nPortIndex, nPixelIndex, nRed, nGreen, nBlue); + break; + case pixel::Type::APA102: + case pixel::Type::SK9822: + s_pOutput->SetPixel4Bytes(nPortIndex, nPixelIndex, 0xFF, nRed, nGreen, nBlue); + break; + case pixel::Type::P9813: { + const auto nFlag = static_cast(0xC0 | ((~nBlue & 0xC0) >> 2) | ((~nRed & 0xC0) >> 4) | ((~nRed & 0xC0) >> 6)); + s_pOutput->SetPixel4Bytes(nPortIndex, nPixelIndex, nFlag, nBlue, nGreen, nRed); + } + break; + case pixel::Type::SK6812W: if ((nRed == nGreen) && (nGreen == nBlue)) { - m_pOutput->SetPixel(nPortIndex, nPixelIndex, 0x00, 0x00, 0x00, nRed); + s_pOutput->SetColourRTZ(nPortIndex, nPixelIndex, 0x00, 0x00, 0x00, nRed); } else { - m_pOutput->SetPixel(nPortIndex, nPixelIndex, nRed, nGreen, nBlue, 0x00); + s_pOutput->SetColourRTZ(nPortIndex, nPixelIndex, nRed, nGreen, nBlue, 0x00); } + break; + default: + s_pOutput->SetColourRTZ(nPortIndex, nPixelIndex, nRed, nGreen, nBlue); + break; } #else - if (m_pOutput->GetType() != pixel::Type::SK6812W) { - m_pOutput->SetPixel(nPixelIndex, nRed, nGreen, nBlue); + auto& pixelConfiguration = PixelConfiguration::Get(); + const auto type = pixelConfiguration.GetType(); + + if (type != pixel::Type::SK6812W) { + s_pOutput->SetPixel(nPixelIndex, nRed, nGreen, nBlue); } else { if ((nRed == nGreen) && (nGreen == nBlue)) { - m_pOutput->SetPixel(nPixelIndex, 0x00, 0x00, 0x00, nRed); + s_pOutput->SetPixel(nPixelIndex, 0x00, 0x00, 0x00, nRed); } else { - m_pOutput->SetPixel(nPixelIndex, nRed, nGreen, nBlue, 0x00); + s_pOutput->SetPixel(nPixelIndex, nRed, nGreen, nBlue, 0x00); } } #endif } - void ColourSet(uint32_t nPortIndex, uint32_t nColour) { - for (uint32_t i = 0; i < m_nCount; i++) { + void ColourSet(const uint32_t nPortIndex, const uint32_t nColour) { + for (uint32_t i = 0; i < PixelConfiguration::Get().GetCount(); i++) { SetPixelColour(nPortIndex, i, nColour); } } - uint32_t DimColour(uint32_t nColour) { + uint32_t DimColour(const uint32_t nColour) { return Colour(static_cast(Red(nColour) >> 1), static_cast(Green(nColour) >> 1), static_cast(Blue(nColour) >> 1)); } - uint8_t Red(uint32_t nColour) { + uint8_t Red(const uint32_t nColour) { return (nColour >> 16) & 0xFF; } - uint8_t Green(uint32_t nColour) { + uint8_t Green(const uint32_t nColour) { return (nColour >> 8) & 0xFF; } - uint8_t Blue(uint32_t nColour) { + uint8_t Blue(const uint32_t nColour) { return nColour & 0xFF; } - void Clear(uint32_t nPortIndex) { + void Clear(const uint32_t nPortIndex) { ColourSet(nPortIndex, 0); } private: #if defined (PIXELPATTERNS_MULTI) - static WS28xxMulti *m_pOutput; + static WS28xxMulti *s_pOutput; #else - static WS28xx *m_pOutput; + static WS28xx *s_pOutput; #endif - static uint32_t m_nActivePorts; - static uint32_t m_nCount; + static uint32_t s_nActivePorts; struct PortConfig { uint32_t nLastUpdate; @@ -167,9 +199,9 @@ class PixelPatterns { pixelpatterns::Pattern ActivePattern; }; - static PortConfig m_PortConfig[pixelpatterns::MAX_PORTS]; + static PortConfig s_PortConfig[pixelpatterns::MAX_PORTS]; - static uint32_t *m_pScannerColours; + static uint32_t *s_pScannerColours; }; #endif /* PIXELPATTERNS_H_ */ diff --git a/lib-ws28xx/include/pixelreboot.h b/lib-ws28xx/include/pixelreboot.h index 382e17ef..bc9cc8ad 100644 --- a/lib-ws28xx/include/pixelreboot.h +++ b/lib-ws28xx/include/pixelreboot.h @@ -2,7 +2,7 @@ * @file pixelreboot.h * */ -/* Copyright (C) 2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-ws28xx/include/pixeltestpattern.h b/lib-ws28xx/include/pixeltestpattern.h index 052fc1b7..93aa8f95 100644 --- a/lib-ws28xx/include/pixeltestpattern.h +++ b/lib-ws28xx/include/pixeltestpattern.h @@ -2,7 +2,7 @@ * @file pixeltestpattern.h * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,17 +33,18 @@ class PixelTestPattern: PixelPatterns { public: - PixelTestPattern(pixelpatterns::Pattern Pattern, uint32_t OutputPorts) : PixelPatterns(OutputPorts) { - s_Pattern = Pattern; + PixelTestPattern(const pixelpatterns::Pattern Pattern, const uint32_t OutputPorts) : PixelPatterns(OutputPorts) { + assert(s_pThis == nullptr); + s_pThis = this; SetPattern(Pattern); } - bool SetPattern(pixelpatterns::Pattern Pattern) { + bool SetPattern(const pixelpatterns::Pattern Pattern) { if (Pattern >= pixelpatterns::Pattern::LAST) { return false; } - s_Pattern = Pattern; + m_Pattern = Pattern; const auto nColour1 = PixelPatterns::Colour(0, 0, 0); const auto nColour2 = PixelPatterns::Colour(100, 100, 100); @@ -80,21 +81,21 @@ class PixelTestPattern: PixelPatterns { } void Run() { - if (s_Pattern != pixelpatterns::Pattern::NONE) { + if (__builtin_expect((m_Pattern != pixelpatterns::Pattern::NONE), 0)) { PixelPatterns::Run(); } } - static pixelpatterns::Pattern GetPattern() { - return s_Pattern; + pixelpatterns::Pattern GetPattern() { + return m_Pattern; } - static PixelTestPattern* Get() { + static PixelTestPattern *Get() { return s_pThis; } private: - static pixelpatterns::Pattern s_Pattern; + pixelpatterns::Pattern m_Pattern; static PixelTestPattern *s_pThis; }; diff --git a/lib-ws28xx/include/pixeltype.h b/lib-ws28xx/include/pixeltype.h index cc476e57..9cf8ff2d 100644 --- a/lib-ws28xx/include/pixeltype.h +++ b/lib-ws28xx/include/pixeltype.h @@ -2,7 +2,7 @@ * @file pixeltype.h * */ -/* Copyright (C) 2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,6 +27,7 @@ #define PIXELTYPE_H_ #include +#include namespace pixel { enum class Type { @@ -77,23 +78,98 @@ static constexpr auto TYPE = Type::WS2812B; static constexpr auto COUNT = 170; static constexpr auto OUTPUT_PORTS = 1; } // namespace defaults -} // namespace pixel -class PixelType { -public: - static const char *GetType(pixel::Type type); - static pixel::Type GetType(const char *pString); +inline Map pixel_get_map(const pixel::Type type) { + if ((type == pixel::Type::WS2811) || (type == pixel::Type::UCS2903)) { + return pixel::Map::RGB; + } - static const char *GetMap(pixel::Map map); - static pixel::Map GetMap(const char *pString); - static pixel::Map GetMap(pixel::Type type); + if (type == pixel::Type::UCS1903) { + return pixel::Map::BRG; + } - static float ConvertTxH(uint8_t nCode); - static uint8_t ConvertTxH(float fTxH); + if (type == pixel::Type::CS8812) { + return pixel::Map::BGR; + } -private: - static const char TYPES[static_cast(pixel::Type::UNDEFINED)][pixel::TYPES_MAX_NAME_LENGTH]; - static const char MAPS[static_cast(pixel::Map::UNDEFINED)][4]; -}; + return pixel::Map::GRB; +} + +static constexpr auto F_INTERVAL = 0.15625f; + +inline float pixel_convert_TxH(const uint8_t nCode) { + switch (nCode) { + case 0x80: + return F_INTERVAL * 1; + break; + case 0xC0: + return F_INTERVAL * 2; + break; + case 0xE0: + return F_INTERVAL * 3; + break; + case 0xF0: + return F_INTERVAL * 4; + break; + case 0xF8: + return F_INTERVAL * 5; + break; + case 0xFC: + return F_INTERVAL * 6; + break; + case 0xFE: + return F_INTERVAL * 7; + break; + default: + return 0; + break; + } + + assert(0); + __builtin_unreachable(); +} + +inline uint8_t pixel_convert_TxH(const float fTxH) { + if (fTxH < 0.5f * F_INTERVAL) { + return 0x00; + } + + if (fTxH < 1.5f * F_INTERVAL) { + return 0x80; + } + + if (fTxH < 2.5f * F_INTERVAL) { + return 0xC0; + } + + if (fTxH < 3.5f * F_INTERVAL) { + return 0xE0; + } + + if (fTxH < 4.5f * F_INTERVAL) { + return 0xF0; + } + + if (fTxH < 5.5f * F_INTERVAL) { + return 0xF8; + } + + if (fTxH < 6.5f * F_INTERVAL) { + return 0xFC; + } + + if (fTxH < 7.5f * F_INTERVAL) { + return 0xFE; + } + + return 0x00; +} + +const char* pixel_get_type(pixel::Type); +pixel::Type pixel_get_type(const char *); + +const char* pixel_get_map(pixel::Map); +pixel::Map pixel_get_map(const char *); +} // namespace pixel #endif /* PIXELTYPE_H_ */ diff --git a/lib-ws28xx/include/spi/ws28xxmulti.h b/lib-ws28xx/include/spi/ws28xxmulti.h deleted file mode 100644 index fe6bf8b7..00000000 --- a/lib-ws28xx/include/spi/ws28xxmulti.h +++ /dev/null @@ -1,100 +0,0 @@ -/** - * @file ws28xxmulti.h - * - */ -/* Copyright (C) 2019-2021 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef SPI_WS28XXMULTI_H_ -#define SPI_WS28XXMULTI_H_ - -#include - -#include "pixelconfiguration.h" - -#if defined (H3) -# include "h3_spi.h" -#endif - -struct JamSTAPLDisplay; - -class WS28xxMulti { -public: - WS28xxMulti(PixelConfiguration& pixelConfiguration); - ~WS28xxMulti(); - - void Print(); - - void SetPixel(uint32_t nPortIndex, uint32_t nPixelIndex, uint8_t nRed, uint8_t nGreen, uint8_t nBlue); - void SetPixel(uint32_t nPortIndex, uint32_t nPixelIndex, uint8_t nRed, uint8_t nGreen, uint8_t nBlue, uint8_t nWhite); - - bool IsUpdating() { - return h3_spi_dma_tx_is_active(); // returns TRUE while DMA operation is active - } - - void Update(); - void Blackout(); - void FullOn(); - - pixel::Type GetType() const { - return m_Type; - } - - uint32_t GetCount() const { - return m_nCount; - } - - pixel::Map GetMap() const { - return m_Map; - } - - void SetJamSTAPLDisplay(JamSTAPLDisplay *pJamSTAPLDisplay) { - m_pJamSTAPLDisplay = pJamSTAPLDisplay; - } - - static WS28xxMulti *Get() { - return s_pThis; - } - -private: - uint8_t ReverseBits(uint8_t nBits); - void SetupHC595(uint8_t nT0H, uint8_t nT1H); - void SetupSPI(uint32_t nSpeedHz); - bool SetupCPLD(); - void SetupBuffers(); - void SetColour(uint32_t nPortIndex, uint32_t nPixelIndex, uint8_t nColour1, uint8_t nColour2, uint8_t nColour3); - -private: - bool m_hasCPLD { false }; - pixel::Type m_Type { pixel::defaults::TYPE }; - uint32_t m_nCount { pixel::defaults::COUNT }; - pixel::Map m_Map { pixel::Map::UNDEFINED }; - bool m_bIsRTZProtocol { true }; - uint8_t m_nGlobalBrightness { 0xFF }; - uint32_t m_nBufSize { 0 }; - uint8_t *m_pBuffer { nullptr }; - uint8_t *m_pBlackoutBuffer { nullptr }; - JamSTAPLDisplay *m_pJamSTAPLDisplay { nullptr }; - - static WS28xxMulti *s_pThis; -}; - -#endif /* SPI_WS28XXMULTI_H_ */ diff --git a/lib-ws28xx/include/ws28xx.h b/lib-ws28xx/include/ws28xx.h index 3361780d..d3fb8ef5 100644 --- a/lib-ws28xx/include/ws28xx.h +++ b/lib-ws28xx/include/ws28xx.h @@ -2,7 +2,7 @@ * @file ws28xx.h * */ -/* Copyright (C) 2017-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -30,44 +30,30 @@ #include "pixelconfiguration.h" -#if defined (USE_SPI_DMA) -# include "hal_spi.h" -#endif +#include "hal_spi.h" class WS28xx { public: - WS28xx(PixelConfiguration& pixelConfiguration); + WS28xx(); ~WS28xx(); void SetPixel(uint32_t nIndex, uint8_t nRed, uint8_t nGreen, uint8_t nBlue); void SetPixel(uint32_t nIndex, uint8_t nRed, uint8_t nGreen, uint8_t nBlue, uint8_t nWhite); -#if defined ( USE_SPI_DMA ) bool IsUpdating () { - return FUNC_PREFIX (spi_dma_tx_is_active()); - } +#if defined (GD32) + return i2s::gd32_spi_dma_tx_is_active(); +#elif defined (H3) + return h3_spi_dma_tx_is_active(); #else - bool IsUpdating() const { return false; - } #endif + } void Update(); void Blackout(); void FullOn(); - pixel::Type GetType() const { - return m_PixelConfiguration.GetType(); - } - - uint32_t GetCount() const { - return m_PixelConfiguration.GetCount(); - } - - pixel::Map GetMap() const { - return m_PixelConfiguration.GetMap(); - } - static WS28xx *Get() { return s_pThis; } @@ -77,7 +63,6 @@ class WS28xx { void SetColorWS28xx(uint32_t nOffset, uint8_t nValue); private: - PixelConfiguration m_PixelConfiguration; uint32_t m_nBufSize; uint8_t *m_pBuffer { nullptr }; uint8_t *m_pBlackoutBuffer { nullptr }; diff --git a/lib-ws28xx/include/ws28xxmulti.h b/lib-ws28xx/include/ws28xxmulti.h index 794a4bee..3872f7a2 100644 --- a/lib-ws28xx/include/ws28xxmulti.h +++ b/lib-ws28xx/include/ws28xxmulti.h @@ -2,7 +2,7 @@ * @file ws28xxmulti.h * */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,11 +27,11 @@ #define WS28XXMULTI_H_ #if defined (H3) -# include "spi/ws28xxmulti.h" +# include "h3/ws28xxmulti.h" #elif defined (GD32) -# include "gpio/ws28xxmulti.h" +# include "gd32/gpio/ws28xxmulti.h" #else -# error +# error Platform is not supported #endif #endif /* WS28XXMULTI_H_ */ diff --git a/lib-ws28xx/src/gpio/ws28xxmulti.cpp b/lib-ws28xx/src/gd32/gpio/ws28xxmulti.cpp similarity index 88% rename from lib-ws28xx/src/gpio/ws28xxmulti.cpp rename to lib-ws28xx/src/gd32/gpio/ws28xxmulti.cpp index 2cc2e127..f0ee9c99 100644 --- a/lib-ws28xx/src/gpio/ws28xxmulti.cpp +++ b/lib-ws28xx/src/gd32/gpio/ws28xxmulti.cpp @@ -23,6 +23,10 @@ * THE SOFTWARE. */ +#if defined (DEBUG_PIXEL) +# undef NDEBUG +#endif + #pragma GCC push_options #pragma GCC optimize ("O3") #pragma GCC optimize ("-funroll-loops") @@ -36,9 +40,10 @@ #include "ws28xxmulti.h" #include "pixelconfiguration.h" #include "pixeltype.h" -#include "gpio/pixelmulti_config.h" +#include "gd32/gpio/pixelmulti_config.h" #include "gd32.h" +#include "gd32_dma_memcpy32.h" #include "debug.h" @@ -76,12 +81,13 @@ namespace pixel { static constexpr auto PORT_COUNT = __builtin_popcount(GPIO_PINx); static_assert(PORT_COUNT <= 16, "Too many ports"); // -static uint16_t s_DmaBuffer[1024 * 16] __attribute__ ((aligned (4))) SECTION_DMA_BUFFER; +static uint16_t s_DmaBuffer[2 * 1024 * 16] __attribute__ ((aligned (4))) SECTION_DMA_BUFFER; static constexpr auto DMA_BUFFER_SIZE = sizeof(pixel::s_DmaBuffer) / sizeof(s_DmaBuffer[0]); +const auto *const s_pBuffer = reinterpret_cast(pixel::s_DmaBuffer + pixel::DMA_BUFFER_SIZE / 2); // RTZ static const uint16_t s_GPIO_PINs[] __attribute__ ((aligned (4))) = { GPIO_PINx } ; -static const auto *s_pGPIO_PINs = reinterpret_cast(&s_GPIO_PINs[0]); -static auto *s_pT0H = reinterpret_cast(&s_DmaBuffer[0]); +static const auto *const s_pGPIO_PINs = reinterpret_cast(&s_GPIO_PINs[0]); +static auto *const s_pT0H = reinterpret_cast(&s_DmaBuffer[0]); static constexpr uint32_t RTZ_TIMER_PERIOD = (0.00000125f * MASTER_TIMER_CLOCK) - 1U; // Clock based static constexpr auto MAX_APA102 = ((DMA_BUFFER_SIZE / 8) - 8 ) / 4; @@ -91,7 +97,6 @@ static volatile bool sv_isRunning; extern "C" { void TIMER3_IRQHandler() { // Slave - __DMB(); const auto nIntFlag = TIMER_INTF(TIMER3); if ((nIntFlag & TIMER_INT_FLAG_CH0) == TIMER_INT_FLAG_CH0) { @@ -104,21 +109,18 @@ void TIMER3_IRQHandler() { // Slave sv_isRunning = false; GPIO_BC(GPIOx) = GPIO_PINx; - #ifndef NDEBUG +#ifndef NDEBUG GPIO_BOP(DEBUG_CS_GPIOx) = DEBUG_CS_GPIO_PINx; - #endif - } else { - assert(0); +#endif } TIMER_INTF(TIMER3) = ~nIntFlag; - __DMB(); } } -WS28xxMulti *WS28xxMulti::s_pThis = nullptr; +WS28xxMulti *WS28xxMulti::s_pThis; -WS28xxMulti::WS28xxMulti(PixelConfiguration& pixelConfiguration): m_PixelConfiguration(pixelConfiguration) { +WS28xxMulti::WS28xxMulti() { DEBUG_ENTRY assert(s_pThis == nullptr); @@ -126,30 +128,32 @@ WS28xxMulti::WS28xxMulti(PixelConfiguration& pixelConfiguration): m_PixelConfigu DEBUG_PRINTF("PORT_COUNT=%u", pixel::PORT_COUNT); - uint32_t nLedsPerPixel; - pixelConfiguration.Validate(nLedsPerPixel); + auto& pixelConfiguration = PixelConfiguration::Get(); - const auto Type = m_PixelConfiguration.GetType(); + pixelConfiguration.Validate(); - if ((Type == pixel::Type::APA102) || (Type == pixel::Type::SK9822) || (Type == pixel::Type::P9813)) { + const auto type = pixelConfiguration.GetType(); + const auto nLedsPerPixel = pixelConfiguration.GetLedsPerPixel(); + + if ((type == pixel::Type::APA102) || (type == pixel::Type::SK9822) || (type == pixel::Type::P9813)) { DEBUG_PRINTF("MAX_APA102=%u", pixel::MAX_APA102); if (pixelConfiguration.GetCount() > pixel::MAX_APA102) { pixelConfiguration.SetCount(pixel::MAX_APA102); - pixelConfiguration.Validate(nLedsPerPixel); - pixelConfiguration.Dump(); + pixelConfiguration.Validate(); } } - const auto nCount = m_PixelConfiguration.GetCount(); + const auto nCount = pixelConfiguration.GetCount(); m_nBufSize = nCount * nLedsPerPixel; - if ((Type == pixel::Type::APA102) || (Type == pixel::Type::SK9822) || (Type == pixel::Type::P9813)) { + if ((type == pixel::Type::APA102) || (type == pixel::Type::SK9822) || (type == pixel::Type::P9813)) { m_nBufSize += nCount; m_nBufSize += 8; } m_nBufSize *= 8; + DEBUG_PRINTF("s_DmaBuffer=%p, s_pBuffer=%p", pixel::s_DmaBuffer, pixel::s_pBuffer); DEBUG_PRINTF("m_nBufSize=%u [%u]", m_nBufSize, (m_nBufSize + 1024) / 1024); assert(m_nBufSize <= pixel::DMA_BUFFER_SIZE); @@ -161,7 +165,6 @@ WS28xxMulti::WS28xxMulti(PixelConfiguration& pixelConfiguration): m_PixelConfigu #if !defined (GD32F4XX) gpio_init(GPIOx, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PINx); #else - gpio_af_set(GPIOx, GPIO_AF_0, GPIO_PINx); gpio_mode_set(GPIOx, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLDOWN, GPIO_PINx); gpio_output_options_set(GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PINx); #endif @@ -173,7 +176,6 @@ WS28xxMulti::WS28xxMulti(PixelConfiguration& pixelConfiguration): m_PixelConfigu #if !defined (GD32F4XX) gpio_init(DEBUG_CS_GPIOx, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, DEBUG_CS_GPIO_PINx); #else - gpio_af_set(DEBUG_CS_GPIOx, GPIO_AF_0, DEBUG_CS_GPIO_PINx); gpio_mode_set(DEBUG_CS_GPIOx, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLDOWN, DEBUG_CS_GPIO_PINx); gpio_output_options_set(DEBUG_CS_GPIOx, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, DEBUG_CS_GPIO_PINx); #endif @@ -187,6 +189,8 @@ WS28xxMulti::WS28xxMulti(PixelConfiguration& pixelConfiguration): m_PixelConfigu Setup(pixelConfiguration.GetClockSpeedHz()); } + dma::memcpy32_init(); + DEBUG_EXIT } @@ -563,10 +567,11 @@ void WS28xxMulti::Setup(uint32_t nFrequency) { * BEGIN Buffer setup */ - const auto Type = m_PixelConfiguration.GetType(); + auto& pixelConfiguration = PixelConfiguration::Get(); + const auto Type = pixelConfiguration.GetType(); if ((Type == pixel::Type::APA102) || (Type == pixel::Type::SK9822) || (Type == pixel::Type::P9813)) { - const auto nCount = m_PixelConfiguration.GetCount(); + const auto nCount = pixelConfiguration.GetCount(); for (auto nPortIndex = 0; nPortIndex < pixel::PORT_COUNT; nPortIndex++) { SetPixel4Bytes(nPortIndex, 0, 0, 0, 0, 0); @@ -586,28 +591,34 @@ void WS28xxMulti::Setup(uint32_t nFrequency) { } void WS28xxMulti::Print() { - const auto Type = m_PixelConfiguration.GetType(); + auto& pixelConfiguration = PixelConfiguration::Get(); + const auto Type = pixelConfiguration.GetType(); printf("Pixel\n"); - printf(" Type : %s [%d]\n", PixelType::GetType(Type), static_cast(Type)); - printf(" Count : %d\n", m_PixelConfiguration.GetCount()); + printf(" Type : %s [%d]\n", pixel::pixel_get_type(Type), static_cast(Type)); + printf(" Count : %d\n", pixelConfiguration.GetCount()); - if (!m_PixelConfiguration.IsRTZProtocol()) { - printf(" Clock : %u Hz\n", m_PixelConfiguration.GetClockSpeedHz()); + if (!pixelConfiguration.IsRTZProtocol()) { + printf(" Clock : %u Hz\n", pixelConfiguration.GetClockSpeedHz()); } else { - const auto Map = m_PixelConfiguration.GetMap(); - const auto nLowCode = m_PixelConfiguration.GetLowCode(); - const auto nHighCode = m_PixelConfiguration.GetHighCode(); + const auto Map = pixelConfiguration.GetMap(); + const auto nLowCode = pixelConfiguration.GetLowCode(); + const auto nHighCode = pixelConfiguration.GetHighCode(); - printf(" Mapping : %s [%d]\n", PixelType::GetMap(Map), static_cast(Map)); - printf(" T0H : %.2f [0x%X]\n", PixelType::ConvertTxH(nLowCode), nLowCode); - printf(" T1H : %.2f [0x%X]\n", PixelType::ConvertTxH(nHighCode), nHighCode); + printf(" Mapping : %s [%d]\n", pixel::pixel_get_map(Map), static_cast(Map)); + printf(" T0H : %.2f [0x%X]\n", pixel::pixel_convert_TxH(nLowCode), nLowCode); + printf(" T1H : %.2f [0x%X]\n", pixel::pixel_convert_TxH(nHighCode), nHighCode); } } void WS28xxMulti::Update() { assert(!sv_isRunning); + dma::memcpy32(reinterpret_cast(pixel::s_DmaBuffer), reinterpret_cast(pixel::s_DmaBuffer + pixel::DMA_BUFFER_SIZE / 2), m_nBufSize / 2); + + while (dma::memcpy32_is_active()) + ; + #ifndef NDEBUG GPIO_BC(DEBUG_CS_GPIOx) = DEBUG_CS_GPIO_PINx; #endif @@ -620,7 +631,9 @@ void WS28xxMulti::Update() { TIMER_CTL0(TIMER2) &= (~TIMER_CTL0_CEN); TIMER_CNT(TIMER2) = 0; - if (m_PixelConfiguration.IsRTZProtocol()) { + auto& pixelConfiguration = PixelConfiguration::Get(); + + if (pixelConfiguration.IsRTZProtocol()) { DMA_CHCTL(TIMER2_DMAx, TIMER2_CH0_DMA_CHx) &= ~DMA_CHXCTL_CHEN; dma_interrupt_flag_clear(TIMER2_DMAx, TIMER2_CH0_DMA_CHx, DMA_INTF_FTFIF); DMA_CHMADDR(TIMER2_DMAx, TIMER2_CH0_DMA_CHx) = reinterpret_cast(pixel::s_pGPIO_PINs); @@ -674,14 +687,16 @@ void WS28xxMulti::Blackout() { __DMB(); } while (sv_isRunning); - if (m_PixelConfiguration.IsRTZProtocol()) { + auto& pixelConfiguration = PixelConfiguration::Get(); + + if (pixelConfiguration.IsRTZProtocol()) { for (uint32_t i = 0; i < pixel::DMA_BUFFER_SIZE / 2; i++) { pixel::s_pT0H[i] = GPIO_PINx | (static_cast(GPIO_PINx) << 16); } } else { - const auto Type = m_PixelConfiguration.GetType(); + const auto Type = pixelConfiguration.GetType(); if ((Type == pixel::Type::APA102) || (Type == pixel::Type::SK9822) || (Type == pixel::Type::P9813)) { - const auto nCount = m_PixelConfiguration.GetCount(); + const auto nCount = pixelConfiguration.GetCount(); for (auto nPortIndex = 0; nPortIndex < pixel::PORT_COUNT; nPortIndex++) { SetPixel4Bytes(nPortIndex, 0, 0, 0, 0, 0); @@ -729,14 +744,16 @@ void WS28xxMulti::FullOn() { __DMB(); } while (sv_isRunning); - if (m_PixelConfiguration.IsRTZProtocol()) { + auto& pixelConfiguration = PixelConfiguration::Get(); + + if (pixelConfiguration.IsRTZProtocol()) { for (uint32_t i = 0; i < pixel::DMA_BUFFER_SIZE / 2; i++) { pixel::s_pT0H[i] = 0; } } else { - const auto Type = m_PixelConfiguration.GetType(); + const auto Type = pixelConfiguration.GetType(); if ((Type == pixel::Type::APA102) || (Type == pixel::Type::SK9822) || (Type == pixel::Type::P9813)) { - const auto nCount = m_PixelConfiguration.GetCount(); + const auto nCount = pixelConfiguration.GetCount(); for (auto nPortIndex = 0; nPortIndex < pixel::PORT_COUNT; nPortIndex++) { SetPixel4Bytes(nPortIndex, 0, 0, 0, 0, 0); @@ -786,13 +803,12 @@ bool WS28xxMulti::IsUpdating() { } void WS28xxMulti::SetColourRTZ(const uint32_t nPortIndex, const uint32_t nPixelIndex, const uint8_t nColour1, const uint8_t nColour2, const uint8_t nColour3) { - assert(nPortIndex < 16); - assert(nPixelIndex < m_nBufSize / 8); //FIXME 8 + assert(nPortIndex < pixel::PORT_COUNT); uint32_t j = 0; const auto k = nPixelIndex * pixel::single::RGB; const auto nBit = nPortIndex + GPIO_PIN_OFFSET; - auto *p = &pixel::s_DmaBuffer[k]; + auto *p = &pixel::s_pBuffer[k]; for (uint8_t mask = 0x80; mask != 0; mask = static_cast(mask >> 1)) { if (!(mask & nColour1)) { @@ -883,51 +899,18 @@ void WS28xxMulti::SetPixel4Bytes(const uint32_t nPortIndex, const uint32_t nPixe } } -void WS28xxMulti::SetPixel(const uint32_t nPortIndex, const uint32_t nPixelIndex, uint8_t nRed, uint8_t nGreen, uint8_t nBlue) { - const auto pGammaTable = m_PixelConfiguration.GetGammaTable(); - - nRed = pGammaTable[nRed]; - nGreen = pGammaTable[nGreen]; - nBlue = pGammaTable[nBlue]; - - if (m_PixelConfiguration.IsRTZProtocol()) { - SetColourRTZ(nPortIndex, nPixelIndex, nRed, nGreen, nBlue); - return; - } - - const auto type = m_PixelConfiguration.GetType(); - - if (type == pixel::Type::WS2801) { - SetColourWS2801(nPortIndex, nPixelIndex, nRed, nGreen, nBlue); - return; - } - - if ((type == pixel::Type::APA102) || (type == pixel::Type::SK9822)) { - SetPixel4Bytes(nPortIndex, 1 + nPixelIndex, m_PixelConfiguration.GetGlobalBrightness(), nBlue, nGreen, nRed); - return; - } - - if (type == pixel::Type::P9813) { - const auto nFlag = static_cast(0xC0 | ((~nBlue & 0xC0) >> 2) | ((~nGreen & 0xC0) >> 4) | ((~nRed & 0xC0) >> 6)); - SetPixel4Bytes(nPortIndex, 1 + nPixelIndex, nFlag, nBlue, nGreen, nRed); - return; - } - - assert(0); - __builtin_unreachable(); - return; -} - -void WS28xxMulti::SetPixel(const uint32_t nPortIndex, const uint32_t nPixelIndex, uint8_t nRed, uint8_t nGreen, uint8_t nBlue, uint8_t nWhite) { +void WS28xxMulti::SetColourRTZ(const uint32_t nPortIndex, const uint32_t nPixelIndex, uint8_t nRed, uint8_t nGreen, uint8_t nBlue, uint8_t nWhite) { assert(nPortIndex < 16); assert(nPixelIndex < m_nBufSize / 8); //FIXME 8 - const auto pGammaTable = m_PixelConfiguration.GetGammaTable(); +#if defined(CONFIG_PIXELDMX_ENABLE_GAMMATABLE) + const auto pGammaTable = pixelConfiguration.GetGammaTable(); nRed = pGammaTable[nRed]; nGreen = pGammaTable[nGreen]; nBlue = pGammaTable[nBlue]; nWhite = pGammaTable[nWhite]; +#endif const auto k = nPixelIndex * pixel::single::RGBW; const auto nBit = nPortIndex + GPIO_PIN_OFFSET; diff --git a/lib-ws28xx/src/i2s/ws28xx.cpp b/lib-ws28xx/src/gd32/i2s/ws28xx.cpp similarity index 66% rename from lib-ws28xx/src/i2s/ws28xx.cpp rename to lib-ws28xx/src/gd32/i2s/ws28xx.cpp index 1a742179..865034ff 100644 --- a/lib-ws28xx/src/i2s/ws28xx.cpp +++ b/lib-ws28xx/src/gd32/i2s/ws28xx.cpp @@ -2,7 +2,7 @@ * @file ws28xx.cpp * */ -/* Copyright (C) 2022 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2022-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,6 +23,10 @@ * THE SOFTWARE. */ +#if defined (DEBUG_PIXELDMX) +# undef NDEBUG +#endif + #include #include #include @@ -30,48 +34,44 @@ #include "ws28xx.h" #include "pixelconfiguration.h" -#include "hal_spi.h" +#include "gd32_spi.h" #include "debug.h" -using namespace pixel; - static uint32_t s_tmp; WS28xx *WS28xx::s_pThis; -WS28xx::WS28xx(PixelConfiguration& pixelConfiguration) { +WS28xx::WS28xx() { DEBUG_ENTRY assert(s_pThis == nullptr); s_pThis = this; - m_PixelConfiguration = pixelConfiguration; + auto& pixelConfiguration = PixelConfiguration::Get(); - uint32_t nLedsPerPixel; - pixelConfiguration.Validate(nLedsPerPixel); - pixelConfiguration.Dump(); + pixelConfiguration.Validate(); - const auto nCount = m_PixelConfiguration.GetCount(); + const auto nCount = pixelConfiguration.GetCount(); - m_nBufSize = nCount * nLedsPerPixel; + m_nBufSize = nCount * pixelConfiguration.GetLedsPerPixel(); - if (m_PixelConfiguration.IsRTZProtocol()) { + if (pixelConfiguration.IsRTZProtocol()) { m_nBufSize *= 8; m_nBufSize += 1; } - const auto type = m_PixelConfiguration.GetType(); + const auto type = pixelConfiguration.GetType(); - if ((type == Type::APA102) || (type == Type::SK9822) || (type == Type::P9813)) { + if ((type == pixel::Type::APA102) || (type == pixel::Type::SK9822) || (type == pixel::Type::P9813)) { m_nBufSize += nCount; m_nBufSize += 8; } SetupBuffers(); - FUNC_PREFIX(spi_dma_begin()); - FUNC_PREFIX(spi_dma_set_speed_hz(pixelConfiguration.GetClockSpeedHz())); + i2s::gd32_spi_dma_begin(); + i2s::gd32_spi_dma_set_speed_hz(pixelConfiguration.GetClockSpeedHz()); DEBUG_EXIT } @@ -87,7 +87,7 @@ void WS28xx::SetupBuffers() { uint32_t nSize; - m_pBuffer = const_cast(FUNC_PREFIX (spi_dma_tx_prepare(&nSize))); + m_pBuffer = const_cast(i2s::gd32_spi_dma_tx_prepare(&nSize)); assert(m_pBuffer != nullptr); const auto nSizeHalf = nSize / 2; @@ -118,7 +118,7 @@ void WS28xx::Update() { pDst[i] = __builtin_bswap16(pSrc[i]); } - FUNC_PREFIX(spi_dma_tx_start(m_pBlackoutBuffer, m_nBufSize)); + i2s::gd32_spi_dma_tx_start(m_pBlackoutBuffer, m_nBufSize); } void WS28xx::Blackout() { @@ -127,29 +127,31 @@ void WS28xx::Blackout() { // A blackout can be called any time. Make sure the previous transmit is ended. do { __ISB(); - } while (FUNC_PREFIX(spi_dma_tx_is_active())); + } while (i2s::gd32_spi_dma_tx_is_active()); auto *pBuffer = m_pBuffer; m_pBuffer = m_pBlackoutBuffer; - const auto type = m_PixelConfiguration.GetType(); - const auto nCount = m_PixelConfiguration.GetCount(); + auto& pixelConfiguration = PixelConfiguration::Get(); - if ((type == Type::APA102) || (type == Type::SK9822) || (type == Type::P9813)) { + const auto type = pixelConfiguration.GetType(); + const auto nCount = pixelConfiguration.GetCount(); + + if ((type == pixel::Type::APA102) || (type == pixel::Type::SK9822) || (type == pixel::Type::P9813)) { memset(m_pBuffer, 0, 4); for (uint32_t nPixelIndex = 0; nPixelIndex < nCount; nPixelIndex++) { SetPixel(nPixelIndex, 0, 0, 0); } - if ((type == Type::APA102) || (type == Type::SK9822)) { + if ((type == pixel::Type::APA102) || (type == pixel::Type::SK9822)) { memset(&m_pBuffer[m_nBufSize - 4], 0xFF, 4); } else { memset(&m_pBuffer[m_nBufSize - 4], 0, 4); } } else { m_pBuffer[0] = 0x00; - memset(&m_pBuffer[1], type == Type::WS2801 ? 0 : m_PixelConfiguration.GetLowCode(), m_nBufSize); + memset(&m_pBuffer[1], type == pixel::Type::WS2801 ? 0 : pixelConfiguration.GetLowCode(), m_nBufSize); } Update(); @@ -157,7 +159,7 @@ void WS28xx::Blackout() { // A blackout may not be interrupted. do { __ISB(); - } while (FUNC_PREFIX(spi_dma_tx_is_active())); + } while (i2s::gd32_spi_dma_tx_is_active()); m_pBuffer = pBuffer; @@ -170,29 +172,31 @@ void WS28xx::FullOn() { // Can be called any time. Make sure the previous transmit is ended. do { __ISB(); - } while (FUNC_PREFIX(spi_dma_tx_is_active())); + } while (i2s::gd32_spi_dma_tx_is_active()); auto *pBuffer = m_pBuffer; m_pBuffer = m_pBlackoutBuffer; - const auto type = m_PixelConfiguration.GetType(); - const auto nCount = m_PixelConfiguration.GetCount(); + auto& pixelConfiguration = PixelConfiguration::Get(); + + const auto type = pixelConfiguration.GetType(); + const auto nCount = pixelConfiguration.GetCount(); - if ((type == Type::APA102) || (type == Type::SK9822) || (type == Type::P9813)) { + if ((type == pixel::Type::APA102) || (type == pixel::Type::SK9822) || (type == pixel::Type::P9813)) { memset(m_pBuffer, 0, 4); for (uint32_t nPixelIndex = 0; nPixelIndex < nCount; nPixelIndex++) { SetPixel(nPixelIndex, 0xFF, 0xFF, 0xFF); } - if ((type == Type::APA102) || (type == Type::SK9822)) { + if ((type == pixel::Type::APA102) || (type == pixel::Type::SK9822)) { memset(&m_pBuffer[m_nBufSize - 4], 0xFF, 4); } else { memset(&m_pBuffer[m_nBufSize - 4], 0, 4); } } else { m_pBuffer[0] = 0x00; - memset(&m_pBuffer[1], type == Type::WS2801 ? 0xFF : m_PixelConfiguration.GetHighCode(), m_nBufSize); + memset(&m_pBuffer[1], type == pixel::Type::WS2801 ? 0xFF : pixelConfiguration.GetHighCode(), m_nBufSize); } Update(); @@ -200,7 +204,7 @@ void WS28xx::FullOn() { // May not be interrupted. do { __ISB(); - } while (FUNC_PREFIX(spi_dma_tx_is_active())); + } while (i2s::gd32_spi_dma_tx_is_active()); m_pBuffer = pBuffer; diff --git a/lib-ws28xx/src/json_get_satus.cpp b/lib-ws28xx/src/json_get_satus.cpp new file mode 100755 index 00000000..080a5681 --- /dev/null +++ b/lib-ws28xx/src/json_get_satus.cpp @@ -0,0 +1,36 @@ +/** + * @file json_get.cpp + * + */ +/* Copyright (C) 2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "pixelconfiguration.h" + +namespace remoteconfig::pixel { +uint32_t json_get_status(char *pOutBuffer, const uint32_t nOutBufferSize) { + auto& pixelConfiguration = PixelConfiguration::Get(); + return static_cast(snprintf(pOutBuffer, nOutBufferSize, "{\"refresh_rate\":\"%u\"}", pixelConfiguration.GetRefreshRate())); +} +} // namespace remoteconfig::pixel diff --git a/lib-ws28xx/src/patterns/pixelpatterns.cpp b/lib-ws28xx/src/patterns/pixelpatterns.cpp index 9d3d09d7..0128bf9d 100644 --- a/lib-ws28xx/src/patterns/pixelpatterns.cpp +++ b/lib-ws28xx/src/patterns/pixelpatterns.cpp @@ -2,7 +2,7 @@ * @file pixelpatterns.cpp * */ -/* Copyright (C) 2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -46,34 +46,33 @@ using namespace pixelpatterns; static constexpr char s_patternName[static_cast(Pattern::LAST)][14] = { "None", "Rainbow cycle", "Theater chase", "Colour wipe", "Scanner", "Fade" }; #if defined (PIXELPATTERNS_MULTI) -WS28xxMulti *PixelPatterns::m_pOutput; +WS28xxMulti *PixelPatterns::s_pOutput; #else -WS28xx *PixelPatterns::m_pOutput; +WS28xx *PixelPatterns::s_pOutput; #endif -uint32_t PixelPatterns::m_nActivePorts; -uint32_t PixelPatterns::m_nCount; -PixelPatterns::PortConfig PixelPatterns::m_PortConfig[pixelpatterns::MAX_PORTS]; -uint32_t *PixelPatterns::m_pScannerColours; +uint32_t PixelPatterns::s_nActivePorts; +PixelPatterns::PortConfig PixelPatterns::s_PortConfig[pixelpatterns::MAX_PORTS]; +uint32_t *PixelPatterns::s_pScannerColours; -PixelPatterns::PixelPatterns(uint32_t nActivePorts) { +PixelPatterns::PixelPatterns(const uint32_t nActivePorts) { DEBUG_ENTRY DEBUG_PRINTF("nActivePorts=%u", nActivePorts); #if defined (PIXELPATTERNS_MULTI) - m_pOutput = WS28xxMulti::Get(); + s_pOutput = WS28xxMulti::Get(); #else - m_pOutput = WS28xx::Get(); + s_pOutput = WS28xx::Get(); #endif - assert(m_pOutput != nullptr); + assert(s_pOutput != nullptr); + + s_nActivePorts = std::min(MAX_PORTS, nActivePorts); - m_nActivePorts = std::min(MAX_PORTS, nActivePorts); - m_nCount = m_pOutput->GetCount(); const auto nMillis = Hardware::Get()->Millis(); for (uint32_t i = 0; i < MAX_PORTS; i++) { - m_PortConfig[i].ActivePattern = Pattern::NONE; - m_PortConfig[i].nLastUpdate = nMillis; - m_PortConfig[i].Direction = Direction::FORWARD; + s_PortConfig[i].ActivePattern = Pattern::NONE; + s_PortConfig[i].nLastUpdate = nMillis; + s_PortConfig[i].Direction = Direction::FORWARD; } DEBUG_EXIT @@ -87,31 +86,14 @@ const char* PixelPatterns::GetName(Pattern pattern) { return "Unknown"; } -void PixelPatterns::Run() { - if (m_pOutput->IsUpdating()) { - return; - } - - auto bIsUpdated = false; - const auto nMillis = Hardware::Get()->Millis(); - - for (uint32_t i = 0; i < m_nActivePorts; i++) { - bIsUpdated |= PortUpdate(i, nMillis); - } - - if (bIsUpdated) { - m_pOutput->Update(); - } -} - bool PixelPatterns::PortUpdate(uint32_t nPortIndex, uint32_t nMillis) { - if ((nMillis - m_PortConfig[nPortIndex].nLastUpdate) < m_PortConfig[nPortIndex].nInterval) { + if ((nMillis - s_PortConfig[nPortIndex].nLastUpdate) < s_PortConfig[nPortIndex].nInterval) { return false; } - m_PortConfig[nPortIndex].nLastUpdate = nMillis; + s_PortConfig[nPortIndex].nLastUpdate = nMillis; - switch (m_PortConfig[nPortIndex].ActivePattern) { + switch (s_PortConfig[nPortIndex].ActivePattern) { case Pattern::RAINBOW_CYCLE: RainbowCycleUpdate(nPortIndex); break; @@ -138,18 +120,18 @@ bool PixelPatterns::PortUpdate(uint32_t nPortIndex, uint32_t nMillis) { void PixelPatterns::RainbowCycle(uint32_t nPortIndex, uint32_t nInterval, pixelpatterns::Direction Direction) { Clear(nPortIndex); - m_PortConfig[nPortIndex].ActivePattern = Pattern::RAINBOW_CYCLE; - m_PortConfig[nPortIndex].nInterval = nInterval; - m_PortConfig[nPortIndex].nTotalSteps= 255; - m_PortConfig[nPortIndex].nPixelIndex = 0; - m_PortConfig[nPortIndex].Direction = Direction; + s_PortConfig[nPortIndex].ActivePattern = Pattern::RAINBOW_CYCLE; + s_PortConfig[nPortIndex].nInterval = nInterval; + s_PortConfig[nPortIndex].nTotalSteps= 255; + s_PortConfig[nPortIndex].nPixelIndex = 0; + s_PortConfig[nPortIndex].Direction = Direction; } void PixelPatterns::RainbowCycleUpdate(uint32_t nPortIndex) { - const auto nIndex = m_PortConfig[nPortIndex].nPixelIndex; + const auto nIndex = s_PortConfig[nPortIndex].nPixelIndex; - for (uint32_t i = 0; i < m_nCount; i++) { - SetPixelColour(nPortIndex, i, Wheel(((i * 256U / m_nCount) + nIndex) & 0xFF)); + for (uint32_t i = 0; i < PixelConfiguration::Get().GetCount(); i++) { + SetPixelColour(nPortIndex, i, Wheel(((i * 256U / PixelConfiguration::Get().GetCount()) + nIndex) & 0xFF)); } Increment(nPortIndex); @@ -158,21 +140,21 @@ void PixelPatterns::RainbowCycleUpdate(uint32_t nPortIndex) { void PixelPatterns::TheaterChase(uint32_t nPortIndex, uint32_t nColour1, uint32_t nColour2, uint32_t nInterval, pixelpatterns::Direction Direction){ Clear(nPortIndex); - m_PortConfig[nPortIndex].ActivePattern = Pattern::THEATER_CHASE; - m_PortConfig[nPortIndex].nInterval = nInterval; - m_PortConfig[nPortIndex].nTotalSteps= m_nCount; - m_PortConfig[nPortIndex].nColour1 = nColour1; - m_PortConfig[nPortIndex].nColour2 = nColour2; - m_PortConfig[nPortIndex].nPixelIndex = 0; - m_PortConfig[nPortIndex].Direction = Direction; + s_PortConfig[nPortIndex].ActivePattern = Pattern::THEATER_CHASE; + s_PortConfig[nPortIndex].nInterval = nInterval; + s_PortConfig[nPortIndex].nTotalSteps= PixelConfiguration::Get().GetCount(); + s_PortConfig[nPortIndex].nColour1 = nColour1; + s_PortConfig[nPortIndex].nColour2 = nColour2; + s_PortConfig[nPortIndex].nPixelIndex = 0; + s_PortConfig[nPortIndex].Direction = Direction; } void PixelPatterns::TheaterChaseUpdate(uint32_t nPortIndex) { - const auto Colour1 = m_PortConfig[nPortIndex].nColour1; - const auto Colour2 = m_PortConfig[nPortIndex].nColour2; - const auto Index = m_PortConfig[nPortIndex].nPixelIndex; + const auto Colour1 = s_PortConfig[nPortIndex].nColour1; + const auto Colour2 = s_PortConfig[nPortIndex].nColour2; + const auto Index = s_PortConfig[nPortIndex].nPixelIndex; - for (uint32_t i = 0; i < m_nCount; i++) { + for (uint32_t i = 0; i < PixelConfiguration::Get().GetCount(); i++) { if ((i + Index) % 3 == 0) { SetPixelColour(nPortIndex, i, Colour1); } else { @@ -186,17 +168,17 @@ void PixelPatterns::TheaterChaseUpdate(uint32_t nPortIndex) { void PixelPatterns::ColourWipe(uint32_t nPortIndex, uint32_t nColour, uint32_t nInterval, pixelpatterns::Direction Direction) { Clear(nPortIndex); - m_PortConfig[nPortIndex].ActivePattern = Pattern::COLOR_WIPE; - m_PortConfig[nPortIndex].nInterval = nInterval; - m_PortConfig[nPortIndex].nTotalSteps= m_nCount; - m_PortConfig[nPortIndex].nColour1 = nColour; - m_PortConfig[nPortIndex].nPixelIndex = 0; - m_PortConfig[nPortIndex].Direction = Direction; + s_PortConfig[nPortIndex].ActivePattern = Pattern::COLOR_WIPE; + s_PortConfig[nPortIndex].nInterval = nInterval; + s_PortConfig[nPortIndex].nTotalSteps= PixelConfiguration::Get().GetCount(); + s_PortConfig[nPortIndex].nColour1 = nColour; + s_PortConfig[nPortIndex].nPixelIndex = 0; + s_PortConfig[nPortIndex].Direction = Direction; } void PixelPatterns::ColourWipeUpdate(uint32_t nPortIndex) { - const auto nColour1 = m_PortConfig[nPortIndex].nColour1; - const auto nIndex = m_PortConfig[nPortIndex].nPixelIndex; + const auto nColour1 = s_PortConfig[nPortIndex].nColour1; + const auto nIndex = s_PortConfig[nPortIndex].nPixelIndex; SetPixelColour(nPortIndex, nIndex, nColour1); Increment(nPortIndex); @@ -205,38 +187,40 @@ void PixelPatterns::ColourWipeUpdate(uint32_t nPortIndex) { void PixelPatterns::Scanner(uint32_t nPortIndex, uint32_t nColour1, uint32_t nInterval) { Clear(nPortIndex); - m_PortConfig[nPortIndex].ActivePattern = Pattern::SCANNER; - m_PortConfig[nPortIndex].nInterval = nInterval; - m_PortConfig[nPortIndex].nTotalSteps= static_cast((m_nCount - 1U) * 2); - m_PortConfig[nPortIndex].nColour1 = nColour1; - m_PortConfig[nPortIndex].nPixelIndex = 0; + const auto nCount = PixelConfiguration::Get().GetCount(); + + s_PortConfig[nPortIndex].ActivePattern = Pattern::SCANNER; + s_PortConfig[nPortIndex].nInterval = nInterval; + s_PortConfig[nPortIndex].nTotalSteps= static_cast((nCount - 1U) * 2); + s_PortConfig[nPortIndex].nColour1 = nColour1; + s_PortConfig[nPortIndex].nPixelIndex = 0; - if (m_pScannerColours == nullptr) { - m_pScannerColours = new uint32_t[m_nCount]; - assert(m_pScannerColours != nullptr); - for (uint32_t i = 0; i < m_nCount; i++) { - m_pScannerColours[i] = 0; + if (s_pScannerColours == nullptr) { + s_pScannerColours = new uint32_t[nCount]; + assert(s_pScannerColours != nullptr); + for (uint32_t i = 0; i < nCount; i++) { + s_pScannerColours[i] = 0; } } } void PixelPatterns::ScannerUpdate(uint32_t nPortIndex) { - const auto nColour1 = m_PortConfig[nPortIndex].nColour1; - const auto nTotalSteps = m_PortConfig[nPortIndex].nTotalSteps; - const auto nIndex = m_PortConfig[nPortIndex].nPixelIndex; + const auto nColour1 = s_PortConfig[nPortIndex].nColour1; + const auto nTotalSteps = s_PortConfig[nPortIndex].nTotalSteps; + const auto nIndex = s_PortConfig[nPortIndex].nPixelIndex; - for (uint32_t i = 0; i < m_nCount; i++) { + for (uint32_t i = 0; i < PixelConfiguration::Get().GetCount(); i++) { if (i == nIndex) { SetPixelColour(nPortIndex, i, nColour1); - m_pScannerColours[i] = nColour1; + s_pScannerColours[i] = nColour1; } else if (i == nTotalSteps - nIndex) { SetPixelColour(nPortIndex, i, nColour1); - m_pScannerColours[i] = nColour1; + s_pScannerColours[i] = nColour1; } else { - const auto nDimColour = DimColour(m_pScannerColours[i]); + const auto nDimColour = DimColour(s_pScannerColours[i]); SetPixelColour(nPortIndex, i, nDimColour); - m_pScannerColours[i] = nDimColour; + s_pScannerColours[i] = nDimColour; } } @@ -246,20 +230,20 @@ void PixelPatterns::ScannerUpdate(uint32_t nPortIndex) { void PixelPatterns::Fade(uint32_t nPortIndex, uint32_t nColour1, uint32_t nColour2, uint32_t nSteps, uint32_t nInterval, pixelpatterns::Direction Direction) { Clear(nPortIndex); - m_PortConfig[nPortIndex].ActivePattern = Pattern::FADE; - m_PortConfig[nPortIndex].nInterval = nInterval; - m_PortConfig[nPortIndex].nTotalSteps= nSteps; - m_PortConfig[nPortIndex].nColour1 = nColour1; - m_PortConfig[nPortIndex].nColour2 = nColour2; - m_PortConfig[nPortIndex].nPixelIndex = 0; - m_PortConfig[nPortIndex].Direction = Direction; + s_PortConfig[nPortIndex].ActivePattern = Pattern::FADE; + s_PortConfig[nPortIndex].nInterval = nInterval; + s_PortConfig[nPortIndex].nTotalSteps= nSteps; + s_PortConfig[nPortIndex].nColour1 = nColour1; + s_PortConfig[nPortIndex].nColour2 = nColour2; + s_PortConfig[nPortIndex].nPixelIndex = 0; + s_PortConfig[nPortIndex].Direction = Direction; } void PixelPatterns::FadeUpdate(uint32_t nPortIndex) { - const auto nColour1 = m_PortConfig[nPortIndex].nColour1; - const auto nColour2 = m_PortConfig[nPortIndex].nColour2; - const auto nTotalSteps = m_PortConfig[nPortIndex].nTotalSteps; - const auto nIndex = m_PortConfig[nPortIndex].nPixelIndex; + const auto nColour1 = s_PortConfig[nPortIndex].nColour1; + const auto nColour2 = s_PortConfig[nPortIndex].nColour2; + const auto nTotalSteps = s_PortConfig[nPortIndex].nTotalSteps; + const auto nIndex = s_PortConfig[nPortIndex].nPixelIndex; const auto nRed = static_cast(((Red(nColour1) * (nTotalSteps - nIndex)) + (Red(nColour2) * nIndex)) / nTotalSteps); const auto nGreen = static_cast(((Green(nColour1) * (nTotalSteps - nIndex)) + (Green(nColour2) * nIndex)) / nTotalSteps); @@ -284,27 +268,27 @@ uint32_t PixelPatterns::Wheel(uint8_t nWheelPos) { } void PixelPatterns::Increment(uint32_t nPortIndex) { - if (m_PortConfig[nPortIndex].Direction == Direction::FORWARD) { - m_PortConfig[nPortIndex].nPixelIndex++; - if (m_PortConfig[nPortIndex].nPixelIndex == m_PortConfig[nPortIndex].nTotalSteps) { - m_PortConfig[nPortIndex].nPixelIndex = 0; + if (s_PortConfig[nPortIndex].Direction == Direction::FORWARD) { + s_PortConfig[nPortIndex].nPixelIndex++; + if (s_PortConfig[nPortIndex].nPixelIndex == s_PortConfig[nPortIndex].nTotalSteps) { + s_PortConfig[nPortIndex].nPixelIndex = 0; } } else { - if (m_PortConfig[nPortIndex].nPixelIndex > 0) { - --m_PortConfig[nPortIndex].nPixelIndex; + if (s_PortConfig[nPortIndex].nPixelIndex > 0) { + --s_PortConfig[nPortIndex].nPixelIndex; } - if (m_PortConfig[nPortIndex].nPixelIndex == 0) { - m_PortConfig[nPortIndex].nPixelIndex = static_cast(m_PortConfig[nPortIndex].nTotalSteps - 1); + if (s_PortConfig[nPortIndex].nPixelIndex == 0) { + s_PortConfig[nPortIndex].nPixelIndex = static_cast(s_PortConfig[nPortIndex].nTotalSteps - 1); } } } void PixelPatterns::Reverse(uint32_t nPortIndex) { - if (m_PortConfig[nPortIndex].Direction == Direction::FORWARD) { - m_PortConfig[nPortIndex].Direction = Direction::REVERSE; - m_PortConfig[nPortIndex].nPixelIndex = static_cast(m_PortConfig[nPortIndex].nTotalSteps - 1); + if (s_PortConfig[nPortIndex].Direction == Direction::FORWARD) { + s_PortConfig[nPortIndex].Direction = Direction::REVERSE; + s_PortConfig[nPortIndex].nPixelIndex = static_cast(s_PortConfig[nPortIndex].nTotalSteps - 1); } else { - m_PortConfig[nPortIndex].Direction = Direction::FORWARD; - m_PortConfig[nPortIndex].nPixelIndex = 0; + s_PortConfig[nPortIndex].Direction = Direction::FORWARD; + s_PortConfig[nPortIndex].nPixelIndex = 0; } } diff --git a/lib-ws28xx/src/patterns/pixeltestpattern.cpp b/lib-ws28xx/src/patterns/pixeltestpattern.cpp index 792750bd..3c98e082 100644 --- a/lib-ws28xx/src/patterns/pixeltestpattern.cpp +++ b/lib-ws28xx/src/patterns/pixeltestpattern.cpp @@ -2,7 +2,7 @@ * @file pixeltestpattern.cpp * */ -/* Copyright (C) 2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -25,5 +25,4 @@ #include "pixeltestpattern.h" -pixelpatterns::Pattern PixelTestPattern::s_Pattern; -PixelTestPattern *PixelTestPattern::s_pThis = nullptr; +PixelTestPattern *PixelTestPattern::s_pThis; diff --git a/lib-ws28xx/src/pixel/ws28xx.cpp b/lib-ws28xx/src/pixel/ws28xx.cpp index 3dd73aa0..4db2cd30 100644 --- a/lib-ws28xx/src/pixel/ws28xx.cpp +++ b/lib-ws28xx/src/pixel/ws28xx.cpp @@ -23,6 +23,10 @@ * THE SOFTWARE. */ +#if defined (DEBUG_PIXEL) +# undef NDEBUG +#endif + #if !defined(__clang__) // Needed for compiling on MacOS # pragma GCC push_options # pragma GCC optimize ("O3") @@ -40,14 +44,15 @@ #include "gamma/gamma_tables.h" void WS28xx::SetColorWS28xx(uint32_t nOffset, uint8_t nValue) { - assert(m_PixelConfiguration.GetType() != pixel::Type::WS2801); + auto& pixelConfiguration = PixelConfiguration::Get(); + assert(pixelConfiguration.GetType() != pixel::Type::WS2801); assert(m_pBuffer != nullptr); assert(nOffset + 7 < m_nBufSize); nOffset += 1; - const auto nLowCode = m_PixelConfiguration.GetLowCode(); - const auto nHighCode = m_PixelConfiguration.GetHighCode(); + const auto nLowCode = pixelConfiguration.GetLowCode(); + const auto nHighCode = pixelConfiguration.GetHighCode(); for (uint8_t mask = 0x80; mask != 0; mask = static_cast(mask >> 1)) { if (nValue & mask) { @@ -60,15 +65,18 @@ void WS28xx::SetColorWS28xx(uint32_t nOffset, uint8_t nValue) { } void WS28xx::SetPixel(uint32_t nPixelIndex, uint8_t nRed, uint8_t nGreen, uint8_t nBlue) { - assert(nPixelIndex < m_PixelConfiguration.GetCount()); + auto& pixelConfiguration = PixelConfiguration::Get(); + assert(nPixelIndex < pixelConfiguration.GetCount()); - const auto pGammaTable = m_PixelConfiguration.GetGammaTable(); +#if defined(CONFIG_PIXELDMX_ENABLE_GAMMATABLE) + const auto pGammaTable = pixelConfiguration.GetGammaTable(); nRed = pGammaTable[nRed]; nGreen = pGammaTable[nGreen]; nBlue = pGammaTable[nBlue]; +#endif - if (m_PixelConfiguration.IsRTZProtocol()) { + if (pixelConfiguration.IsRTZProtocol()) { const auto nOffset = nPixelIndex * 24U; SetColorWS28xx(nOffset, nRed); @@ -79,7 +87,7 @@ void WS28xx::SetPixel(uint32_t nPixelIndex, uint8_t nRed, uint8_t nGreen, uint8_ assert(m_pBuffer != nullptr); - const auto type = m_PixelConfiguration.GetType(); + const auto type = pixelConfiguration.GetType(); if (type == pixel::Type::WS2801) { const auto nOffset = nPixelIndex * 3U; @@ -96,7 +104,7 @@ void WS28xx::SetPixel(uint32_t nPixelIndex, uint8_t nRed, uint8_t nGreen, uint8_ const auto nOffset = 4U + (nPixelIndex * 4U); assert(nOffset + 3U < m_nBufSize); - m_pBuffer[nOffset] = m_PixelConfiguration.GetGlobalBrightness(); + m_pBuffer[nOffset] = pixelConfiguration.GetGlobalBrightness(); m_pBuffer[nOffset + 1] = nRed; m_pBuffer[nOffset + 2] = nGreen; m_pBuffer[nOffset + 3] = nBlue; @@ -123,15 +131,17 @@ void WS28xx::SetPixel(uint32_t nPixelIndex, uint8_t nRed, uint8_t nGreen, uint8_ } void WS28xx::SetPixel(uint32_t nPixelIndex, uint8_t nRed, uint8_t nGreen, uint8_t nBlue, uint8_t nWhite) { - assert(nPixelIndex < m_PixelConfiguration.GetCount()); - assert(m_PixelConfiguration.GetType() == pixel::Type::SK6812W); + assert(nPixelIndex < PixelConfiguration::Get().GetCount()); + assert(PixelConfiguration::Get().GetType() == pixel::Type::SK6812W); - const auto pGammaTable = m_PixelConfiguration.GetGammaTable(); +#if defined(CONFIG_PIXELDMX_ENABLE_GAMMATABLE) + const auto pGammaTable = pixelConfiguration.GetGammaTable(); nRed = pGammaTable[nRed]; nGreen = pGammaTable[nGreen]; nBlue = pGammaTable[nBlue]; nWhite = pGammaTable[nWhite]; +#endif const auto nOffset = nPixelIndex * 32U; diff --git a/lib-ws28xx/src/pixelconfiguration.cpp b/lib-ws28xx/src/pixelconfiguration.cpp deleted file mode 100644 index bf079081..00000000 --- a/lib-ws28xx/src/pixelconfiguration.cpp +++ /dev/null @@ -1,145 +0,0 @@ -/** - * @file pixelconfiguration.cpp - * - */ -/* Copyright (C) 2021-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#if !defined(__clang__) // Needed for compiling on MacOS -# pragma GCC push_options -# pragma GCC optimize ("Os") -#endif - -#include - -#include "pixelconfiguration.h" -#include "pixeltype.h" -#include "gamma/gamma_tables.h" - -#include "debug.h" - -using namespace pixel; - -void PixelConfiguration::Validate(uint32_t& nLedsPerPixel) { - DEBUG_ENTRY - - if (m_type == Type::SK6812W) { - m_nCount = m_nCount <= static_cast(max::ledcount::RGBW) ? m_nCount : static_cast(max::ledcount::RGBW); - nLedsPerPixel = 4; - } else { - m_nCount = m_nCount <= static_cast(max::ledcount::RGB) ? m_nCount : static_cast(max::ledcount::RGB); - nLedsPerPixel = 3; - } - - if ((m_type == Type::APA102) || (m_type == Type::SK9822)){ - if (m_nGlobalBrightness > 0x1F) { - m_nGlobalBrightness = 0xFF; - } else { - m_nGlobalBrightness = 0xE0 | (m_nGlobalBrightness & 0x1F); - } - } - - if ((m_type == Type::WS2801) || (m_type == Type::APA102) || (m_type == Type::SK9822) || (m_type == Type::P9813)) { - m_bIsRTZProtocol = false; - - if (m_map == Map::UNDEFINED) { - m_map = Map::RGB; - } - - if (m_type == Type::P9813) { - if (m_nClockSpeedHz == 0) { - m_nClockSpeedHz = spi::speed::p9813::default_hz; - } else if (m_nClockSpeedHz > spi::speed::p9813::max_hz) { - m_nClockSpeedHz = spi::speed::p9813::max_hz; - } - } else { - if (m_nClockSpeedHz == 0) { - m_nClockSpeedHz = spi::speed::ws2801::default_hz; - } else if (m_nClockSpeedHz > spi::speed::ws2801::max_hz) { - m_nClockSpeedHz = spi::speed::ws2801::max_hz; - } - } - } else { - m_bIsRTZProtocol = true; - - if (m_map == Map::UNDEFINED) { - m_map = PixelType::GetMap(m_type); - } - - if (m_nLowCode >= m_nHighCode) { - m_nLowCode = 0; - m_nHighCode = 0; - } - - uint8_t nLowCode, nHighCode; - - GetTxH(m_type, nLowCode, nHighCode); - - if (m_nLowCode == 0) { - m_nLowCode = nLowCode; - } - - if (m_nHighCode == 0) { - m_nHighCode = nHighCode; - } - - m_nClockSpeedHz = 6400000; // 6.4MHz / 8 bits = 800Hz - } - - if (m_bEnableGammaCorrection) { - if (m_nGammaValue == 0) { - m_pGammaTable = gamma::get_table_default(m_type); - } else { - m_pGammaTable = gamma::get_table(m_nGammaValue); - } - } else { - m_pGammaTable = gamma10_0; - } - - DEBUG_EXIT -} - -void PixelConfiguration::GetTxH(Type type, uint8_t &nLowCode, uint8_t &nHighCode) { - nLowCode = 0xC0; - nHighCode = (type == Type::WS2812B ? 0xF8 : - (((type == Type::UCS1903) || (type == Type::UCS2903) || (type == Type::CS8812)) ? 0xFC : 0xF0)); -} - -#include - -void PixelConfiguration::Print() { - printf("Pixel configuration\n"); - printf(" Type : %s [%d]\n", PixelType::GetType(m_type), static_cast(m_type)); - printf(" Count : %d\n", m_nCount); - - if (m_bIsRTZProtocol) { - printf(" Mapping : %s [%d]\n", PixelType::GetMap(m_map), static_cast(m_map)); - printf(" T0H : %.2f [0x%X]\n", PixelType::ConvertTxH(m_nLowCode), m_nLowCode); - printf(" T1H : %.2f [0x%X]\n", PixelType::ConvertTxH(m_nHighCode), m_nHighCode); - } else { - if ((m_type == Type::APA102) || (m_type == Type::SK9822)){ - printf(" GlobalBrightness: %u\n", m_nGlobalBrightness); - } - } - - printf(" Gamma correction %s\n", m_bEnableGammaCorrection ? "Yes" : "No"); - printf(" Clock: %u Hz\n", m_nClockSpeedHz); -} diff --git a/lib-ws28xx/src/pixeltype.cpp b/lib-ws28xx/src/pixeltype.cpp index 37be1cfb..a4351151 100644 --- a/lib-ws28xx/src/pixeltype.cpp +++ b/lib-ws28xx/src/pixeltype.cpp @@ -2,7 +2,7 @@ * @file pixeltype.cpp * */ -/* Copyright (C) 2021 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,20 +23,20 @@ * THE SOFTWARE. */ -#if !defined(__clang__) // Needed for compiling on MacOS +#if defined(__GNUC__) && !defined(__clang__) ///< Needed for macOS # pragma GCC push_options # pragma GCC optimize ("Os") #endif #include #include +#include #include #include "pixeltype.h" -using namespace pixel; - -const char PixelType::TYPES[static_cast(Type::UNDEFINED)][TYPES_MAX_NAME_LENGTH] = +namespace pixel { +const char TYPES[static_cast(pixel::Type::UNDEFINED)][pixel::TYPES_MAX_NAME_LENGTH] = { "WS2801\0", // 1 "WS2811\0", "WS2812\0", "WS2812B", "WS2813\0", "WS2815\0", // 5 "SK6812\0", "SK6812W", // 2 @@ -46,130 +46,68 @@ const char PixelType::TYPES[static_cast(Type::UNDEFINED)][TYPES_MAX_NA "P9813", // 1 }; // = 14 -const char PixelType::MAPS[static_cast(Map::UNDEFINED)][4] = { "RGB", "RBG", "GRB", "GBR", "BRG", "BGR"}; +const char MAPS[static_cast(pixel::Map::UNDEFINED)][4] = { "RGB", "RBG", "GRB", "GBR", "BRG", "BGR"}; -const char *PixelType::GetType(Type type) { - if (type < Type::UNDEFINED) { +const char *pixel_get_type(pixel::Type type) { + if (type < pixel::Type::UNDEFINED) { return TYPES[static_cast(type)]; } return "Unknown"; } -Type PixelType::GetType(const char *pString) { +pixel::Type pixel_get_type(const char *pString) { assert(pString != nullptr); + uint32_t index = 0; - for (uint32_t i = 0; i < static_cast(Type::UNDEFINED); i++) { - if (strcasecmp(pString, TYPES[i]) == 0) { - return static_cast(i); + for (const char (&type)[pixel::TYPES_MAX_NAME_LENGTH] : TYPES) { + if (strcasecmp(pString, type) == 0) { + return static_cast(index); } + ++index; } - return Type::UNDEFINED; + return pixel::Type::UNDEFINED; } -Map PixelType::GetMap(const char *pString) { +pixel::Map pixel_get_map(const char *pString) { assert(pString != nullptr); + uint32_t index = 0; - for (uint32_t nIndex = 0; nIndex < static_cast(Map::UNDEFINED); nIndex++) { - if (strncasecmp(MAPS[nIndex], pString, 3) == 0) { - return static_cast(nIndex); + for (const char (&map)[4] : MAPS) { + if (strncasecmp(map, pString, 3) == 0) { + return static_cast(index); } + ++index; } - return Map::UNDEFINED; + return pixel::Map::UNDEFINED; } -const char *PixelType::GetMap(Map map) { - if (map < Map::UNDEFINED) { +const char *pixel_get_map(pixel::Map map) { + if (map < pixel::Map::UNDEFINED) { return MAPS[static_cast(map)]; } return "Undefined"; } +} // namespace pixel -Map PixelType::GetMap(Type type) { - if ((type == Type::WS2811) || (type == Type::UCS2903)) { - return Map::RGB; - } - - if (type == Type::UCS1903) { - return Map::BRG; - } - - if (type == Type::CS8812) { - return Map::BGR; - } - - return Map::GRB; -} - -static constexpr auto F_INTERVAL = 0.15625f; - -float PixelType::ConvertTxH(uint8_t nCode) { - switch (nCode) { - case 0x80: - return F_INTERVAL * 1; - break; - case 0xC0: - return F_INTERVAL * 2; - break; - case 0xE0: - return F_INTERVAL * 3; - break; - case 0xF0: - return F_INTERVAL * 4; - break; - case 0xF8: - return F_INTERVAL * 5; - break; - case 0xFC: - return F_INTERVAL * 6; - break; - case 0xFE: - return F_INTERVAL * 7; - break; - default: - return 0; - break; - } - - assert(0); - __builtin_unreachable(); -} - -uint8_t PixelType::ConvertTxH(float fTxH) { - if (fTxH < 0.5f * F_INTERVAL) { - return 0x00; - } - - if (fTxH < 1.5f * F_INTERVAL) { - return 0x80; - } - - if (fTxH < 2.5f * F_INTERVAL) { - return 0xC0; - } - - if (fTxH < 3.5f * F_INTERVAL) { - return 0xE0; - } - - if (fTxH < 4.5f * F_INTERVAL) { - return 0xF0; - } +namespace remoteconfig::pixel { +uint32_t json_get_types(char *pOutBuffer, const uint32_t nOutBufferSize) { + const auto nBufferSize = nOutBufferSize - 2U; + auto nLength = static_cast(snprintf(pOutBuffer, nBufferSize, "{\"types\":[" )); - if (fTxH < 5.5f * F_INTERVAL) { - return 0xF8; + for (const char (&type)[::pixel::TYPES_MAX_NAME_LENGTH] : ::pixel::TYPES) { + nLength += static_cast(snprintf(&pOutBuffer[nLength], nBufferSize - nLength, "\"%s\",", type)); } - if (fTxH < 6.5f * F_INTERVAL) { - return 0xFC; - } + nLength--; - if (fTxH < 7.5f * F_INTERVAL) { - return 0xFE; - } + pOutBuffer[nLength++] = ']'; + pOutBuffer[nLength++] = '}'; - return 0x00; + assert(nLength <= nOutBufferSize); + return nLength; } +} // namespace remoteconfig::pixel diff --git a/lib-ws28xxdmx/.cproject b/lib-ws28xxdmx/.cproject index 8dfc395b..4d2fb955 100644 --- a/lib-ws28xxdmx/.cproject +++ b/lib-ws28xxdmx/.cproject @@ -30,11 +30,9 @@ - diff --git a/lib-ws28xxdmx/Makefile.GD32 b/lib-ws28xxdmx/Makefile.GD32 index 4fe9d4a3..1d567e48 100644 --- a/lib-ws28xxdmx/Makefile.GD32 +++ b/lib-ws28xxdmx/Makefile.GD32 @@ -1,5 +1,4 @@ -DEFINES=USE_SPI_DMA -DEFINES+=NDEBUG +DEFINES=NDEBUG EXTRA_INCLUDES=../lib-ws28xx/include ../lib-lightset/include ../lib-properties/include diff --git a/lib-ws28xxdmx/Rules.mk b/lib-ws28xxdmx/Rules.mk index 63080529..4d22bc10 100644 --- a/lib-ws28xxdmx/Rules.mk +++ b/lib-ws28xxdmx/Rules.mk @@ -5,14 +5,21 @@ EXTRA_INCLUDES+=../lib-properties/include EXTRA_SRCDIR+=src/params ifneq ($(MAKE_FLAGS),) - ifneq (,$(findstring ENABLE_RDM_MANUFACTURER_PIDS,$(MAKE_FLAGS))) + ifneq (,$(findstring OUTPUT_DMX_PIXEL,$(MAKE_FLAGS))) + EXTRA_SRCDIR+=src/dmx + endif + ifneq (,$(findstring OUTPUT_DMX_PIXEL_MULTI,$(MAKE_FLAGS))) + EXTRA_SRCDIR+=src/dmxmulti + endif + ifneq (,$(findstring CONFIG_RDM_ENABLE_MANUFACTURER_PIDS,$(MAKE_FLAGS))) EXTRA_INCLUDES+=../lib-rdm/include EXTRA_SRCDIR+=src/rdm endif else DEFINES+=CONFIG_PIXELDMX_MAX_PORTS=8 - DEFINES+=ENABLE_RDM_MANUFACTURER_PIDS + DEFINES+=LIGHTSET_PORTS=32 + DEFINES+=CONFIG_RDM_ENABLE_MANUFACTURER_PIDS CONFIG_RDM_MANUFACTURER_PIDS_SET DEFINES+=OUTPUT_DMX_PIXEL EXTRA_INCLUDES+=../lib-rdm/include - EXTRA_SRCDIR+=src/rdm + EXTRA_SRCDIR+=src/dmx src/dmxmulti src/rdm endif \ No newline at end of file diff --git a/lib-ws28xxdmx/include/pixeldmxconfiguration.h b/lib-ws28xxdmx/include/pixeldmxconfiguration.h index 5a24a343..49bfbb19 100644 --- a/lib-ws28xxdmx/include/pixeldmxconfiguration.h +++ b/lib-ws28xxdmx/include/pixeldmxconfiguration.h @@ -2,7 +2,7 @@ * @file pixeldmxconfiguration.h * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -22,24 +22,44 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ +/** + * Static Local Variables: + * Since C++11, the initialization of function-local static variables, is guaranteed to be thread-safe. + * This means that even if multiple threads attempt to access Get() simultaneously, + * the C++ runtime ensures that the instance is initialized only once. + */ #ifndef PIXELDMXCONFIGURATION_H_ #define PIXELDMXCONFIGURATION_H_ #include +#include +#include +#include #include "pixelconfiguration.h" +#include "debug.h" + namespace pixeldmxconfiguration { struct PortInfo { - uint32_t nBeginIndexPort[4]; - uint32_t nProtocolPortIndexLast; + uint16_t nBeginIndexPort[4]; + uint16_t nProtocolPortIndexLast; }; } // namespace pixeldmxconfiguration class PixelDmxConfiguration: public PixelConfiguration { public: - void SetOutputPorts(uint32_t nOutputPorts) { + PixelDmxConfiguration() { + DEBUG_ENTRY + + assert(s_pThis == nullptr); + s_pThis = this; + + DEBUG_EXIT + } + + void SetOutputPorts(const uint16_t nOutputPorts) { m_nOutputPorts = nOutputPorts; } @@ -47,7 +67,7 @@ class PixelDmxConfiguration: public PixelConfiguration { return m_nOutputPorts; } - void SetGroupingCount(uint16_t nGroupingCount) { + void SetGroupingCount(const uint16_t nGroupingCount) { m_nGroupingCount = nGroupingCount; } @@ -63,24 +83,98 @@ class PixelDmxConfiguration: public PixelConfiguration { return m_nUniverses; } - void SetDmxStartAddress(uint16_t nDmxStartAddress) { + pixeldmxconfiguration::PortInfo& GetPortInfo() { + return m_portInfo; + } + + void SetDmxStartAddress(const uint16_t nDmxStartAddress) { m_nDmxStartAddress = nDmxStartAddress; } - uint16_t GetDmxStartAddress() const { + uint32_t GetDmxStartAddress() const { return m_nDmxStartAddress; } - void Validate(uint32_t nPortsMax, uint32_t& nLedsPerPixel, pixeldmxconfiguration::PortInfo& portInfo); + uint32_t GetDmxFootprint() const { + return m_nDmxFootprint; + } + + void Validate(const uint32_t nPortsMax) { + DEBUG_ENTRY + + PixelConfiguration::Validate(); + + if (!PixelConfiguration::IsRTZProtocol()) { + if (!((PixelConfiguration::GetType() == pixel::Type::WS2801) || (PixelConfiguration::GetType() == pixel::Type::APA102) || (PixelConfiguration::GetType() == pixel::Type::SK9822))) { + PixelConfiguration::SetType(pixel::Type::WS2801); + } + + PixelConfiguration::Validate(); + } + + m_portInfo.nBeginIndexPort[0] = 0; + + if (PixelConfiguration::GetType() == pixel::Type::SK6812W) { + m_portInfo.nBeginIndexPort[1] = 128; + m_portInfo.nBeginIndexPort[2] = 256; + m_portInfo.nBeginIndexPort[3] = 384; + } else { + m_portInfo.nBeginIndexPort[1] = 170; + m_portInfo.nBeginIndexPort[2] = 340; + m_portInfo.nBeginIndexPort[3] = 510; + } + + if ((m_nGroupingCount == 0) || (m_nGroupingCount > PixelConfiguration::GetCount())) { + m_nGroupingCount = PixelConfiguration::GetCount(); + } + + m_nGroups = PixelConfiguration::GetCount() / m_nGroupingCount; + m_nOutputPorts = std::min(nPortsMax, m_nOutputPorts); + m_nUniverses = (1U + (m_nGroups / (1U + m_portInfo.nBeginIndexPort[1]))); + m_nDmxFootprint = PixelConfiguration::GetLedsPerPixel() * m_nGroups; + + if (nPortsMax == 1) { + m_portInfo.nProtocolPortIndexLast = static_cast(m_nGroups / (1U + m_portInfo.nBeginIndexPort[1])); + } else { +#if defined (NODE_DDP_DISPLAY) + m_portInfo.nProtocolPortIndexLast = static_cast(((m_nOutputPorts - 1U) * 4U) + m_nUniverses - 1U); +#else + m_portInfo.nProtocolPortIndexLast = static_cast((m_nOutputPorts * m_nUniverses) - 1U); +#endif + } + + DEBUG_EXIT + } + + void Print() { + PixelConfiguration::Print(); + puts("Pixel DMX configuration"); + printf(" Outputs : %u\n", m_nOutputPorts); + printf(" Grouping count : %u [Groups : %u]\n", m_nGroupingCount, m_nGroups); + printf(" Universes : %u\n", m_nUniverses); + printf(" DmxFootprint : %u\n", m_nDmxFootprint); + +#ifndef NDEBUG + const auto& beginIndexPort = m_portInfo.nBeginIndexPort; + printf(" %u:%u:%u:%u -> %u\n", beginIndexPort[0], beginIndexPort[1], beginIndexPort[2], beginIndexPort[3], m_portInfo.nProtocolPortIndexLast); +#endif + } - void Print(); + static PixelDmxConfiguration& Get() { + assert(s_pThis != nullptr); // Ensure that s_pThis is valid + return *s_pThis; + } private: uint32_t m_nOutputPorts { 1 }; uint32_t m_nGroupingCount { 1 }; uint32_t m_nGroups { pixel::defaults::COUNT }; - uint32_t m_nUniverses; - uint16_t m_nDmxStartAddress { 1 }; + uint32_t m_nUniverses { 0 }; + uint32_t m_nDmxStartAddress { 1 }; + uint32_t m_nDmxFootprint { 0 }; + pixeldmxconfiguration::PortInfo m_portInfo; + + static inline PixelDmxConfiguration *s_pThis { nullptr }; }; #endif /* PIXELDMXCONFIGURATION_H_ */ diff --git a/lib-ws28xxdmx/include/pixeldmxparams.h b/lib-ws28xxdmx/include/pixeldmxparams.h index 59eab6c4..9257d6c0 100644 --- a/lib-ws28xxdmx/include/pixeldmxparams.h +++ b/lib-ws28xxdmx/include/pixeldmxparams.h @@ -2,7 +2,7 @@ * @file pixeldmxparams.h * */ -/* Copyright (C) 2017-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2017-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"); to deal @@ -29,6 +29,7 @@ #include #include "pixeldmxconfiguration.h" +#include "configstore.h" #if !defined (CONFIG_PIXELDMX_MAX_PORTS) # error CONFIG_PIXELDMX_MAX_PORTS is not defined @@ -71,24 +72,25 @@ struct Mask { static constexpr auto HIGH_CODE = (1U << 11); static constexpr auto START_UNI_PORT_1 = (1U << 12); }; -} // pixeldmxparams name +} // pixeldmxparams class PixelDmxParamsStore { public: - virtual ~PixelDmxParamsStore() { + static void Update(const struct pixeldmxparams::Params *pParams) { + ConfigStore::Get()->Update(configstore::Store::WS28XXDMX, pParams, sizeof(struct pixeldmxparams::Params)); } - virtual void Update(const struct pixeldmxparams::Params *pWS28xxDmxParams)=0; - virtual void Copy(struct pixeldmxparams::Params *pWS28xxDmxParams)=0; + static void Copy(struct pixeldmxparams::Params *pParams) { + ConfigStore::Get()->Copy(configstore::Store::WS28XXDMX, pParams, sizeof(struct pixeldmxparams::Params)); + } }; class PixelDmxParams { public: - PixelDmxParams(PixelDmxParamsStore *pPixelDmxParamsStore); - ~PixelDmxParams() { - } + PixelDmxParams(); + ~PixelDmxParams() = default; - bool Load(); + void Load(); void Load(const char *pBuffer, uint32_t nLength); void Builder(const struct pixeldmxparams::Params *pParams, char *pBuffer, uint32_t nLength, uint32_t& nSize); @@ -96,14 +98,12 @@ class PixelDmxParams { Builder(nullptr, pBuffer, nLength, nSize); } - void Set(PixelDmxConfiguration *pPixelDmxConfiguration); - - void Dump(); + void Set(); uint16_t GetStartUniversePort(uint32_t nOutputPortIndex, bool& isSet) const { if (nOutputPortIndex < pixeldmxparams::MAX_PORTS) { isSet = isMaskSet(pixeldmxparams::Mask::START_UNI_PORT_1 << nOutputPortIndex); - return m_pixelDmxParams.nStartUniverse[nOutputPortIndex]; + return m_Params.nStartUniverse[nOutputPortIndex]; } isSet = false; @@ -111,20 +111,20 @@ class PixelDmxParams { } uint8_t GetTestPattern() const { - return m_pixelDmxParams.nTestPattern; + return m_Params.nTestPattern; } static void staticCallbackFunction(void *p, const char *s); private: + void Dump(); void callbackFunction(const char *pLine); bool isMaskSet(uint32_t nMask) const { - return (m_pixelDmxParams.nSetList & nMask) == nMask; + return (m_Params.nSetList & nMask) == nMask; } private: - PixelDmxParamsStore *m_pPixelDmxParamsStore; - pixeldmxparams::Params m_pixelDmxParams; + pixeldmxparams::Params m_Params; }; #endif /* PIXELDMXPARAMS_H_ */ diff --git a/lib-ws28xxdmx/include/pixeldmxparamsrdm.h b/lib-ws28xxdmx/include/pixeldmxparamsrdm.h index 5cac0228..6edc66eb 100644 --- a/lib-ws28xxdmx/include/pixeldmxparamsrdm.h +++ b/lib-ws28xxdmx/include/pixeldmxparamsrdm.h @@ -2,7 +2,7 @@ * @file pixeldmxparamsrdm.h * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -27,10 +27,12 @@ #define PIXELDMXPARAMSRDM_H_ #include +#include -#include "pixeldmxstore.h" #include "lightset.h" +#include "debug.h" + namespace pixeldmx { namespace paramsdmx { enum class SlotInfo { @@ -40,17 +42,31 @@ static constexpr auto DMX_FOOTPRINT = static_cast(SlotInfo::LAST); } // namespace paramsdmx } // namespace pixeldmx -class PixelDmxParamsRdm: public LightSet { +class PixelDmxParamsRdm final: public LightSet { public: - PixelDmxParamsRdm(PixelDmxStore *pWS28xxDmxStore); + PixelDmxParamsRdm() { + DEBUG_ENTRY + DEBUG_EXIT + } + + void Start([[maybe_unused]] uint32_t nPortIndex) override { + DEBUG_ENTRY + assert(nPortIndex == 0); + DEBUG_EXIT + } + + void Stop([[maybe_unused]] uint32_t nPortIndex) override { + DEBUG_ENTRY + assert(nPortIndex == 0); + DEBUG_EXIT + } + + void SetData(const uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength, const bool doUpdate = true) override; - void Start(const uint32_t nPortIndex) override; - void Stop(const uint32_t nPortIndex) override; - void SetData(uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength, const bool doUpdate = true) override; - void Sync(__attribute__((unused)) const uint32_t nPortIndex) override {} - void Sync(__attribute__((unused)) const bool doForce) override {} + void Sync([[maybe_unused]] const uint32_t nPortIndex) override {} + void Sync() override {} - bool SetDmxStartAddress(__attribute__((unused)) uint16_t nDmxStartAddress) override { + bool SetDmxStartAddress([[maybe_unused]] uint16_t nDmxStartAddress) override { return false; } @@ -62,13 +78,21 @@ class PixelDmxParamsRdm: public LightSet { return pixeldmx::paramsdmx::DMX_FOOTPRINT; } - bool GetSlotInfo(uint16_t nSlotOffset, lightset::SlotInfo &tSlotInfo) override; + bool GetSlotInfo(uint16_t nSlotOffset, lightset::SlotInfo &slotInfo) override { + if (nSlotOffset >= pixeldmx::paramsdmx::DMX_FOOTPRINT) { + return false; + } + + slotInfo.nType = 0x00; // ST_PRIMARY + slotInfo.nCategory = 0xFFFF; // SD_UNDEFINED; + + return true; + } void Display(const uint8_t *pData) __attribute__((weak)); private: - static PixelDmxStore *s_pWS28xxDmxStore; - static uint8_t s_Data; + uint8_t m_Data { 0 }; }; #endif /* PIXELDMXPARAMSRDM_H_ */ diff --git a/lib-ws28xxdmx/include/pixeldmxstore.h b/lib-ws28xxdmx/include/pixeldmxstore.h old mode 100644 new mode 100755 index 58476b9e..b9af4ef5 --- a/lib-ws28xxdmx/include/pixeldmxstore.h +++ b/lib-ws28xxdmx/include/pixeldmxstore.h @@ -2,7 +2,7 @@ * @file pixeldmxstore.h * */ -/* Copyright (C) 2019-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2018-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,19 +26,37 @@ #ifndef PIXELDMXSTORE_H_ #define PIXELDMXSTORE_H_ +#include #include +#include "pixeldmxparams.h" +#include "configstore.h" + class PixelDmxStore { public: - virtual ~PixelDmxStore() { + static void SaveType(uint8_t nType) { + ConfigStore::Get()->Update(configstore::Store::WS28XXDMX, offsetof(struct pixeldmxparams::Params, nType), &nType, sizeof(uint8_t), pixeldmxparams::Mask::TYPE); + } + + static void SaveCount(uint16_t nCount) { + ConfigStore::Get()->Update(configstore::Store::WS28XXDMX, offsetof(struct pixeldmxparams::Params, nCount), &nCount, sizeof(uint16_t), pixeldmxparams::Mask::COUNT); + } + + static void SaveGroupingCount(uint16_t nGroupingCount) { + ConfigStore::Get()->Update(configstore::Store::WS28XXDMX, offsetof(struct pixeldmxparams::Params, nGroupingCount), &nGroupingCount, sizeof(uint16_t), pixeldmxparams::Mask::GROUPING_COUNT); } - virtual void SaveType(uint8_t nType)=0; - virtual void SaveCount(uint16_t nCount)=0; - virtual void SaveGroupingCount(uint16_t nGroupingCount)=0; - virtual void SaveMap(uint8_t nMap)=0; - virtual void SaveTestPattern(uint8_t nTestPattern)=0; - virtual void SaveDmxStartAddress(uint16_t nDmxStartAddress)=0; + static void SaveMap(uint8_t nMap) { + ConfigStore::Get()->Update(configstore::Store::WS28XXDMX, offsetof(struct pixeldmxparams::Params, nMap), &nMap, sizeof(uint8_t), pixeldmxparams::Mask::MAP); + } + + static void SaveTestPattern(uint8_t nTestPattern) { + ConfigStore::Get()->Update(configstore::Store::WS28XXDMX, offsetof(struct pixeldmxparams::Params, nTestPattern), &nTestPattern, sizeof(uint8_t), pixeldmxparams::Mask::TEST_PATTERN); + } + + static void SaveDmxStartAddress(uint16_t nDmxStartAddress) { + ConfigStore::Get()->Update(configstore::Store::WS28XXDMX, offsetof(struct pixeldmxparams::Params, nDmxStartAddress), &nDmxStartAddress, sizeof(uint16_t), pixeldmxparams::Mask::DMX_START_ADDRESS); + } }; #endif /* PIXELDMXSTORE_H_ */ diff --git a/lib-ws28xxdmx/include/ws28xxdmx.h b/lib-ws28xxdmx/include/ws28xxdmx.h index b131d398..80f0fe42 100644 --- a/lib-ws28xxdmx/include/ws28xxdmx.h +++ b/lib-ws28xxdmx/include/ws28xxdmx.h @@ -2,7 +2,7 @@ * @file ws28xxdmx.h * */ -/* Copyright (C) 2016-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2016-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,31 +32,28 @@ #include "lightset.h" #include "ws28xx.h" + #include "pixeldmxconfiguration.h" #include "pixelpatterns.h" -#include "pixeldmxstore.h" -#include "pixeldmxhandler.h" class WS28xxDmx final: public LightSet { public: - WS28xxDmx(PixelDmxConfiguration& pixelDmxConfiguration); + WS28xxDmx(); ~WS28xxDmx() override; void Start(const uint32_t nPortIndex) override; void Stop(const uint32_t nPortIndex) override; - void SetData(uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength, const bool doUpdate = true) override; - void Sync(__attribute__((unused)) const uint32_t nPortIndex) override {} - void Sync(const bool doForce) override { - if (__builtin_expect((!doForce), 1)) { - assert(m_pWS28xx != nullptr); - m_pWS28xx->Update(); - } + void SetData(const uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength, const bool doUpdate = true) override; + void Sync([[maybe_unused]] const uint32_t nPortIndex) override {} + void Sync() override { + assert(m_pWS28xx != nullptr); + m_pWS28xx->Update(); } #if defined (OUTPUT_HAVE_STYLESWITCH) - void SetOutputStyle(__attribute__((unused)) const uint32_t nPortIndex, __attribute__((unused)) const lightset::OutputStyle outputStyle) override {} - lightset::OutputStyle GetOutputStyle(__attribute__((unused)) const uint32_t nPortIndex) const override { + void SetOutputStyle([[maybe_unused]] const uint32_t nPortIndex, [[maybe_unused]] const lightset::OutputStyle outputStyle) override {} + lightset::OutputStyle GetOutputStyle([[maybe_unused]] const uint32_t nPortIndex) const override { return lightset::OutputStyle::DELTA; } #endif @@ -65,50 +62,18 @@ class WS28xxDmx final: public LightSet { void FullOn() override; void Print() override { - m_pixelDmxConfiguration.Print(); - } - - void SetWS28xxDmxStore(PixelDmxStore *pWS28xxDmxStore) { - m_pWS28xxDmxStore = pWS28xxDmxStore; - } - - void SetPixelDmxHandler(PixelDmxHandler *pPixelDmxHandler) { - m_pPixelDmxHandler = pPixelDmxHandler; - } - - pixel::Type GetType() const { - return m_pixelDmxConfiguration.GetType(); - } - - pixel::Map GetMap() const { - return m_pixelDmxConfiguration.GetMap(); - } - - uint32_t GetCount() const { - return m_pixelDmxConfiguration.GetCount(); - } - - uint32_t GetGroups() const { - return m_pixelDmxConfiguration.GetGroups(); - } - - uint32_t GetGroupingCount() const { - return m_pixelDmxConfiguration.GetGroupingCount(); - } - - uint32_t GetUniverses() const { - return m_pixelDmxConfiguration.GetUniverses(); + PixelDmxConfiguration::Get().Print(); } // RDM bool SetDmxStartAddress(uint16_t nDmxStartAddress) override; uint16_t GetDmxStartAddress() override { - return m_nDmxStartAddress; + return PixelDmxConfiguration::Get().GetDmxStartAddress(); } uint16_t GetDmxFootprint() override { - return m_nDmxFootprint; + return PixelDmxConfiguration::Get().GetDmxFootprint(); } bool GetSlotInfo(uint16_t nSlotOffset, lightset::SlotInfo &tSlotInfo) override; @@ -118,16 +83,7 @@ class WS28xxDmx final: public LightSet { } private: - PixelDmxConfiguration m_pixelDmxConfiguration; - pixeldmxconfiguration::PortInfo m_PortInfo; - uint32_t m_nChannelsPerPixel; - - uint16_t m_nDmxStartAddress; - uint16_t m_nDmxFootprint; - WS28xx *m_pWS28xx { nullptr }; - PixelDmxStore *m_pWS28xxDmxStore { nullptr }; - PixelDmxHandler *m_pPixelDmxHandler { nullptr }; bool m_bIsStarted { false }; bool m_bBlackout { false }; diff --git a/lib-ws28xxdmx/include/ws28xxdmxmulti.h b/lib-ws28xxdmx/include/ws28xxdmxmulti.h index 4c34ccf4..ebbf1809 100644 --- a/lib-ws28xxdmx/include/ws28xxdmxmulti.h +++ b/lib-ws28xxdmx/include/ws28xxdmxmulti.h @@ -2,7 +2,7 @@ * @file ws28xxdmxmulti.h * */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -30,87 +30,107 @@ #include #include "lightset.h" +#include "lightsetdata.h" #include "ws28xxmulti.h" #include "pixeldmxconfiguration.h" #include "pixelpatterns.h" -#include "pixeldmxhandler.h" +#include "logic_analyzer.h" namespace ws28xxdmxmulti { - +#if !defined (CONFIG_PIXELDMX_MAX_PORTS) +# define CONFIG_PIXELDMX_MAX_PORTS 8 +#endif +static constexpr auto MAX_PORTS = CONFIG_PIXELDMX_MAX_PORTS; } // namespace ws28xxdmxmulti class WS28xxDmxMulti final: public LightSet { public: - WS28xxDmxMulti(PixelDmxConfiguration& pixelDmxConfiguration); + WS28xxDmxMulti(); ~WS28xxDmxMulti() override; void Start(const uint32_t nPortIndex) override; void Stop(const uint32_t nPortIndex) override; - void SetData(uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength, const bool doUpdate = true) override; - void Sync(__attribute__((unused)) const uint32_t nPortIndex) override {} - void Sync(const bool doForce) override { - if (__builtin_expect((!doForce), 1)) { - assert(m_pWS28xxMulti != nullptr); - m_pWS28xxMulti->Update(); + void SetData(const uint32_t nPortIndex, [[maybe_unused]] const uint8_t *pData, [[maybe_unused]] uint32_t nLength, const bool doUpdate) override { + logic_analyzer::ch0_set(); + + if (!doUpdate) { + logic_analyzer::ch0_clear(); + return; } - } -#if defined (OUTPUT_HAVE_STYLESWITCH) - void SetOutputStyle(__attribute__((unused)) const uint32_t nPortIndex, __attribute__((unused)) const lightset::OutputStyle outputStyle) override {} - lightset::OutputStyle GetOutputStyle(__attribute__((unused)) const uint32_t nPortIndex) const override { - return lightset::OutputStyle::DELTA; - } + auto &pixelDmxConfiguration = PixelDmxConfiguration::Get(); + auto &portInfo = pixelDmxConfiguration.GetPortInfo(); + + if (nPortIndex == portInfo.nProtocolPortIndexLast) { + logic_analyzer::ch1_set(); + + for (uint32_t nIndex = 0 ; nIndex <= portInfo.nProtocolPortIndexLast;nIndex++) { + logic_analyzer::ch2_set(); + SetData(nIndex, lightset::Data::Backup(nIndex), lightset::Data::GetLength(nIndex)); + logic_analyzer::ch2_clear(); + } + +#if defined (H3) + logic_analyzer::ch3_set(); + + while (m_pWS28xxMulti->IsUpdating()) { + // wait for completion + } + + logic_analyzer::ch3_clear(); #endif - void Blackout(bool bBlackout) override; - void FullOn() override; + m_pWS28xxMulti->Update(); - void Print() override { - m_pixelDmxConfiguration.Print(); - } + logic_analyzer::ch1_clear(); + } - pixel::Type GetType() const { - return m_pixelDmxConfiguration.GetType(); + logic_analyzer::ch0_clear(); } - pixel::Map GetMap() const { - return m_pixelDmxConfiguration.GetMap(); - } + void Sync(const uint32_t nPortIndex) override { + logic_analyzer::ch2_set(); - uint32_t GetCount() const { - return m_pixelDmxConfiguration.GetCount(); - } + SetData(nPortIndex, lightset::Data::Backup(nPortIndex), lightset::Data::GetLength(nPortIndex)); - uint32_t GetGroups() const { - return m_pixelDmxConfiguration.GetGroups(); + logic_analyzer::ch2_clear(); } - uint32_t GetGroupingCount() const { - return m_pixelDmxConfiguration.GetGroupingCount(); - } + void Sync() override { + logic_analyzer::ch1_set(); + logic_analyzer::ch3_set(); - uint32_t GetUniverses() const { - return m_pixelDmxConfiguration.GetUniverses(); - } + while (m_pWS28xxMulti->IsUpdating()) { + // wait for completion + } + + logic_analyzer::ch3_clear(); + + m_pWS28xxMulti->Update(); - uint32_t GetOutputPorts() const { - return m_pixelDmxConfiguration.GetOutputPorts(); + logic_analyzer::ch1_clear(); } - uint32_t GetChannelsPerPixel() const { - return m_nChannelsPerPixel; +#if defined (OUTPUT_HAVE_STYLESWITCH) + void SetOutputStyle([[maybe_unused]] const uint32_t nPortIndex, [[maybe_unused]] const lightset::OutputStyle outputStyle) override {} + lightset::OutputStyle GetOutputStyle([[maybe_unused]] const uint32_t nPortIndex) const override { + return lightset::OutputStyle::DELTA; } +#endif + + void Blackout(bool bBlackout) override; + void FullOn() override; - void SetPixelDmxHandler(PixelDmxHandler *pPixelDmxHandler) { - m_pPixelDmxHandler = pPixelDmxHandler; + void Print() override { + PixelDmxConfiguration::Get().Print(); } // RDMNet LLRP Device Only - bool SetDmxStartAddress(__attribute__((unused)) uint16_t nDmxStartAddress) override { + bool SetDmxStartAddress([[maybe_unused]] uint16_t nDmxStartAddress) override { return false; } @@ -123,12 +143,10 @@ class WS28xxDmxMulti final: public LightSet { } private: - PixelDmxConfiguration m_pixelDmxConfiguration; - pixeldmxconfiguration::PortInfo m_PortInfo; - uint32_t m_nChannelsPerPixel; + void SetData(const uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength); +private: WS28xxMulti *m_pWS28xxMulti { nullptr }; - PixelDmxHandler *m_pPixelDmxHandler { nullptr }; uint32_t m_bIsStarted { 0 }; bool m_bBlackout { false }; diff --git a/lib-ws28xxdmx/src/dmx/ws28xxdmx.cpp b/lib-ws28xxdmx/src/dmx/ws28xxdmx.cpp index 5c39c61e..a7bdc0d5 100755 --- a/lib-ws28xxdmx/src/dmx/ws28xxdmx.cpp +++ b/lib-ws28xxdmx/src/dmx/ws28xxdmx.cpp @@ -2,7 +2,7 @@ * @file ws28xxdmx.cpp * */ -/* Copyright (C) 2016-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2016-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,6 +23,10 @@ * THE SOFTWARE. */ +#if defined (DEBUG_PIXELDMX) +# undef NDEBUG +#endif + #pragma GCC push_options #pragma GCC optimize ("O3") #pragma GCC optimize ("-funroll-loops") @@ -38,26 +42,32 @@ #include "lightset.h" #include "pixeldmxconfiguration.h" +#include "pixeldmxstore.h" + +#if defined (PIXELDMXSTARTSTOP_GPIO) +# include "hal_gpio.h" +#endif #include "debug.h" WS28xxDmx *WS28xxDmx::s_pThis; -WS28xxDmx::WS28xxDmx(PixelDmxConfiguration& pixelDmxConfiguration): m_pixelDmxConfiguration(pixelDmxConfiguration) { +WS28xxDmx::WS28xxDmx() { DEBUG_ENTRY assert(s_pThis == nullptr); s_pThis = this; - m_pixelDmxConfiguration.Validate(1 , m_nChannelsPerPixel, m_PortInfo); + PixelDmxConfiguration::Get().Validate(1); - m_pWS28xx = new WS28xx(m_pixelDmxConfiguration); + m_pWS28xx = new WS28xx(); assert(m_pWS28xx != nullptr); - m_pWS28xx->Blackout(); - m_nDmxStartAddress = m_pixelDmxConfiguration.GetDmxStartAddress(); - m_nDmxFootprint = static_cast(m_nChannelsPerPixel * m_pixelDmxConfiguration.GetGroups()); +#if defined (PIXELDMXSTARTSTOP_GPIO) + FUNC_PREFIX(gpio_fsel(PIXELDMXSTARTSTOP_GPIO, GPIO_FSEL_OUTPUT)); + FUNC_PREFIX(gpio_clr(PIXELDMXSTARTSTOP_GPIO)); +#endif DEBUG_EXIT } @@ -71,31 +81,31 @@ WS28xxDmx::~WS28xxDmx() { DEBUG_EXIT } -void WS28xxDmx::Start(__attribute__((unused)) uint32_t nPortIndex) { +void WS28xxDmx::Start([[maybe_unused]] uint32_t nPortIndex) { if (m_bIsStarted) { return; } m_bIsStarted = true; - if (m_pPixelDmxHandler != nullptr) { - m_pPixelDmxHandler->Start(); - } +#if defined (PIXELDMXSTARTSTOP_GPIO) + FUNC_PREFIX(gpio_set(PIXELDMXSTARTSTOP_GPIO)); +#endif } -void WS28xxDmx::Stop(__attribute__((unused)) uint32_t nPortIndex) { +void WS28xxDmx::Stop([[maybe_unused]] uint32_t nPortIndex) { if (!m_bIsStarted) { return; } m_bIsStarted = false; - if (m_pPixelDmxHandler != nullptr) { - m_pPixelDmxHandler->Stop(); - } +#if defined (PIXELDMXSTARTSTOP_GPIO) + FUNC_PREFIX(gpio_clr(PIXELDMXSTARTSTOP_GPIO)); +#endif } -void WS28xxDmx::SetData(uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength, const bool doUpdate) { +void WS28xxDmx::SetData([[maybe_unused]] uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength, const bool doUpdate) { assert(pData != nullptr); assert(nLength <= lightset::dmx::UNIVERSE_SIZE); @@ -103,21 +113,32 @@ void WS28xxDmx::SetData(uint32_t nPortIndex, const uint8_t *pData, uint32_t nLen return; } + auto &pixelDmxConfiguration = PixelDmxConfiguration::Get(); + auto &portInfo = pixelDmxConfiguration.GetPortInfo(); uint32_t d = 0; +#if !defined(LIGHTSET_PORTS) + static constexpr uint32_t nSwitch = 0; +#else const auto nSwitch = nPortIndex & 0x03; - const auto nGroups = m_pixelDmxConfiguration.GetGroups(); - const auto beginIndex = m_PortInfo.nBeginIndexPort[nSwitch]; - const auto endIndex = std::min(nGroups, (beginIndex + (nLength / m_nChannelsPerPixel))); - - if ((nSwitch == 0) && (nGroups < m_PortInfo.nBeginIndexPort[1])) { - d = static_cast(m_pixelDmxConfiguration.GetDmxStartAddress() - 1); +#endif + const auto nGroups = pixelDmxConfiguration.GetGroups(); +#if !defined(LIGHTSET_PORTS) + static constexpr uint32_t beginIndex = 0; +#else + const auto beginIndex = portInfo.nBeginIndexPort[nSwitch]; +#endif + const auto nChannelsPerPixel = pixelDmxConfiguration.GetLedsPerPixel(); + const auto endIndex = std::min(nGroups, (beginIndex + (nLength / nChannelsPerPixel))); + + if ((nSwitch == 0) && (nGroups < portInfo.nBeginIndexPort[1])) { + d = (pixelDmxConfiguration.GetDmxStartAddress() - 1U); } - const auto nGroupingCount = m_pixelDmxConfiguration.GetGroupingCount(); + const auto nGroupingCount = pixelDmxConfiguration.GetGroupingCount(); - if (m_nChannelsPerPixel == 3) { - switch (m_pixelDmxConfiguration.GetMap()) { + if (nChannelsPerPixel == 3) { + switch (pixelDmxConfiguration.GetMap()) { case pixel::Map::RGB: for (uint32_t j = beginIndex; (j < endIndex) && (d < nLength); j++) { auto const nPixelIndexStart = (j * nGroupingCount); @@ -178,7 +199,7 @@ void WS28xxDmx::SetData(uint32_t nPortIndex, const uint8_t *pData, uint32_t nLen break; } } else { - assert(m_nChannelsPerPixel == 4); + assert(nChannelsPerPixel == 4); for (auto j = beginIndex; (j < endIndex) && (d < nLength); j++) { auto const nPixelIndexStart = (j * nGroupingCount); for (uint32_t k = 0; k < nGroupingCount; k++) { @@ -188,7 +209,11 @@ void WS28xxDmx::SetData(uint32_t nPortIndex, const uint8_t *pData, uint32_t nLen } } - if ((doUpdate) && (nPortIndex == m_PortInfo.nProtocolPortIndexLast)) { +#if !defined(LIGHTSET_PORTS) + if (doUpdate) { +#else + if ((doUpdate) && (nPortIndex == portInfo.nProtocolPortIndexLast)) { +#endif if (__builtin_expect((m_bBlackout), 0)) { return; } @@ -223,21 +248,19 @@ void WS28xxDmx::FullOn() { bool WS28xxDmx::SetDmxStartAddress(uint16_t nDmxStartAddress) { assert((nDmxStartAddress != 0) && (nDmxStartAddress <= lightset::dmx::UNIVERSE_SIZE)); - if (nDmxStartAddress == m_nDmxStartAddress) { + auto &pixelDmxConfiguration = PixelDmxConfiguration::Get(); + + if (nDmxStartAddress == pixelDmxConfiguration.GetDmxStartAddress()) { return true; } - if ((nDmxStartAddress + m_nDmxFootprint) > lightset::dmx::UNIVERSE_SIZE) { + if ((nDmxStartAddress + pixelDmxConfiguration.GetDmxFootprint()) > lightset::dmx::UNIVERSE_SIZE) { return false; } if ((nDmxStartAddress != 0) && (nDmxStartAddress <= lightset::dmx::UNIVERSE_SIZE)) { - m_nDmxStartAddress = nDmxStartAddress; - - if (m_pWS28xxDmxStore != nullptr) { - m_pWS28xxDmxStore->SaveDmxStartAddress(m_nDmxStartAddress); - } - + pixelDmxConfiguration.SetDmxStartAddress(nDmxStartAddress); + PixelDmxStore::SaveDmxStartAddress(nDmxStartAddress); return true; } @@ -247,13 +270,15 @@ bool WS28xxDmx::SetDmxStartAddress(uint16_t nDmxStartAddress) { // RDM bool WS28xxDmx::GetSlotInfo(uint16_t nSlotOffset, lightset::SlotInfo& slotInfo) { - if (nSlotOffset > m_nDmxFootprint) { + auto &pixelDmxConfiguration = PixelDmxConfiguration::Get(); + + if (nSlotOffset > pixelDmxConfiguration.GetDmxFootprint()) { return false; } slotInfo.nType = 0x00; // ST_PRIMARY - switch (nSlotOffset % m_nChannelsPerPixel) { + switch (nSlotOffset % pixelDmxConfiguration.GetLedsPerPixel()) { case 0: slotInfo.nCategory = 0x0205; // SD_COLOR_ADD_RED break; diff --git a/lib-ws28xxdmx/src/dmx/ws28xxdmxmulti.cpp b/lib-ws28xxdmx/src/dmx/ws28xxdmxmulti.cpp deleted file mode 100755 index 4a1a8ecb..00000000 --- a/lib-ws28xxdmx/src/dmx/ws28xxdmxmulti.cpp +++ /dev/null @@ -1,218 +0,0 @@ -/** - * @file ws28xxdmxmulti.cpp - * - */ -/* Copyright (C) 2019-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#pragma GCC push_options -#pragma GCC optimize ("O3") -#pragma GCC optimize ("-funroll-loops") -#pragma GCC optimize ("-fprefetch-loop-arrays") - -#include -#include -#include - -#include "ws28xxdmxmulti.h" -#include "ws28xxmulti.h" -#include "ws28xx.h" - -#include "pixeldmxparams.h" -#include "pixeldmxconfiguration.h" - -#include "debug.h" - -namespace ws28xxdmxmulti { -#if !defined (CONFIG_PIXELDMX_MAX_PORTS) -# define CONFIG_PIXELDMX_MAX_PORTS 8 -#endif -static constexpr auto MAX_PORTS = CONFIG_PIXELDMX_MAX_PORTS; -} // namespace ws28xxdmxmulti - -WS28xxDmxMulti::WS28xxDmxMulti(PixelDmxConfiguration& pixelDmxConfiguration): m_pixelDmxConfiguration(pixelDmxConfiguration) { - DEBUG_ENTRY - - m_pixelDmxConfiguration.Validate(ws28xxdmxmulti::MAX_PORTS , m_nChannelsPerPixel, m_PortInfo); - - DEBUG_PRINTF("m_PortInfo.nProtocolPortIndexLast=%u", m_PortInfo.nProtocolPortIndexLast); - - m_pWS28xxMulti = new WS28xxMulti(pixelDmxConfiguration); - assert(m_pWS28xxMulti != nullptr); - - m_pWS28xxMulti->Blackout(); - - DEBUG_EXIT -} - -WS28xxDmxMulti::~WS28xxDmxMulti() { - delete m_pWS28xxMulti; - m_pWS28xxMulti = nullptr; -} - -void WS28xxDmxMulti::Start(const uint32_t nPortIndex) { - DEBUG_PRINTF("%u", nPortIndex); - - if (m_bIsStarted == 0) { - if (m_pPixelDmxHandler != nullptr) { - m_pPixelDmxHandler->Start(); - } - } - m_bIsStarted |= (1U << nPortIndex); -} - -void WS28xxDmxMulti::Stop(const uint32_t nPortIndex) { - DEBUG_PRINTF("%u", nPortIndex); - - if (m_bIsStarted & (1U << nPortIndex)) { - m_bIsStarted &= ~(1U << nPortIndex); - } - - if (m_bIsStarted == 0) { - if (m_pPixelDmxHandler != nullptr) { - m_pPixelDmxHandler->Stop(); - } - } -} - -void WS28xxDmxMulti::SetData(uint32_t nPortIndex, const uint8_t* pData, uint32_t nLength, const bool doUpdate) { - assert(pData != nullptr); - assert(nLength <= lightset::dmx::UNIVERSE_SIZE); - -#if defined (NODE_DDP_DISPLAY) - const auto nOutIndex = (nPortIndex / 4); - const auto nSwitch = nPortIndex - (nOutIndex * 4); -#else - const auto nUniverses = m_pixelDmxConfiguration.GetUniverses(); - const auto nOutIndex = (nPortIndex / nUniverses); - const auto nSwitch = nPortIndex - (nOutIndex * nUniverses); -#endif - - const auto nGroups = m_pixelDmxConfiguration.GetGroups(); - const auto beginIndex = m_PortInfo.nBeginIndexPort[nSwitch]; - const auto endIndex = std::min(nGroups, (beginIndex + (nLength / m_nChannelsPerPixel))); - - while (m_pWS28xxMulti->IsUpdating()) { - // wait for completion - } - - uint32_t d = 0; - - const auto nGroupingCount = m_pixelDmxConfiguration.GetGroupingCount(); - - if (m_nChannelsPerPixel == 3) { - switch (m_pixelDmxConfiguration.GetMap()) { - case pixel::Map::RGB: - for (uint32_t j = beginIndex; (j < endIndex) && (d < nLength); j++) { - auto const nPixelIndexStart = (j * nGroupingCount); - for (uint32_t k = 0; k < nGroupingCount; k++) { - m_pWS28xxMulti->SetPixel(nOutIndex, nPixelIndexStart + k, pData[d + 0], pData[d + 1], pData[d + 2]); - } - d = d + 3; - } - break; - case pixel::Map::RBG: - for (uint32_t j = beginIndex; (j < endIndex) && (d < nLength); j++) { - auto const nPixelIndexStart = (j * nGroupingCount); - for (uint32_t k = 0; k < nGroupingCount; k++) { - m_pWS28xxMulti->SetPixel(nOutIndex, nPixelIndexStart + k, pData[d + 0], pData[d + 2], pData[d + 1]); - } - d = d + 3; - } - break; - case pixel::Map::GRB: - for (uint32_t j = beginIndex; (j < endIndex) && (d < nLength); j++) { - auto const nPixelIndexStart = (j * nGroupingCount); - for (uint32_t k = 0; k < nGroupingCount; k++) { - m_pWS28xxMulti->SetPixel(nOutIndex, nPixelIndexStart + k, pData[d + 1], pData[d + 0], pData[d + 2]); - } - d = d + 3; - } - break; - case pixel::Map::GBR: - for (uint32_t j = beginIndex; (j < endIndex) && (d < nLength); j++) { - auto const nPixelIndexStart = (j * nGroupingCount); - for (uint32_t k = 0; k < nGroupingCount; k++) { - m_pWS28xxMulti->SetPixel(nOutIndex, nPixelIndexStart + k, pData[d + 2], pData[d + 0], pData[d + 1]); - } - d = d + 3; - } - break; - case pixel::Map::BRG: - for (uint32_t j = beginIndex; (j < endIndex) && (d < nLength); j++) { - auto const nPixelIndexStart = (j * nGroupingCount); - for (uint32_t k = 0; k < nGroupingCount; k++) { - m_pWS28xxMulti->SetPixel(nOutIndex, nPixelIndexStart + k, pData[d + 1], pData[d + 2], pData[d + 0]); - } - d = d + 3; - } - break; - case pixel::Map::BGR: - for (uint32_t j = beginIndex; (j < endIndex) && (d < nLength); j++) { - auto const nPixelIndexStart = (j * nGroupingCount); - for (uint32_t k = 0; k < nGroupingCount; k++) { - m_pWS28xxMulti->SetPixel(nOutIndex, nPixelIndexStart + k, pData[d + 2], pData[d + 1], pData[d + 0]); - } - d = d + 3; - } - break; - default: - assert(0); - __builtin_unreachable(); - break; - } - } else { - assert(m_nChannelsPerPixel == 4); - for (uint32_t j = beginIndex; (j < endIndex) && (d < nLength); j++) { - auto const nPixelIndexStart = (j * nGroupingCount); - for (uint32_t k = 0; k < nGroupingCount; k++) { - m_pWS28xxMulti->SetPixel(nOutIndex, nPixelIndexStart + k, pData[d], pData[d + 1], pData[d + 2], pData[d + 3]); - } - d = d + 4; - } - } - - if ((doUpdate) && (nPortIndex == m_PortInfo.nProtocolPortIndexLast)) { - m_pWS28xxMulti->Update(); - } -} - -void WS28xxDmxMulti::Blackout(bool bBlackout) { - m_bBlackout = bBlackout; - - while (m_pWS28xxMulti->IsUpdating()) { - // wait for completion - } - - if (bBlackout) { - m_pWS28xxMulti->Blackout(); - } else { - m_pWS28xxMulti->Update(); - } -} - -void WS28xxDmxMulti::FullOn() { - while (m_pWS28xxMulti->IsUpdating()) { - // wait for completion - } - - m_pWS28xxMulti->FullOn(); -} diff --git a/lib-ws28xxdmx/src/dmxmulti/ws28xxdmxmulti.cpp b/lib-ws28xxdmx/src/dmxmulti/ws28xxdmxmulti.cpp new file mode 100755 index 00000000..66a7cc08 --- /dev/null +++ b/lib-ws28xxdmx/src/dmxmulti/ws28xxdmxmulti.cpp @@ -0,0 +1,232 @@ +/** + * @file ws28xxdmxmulti.cpp + * + */ +/* Copyright (C) 2019-2024 by Arjan van Vught mailto:info@gd32-dmx.org + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#if defined (DEBUG_PIXELDMX) +# undef NDEBUG +#endif + +#pragma GCC push_options +#pragma GCC optimize ("O3") +#pragma GCC optimize ("-funroll-loops") +#pragma GCC optimize ("-fprefetch-loop-arrays") + +#include +#include +#include + +#include "ws28xxdmxmulti.h" +#include "ws28xxmulti.h" +#include "ws28xx.h" + +#include "pixeldmxparams.h" +#include "pixeldmxconfiguration.h" + +#if defined (PIXELDMXSTARTSTOP_GPIO) +# include "hal_gpio.h" +#endif + +#include "debug.h" + +WS28xxDmxMulti::WS28xxDmxMulti() { + DEBUG_ENTRY + + PixelDmxConfiguration::Get().Validate(ws28xxdmxmulti::MAX_PORTS); + + m_pWS28xxMulti = new WS28xxMulti(); + assert(m_pWS28xxMulti != nullptr); + m_pWS28xxMulti->Blackout(); + +#if defined (PIXELDMXSTARTSTOP_GPIO) + FUNC_PREFIX(gpio_fsel(PIXELDMXSTARTSTOP_GPIO, GPIO_FSEL_OUTPUT)); + FUNC_PREFIX(gpio_clr(PIXELDMXSTARTSTOP_GPIO)); +#endif + + DEBUG_EXIT +} + +WS28xxDmxMulti::~WS28xxDmxMulti() { + delete m_pWS28xxMulti; + m_pWS28xxMulti = nullptr; +} + +void WS28xxDmxMulti::Start(const uint32_t nPortIndex) { + DEBUG_PRINTF("%u", nPortIndex); + + if (m_bIsStarted == 0) { +#if defined (PIXELDMXSTARTSTOP_GPIO) + FUNC_PREFIX(gpio_set(PIXELDMXSTARTSTOP_GPIO)); +#endif + } + + m_bIsStarted |= (1U << nPortIndex); +} + +void WS28xxDmxMulti::Stop(const uint32_t nPortIndex) { + DEBUG_PRINTF("%u", nPortIndex); + + if (m_bIsStarted & (1U << nPortIndex)) { + m_bIsStarted &= ~(1U << nPortIndex); + } + + if (m_bIsStarted == 0) { +#if defined (PIXELDMXSTARTSTOP_GPIO) + FUNC_PREFIX(gpio_clr(PIXELDMXSTARTSTOP_GPIO)); +#endif + } +} + +void WS28xxDmxMulti::SetData(const uint32_t nPortIndex, const uint8_t* pData, uint32_t nLength) { + assert(pData != nullptr); + assert(nLength <= lightset::dmx::UNIVERSE_SIZE); + + auto &pixelDmxConfiguration = PixelDmxConfiguration::Get(); + +#if defined (NODE_DDP_DISPLAY) + const auto nOutIndex = (nPortIndex / 4); + const auto nSwitch = nPortIndex - (nOutIndex * 4); +#else + const auto nUniverses = pixelDmxConfiguration.GetUniverses(); + const auto nOutIndex = (nPortIndex / nUniverses); + const auto nSwitch = nPortIndex - (nOutIndex * nUniverses); +#endif + + auto &portInfo = pixelDmxConfiguration.GetPortInfo(); + + const auto nGroups = pixelDmxConfiguration.GetGroups(); + const auto beginIndex = portInfo.nBeginIndexPort[nSwitch]; + const auto nChannelsPerPixel = pixelDmxConfiguration.GetLedsPerPixel(); + const auto endIndex = std::min(nGroups, (beginIndex + (nLength / nChannelsPerPixel))); + const auto nGroupingCount = pixelDmxConfiguration.GetGroupingCount(); + const auto pixelType = pixelDmxConfiguration.GetType(); + const auto isRTZProtocol = pixelDmxConfiguration.IsRTZProtocol(); + + uint32_t d = 0; + + if (nChannelsPerPixel == 3) { + // Define a lambda to handle pixel setting based on color order + auto setPixelsColourRTZ = [&](const uint32_t nPortIndex, const uint32_t nPixelIndex, const uint32_t r, const uint32_t g, const uint32_t b) { +#if defined(CONFIG_PIXELDMX_ENABLE_GAMMATABLE) + const auto pGammaTable = m_pWS28xxMulti->m_PixelConfiguration.GetGammaTable(); + r = pGammaTable[r]; + g = pGammaTable[g]; + b = pGammaTable[b]; +#endif + m_pWS28xxMulti->SetColourRTZ(nPortIndex, nPixelIndex, r, g, b); + }; + + // Define a lambda to handle pixel setting based on color order + auto setPixelsColour3 = [&](const uint32_t nPortIndex, const uint32_t nPixelIndex, const uint32_t r, const uint32_t g, const uint32_t b) { +#if defined(CONFIG_PIXELDMX_ENABLE_GAMMATABLE) + const auto pGammaTable = m_pWS28xxMulti->m_PixelConfiguration.GetGammaTable(); + r = pGammaTable[r]; + g = pGammaTable[g]; + b = pGammaTable[b]; +#endif + + switch (pixelType) { + case pixel::Type::WS2801: + m_pWS28xxMulti->SetColourWS2801(nPortIndex, nPixelIndex, r, g, b); + break; + case pixel::Type::APA102: + case pixel::Type::SK9822: + m_pWS28xxMulti->SetPixel4Bytes(nPortIndex, 1 + nPixelIndex, pixelDmxConfiguration.GetGlobalBrightness(), b, g, r); + break; + case pixel::Type::P9813: { + const auto nFlag = static_cast(0xC0 | ((~b & 0xC0) >> 2) | ((~r & 0xC0) >> 4) | ((~r & 0xC0) >> 6)); + m_pWS28xxMulti->SetPixel4Bytes(nPortIndex, 1 + nPixelIndex, nFlag, b, g, r); + } + break; + default: + assert(0); + __builtin_unreachable(); + break; + } + }; + + constexpr uint32_t channelMap[6][3] = { + {0, 1, 2}, // RGB + {0, 2, 1}, // RBG + {1, 0, 2}, // GRB + {2, 0, 1}, // GBR + {1, 2, 0}, // BRG + {2, 1, 0} // BGR + }; + + const auto mapIndex = static_cast(pixelDmxConfiguration.GetMap()); + // Ensure mapIndex is within valid bounds + assert(mapIndex < sizeof(channelMap) / sizeof(channelMap[0])); // Runtime check + auto const& map = channelMap[mapIndex]; + + if (isRTZProtocol) { + for (uint32_t j = beginIndex; (j < endIndex) && (d < nLength); j++) { + auto const nPixelIndexStart = j * nGroupingCount; + for (uint32_t k = 0; k < nGroupingCount; k++) { + setPixelsColourRTZ(nOutIndex, nPixelIndexStart + k, pData[d + map[0]], pData[d + map[1]], pData[d + map[2]]); + } + d += 3; // Increment by 3 since we're processing 3 channels per pixel + } + } else { + for (uint32_t j = beginIndex; (j < endIndex) && (d < nLength); j++) { + auto const nPixelIndexStart = j * nGroupingCount; + for (uint32_t k = 0; k < nGroupingCount; k++) { + setPixelsColour3(nOutIndex, nPixelIndexStart + k, pData[d + map[0]], pData[d + map[1]], pData[d + map[2]]); + } + d += 3; // Increment by 3 since we're processing 3 channels per pixel + } + } + } else { + assert(nChannelsPerPixel == 4); + assert(isRTZProtocol); + for (uint32_t j = beginIndex; (j < endIndex) && (d < nLength); j++) { + auto const nPixelIndexStart = (j * nGroupingCount); + for (uint32_t k = 0; k < nGroupingCount; k++) { + m_pWS28xxMulti->SetColourRTZ(nOutIndex, nPixelIndexStart + k, pData[d], pData[d + 1], pData[d + 2], pData[d + 3]); + } + d = d + 4; // Increment by 4 since we're processing 4 channels per pixel + } + } +} + +void WS28xxDmxMulti::Blackout(bool bBlackout) { + m_bBlackout = bBlackout; + + while (m_pWS28xxMulti->IsUpdating()) { + // wait for completion + } + + if (bBlackout) { + m_pWS28xxMulti->Blackout(); + } else { + m_pWS28xxMulti->Update(); + } +} + +void WS28xxDmxMulti::FullOn() { + while (m_pWS28xxMulti->IsUpdating()) { + // wait for completion + } + + m_pWS28xxMulti->FullOn(); +} diff --git a/lib-ws28xxdmx/src/params/pixeldmxparams.cpp b/lib-ws28xxdmx/src/params/pixeldmxparams.cpp index 55c512b6..6cdd42cc 100644 --- a/lib-ws28xxdmx/src/params/pixeldmxparams.cpp +++ b/lib-ws28xxdmx/src/params/pixeldmxparams.cpp @@ -2,7 +2,7 @@ * @file pixeldmxparams.cpp * */ -/* Copyright (C) 2016-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2016-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,6 +23,10 @@ * THE SOFTWARE. */ +#if defined (DEBUG_PIXELDMX) +# undef NDEBUG +#endif + #if !defined(__clang__) // Needed for compiling on MacOS # pragma GCC push_options # pragma GCC optimize ("Os") @@ -37,6 +41,7 @@ #include "pixeltype.h" #include "pixelpatterns.h" #include "pixelconfiguration.h" + #include "gamma/gamma_tables.h" #include "lightset.h" @@ -53,58 +58,64 @@ using namespace pixel; using namespace lightset; -PixelDmxParams::PixelDmxParams(PixelDmxParamsStore *pPixelDmxParamsStore): m_pPixelDmxParamsStore(pPixelDmxParamsStore) { - m_pixelDmxParams.nSetList = 0; - m_pixelDmxParams.nType = static_cast(pixel::defaults::TYPE); - m_pixelDmxParams.nCount = defaults::COUNT; - m_pixelDmxParams.nDmxStartAddress = dmx::START_ADDRESS_DEFAULT; - m_pixelDmxParams.nSpiSpeedHz = spi::speed::ws2801::default_hz; - m_pixelDmxParams.nGlobalBrightness = 0xFF; - m_pixelDmxParams.nActiveOutputs = defaults::OUTPUT_PORTS; - m_pixelDmxParams.nGroupingCount = 1; - m_pixelDmxParams.nMap = static_cast(Map::UNDEFINED); - m_pixelDmxParams.nLowCode = 0; - m_pixelDmxParams.nHighCode = 0; - m_pixelDmxParams.nGammaValue = 0; - m_pixelDmxParams.nTestPattern = 0; +PixelDmxParams::PixelDmxParams() { + m_Params.nSetList = 0; + m_Params.nType = static_cast(pixel::defaults::TYPE); + m_Params.nCount = defaults::COUNT; + m_Params.nDmxStartAddress = dmx::START_ADDRESS_DEFAULT; + m_Params.nSpiSpeedHz = spi::speed::ws2801::default_hz; + m_Params.nGlobalBrightness = 0xFF; + m_Params.nActiveOutputs = defaults::OUTPUT_PORTS; + m_Params.nGroupingCount = 1; + m_Params.nMap = static_cast(Map::UNDEFINED); + m_Params.nLowCode = 0; + m_Params.nHighCode = 0; + m_Params.nGammaValue = 0; + m_Params.nTestPattern = 0; for (uint32_t nPortIndex = 0; nPortIndex < pixeldmxparams::MAX_PORTS; nPortIndex++) { - m_pixelDmxParams.nStartUniverse[nPortIndex] = static_cast(1 + (nPortIndex * 4)); + m_Params.nStartUniverse[nPortIndex] = static_cast(1 + (nPortIndex * 4)); } } -bool PixelDmxParams::Load() { - m_pixelDmxParams.nSetList = 0; +void PixelDmxParams::Load() { + DEBUG_ENTRY + + m_Params.nSetList = 0; #if !defined(DISABLE_FS) ReadConfigFile configfile(PixelDmxParams::staticCallbackFunction, this); if (configfile.Read(DevicesParamsConst::FILE_NAME)) { - if (m_pPixelDmxParamsStore != nullptr) { - m_pPixelDmxParamsStore->Update(&m_pixelDmxParams); - } + PixelDmxParamsStore::Update(&m_Params); } else #endif - if (m_pPixelDmxParamsStore != nullptr) { - m_pPixelDmxParamsStore->Copy(&m_pixelDmxParams); - } else { - return false; - } + PixelDmxParamsStore::Copy(&m_Params); - return true; +#ifndef NDEBUG + Dump(); +#endif + DEBUG_EXIT } void PixelDmxParams::Load(const char *pBuffer, uint32_t nLength) { + DEBUG_ENTRY + assert(pBuffer != nullptr); assert(nLength != 0); - m_pixelDmxParams.nSetList = 0; + m_Params.nSetList = 0; ReadConfigFile config(PixelDmxParams::staticCallbackFunction, this); config.Read(pBuffer, nLength); - m_pPixelDmxParamsStore->Update(&m_pixelDmxParams); + PixelDmxParamsStore::Update(&m_Params); + +#ifndef NDEBUG + Dump(); +#endif + DEBUG_EXIT } void PixelDmxParams::callbackFunction(const char *pLine) { @@ -119,25 +130,25 @@ void PixelDmxParams::callbackFunction(const char *pLine) { if (Sscan::Char(pLine, DevicesParamsConst::TYPE, cBuffer, nLength) == Sscan::OK) { cBuffer[nLength] = '\0'; - const auto type = PixelType::GetType(cBuffer); + const auto type = pixel::pixel_get_type(cBuffer); if (type != pixel::Type::UNDEFINED) { - m_pixelDmxParams.nType = static_cast(type); - m_pixelDmxParams.nSetList |= pixeldmxparams::Mask::TYPE; + m_Params.nType = static_cast(type); + m_Params.nSetList |= pixeldmxparams::Mask::TYPE; } else { - m_pixelDmxParams.nType = static_cast(pixel::defaults::TYPE); - m_pixelDmxParams.nSetList &= ~pixeldmxparams::Mask::TYPE; + m_Params.nType = static_cast(pixel::defaults::TYPE); + m_Params.nSetList &= ~pixeldmxparams::Mask::TYPE; } return; } if (Sscan::Uint16(pLine, DevicesParamsConst::COUNT, nValue16) == Sscan::OK) { if (nValue16 != 0 && nValue16 <= std::max(max::ledcount::RGB, max::ledcount::RGBW)) { - m_pixelDmxParams.nCount = nValue16; - m_pixelDmxParams.nSetList |= pixeldmxparams::Mask::COUNT; + m_Params.nCount = nValue16; + m_Params.nSetList |= pixeldmxparams::Mask::COUNT; } else { - m_pixelDmxParams.nCount = defaults::COUNT; - m_pixelDmxParams.nSetList &= ~pixeldmxparams::Mask::COUNT; + m_Params.nCount = defaults::COUNT; + m_Params.nSetList &= ~pixeldmxparams::Mask::COUNT; } return; } @@ -146,47 +157,47 @@ void PixelDmxParams::callbackFunction(const char *pLine) { if (Sscan::Char(pLine, DevicesParamsConst::MAP, cBuffer, nLength) == Sscan::OK) { cBuffer[nLength] = '\0'; - const auto map = PixelType::GetMap(cBuffer); + const auto map = pixel::pixel_get_map(cBuffer); if (map != Map::UNDEFINED) { - m_pixelDmxParams.nSetList |= pixeldmxparams::Mask::MAP; + m_Params.nSetList |= pixeldmxparams::Mask::MAP; } else { - m_pixelDmxParams.nSetList &= ~pixeldmxparams::Mask::MAP; + m_Params.nSetList &= ~pixeldmxparams::Mask::MAP; } - m_pixelDmxParams.nMap = static_cast(map); + m_Params.nMap = static_cast(map); return; } if (Sscan::Float(pLine, DevicesParamsConst::LED_T0H, fValue) == Sscan::OK) { - if ((nValue8 = PixelType::ConvertTxH(fValue)) != 0) { - m_pixelDmxParams.nSetList |= pixeldmxparams::Mask::LOW_CODE; + if ((nValue8 = pixel::pixel_convert_TxH(fValue)) != 0) { + m_Params.nSetList |= pixeldmxparams::Mask::LOW_CODE; } else { - m_pixelDmxParams.nSetList &= ~pixeldmxparams::Mask::LOW_CODE; + m_Params.nSetList &= ~pixeldmxparams::Mask::LOW_CODE; } - m_pixelDmxParams.nLowCode = nValue8; + m_Params.nLowCode = nValue8; return; } if (Sscan::Float(pLine, DevicesParamsConst::LED_T1H, fValue) == Sscan::OK) { - if ((nValue8 = PixelType::ConvertTxH(fValue)) != 0) { - m_pixelDmxParams.nSetList |= pixeldmxparams::Mask::HIGH_CODE; + if ((nValue8 = pixel::pixel_convert_TxH(fValue)) != 0) { + m_Params.nSetList |= pixeldmxparams::Mask::HIGH_CODE; } else { - m_pixelDmxParams.nSetList &= ~pixeldmxparams::Mask::HIGH_CODE; + m_Params.nSetList &= ~pixeldmxparams::Mask::HIGH_CODE; } - m_pixelDmxParams.nHighCode = nValue8; + m_Params.nHighCode = nValue8; return; } if (Sscan::Uint16(pLine, DevicesParamsConst::GROUPING_COUNT, nValue16) == Sscan::OK) { if (nValue16 > 1 && nValue16 <= std::max(max::ledcount::RGB, max::ledcount::RGBW)) { - m_pixelDmxParams.nGroupingCount = nValue16; - m_pixelDmxParams.nSetList |= pixeldmxparams::Mask::GROUPING_COUNT; + m_Params.nGroupingCount = nValue16; + m_Params.nSetList |= pixeldmxparams::Mask::GROUPING_COUNT; } else { - m_pixelDmxParams.nGroupingCount = 1; - m_pixelDmxParams.nSetList &= ~pixeldmxparams::Mask::GROUPING_COUNT; + m_Params.nGroupingCount = 1; + m_Params.nSetList &= ~pixeldmxparams::Mask::GROUPING_COUNT; } return; } @@ -195,33 +206,33 @@ void PixelDmxParams::callbackFunction(const char *pLine) { if (Sscan::Uint32(pLine, DevicesParamsConst::SPI_SPEED_HZ, nValue32) == Sscan::OK) { if (nValue32 != pixel::spi::speed::ws2801::default_hz) { - m_pixelDmxParams.nSetList |= pixeldmxparams::Mask::SPI_SPEED; + m_Params.nSetList |= pixeldmxparams::Mask::SPI_SPEED; } else { - m_pixelDmxParams.nSetList &= ~pixeldmxparams::Mask::SPI_SPEED; + m_Params.nSetList &= ~pixeldmxparams::Mask::SPI_SPEED; } - m_pixelDmxParams.nSpiSpeedHz = nValue32; + m_Params.nSpiSpeedHz = nValue32; return; } if (Sscan::Uint8(pLine, DevicesParamsConst::GLOBAL_BRIGHTNESS, nValue8) == Sscan::OK) { if ((nValue8 != 0) && (nValue8 != 0xFF)) { - m_pixelDmxParams.nSetList |= pixeldmxparams::Mask::GLOBAL_BRIGHTNESS; - m_pixelDmxParams.nGlobalBrightness = nValue8; + m_Params.nSetList |= pixeldmxparams::Mask::GLOBAL_BRIGHTNESS; + m_Params.nGlobalBrightness = nValue8; } else { - m_pixelDmxParams.nSetList &= ~pixeldmxparams::Mask::GLOBAL_BRIGHTNESS; - m_pixelDmxParams.nGlobalBrightness = 0xFF; + m_Params.nSetList &= ~pixeldmxparams::Mask::GLOBAL_BRIGHTNESS; + m_Params.nGlobalBrightness = 0xFF; } return; } -#if defined (PARAMS_INLCUDE_ALL) || !defined(OUTPUT_DMX_PIXEL_MULTI) +#if !defined(OUTPUT_DMX_PIXEL_MULTI) if (Sscan::Uint16(pLine, LightSetParamsConst::DMX_START_ADDRESS, nValue16) == Sscan::OK) { if ((nValue16 != 0) && nValue16 <= (dmx::UNIVERSE_SIZE) && (nValue16 != dmx::START_ADDRESS_DEFAULT)) { - m_pixelDmxParams.nDmxStartAddress = nValue16; - m_pixelDmxParams.nSetList |= pixeldmxparams::Mask::DMX_START_ADDRESS; + m_Params.nDmxStartAddress = nValue16; + m_Params.nSetList |= pixeldmxparams::Mask::DMX_START_ADDRESS; } else { - m_pixelDmxParams.nDmxStartAddress = dmx::START_ADDRESS_DEFAULT; - m_pixelDmxParams.nSetList &= ~pixeldmxparams::Mask::DMX_START_ADDRESS; + m_Params.nDmxStartAddress = dmx::START_ADDRESS_DEFAULT; + m_Params.nSetList &= ~pixeldmxparams::Mask::DMX_START_ADDRESS; } return; } @@ -230,23 +241,23 @@ void PixelDmxParams::callbackFunction(const char *pLine) { for (uint32_t i = 0; i < pixeldmxparams::MAX_PORTS; i++) { if (Sscan::Uint16(pLine, LightSetParamsConst::START_UNI_PORT[i], nValue16) == Sscan::OK) { if (nValue16 > 0) { - m_pixelDmxParams.nStartUniverse[i] = nValue16; - m_pixelDmxParams.nSetList |= (pixeldmxparams::Mask::START_UNI_PORT_1 << i); + m_Params.nStartUniverse[i] = nValue16; + m_Params.nSetList |= (pixeldmxparams::Mask::START_UNI_PORT_1 << i); } else { - m_pixelDmxParams.nStartUniverse[i] = static_cast(1 + (i * 4)); - m_pixelDmxParams.nSetList &= ~(pixeldmxparams::Mask::START_UNI_PORT_1 << i); + m_Params.nStartUniverse[i] = static_cast(1 + (i * 4)); + m_Params.nSetList &= ~(pixeldmxparams::Mask::START_UNI_PORT_1 << i); } } } -#if defined (PARAMS_INLCUDE_ALL) || defined(OUTPUT_DMX_PIXEL_MULTI) +#if defined(OUTPUT_DMX_PIXEL_MULTI) if (Sscan::Uint8(pLine, DevicesParamsConst::ACTIVE_OUT, nValue8) == Sscan::OK) { if ((nValue8 > 0) && (nValue8 <= pixeldmxparams::MAX_PORTS) && (nValue8 != pixel::defaults::OUTPUT_PORTS)) { - m_pixelDmxParams.nActiveOutputs = nValue8; - m_pixelDmxParams.nSetList |= pixeldmxparams::Mask::ACTIVE_OUT; + m_Params.nActiveOutputs = nValue8; + m_Params.nSetList |= pixeldmxparams::Mask::ACTIVE_OUT; } else { - m_pixelDmxParams.nActiveOutputs = pixel::defaults::OUTPUT_PORTS; - m_pixelDmxParams.nSetList &= ~pixeldmxparams::Mask::ACTIVE_OUT; + m_Params.nActiveOutputs = pixel::defaults::OUTPUT_PORTS; + m_Params.nSetList &= ~pixeldmxparams::Mask::ACTIVE_OUT; } return; } @@ -254,20 +265,21 @@ void PixelDmxParams::callbackFunction(const char *pLine) { if (Sscan::Uint8(pLine, DevicesParamsConst::TEST_PATTERN, nValue8) == Sscan::OK) { if ((nValue8 != static_cast(pixelpatterns::Pattern::NONE)) && (nValue8 < static_cast(pixelpatterns::Pattern::LAST))) { - m_pixelDmxParams.nTestPattern = nValue8; - m_pixelDmxParams.nSetList |= pixeldmxparams::Mask::TEST_PATTERN; + m_Params.nTestPattern = nValue8; + m_Params.nSetList |= pixeldmxparams::Mask::TEST_PATTERN; } else { - m_pixelDmxParams.nTestPattern = static_cast(pixelpatterns::Pattern::NONE); - m_pixelDmxParams.nSetList &= ~pixeldmxparams::Mask::TEST_PATTERN; + m_Params.nTestPattern = static_cast(pixelpatterns::Pattern::NONE); + m_Params.nSetList &= ~pixeldmxparams::Mask::TEST_PATTERN; } return; } +#if defined(CONFIG_PIXELDMX_ENABLE_GAMMATABLE) if (Sscan::Uint8(pLine, DevicesParamsConst::GAMMA_CORRECTION, nValue8) == Sscan::OK) { if (nValue8 != 0) { - m_pixelDmxParams.nSetList |= pixeldmxparams::Mask::GAMMA_CORRECTION; + m_Params.nSetList |= pixeldmxparams::Mask::GAMMA_CORRECTION; } else { - m_pixelDmxParams.nSetList &= ~pixeldmxparams::Mask::GAMMA_CORRECTION; + m_Params.nSetList &= ~pixeldmxparams::Mask::GAMMA_CORRECTION; } return; } @@ -275,148 +287,179 @@ void PixelDmxParams::callbackFunction(const char *pLine) { if (Sscan::Float(pLine, DevicesParamsConst::GAMMA_VALUE, fValue) == Sscan::OK) { const auto nValue = static_cast(fValue * 10); if ((nValue < gamma::MIN) || (nValue > gamma::MAX)) { - m_pixelDmxParams.nGammaValue = 0; + m_Params.nGammaValue = 0; } else { - m_pixelDmxParams.nGammaValue = nValue; + m_Params.nGammaValue = nValue; } + return; } -} - -void PixelDmxParams::staticCallbackFunction(void *p, const char *s) { - assert(p != nullptr); - assert(s != nullptr); - - (static_cast(p))->callbackFunction(s); +#endif } void PixelDmxParams::Builder(const struct pixeldmxparams::Params *ptWS28xxParams, char *pBuffer, uint32_t nLength, uint32_t& nSize) { assert(pBuffer != nullptr); if (ptWS28xxParams != nullptr) { - memcpy(&m_pixelDmxParams, ptWS28xxParams, sizeof(struct pixeldmxparams::Params)); + memcpy(&m_Params, ptWS28xxParams, sizeof(struct pixeldmxparams::Params)); } else { - m_pPixelDmxParamsStore->Copy(&m_pixelDmxParams); + PixelDmxParamsStore::Copy(&m_Params); } PropertiesBuilder builder(DevicesParamsConst::FILE_NAME, pBuffer, nLength); - builder.Add(DevicesParamsConst::TYPE, PixelType::GetType(static_cast(m_pixelDmxParams.nType)), isMaskSet(pixeldmxparams::Mask::TYPE)); - builder.Add(DevicesParamsConst::COUNT, m_pixelDmxParams.nCount, isMaskSet(pixeldmxparams::Mask::COUNT)); + builder.Add(DevicesParamsConst::TYPE, pixel::pixel_get_type(static_cast(m_Params.nType)), isMaskSet(pixeldmxparams::Mask::TYPE)); + builder.Add(DevicesParamsConst::COUNT, m_Params.nCount, isMaskSet(pixeldmxparams::Mask::COUNT)); + +#if defined(CONFIG_PIXELDMX_ENABLE_GAMMATABLE) builder.Add(DevicesParamsConst::GAMMA_CORRECTION, isMaskSet(pixeldmxparams::Mask::GAMMA_CORRECTION)); - if (m_pixelDmxParams.nGammaValue == 0) { + if (m_Params.nGammaValue == 0) { builder.Add(DevicesParamsConst::GAMMA_VALUE, "", false); } else { - builder.Add(DevicesParamsConst::GAMMA_VALUE, static_cast(m_pixelDmxParams.nGammaValue) / 10, true); + builder.Add(DevicesParamsConst::GAMMA_VALUE, static_cast(m_Params.nGammaValue) / 10, true); } +#endif builder.AddComment("Overwrite datasheet"); if (!isMaskSet(pixeldmxparams::Mask::MAP)) { - m_pixelDmxParams.nMap = static_cast(PixelType::GetMap(static_cast(m_pixelDmxParams.nType))); + m_Params.nMap = static_cast(pixel::pixel_get_map(static_cast(m_Params.nType))); } - builder.Add(DevicesParamsConst::MAP, PixelType::GetMap(static_cast(m_pixelDmxParams.nMap)), isMaskSet(pixeldmxparams::Mask::MAP)); + builder.Add(DevicesParamsConst::MAP, pixel::pixel_get_map(static_cast(m_Params.nMap)), isMaskSet(pixeldmxparams::Mask::MAP)); if (!isMaskSet(pixeldmxparams::Mask::LOW_CODE) || !isMaskSet(pixeldmxparams::Mask::HIGH_CODE)) { uint8_t nLowCode; uint8_t nHighCode; - PixelConfiguration::GetTxH(static_cast(m_pixelDmxParams.nType), nLowCode, nHighCode); + PixelConfiguration::Get().GetTxH(static_cast(m_Params.nType), nLowCode, nHighCode); if (!isMaskSet(pixeldmxparams::Mask::LOW_CODE)) { - m_pixelDmxParams.nLowCode = nLowCode; + m_Params.nLowCode = nLowCode; } if (!isMaskSet(pixeldmxparams::Mask::HIGH_CODE)) { - m_pixelDmxParams.nHighCode = nHighCode; + m_Params.nHighCode = nHighCode; } } builder.AddComment("Overwrite timing (us)"); - builder.Add(DevicesParamsConst::LED_T0H, PixelType::ConvertTxH(m_pixelDmxParams.nLowCode), isMaskSet(pixeldmxparams::Mask::LOW_CODE), 2); - builder.Add(DevicesParamsConst::LED_T1H, PixelType::ConvertTxH(m_pixelDmxParams.nHighCode), isMaskSet(pixeldmxparams::Mask::HIGH_CODE), 2); + builder.Add(DevicesParamsConst::LED_T0H, pixel::pixel_convert_TxH(m_Params.nLowCode), isMaskSet(pixeldmxparams::Mask::LOW_CODE), 2); + builder.Add(DevicesParamsConst::LED_T1H, pixel::pixel_convert_TxH(m_Params.nHighCode), isMaskSet(pixeldmxparams::Mask::HIGH_CODE), 2); builder.AddComment("Grouping"); - builder.Add(DevicesParamsConst::GROUPING_COUNT, m_pixelDmxParams.nGroupingCount, isMaskSet(pixeldmxparams::Mask::GROUPING_COUNT)); + builder.Add(DevicesParamsConst::GROUPING_COUNT, m_Params.nGroupingCount, isMaskSet(pixeldmxparams::Mask::GROUPING_COUNT)); builder.AddComment("Clock based chips"); - builder.Add(DevicesParamsConst::SPI_SPEED_HZ, m_pixelDmxParams.nSpiSpeedHz, isMaskSet(pixeldmxparams::Mask::SPI_SPEED)); + builder.Add(DevicesParamsConst::SPI_SPEED_HZ, m_Params.nSpiSpeedHz, isMaskSet(pixeldmxparams::Mask::SPI_SPEED)); builder.AddComment("APA102/SK9822"); - builder.Add(DevicesParamsConst::GLOBAL_BRIGHTNESS, m_pixelDmxParams.nGlobalBrightness, isMaskSet(pixeldmxparams::Mask::GLOBAL_BRIGHTNESS)); + builder.Add(DevicesParamsConst::GLOBAL_BRIGHTNESS, m_Params.nGlobalBrightness, isMaskSet(pixeldmxparams::Mask::GLOBAL_BRIGHTNESS)); -#if defined (PARAMS_INLCUDE_ALL) || !defined(OUTPUT_DMX_PIXEL_MULTI) +#if !defined(OUTPUT_DMX_PIXEL_MULTI) builder.AddComment("DMX"); - builder.Add(LightSetParamsConst::DMX_START_ADDRESS, m_pixelDmxParams.nDmxStartAddress, isMaskSet(pixeldmxparams::Mask::DMX_START_ADDRESS)); + builder.Add(LightSetParamsConst::DMX_START_ADDRESS, m_Params.nDmxStartAddress, isMaskSet(pixeldmxparams::Mask::DMX_START_ADDRESS)); #endif for (uint32_t i = 0; i < pixeldmxparams::MAX_PORTS; i++) { - builder.Add(LightSetParamsConst::START_UNI_PORT[i],m_pixelDmxParams.nStartUniverse[i], isMaskSet(pixeldmxparams::Mask::START_UNI_PORT_1 << i)); + builder.Add(LightSetParamsConst::START_UNI_PORT[i],m_Params.nStartUniverse[i], isMaskSet(pixeldmxparams::Mask::START_UNI_PORT_1 << i)); } -#if defined (PARAMS_INLCUDE_ALL) || defined(OUTPUT_DMX_PIXEL_MULTI) - builder.Add(DevicesParamsConst::ACTIVE_OUT, m_pixelDmxParams.nActiveOutputs, isMaskSet(pixeldmxparams::Mask::ACTIVE_OUT)); +#if defined(OUTPUT_DMX_PIXEL_MULTI) + builder.Add(DevicesParamsConst::ACTIVE_OUT, m_Params.nActiveOutputs, isMaskSet(pixeldmxparams::Mask::ACTIVE_OUT)); #endif builder.AddComment("Test pattern"); - builder.Add(DevicesParamsConst::TEST_PATTERN, m_pixelDmxParams.nTestPattern, isMaskSet(pixeldmxparams::Mask::TEST_PATTERN)); + builder.Add(DevicesParamsConst::TEST_PATTERN, m_Params.nTestPattern, isMaskSet(pixeldmxparams::Mask::TEST_PATTERN)); nSize = builder.GetSize(); DEBUG_PRINTF("nSize=%d", nSize); } -void PixelDmxParams::Set(PixelDmxConfiguration *pPixelDmxConfiguration) { - assert(pPixelDmxConfiguration != nullptr); - +void PixelDmxParams::Set() { // Pixel + auto& pixelConfiguration = PixelConfiguration::Get(); if (isMaskSet(pixeldmxparams::Mask::TYPE)) { - pPixelDmxConfiguration->SetType(static_cast(m_pixelDmxParams.nType)); + pixelConfiguration.SetType(static_cast(m_Params.nType)); } if (isMaskSet(pixeldmxparams::Mask::COUNT)) { - pPixelDmxConfiguration->SetCount(m_pixelDmxParams.nCount); + pixelConfiguration.SetCount(m_Params.nCount); } if (isMaskSet(pixeldmxparams::Mask::MAP)) { - pPixelDmxConfiguration->SetMap(static_cast(m_pixelDmxParams.nMap)); + pixelConfiguration.SetMap(static_cast(m_Params.nMap)); } if (isMaskSet(pixeldmxparams::Mask::LOW_CODE)) { - pPixelDmxConfiguration->SetLowCode(m_pixelDmxParams.nLowCode); + pixelConfiguration.SetLowCode(m_Params.nLowCode); } if (isMaskSet(pixeldmxparams::Mask::HIGH_CODE)) { - pPixelDmxConfiguration->SetHighCode(m_pixelDmxParams.nHighCode); + pixelConfiguration.SetHighCode(m_Params.nHighCode); } if (isMaskSet(pixeldmxparams::Mask::SPI_SPEED)) { - pPixelDmxConfiguration->SetClockSpeedHz(m_pixelDmxParams.nSpiSpeedHz); + pixelConfiguration.SetClockSpeedHz(m_Params.nSpiSpeedHz); } if (isMaskSet(pixeldmxparams::Mask::GLOBAL_BRIGHTNESS)) { - pPixelDmxConfiguration->SetGlobalBrightness(m_pixelDmxParams.nGlobalBrightness); + pixelConfiguration.SetGlobalBrightness(m_Params.nGlobalBrightness); } +#if defined(CONFIG_PIXELDMX_ENABLE_GAMMATABLE) if (isMaskSet(pixeldmxparams::Mask::GAMMA_CORRECTION)) { - pPixelDmxConfiguration->SetEnableGammaCorrection(true); - if (m_pixelDmxParams.nGammaValue != 0) { - pPixelDmxConfiguration->SetGammaTable(m_pixelDmxParams.nGammaValue); + pixelConfiguration.SetEnableGammaCorrection(true); + if (m_Params.nGammaValue != 0) { + pixelConfiguration.SetGammaTable(m_Params.nGammaValue); } } +#endif // Dmx + auto& pixelDmxConfiguration = PixelDmxConfiguration::Get(); if (isMaskSet(pixeldmxparams::Mask::DMX_START_ADDRESS)) { - pPixelDmxConfiguration->SetDmxStartAddress(m_pixelDmxParams.nDmxStartAddress); + pixelDmxConfiguration.SetDmxStartAddress(m_Params.nDmxStartAddress); } if (isMaskSet(pixeldmxparams::Mask::GROUPING_COUNT)) { - pPixelDmxConfiguration->SetGroupingCount(m_pixelDmxParams.nGroupingCount); + pixelDmxConfiguration.SetGroupingCount(m_Params.nGroupingCount); } -#if defined (PARAMS_INLCUDE_ALL) || defined(OUTPUT_DMX_PIXEL_MULTI) +#if defined(OUTPUT_DMX_PIXEL_MULTI) if (isMaskSet(pixeldmxparams::Mask::ACTIVE_OUT)) { - pPixelDmxConfiguration->SetOutputPorts(m_pixelDmxParams.nActiveOutputs); + pixelDmxConfiguration.SetOutputPorts(m_Params.nActiveOutputs); } #endif } + +void PixelDmxParams::staticCallbackFunction(void *p, const char *s) { + assert(p != nullptr); + assert(s != nullptr); + + (static_cast(p))->callbackFunction(s); +} + +void PixelDmxParams::Dump() { + printf("%s::%s \'%s\':\n", __FILE__,__FUNCTION__, DevicesParamsConst::FILE_NAME); + printf(" %s=%s [%d]\n", DevicesParamsConst::TYPE, pixel::pixel_get_type(static_cast(m_Params.nType)), static_cast(m_Params.nType)); + printf(" %s=%d [%s]\n", DevicesParamsConst::MAP, static_cast(m_Params.nMap), pixel::pixel_get_map(static_cast(m_Params.nMap))); + printf(" %s=%.2f [0x%X]\n", DevicesParamsConst::LED_T0H, pixel::pixel_convert_TxH(m_Params.nLowCode), m_Params.nLowCode); + printf(" %s=%.2f [0x%X]\n", DevicesParamsConst::LED_T1H, pixel::pixel_convert_TxH(m_Params.nHighCode), m_Params.nHighCode); + printf(" %s=%d\n", DevicesParamsConst::COUNT, m_Params.nCount); + + for (uint32_t i = 0; i < std::min(static_cast(pixelpatterns::MAX_PORTS), sizeof(LightSetParamsConst::START_UNI_PORT) / sizeof(LightSetParamsConst::START_UNI_PORT[0])); i++) { + printf(" %s=%d\n", LightSetParamsConst::START_UNI_PORT[i], m_Params.nStartUniverse[i]); + } + + printf(" %s=%d\n", DevicesParamsConst::ACTIVE_OUT, m_Params.nActiveOutputs); + printf(" %s=%d\n", DevicesParamsConst::GROUPING_COUNT, m_Params.nGroupingCount); + printf(" %s=%u\n", DevicesParamsConst::SPI_SPEED_HZ, static_cast(m_Params.nSpiSpeedHz)); + printf(" %s=%d\n", DevicesParamsConst::GLOBAL_BRIGHTNESS, m_Params.nGlobalBrightness); + printf(" %s=%d\n", LightSetParamsConst::DMX_START_ADDRESS, m_Params.nDmxStartAddress); + printf(" %s=%d\n", DevicesParamsConst::TEST_PATTERN, m_Params.nTestPattern); +#if defined(CONFIG_PIXELDMX_ENABLE_GAMMATABLE) + printf(" %s=%d\n", DevicesParamsConst::GAMMA_CORRECTION, isMaskSet(pixeldmxparams::Mask::GAMMA_CORRECTION)); + printf(" %s=%1.1f [%u]\n", DevicesParamsConst::GAMMA_VALUE, static_cast(m_Params.nGammaValue) / 10, m_Params.nGammaValue); +#endif +} diff --git a/lib-ws28xxdmx/src/params/pixeldmxparamsdump.cpp b/lib-ws28xxdmx/src/params/pixeldmxparamsdump.cpp deleted file mode 100644 index d882256e..00000000 --- a/lib-ws28xxdmx/src/params/pixeldmxparamsdump.cpp +++ /dev/null @@ -1,105 +0,0 @@ -/** - * @file pixeldmxparamsdump.cpp - * - */ -/* Copyright (C) 2016-2022 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#if !defined(__clang__) // Needed for compiling on MacOS -# pragma GCC push_options -# pragma GCC optimize ("Os") -#endif - -#ifndef NDEBUG -# include -# include -# include - -# include "pixeltype.h" - -# include "devicesparamsconst.h" -# include "lightsetparamsconst.h" -#endif - -#include "pixeldmxparams.h" - -using namespace pixeldmxparams; - -void PixelDmxParams::Dump() { -#ifndef NDEBUG - printf("%s::%s \'%s\':\n", __FILE__,__FUNCTION__, DevicesParamsConst::FILE_NAME); - - if (isMaskSet(Mask::TYPE)) { - printf(" %s=%s [%d]\n", DevicesParamsConst::TYPE, PixelType::GetType(static_cast(m_pixelDmxParams.nType)), static_cast(m_pixelDmxParams.nType)); - } - - if (isMaskSet(Mask::MAP)) { - printf(" %s=%d [%s]\n", DevicesParamsConst::MAP, static_cast(m_pixelDmxParams.nMap), PixelType::GetMap(static_cast(m_pixelDmxParams.nMap))); - } - - if (isMaskSet(Mask::LOW_CODE)) { - printf(" %s=%.2f [0x%X]\n", DevicesParamsConst::LED_T0H, PixelType::ConvertTxH(m_pixelDmxParams.nLowCode), m_pixelDmxParams.nLowCode); - } - - if (isMaskSet(Mask::HIGH_CODE)) { - printf(" %s=%.2f [0x%X]\n", DevicesParamsConst::LED_T1H, PixelType::ConvertTxH(m_pixelDmxParams.nHighCode), m_pixelDmxParams.nHighCode); - } - - if (isMaskSet(Mask::COUNT)) { - printf(" %s=%d\n", DevicesParamsConst::COUNT, m_pixelDmxParams.nCount); - } - - for (uint32_t i = 0; i < std::min(static_cast(MAX_PORTS), sizeof(LightSetParamsConst::START_UNI_PORT) / sizeof(LightSetParamsConst::START_UNI_PORT[0])); i++) { - if (isMaskSet(Mask::START_UNI_PORT_1 << i)) { - printf(" %s=%d\n", LightSetParamsConst::START_UNI_PORT[i], m_pixelDmxParams.nStartUniverse[i]); - } - } - - if (isMaskSet(Mask::ACTIVE_OUT)) { - printf(" %s=%d\n", DevicesParamsConst::ACTIVE_OUT, m_pixelDmxParams.nActiveOutputs); - } - - if (isMaskSet(Mask::GROUPING_COUNT)) { - printf(" %s=%d\n", DevicesParamsConst::GROUPING_COUNT, m_pixelDmxParams.nGroupingCount); - } - - if (isMaskSet(Mask::SPI_SPEED)) { - printf(" %s=%d\n", DevicesParamsConst::SPI_SPEED_HZ, m_pixelDmxParams.nSpiSpeedHz); - } - - if (isMaskSet(Mask::GLOBAL_BRIGHTNESS)) { - printf(" %s=%d\n", DevicesParamsConst::GLOBAL_BRIGHTNESS, m_pixelDmxParams.nGlobalBrightness); - } - - if (isMaskSet(Mask::DMX_START_ADDRESS)) { - printf(" %s=%d\n", LightSetParamsConst::DMX_START_ADDRESS, m_pixelDmxParams.nDmxStartAddress); - } - - if (isMaskSet(Mask::TEST_PATTERN)) { - printf(" %s=%d\n", DevicesParamsConst::TEST_PATTERN, m_pixelDmxParams.nTestPattern); - } - - if (isMaskSet(Mask::GAMMA_CORRECTION)) { - printf(" %s=1 [Yes]\n", DevicesParamsConst::GAMMA_CORRECTION); - printf(" %s=%1.1f [%u]\n", DevicesParamsConst::GAMMA_VALUE, static_cast(m_pixelDmxParams.nGammaValue) / 10, m_pixelDmxParams.nGammaValue); - } -#endif -} diff --git a/lib-ws28xxdmx/src/params/pixeldmxparamsrdm.cpp b/lib-ws28xxdmx/src/params/pixeldmxparamsrdm.cpp index 139be731..13fadf64 100644 --- a/lib-ws28xxdmx/src/params/pixeldmxparamsrdm.cpp +++ b/lib-ws28xxdmx/src/params/pixeldmxparamsrdm.cpp @@ -2,7 +2,7 @@ * @file pixeldmxparamsdmx.cpp * */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2021-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,48 +23,25 @@ * THE SOFTWARE. */ +#if defined (DEBUG_PIXELDMX) +# undef NDEBUG +#endif + #include #include #include "pixeldmxparamsrdm.h" -#include "pixeltype.h" #include "pixeldmxstore.h" +#include "pixeltype.h" #include "lightset.h" #include "debug.h" -using namespace pixeldmx::paramsdmx; - -PixelDmxStore *PixelDmxParamsRdm::s_pWS28xxDmxStore; -uint8_t PixelDmxParamsRdm::s_Data; - -PixelDmxParamsRdm::PixelDmxParamsRdm(PixelDmxStore *pWS28xxDmxStore) { - DEBUG_ENTRY - - s_pWS28xxDmxStore = pWS28xxDmxStore; - - DEBUG_EXIT -} - -void PixelDmxParamsRdm::Start(__attribute__((unused)) uint32_t nPortIndex) { - DEBUG_ENTRY - assert(nPortIndex == 0); - - DEBUG_EXIT -} - -void PixelDmxParamsRdm::Stop(__attribute__((unused)) uint32_t nPortIndex) { - DEBUG_ENTRY - assert(nPortIndex == 0); - - DEBUG_EXIT -} - -void PixelDmxParamsRdm::SetData(__attribute__((unused)) uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength, __attribute__((unused)) const bool doUpdate) { +void PixelDmxParamsRdm::SetData([[maybe_unused]] uint32_t nPortIndex, const uint8_t *pData, uint32_t nLength, [[maybe_unused]] const bool doUpdate) { assert(nPortIndex == 0); - if (nLength < DMX_FOOTPRINT) { + if (nLength < pixeldmx::paramsdmx::DMX_FOOTPRINT) { return; } @@ -77,30 +54,32 @@ void PixelDmxParamsRdm::SetData(__attribute__((unused)) uint32_t nPortIndex, con * Slot 6: Program; */ - assert(DMX_FOOTPRINT == 6); + assert(pixeldmx::paramsdmx::DMX_FOOTPRINT == 6); - const auto nLastIndex = DMX_FOOTPRINT - 1U; + const auto nLastIndex = pixeldmx::paramsdmx::DMX_FOOTPRINT - 1U; if (pData[nLastIndex] == 0x00) { - s_Data = 0x00; + m_Data = 0x00; } else { - if ((pData[nLastIndex] == 0xFF) && (s_Data == 0x00)) { + if ((pData[nLastIndex] == 0xFF) && (m_Data == 0x00)) { DEBUG_PUTS("Program"); - s_Data = 0xFF; + m_Data = 0xFF; - auto nData = pData[static_cast(SlotInfo::TYPE)]; + auto nData = pData[static_cast(pixeldmx::paramsdmx::SlotInfo::TYPE)]; auto nUndefined = static_cast(pixel::Type::UNDEFINED); - s_pWS28xxDmxStore->SaveType(nData < nUndefined ? nData : nUndefined); + const auto nType = nData < nUndefined ? nData : nUndefined; + PixelDmxStore::SaveType(nType); // Validation takes place in class PixelDmxConfiguration - s_pWS28xxDmxStore->SaveCount(pData[static_cast(SlotInfo::COUNT)]); - s_pWS28xxDmxStore->SaveGroupingCount(pData[static_cast(SlotInfo::GROUPING_COUNT)]); + PixelDmxStore::SaveCount(pData[static_cast(pixeldmx::paramsdmx::SlotInfo::COUNT)]); + PixelDmxStore::SaveGroupingCount(pData[static_cast(pixeldmx::paramsdmx::SlotInfo::GROUPING_COUNT)]); - nData = pData[static_cast(SlotInfo::MAP)]; + nData = pData[static_cast(pixeldmx::paramsdmx::SlotInfo::MAP)]; nUndefined = static_cast(pixel::Map::UNDEFINED); - s_pWS28xxDmxStore->SaveMap(nData < nUndefined ? nData : nUndefined); + const auto nMap = nData < nUndefined ? nData : nUndefined; + PixelDmxStore::SaveMap(nMap); - s_pWS28xxDmxStore->SaveTestPattern(pData[static_cast(SlotInfo::TEST_PATTERN)]); + PixelDmxStore::SaveTestPattern(pData[static_cast(pixeldmx::paramsdmx::SlotInfo::TEST_PATTERN)]); } } @@ -109,17 +88,6 @@ void PixelDmxParamsRdm::SetData(__attribute__((unused)) uint32_t nPortIndex, con } } -bool PixelDmxParamsRdm::GetSlotInfo(uint16_t nSlotOffset, lightset::SlotInfo &slotInfo) { - if (nSlotOffset >= DMX_FOOTPRINT) { - return false; - } - - slotInfo.nType = 0x00; // ST_PRIMARY - slotInfo.nCategory = 0xFFFF; // SD_UNDEFINED; - - return true; -} - -void PixelDmxParamsRdm::Display(__attribute__((unused)) const uint8_t *pData) { +void PixelDmxParamsRdm::Display([[maybe_unused]] const uint8_t *pData) { // Weak } diff --git a/lib-ws28xxdmx/src/pixeldmxconfiguration.cpp b/lib-ws28xxdmx/src/pixeldmxconfiguration.cpp deleted file mode 100644 index f55f0eec..00000000 --- a/lib-ws28xxdmx/src/pixeldmxconfiguration.cpp +++ /dev/null @@ -1,102 +0,0 @@ -/** - * @file pixeldmxconfiguration.cpp - * - */ -/* Copyright (C) 2021-2023 by Arjan van Vught mailto:info@orangepi-dmx.nl - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#if !defined(__clang__) // Needed for compiling on MacOS -# pragma GCC push_options -# pragma GCC optimize ("Os") -#endif - -#include -#include -#include - -#include "pixeldmxconfiguration.h" - -#include "debug.h" - -#if defined (NODE_ARTNET_MULTI) -# define NODE_ARTNET -#endif - -using namespace pixel; - -void PixelDmxConfiguration::Validate(uint32_t nPortsMax, uint32_t& nLedsPerPixel, pixeldmxconfiguration::PortInfo& portInfo) { - DEBUG_ENTRY - - PixelConfiguration::Validate(nLedsPerPixel); - - if (!IsRTZProtocol()) { - const auto type = GetType(); - if (!((type == Type::WS2801) || (type == Type::APA102) || (type == Type::SK9822))) { - SetType(Type::WS2801); - } - - PixelConfiguration::Validate(nLedsPerPixel); - } - - portInfo.nBeginIndexPort[0] = 0; - - if (GetType() == Type::SK6812W) { - portInfo.nBeginIndexPort[1] = 128; - portInfo.nBeginIndexPort[2] = 256; - portInfo.nBeginIndexPort[3] = 384; - } else { - portInfo.nBeginIndexPort[1] = 170; - portInfo.nBeginIndexPort[2] = 340; - portInfo.nBeginIndexPort[3] = 510; - } - - if ((m_nGroupingCount == 0) || (m_nGroupingCount > GetCount())) { - m_nGroupingCount = GetCount(); - } - - m_nGroups = GetCount() / m_nGroupingCount; - - m_nOutputPorts = std::min(nPortsMax, m_nOutputPorts); - m_nUniverses = (1U + (m_nGroups / (1U + portInfo.nBeginIndexPort[1]))); - - if (nPortsMax == 1) { - portInfo.nProtocolPortIndexLast = (m_nGroups / (1U + portInfo.nBeginIndexPort[1])); - } else { -#if defined (NODE_DDP_DISPLAY) - portInfo.nProtocolPortIndexLast = (((m_nOutputPorts - 1U) * 4U) + m_nUniverses - 1U); -#else - portInfo.nProtocolPortIndexLast = ((m_nOutputPorts * m_nUniverses) - 1U); -#endif - } - - DEBUG_PRINTF("portInfo.nProtocolPortIndexLast=%u", portInfo.nProtocolPortIndexLast); - DEBUG_EXIT -} - -#include - -void PixelDmxConfiguration::Print() { - PixelConfiguration::Print(); - - printf("Pixel DMX configuration\n"); - printf(" Outputs : %d\n", m_nOutputPorts); - printf(" Grouping count : %d [Groups : %d]\n", m_nGroupingCount, m_nGroups); -} diff --git a/lib-ws28xxdmx/src/rdm/rdm_manufacturer_pid.cpp b/lib-ws28xxdmx/src/rdm/rdm_manufacturer_pid.cpp index a80e6084..9d0f4d3f 100755 --- a/lib-ws28xxdmx/src/rdm/rdm_manufacturer_pid.cpp +++ b/lib-ws28xxdmx/src/rdm/rdm_manufacturer_pid.cpp @@ -2,7 +2,7 @@ * @file rdm_manufacturer_pid.cpp * */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@orangepi-dmx.nl +/* Copyright (C) 2023-2024 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,6 +23,10 @@ * THE SOFTWARE. */ +#if defined (DEBUG_PIXELDMX) +# undef NDEBUG +#endif + #include #include #include @@ -33,6 +37,7 @@ #include "rdm_e120.h" #include "pixeltype.h" +#include "pixeldmxstore.h" #include "debug.h" @@ -72,7 +77,11 @@ const rdm::ParameterDescription RDMHandler::PARAMETER_DESCRIPTIONS[] = { { rdm::E120_MANUFACTURER_PIXEL_TYPE::code, rdm::DEVICE_DESCRIPTION_MAX_LENGTH, E120_DS_ASCII, +#if defined (CONFIG_RDM_MANUFACTURER_PIDS_SET) + E120_CC_GET_SET, +#else E120_CC_GET, +#endif 0, E120_UNITS_NONE, E120_PREFIX_NONE, @@ -84,8 +93,12 @@ const rdm::ParameterDescription RDMHandler::PARAMETER_DESCRIPTIONS[] = { }, { rdm::E120_MANUFACTURER_PIXEL_COUNT::code, 2, - E120_DS_UNSIGNED_DWORD, + E120_DS_UNSIGNED_WORD, +#if defined (CONFIG_RDM_MANUFACTURER_PIDS_SET) + E120_CC_GET_SET, +#else E120_CC_GET, +#endif 0, E120_UNITS_NONE, E120_PREFIX_NONE, @@ -97,8 +110,12 @@ const rdm::ParameterDescription RDMHandler::PARAMETER_DESCRIPTIONS[] = { }, { rdm::E120_MANUFACTURER_PIXEL_GROUPING_COUNT::code, 2, - E120_DS_UNSIGNED_DWORD, + E120_DS_UNSIGNED_WORD, +#if defined (CONFIG_RDM_MANUFACTURER_PIDS_SET) + E120_CC_GET_SET, +#else E120_CC_GET, +#endif 0, E120_UNITS_NONE, E120_PREFIX_NONE, @@ -111,7 +128,11 @@ const rdm::ParameterDescription RDMHandler::PARAMETER_DESCRIPTIONS[] = { { rdm::E120_MANUFACTURER_PIXEL_MAP::code, rdm::DEVICE_DESCRIPTION_MAX_LENGTH, E120_DS_ASCII, +#if defined (CONFIG_RDM_MANUFACTURER_PIDS_SET) + E120_CC_GET_SET, +#else E120_CC_GET, +#endif 0, E120_UNITS_NONE, E120_PREFIX_NONE, @@ -130,34 +151,35 @@ uint32_t RDMHandler::GetParameterDescriptionCount() const { #include "ws28xxdmx.h" namespace rdm { -bool handle_manufactureer_pid_get(const uint16_t nPid, __attribute__((unused)) const ManufacturerParamData *pIn, ManufacturerParamData *pOut, uint16_t& nReason) { +bool handle_manufactureer_pid_get(const uint16_t nPid, [[maybe_unused]] const ManufacturerParamData *pIn, ManufacturerParamData *pOut, uint16_t& nReason) { + DEBUG_PRINTF("nPid=%x", __builtin_bswap16(nPid)); + + auto &pixelConfiguration = PixelConfiguration::Get(); + auto &pixelDmxConfiguration = PixelDmxConfiguration::Get(); + switch (nPid) { case rdm::E120_MANUFACTURER_PIXEL_TYPE::code: { - const auto *pString = ::PixelType::GetType(WS28xxDmx::Get()->GetType()); + const auto *pString = ::pixel::pixel_get_type(pixelConfiguration.GetType()); pOut->nPdl = static_cast(strlen(pString)); memcpy(pOut->pParamData, pString, pOut->nPdl); return true; } case rdm::E120_MANUFACTURER_PIXEL_COUNT::code: { - const auto nCount = WS28xxDmx::Get()->GetCount(); - pOut->nPdl = 4; - pOut->pParamData[0] = static_cast(nCount >> 24); - pOut->pParamData[1] = static_cast(nCount >> 16); - pOut->pParamData[2] = static_cast(nCount >> 8); - pOut->pParamData[3] = static_cast(nCount); + const auto nCount = pixelConfiguration.GetCount(); + pOut->nPdl = 2; + pOut->pParamData[0] = static_cast(nCount >> 8); + pOut->pParamData[1] = static_cast(nCount); return true; } case rdm::E120_MANUFACTURER_PIXEL_GROUPING_COUNT::code: { - const auto nGroupingCount = WS28xxDmx::Get()->GetGroupingCount(); - pOut->nPdl = 4; - pOut->pParamData[0] = static_cast(nGroupingCount >> 24); - pOut->pParamData[1] = static_cast(nGroupingCount >> 16); - pOut->pParamData[2] = static_cast(nGroupingCount >> 8); - pOut->pParamData[3] = static_cast(nGroupingCount); + const auto nGroupingCount = pixelDmxConfiguration.GetGroupingCount(); + pOut->nPdl = 2; + pOut->pParamData[0] = static_cast(nGroupingCount >> 8); + pOut->pParamData[1] = static_cast(nGroupingCount); return true; } case rdm::E120_MANUFACTURER_PIXEL_MAP::code: { - const auto *pString = ::PixelType::GetMap(WS28xxDmx::Get()->GetMap()); + const auto *pString = ::pixel::pixel_get_map(pixelConfiguration.GetMap()); pOut->nPdl = static_cast(strlen(pString)); memcpy(pOut->pParamData, pString, pOut->nPdl); return true; @@ -169,4 +191,71 @@ bool handle_manufactureer_pid_get(const uint16_t nPid, __attribute__((unused)) c nReason = E120_NR_UNKNOWN_PID; return false; } +#if defined (CONFIG_RDM_MANUFACTURER_PIDS_SET) +// C++ attribute: maybe_unused (since C++17) +bool handle_manufactureer_pid_set(const bool isBroadcast, const uint16_t nPid, const rdm::ParameterDescription ¶meterDescription, const ManufacturerParamData *pIn, [[maybe_unused]] ManufacturerParamData *pOut, uint16_t& nReason) { + DEBUG_PRINTF("nPid=%x", __builtin_bswap16(nPid)); + + if (isBroadcast) { + return false; + } + + switch (nPid) { + case rdm::E120_MANUFACTURER_PIXEL_COUNT::code: { + if (pIn->nPdl == 2) { + const uint16_t nCount = pIn->pParamData[1] | pIn->pParamData[0] << 8; + + if ((nCount < parameterDescription.min_value) && (nCount > parameterDescription.max_value)) { + nReason = E120_NR_DATA_OUT_OF_RANGE; + return false; + } + + PixelDmxStore::SaveCount(nCount); + return true; + } + + nReason = E120_NR_FORMAT_ERROR; + return false; + } + case rdm::E120_MANUFACTURER_PIXEL_GROUPING_COUNT::code: { + if (pIn->nPdl == 2) { + const uint16_t nGroupingCount = pIn->pParamData[1] | pIn->pParamData[0] << 8; + + if ((nGroupingCount < parameterDescription.min_value) && (nGroupingCount > parameterDescription.max_value)) { + nReason = E120_NR_DATA_OUT_OF_RANGE; + return false; + } + + PixelDmxStore::SaveGroupingCount(nGroupingCount); + return true; + } + + nReason = E120_NR_FORMAT_ERROR; + return false; + } + case rdm::E120_MANUFACTURER_PIXEL_MAP::code: { + if (pIn->nPdl == 3) { + const auto map = ::pixel::pixel_get_map(reinterpret_cast(pIn->pParamData)); + + if (map == pixel::Map::UNDEFINED) { + nReason = E120_NR_DATA_OUT_OF_RANGE; + return false; + } + + PixelDmxStore::SaveMap(static_cast(map)); + return true; + } + + nReason = E120_NR_FORMAT_ERROR; + return false; + } + default: + break; + } + + nReason = E120_NR_UNKNOWN_PID; + return false; + +} +#endif } // namespace rdm diff --git a/scripts/build_all.sh b/scripts/build_all.sh index 0c9959e2..b2473252 100755 --- a/scripts/build_all.sh +++ b/scripts/build_all.sh @@ -1,14 +1,4 @@ #!/bin/bash -NPROC=2 - -if [ "$(uname)" == "Darwin" ]; then - NPROC=$(sysctl -a | grep machdep.cpu.core_count | cut -d ':' -f 2) -elif [ "$(expr substr $(uname -s) 1 5)" == "Linux" ]; then - NPROC=$(nproc) -fi - -let NPROC-- - cd .. DIR=gd32_* @@ -37,8 +27,8 @@ do for m in $MAKEFILE do - make -f $m -j $NPROC clean - make -f $m -j $NPROC ENET_PHY=$i + make -f $m -j clean + make -f $m ENET_PHY=$i retVal=$? if [ $retVal -ne 0 ]; then