From c4bda730f69de807b3f2e38ca54cf1e4b9acf439 Mon Sep 17 00:00:00 2001 From: Thomas Epperson Date: Fri, 27 Dec 2024 15:52:25 -0600 Subject: [PATCH] Rename edge detect because it conflicted with another verilog package. --- nes/hdl/edge_detect.vhd | 8 ++++---- nes/hdl/nes_tripler.vhd | 16 ++++++++-------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/nes/hdl/edge_detect.vhd b/nes/hdl/edge_detect.vhd index 6fc7785..cec0d28 100644 --- a/nes/hdl/edge_detect.vhd +++ b/nes/hdl/edge_detect.vhd @@ -2,15 +2,15 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -entity edge_detect is +entity uob_edge_detect is port ( clock: in std_logic; sig: in std_logic; rising: out std_logic; falling: out std_logic); -end edge_detect; +end uob_edge_detect; -architecture Behavioral of edge_detect is +architecture Behavioral of uob_edge_detect is signal delay_sig: std_logic; begin @@ -31,4 +31,4 @@ begin end if; end process; -end Behavioral; \ No newline at end of file +end Behavioral; diff --git a/nes/hdl/nes_tripler.vhd b/nes/hdl/nes_tripler.vhd index 1a3bd0c..b293322 100644 --- a/nes/hdl/nes_tripler.vhd +++ b/nes/hdl/nes_tripler.vhd @@ -6,7 +6,7 @@ entity nes_tripler is Generic ( sim: integer); Port ( - clock: in std_logic; + clock: in std_logic; ppu_clock: in std_logic; ignore_sync: in std_logic := '0'; fsync_pause: out std_logic; @@ -168,38 +168,38 @@ architecture Behavioral of nes_tripler is begin hdmi_valid_out <= hdmi_valid_calc2; - hdmi_line_ready_detector: entity work.edge_detect port map( + hdmi_line_ready_detector: entity work.uob_edge_detect port map( clock => clock, sig => hdmi_line_ready, rising => hdmi_line_ready_rising); - hdmi_trigger: entity work.edge_detect port map( + hdmi_trigger: entity work.uob_edge_detect port map( clock => clock, sig => hdmi_valid_calc, rising => hdmi_line_done_rising, falling => hdmi_line_done); - hdmi_rising: entity work.edge_detect port map( + hdmi_rising: entity work.uob_edge_detect port map( clock => clock, sig => hdmi_start_output, rising => hdmi_start_output_rising); - ppu_clock_rising_e: entity work.edge_detect port map( + ppu_clock_rising_e: entity work.uob_edge_detect port map( clock => clock, sig => ppu_clock, rising => ppu_clock_rising); - ppu_hstart_rising_e: entity work.edge_detect port map( + ppu_hstart_rising_e: entity work.uob_edge_detect port map( clock => clock, sig => ppu_hstart, rising => ppu_hstart_rising); - ppu_vstart_rising_e: entity work.edge_detect port map( + ppu_vstart_rising_e: entity work.uob_edge_detect port map( clock => clock, sig => ppu_vstart, rising => ppu_vstart_rising); - hdmi_vsync_rising_e: entity work.edge_detect port map( + hdmi_vsync_rising_e: entity work.uob_edge_detect port map( clock => clock, sig => hdmi_vsync, rising => hdmi_vsync_rising);