From 870fdc6fef6f883ae4c4e1e798b9ed616b2686d3 Mon Sep 17 00:00:00 2001 From: Thomas Epperson Date: Thu, 19 Dec 2024 10:29:54 -0600 Subject: [PATCH] Remove unused signals. --- .gitignore | 6 + nes/hdl/clock_calcs.ods | Bin 0 -> 19876 bytes nes/hdl/modelsim.ini | 2202 +++++++++++++++++++++++++++++++++ nes/hdl/nes.vhd | 118 +- nes/hdl/nes_cartridge.vhd | 7 +- nes/hdl/nes_ppu.vhd | 7 + nes/hdl/nes_tang_nano_20k.vhd | 1 - nes/hdl/nestb.vhd | 2 +- nes/hdl/sim_tangnano20k.tcl | 82 ++ 9 files changed, 2305 insertions(+), 120 deletions(-) create mode 100644 nes/hdl/clock_calcs.ods create mode 100644 nes/hdl/modelsim.ini create mode 100644 nes/hdl/sim_tangnano20k.tcl diff --git a/.gitignore b/.gitignore index 6b351b8..790beec 100644 --- a/.gitignore +++ b/.gitignore @@ -84,3 +84,9 @@ nes/hdl/incremental_db/* nes/hdl/output_files/* nes/hdl/impl/* nes/hdl/*.user + +nes/hdl/dsim/*.env +nes/hdl/dsim/*.log +nes/hdl/dsim/dsim_work/* +nes/hdl/rtl_work/* +nes/hdl/transcript diff --git a/nes/hdl/clock_calcs.ods b/nes/hdl/clock_calcs.ods new file mode 100644 index 0000000000000000000000000000000000000000..362df7eac878bd77f7c50b29f427bc47b95c7a29 GIT binary patch literal 19876 zcmb5U1yEc~*Dead-66OI3GM{<;K6Nhm%#!IF2OChyE}sq?(PH|971pl1Py+8zgz#g zb*tX{ojSd%t9tLMr+f8Uy?Q-scdIJG!Q;cgAj7}_y^{1o?FFLPU|?YWsc)ZP9Bdsd z-MpMFO`V?43;AEdQIR|2CSdo2eVf)y(w2;r?y3f292H zsDD$bvx}3pi>2%TVZ48n)7i-xsl+$>t;_-k&;kX#+>gcmONyyZ9>G`A<_Mp#ls&&dI?m#_@6NGmIt-$ zxxPt-1QYel)``d+(T1lx;Rq7OMqAd)ZNbUZiN;ewcmeyp!Ze)Y^HnPcDn0GdD>n}+ zX&>ZO;dMA8n~5jeCjP>OP2%(m=o8>`aU!>7nk!xrz@pb{VRDUX3j-3~?Q6R&rs#cy zcnh1^PuE(JPDiI4oVj--Z9IkiSa`giP2x!#@cFIxJ9(J%_YS6C!0!?x^iR&`*y~;O zxOb$vHwy3*dvh9^6C_FYCda*aWNe*yXeOyyGWZ0($Ctbwe%mMoE1I@r`e{=zTjGYzU!}Rx05cm z7ez<`5J`%jCYAm}^@9kX-@-3(rKsnSKM(lD}ny9B`c5?#)r1SHO6G;1Sg+~gyc zJ!x-JkJ+Z`mJs_Z-KD5o%1(AFnMC+HTzy`v@<-*Ap3Oc&TNho?C3Zyf!c%3w)lf|zi`q^ux;1}cLleS=IAb*rCB%1%w$7)3#N=iE{!RF!hx{JP- za_~XHV=p-eZY2#{+3K*03dz53@jaqfJ3__#pf-{SX=+y{r59grpvpr6F_ zOy&;V{515J8DAB;<$O4BF7B-Sz5NltSjVof!_%7@sI&E3;?gmR3UQ_=qHdHP45ny}qiQI8sIuzh6gdIHsgZ>2uv)2!Z%M zQxx@VH4G7{i8Xt(*I)}1L&{BnEWBxv;PnvMtc72{#)lQ1&7brId zKU(+!?w-*M0u=U@jxiq{iaqoXsgmd#6&s9K=qbP`l&!3nc>jRMLossh?c{orRelg+Id>|!JwmUn%>9eN5)eo*@6`Lq!&HLxy6-Sm1M}YYnDti z9fDbsZ#^v=Yyl3Z>>CR}j=%*8&M@;mO4ni4DM}6ch#_&e zx=xsR%_$w<>H};`8(y>iC`C%aLaXqqH-7rq0NTvv}hO0J|pc69~>F0 za+0C<0PI%75~_9&4lbodhu$r7$T!9gKhHs-SPge|zjo1R~HK{S;#bz-D# zo8jU#gNoc)iAXv@5KYOwFCfs{(NmMZGa~dw@?*h_@!j6oDdQKp1?&E=jx&*`YnYm1 zpD&NrC)ThKH|{q4cwKH6(2*!als{m~FRn_3n3o>I#*%!}BatO{uX{q2T@+j++AqH^ zFWR3uE7$eIbYEy%3<$A*irk7Gq>ypQbB|sAr9+gfLGk>N5`%K|R%Aot*V)zT4o;Ih zQZc)LlH{!s1B9!4SM8H`TFtJ0xfqVu*I$3X916J_$BpPT-UYrNaHK-wFL>1g6xIgc zBU=41z&MF~1sj9yIc$0w5VwTf6iuV`>Umqu>RWp^MOvJfNeKt$e8}5S`Gyxlkt$C{ z&vcORUEEI52~B>_+@ZO%=H#*W!S{LTV^1D9M-9(6|CEeSp7n$heovjSS+4+GbTYq3 zgeAjU*No$C4-6?PMCnUEH95tc{_0NnZ3xUX~% zF8~(2|I7&YE|xQbsv|QpyWH@7j0UA&&WEipUlGFMS)J1Fx<`Zbur%(tAotB^rEERm z=65Kv4k=bF)Y9Gkv+E4IB&S-C09>}2{rwkRaWf{HeXBMBoAczXA_(d6UcUjV&ww_u zYj=3bZEBZ;)%=HAyl50o^w$|P-2ip+>})NpN?=T<*P^)moA;y~3zR)vmR+mHNNMV# z3f<4?ot?;)6CF1`ubg27RZ&}fOVLO^@5_)7m|y1g>Z0(bQpxJ+*6cA>O%GT>l$`47 zek<3j!B)jK0tEzq#H0HOCG!&c2h`)Y^>+NJVK1_5YrYB03+X+W)wYoOScrS&XJ2|< z;HMGrjo|DGQC-}A%lps22;6^_^r)qeFY%R}#bFdsTtEXBUw0yQ1glJ}i|DD!1T0`?JT~hn>e^)Uno=EOQLPs*C58 z2Mv;qv~1-^BbnjVpPnGto6>FXwraG)`t!VPBQbTa=bp9J7fMw{BxIVRWcD%?7#LCk z7?}TupZ^=ZLw}=p4yKN_R+g@AY%Ug7Q%O^f!5r8j=fa_u)63%Q2na5W<85|%y}V(% z2<(@cxSQRvN!n_~mB)DtJ2juVw_=;J&P>ThqZ`WmGHPxF6d(1oGu;9Qg(CrwACa;RCe`yCf~f7{*RE0*t%m z8crb|0Z~?tWjo0rk5fx1Tnla;1^(Ge_&HrQ*07uMmvFH%Nh?Dos$8K;o`Thrw_-=W ze%EV4$ZM2a&E@8%wNlPcpu6H^Z}2Ph1ky$Ct~Q;s^|CX{SGDf}nOC2g_%L>>X1+u> zy)IuU*x;zq{bD}x)kA~*)+L_s)M@-xo*E)@V_U;tE6Ol1E2Y zn0Z_V^o>HOy^Zcm)KFh8Lg!aC z;?clks!@1aMHBsdpUbGi!$EmO-F8#s1n_VRt7J#bQ60jjcRS9VZn)PNzFvl zzU9F&%Tx~qrtr$DK>K%S941OzZ1IsTu2`i!ndR4|`!KgQCT^MJLCl#}GS59KQqa8O zW#kbwy(-%S#YDUMQhLVFLCn8p*ODo#P^n(I+52z}TzSrIZp{2k)T3+mKz`p_)`gQB zi?c6WC?mo7d54owFsl4qLPIZ6yLhd;P+lI_)jjdrYr^t5BDY)P(ozljtmnTJaU5}X z-^6GU^)WF+&XcAxdM~iTcw;)o&qqj%1M(}YoaeTIW)l_X2xaGeq`L*XCwT^!;;N{V zHW{ZrN!FeBp+`n7;Zi3LCZgIog;Ivzc;n#YNGPP-ot&i&s<0%?9uVE1m{yQvZl7JY76{n-t+U|Qci3T*)ec&#(9 zX%TG?869D@el3LHQ%_6??k(DAE7d4c_(5vg4l>q|!<%L@Kl>aD zmy(L+II{Gjmy!vjxV)psjxrthDr+Re$REEiYs^;chbbi!DRAjcXU0;7Ht3$)(AQiq z&M9C1!caNjhg_4I&2hy6J1bkYSWetgW zJLp3x9BJ!^=?#l6Oed2td{U;ba(iySKPHUzVi6$aS~^T{F{O~*TaNf(gsu`FwlMG9 zjxP_mEbZrwC(Cyq88~A)RwHR{aC&hP`nx(F9hbIFi#g& z<0cf^TDYb8vUxL>^eGt0*Foa!a;)UZQsg0=C61a0VX9cai!`wzlh39Twsk{GyKy4L zl`Q;Sb~?6m3WpuLYEyW7S5|~JuFSQkH^JQbnoq@=#Ju~sdB3qlqsmy}=4XY_6pIeX zhR~q1uWUOnFU`dacT>49@HWfy8Sq>}E;7a&h5X~%>y_teK@F9P2@4}d?yf+UtV6kG z7UK~aQN;tIFIPAHD+C;!axn&<8xvps)!XE~ebl`KYP$#ZZ~{as7XI$Kca5oYE+j=I zn;ZNQ?iQ<9SewVvR3M8ifqxZMmz|Et*1QA}?itILwKS%p@m)Jozo!R&x1y2q4_{DQ zzr4IwxBipXo<76?zN_j@%!Xl=BDRCeA*$^TJQDW&sIM*V+1(WT&rJ=R(m8V|5;d2&~R$}OLS354Z zPa<{UdER)cPW*MDl6(uM6=8VtYI30R{dMeysQEcD82Ct&(v1+OMIM1TxRpJ{6`~Bs zx$gX9`&eX?NaH@5E2qpWIVKEd_i=)_;M?&JH8Bm4xK*yK6uw5Gf>>a(|1M`3ar2(M z@1#*BG@4@E8JO}c)2C5W zsm;GIe7nMtVMFtqxfQwLG$^y@#z+Pa-m73Ey(gS@g4RfQ{a98-qW|RFb!(q0&son& zwkJUYpGbj?CfQu^Y9%GkhnB}u%#P%OT1=etESi*Y@XhD^kvgl)q!cMIg947qWyVVO zbct-?CPkePp8X?galaL0-(=nN-qW;!ep2GxpF zK7O2i1Cy8KJ+(b}DsvBi>@tOU_vKl&jA_{kB{ zbhqVT*FX0;);^HDJaGI~j0ifh>Yb;TJw@nI{aZD~dqePaL(LJ(k;PeWe-VuB6Oo<* z8pF@Vd(jHZ3PLYKMa0dcNae|5U~4dRVthKG3=BXiV8Qo{_3Zu|o-q>HJ>-FTp(F5! znut`gvg>yZ<8_v2+Nb5QkcalqaLmGv+2s1a0u%A@Ur>cZ;qs_!1+oy1;A#qBIC!)d zW{u5BN)Z!uw5;C4zxEdvX^~R@4Kn(1MDR@Ymnd}>`$M^dv_H!eX`aZ7$l?ZW;Kz#o z9{h%9w8r^waYX7d0UwdO0eIL_^#b?nnoZPeXGzbP*XYx z2}s#4r5fOU?5SagVs7NEywsLgULav$eG~AWd|}6sJM6&cWO+69bX~!Wg*ju#g<*Cw zmcT7oeI*D#XxN|OZ~_`!7{H_lQDM4M$1SyutX~VK=lp!^X+^StYjhYjEG_uS&ZEu~ zkNz_Q7D133Jt*KGL!CL1TZP@ph~!Ic8^2j9KAq1i@2AZ6*6t}~fOzv!SB`{HgDEN; zcW=n8WG_V>5oRmWBoCq$2l{so6TJ7^uB!-8#4N7RAY%AQY8o!~ejahn%{hJ+{-~pD zle&g=e2cbyPAx=s60@%Is9`FObaL3>4d;%}q_*VaWnt5Bi2qE&rNEzdwB)Bp75t1U zyAFBg19ly4YR7(u73&{yV$`S*nJ{;e&uZl}rKIO;N>bFO&ULL*%7vRF&aZ~u%^cXc zVF)8ua6XUbe`|8b-Dr!EMKEBT16f4OLRJspac?JrwH!Nf)35&Uc0|CRy#=eWhv&GaAoAETihm&JkKd8b2lZq!GKjnC4rAfhQ^ zzo;;!&?PhIKhX|49ZjcuzC*aG&*BS@LUR(n+RWli#!5?yHR^+mXOb79NZ`CTE#aEN z6gd+c(!W;qV?4WR#O*C1*g*Lnr}Fc}CO$Kj|BFJG6#HhLz_8yIgI}iZlF4VeC{h-n z@klM|gAfn%=RcUBX=nYG%DqxiiHWYCx9C>HeOs-<)x3-9)kV`e^QQ6m?|Hr#63&PG z3iX*Ce`<#ivqrrOpAWSI8%FLBCT$IU4lDDv3_lKFom@e{yL#;C)zD-;iZ!a@`b3Cn zC&uxMTBQ8Fsh*OaQj3rJh5Z1rJZi%jzkvKa?v`q@`UTLIQ{m&@ce=Ij=qk+xbVfGw zn(^aUM3fWLp+<`>BCMj;*JveM2b`~}H7UPZe*DnBX1_&OS-+vRd;U>)qaY1?ccUi7 zVsHI~jh-nE3#ipquv(x92)aP~f}N|+Z(_1M(SEE(PVS4*W|m6FGKS~=TCU_F@U*-i zE*!ndiD_*;686b__r<)d>HEs*Pq2ApZ4JuS16}2R%zEcJms9YT*s1>4#O|NG*wxa_ z&DPQSKL;OY07H$FPw0MI#(lfw4+t!7`5p>^p@yw)nf<>v`T5oKv0_u|$yYaxdtBzY zR1?+bGBboG@ObLuEM(>qlCyoYKARn&B=0k-bgddKuE7$UjP4ySbetRirtsPV^yK_> z9)+_Bd;bAPuCc1`J)qFTrek3WW-op|OnQu-YYL>%fb2F8ul!wtt(n)j#<8@&fmx$( zZ>NHvkKR$6DQV2YX>M7Hw{jsiE{^$VV@O@v*T|-xdundz#tzhz`0Q_#^8(PRzyGK) zwEx<}p*#R&J+1rXe`4XEdOE|#kFB?MI?1kYT1HW^?)!_wt2r~R<@_cWspei>Tp#wt z{FK!(Q%{M%jmN0UTipxolKLmWq*pAneS z<}f&S+!8gAnyb{yt4ePDQu8&_ZopMM)&zA6+(2G$90I=xy=6pak#{%fF?}}Cy<*r!q6NER4H)8->2j%R8ZyAe20jzoy815M=eiHAV#8yU zQS4^BG@toAB0}JaoU<`yWjwXXadI{CkcTRecy^}R_x>>EZ9OO&cUAxk%0eCp6(K=V``fCGJlXa)(J;!f zjHk|#NeQL!TOb!bqxE-Y%_jyCb^0gq0&KWa)Q>&xnj(M4QL^^onW;eCHShF=K3zC7 z?;|lP-7KxCh!egFk?8zLD=(Dh@S9jLFNnaH+M(yxU%*7wY-7_CvtKwtqGK-9soCkh za4pK?Owmu8k%HK#nhGkbCl8U8`-9JM&GA~rq7fOJutJ;aBjb58YexC{SHro^L!0E= z(9Jv9CohdDeU$Jd1hC^_=QA3#Co@7QZ1Ckxx74a$jkuE71`hZrv-%&$sCHEhh$?&N zE`0YU+P@%f<+_~Bl&fnp-p`n^KQl?a9#|gwIwtmr2kQlJr5eiNH^Sa0;OObcpSV?| z^9KCNAFzPw59}DOPoJgLI+)}@x`^z<#Do1>{&BKwZ(GQ`R9D<_u8&bW-(hvxTgDFu zgUTK_{ec%wn2&Fi>;l9zoGaD4(3PLEOgiX<>Mzy(f->BmRB__?hh>OXg9#o<7+pfN zV|^cPfs|er#Ybp3i@%O)!s>W%oL#)@PBFGDqY&9s1ID^MonOBze$H+P8#h+I7QE;&!#itaIE+iO zp(6J95vBV#{M0o>Xa%R-@b7f3h&)Kx%w0epB;q&osegY|R22(S;@)^T5mMcDRGhXC z?kbwWkGPH^w%AjwnKJ4nm=c*+W_Y+xs!1^bid3@2V?16`Y384F*c=kWn2l%mk zBE%SAVE(E9oMvm&mO>OO6+1>u9$>!{69jW?776X;!pCe%mc{yoy7#LWsw>pLV zww1zU9K7d(fq8eQs-!6c3j+&>fQEpKfd=;u6#*3!6%iff?ZHFGCB;QY#>T)Uz{ViM zMj*pQdr$NpjerK9lpddgla!i)n4X`85S@kyo0bHRhJuut9G{8uJqHEBM`{v&dJ=ki zdRk^~S~ejTHXa5}AwDJ=K`tgf{!ip=5)>S=RP5sPyq}qc)%ZlD*(5XtB;0KTF*g2%T!*+R!PrVPTyY6z*Wo8LfOny*VInS%G*Xq*2+-B1t9a) zK*7sc4rr?DX{zLHrD=i>d?FF4XOJk9-kkxx>Ee|mk0gLb5gLA-}iB*-Gf*EQMCDn7tDI@l*O2$&J>UJ&L` z6zy7>;%uB?)}ta3<3Ra-@RXlZs*V@_B_L1uG7 zY+KRyuJX8+(xjrI;^MN(q6%W@Csyny={1|Yjm!C zYNK^}yK`>0zdB{4F>9=?Y_OwouB&XKzZKe7y)xFa^`mEdx^;i9b8Kv^e{z0!c75u{ z+~nfs{N%v=?DX1f-`e~H6uLCFdN8_ivAD52{qy(Kud9`vllh&?#lyR$qleY~%hjXX zwbRGVKd%QXBfr+>er~KDZOvY6PMq(|obIk(|C+cxTzb9OI6OMqIlKLJ`FwnFb9()F z^6+|fvUBnK$0N8kp* zz)-=+OG{{auAb%i7~mhY{Y9GHpc`dM3nC;;P>lLW^DzpRQ!D9u5RFDFA|aT!)b3^{ z#ZH-q^Uq+ESrbMS;r#xG)lv~7mrR?)$_O=e{z&>ik{7xnCJ}6mR4ywM!T~vVT#ZEO zhK`LN?w@lHlB6>>COaQDJT|?y&V_|(VZt7$sooVo_?4|T++Pr_JyziGA{=x)8~ssP z(tj~>OQK}+! zb30+b?-nB@&ztJ`jvYso51K^s7b?ZxHT#PeR8h9B4k02`TF;pu@QJTQB`3=edU`$X zFJA}ry5x=aw-5z6$ecFy>}?)-NsSYo#VOaaD9iuF|JnODS$6EBk>sn5BKgH3-B&Gz z@z2cJ{=Z8?=)dV#z~PFnKY8!JD<4ym4+uv`PEsdKWl>)R%AXGMhmqS(wKYC*+}jQT z?WmZI-AsH>&*iwS%8GjsR1>CO;)8r&LI!q$wZ#sKe?_nrF2jz;(uCE(xB71MRy>pF zqTb%R6qB=}PD*IaxhUysJ@lB`c3Ufy;Evg==HEE`BpRUIEzfdnKBH^`bZdwcN#n0E ziWdDw+PGXyKScLOrL`|#d^wFfW`#BQ?`(VqlZcF=zA$4&Vr!>qRwTyi;fcCeR44)WWT2;D@QuTaAW&Ainkf~$(?yL%~rmv2!?oz^KHY4GFzL&J? zq$=R2A1G(0f9&mI!BA!yG>#nM?dM5{y0FP_yH^A^GJ-R|lKXK$ z!XE_P@2>}=+@^e5kP_#als{EZqesW?pY3L63tZo?z-{v0ivc)n%b!_Bm)Nq4I{@H{ z5R?Q`Zcth_U-i6qHe7EPhJYK}SMSYrl~JCPo-xD*x8(o?ws^3y<0p6RrRZ+JGrhph zYtp2SQH!Mfv}kKx{ZW5ZcFZnUo!9|xb_RdibpFfemLk^OQos+#4(5Y2ol!R{*XdbH zg&ihe0VmVNmrB0&hPFDH5(Gkriob|Q+!`5#ydVQKtR)VrIf-9ro3W+a=7Sc80Ux5Y>n9N1j;cjpCm$Sq*KV}7tc-!2 zm*vMA#zTiHJ$BEpnK4s}nmt35a&}tdHx?*bBv#1G@VX`Z@2}BDi-jgR5+}h` z=IEx;$iFfqOf^QUuf@~*oLg0t)<$!4cdyoblKT5`nF_v>aaQjfD|t^f^NfnWj50WJ zhPcoktrpf61&=B|$b!l5j2(Zn(rMno3xJyfX7Ax!t$F-!z5ddq6L=mO0m!n+{}Qrb zb*@cZJ-8PAp*QrD1aj$-rJ%{|<8J%CzuQ$V`h$A9NYOYI*%Bo`&q@&N-kaT8sXyzb zdZL3ov?|K_&^VTx$hB-dGNiM}5EsV#l_+L7ntb!Kv5zND^@87OwjhaP!i=9pKs>LI zU{QgYDvpyHq9)qf*a3(C=WY8&!CPa}I%xxf_0dN=vZZE%qmOIq0kCZW)3K||*~A^# zKj|K0s(!(Lo05f{wga!2kG6X)fAM@^Z#2(4o_ZLz`1EBzXN7zC_cv}*`RIUF_{6k2 zjSnEv6eormPTLe@>hNzho=ZR2w;B9!G##jm;c`eMS(93~h3^NYOjpvUY59E|X0YXG zMk;T5l=xZm`rCDf;MAiJ{loYcA99;&CkuZ^UA~yo8MgCWbpx0z-s{}^E|SFG-J@>n zMMU@lm-0ilQXa^HnkwczO;7{UX8Lr7`&z9J<^G@{N3Opt#eX;Q9j->7o4%w{9F%ZZ zt6a?fcKF>ZsU`SRbp*Q50A{M%NwZMvKJ1(rkeA;|nGPwJx0F3veRUqV2kIbh_&ksu zf^ig0g0D^7h?}9=eeRL|q)I-ll31rHv1KVykAlVq%S4Poo`6Z zRhr-Xtw>?IM=M^JVz&lbm`JE1IO2$Jf-lEUt!NItiXH--;gpU|CNs&X)||CXkC!rN z@ktQ-#n)iKT^1|8d~{g6$k|1UW;6?{)95Y z-E(uZph$82ciK|WMWCBsn=%FOvk~`^%0=`f;6daZqgy-&V*7J%tsiKi$p;;HQLgIe zBP0V`t?}v%Cw$(#6Jwcz9Tg|O5WQ*`>-nik`U!@D?q40ZL_B| zGF!{)Pq_X)**CkjA9tcO&oz!exUa)fx@r{|dK=W-kV+)bw*}`QRY=+RNJ$w#GJob` z!H{qv@}6&9j@P{X5CU%tEtkboCsmu}q)?O@__VNn`~GX}YTJ~HkTn{~dtd_JxtQJc zn?*MRX@>HCoJHAlvCK8$@?(utk`XgqEx6!7_*~24avbyAM(w6I=~6S&06cmpe%B*R z0ZkCF1MmAi`a*KDXK-kjRBmZ^nC{=vA}@xM`|*MV@5P3Sd&iEB@TvxP6PTY4q)sjp z&~(s`z2(Vj-w7@>0DP`UWql$210t*FFyKZ z*5)qOiKILl0Lg`e$S&1R98Fh+Un|Jz=cyB}A*GG|O)GG*Kl%>!ym46>3>l2MJ?t;Y z+hi8I>oskaKkP)Ep?3XJcyyv9N+W$pZ)$#^oocKIdRP?5%f3fiT&&Ae;>7etEsIkC zvIrg#ZF#ok|J)-wDcCE?=C?if2Y)yK=LYmDy3fB})Cdt1yZS+Zl0Brce{=|CSK3gMpdK<Y4C1h zq**~0*Dzae3j;E==c>DLNLsZ6RgfJpKk1~b>VI+YbJhMeg?O5215RL4ze%KO_Gi#v z%sG*^uEbP%wk(qddgU&z1*W4Js^QKhKJYOEfQ?nOjuq!l#g4pQjafQ^dO+*8x@%(p z=oNHJJRyG%TMZ%i;@owFk0{(Btfof%EWuCb_hA=*nSFuO5fuvn$_D)tF1CQR55TTW zC#`5*cWnK3!V^r7S#3rv*ULCtbGhgSjC!?m@t8!2e^Ar)NxhPzM*w_X|73-q-Ujj- zD_wtNyF@ez6C!I6*I5T^g?WCqJu87IwiFt>x?W#3h-~4(RhhNTq#0BUpbh#+Zzy}S zS&aWmgXO?V5G&!Y=^55_fR84Is7tJi0CZDc>|Tq>sRp@GM2yApCj;XY+n{2~8GliH zb2`MD8(Og)Er;2J>#)a(#8-y-hll5?^W{IH?E2(zq}(oNuJ(O=f%3XAV0&!>~4p=RT*GRS83d> zrRZ?j#k#QH?!;`^>f|_?d0aPtMe)ll|MTDD<_1V}ZVBPIy_Kfet)bi3wp#$0ep`n5 zC~oJMn9tbxNF5tC6vZ{>s%dFeii>R@>l4c4Xx~UbUcg5j%s#+|{_w7}?nC|`x9gza ztU`9YlS5jsKYIr2wrUl&Y%Ce8o>idtVq!k4YL4I`Q=|joFK2%=@jRw*J@WH-78V>Dl1pY}3;n0EBB@EOAE$gD+8z%8zDDlQ0YwfkNlb@N^pZIW9^?@3vE!b6 zm=`l_ud4h;g`mQ66*Y8Qu^)dLdX91UcdAO0H!EKrkIh5{2b&d{`F=?+1fgs^LaH;d zQ?EAc*C~ybe|Jc$Z%zWD`Nz-{cc|PLI*2%;ZI3y(oQa;~;ayjvwTisItXUfGv5}vq zB_5Y6)(PbTdJ$dZTfgcr%Y$#o9l^#g@%q56D&QeFVOLnT=7#p_aGs<|G!4633{cQ~j&d}t=E9pK(teyeAGW66K|g|=}38mJ4t?i4t$gHF}? zAgAo5-hT7Y;Zhdq$!Rljkh(PU7CVpUf2ds1&>yR^y-p>*w~lqcY_ge3VqJ)jqLu*# z`58QCz7*oMKvzpaU)>J9mBt~Zk$+ybWI>l9!n1cA5jfe$amb6`l6Jdx8+75h%jR8o z%qthhhUg>FOG}puLX^Dx=P^9|#GbV17gx^aKc)I~$}WA-JGsaq=Bb0vL|b_n`)u=Ipu^_!XoDOyX0J>%bsRDAK1USY<{VcX=FuxY&o*q9*covQ|DL|zeh|32w{C?tQ~ zImpmuaMF@pJ=%6fY9}=0dZ+ZyQMcMrsN?E503qYZ+wZ|ZcUWl3ac*RsM}Mz#jW1J7X-TCluNJ_K+U=Y40{5$%>C@Gk<*410$nu0KPq)0NRo8IW(#)_FW^CbPSqmD4cM=i8cw) zP(IrYI-yGgEBL40kUP0+6Pq8#?Xs|IzJR}W`z%g~C84(_&~g;!D$WpRxZ zl|%>t{L~BbInWZP*E^A(MEWkeMo=}c1XiLX6>Tp->oP&`Ic@?!qUj{`Y{_fSJ6P47 zPdWy$=8)HCZVp0ABydUw^aWR(s>st5A$%RK+N?R3aU4HtX|#%uS^3vlNiA=OXIZ;^ z&pNhrPNr(qmo2MA+Sbrirzmh+9YjR)Hvs&tC3d$Y13sJ*VH^Vy0fEUtLtHy#{ZqE3 zcD-o`#paR$FqCm$Z}aU^n;x*HQeHEJ1U>A6lSN912d6usn)iAIP=&{{^bqA*b5oV7 zzU}83vJcqW_4f`TNG#Q#{`+UrDzk6>?yVQPROe*_7RFb9iYXX&0#T{~JdH&ql!Sdc z>kIU=ncgml|C}S3K*1tD_s`Jo@^wq6Wb?E*X|@Qhd)WpS13UFWI7Fj{cgDo34ayn4 z;4o-=891bBiKj{pQBYsxIvMS#vq$Yf)$|wuDAI8a9tJ$xFZK2`;u5zjlvbYgFw|N( zg|gV;PXtfN3$5%`n%CSo`_w?hCQP)cmsSk}7L6}Wz+&-QkcHoe;m58ffY+twCKc7;xby^MtF1h!+Z7vfNL7- z9stXA9FoeN<;VP(3k1LCkGYo^S@*y4Y9i&*Vg*+RG=wxYcV{#oMnoO}I_jZUIWFK5 zTw-k_nw?A8ew@Zn_Eit6Li+&rL{~5n(R~uKpE1R>3t(10Jj7=MRbGCvtxB)VCF3?B zQ7L;W(~KLmr`A;Jrl`J|%oA_{OKm18SokU{T1cPf)3-}5ABDnx8~;NXYH+gUHV*ls z&AJ5G{%+din0zn>AXPLfs9ZHGy<=Z?QkElLWpKjk{18X`Hp%d}=`~3YYgJa3#l&`fAE)?#NIn1;Xj?cP}iEO=IyXluma5Q-z(qQgKcwr zvVm_>Bnx+4&}5i^t?9VREBOcv)N(3E3{D;}+n{Z?2EfHN)7AK^!YrSGg}R=nb+v~o zRn7HAgA?w6ZT5QfGd?RY8Y)?j-LE<*`=&(49J~9_uU&$6R?&y|HEqyKPrB8$UZd;b zbBKQXwWtCfS91=3vn-SZ?wLtlrt+Bx`un>#^p&A}bL{}UI$Oibw{D@;p^ePB}b3*fUI=16%^ItvNS&~$$Z>i%}I)rwOHwuor(!08@g=3mfYa? z+~$;wg}71sp^XNEw?F7&EiRD8R*$uOLgQH-UBCorLV5GA31ym9EI)MvF^xp6Pt9~I z;b& zy2jrCuv34YA_Ds-W}}ec$zzW=i?&IYD!|TYr4=-D^1)-|EAVUpd^0(sNvYG8q5X2X zw+^-Q@5tAF^)1at$Hb8V^`me^+gG1QLTXx|sJn3jMV+t^UD+HA*OSTf+3Mqy*lIf~ zux&vww=navBY4r!Sl((CPAiqD`x|Sy9U=q%4-4m18PfXVnsDf<(Q*b#2c*yFuxi5X z^tvE4#LMuzz_i|CFPOJ#q(G-iGU75t>b!fiWkDw^<}sYTAli0KnOU*pxldwMCv8DM z?<7A+*-#%?QFpbs8kiS z*S@**)Me5?p=HuRJ|c_twHwO!TDFAqH2PGaPvH|z7p#cUd3It325;0sU*ZTYj%&3Z z>4oo_W;h`}OsxH!oX=`Ow%Csdl}$g_P01T7OHip}y~&K~pER zF9Lx&%u1kXKv;-{mz)x!Ay$YF)mEAMz%zs8`^~HtZ81yD=O?Gf`O=^u3{ut~>ixfw z#)iZ`oSbM<530pU#h_B>Nb=1qn0iMZm}V)u9R8_*G`D>SZmHv zZM}{B$zel_s%zCXTr!o|a|IOPX%x5?x1VxAB6UCwGDzDVnD4;Q%vh!;N;BcOg+zOC zbKxBP@LTo92AuUc1MuNt&jCT!3q^H-=b=duKDTD5<1xTz0KmYa!PF9E(!b4-B1U6x?FH#g{%9Q~R=r`x!d zh+pJY;;<>cXK?Z%6}aK~ts1Za0R9!^zE!)q3d{!I&_=h##~Psr6M#XZ)aQD@F(u|< z;_%s06sS0`#mG7?oOFcr&_c)C0?Zygt3qOp)wUD5`DQ+|J7^|hD0{5y7({yu;9*ET zDEYt`Fe7+OA04bWWPIt6?yIuw3eGtOc-Vpiwc8xm)b}vT6Cq!i%={OXVvp3(q^BX6 zr|Ce}TT-nG$%teVWlDz;;RkGP0iWvl5BewI8W7l!IfM}abSl@PV1s4?<^|ri#djZ9 z2VB8D7mhWMZ~);gDz#X`@BW5%Xi1V z(E!a%x&=^y-!xn00DkjF%oQ6&6lkI5l3;8a$JctO@%*EEaee4j8`6{oYVxGLvOrlnu2DQ-?4wq?9X)bkc@D#;kCBpgo zvGZ&gpmJ0L`J&ZRNA5>r-aIk?UN1C$WDk|vDigTT2LNg|Lb=Uv=C~lg0zJNeE?WCa zr>`rnJ%+}z_s*xuxI@#^CoUU!HVv3JI8jLf-*^J3i_M;-){wQ>zgvUCb}U+M%Q%@d zk^iJZ9K8@MN?e#m=NZX8cyEwGv2_#Qd%!`R< z$eBXm)n!i!fXY~X!!2|9%1Qg}9ZROD9Xt$h3gNhw6BNZ)uYj(u3qA-G6s2OmVBlH< z1lxdL^BWU$ST6eMzG)%bf?j!si@_Zw2EZJVrPaz*NORS3SASECImj_ArAe3y>Dfw^ z+E?Ve*M4T-ZU36KYz-*9j1%)=ya*DTJzNcmF#<18!s>>`mw3V8gxet8Qhs6zd74n8 zeq(k4+nyvv82cY8p*rMAF~!3C2R#H0ql!aV(#qL`3L$kuD@_-CjnE#h``@Q2ke57A z-!5G2l_artg{0iWu6*X`7N-~sxCrR`w%f_-)<6aT>{>GbZY|cSR2BCm<wIvAh@Y5u`X*CAZg{^agdI@lv z3o+6~xojlX!g_Oen_BFKKL|$DAry+uP$w}~k(jRq7T}hO%d_!HZ!v*iU?Lk%C;qS> zTkO|mfi?Xu$w=PgW-~hlZ-E|QD;64EGsSR*zf<22h&j5(%3$sU$Z`bq#3Q#>en~?e#wU-oT{`fVKZR(^|L3 zzYWeUUAJ|{5#!k_xAuiyjk4CCcjtN3b?M$?+$kF~w_V@5PI}Juf`j=RW3KNyRvY`; ztzXpX$^1P6YKPhHM19_ME$N6*)>_?pYfF9XpG94c@SJ|)YT(X2>%Ol2`sB#GsT|(N zH@wW-nx9|1cJi_q75mEMbMvP@Oj?`$XU2-<2;P~L z*q`ucVy&Z@@w_<+w|24~elwNTzLSB0`8#MWKXj(>%M-h=zbuHzez5b}8mEqPd27#3Stb5!)o$rWYJZmleIU1UUFq!|KiuNB-weFI z>)z$d5>t!UGOy0kt9op<$0CP)!b7{c*S7wf>m8e&wpRCTQ0s(0Kg9Mw)+=3mmDhjg zHIucs*dl>NY}@s%dA$;cpS#3f-})_K?e;Kkmj9XhGY%A&Y}vED{tNXeLg1prR5s&Z@D+kt2I_<`>sB6;YDq1cGlYVuut>%6l~SHd~(%{p4GrM z-sR;NCT8DV>2%`5zcX9a4m_1?54rwpje((U?H{JF>$m=U0-eD<`EGQ!){dY4tJ=G_ zn&mCK_RAUA8nYBy9+SN*tT2S*=CW^HM}S?c1OGl>Qth&9`gmw|!RPHJzkl@?#b)1( zDnGaN-u%x=hs#f|tJ&YxSazQ|A|}WE|C+r^y)JH=zs)NDOIfQx^!a@y(-PihEL#zB zeOA7Ua0e*ahVm={HWakjfURl|QDz{2NmnC~A9U0K$X}VH0OW@lP5?E!C4hXQlvCF< zh~?CB8?sj@_bIYzkZ`0V+%Qdp#0q(_fXg&U9FrQS_)P<+7!p#5;V$9-?BP=1)V76* zcmfv&F?hQAxvX5YvT0hBGD3sqbNV}Hd%D%I<3Mcn} zE(+NdX3YHlO;eeipRjpZ5tHQnKy9td;))im9c3As>U#~hv05tkc-;;yjXoH`UMkuD zd^Y3cxvQHOIUha}8^2w^Av*N3rNiM6j&s`WDLNA8w} zKqKH1Zyn%j#{h3eCJ_eQMhY;Da2w9;;1Furl3aIaxA8x9=(LyBvgMr#AXuGQB1haLG_m;6J{tQj%I?G0^7Zh zyssa$5*GpdfulroaLUx%2=P%m}c> Y9Y--8;LXYgQYHw5slY-<6I|{C0M16#ssI20 literal 0 HcmV?d00001 diff --git a/nes/hdl/modelsim.ini b/nes/hdl/modelsim.ini new file mode 100644 index 0000000..05674d4 --- /dev/null +++ b/nes/hdl/modelsim.ini @@ -0,0 +1,2202 @@ +; vsim modelsim.ini file +[Version] +INIVersion = "QA Baseline: 2021.1 Beta - 4536908" + +; Copyright 1991-2020 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini +; +; VITAL concerns: +; +; The library ieee contains (among other packages) the packages of the +; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use +; the physical library ieee (recommended), or use the physical library +; vital2000, but not both. The design can use logical library ieee and/or +; vital2000 as long as each of these maps to the same physical library, either +; ieee or vital2000. +; +; A design using the 1995 version of the VITAL packages, whether or not +; it also uses the 2000 version of the VITAL packages, must have logical library +; name ieee mapped to physical library vital1995. (A design cannot use library +; vital1995 directly because some packages in this library use logical name ieee +; when referring to the other packages in the library.) The design source +; should use logical name ieee when referring to any packages there except the +; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical +; name vital2000 (mapped to physical library vital2000) to refer to those +; packages. +; ieee = $MODEL_TECH/../vital1995 +; +; For compatiblity with previous releases, logical library name vital2000 maps +; to library vital2000 (a different library than library ieee, containing the +; same packages). +; A design should not reference VITAL from both the ieee library and the +; vital2000 library because the vital packages are effectively different. +; A design that references both the ieee and vital2000 libraries must have +; both logical names ieee and vital2000 mapped to the same library, either of +; these: +; $MODEL_TECH/../ieee +; $MODEL_TECH/../vital2000 +; + +; added mapping for ADMS + +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib + +; Altera Primitive libraries +; +; VHDL Section +; +; +; Verilog Section +; + +; Automatically perform logical->physical mapping for physical libraries that +; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). +; The tail of the filesystem path name is chosen as the logical library name. +; For example, in the command "vopt -L ./path/to/lib1 -o opttop top", +; vopt automatically performs the mapping "lib1 -> ./path/to/lib1". +; See the User Manual for more details. +; +; AutoLibMapping = 0 + +work = rtl_work +max10_hdmi_output = ./nes_iputf_libs/max10_hdmi_output +[DefineOptionset] +; Define optionset entries for the various compilers, vmake, and vsim. +; These option sets can be used with the "-optionset " syntax. +; i.e. +; vlog -optionset COMPILEDEBUG top.sv +; vsim -optionset UVMDEBUG my_top +; +; Following are some useful examples. + +; define a vsim optionset for uvm debugging +UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop + +; define a vopt optionset for debugging +VOPTDEBUG = +acc -debugdb + +[encryption] +; For vencrypt and vhencrypt. + +; Controls whether to encrypt whole files by ignoring all protect directives +; (except "viewport" and "interface_viewport") that are present in the input. +; The default is 0, use embedded protect directives to control the encryption. +; Set this to 1 to encrypt whole files by ignoring embedded protect directives. +; wholefile = 0 + +; Sets the data_method to use for the symmetric session key. +; The session key is a symmetric key that is randomly generated for each +; protected region (envelope) and is the heart of all encryption. This is used +; to set the length of the session key to generate and use when encrypting the +; HDL text. Supported values are aes128, aes192, and aes256. +; data_method = aes128 + +; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption +; "recipe" comprising an optional common block, at least one tool block (which +; contains the key public key), and the text to be encrypted. The common block +; and any of the tool blocks may contain rights in the form of the "control" +; directive. The text to be encrypted is specified either by setting +; "wholefile" to 1 or by embedding protect "begin" and "end" directives in +; the input HDL files. + +; Common recipe specification file. This file is optional. Its presence will +; require at least one "toolblock" to be specified. +; Directives such as "author" "author_info" and "data_method", +; as well as the common block license specification, go in this file. +; common = + +; Tool block specification recipe(s). Public key file with optional tool block +; file name. May be multiply-defined; at least one tool block is required if +; a recipe is being specified. +; Key file is a file name with no extension (.deprecated or .active will be +; supplied by the encryption tool). +; Rights file name is optional. +; toolblock = [,]{:[,]} + +; Location of directory containing recipe files. +; The default location is in the product installation directory. +; keyring = $MODEL_TECH/../keyring + +; Enable encryption statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [cmd,msg]. +Stats = cmd,msg + +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +; Value of 4 or ams99 for VHDL-AMS-1999 +; Value of 5 or ams07 for VHDL-AMS-2007 +VHDL93 = 2002 + +; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. +; ignoreStandardRealVector = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Set the prefix to be honored for synthesis/coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverSub = 0 + +; Automatically exclude VHDL case statement OTHERS choice branches. +; This includes OTHERS choices in selected signal assigment statements. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Turn on or off clkOpt optimization for code coverage. Default is on. +; CoverClkOpt = 1 + +; Turn on or off clkOpt optimization builtins for code coverage. Default is on. +; CoverClkOptBuiltins = 0 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Set this to cause the compilers to force data to be committed to disk +; when the files are closed. +; SyncCompilerFiles = 1 + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; Controls whether or not to show immediate assertions with constant expressions +; in GUI/report/UCDB etc. By default, immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls how VHDL basic identifiers are stored with the design unit. +; Does not make the language case-sensitive, affects only how declarations +; declared with basic identifiers have their names stored and printed +; (in the GUI, examine, etc.). +; Default is to preserve the case as originally depicted in the VHDL source. +; Value of 0 indicates to change all basic identifiers to lower case. +; PreserveCase = 0 + +; For Configuration Declarations, controls the effect that USE clauses have +; on visibility inside the configuration items being configured. If 1 +; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, +; extend the visibility of objects made visible through USE clauses into nested +; component configurations. +; OldVHDLConfigurationVisibility = 0 + +; Allows VHDL configuration declarations to be in a different library from +; the corresponding configured entity. Default is to not allow this for +; stricter LRM-compliance. +; SeparateConfigLibrary = 1; + +; Determine how mode OUT subprogram parameters of type array and record are treated. +; If 0 (the default), then only VHDL 2008 will do this initialization. +; If 1, always initialize the mode OUT parameter to its default value. +; If 2, do not initialize the mode OUT out parameter. +; Note that prior to release 10.1, all language versions did not initialize mode +; OUT array and record type parameters, unless overridden here via this mechanism. +; In release 10.1 and later, only files compiled with VHDL 2008 will cause this +; initialization, unless overridden here. +; InitOutCompositeParam = 0 + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Describe compilation options according to matching file patterns. +; File pattern * matches all printing characters other than '/'. +; File pattern **/x matches all paths containing file/directory x. +; File pattern x/** matches all paths beginning at directory x. +; FileOptMap = (**/*.vhd => -2008); + +; Describe library targets of compilation according to matching file patterns. +; LibMap = (**/*.vhd => work); + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with total size in bytes equal to or more than the sparse memory +; threshold gets marked as sparse automatically, unless specified otherwise +; in source code or by the +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with total size equal +; to or greater than 1Mb are marked as sparse) +; SparseMemThreshold = 1048576 + +; Set the prefix to be honored for synthesis and coverage pragma recognition. +; Default is "". +; AddPragmaPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is disabled by default when expression and/or condition +; coverage is active. +; CoverUDP = 1 + +; Enable or disable Rapid Expression Coverage mode for conditions and expressions. +; Disabling this would convert non-masking conditions in FEC tables to matching +; input patterns. +; CoverREC = 1 + +; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions +; for expression/condition coverage. +; NOTE: Enabling this may have a negative impact on simulation performance. +; CoverExpandReductionPrefix = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Turn on code coverage in VLOG `celldefine modules, modules containing +; specify blocks, and modules included using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 0 to 5, with the following +; meanings (the default is 3): +; 5 -- All allowable optimizations are on. +; 4 -- Turn off removing unreferenced code. +; 3 -- Turn off process, always block and if statement merging. +; 2 -- Turn off expression optimization, converting primitives +; to continuous assignments, VHDL subprogram inlining. +; and VHDL clkOpt (converting FF's to builtins). +; 1 -- Turn off continuous assignment optimizations and clock suppression. +; 0 -- Turn off Verilog module inlining and VHDL arch inlining. +; HOWEVER, if fsm coverage is turned on, optimizations will be forced to +; level 3, with also turning off converting primitives to continuous assigns. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => _ +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = [ ...] +LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SvFileSuffixes = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2005 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "mti_design_element_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls if untyped parameters that are initialized with values greater +; than 2147483647 are mapped to generics of type INTEGER or ignored. +; If mapped to VHDL Integers, values greater than 2147483647 +; are mapped to negative values. +; Default is to map these parameter to generic of type INTEGER +; ForceUnsignedToVHDLInteger = 1 + +; Enable AMS wreal (wired real) extensions. Default is 0. +; WrealType = 1 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-][,[+|-]*] + +; Generate symbols debugging database in only some special cases to save on +; the number of files in the library. For other design-units, this database is +; generated on-demand in vsim. +; Default is to to generate debugging database for all design-units. +; SmartDbgSym = 1 + +; Controls how $unit library entries are named. Valid options are: +; "file" (generate name based on the first file on the command line) +; "du" (generate name based on first design unit following an item +; found in $unit scope) +; CUAutoName = file + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; CppInstall = 7.4.0 + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. +; Sc22Mode = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +; Enable use of UVMC library. Default is off. +; UseUvmc = 1 + +[vopt] +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; enable or disable param saving in UCDB. +; CoverageSaveParam = 0 + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Controls set of CoverConstructs that are being considered for Coverage +; Collection. +; Some of Valid options are: default,set1,set2 +; Covermode = default + +; Override all PA VOPT and VSIM commands to run simulation in Non-PA mode. +; NonPAmode = 1 + +; Controls set of HDL cover constructs that would be considered(or not considered) +; for Coverage Collection. (Default corresponds to covermode default). +; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". +; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable Multi Bit Expression Coverage in a Design, If design has expression with +; multi bit operands, this option enables its Expression Coverage. +; The default value is 0. +; CoverFecMultiBit = 1 + +; Increase or decrease the limit on the size of expressions and conditions +; considered for expression and condition coverages. Higher FecUdpEffort leads +; to higher compile, optimize and simulation time, but more expressions and +; conditions are considered for coverage in the design. FecUdpEffort can +; be set to a number ranging from 1 (low) to 3 (high), defined as: +; 1 - (low) Only small expressions and conditions considered for coverage. +; 2 - (medium) Bigger expressions and conditions considered for coverage. +; 3 - (high) Very large expressions and conditions considered for coverage. +; The default setting is 1 (low). +; FecUdpEffort = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Enable deglitching of code coverage in combinatorial, non-clocked, processes. +; Default is no deglitching. +; CoverDeglitchOn = 1 + +; Enable compiler statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; Control the code coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a +; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; CoverDeglitchPeriod = 0 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Set the number of processes created during the code generation phase. +; By default a heuristic is used to set this value. This may be set to 0 +; to disable this feature completely. +; ParallelJobs = 0 + +; Controls SystemVerilog Language Extensions. These options enable +; some non-LRM compliant behavior. +; SvExtensions = [+|-][,[+|-]*] + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Disable SystemVerilog elaboration system task messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Enable or disable automatic creation of missing libraries. +; Default is 1 (enabled) +; CreateLib = 1 + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 10000000 + +; Specify libraries to be searched for precompiled modules +; LibrarySearchPath = [ ...] + +; Set XPROP assertion fail limit. Default is 5. +; Any positive integer, -1 for infinity. +; XpropAssertionLimit = 5 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Control SVA and VHDL immediate assertion directives during simulation +; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts +; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts +; SimulateImmedAsserts = 1 + +; License feature mappings for Verilog and VHDL +; qhsimvh Single language VHDL license +; qhsimvl Single language Verilog license +; msimhdlsim Language neutral license for either Verilog or VHDL +; msimhdlmix Second language only, language neutral license for either +; Verilog or VHDL +; +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately checkout and hold a VHDL license (i.e., one of +; qhsimvh, msimhdlsim, or msimhdlmix) +; vlog Immediately checkout and hold a Verilog license (i.e., one of +; qhsimvl, msimhdlsim, or msimhdlmix) +; plus Immediately checkout and hold a VHDL license and a Verilog license +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer license feature (PE ONLY) +; noslvhdl Disable checkout of qhsimvh license feature +; noslvlog Disable checkout of qhsimvl license feature +; nomix Disable checkout of msimhdlmix license feature +; nolnl Disable checkout of msimhdlsim license feature +; mixedonly Disable checkout of qhsimvh and qhsimvl license features +; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features +; +; Examples (remove ";" comment character to activate licensing directives): +; Single directive: +; License = plus +; Multi-directive (Note: space delimited directives): +; License = noqueue plus + +; Severity level of a VHDL assertion message or of a SystemVerilog severity system task +; which will cause a running simulation to stop. +; VHDL assertions and SystemVerilog severity system task that occur with the +; given severity or higher will cause a running simulation to stop. +; This value is ignored during elaboration. +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Severity level of a tool message which will cause a running simulation to +; stop. This value is ignored during elaboration. Default is to not break. +; 0 = Note 1 = Warning 2 = Error 3 = Fatal +;BreakOnMessage = 2 + +; The class debug feature enables more visibility and tracking of class instances +; during simulation. By default this feature is disabled (0). To enable this +; feature set ClassDebug to 1. +; ClassDebug = 1 + +; Message Format conversion specifications: +; %S - Severity Level of message/assertion +; %R - Text of message +; %T - Time of message +; %D - Delta value (iteration number) of Time +; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected +; %i - Instance/Region/Signal pathname with Process name (if available) +; %I - shorthand for one of these: +; " %K: %i" +; " %K: %i File: %F" (when path is not Process or Signal) +; except that the %i in this case does not report the Process name +; %O - Process name +; %P - Instance/Region path without leaf process +; %F - File name +; %L - Line number; if assertion message, then line number of assertion or, if +; assertion is in a subprogram, line from which the call is made +; %u - Design unit name in form library.primary +; %U - Design unit name in form library.primary(secondary) +; %% - The '%' character itself +; +; If specific format for Severity Level is defined, use that format. +; Else, for a message that occurs during elaboration: +; -- Failure/Fatal message in VHDL region that is not a Process, and in +; certain non-VHDL regions, uses MessageFormatBreakLine; +; -- Failure/Fatal message otherwise uses MessageFormatBreak; +; -- Note/Warning/Error message uses MessageFormat. +; Else, for a message that occurs during runtime and triggers a breakpoint because +; of the BreakOnAssertion setting: +; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; +; -- otherwise uses MessageFormatBreak. +; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. +; +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops because of a breakpoint or fatal error. +; Example with function name: # Break in Process ctr at counter.vhd line 44 +; Example without function name: # Break at counter.vhd line 44 +; Default value is 1. +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned +; Flags may be one of: enumnumeric, showbase, wreal +DefaultRadix = hexadecimal +DefaultRadixFlags = showbase +; Set to 1 for make the signal_force VHDL and Verilog functions use the +; default radix when processing the force value. Prior to 10.2 signal_force +; used the default radix, now it always uses symbolic unless value explicitly indicates base +;SignalForceFunctionUseDefaultRadix = 0 + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. +; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. +; BatchMode = 1 + +; File for saving command transcript when -batch option used +; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero +; default is unset so command transcript only goes to stdout for better performance +; BatchTranscriptFile = transcript + +; File for saving command transcript, this option is ignored when -batch option is used +TranscriptFile = transcript + +; Transcript file long line wrapping mode(s) +; mode == 0 :: no wrapping, line recorded as is +; mode == 1 :: wrap at first whitespace after WSColumn +; or at Column. +; mode == 2 :: wrap as above, but add continuation +; character ('\') at end of each wrapped line +; +; WrapMode = 0 +; WrapColumn = 30000 +; WrapWSColumn = 27000 + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable SystemVerilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; Control the iteration of events when a VHDL signal is forced to a value +; This flag can be set to honour the signal update event in next iteration, +; the default is to update and propagate in the same iteration. +; ForceSigNextIter = 1 + +; Enable simulation statistics. Specify one or more arguments: +; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] +; Add '-' to disable specific statistics. Default is [time,cmd,msg]. +; Stats = time,cmd,msg + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; If nonzero, close files as soon as there is either an explicit call to +; file_close, or when the file variable's scope is closed. When zero, a +; file opened in append mode is not closed in case it is immediately +; reopened in append mode; otherwise, the file will be closed at the +; point it is reopened. +; AppendClose = 1 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from accelerated versions of the std_logic_arith, +; std_logic_unsigned, and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from accelerated versions of the IEEE numeric_std +; and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names +; in the design hierarchy. +; This style is controlled by the value of the GenerateFormat +; value described next. Default is to use new-style names, which +; comprise the generate statement label, '(', the value of the generate +; parameter, and a closing ')'. +; Set this to 1 to use old-style names. +; OldVhdlForGenNames = 1 + +; Control the format of the old-style VHDL FOR generate statement region +; name for each iteration. Do not quote the value. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate statement label; the %d represents the generate parameter value +; at a particular iteration (this is the position number if the generate parameter +; is of an enumeration type). Embedded whitespace is allowed (but discouraged); +; leading and trailing whitespace is ignored. +; Application of the format must result in a unique region name over all +; loop iterations for a particular immediately enclosing scope so that name +; lookup can function properly. The default is %s__%d. +; GenerateFormat = %s__%d + +; Enable more efficient logging of VHDL Variables. +; Logging VHDL variables without this enabled, while possible, is very +; inefficient. Enabling this will provide a more efficient logging methodology +; at the expense of more memory usage. By default this feature is disabled (0). +; To enabled this feature, set this variable to 1. +; VhdlVariableLogging = 1 + +; Enable logging of VHDL access type variables and their designated objects. +; This setting will allow both variables of an access type ("access variables") +; and their designated objects ("access objects") to be logged. Logging a +; variable of an access type will automatically also cause the designated +; object(s) of that variable to be logged as the simulation progresses. +; Further, enabling this allows access objects to be logged by name. By default +; this feature is disabled (0). To enable this feature, set this variable to 1. +; Enabling this will automatically enable the VhdlVariableLogging feature also. +; AccessObjDebug = 1 + +; Make each VHDL package in a PDU has its own separate copy of the package instead +; of sharing the package between PDUs. The default is to share packages. +; To ensure that each PDU has its own set of packages, set this variable to 1. +; VhdlSeparatePduPackage = 1 + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. +; Use custom gcc compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; DpiCppPath = /bin/gcc +; +; Specify the compiler version from the list of support GNU compilers. +; examples 4.7.4, 5.3.0, 7.4.0 +; DpiCppInstall = 7.4.0 + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify whether the Verilog system task $fopen or vpi_mcd_open() +; will create directories that do not exist when opening the file +; in "a" or "w" mode. +; The default is 0 (do not create non-existent directories) +; CreateDirForFileAccess = 1 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + + +; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. +; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. +; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". +; The list of options must be delimited by commas, without spaces or tabs. +; +; Some examples +; To turn on all available UVM-aware debug features: +; UVMControl = all +; To turn on the struct window, mesage logging, and transaction logging: +; UVMControl = struct,msglog,trlog +; To turn on all options except certe: +; UVMControl = all,-certe +; To completely disable all UVM-aware debug functionality: +; UVMControl = disable + +; Specify the WildcardFilter setting. +; A space separated list of object types to be excluded when performing +; wildcard matches with log, wave, etc commands. The default value for this variable is: +; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" +; See "Using the WildcardFilter Preference Variable" in the documentation for +; details on how to use this variable and for descriptions of the filter types. +WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile + +; Specify the WildcardSizeThreshold setting. +; This integer setting specifies the size at which objects will be excluded when +; performing wildcard matches with log, wave, etc commands. Objects of size equal +; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard +; matches. The size is a simple calculation of number of bits or items in the object. +; The default value is 8k (8192). Setting this value to 0 will disable the checking +; of object size against this threshold and allow all objects of any size to be logged. +WildcardSizeThreshold = 8192 + +; Specify whether warning messages are output when objects are filtered out due to the +; WildcardSizeThreshold. The default is 0 (no messages generated). +WildcardSizeThresholdVerbose = 0 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify whether to lock the WLF file. +; Locking the file prevents other invocations of ModelSim/Questa tools from +; inadvertently overwriting the WLF file. +; The default is 1, lock the WLF file. +; WLFFileLock = 0 + +; Specify the update interval for the WLF file in live simulation. +; The interval is given in seconds. +; The value is the smallest interval between WLF file updates. The WLF file +; will be flushed (updated) after (at least) the interval has elapsed, ensuring +; that the data is correct when viewed from a separate viewer. +; A value of 0 means that no updating will occur. +; The default value is 10 seconds. +; WLFUpdateInterval = 10 + +; Specify the WLF cache size limit for WLF files. +; The value is given in megabytes. A value of 0 turns off the cache. +; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). +; On Windows, the default value is 1000 (megabytes) to help to avoid filling +; process memory. +; WLFSimCacheSize allows a different cache size to be set for a live simulation +; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize +; is not set, it defaults to the WLFCacheSize value. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines. +; If 0, no threads will be used; if 1, threads will be used if the system has +; more than one processor. +; WLFUseThreads = 1 + +; Specify the size of objects that will trigger "large object" messages +; at log/wave/list time. The size calculation of the object is the same as that +; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. +; Setting LargeObjectSize to 0 will disable these messages. +; LargeObjectSize = 500000 + +; Specify the depth of stack frames returned by $stacktrace([level]). +; This depth will be picked up when the optional 'level' argument +; is not specified or its value is not a positive integer. +; StackTraceDepth = 100 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; For SystemC-2.3.2 the valid values are 0,1 and 2 +; 0 = SC_SIGNAL_WRITE_CHECK_DISABLE_ +; 1 = SC_SIGNAL_WRITE_CHECK_DEFAULT_ +; 2 = SC_SIGNAL_WRITE_CHECK_CONFLICT_ +; For SystemC-2.2 the valid values are 0 and 1 +; 0 = DISABLE +; 1 = ENABLE +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Set SystemC thread stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). The stack size for sc_thread depends +; on the amount of data on the sc_thread stack and the memory required +; to succesfully execute the thread. +; ScStackSize = 1 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Enable calling of the DPI export taks/functions from the +; SystemC start_of_simulation() callback. +; The default is off. +; EnableDpiSosCb = 1 + + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: This variable can be overridden with the vsim "-onfinish" command line switch. +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result. Default is 0. +; 0 == do not print simstats +; 1 == print at end of simulation +; 2 == print at end of each run command and end of simulation +; PrintSimStats = 1 + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Enable assertion counts. Default is off. +; AssertionCounts = 1 + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. +; AssertionEnable = 0 + +; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionLimit = 1 + +; Turn on/off concurrent assertion pass log. Default is off. +; Assertion pass logging is only enabled when assertion is browseable +; and assertion debug is enabled. +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + +; Assertion thread limit after which assertion would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for an assertion go +; beyond this limit, the assertion would be either switched off or killed. This +; limit applies to only assert directives. +;AssertionThreadLimit = -1 + +; Action to be taken once the assertion thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only assert directives. +;AssertionThreadLimitAction = kill + +; Cover thread limit after which cover would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for a cover go +; beyond this limit, the cover would be either switched off or killed. This +; limit applies to only cover directives. +;CoverThreadLimit = -1 + +; Action to be taken once the cover thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only cover directives. +;CoverThreadLimitAction = kill + + +; By default immediate assertions do not participate in Assertion Coverage calculations +; unless they are executed. This switch causes all immediate assertions in the design +; to participate in Assertion Coverage calculations, whether attempted or not. +; UnattemptedImmediateAssertions = 0 + +; By default immediate covers participate in Coverage calculations +; whether they are attempted or not. This switch causes all unattempted +; immediate covers in the design to stop participating in Coverage +; calculations. +; UnattemptedImmediateCovers = 0 + +; By default pass action block is not executed for assertions on vacuous +; success. The following variable is provided to enable execution of +; pass action block on vacuous success. The following variable is only effective +; if the user does not disable pass action block execution by using either +; system tasks or CLI. Also there is a performance penalty for enabling +; the following variable. +;AssertionEnableVacuousPassActionBlock = 1 + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; This option applies to condition and expression coverage UDP tables. It +; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. +; If this option is used and a match occurs in more than one row in the UDP table, +; none of the counts for all matching rows is incremented. By default, counts are +; incremented for all matching rows. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays +; and VHDL arrays-of-arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, +; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. +; This leads to a longer simulation time with bigger arrays covered with toggle coverage. +; Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized +; one-dimensional packed vectors for toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for +; toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Turn off automatic inclusion of VHDL records in toggle coverage. +; Default is to include them. +; ToggleVHDLRecords = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. +; Following is the toggle coverage calculation criteria based on extended toggle mode: +; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). +; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. +; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. +; ExtendedToggleMode = 3 + +; Enable toggle statistics collection only for ports. Default is 0. +; TogglePortsOnly = 1 + +; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; FecCountLimit = 1 + +; Limit the counts that are tracked for UDP Coverage. When a bin has +; reached this count, further tracking of the input patterns linked to it is ignored. +; Default is 1. For unlimited counts, set to 0. +; NOTE: Changing this value from its default value may affect simulation performance. +; UdpCountLimit = 1 + +; Control toggle coverage deglitching period. A period of 0, eliminates delta +; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either +; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". +; ToggleDeglitchPeriod = 10.0ps + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this +; setting. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the threshold of Coverpoint wildcard bin value range size, above which +; a warning will be triggered. The default is 4K -- 12 wildcard bits. +; SVCoverpointWildCardBinValueSizeWarn = 4096 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SVCovergroup63Compatibility = 0 + +; Enforce the default behavior of covergroup get_coverage() builtin function, GUI +; and report. This variable sets the default value of type_option.merge_instances. +; There are two vsim command line options, -cvgmergeinstances and +; -nocvgmergeinstances to override this setting from vsim command line. +; The default value of this variable, -1 (don't care), allows the tool to determine +; the effective value, based on factors related to capacity and optimization. +; The type_option.merge_instances appears in the GUI and coverage reports as either +; auto(1) or auto(0), depending on whether the effective value was determined to +; be a 1 or a 0. +; SVCovergroupMergeInstancesDefault = -1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins +; MaxSVCoverpointBinsInst = 1048576 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins +; MaxSVCrossBinsInst = 67108864 + +; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. +; By default, this variable is set 0, in which case option.no_collect setting will take effect. +; If this variable is set to 1, all zero-weight coverage items will not be saved. +; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting +; of this variable. +; CvgZWNoCollect = 1 + +; Specify a space delimited list of double quoted TCL style +; regular expressions which will be matched against the text of all messages. +; If any regular expression is found to be contained within any message, the +; status for that message will not be propagated to the UCDB TESTSTATUS. +; If no match is detected, then the status will be propagated to the +; UCDB TESTSTATUS. More than one such regular expression text is allowed, +; and each message text is compared for each regular expression in the list. +; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Generate the stub definitions for the undefined symbols in the shared libraries being +; loaded in the simulation. When this flow is turned on, the undefined symbols will not +; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. +; The valid arguments are: on, off, verbose. +; on : turn on the automatic generation of stub definitions. +; off: turn off the flow. The undefined symbols will trigger an immediate load failure. +; verbose: Turn on the flow and report the undefined symbols for each shared library. +; NOTE: This variable can be overriden with vsim switch "-undefsyms". +; The default is on. +; +; UndefSyms = off + +; Enable the support for checkpointing foreign C/C++ libraries. +; The valid arguments are: 0, 1, 2 +; 0: off (default) +; 1: on (manually save/restore user shared library data) +; 2: auto (automatically save/restore user shared library data) +; This option is not supported on the Windows platforms. +; +; AllowCheckpointCpp = 2 + +; Initial seed for the random number generator of the root thread (SystemVerilog). +; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. +; The default value is 0. +; Sv_Seed = 0 + +; Specify the solver "engine" that vsim will select for constrained random +; generation. +; Valid values are: +; "auto" - automatically select the best engine for the current +; constraint scenario +; "bdd" - evaluate all constraint scenarios using the BDD solver engine +; "act" - evaluate all constraint scenarios using the ACT solver engine +; While the BDD solver engine is generally efficient with constraint scenarios +; involving bitwise logical relationships, the ACT solver engine can exhibit +; superior performance with constraint scenarios involving large numbers of +; random variables related via arithmetic operators (+, *, etc). +; NOTE: This variable can be overridden with the vsim "-solveengine" command +; line switch. +; The default value is "auto". +; SolveEngine = auto + +; Specify the maximum size that a random dynamic array or queue may be resized +; to by the solver. If the solver attempts to resize a dynamic array or queue +; to a size greater than the specified limit, the solver will abort with an error. +; The default value is 10000. The maximum value is 10000000. A value of 0 is +; equivalent to specifying the maximum value. +; SolveArrayResizeMax = 10000 + +; Specify error message severity when randomize() and randomize(null) failures +; are detected. +; +; Integer value up to two digits are allowed with each digit having the following legal values: +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; +; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents +; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit) +; represents the setting for randomize(null) calls. +; +; 2) When a single digit value is used, the setting is applied to both normal randomize() call +; and randomize(null) call. +; +; Example: Fatal error for randomize() failures and NO error for randomize(null) failures +; -solvefailseverity=40 +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefailseverity" command +; line switch. +; +; The default is 1 (warning). +; SolveFailSeverity = 1 + +; Error message severity for suppressible errors that are detected in a +; solve/before constraint. +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" +; command line switch. +; The default is 3 (failure). +; SolveBeforeErrorSeverity = 3 + +; Error message severity for suppressible errors that are related to +; solve engine capacity limits +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" +; command line switch. +; The default is 3 (failure). +; SolveEngineErrorSeverity = 3 + +; Enable/disable constraint conflicts on randomize() failure +; Valid values: +; 0 - disable solvefaildebug +; 1 - basic debug (no performance penalty) +; 2 - enhanced debug (runtime performance penalty) +; +; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is +; enabled, a constraint contradiction report will be displayed for randomize() calls that +; have a message severity >= warning (i.e. constraint contradiction reports will not be +; generated for randomize() calls having a "no error" severity level) +; +; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command +; line switch. +; +; The default is 1 (basic debug). +; SolveFailDebug = 1 + +; Upon encountering a randomize() failure, generate a simplified testcase that +; will reproduce the failure. Optionally output the testcase to a file. +; Testcases for 'no-solution' failures will only be produced if SolveFailDebug +; is enabled (see above). +; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" +; command line switch. +; The default is OFF (do not generate a testcase). To enable testcase +; generation, uncomment this variable. To redirect testcase generation to a +; file, specify the name of the output file. +; SolveFailTestcase = + +; Specify solver timeout threshold (in seconds). randomize() will fail if the +; CPU time required to evaluate any randset exceeds the specified timeout. +; The default value is 500. A value of 0 will disable timeout failures. +; SolveTimeout = 500 + +; Specify the alternative behavior during solver replay. Must be used when combined with -solvereplay switch. +; SolveReplayOpt=[+|-][,[+|-]]*" +' Valid settings: +; validate : toggle the checking of value changes of non-random variables involved in randomize(). (default is off)" +; SolveReplayOpt=validate + +; Switch to specify options that control the behavior of the solver profiler.. +; Valid options are: +; cputime - use CPU time instead of elapsed time (wall time) to measure performance data (default is off) +; randsets - enable detailed profiling of randsets (default is off) +; testgen - generate testcases for profiled randsets (only when randsets option is enabled) (default is off) +; SolverFProf = [+|-]