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PLAYMOD3.ASM
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; ****************************************************************************
; playmod3.asm (for MSDOS)
; ----------------------------------------------------------------------------
; PLAYMOD3.COM ! ICH AC97 MOD PLAYER & VGA DEMO program by Erdogan TAN
;
; 18/02/2017
;
; [ Last Modification: 19/05/2024 ]
;
; Derived from source code of 'PLAYWAV.COM' ('PLAYWAV.ASM') by Erdogan Tan
; (17/02/2017)
; Modified from 'PLAYMOD2.COM' ('playmod2.asm') source code
; AC97 MOD PLAYER & VGA DEMO program (tuneloop version)
; by Erdogan TAN (12/05/2024)
;
; Derived from source code of 'PLAY.EXE' (TINYPLAY) by Carlos Hasan (1993)
; PLAY.EXE: PLAY.ASM, MODLOAD.ASM, MODPLAY.ASM, SB.ASM
;
; Assembler: NASM 2.15
; ----------------------------------------------------------------------------
; nasm playmod3.asm -l playmod3.lst -o PLAYMOD3.COM
; ****************************************************************************
; Tiny MOD Player v0.1b by Carlos Hasan.
; July 14th, 1993.
;=============================================================================
; PLAYWAV.ASM / PLAYER.ASM / TINYPLAY.ASM
;=============================================================================
; Audio controller, codec & PCI functions are derived from '.wav file player
; for DOS' source code by Jeff Leyda (PLAYER.EXE), Sep 02, 2002.
; AC97 Interrupt version ; 12/05/2024
[BITS 16]
[org 100h]
Start:
; 15/05/2024
; 13/05/2024
; Clear BSS (uninitialized data) area
;xor ax, ax ; 0
;mov cx, (EOF - bss_start)/2
;mov di, bss_start
;rep stosw
call DetectICH ; Detect AC97 Audio Device
GetFileName: ; Parse the Command line...
mov si, 80h
mov bl, [si]
xor bh, bh
inc bx
mov byte [si+bx], 0 ; make AsciiZ filename.
inc si
ScanName:
lodsb
test al, al
je pmsg_2017
cmp al, 20h
je short ScanName ; scan start of name.
mov di, si
dec di
ScanPeriod:
lodsb
cmp al, '.' ; if period NOT found,
je short PrintMesg ; then add a .MOD extension.
test al, al
jnz short ScanPeriod
dec si
SetExt:
;mov byte [si+0], '.'
;mov byte [si+1], 'M'
;mov byte [si+2], 'O'
;mov byte [si+3], 'D'
mov dword [si], '.MOD'
mov byte [si+4], 0
PrintMesg:
mov ax, 0900h ; Prints the Credits Text.
;lea dx, [Credits]
mov dx, Credits
int 21h
; 13/05/2024
call write_ac97_dev_info
mov ax, 0900h ; Prints the Credits Text.
mov dx, CRLF
int 21h
LoadMod:
; es:di = Filename address
push es
push di
call LoadModule ; Load the MODule...
cmp word [ErrorInfo], 0 ; any error loading?
je short init_codec
mov ax, 0900h ; yes, print error and Exit.
;lea dx, [ErrorMesg]
mov dx, ErrorMesg
int 21h
jmp Exit
init_codec:
; 13/05/2024
;call write_ac97_dev_info
; 08/05/2024
; 17/02/2017
;mov dx, [stats_cmd]
;or dl, IO_ENA+BM_ENA ; enable IO and bus master
;call pciRegWrite16 ; pciRegWrite8
; 18/02/2017
;mov word [sample_rate], 22050 ; Mixing at 22.050 kHz
; 15/05/2024
mov word [sample_rate], 24000
; 16/05/2024
;mov word [sample_rate], 16000
; 08/05/2024
; (48 kHZ mixing is necessary
; if the AC97 hardware/codec has not got VRA feature)
; ((or frequency converting code would be needed))
;mov word [sample_rate], 48000 ; Mixing at 48 kHz
; setup the Codec (actually mixer registers)
call codecConfig ; unmute codec, set rates.
jnc short PlayNow
_codec_err:
push cs
pop ds
mov dx, CodecErrMsg
mov ah, 9
int 21h
jmp Exit
CodecErrMsg db "Codec Error!"
db CR,LF,"$"
PlayNow:
mov ax, BdlBuffer
mov [BDL_BUFFER], ax
mov ax, DmaBuffer ; DmaBuffer (4096 bytes) buff addr
mov [DMA_BUFFER1], ax ; 2048 byte half buffer 1
add ax, BUFFERSIZE ; code/current segment
mov [DMA_BUFFER2], ax ; 2048 byte half buffer 2
;mov word [MixSpeed], 22050 ; Mixing at 22.050 kHz
call StartPlaying
mov ax, 0013h ; Set Mode 320x200x256
int 10h
mov cx, 128 ; Make a lookup table
xor bx, bx ; for fastest pixel
mov dx, 320*(100-64) ; addressing.
MakeOfs:
mov [RowOfs+bx], dx
mov [RowOfs+bx+2], dx
add dx, 320
add bx, 4
loop MakeOfs
; Note: Normally IRQ 0 calls the ModPlay Polling at 18.2Hz thru
; the software interrupt 1Ch. If the IRQ 0 is disabled, then
; the INT 1Ch MUST BE CALLED at least MixSpeed/1024 times per
; second, or the module will sound "looped".
; Because we need better sync with the ModPlayer to draw the scope,
; the polling is called from my routine, and then the irq 0 must be
; disabled. The [DmaBuffer] points to the current buffer of 8-bit
; samples played by the Sound Blaster. Note that some samples are
; discarded in the next code, just for fun!
;in al, 21h ; disable irq 0!
;or al, 00000001b
;out 21h, al
call ModPlay ; 13/02/2017
;in al, 21h ; enable irq 0!
;and al, 11111110b
;out 21h, al
mov ax, 0003h ; Set Text Mode 80x25x16
int 10h
; 16/05/2024
;call StopPlaying ; STOP!
Exit:
;call FreeModule ; Free MODule core.
error_exit:
mov ax, 4C00h ; Bye!
int 21h
here:
jmp short here
pmsg_2017:
mov ax, 0900h ; Prints the Credits Text.
;lea dx, [msg_2017]
mov dx, msg_2017
int 21h
jmp short Exit
DetectICH:
; 18/02/2017
; Detech Intel ICH based AC97 Audio Device
call pciFindDevice ; AC97.ASM (PLAYWAV.COM)
jnc short _1
; couldn't find the audio device!
;push cs
;pop ds
mov dx, noDevMsg
mov ah, 9
int 21h
jmp short error_exit
noDevMsg db "Error: Unable to find Intel ICH based audio device!",CR,LF,"$"
_1:
; 18/02/2017
; eax = BUS/DEV/FN
; 00000000BBBBBBBBDDDDDFFF00000000
; edx = DEV/VENDOR
; DDDDDDDDDDDDDDDDVVVVVVVVVVVVVVVV
mov [bus_dev_fn], eax
mov [dev_vendor], edx
; get ICH base address regs for mixer and bus master
mov al, NAMBAR_REG
call pciRegRead16 ; read PCI registers 10-11
;and dx, IO_ADDR_MASK ; mask off BIT0
; 14/05/2024
and dl, 0FEh
mov [NAMBAR], dx ; save audio mixer base addr
mov al, NABMBAR_REG
call pciRegRead16
;and dx, IO_ADDR_MASK
; 14/05/2024
and dl, 0C0h
mov [NABMBAR], dx ; save bus master base addr
; 08/05/2024
; 06/11/2023
;; init controller
;; 17/02/2017
;mov al, PCI_CMD_REG ; command register (04h)
;call pciRegRead16 ; pciRegRead8
;
;; eax = BUS/DEV/FN/REG
;; dx = PCI Command Register Content ; 17/02/2017
;; 00000000CCCCCCCC
;mov [stats_cmd], dx
;
; 06/11/2023
;mov al, PCI_IO_BASE ; IO base address register (10h)
;call pciRegRead32
;
;and dx, 0FFC0h ; IO_ADDR_MASK (0FFFE) ?
;mov [ac97_io_base], dx
mov al, AC97_INT_LINE ; Interrupt line register (3Ch)
call pciRegRead8 ; 17/02/2017
mov [ac97_int_ln_reg], dl
; 28/11/2016
;mov bx, 1 ; 08/05/2024
xor dh, dh ; 17/02/2017
; 10/11/2023
;mov cx, dx
;shl bx, cl
; 04/11/2023
cli
;not bx
in al, 0A1h ; irq 8-15
mov ah, al
in al, 21h ; irq 0-7
; 04/11/2023
; save IRQ status
mov [IRQ_status], ax
; 12/05/2024 (enable AC97 IRQ)
;mov cl, dl
;mov bx, 1
;shl bx, cl
;not bx
;and ax, bx
;out 21h, al
;mov al, ah
;out 0A1h, al
; 15/05/2024
;and ax, bx ; unmask
btr ax, dx ; unmask
out 21h, al ; enable interrupt (if irq <= 7)
mov al, ah
out 0A1h, al ; enable interrupt (if irq > 7)
;not bx
; 08/05/2024
;mov dx, 4D1h ;8259 ELCR1
;in al, dx
;mov ah, al
;mov dx, 4D0h
;in al, dx
;;or ax, bx
;bts ax, cx
;mov dx, 4D0h
;out dx, al ;set level-triggered mode
;mov al, ah
;mov dx, 4D1h
;out dx, al ;set level-triggered mode
; 24/11/2016 - Erdogan Tan
;mov bx, cx
; 10/11/2023
mov bx, dx
mov bl, [bx+irq_int]
shl bx, 2 ; * 4
; set up interrupt vector
; 30/11/2016
push es
xor ax, ax
mov es, ax
; 04/11/2023
; save interrupt vector
;mov ax, [es:bx]
; 13/05/2024
mov ax, ac97_int_handler
xchg ax, [es:bx]
mov [IRQ_vector], ax
;mov ax, [es:bx+2]
; 13/05/2024
mov ax, cs
xchg ax, [es:bx+2]
mov [IRQ_vector+2], ax
; 13/05/2024
;mov word [es:bx], ac97_int_handler
;mov ax, cs
;mov [es:bx+2], ax
pop es
; 04/11/2023
sti
retn
; 16/05/2024
%if 0
; 15/05/2024
ac97_int_handler:
; 13/05/2024
; 12/05/2024
; 11/05/2024
; 11/11/2023
; 10/11/2023
; 17/02/2016
push eax ; 11/11/2023
push dx
; 05/11/2023
;push cx
;push bx
;push si
;push di
; 10/11/2023
; EOI at first
mov al, 20h
test byte [ac97_int_ln_reg], 8
jz short _ih_0
out 0A0h, al ; 20h ; EOI
_ih_0:
out 20h, al ; 20h ; EOI
; 11/11/2023
; 09/11/2023
mov dx, GLOB_STS_REG
add dx, [NABMBAR]
in eax, dx
; 12/05/2024
; 09/11/2023
;cmp eax, 0FFFFFFFFh ; -1
;je short _ih_3
; 15/05/2024
inc eax ; 0FFFFFFFFh
jz short _ih_3
dec eax ; 0
jz short _ih_3
; 15/05/2024
cmp byte [tLoop], 1
jb short _ih_2
; 12/05/2024
;test al, 40h ; PCM Out Interrupt
; 15/05/2024
test al, PCM_OUT_IRQ
jnz short _ih_1
; 15/05/2024
;test eax, eax
;jz short _ih_3
; 12/05/2024
;test ax, PCM_OUT_IRQ
;jnz short _ih_1
;mov dx, GLOB_STS_REG
;add dx, [NABMBAR]
; 12/05/2024
;out dx, eax
jmp short _ih_2
;jmp short _ih_3
; .....
;mov al, 1
; 10/11/2023
;mov [tLoop], al ; 1
;cmp [inside], al ; 1
;jnb short _ih_2 ; busy
;mov [inside], al ; 1
;
;; 09/11/2023
;mov dx, [NABMBAR]
;add dx, PO_SR_REG ; set pointer to Status reg
;in al, dx
;; 10/11/2023
;;;out dx, eax
;;out dx, al ; clear interrupt event
; ; (by writing 1 to same bits)
;
;;mov [pcm_irq_status], al ; 05/11/2023
;test al, BCIS ; Buffer Completion Interrupt Status (Bit 3)
;jz short _ih_3
; .....
_ih_1:
; 11/11/2023
;push eax
; 15/05/2024
push ax
; 13/05/2024
mov ax, 1Ch ; FIFOE(=16)+BCIS(=8)+LVBCI(=4)
mov dx, PO_SR_REG
add dx, [NABMBAR]
out dx, ax
; 13/05/2024
mov dx, PO_CIV_REG
add dx, [NABMBAR]
in al, dx
mov ah, al
dec al
and al, 1Fh
mov dx, PO_LVI_REG
add dx, [NABMBAR]
out dx, al
and ah, 1
; 13/05/2024
inc ah
mov [tBuff], ah ; 1 = Buffer 1, 2 = Buffer 2
; 13/05/2024
; 10/11/2023
; 28/11/2016 - Erdogan Tan
;call tuneLoop
; 11/11/2023
;pop eax
; 15/05/2024
pop ax
mov dx, GLOB_STS_REG
add dx, [NABMBAR]
_ih_2: ; 12/05/2024
out dx, eax
; 12/05/2024
_ih_3:
; 11/11/2023
;mov dx, [NABMBAR]
;add dx, PO_SR_REG ; set pointer to Status reg
;mov ax, 1Ch
;out dx, ax
; ; 10/11/2023
; mov al, 20h
; test byte [ac97_int_ln_reg], 8
; jz short _ih_3
; out 0A0h, al ; 20h ; EOI
;_ih_3:
; out 20h, al ; 20h ; EOI
;_ih_4:
;mov byte [inside], 0
;pop di
;pop si
;pop bx
;pop cx
pop dx
pop eax ; 11/11/2023
iret
%else
; 16/05/2024
; 15/05/2024
ac97_int_handler:
; 13/05/2024
; 12/05/2024
; 11/05/2024
; 11/11/2023
; 10/11/2023
; 17/02/2016
push ax ; + ; 16/05/2024
;push eax ; * ; 11/11/2023
push dx ; **
; 05/11/2023
;push cx
;push bx
;push si
;push di
; 16/05/2024
; 10/11/2023
; EOI at first
mov al, 20h
test byte [ac97_int_ln_reg], 8
jz short _ih_0
out 0A0h, al ; 20h ; EOI
_ih_0:
out 20h, al ; 20h ; EOI
; 16/05/2024
; mov dx, GLOB_STS_REG
; add dx, [NABMBAR]
; in eax, dx
;
; inc eax ; 0FFFFFFFFh
; jz short _ih_3
; dec eax ; 0
; ;jz short _ih_3
;_ih_3:
; ; 16/05/2024
; push eax ; ***
; 16/05/2024
; 24/11/2023 (TRDOS386 'audio.s')
mov dx, [NABMBAR]
add dx, PO_SR_REG
in ax, dx
test al, BCIS ; bit 3, 8
jz short _ih_2
; 15/05/2024
cmp byte [tLoop], 1
jb short _ih_2
_ih_1:
; 16/05/2024
; 13/05/2024
;mov ax, 1Ch ; FIFOE(=16)+BCIS(=8)+LVBCI(=4)
;add dx, PO_SR_REG
;add dx, [NABMBAR]
;out dx, ax
; 16/05/2024
push ax ; ****
; 13/05/2024
mov dx, PO_CIV_REG
add dx, [NABMBAR]
in al, dx
mov ah, al
dec al
and al, 1Fh
mov dx, PO_LVI_REG
add dx, [NABMBAR]
out dx, al
and ah, 1
; 13/05/2024
inc ah
mov [tBuff], ah ; 1 = Buffer 1, 2 = Buffer 2
; 13/05/2024
; 10/11/2023
; 28/11/2016 - Erdogan Tan
;call tuneLoop
; 16/05/2024
pop ax ; ****
; 16/05/2024
_ih_2:
;mov ax, 1Ch ; FIFOE(=16)+BCIS(=8)+LVBCI(=4)
mov dx, [NABMBAR]
add dx, PO_SR_REG
out dx, ax
; ; 16/05/2024
; pop eax ; ***
;
; or eax, eax
; jz short _ih_4
;
; mov dx, GLOB_STS_REG
; add dx, [NABMBAR]
; out dx, eax
; 16/05/2024
_ih_4:
; 10/11/2023
;mov al, 20h
;test byte [ac97_int_ln_reg], 8
;jz short _ih_5
;out 0A0h, al ; 20h ; EOI
;_ih_5:
;out 20h, al ; 20h ; EOI
;_ih_6:
;pop di
;pop si
;pop bx
;pop cx
pop dx ; **
;pop eax ; * ; 11/11/2023
pop ax ; + ; 16/05/2024
iret
%endif
;=============================================================================
; PCI.ASM
;=============================================================================
; EQUATES
;constants of stuff that seem hard to remember at times.
TRUE EQU 1
FALSE EQU 0
ENABLED EQU 1
DISABLED EQU 0
BIT0 EQU 1
BIT1 EQU 2
BIT2 EQU 4
BIT3 EQU 8
BIT4 EQU 10h
BIT5 EQU 20h
BIT6 EQU 40h
BIT7 EQU 80h
BIT8 EQU 100h
BIT9 EQU 200h
BIT10 EQU 400h
BIT11 EQU 800h
BIT12 EQU 1000h
BIT13 EQU 2000h
BIT14 EQU 4000h
BIT15 EQU 8000h
BIT16 EQU 10000h
BIT17 EQU 20000h
BIT18 EQU 40000h
BIT19 EQU 80000h
BIT20 EQU 100000h
BIT21 EQU 200000h
BIT22 EQU 400000h
BIT23 EQU 800000h
BIT24 EQU 1000000h
BIT25 EQU 2000000h
BIT26 EQU 4000000h
BIT27 EQU 8000000h
BIT28 EQU 10000000h
BIT29 EQU 20000000h
BIT30 EQU 40000000h
BIT31 EQU 80000000h
;special characters
NUL EQU 0
NULL EQU 0
BELL EQU 07
BS EQU 08
TAB EQU 09
LF EQU 10
CR EQU 13
ESCAPE EQU 27 ;ESC is a reserved word....
;file stuff
READONLY EQU BIT0
HIDDEN EQU BIT1
SYSTEM EQU BIT2
VOLUME EQU BIT3 ;ignored for file access
DIRECTORY EQU BIT4 ;must be 0 for file access
ARCHIVE EQU BIT5
SHAREABLE EQU BIT7 ;for novell networks
OPEN EQU 2 ; open existing file
CREATE EQU 1 ; create new file
; PCI equates
; PCI function address (PFA)
; bit 31 = 1
; bit 23:16 = bus number (0-255)
; bit 15:11 = device number (0-31)
; bit 10:8 = function number (0-7)
; bit 7:0 = register number (0-255)
IO_ADDR_MASK EQU 0FFFEh ; mask off bit 0 for reading BARs
PCI_INDEX_PORT EQU 0CF8h
PCI_DATA_PORT EQU 0CFCh
PCI32 EQU BIT31 ; bitflag to signal 32bit access
PCI16 EQU BIT30 ; bitflag for 16bit access
PCI_FN0 EQU 0 << 8
PCI_FN1 EQU 1 << 8
PCI_FN2 EQU 2 << 8
PCI_FN3 EQU 3 << 8
PCI_FN4 EQU 4 << 8
PCI_FN5 EQU 5 << 8
PCI_FN6 EQU 6 << 8
PCI_FN7 EQU 7 << 8
PCI_CMD_REG EQU 04h ; reg 04, command reg
IO_ENA EQU BIT0 ; i/o decode enable
MEM_ENA EQU BIT1 ; memory decode enable
BM_ENA EQU BIT2 ; bus master enable
; CODE
; AC97.ASM
; PCI device register reader/writers.
; NASM version: Erdogan Tan (29/11/2016)
; Last Update: 17/02/2017
;===============================================================
; 8/16/32bit PCI reader
;
; Entry: EAX=PCI Bus/Device/fn/register number
; BIT30 set if 32 bit access requested
; BIT29 set if 16 bit access requested
; otherwise defaults to 8bit read
;
; Exit: DL,DX,EDX register data depending on requested read size
;
; Note: this routine is meant to be called via pciRegRead8, pciRegread16,
; or pciRegRead32, listed below.
;
; Note2: don't attempt to read 32bits of data from a non dword aligned reg
; number. Likewise, don't do 16bit reads from non word aligned reg #
;
pciRegRead:
push ebx
push cx
mov ebx, eax ; save eax, dh
mov cl, dh
and eax, (~PCI32)+PCI16 ; clear out data size request
or eax, BIT31 ; make a PCI access request
and al, ~3 ; NOT 3 ; force index to be dword
mov dx, PCI_INDEX_PORT
out dx, eax ; write PCI selector
mov dx, PCI_DATA_PORT
mov al, bl
and al, 3 ; figure out which port to
add dl, al ; read to
in eax, dx ; do 32bit read
test ebx, PCI32
jz short _pregr1
mov edx, eax ; return 32bits of data
_pregr1:
mov dx, ax ; return 16bits of data
test ebx, PCI32+PCI16
jnz short _pregr2
mov dh, cl ; restore dh for 8 bit read
_pregr2:
mov eax, ebx ; restore eax
and eax, (~PCI32)+PCI16 ; clear out data size request
pop cx
pop ebx
retn
pciRegRead8:
and eax, (~PCI16)+PCI32 ; set up 8 bit read size
jmp short pciRegRead ; call generic PCI access
pciRegRead16:
and eax, (~PCI16)+PCI32 ; set up 16 bit read size
or eax, PCI16 ; call generic PCI access
jmp short pciRegRead
pciRegRead32:
and eax, (~PCI16)+PCI32 ; set up 32 bit read size
or eax, PCI32 ; call generic PCI access
jmp short pciRegRead
;===============================================================
; 8/16/32bit PCI writer
;
; Entry: EAX=PCI Bus/Device/fn/register number
; BIT31 set if 32 bit access requested
; BIT30 set if 16 bit access requested
; otherwise defaults to 8bit read
; DL/DX/EDX data to write depending on size
;
;
; note: this routine is meant to be called via pciRegWrite8, pciRegWrite16,
; or pciRegWrite32 as detailed below.
;
; Note2: don't attempt to write 32bits of data from a non dword aligned reg
; number. Likewise, don't do 16bit writes from non word aligned reg #
;
pciRegWrite:
push ebx
push cx
mov ebx, eax ; save eax, dx
mov cx, dx
or eax, BIT31 ; make a PCI access request
and eax, ~PCI16 ; NOT PCI16 ; clear out data size request
and al, ~3 ; NOT 3 ; force index to be dword
mov dx, PCI_INDEX_PORT
out dx, eax ; write PCI selector
mov dx, PCI_DATA_PORT
mov al, bl
and al, 3 ; figure out which port to
add dl, al ; write to
mov eax, edx ; put data into eax
mov ax, cx
out dx, al
test ebx, PCI16+PCI32 ; only 8bit access? bail
jz short _pregw1
out dx, ax ; write 16 bit value
test ebx, PCI16 ; 16bit requested? bail
jnz short _pregw1
out dx, eax ; write full 32bit
_pregw1:
mov eax, ebx ; restore eax
and eax, (~PCI32)+PCI16 ; clear out data size request
mov dx, cx ; restore dx
pop cx
pop ebx
ret
pciRegWrite8:
and eax, (~PCI16)+PCI32 ; set up 8 bit write size
jmp short pciRegWrite ; call generic PCI access
pciRegWrite16:
and eax, (~PCI16)+PCI32 ; set up 16 bit write size
or eax, PCI16 ; call generic PCI access
jmp short pciRegWrite
pciRegWrite32:
and eax, (~PCI16)+PCI32 ; set up 32 bit write size
or eax, PCI32 ; call generic PCI access
jmp short pciRegWrite
; AC97.ASM (PLAYWAV.COM)
; 17/02/2017 (Modifed by Erdogan Tan for various ICH device IDs)
;===============================================================
; PCIFindDevice: scan through PCI space looking for a device+vendor ID
;
; ENTRY: none
;; Entry: EAX=Device+Vendor ID
;
; Exit: EAX=PCI address if device found
; EDX=Device+Vendor ID
; CY clear if found, set if not found. EAX invalid if CY set.
;
; [old stackless] Destroys: ebx, esi, edi, cl
;
pciFindDevice:
;push cx
;push eax ; *
;push esi
;push edi
;mov esi, eax ; save off vend+device ID
; 17/02/2017
mov si, valid_ids ; address of Valid ICH (AC97) Device IDs
mov cx, valid_id_count
pfd_0:
mov edi, (80000000h - 100h) ; start with bus 0, dev 0 func 0
nextPCIdevice:
add edi, 100h
cmp edi, 80FFF800h ; scanned all devices?
;stc
;je short PCIScanExit ; not found
jb short pfd_1
mov edi, 80000000h
add si, 4 ; scan for next device ID
loop pfd_1
stc
;jmp short PCIScanExit
retn
pfd_1:
mov eax, edi ; read PCI registers
call pciRegRead32
;cmp edx, esi ; found device?
cmp edx, dword [si]
jne short nextPCIdevice
;clc
PCIScanExit:
;pushf
mov eax, BIT31
not eax
and eax, edi ; return only bus/dev/fn #
;popf
;pop edi
;pop esi
;pop edx ; *
;pop cx
retn
;=============================================================================
; CODEC.ASM
;=============================================================================
; EQUATES
;Codec registers.
;
;Not all codecs are created equal. Refer to the spec for your specific codec.
;
;All registers are 16bits wide. Access to codec registers over the AC97 link
;is defined by the OEM.
;
;Secondary codec's are accessed by ORing in BIT7 of all register accesses.
;
; each codec/mixer register is 16bits
CODEC_RESET_REG equ 00 ; reset codec
CODEC_MASTER_VOL_REG equ 02 ; master volume
CODEC_HP_VOL_REG equ 04 ; headphone volume
CODEC_MASTER_MONO_VOL_REG equ 06 ; master mono volume
CODEC_MASTER_TONE_REG equ 08 ; master tone (R+L)
CODEC_PCBEEP_VOL_REG equ 0ah ; PC beep volume
CODEC_PHONE_VOL_REG equ 0bh ; phone volume
CODEC_MIC_VOL_REG equ 0eh ; MIC volume
CODEC_LINE_IN_VOL_REG equ 10h ; line input volume
CODEC_CD_VOL_REG equ 12h ; CD volume
CODEC_VID_VOL_REG equ 14h ; video volume
CODEC_AUX_VOL_REG equ 16h ; aux volume
CODEC_PCM_OUT_REG equ 18h ; PCM output volume
CODEC_RECORD_SELECT_REG equ 1ah ; record select input
CODEC_RECORD_VOL_REG equ 1ch ; record volume
CODEC_RECORD_MIC_VOL_REG equ 1eh ; record mic volume
CODEC_GP_REG equ 20h ; general purpose
CODEC_3D_CONTROL_REG equ 22h ; 3D control
; 24h is reserved
CODEC_POWER_CTRL_REG equ 26h ; powerdown control
CODEC_EXT_AUDIO_REG equ 28h ; extended audio
CODEC_EXT_AUDIO_CTRL_REG equ 2ah ; extended audio control
CODEC_PCM_FRONT_DACRATE_REG equ 2ch ; PCM out sample rate
CODEC_PCM_SURND_DACRATE_REG equ 2eh ; surround sound sample rate
CODEC_PCM_LFE_DACRATE_REG equ 30h ; LFE sample rate
CODEC_LR_ADCRATE_REG equ 32h ; PCM in sample rate
CODEC_MIC_ADCRATE_REG equ 34h ; mic in sample rate
; registers 36-7a are reserved on the ICH
CODEC_VENDORID1_REG equ 7ch ; codec vendor ID 1
CODEC_VENDORID2_REG equ 7eh ; codec vendor ID 2
; Mixer registers 0 through 51h reside in the ICH and are not forwarded over
; the AC97 link to the codec, which I think is a little weird. Looks like
; the ICH makes it so you don't need a fully functional codec to play audio?
;
; whenever 2 codecs are present in the system, use BIT7 to access the 2nd
; set of registers, ie 80h-feh
PRIMARY_CODEC equ 0 ; 0-7F for primary codec
SECONDARY_CODEC equ BIT7 ; 80-8f registers for 2ndary