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1. arithmetic-encoder-av1 arithmetic-encoder-av1 Public

   This project is being developed as part of a Master's degree research sponsored by Brazil's CNPQ. It's goal is to design a hardware architecture to accelerate the AV1 arithmetic encoder.

   Verilog 26 3

2. pamPy pamPy Public

   Development of a processor, in Verilog, able to executes Python algorithm.

   Verilog 2

3. new_pythonProcessor new_pythonProcessor Public

   Development of a processor, in VHDL, able to executes Python Algorithm.

   VHDL 2

4. pyConv pyConv Public

   Converter algorithm created to generate the memory inicialization files (.mif and .mem) for Quartus II and Modelsim based on Python Assembler code entry.

   C 2

5. Projeto_Redes Projeto_Redes Public

   FTP server implemented in C based on RFC 679.

   C