chore(core): unify comment style in startup_init.c

[no changelog]

core/embed/sys/startup/stm32f4/startup_init.c

@@ -191,20 +191,20 @@ void SystemInit(void) {
 
 #ifdef TREZOR_MODEL_T2T1
 void set_core_clock(clock_settings_t settings) {
-  /* Enable HSI clock */
+  // Enable HSI clock
   RCC->CR |= RCC_CR_HSION;
 
-  /* Wait till HSI is ready */
+  // Wait till HSI is ready
   while (!(RCC->CR & RCC_CR_HSIRDY))
     ;
 
-  /* Select HSI clock as main clock */
+  // Select HSI clock as main clock
   RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_SW)) | RCC_CFGR_SW_HSI;
 
-  /* Disable PLL */
+  // Disable PLL
   RCC->CR &= ~RCC_CR_PLLON;
 
-  /* Set PLL settings */
+  // Set PLL settings
   clock_conf_t conf = clock_conf[settings];
   RCC->PLLCFGR =
       (RCC_PLLCFGR_RST_VALUE & ~RCC_PLLCFGR_PLLQ & ~RCC_PLLCFGR_PLLSRC &
@@ -215,14 +215,14 @@ void set_core_clock(clock_settings_t settings) {
       (conf.plln << RCC_PLLCFGR_PLLN_Pos) | (conf.pllm << RCC_PLLCFGR_PLLM_Pos);
   SystemCoreClock = conf.freq * 1000000U;
 
-  /* Enable PLL */
+  // Enable PLL
   RCC->CR |= RCC_CR_PLLON;
 
-  /* Wait till PLL is ready */
+  // Wait till PLL is ready
   while (!(RCC->CR & RCC_CR_PLLRDY))
     ;
 
-  /* Enable PLL as main clock */
+  // Enable PLL as main clock
   RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_SW)) | RCC_CFGR_SW_PLL;
 
   systick_update_freq();

core/embed/sys/startup/stm32u5/startup_init.c

@@ -164,26 +164,26 @@ void SystemInit(void) {
   while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLASH_ACR_LATENCY_5WS)
     ;
 
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set MSION bit */
+  // Reset the RCC clock configuration to the default reset state
+  // Set MSION bit
   RCC->CR = RCC_CR_MSISON;
 
-  /* Reset CFGR register */
+  // Reset CFGR register
   RCC->CFGR1 = 0U;
   RCC->CFGR2 = 0U;
   RCC->CFGR3 = 0U;
 
-  /* Reset HSEON, CSSON , HSION, PLLxON bits */
+  // Reset HSEON, CSSON , HSION, PLLxON bits
   RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLL1ON | RCC_CR_PLL2ON |
                RCC_CR_PLL3ON | RCC_CR_HSI48ON);
 
-  /* Reset PLLCFGR register */
+  // Reset PLLCFGR register
   RCC->PLL1CFGR = 0U;
 
-  /* Reset HSEBYP bit */
+  // Reset HSEBYP bit
   RCC->CR &= ~(RCC_CR_HSEBYP);
 
-  /* Disable all interrupts */
+  // Disable all interrupts
   RCC->CIER = 0U;
 
   __HAL_RCC_PWR_CLK_ENABLE();
@@ -225,8 +225,7 @@ void SystemInit(void) {
   while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == 0U)
     ;
 
-  /** Initializes the CPU, AHB and APB buses clocks
-   */
+  //Initializes the CPU, AHB and APB buses clocks
   FLASH->ACR = FLASH_ACR_LATENCY_4WS;
   // wait until the new wait state config takes effect -- per section 3.5.1
   // guidance
@@ -239,17 +238,13 @@ void SystemInit(void) {
 
   MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, RCC_SYSCLKSOURCE_PLLCLK);
 
-  /*
-   * Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral
-   */
+  // Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral
   HAL_PWREx_DisableUCPDDeadBattery();
 
 #ifdef USE_SMPS
-  /*
-   * Switch to SMPS regulator instead of LDO
-   */
+  // Switch to SMPS regulator instead of LDO
   SET_BIT(PWR->CR3, PWR_CR3_REGSEL);
-  /* Wait until system switch on new regulator */
+  // Wait until system switch on new regulator
   while (HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_REGS))
     ;
 #endif
@@ -294,15 +289,15 @@ void SystemInit(void) {
   // enable instruction cache in default 2-way mode
   ICACHE->CR = ICACHE_CR_EN;
 
-  /* Configure Flash prefetch */
+  // Configure Flash prefetch
 #if (PREFETCH_ENABLE != 0U)
   __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
-#endif /* PREFETCH_ENABLE */
+#endif
 
-  /* Set Interrupt Group Priority */
+  // Set Interrupt Group Priority
   HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 
-  /* Update the SystemCoreClock global variable */
+  // Update the SystemCoreClock global variable
   /// SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 &
   /// RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos];