fixup! feat(core): enable LSE on T3W1

core/embed/sys/tamper/stm32u5/tamper.c

@@ -33,68 +33,64 @@
 #define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos)
 #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk
 
-/*
- * This function replaces calls to universal, but flash-wasting
- * functions HAL_RCC_OscConfig and HAL_RCCEx_PeriphCLKConfig.
- *
- * This is the configuration before the optimization:
- *  clk_init_def.PeriphClockSelection = RCC_PERIPHCLK_RTC;
- *  clk_init_def.RTCClockSelection = RCC_RTCCLKSOURCE_LSI (or
- * RCC_RTCCLKSOURCE_LSE); HAL_RCCEx_PeriphCLKConfig(&clk_init_def);
- */
+// This function replaces calls to universal, but flash-wasting
+// functions HAL_RCC_OscConfig and HAL_RCCEx_PeriphCLKConfig.
+//
+// This is the configuration before the optimization:
+// clk_init_def.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+// clk_init_def.RTCClockSelection = RCC_RTCCLKSOURCE_LSI (or
+// RCC_RTCCLKSOURCE_LSE); HAL_RCCEx_PeriphCLKConfig(&clk_init_def);
 HAL_StatusTypeDef clk_init(uint32_t source) {
-  uint32_t tickstart = 0U;
 
-  FlagStatus pwrclkchanged = RESET;
+  bool pwrclkchanged = false;
 
-  /* Enable Power Clock */
+  // Enable Power Clock
   if (__HAL_RCC_PWR_IS_CLK_DISABLED()) {
     __HAL_RCC_PWR_CLK_ENABLE();
-    pwrclkchanged = SET;
+    pwrclkchanged = true;
   }
-  /* Enable write access to Backup domain */
+  // Enable write access to Backup domain
   SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
 
-  /* Wait for Backup domain Write protection disable */
-  tickstart = HAL_GetTick();
+  // Wait for Backup domain Write protection disable
+  uint32_t deadline = ticks_timeout(RCC_DBP_TIMEOUT_VALUE);
 
   while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) {
-    if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) {
+    if (ticks_expired(deadline)) {
       return HAL_TIMEOUT;
     }
   }
-  /* Reset the Backup domain only if the RTC Clock source selection is modified
-   * from default */
+  // Reset the Backup domain only if the RTC Clock source selection is modified
+  // from default
   uint32_t bdcr_temp = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
 
   if ((bdcr_temp != RCC_RTCCLKSOURCE_NO_CLK) && (bdcr_temp != source)) {
-    /* Store the content of BDCR register before the reset of Backup Domain */
+    // Store the content of BDCR register before the reset of Backup Domain
     bdcr_temp = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
-    /* RTC Clock selection can be changed only if the Backup Domain is reset */
+    // RTC Clock selection can be changed only if the Backup Domain is reset
     __HAL_RCC_BACKUPRESET_FORCE();
     __HAL_RCC_BACKUPRESET_RELEASE();
-    /* Restore the Content of BDCR register */
+    // Restore the Content of BDCR register
     RCC->BDCR = bdcr_temp;
   }
 
-  /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+  // Wait for LSE reactivation if LSE was enabled prior to Backup Domain reset
   if (HAL_IS_BIT_SET(bdcr_temp, RCC_BDCR_LSEON)) {
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
+    deadline = ticks_timeout(RCC_LSE_TIMEOUT_VALUE);
 
-    /* Wait till LSE is ready */
+    // Wait till LSE is ready
     while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) {
-      if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) {
+      if (ticks_expired(deadline)) {
         return HAL_TIMEOUT;
       }
     }
   }
 
-  /* Apply new RTC clock source selection */
+  // Apply new RTC clock source selection
   __HAL_RCC_RTC_CONFIG(source);
 
-  /* Restore clock configuration if changed */
-  if (pwrclkchanged == SET) {
+  // Restore clock configuration if changed
+  if (pwrclkchanged) {
     __HAL_RCC_PWR_CLK_DISABLE();
   }
   return HAL_OK;