diff --git a/core/embed/sys/startup/stm32u5/startup_init.c b/core/embed/sys/startup/stm32u5/startup_init.c
index 172c9a0faae..2d07e84288f 100644
--- a/core/embed/sys/startup/stm32u5/startup_init.c
+++ b/core/embed/sys/startup/stm32u5/startup_init.c
@@ -125,6 +125,42 @@ void lsi_init(void) {
     ;
 }
 
+/*
+ * This function replaces calls to universal, but flash-wasting
+ * function HAL_RCC_OscConfig.
+ *
+ * This is the configuration before the optimization:
+ *  osc_init_def.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ *  osc_init_def.LSEState = RCC_LSE_ON;
+ *  HAL_RCC_OscConfig(&osc_init_def);
+ */
+void lse_init(void) {
+  /* Update LSE configuration in Backup Domain control register    */
+  /* Requires to enable write access to Backup Domain of necessary */
+
+  if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) {
+    /* Enable write access to Backup domain */
+    SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
+
+    while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
+      ;
+  }
+
+  /* LSE oscillator enable */
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+
+  /* Wait till LSE is ready */
+  while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
+    ;
+
+  /* Make sure LSESYSEN/LSESYSRDY are reset */
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
+
+  /* Wait till LSESYSRDY is cleared */
+  while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U)
+    ;
+}
+
 void SystemInit(void) {
   // set flash wait states for an increasing HCLK frequency
 
@@ -228,7 +264,7 @@ void SystemInit(void) {
   PWR->SVMCR |= PWR_SVMCR_IO2SV;
 
 #ifdef USE_LSE
-  // TODO
+  lse_init();
 #else
   lsi_init();
 #endif
diff --git a/core/embed/sys/tamper/stm32u5/tamper.c b/core/embed/sys/tamper/stm32u5/tamper.c
index 560edd8a03c..ff454b355a0 100644
--- a/core/embed/sys/tamper/stm32u5/tamper.c
+++ b/core/embed/sys/tamper/stm32u5/tamper.c
@@ -39,10 +39,10 @@
  *
  * This is the configuration before the optimization:
  *  clk_init_def.PeriphClockSelection = RCC_PERIPHCLK_RTC;
- *  clk_init_def.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
- *  HAL_RCCEx_PeriphCLKConfig(&clk_init_def);
+ *  clk_init_def.RTCClockSelection = RCC_RTCCLKSOURCE_LSI (or
+ * RCC_RTCCLKSOURCE_LSE); HAL_RCCEx_PeriphCLKConfig(&clk_init_def);
  */
-HAL_StatusTypeDef clk_init(void) {
+HAL_StatusTypeDef clk_init(uint32_t source) {
   uint32_t tickstart = 0U;
 
   FlagStatus pwrclkchanged = RESET;
@@ -67,8 +67,7 @@ HAL_StatusTypeDef clk_init(void) {
    * from default */
   uint32_t bdcr_temp = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
 
-  if ((bdcr_temp != RCC_RTCCLKSOURCE_NO_CLK) &&
-      (bdcr_temp != RCC_RTCCLKSOURCE_LSI)) {
+  if ((bdcr_temp != RCC_RTCCLKSOURCE_NO_CLK) && (bdcr_temp != source)) {
     /* Store the content of BDCR register before the reset of Backup Domain */
     bdcr_temp = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
     /* RTC Clock selection can be changed only if the Backup Domain is reset */
@@ -92,7 +91,7 @@ HAL_StatusTypeDef clk_init(void) {
   }
 
   /* Apply new RTC clock source selection */
-  __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
+  __HAL_RCC_RTC_CONFIG(source);
 
   /* Restore clock configuration if changed */
   if (pwrclkchanged == SET) {
@@ -102,8 +101,11 @@ HAL_StatusTypeDef clk_init(void) {
 }
 
 void tamper_init(void) {
-  // TODO LSE
-  clk_init();
+#ifdef USE_LSE
+  clk_init(RCC_RTCCLKSOURCE_LSE);
+#else
+  clk_init(RCC_RTCCLKSOURCE_LSI);
+#endif
 
   // Enable RTC peripheral (tampers are part of it)
   __HAL_RCC_RTC_ENABLE();
diff --git a/core/site_scons/models/T3W1/trezor_t3w1_revA.py b/core/site_scons/models/T3W1/trezor_t3w1_revA.py
index 07e0e02b30e..047fc134b92 100644
--- a/core/site_scons/models/T3W1/trezor_t3w1_revA.py
+++ b/core/site_scons/models/T3W1/trezor_t3w1_revA.py
@@ -36,6 +36,7 @@ def configure(
         ("HW_REVISION", str(hw_revision)),
         ("HSE_VALUE", "32000000"),
         ("USE_HSE", "1"),
+        ("USE_LSE", "1"),
         ("FIXED_HW_DEINIT", "1"),
     ]
 
diff --git a/core/site_scons/models/T3W1/trezor_t3w1_revA0.py b/core/site_scons/models/T3W1/trezor_t3w1_revA0.py
index d622843aa41..3e66a3b1f3a 100644
--- a/core/site_scons/models/T3W1/trezor_t3w1_revA0.py
+++ b/core/site_scons/models/T3W1/trezor_t3w1_revA0.py
@@ -36,6 +36,7 @@ def configure(
         ("HW_REVISION", str(hw_revision)),
         ("HSE_VALUE", "32000000"),
         ("USE_HSE", "1"),
+        ("USE_LSE", "1"),
         ("FIXED_HW_DEINIT", "1"),
     ]
 
diff --git a/core/site_scons/models/T3W1/trezor_t3w1_revB.py b/core/site_scons/models/T3W1/trezor_t3w1_revB.py
index 6e2dc30805e..4662d1b257b 100644
--- a/core/site_scons/models/T3W1/trezor_t3w1_revB.py
+++ b/core/site_scons/models/T3W1/trezor_t3w1_revB.py
@@ -36,6 +36,7 @@ def configure(
         ("HW_REVISION", str(hw_revision)),
         ("HSE_VALUE", "32000000"),
         ("USE_HSE", "1"),
+        ("USE_LSE", "1"),
         ("FIXED_HW_DEINIT", "1"),
     ]