A C-Program that simulates Virtual Memory Management based on a text file input of logical addresses which represents sequential instructions with address range 0 thru 2^16 - 1. See the Project Report for more details regarding usage.

21Summer-VE370-Intro-to-Computer-Organization-Projects: -Project1: RISC-V Assembly, simluating c code. -Project2: 1.RISC-V64 single cycle processor. 2.RISC-V64 five-stage pipelined processor. -Project3: Virtual memory, TLB, cache, memory simulator. -Project4: Literature review on Computer Organization.

Simulates a memory-subsystem encompassing a bi-level TLB and a bi-level cache system along with a main memory following segmentation with paging with all different replacement policies

TLB simulator. LRU priority.

💻 Cache Simulator in Typescript (CLI)

Simulating TLB and its interfacing with Page Table (Virtual memory concepts)

Operating Systems Laboratory (Semester 5): Includes a Shell, a Page Table and a Translation Lookaside Buffer

2-level TLB Controller

Implementation of the Cortex-A53 memory system using a virtual memory simulator to reveal the key steps such as instruction fetch, address generation and computation, tag searches in caches, TLBs and virtual to physical address translations.

TLB (Translation Lookaside Buffer) Simulator

A collection of problem set solutions for NYU CSCI 201 Computer Systems Organization

Implement Virtual Page Yable Register(VPTR, known as page table, CAM, TLB..etc) in memory.

Model of a noncontiguous segmented memory management unit.

A Python-based simulator showcasing memory management concepts such as allocation strategies, segmentation, pagination, swapping, and TLB. Interactive examples implemented in Jupyter notebooks