assertion-based-verification

Here are 2 public repositories matching this topic...

Ghonimo / Formal-Verification-of-an-AHB2APB-Bridge

Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation including a final report and project progression presentation.

verification abp uvm formal-verification amba ahb harward computer-ar assertion-based-verification ahb2

Updated Mar 23, 2024
SystemVerilog

MohamedHussein27 / SPI-Slave-with-RAM-UVM

Star

This project uses UVM to verify an SPI Slave connected to internal RAM. It includes multiple agents (active and passive) and integrates assertion-based verification for both SPI and RAM behavior.

multi-agent spi systemverilog uvm uvm-verification assertion-based-verification

Updated Apr 24, 2025
SystemVerilog

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