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;*******************************************************************************
;* MC9S08GW64 FRAMEWORK INCLUDE FILE FOR ASM8 ASSEMBLER *
;*******************************************************************************
; FREEWARE, Copyright (c) Tony G. Papadimitriou <tonyp@acm.org>
;*******************************************************************************
#Uses macros.inc
#Message **********************
#Message * Target: MC9S08GW64 *
#Message **********************
#HcsOn
#ifdef BOOT
#Message TBoot pre-loaded
#ifexists tboot_gw64.exp
#Uses tboot_gw64.exp
#else ifexists tboot.exp
#Uses tboot.exp
#else
#Uses tboot/tboot_gw64.exp
#endif
#endif
_GW_ def 64
_GW64_ def *
; ###################################################################
; Filename : mc9s08gw64.inc
; Processor : MC9S08GW64CLK
; FileFormat: V2.32
; DataSheet : MC9S08GW64RM Rev.3 Draft A 10/2010
; Compiler : CodeWarrior compiler
; Date/Time : 1.11.2010, 16:46
; Abstract :
; This header implements the mapping of I/O devices.
;
; Copyright : 1997 - 2010 Freescale Semiconductor, Inc. All Rights Reserved.
;
; http : www.freescale.com
; mail : support@freescale.com
;
; CPU Registers Revisions:
; - none
;
; File-Format-Revisions:
; - none
;
; Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific
; derivative device. To avoid extra current drain from floating input pins, the user’s reset
; initialization routine in the application program must either enable on-chip pull-up devices
; or change the direction of unconnected pins to outputs so the pins do not float.
; ###################################################################
;*** Memory Map and Interrupt Vectors
;******************************************
STANDBYXRAM equ $18C0
STANDBYXRAM_END equ $18DF
PPAGE_0Start equ $8000
PPAGE_0End equ $90BF
PPAGE_0_1Start equ $9800
PPAGE_0_1End equ $995F
PPAGE_2Start equ $028000
PPAGE_2End equ $02BFFF
;-------------------------------------------------------------------------------
PTAD equ $00,1 ;Port A Data Register
PTADD equ $01,1 ;Port A Data Direction Register
PTBD equ $02,1 ;Port B Data Register
PTBDD equ $03,1 ;Port B Data Direction Register
PTCD equ $04,1 ;Port C Data Register
PTCDD equ $05,1 ;Port C Data Direction Register
PTDD equ $06,1 ;Port D Data Register
PTDDD equ $07,1 ;Port D Data Direction Register
PTED equ $08,1 ;Port E Data Register
PTEDD equ $09,1 ;Port E Data Direction Register
PTFD equ $0A,1 ;Port F Data Register
PTFDD equ $0B,1 ;Port F Data Direction Register
PTGD equ $0C,1 ;Port G Data Register
PTGDD equ $0D,1 ;Port G Data Direction Register
PTHD equ $0E,1 ;Port H Data Register
PTHDD equ $0F,1 ;Port H Data Direction Register
;-------------------------------------------------------------------------------
MTIM1SC equ $10,1 ;MTIM Clock Configuration Register
MTIM1CLK equ $11,1 ;MTIM Clock Configuration Register
MTIM1CNT equ $12,1 ;MTIM Counter Register
MTIM1MOD equ $13,1 ;MTIM Modulo Register
MTIM2SC equ $14,1 ;MTIM Clock Configuration Register
MTIM2CLK equ $15,1 ;MTIM Clock Configuration Register
MTIM2CNT equ $16,1 ;MTIM Counter Register
MTIM2MOD equ $17,1 ;MTIM Modulo Register
MTIM3SC equ $18,1 ;MTIM16 Status and Control Register
MTIM3CLK equ $19,1 ;MTIM16 Clock Configuration Register
MTIM3CNT equ $1A,2 ;MTIM16 Counter Register
MTIM3CNTH equ $1A,1 ;MTIM16 Counter Register High
MTIM3CNTL equ $1B,1 ;MTIM16 Counter Register Low
MTIM3MOD equ $1C,2 ;MTIM16 Modulo Register
MTIM3MODH equ $1C,1 ;MTIM16 Modulo Register High
MTIM3MODL equ $1D,1 ;MTIM16 Modulo Register Low
@bitnum MTIM_TSTP,4 ;MTIM Counter Stop
@bitnum MTIM_TRST,5 ;MTIM Counter Reset
@bitnum MTIM_TOIE,6 ;MTIM Overflow Interrupt Enable
@bitnum MTIM_TOF,7 ;MTIM Overflow Flag
@bitnum MTIM_PS0,0 ;Clock source Prescaler Bit 0
@bitnum MTIM_PS1,1 ;Clock source Prescaler Bit 1
@bitnum MTIM_PS2,2 ;Clock source Prescaler Bit 2
@bitnum MTIM_PS3,3 ;Clock source Prescaler Bit 3
@bitnum MTIM_CLKS0,4 ;Clock source Select Bit 0
@bitnum MTIM_CLKS1,5 ;Clock source Select Bit 1
;-------------------------------------------------------------------------------
PDBSC equ $20,2 ;PDB Status and Control Register
PDBSCH equ $20,1 ;PDB Status and Control High Register
PDBSCL equ $21,1 ;PDB Status and Control Low Register
PDBMOD equ $22,2 ;PDB Counter Modulus Register
PDBMODH equ $22,1 ;PDB Counter Modulus High Register
PDBMODL equ $23,1 ;PDB Counter Modulus Low Register
PDBCNT equ $24,2 ;PDB Counter Value Register
PDBCNTH equ $24,1 ;PDB Counter Value High Register
PDBCNTL equ $25,1 ;PDB Counter Value Low Register
PDBIDLY equ $26,2 ;PDB Interrupt Delay Register
PDBIDLYH equ $26,1 ;PDB Interrupt Delay High Register
PDBIDLYL equ $27,1 ;PDB Interrupt Delay Low Register
PDBCH1CR equ $28,2 ;PDB Channel 1 Control Register
PDBCH1CRH equ $28,1 ;PDB Channel 1 Control High Register
PDBCH1CRL equ $29,1 ;PDB Channel 1 Control Low Register
PDBCH1DLYA equ $2A,2 ;PDB Channel 1 Delay A Register
PDBCH1DLYAH equ $2A,1 ;PDB Channel 1 Delay A High Register
PDBCH1DLYAL equ $2B,1 ;PDB Channel 1 Delay A Low Register
PDBCH1DLYB equ $2C,2 ;PDB Channel 1 Delay B Register
PDBCH1DLYBH equ $2C,1 ;PDB Channel 1 Delay B High Register
PDBCH1DLYBL equ $2D,1 ;PDB Channel 1 Delay B Low Register
PDBCH2CR equ $30,2 ;PDB Channel 2 Control Register
PDBCH2CRH equ $30,1 ;PDB Channel 2 Control High Register
PDBCH2CRL equ $31,1 ;PDB Channel 2 Control Low Register
PDBCH2DLYA equ $32,2 ;PDB Channel 2 Delay A Register
PDBCH2DLYAH equ $32,1 ;PDB Channel 2 Delay A High Register
PDBCH2DLYAL equ $33,1 ;PDB Channel 2 Delay A Low Register
PDBCH2DLYB equ $34,2 ;PDB Channel 2 Delay B Register
PDBCH2DLYBH equ $34,1 ;PDB Channel 2 Delay B High Register
PDBCH2DLYBL equ $35,1 ;PDB Channel 2 Delay B Low Register
@bitnum PDBSCH_PRESCALER0,5 ;Clock Prescaler Select, bit 0
@bitnum PDBSCH_PRESCALER1,6 ;Clock Prescaler Select, bit 1
@bitnum PDBSCH_PRESCALER2,7 ;Clock Prescaler Select, bit 2
@bitnum PDBSCL_EN,0 ;Module Enable
@bitnum PDBSCL_IE,1 ;Interrupt Enable
@bitnum PDBSCL_TRIGSEL0,2 ;Input Trigger Select, bit 0
@bitnum PDBSCL_TRIGSEL1,3 ;Input Trigger Select, bit 1
@bitnum PDBSCL_TRIGSEL2,4 ;Input Trigger Select, bit 2
@bitnum PDBSCL_SWTRIG,5 ;Software Trigger
@bitnum PDBSCL_CONT,6 ;Continuous Mode Enable
@bitnum PDBSCL_IF,7 ;Interrupt Flag
@bitnum PDBCHxCRH_ERRB,6 ;Sequence error on TriggerB
@bitnum PDBCHxCRH_ERRA,7 ;Sequence error on TriggerA
@bitnum PDBCHxCRL_ENB,0 ;Trigger B Enable
@bitnum PDBCHxCRL_ENA,1 ;Trigger A Enable
@bitnum PDBCHxCRL_BOS0,2 ;Channel 1 Trigger B Output Select, bit 0
@bitnum PDBCHxCRL_BOS1,3 ;Channel 1 Trigger B Output Select, bit 1
@bitnum PDBCHxCRL_AOS0,4 ;Channel 1 Trigger A Output Select, bit 0
@bitnum PDBCHxCRL_AOS1,5 ;Channel 1 Trigger A Output Select, bit 1
@bitnum PDBCH2CRL_ENB,0 ;Trigger B Enable
@bitnum PDBCH2CRL_ENA,1 ;Trigger A Enable
@bitnum PDBCH2CRL_BOS0,2 ;Channel 2 Trigger B Output Select, bit 0
@bitnum PDBCH2CRL_BOS1,3 ;Channel 2 Trigger B Output Select, bit 1
@bitnum PDBCH2CRL_AOS0,4 ;Channel 2 Trigger A Output Select, bit 0
@bitnum PDBCH2CRL_AOS1,5 ;Channel 2 Trigger A Output Select, bit 1
;-------------------------------------- ;MMU related
PPAGE equ $38,1 ;Program Page Register
LAP2 equ $39,1 ;Linear Address Pointer Register 2
LAP1 equ $3A,1 ;Linear Address Pointer Register 1
LAP0 equ $3B,1 ;Linear Address Pointer Register 0
LWP equ $3C,1 ;Linear Word Post Increment Register
LBP equ $3D,1 ;Linear Byte Post Increment Register
LB equ $3E,1 ;Linear Byte Register
LAPAB equ $3F,1 ;Linear Address Pointer Add Byte Register
;--------------------------------------
ADC0SC1A equ $40,1 ;Status and Control Register 1A
ADC0SC1B equ $41,1 ;Status and Control Register 1B
ADC0CFG1 equ $42,1 ;Configuration Register 1
ADC0CFG2 equ $43,1 ;Configuration Register 2
ADC0RA equ $44,2 ;Data Result Register A
ADC0RHA equ $44,1 ;Data Result High Register A
ADC0RLA equ $45,1 ;Data Result Low Register A
ADC0RB equ $46,2 ;Data Result Register B
ADC0RHB equ $46,1 ;Data Result High Register B
ADC0RLB equ $47,1 ;Data Result Low Register B
@bitnum ADCH0,0 ;Input Channel Select Bit 0
@bitnum ADCH1,1 ;Input Channel Select Bit 1
@bitnum ADCH2,2 ;Input Channel Select Bit 2
@bitnum ADCH3,3 ;Input Channel Select Bit 3
@bitnum ADCH4,4 ;Input Channel Select Bit 4
@bitnum DIFF,5 ;Differential Mode Enable - DIFFA configures the ADC to operate in differential mode
@bitnum AIEN,6 ;Interrupt Enable - AIENA enables conversion complete interrupts. When COCOA becomes set while the respective AIENA
@bitnum COCO,7 ;Conversion Complete Flag
@bitnum ADICLK0,0 ;Input Clock Select Bit 0
@bitnum ADICLK1,1 ;Input Clock Select Bit 1
@bitnum MODE0,2 ;Conversion Mode Selection Bit 0
@bitnum MODE1,3 ;Conversion Mode Selection Bit 1
@bitnum ADLSMP,4 ;Long Sample Time Configuration
@bitnum ADIV0,5 ;Clock Divide Select Bit 0
@bitnum ADIV1,6 ;Clock Divide Select Bit 1
@bitnum ADLPC,7 ;Low Power Configuration
@bitnum ADLSTS0,0 ;Long Sample Time Select Bit 0
@bitnum ADLSTS1,1 ;Long Sample Time Select Bit 1
@bitnum ADHSC,2 ;High Speed Configuration
@bitnum ADACKEN,3 ;Asynchronous Clock Output Enable
;-------------------------------------------------------------------------------
SPI0C1 equ $48,1 ;SPI0 Control Register 1
SPI0C2 equ $49,1 ;SPI0 Control Register 2
SPI0BR equ $4A,1 ;SPI0 Baud Rate Register
SPI0S equ $4B,1 ;SPI0 Status Register
SPI0D equ $4D,1 ;SPI0 Data Register
SPI1C1 equ $50,1 ;SPI1 Control Register 1
SPI1C2 equ $51,1 ;SPI1 Control Register 2
SPI1BR equ $52,1 ;SPI1 Baud Rate Register
SPI1S equ $53,1 ;SPI1 Status Register
SPI1D equ $55,1 ;SPI1 Data Register
SPI2C1 equ $58,1 ;SPI2 Control Register 1
SPI2C2 equ $59,1 ;SPI2 Control Register 2
SPI2BR equ $5A,1 ;SPI2 Baud Rate Register
SPI2S equ $5B,1 ;SPI2 Status Register
SPI2D equ $5D,1 ;SPI2 Data Register
@bitnum SPI_LSBFE,0 ;LSB First (Shifter Direction)
@bitnum SPI_SSOE,1 ;Slave Select Output Enable
@bitnum SPI_CPHA,2 ;Clock Phase
@bitnum SPI_CPOL,3 ;Clock Polarity
@bitnum SPI_MSTR,4 ;Master/Slave Mode Select
@bitnum SPI_SPTIE,5 ;SPI Transmit Interrupt Enable
@bitnum SPI_SPE,6 ;SPI System Enable
@bitnum SPI_SPIE,7 ;SPI Interrupt Enable (for SPRF and MODF)
@bitnum SPI_SPC0,0 ;SPI Pin Control 0
@bitnum SPI_SPISWAI,1 ;SPI Stop in Wait Mode
@bitnum SPI_BIDIROE,3 ;Bidirectional Mode Output Enable
@bitnum SPI_MODFEN,4 ;Master Mode-Fault Function Enable
@bitnum SPI_MODF,4 ;Master Mode Fault Flag
@bitnum SPI_SPTEF,5 ;SPI Transmit Buffer Empty Flag
@bitnum SPI_SPRF,7 ;SPI Read Buffer Full Flag
;-------------------------------------------------------------------------------
PCNT_STATUS equ $60,2 ;PCounter Status Register
PCNT_STATUS_H equ $60,1 ;PCounter Status Register High
PCNT_STATUS_L equ $61,1 ;PCounter Status Register Low
PCNT_CTRL equ $62,2 ;PCounter Control Register
PCNT_CTRL_H equ $62,1 ;PCounter Control Register High
PCNT_CTRL_L equ $63,1 ;PCounter Control Register Low
PCNT_FCMOD equ $64,2 ;PCounter Forward Counter Modulus Register
PCNT_FCMOD_H equ $64,1 ;PCounter Forward Counter Modulus Register High
PCNT_FCMOD_L equ $65,1 ;PCounter Forward Counter Modulus Register Low
PCNT_FCNTR equ $66,2 ;PCounter Forward Counter Register
PCNT_FCNTR_H equ $66,1 ;PCounter Forward Counter Register High
PCNT_FCNTR_L equ $67,1 ;PCounter Forward Counter Register Low
PCNT_RCMOD equ $68,2 ;PCounter Reverse Counter Modulus Register
PCNT_RCMOD_H equ $68,1 ;PCounter Reverse Counter Modulus Register High
PCNT_RCMOD_L equ $69,1 ;PCounter Reverse Counter Modulus Register Low
PCNT_RCNTR equ $6A,2 ;PCounter Reverse Counter Register
PCNT_RCNTR_H equ $6A,1 ;PCounter Reverse Counter Register High
PCNT_RCNTR_L equ $6B,1 ;PCounter Reverse Counter Register Low
PCNT_PWM_MOD equ $6C,2 ;PCounter PWM Modulus Register
PCNT_PWM_MOD_H equ $6C,1 ;PCounter PWM Modulus Register High
PCNT_PWM_MOD_L equ $6D,1 ;PCounter PWM Modulus Register Low
PCNT_PWM_CH0_VAL equ $6E,2 ;PCounter PWM Channel 0 Value Register
PCNT_PWM_CH0_H_VAL equ $6E,1 ;PCounter PWM Channel 0 Value Register High
PCNT_PWM_CH0_L_VAL equ $6F,1 ;PCounter PWM Channel 0 Value Register Low
PCNT_PWM_CH1_VAL equ $70,2 ;PCounter PWM Channel 1 Value Register
PCNT_PWM_CH1_H_VAL equ $70,1 ;PCounter PWM Channel 1 Value Register High
PCNT_PWM_CH1_L_VAL equ $71,1 ;PCounter PWM Channel 1 Value Register Low
PCNT_STATE equ $72,2 ;PCounter Status Register
PCNT_STATE_H equ $72,1 ;PCounter Status Register High
PCNT_STATE_L equ $73,1 ;PCounter Status Register Low
@bitnum CURR_INV,0 ;Current state of the state machine when a state invalid event occurs, bit 0
@bitnum PSTATE_INV,4 ;Sensor input pin state when a state invalid event occurs, bit 0
@bitnum FCOVF,0 ;FCounter Overflow Flag
@bitnum RCOVF,1 ;RCounter Overflow Flag
@bitnum SINVF,2 ;State Invalid Interrupt Flag
@bitnum CHANNEL_SEL,0 ;Channel select bit 0
@bitnum PCNT_MODE0,3 ;Mode select, bit 0
@bitnum PCNT_MODE1,4 ;Mode select, bit 1
@bitnum FCOVFIE,5 ;FCounter Overflow Interrupt Enable bit
@bitnum RCOVFIE,6 ;RCounter Overflow Interrupt Eenable bit
@bitnum SINVIE,7 ;State Invalid Interrupt Enable bit
@bitnum PCNT_FILTER_VALUE,0 ;Filter value bit 0
@bitnum PCNT_CPWMS,4 ;PWM alignment selection
@bitnum PCNT_POL,5 ;PWM polarity bit
@bitnum PCNT_DIR,6 ;Direction bit
@bitnum PCNT_PCNT_EN,7 ;Enable/Disable bit
@bitnum PCNTCURR_STATE,0 ;This is for debugging purpose.These bits reflect the current state of the state machine
@bitnum PCNTPCOUNTER_STATE,3;This is for debugging purpose.These bits reflect value on sensor inputs coming into PCounter
;-------------------------------------------------------------------------------
KBISC equ $74,1 ;KBI Status and Control Register
@bitnum KBIMOD,0 ;Keyboard Detection Mode
@bitnum KBIE,1 ;Keyboard Interrupt Enable
@bitnum KBACK,2 ;Keyboard Interrupt Acknowledge
@bitnum KBF,3 ;Keyboard Interrupt Flag
KBIPE equ $75,1 ;KBI Pin Enable Register
KBIES equ $76,1 ;KBI Edge Select Register
;-------------------------------------------------------------------------------
IRQSC equ $77,1 ;Interrupt request status and control register
@bitnum IRQMOD,0 ;IRQ Detection Mode
@bitnum IRQIE,1 ;IRQ Interrupt Enable
@bitnum IRQACK,2 ;IRQ Acknowledge
@bitnum IRQF,3 ;IRQ Flag
@bitnum IRQPE,4 ;IRQ Pin Enable
@bitnum IRQEDG,5 ;IRQ Edge Select
@bitnum IRQPDD,6 ;IRQ Pull Device Disable
;-------------------------------------------------------------------------------
SCI0BD equ $78,1 ;SCI0 Baud Rate Register
SCI0BDH equ $78,1 ;SCI0 Baud Rate Register High
@bitnum RXEDGIE,6 ;RxD Input Active Edge Interrupt Enable (for RXEDGIF)
@bitnum LBKDIE,7 ;LIN Break Detect Interrupt Enable (for LBKDIF)
SCI0BDL equ $79,1 ;SCI0 Baud Rate Register Low
SCI0C1 equ $7A,1 ;SCI0 Control Register 1
SCI0C1_PT equ 0 ;Parity Type
SCI0C1_PE equ 1 ;Parity Enable
SCI0C1_ILT equ 2 ;Idle Line Type Select
SCI0C1_WAKE equ 3 ;Receiver Wakeup Method Select
SCI0C1_M equ 4 ;9-Bit or 8-Bit Mode Select
SCI0C1_RSRC equ 5 ;Receiver Source Select
SCI0C1_SCISWAI equ 6 ;SCI Stops in Wait Mode
SCI0C1_LOOPS equ 7 ;Loop Mode Select
SCI0C2 equ $7B,1 ;SCI0 Control Register 2
SCI0C2_SBK equ 0 ;Send Break
SCI0C2_RWU equ 1 ;Receiver Wakeup Control
SCI0C2_RE equ 2 ;Receiver Enable
SCI0C2_TE equ 3 ;Transmitter Enable
SCI0C2_ILIE equ 4 ;Idle Line Interrupt Enable (for IDLE)
SCI0C2_RIE equ 5 ;Receiver Interrupt Enable (for RDRF)
SCI0C2_TCIE equ 6 ;Transmission Complete Interrupt Enable (for TC)
SCI0C2_TIE equ 7 ;Transmit Interrupt Enable (for TDRE)
SCI0S1 equ $7C,1 ;SCI0 Status Register 1
SCI0S1_PF equ 0 ;Parity Error Flag
SCI0S1_FE equ 1 ;Framing Error Flag
SCI0S1_NF equ 2 ;Noise Flag
SCI0S1_OR equ 3 ;Receiver Overrun Flag
SCI0S1_IDLE equ 4 ;Idle Line Flag
SCI0S1_RDRF equ 5 ;Receive Data Register Full Flag
SCI0S1_TC equ 6 ;Transmission Complete Flag
SCI0S1_TDRE equ 7 ;Transmit Data Register Empty Flag
SCI0S2 equ $7D,1 ;SCI0 Status Register 2
SCI0S2_RAF equ 0 ;Receiver Active Flag
SCI0S2_LBKDE equ 1 ;LIN Break Detection Enable
SCI0S2_BRK13 equ 2 ;Break Character Generation Length
SCI0S2_RWUID equ 3 ;Receive Wake Up Idle Detect
SCI0S2_RXINV equ 4 ;Receive Data Inversion
SCI0S2_RXEDGIF equ 6 ;RxD Pin Active Edge Interrupt Flag
SCI0S2_LBKDIF equ 7 ;LIN Break Detect Interrupt Flag
SCI0C3 equ $7E,1 ;SCI0 Control Register 3
SCI0C3_PEIE equ 0 ;Parity Error Interrupt Enable
SCI0C3_FEIE equ 1 ;Framing Error Interrupt Enable
SCI0C3_NEIE equ 2 ;Noise Error Interrupt Enable
SCI0C3_ORIE equ 3 ;Overrun Interrupt Enable
SCI0C3_TXINV equ 4 ;Transmit Data Inversion
SCI0C3_TXDIR equ 5 ;TxD Pin Direction in Single-Wire Mode
SCI0C3_T8 equ 6 ;Ninth Data Bit for Transmitter
SCI0C3_R8 equ 7 ;Ninth Data Bit for Receiver
SCI0D equ $7F,1 ;SCI0 Data Register
;-------------------------------------------------------------------------------
ADC1SC1A equ $80,1 ;Status and Control Register 1A
ADC1SC1A_DIFFA equ 5 ;Differential Mode Enable - DIFFA configures the ADC to operate in differential mode
ADC1SC1A_AIENA equ 6 ;Interrupt Enable - AIENA enables conversion complete interrupts. When COCOA becomes set while the respective AIENA
ADC1SC1A_COCOA equ 7 ;Conversion Complete Flag
ADC1SC1B equ $81,1 ;Status and Control Register 1B
ADC1SC1B_ADCHB0 equ 0 ;Input Channel Select Bit 0
ADC1SC1B_ADCHB1 equ 1 ;Input Channel Select Bit 1
ADC1SC1B_ADCHB2 equ 2 ;Input Channel Select Bit 2
ADC1SC1B_ADCHB3 equ 3 ;Input Channel Select Bit 3
ADC1SC1B_ADCHB4 equ 4 ;Input Channel Select Bit 4
ADC1SC1B_DIFFB equ 5 ;Differential Mode Enable - DIFFB configures the ADC to operate in differential mode
ADC1SC1B_AIENB equ 6 ;Interrupt Enable - AIENB enables conversion complete interrupts. When COCOB becomes set while the respective AIENB
ADC1SC1B_COCOB equ 7 ;Conversion Complete Flag
ADC1CFG1 equ $82,1 ;Configuration Register 1
ADC1CFG1_ADICLK0 equ 0 ;Input Clock Select Bit 0
ADC1CFG1_ADICLK1 equ 1 ;Input Clock Select Bit 1
ADC1CFG1_MODE0 equ 2 ;Conversion Mode Selection Bit 0
ADC1CFG1_MODE1 equ 3 ;Conversion Mode Selection Bit 1
ADC1CFG1_ADLSMP equ 4 ;Long Sample Time Configuration
ADC1CFG1_ADIV0 equ 5 ;Clock Divide Select Bit 0
ADC1CFG1_ADIV1 equ 6 ;Clock Divide Select Bit 1
ADC1CFG1_ADLPC equ 7 ;Low Power Configuration
ADC1CFG2 equ $83,1 ;Configuration Register 2
ADC1CFG2_ADLSTS0 equ 0 ;Long Sample Time Select Bit 0
ADC1CFG2_ADLSTS1 equ 1 ;Long Sample Time Select Bit 1
ADC1CFG2_ADHSC equ 2 ;High Speed Configuration
ADC1CFG2_ADACKEN equ 3 ;Asynchronous Clock Output Enable
ADC1RA equ $84,2 ;Data Result Register A
ADC1RHA equ $84,1 ;Data Result High Register A
ADC1RLA equ $85,1 ;Data Result Low Register A
ADC1RB equ $86,2 ;Data Result Register B
ADC1RHB equ $86,1 ;Data Result High Register B
ADC1RLB equ $87,1 ;Data Result Low Register B
;-------------------------------------------------------------------------------
SCI1BD equ $88,2 ;SCI1 Baud Rate Register
SCI1BDH equ $88,1 ;SCI1 Baud Rate Register High
SCI1BDL equ $89,1 ;SCI1 Baud Rate Register Low
SCI1C1 equ $8A,1 ;SCI1 Control Register 1
SCI1C1_PT equ 0 ;Parity Type
SCI1C1_PE equ 1 ;Parity Enable
SCI1C1_ILT equ 2 ;Idle Line Type Select
SCI1C1_WAKE equ 3 ;Receiver Wakeup Method Select
SCI1C1_M equ 4 ;9-Bit or 8-Bit Mode Select
SCI1C1_RSRC equ 5 ;Receiver Source Select
SCI1C1_SCISWAI equ 6 ;SCI Stops in Wait Mode
SCI1C1_LOOPS equ 7 ;Loop Mode Select
SCI1C2 equ $8B,1 ;SCI1 Control Register 2
SCI1C2_SBK equ 0 ;Send Break
SCI1C2_RWU equ 1 ;Receiver Wakeup Control
SCI1C2_RE equ 2 ;Receiver Enable
SCI1C2_TE equ 3 ;Transmitter Enable
SCI1C2_ILIE equ 4 ;Idle Line Interrupt Enable (for IDLE)
SCI1C2_RIE equ 5 ;Receiver Interrupt Enable (for RDRF)
SCI1C2_TCIE equ 6 ;Transmission Complete Interrupt Enable (for TC)
SCI1C2_TIE equ 7 ;Transmit Interrupt Enable (for TDRE)
SCI1S1 equ $8C,1 ;SCI1 Status Register 1
SCI1S1_PF equ 0 ;Parity Error Flag
SCI1S1_FE equ 1 ;Framing Error Flag
SCI1S1_NF equ 2 ;Noise Flag
SCI1S1_OR equ 3 ;Receiver Overrun Flag
SCI1S1_IDLE equ 4 ;Idle Line Flag
SCI1S1_RDRF equ 5 ;Receive Data Register Full Flag
SCI1S1_TC equ 6 ;Transmission Complete Flag
SCI1S1_TDRE equ 7 ;Transmit Data Register Empty Flag
SCI1S2 equ $8D,1 ;SCI1 Status Register 2
SCI1S2_RAF equ 0 ;Receiver Active Flag
SCI1S2_LBKDE equ 1 ;LIN Break Detection Enable
SCI1S2_BRK13 equ 2 ;Break Character Generation Length
SCI1S2_RWUID equ 3 ;Receive Wake Up Idle Detect
SCI1S2_RXINV equ 4 ;Receive Data Inversion
SCI1S2_RXEDGIF equ 6 ;RxD Pin Active Edge Interrupt Flag
SCI1S2_LBKDIF equ 7 ;LIN Break Detect Interrupt Flag
SCI1C3 equ $8E,1 ;SCI1 Control Register 3
SCI1C3_PEIE equ 0 ;Parity Error Interrupt Enable
SCI1C3_FEIE equ 1 ;Framing Error Interrupt Enable
SCI1C3_NEIE equ 2 ;Noise Error Interrupt Enable
SCI1C3_ORIE equ 3 ;Overrun Interrupt Enable
SCI1C3_TXINV equ 4 ;Transmit Data Inversion
SCI1C3_TXDIR equ 5 ;TxD Pin Direction in Single-Wire Mode
SCI1C3_T8 equ 6 ;Ninth Data Bit for Transmitter
SCI1C3_R8 equ 7 ;Ninth Data Bit for Receiver
SCI1D equ $8F,1 ;SCI1 Data Register
;-------------------------------------------------------------------------------
IICA1 equ $90,2 ;IIC Address Register
IICA equ $90,1 ;IIC Address Register
IICF equ $91,1 ;IIC Frequency Divider Register
IICF_ICR0 equ 0 ;IIC Clock Rate Bit 0
IICF_ICR1 equ 1 ;IIC Clock Rate Bit 1
IICF_ICR2 equ 2 ;IIC Clock Rate Bit 2
IICF_ICR3 equ 3 ;IIC Clock Rate Bit 3
IICF_ICR4 equ 4 ;IIC Clock Rate Bit 4
IICF_ICR5 equ 5 ;IIC Clock Rate Bit 5
IICF_MULT0 equ 6 ;Multiplier Factor Bit 0
IICF_MULT1 equ 7 ;Multiplier Factor Bit 1
IICC1 equ $92,1 ;IIC Control Register 1
IICC1_WUEN equ 1 ;Wake-up Enable
IICC1_RSTA equ 2 ;Repeat START
IICC1_TXAK equ 3 ;Transmit Acknowledge Enable
IICC1_TX equ 4 ;Transmit Mode Select
IICC1_MST equ 5 ;Master Mode Select
IICC1_IICIE equ 6 ;IIC Interrupt Enable
IICC1_IICEN equ 7 ;IIC Enable
IICC equ $92,1 ;IIC Control Register
IICC_WUEN equ 1 ;Wake-up Enable
IICC_RSTA equ 2 ;Repeat START
IICC_TXAK equ 3 ;Transmit Acknowledge Enable
IICC_TX equ 4 ;Transmit Mode Select
IICC_MST equ 5 ;Master Mode Select
IICC_IICIE equ 6 ;IIC Interrupt Enable
IICC_IICEN equ 7 ;IIC Enable
IICS equ $93,1 ;IIC Status Register
IICS_RXAK equ 0 ;Receive Acknowledge
IICS_IICIF equ 1 ;IIC Interrupt Flag
IICS_SRW equ 2 ;Slave Read/Write
IICS_ARBL equ 4 ;Arbitration Lost
IICS_BUSY equ 5 ;Bus Busy
IICS_IAAS equ 6 ;Addressed as a Slave
IICS_TCF equ 7 ;Transfer Complete Flag
IICD equ $94,1 ;IIC Data I/O Register
IICC2 equ $95,1 ;IIC Control Register 2
IICC2_AD8 equ 0 ;Slave Address Bit 8
IICC2_AD9 equ 1 ;Slave Address Bit 9
IICC2_AD10 equ 2 ;Slave Address Bit 10
IICC2_ADEXT equ 6 ;Address Extension
IICC2_GCAEN equ 7 ;General Call Address Enable
IICFLT equ $96,1 ;IIC Filter register
IICSMB equ $97,1 ;SMBus Control and Status Register
IICSMB_SHTF2IE equ 0 ;SHTF2 Interrupt Enable
IICSMB_SHTF2 equ 1 ;SCL High Timeout Flag 2
IICSMB_SHTF1 equ 2 ;SCL High Timeout Flag 1
IICSMB_SLTF equ 3 ;SCL Low Timeout Flag
IICSMB_TCKSEL equ 4 ;Time Out Counter Clock Select
IICSMB_SIICAEN equ 5 ;Second IIC Address Enable
IICSMB_ALERTEN equ 6 ;SMBus Alert Response Address Enable
IICSMB_FACK equ 7 ;Fast NACK/ACK enable
IICA2 equ $98,1 ;IIC Address Register 2
IICSLT equ $99,2 ;IIC SCL Low Time Out register
IICSLTH equ $99,1 ;IIC SCL Low Time Out register - High byte
IICSLTL equ $9A,1 ;IIC SCL Low Time Out register - Low byte
;-------------------------------------------------------------------------------
FTMSC equ $A0,1 ;FTM Status and Control Register
FTMCNT equ $A1,2 ;FTM Timer Counter Register
FTMCNTH equ $A1,1 ;FTM Timer Counter Register High
FTMCNTL equ $A2,1 ;FTM Timer Counter Register Low
FTMMOD equ $A3,2 ;FTM Timer Counter Modulo Register
FTMMODH equ $A3,1 ;FTM Timer Counter Modulo Register High
FTMMODL equ $A4,1 ;FTM Timer Counter Modulo Register Low
FTMC0SC equ $A5,1 ;FTM Timer Channel 0 Status and Control Register
FTMC0V equ $A6,2 ;FTM Timer Channel 0 Value Register
FTMC0VH equ $A6,1 ;FTM Timer Channel 0 Value Register High
FTMC0VL equ $A7,1 ;FTM Timer Channel 0 Value Register Low
FTMC1SC equ $A8,1 ;FTM Timer Channel 1 Status and Control Register
FTMC1V equ $A9,2 ;FTM Timer Channel 1 Value Register
FTMC1VH equ $A9,1 ;FTM Timer Channel 1 Value Register High
FTMC1VL equ $AA,1 ;FTM Timer Channel 1 Value Register Low
@bitnum PS0,0 ;Prescale Divisor Select Bit 0
@bitnum PS1,1 ;Prescale Divisor Select Bit 1
@bitnum PS2,2 ;Prescale Divisor Select Bit 2
@bitnum CLKSA,3 ;Clock Source Select A
@bitnum CLKSB,4 ;Clock Source Select B
@bitnum CPWMS,5 ;Center-Aligned PWM Select
@bitnum TOIE,6 ;Timer Overflow Interrupt Enable
@bitnum TOF,7 ;Timer Overflow Flag
@bitnum ELSxA,2 ;Edge/Level Select Bit A
@bitnum ELSxB,3 ;Edge/Level Select Bit B
@bitnum MSxA,4 ;Mode Select A for FTM Channel 1
@bitnum MSxB,5 ;Mode Select B for FTM Channel 1
@bitnum CHxIE,6 ;Channel 1 Interrupt Enable
@bitnum CHxF,7 ;Channel 1 Flag
;-------------------------------------------------------------------------------
CRCDH equ $B0,2 ;CRC Data High Register (Word)
CRCDH1 equ $B0,1 ;CRC Data High 1 (Upper Byte)
CRCDH0 equ $B1,1 ;CRC Data High 0 (Lower Byte)
CRCDL equ $B2,2 ;CRC Data Low Register (Word)
CRCDL1 equ $B2,1 ;CRC Data Low 1 (Upper Byte)
CRCDL0 equ $B3,1 ;CRC Data Low 0 (Lower Byte)
CRCPH equ $B4,2 ;CRC Polynomial High (Word)
CRCPH1 equ $B4,1 ;CRC Polynomial High Word Upper Byte
CRCPH0 equ $B5,1 ;CRC Polynomial High Word Lower Byte
CRCPL equ $B6,2 ;CRC Polynomial Low (Word)
CRCPL1 equ $B6,1 ;CRC Polynomial Low 1 (Upper Byte)
CRCPL0 equ $B7,1 ;CRC Polynomial Low 0 (Lower Byte)
CRCCTL equ $B8,1 ;CRC Control Register
@bitnum CRCCTL_CRCW,0 ;Width of CRC protocol
@bitnum CRCCTL_SEED,1 ;Write to the CRC Data Registers is a SEED
@bitnum CRCCTL_FXOR,2 ;Complement Read of CRCDH/L registers
@bitnum CRCCTL_TOTR0,4 ;Type of Transpose for Read bit 0, bit 0
@bitnum CRCCTL_TOTR1,5 ;Type of Transpose for Read bit 0, bit 1
@bitnum CRCCTL_TOTW0,6 ;Type of Transpose for Writes, bit 0, bit 0
@bitnum CRCCTL_TOTW1,7 ;Type of Transpose for Writes, bit 0, bit 1
;-------------------------------------------------------------------------------
LCDPEN0 equ $1080,1 ;LCD Pin Enable Register 0
LCDPEN1 equ $1081,1 ;LCD Pin Enable Register 1
LCDPEN2 equ $1082,1 ;LCD Pin Enable Register 2
LCDPEN3 equ $1083,1 ;LCD Pin Enable Register 3
LCDPEN4 equ $1084,1 ;LCD Pin Enable Register 4
LCDPEN5 equ $1085,1 ;LCD Pin Enable Register 5
LCDBPEN0 equ $1088,1 ;LCD Backplane Enable Register 0
LCDBPEN1 equ $1089,1 ;LCD Backplane Enable Register 1
LCDBPEN2 equ $108A,1 ;LCD Backplane Enable Register 2
LCDBPEN3 equ $108B,1 ;LCD Backplane Enable Register 3
LCDBPEN4 equ $108C,1 ;LCD Backplane Enable Register 4
LCDBPEN5 equ $108D,1 ;LCD Backplane Enable Register 5
LCDWF0 equ $1090,1 ;LCD Waveform Register 0
LCDWF1 equ $1091,1 ;LCD Waveform Register 1
LCDWF2 equ $1092,1 ;LCD Waveform Register 2
LCDWF3 equ $1093,1 ;LCD Waveform Register 3
LCDWF4 equ $1094,1 ;LCD Waveform Register 4
LCDWF5 equ $1095,1 ;LCD Waveform Register 5
LCDWF6 equ $1096,1 ;LCD Waveform Register 6
LCDWF7 equ $1097,1 ;LCD Waveform Register 7
LCDWF8 equ $1098,1 ;LCD Waveform Register 8
LCDWF9 equ $1099,1 ;LCD Waveform Register 9
LCDWF10 equ $109A,1 ;LCD Waveform Register 10
LCDWF11 equ $109B,1 ;LCD Waveform Register 11
LCDWF12 equ $109C,1 ;LCD Waveform Register 12
LCDWF13 equ $109D,1 ;LCD Waveform Register 13
LCDWF14 equ $109E,1 ;LCD Waveform Register 14
LCDWF15 equ $109F,1 ;LCD Waveform Register 15
LCDWF16 equ $10A0,1 ;LCD Waveform Register 16
LCDWF17 equ $10A1,1 ;LCD Waveform Register 17
LCDWF18 equ $10A2,1 ;LCD Waveform Register 18
LCDWF19 equ $10A3,1 ;LCD Waveform Register 19
LCDWF20 equ $10A4,1 ;LCD Waveform Register 20
LCDWF21 equ $10A5,1 ;LCD Waveform Register 21
LCDWF22 equ $10A6,1 ;LCD Waveform Register 22
LCDWF23 equ $10A7,1 ;LCD Waveform Register 23
LCDWF24 equ $10A8,1 ;LCD Waveform Register 24
LCDWF25 equ $10A9,1 ;LCD Waveform Register 25
LCDWF26 equ $10AA,1 ;LCD Waveform Register 26
LCDWF27 equ $10AB,1 ;LCD Waveform Register 27
LCDWF28 equ $10AC,1 ;LCD Waveform Register 28
LCDWF29 equ $10AD,1 ;LCD Waveform Register 29
LCDWF30 equ $10AE,1 ;LCD Waveform Register 30
LCDWF31 equ $10AF,1 ;LCD Waveform Register 31
LCDWF32 equ $10B0,1 ;LCD Waveform Register 32
LCDWF33 equ $10B1,1 ;LCD Waveform Register 33
LCDWF34 equ $10B2,1 ;LCD Waveform Register 34
LCDWF35 equ $10B3,1 ;LCD Waveform Register 35
LCDWF36 equ $10B4,1 ;LCD Waveform Register 36
LCDWF37 equ $10B5,1 ;LCD Waveform Register 37
LCDWF38 equ $10B6,1 ;LCD Waveform Register 38
LCDWF39 equ $10B7,1 ;LCD Waveform Register 39
LCDWF40 equ $10B8,1 ;LCD Waveform Register 40
LCDWF41 equ $10B9,1 ;LCD Waveform Register 41
LCDWF42 equ $10BA,1 ;LCD Waveform Register 42
LCDWF43 equ $10BB,1 ;LCD Waveform Register 43
;-------------------------------------------------------------------------------
SRS equ $1800,1 ;System Reset Status Register
@bitnum SRS_LVD,1 ;Low Voltage Detect
@bitnum SRS_ILAD,3 ;Illegal Address
@bitnum SRS_ILOP,4 ;Illegal Opcode
@bitnum SRS_COP,5 ;Computer Operating Properly (COP) Watchdog
@bitnum SRS_PIN,6 ;External Reset Pin
@bitnum SRS_POR,7 ;Power-On Reset
;-------------------------------------------------------------------------------
SBDFR equ $1801,1 ;System Background Debug Force Reset Register
@bitnum SBDFR_BDFR,0 ;Background Debug Force Reset
;-------------------------------------------------------------------------------
SOPT1 equ $1802,1 ;System Options Register 1
@bitnum COPW,0 ;COP Window Mode
@bitnum COPCLKS,1 ;COP Watchdog Clock Select
@bitnum COPT0,2 ;COP Watchdog Timeout, bit 0
@bitnum COPT1,3 ;COP Watchdog Timeout, bit 1
@bitnum STOPE,5 ;Stop Mode Enable
@bitnum BKGDPE,7 ;Unused
;-------------------------------------------------------------------------------
SDID equ $1805,2 ;System Device Identification Register
SDIDH equ $1805,1 ;System Device Identification Register High
SDIDL equ $1806,1 ;System Device Identification Register Low
;-------------------------------------------------------------------------------
SCGC1 equ $1808,1 ;System Clock Gating Control 1 Register
@bitnum SCG_SCI0,0 ;SCI0 Clock Gate Control
@bitnum SCG_SCI1,1 ;SCI1 Clock Gate Control
@bitnum SCG_SCI2,2 ;SCI2 Clock Gate Control
@bitnum SCG_SCI3,3 ;SCI3 Clock Gate Control
@bitnum SCG_IIC,4 ;IIC Clock Gate Control
@bitnum SCG_KBI,5 ;KBI Clock Gate Control
@bitnum SCG_ADC0,6 ;ADC0 Clock Gate Control
@bitnum SCG_ADC1,7 ;ADC1 Clock Gate Control
SCGC2 equ $1809,1 ;System Clock Gating Control 2 Register
@bitnum SCG_SPI0,0 ;SPI0 Clock Gate Control
@bitnum SCG_SPI1,1 ;SPI1 Clock Gate Control
@bitnum SCG_SPI2,2 ;SPI2 Clock Gate Control
@bitnum SCG_LCD,3 ;LCD Clock Gate Control
@bitnum SCG_IRQ,4 ;IRQ Clock Gate Control
@bitnum SCG_VREF,5 ;VREF Clock Gate Control
@bitnum SCG_CLKPRE,7 ;CLKPRE Clock Gate Control
SCGC3 equ $180A,1 ;System Clock Gating Control 3 Register
@bitnum SCG_PTA,0 ;PTA Clock Gate Control
@bitnum SCG_PTB,1 ;PTB Clock Gate Control
@bitnum SCG_PTC,2 ;PTC Clock Gate Control
@bitnum SCG_PTD,3 ;PTD Clock Gate Control
@bitnum SCG_PTE,4 ;PTE Clock Gate Control
@bitnum SCG_PTF,5 ;PTF Clock Gate Control
@bitnum SCG_PTG,6 ;PTG Clock Gate Control
@bitnum SCG_PTH,7 ;PTH Clock Gate Control
SCGC4 equ $180B,1 ;System Clock Gating Control 4 Register
@bitnum SCG_MTIM3,0 ;MTIM3 Clock Gate Control
@bitnum SCG_MTIM2,1 ;MTIM2 Clock Gate Control
@bitnum SCG_MTIM1,2 ;MTIM1 Clock Gate Control
@bitnum SCG_PDB,3 ;PDB Clock Gate Control
@bitnum SCG_FTM,4 ;FTM Clock Gate Control
@bitnum SCG_CRC,5 ;CRC Clock Gate Control
@bitnum SCG_MUXCTRL,6 ;MUXCTRL Clock Gate Control
SCGC5 equ $180C,1 ;System Clock Gating Control 5 Register
@bitnum SCG_FLS,0 ;FLS Clock Gate Control
@bitnum SCG_PCNT,2 ;PCNT Clock Gate Control
@bitnum SCG_IRTC,3 ;IRTC Clock Gate Control
@bitnum SCG_BKPT,4 ;BKPT Clock Gate Control
@bitnum SCG_PRACMP0,5 ;PRACMP0 Clock Gate Control
@bitnum SCG_PRACMP1,6 ;PRACMP1 Clock Gate Control
@bitnum SCG_PRACMP2,7 ;PRACMP2 Clock Gate Control
;-------------------------------------------------------------------------------
SIMIPS1 equ $180D,1 ;Internal Peripheral Select Register 1
SIMIPS2 equ $180E,1 ;Internal Peripheral Select Register 2
SIMIPS3 equ $180F,1 ;Internal Peripheral Select Register 3
SIMCO equ $1813,1 ;SIM Clock Options Register
@bitnum SIMIPS1_MTIM2CS,2 ;MTIM2 External Clock Select
@bitnum SIMIPS1_PCNTSS,3 ;PCNT Sensor Select
@bitnum SIMIPS1_MTIM3CS,5 ;MTIM3 External Clock Select
@bitnum SIMIPS1_FTMCS,6 ;FTM External Clock Select
@bitnum SIMIPS2_MODTX1,0 ;Modulate TxD1
@bitnum SIMIPS2_MTBASE1,2 ;SCI1 Tx Modulation Time Base Select
@bitnum SIMIPS2_RX1IN,5 ;SCI1 Rx Input Pin Select
@bitnum SIMIPS3_MODTX2,0 ;Modulate Tx2
@bitnum SIMIPS3_DDRIVE,1 ;Double Current Drive on TxD2 Enable
@bitnum SIMIPS3_MTBASE2,2 ;SCI2 Tx Modulation Time Base Select
@bitnum SIMIPS3_RX2IN,5 ;SCI2 Rx Input Pin Select
@bitnum SIMIPS3_PCNTFCS,6 ;PCNT Filter Clock Select
@bitnum SIMCO_CS,0 ;Clock Select for CLKOUT pin
;-------------------------------------------------------------------------------
CCSCTRL equ $1814,1 ;Clock Check and Select Control Register
@bitnum ICS_EXT_CLK_SEL,0 ;ICS External Clock Select
;-------------------------------------------------------------------------------
SPMSC1 equ $181C,1 ;System Power Management Status and Control 1 Register
@bitnum BGBE,0 ;Bandgap Buffer Enable
@bitnum BGBDS,1 ;Bandgap Buffer Drive Select
@bitnum LVDE,2 ;Low-Voltage Detect Enable
@bitnum LVDSE,3 ;Low-Voltage Detect Stop Enable
@bitnum LVDRE,4 ;Low-Voltage Detect Reset Enable
@bitnum LVDIE,5 ;Low-Voltage Detect Interrupt Enable
@bitnum LVDACK,6 ;Low-Voltage Detect Acknowledge
@bitnum LVDF,7 ;Low-Voltage Detect Flag
SPMSC2 equ $181D,1 ;System Power Management Status and Control 2 Register
@bitnum PPDC,0 ;Partial Power Down Control
@bitnum PPDE,1 ;Partial Power-Down Enable
@bitnum PPDACK,2 ;Partial Power Down Acknowledge
@bitnum PPDF,3 ;Partial Power Down Flag
@bitnum LPWUI,5 ;Low Power Wake Up on Interrupt
@bitnum LPRS,6 ;Low Power Regulator Status
@bitnum LPR,7 ;Low Power Regulator Control
SPMSC3 equ $181F,1 ;System Power Management Status and Control 3 Register
@bitnum LVWIE,3 ;Low-Voltage Warning Interrupt Enable
@bitnum LVWV,4 ;Low-Voltage Warning Voltage Select
@bitnum LVDV,5 ;Low-Voltage Detect Voltage Select
@bitnum LVWACK,6 ;Low-Voltage Warning Acknowledge
@bitnum LVWF,7 ;Low-Voltage Warning Flag
;-------------------------------------------------------------------------------
FCDIV equ $1820,1 ;FLASH Clock Divider Register
@bitnum FPRDIV8,6 ;Prescale (Divide) FLASH Clock by 8
@bitnum FDIVLD,7 ;Divisor Loaded Status Flag
FOPT equ $1821,1 ;Flash Options Register
@bitnum SEC0,0 ;Flash Security Bit 0
@bitnum SEC1,1 ;Flash Security Bit 1
@bitnum FNORED,6 ;Vector Redirection Disable
@bitnum KEYEN,7 ;Enable Security Key Writing
FCNFG equ $1823,1 ;Flash Configuration Register
FCNFG_KEYACC equ 5 ;Enable Security Key Writing
FPROT equ $1824,1 ;Flash Protection Register
@bitnum FPROT_FPDIS,0 ;Flash Protection Disable
FSTAT equ $1825,1 ;Flash Status Register
@bitnum FBLANK,2 ;FLASH Flag Indicating the Erase Verify Operation Status
@bitnum FACCERR,4 ;FLASH Access Error Flag
@bitnum FPVIOL,5 ;FLASH Protection Violation Flag
@bitnum FCCF,6 ;FLASH Command Complete Interrupt Flag
@bitnum FCBEF,7 ;FLASH Command Buffer Empty Flag
FCMD equ $1826,1 ;Flash Command Register
;-------------------------------------------------------------------------------
BKPTCA equ $1830,2 ;Breakpoint Comparator A Register(word access)
BKPTCAH equ $1830,1 ;Breakpoint Comparator A High Register
BKPTCAL equ $1831,1 ;Breakpoint Comparator A Low Register
BKPTCB equ $1832,2 ;Breakpoint Comparator B Register(word access)
BKPTCBH equ $1832,1 ;Breakpoint Comparator B High Register
BKPTCBL equ $1833,1 ;Breakpoint Comparator B Low Register
BKPTCC equ $1834,2 ;Breakpoint Comparator C Register(word access)
BKPTCCH equ $1834,1 ;Breakpoint Comparator C High Register
BKPTCCL equ $1835,1 ;Breakpoint Comparator C Low Register
BKPTAC equ $1836,1 ;Breakpoint Comparator A Control Register
@bitnum BKPTAC_FMDC,0 ;Full Mode Data Condition
@bitnum BKPTAC_FMEN,1 ;Full Mode Enable Bit
@bitnum BKPTAC_PAGESELA,3 ;Comparator A Page Select Bit
@bitnum BKPTAC_TAGA,4 ;Tag or Force Bit
@bitnum BKPTAC_RWA,5 ;Read/Write Comparator A Value Bit
@bitnum BKPTAC_RWAEN,6 ;Read/Write Comparator A Enable Bit
@bitnum BKPTAC_BKPTAEN,7 ;BKPT A Enable Bit
BKPTBC equ $1837,1 ;Breakpoint Comparator B Control Register
@bitnum BKPTBC_PAGESELB,3 ;Comparator B Page Select Bit
@bitnum BKPTBC_TAGB,4 ;Tag or Force Bit
@bitnum BKPTBC_RWB,5 ;Read/Write Comparator B Value Bit
@bitnum BKPTBC_RWBEN,6 ;Read/Write Comparator B Enable Bit
@bitnum BKPTBC_BKPTBEN,7 ;BKPT B Enable Bit
BKPTBCC equ $1838,1 ;Breakpoint Comparator C Control Register
@bitnum BKPTBCC_PAGESELC,3 ;Comparator C Page Select Bit
@bitnum BKPTBCC_TAGC,4 ;Tag or Force Bit
@bitnum BKPTBCC_RWC,5 ;Read/Write Comparator C Value Bit
@bitnum BKPTBCC_RWCEN,6 ;Read/Write Comparator C Enable Bit
@bitnum BKPTBCC_BKPTCEN,7 ;BKPT C Enable Bit
BKPTS equ $1839,1 ;Breakpoint Status Register
@bitnum BKPTS_CF,0 ;Comparator C Match Bit
@bitnum BKPTS_BF,1 ;Comparator B Match Bit
@bitnum BKPTS_AF,2 ;Comparator A Match Bit
;-------------------------------------------------------------------------------
ICSC1 equ $183C,1 ;ICS Control Register 1
@bitnum IREFSTEN,0 ;Internal Reference Stop Enable
@bitnum IRCLKEN,1 ;Internal Reference Clock Enable
@bitnum IREFS,2 ;Internal Reference Select
@bitnum RDIV0,3 ;Reference Divider, bit 0
@bitnum RDIV1,4 ;Reference Divider, bit 1
@bitnum RDIV2,5 ;Reference Divider, bit 2
@bitnum ICS_CLKS0,6 ;Clock Source Select, bit 0
@bitnum ICS_CLKS1,7 ;Clock Source Select, bit 1
ICSC2 equ $183D,1 ;ICS Control Register 2
@bitnum EREFSTEN,0 ;External Reference Stop Enable
@bitnum ERCLKEN,1 ;External Reference Enable
@bitnum EREFS,2 ;External Reference Select
@bitnum LP,3 ;Low Power Select
@bitnum HGO,4 ;High Gain Oscillator Select
@bitnum RANGE_SEL,5 ;Frequency Range Select
@bitnum BDIV0,6 ;Bus Frequency Divider, bit 0
@bitnum BDIV1,7 ;Bus Frequency Divider, bit 1
ICSTRM equ $183E,1 ;ICS Trim Register
ICSSC equ $183F,1 ;ICS Status and Control Register
ICSSC_FTRIM equ 0 ;ICS Fine Trim
ICSSC_OSCINIT equ 1 ;OSC Initialization
ICSSC_CLKST0 equ 2 ;Clock Mode Status, bit 0
ICSSC_CLKST1 equ 3 ;Clock Mode Status, bit 1
ICSSC_IREFST equ 4 ;Internal Reference Status
ICSSC_DMX32 equ 5 ;DCO Maximum frequency with 32.768 kHz reference
ICSSC_DRST_DRS0 equ 6 ;DCO Range Status/Range Select, bit 0
ICSSC_DRST_DRS1 equ 7 ;DCO Range Status/Range Select, bit 1
;-------------------------------------------------------------------------------
ADC0CV1 equ $1840,2 ;Compare Value 1 Register
ADC0CV1H equ $1840,1 ;Compare Value 1 High Register
ADC0CV1L equ $1841,1 ;Compare Value 1 Low Register
ADC0CV2 equ $1842,2 ;Compare Value 2 Register
ADC0CV2H equ $1842,1 ;Compare Value 2 High Register
ADC0CV2L equ $1843,1 ;Compare Value 2 Low Register
ADC0SC2 equ $1844,1 ;Status and Control Register 2
ADC0SC2_REFSEL0 equ 0 ;Voltage Reference Selection, bit 0
ADC0SC2_REFSEL1 equ 1 ;Voltage Reference Selection, bit 1
ADC0SC2_ACREN equ 3 ;Compare Function Range Enable
ADC0SC2_ACFGT equ 4 ;Compare Function Greater Than Enable
ADC0SC2_ACFE equ 5 ;Compare Function Enable - ACFE is used to enable the compare function
ADC0SC2_ADTRG equ 6 ;Conversion Trigger Select-ADTRG is used to select the type of trigger to be used for initiating
ADC0SC2_ADACT equ 7 ;Conversion Active - ADACT indicates that a conversion is in progress. ADACT is set when a
ADC0SC3 equ $1845,1 ;Status and Control Register 3
ADC0SC3_AVGS0 equ 0 ;Hardware Average select, bit 0
ADC0SC3_AVGS1 equ 1 ;Hardware Average select, bit 1
ADC0SC3_AVGE equ 2 ;Hardware average enable - AVGE enables the hardware average function of the ADC
ADC0SC3_ADCO equ 3 ;Continuous Conversion Enable - ADCO enables continuous conversions
ADC0SC3_CALF equ 6 ;Calibration Failed Flag - CALF displays the result of the calibration sequence
ADC0SC3_CAL equ 7 ;Calibration - CAL begins the calibration sequence when set
ADC0OFS equ $1846,2 ;Offset Correction Register
ADC0OFSH equ $1846,1 ;Offset Correction High Register
ADC0OFSL equ $1847,1 ;Offset Correction Low Register
ADC0PG equ $1848,2 ;Plus-Side Gain Register
ADC0PGH equ $1848,1 ;Plus-Side Gain High Register
ADC0PGL equ $1849,1 ;Plus-Side Gain Low Register
ADC0MG equ $184A,2 ;Minus-Side Gain Register