Advice needed on how to test circuit board bypass capacitor placement #119
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Hi, since openEMS is general FDTD solver for electromagnetics you can use it to investigate for trace coupling. I'm not expert but was thinking about this example, so I can assist you, since you will be working with little more complex 3D structures as they are PCB traces of existing circuit. So ideal and fast workflow is as following: It's not that hard, if your schematic is not secret you can post it here and I can look at that and try it if it will give you expected results. This is great example and I hoped that in future somebody will try this. |
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First of all, please excuse that I am very much a beginner so I probably don't know how to even phrase my problem properly.
I have two circuit boards that implement the same netlist. I have authored these in KiCad, so I am able to export a HyperLynx file for each of them. The boards differ in the bypass capacitor placements. I would like to quantify which placement is "better" and by how much and/or evaluate whether the worse placement would likely still "work".
My first question is whether OpenEMS is even the right tool to do this.
Assuming yes to that, how do I set up the problem for OpenEMS? On the board I have two communicating chips, let's say it's an FPGA and a DDR3L memory.
I think what I need to do is create a signal on one trace loop and measure how much of it is coupled onto an adjacent trace loop, with the expectation that a tighter bypass results in less coupling. Proceeding with that assumption, how do I tell OpenEMS that an output pin on a component is a driver that interacts with the nearest ground and power pins?
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