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Add Soundwire support for AMD platform ACP_7_0. #9836

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merged 2 commits into from
Feb 18, 2025
Merged

Add Soundwire support for AMD platform ACP_7_0. #9836

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2764210
amd : ACP_7_0 : Add SW support for the platform ACP_7_0.
saisurya-ch Jan 2, 2025
0feb83a
amd : ACP_7_0 : Add SW topology for the platform ACP_7_0.
saisurya-ch Feb 17, 2025
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78 changes: 65 additions & 13 deletions src/drivers/amd/rembrandt/acp_sw_audio_dma.c
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Original file line number Diff line number Diff line change
Expand Up @@ -12,12 +12,18 @@
#include <sof/lib/uuid.h>
#include <sof/trace/trace.h>

#ifdef CONFIG_ACP_6_3
#if defined(CONFIG_ACP_6_3) || defined(CONFIG_ACP_7_0)

SOF_DEFINE_REG_UUID(acp_sw_audio);

DECLARE_TR_CTX(acp_sw_audio_tr, SOF_UUID(acp_sw_audio_uuid), LOG_LEVEL_INFO);

#if defined(CONFIG_ACP_6_3)
#define DMA_CH_COUNT 8
#elif defined(CONFIG_ACP_7_0)
#define DMA_CH_COUNT 12
#endif

//initialization of soundwire-0 fifos(Audio, BT and HS)
#define SW0_AUDIO_FIFO_SIZE 128
#define SW0_AUDIO_TX_FIFO_ADDR 0
Expand All @@ -31,10 +37,18 @@ DECLARE_TR_CTX(acp_sw_audio_tr, SOF_UUID(acp_sw_audio_uuid), LOG_LEVEL_INFO);
#define SW0_HS_TX_FIFO_ADDR (SW0_BT_RX_FIFO_ADDR + SW0_BT_FIFO_SIZE)
#define SW0_HS_RX_FIFO_ADDR (SW0_HS_TX_FIFO_ADDR + SW0_HS_FIFO_SIZE)

//initialization of soundwire-1 fifo
#define SW1_FIFO_SIZE 128
#define SW1_TX_FIFO_ADDR (SW0_HS_RX_FIFO_ADDR + SW1_FIFO_SIZE)
#define SW1_RX_FIFO_ADDR (SW1_TX_FIFO_ADDR + SW1_FIFO_SIZE)
//initialization of soundwire-1 fifos(Audio, BT and HS)
#define SW1_AUDIO_FIFO_SIZE 128
#define SW1_AUDIO_TX_FIFO_ADDR (SW0_HS_RX_FIFO_ADDR + SW0_HS_FIFO_SIZE)
#define SW1_AUDIO_RX_FIFO_ADDR (SW1_AUDIO_TX_FIFO_ADDR + SW1_AUDIO_FIFO_SIZE)

#define SW1_BT_FIFO_SIZE 128
#define SW1_BT_TX_FIFO_ADDR (SW1_AUDIO_RX_FIFO_ADDR + SW1_AUDIO_FIFO_SIZE)
#define SW1_BT_RX_FIFO_ADDR (SW1_BT_TX_FIFO_ADDR + SW1_BT_FIFO_SIZE)

#define SW1_HS_FIFO_SIZE 128
#define SW1_HS_TX_FIFO_ADDR (SW1_BT_RX_FIFO_ADDR + SW1_BT_FIFO_SIZE)
#define SW1_HS_RX_FIFO_ADDR (SW1_HS_TX_FIFO_ADDR + SW1_HS_FIFO_SIZE)

static uint32_t sw_audio_buff_size_playback;
static uint32_t sw_audio_buff_size_capture;
Expand All @@ -55,7 +69,7 @@ struct sw_dev_register {
uint32_t statusindex;
};

static struct sw_dev_register sw_dev[8] = {
static struct sw_dev_register sw_dev[DMA_CH_COUNT] = {
{ACP_SW_HS_RX_EN, ACP_SW_HS_RX_EN_STATUS, ACP_HS_RX_FIFOADDR, SW0_HS_RX_FIFO_ADDR,
ACP_HS_RX_FIFOSIZE, SW0_HS_FIFO_SIZE, ACP_HS_RX_RINGBUFADDR, ACP_HS_RX_RINGBUFSIZE,
ACP_HS_RX_DMA_SIZE, ACP_HS_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_INTR_CNTL, 0},
Expand All @@ -64,13 +78,13 @@ ACP_HS_RX_DMA_SIZE, ACP_HS_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_
ACP_HS_TX_FIFOSIZE, SW0_HS_FIFO_SIZE, ACP_HS_TX_RINGBUFADDR, ACP_HS_TX_RINGBUFSIZE,
ACP_HS_TX_DMA_SIZE, ACP_HS_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_INTR_CNTL, 1},

{ACP_P1_SW_BT_RX_EN, ACP_P1_SW_BT_RX_EN_STATUS, ACP_P1_BT_RX_FIFOADDR, SW1_RX_FIFO_ADDR,
ACP_P1_BT_RX_FIFOSIZE, SW1_FIFO_SIZE, ACP_P1_BT_RX_RINGBUFADDR, ACP_P1_BT_RX_RINGBUFSIZE,
{ACP_P1_SW_BT_RX_EN, ACP_P1_SW_BT_RX_EN_STATUS, ACP_P1_BT_RX_FIFOADDR, SW1_BT_RX_FIFO_ADDR,
ACP_P1_BT_RX_FIFOSIZE, SW1_BT_FIFO_SIZE, ACP_P1_BT_RX_RINGBUFADDR, ACP_P1_BT_RX_RINGBUFSIZE,
ACP_P1_BT_RX_DMA_SIZE, ACP_P1_BT_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1,
2},

{ACP_P1_SW_BT_TX_EN, ACP_P1_SW_BT_TX_EN_STATUS, ACP_P1_BT_TX_FIFOADDR, SW1_TX_FIFO_ADDR,
ACP_P1_BT_TX_FIFOSIZE, SW1_FIFO_SIZE, ACP_P1_BT_TX_RINGBUFADDR, ACP_P1_BT_TX_RINGBUFSIZE,
{ACP_P1_SW_BT_TX_EN, ACP_P1_SW_BT_TX_EN_STATUS, ACP_P1_BT_TX_FIFOADDR, SW1_BT_TX_FIFO_ADDR,
ACP_P1_BT_TX_FIFOSIZE, SW1_BT_FIFO_SIZE, ACP_P1_BT_TX_RINGBUFADDR, ACP_P1_BT_TX_RINGBUFSIZE,
ACP_P1_BT_TX_DMA_SIZE, ACP_P1_BT_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1,
3},

Expand All @@ -88,7 +102,29 @@ ACP_BT_RX_DMA_SIZE, ACP_BT_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_

{ACP_SW_BT_TX_EN, ACP_SW_BT_TX_EN_STATUS, ACP_BT_TX_FIFOADDR, SW0_BT_TX_FIFO_ADDR,
ACP_BT_TX_FIFOSIZE, SW0_BT_FIFO_SIZE, ACP_BT_TX_RINGBUFADDR, ACP_BT_TX_RINGBUFSIZE,
ACP_BT_TX_DMA_SIZE, ACP_BT_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_INTR_CNTL, 3}
ACP_BT_TX_DMA_SIZE, ACP_BT_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_INTR_CNTL, 3},

#if defined(CONFIG_ACP_7_0)
{ACP_P1_SW_AUDIO_RX_EN, ACP_P1_SW_AUDIO_RX_EN_STATUS, ACP_P1_AUDIO_RX_FIFOADDR,
SW1_AUDIO_RX_FIFO_ADDR, ACP_P1_AUDIO_RX_FIFOSIZE, SW1_AUDIO_FIFO_SIZE,
ACP_P1_AUDIO_RX_RINGBUFADDR, ACP_P1_AUDIO_RX_RINGBUFSIZE, ACP_P1_AUDIO_RX_DMA_SIZE,
ACP_P1_AUDIO_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1, 4},

{ACP_P1_SW_AUDIO_TX_EN, ACP_P1_SW_AUDIO_TX_EN_STATUS, ACP_P1_AUDIO_TX_FIFOADDR,
SW1_AUDIO_TX_FIFO_ADDR, ACP_P1_AUDIO_TX_FIFOSIZE, SW1_AUDIO_FIFO_SIZE,
ACP_P1_AUDIO_TX_RINGBUFADDR, ACP_P1_AUDIO_TX_RINGBUFSIZE, ACP_P1_AUDIO_TX_DMA_SIZE,
ACP_P1_AUDIO_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1, 5},

{ACP_P1_SW_HEADSET_RX_EN, ACP_P1_SW_HEADSET_RX_EN_STATUS, ACP_P1_HS_RX_FIFOADDR,
SW1_HS_RX_FIFO_ADDR, ACP_P1_HS_RX_FIFOSIZE, SW1_HS_FIFO_SIZE,
ACP_P1_HS_RX_RINGBUFADDR, ACP_P1_HS_RX_RINGBUFSIZE, ACP_P1_HS_RX_DMA_SIZE,
ACP_P1_HS_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1, 0},

{ACP_P1_SW_HEADSET_TX_EN, ACP_P1_SW_HEADSET_TX_EN_STATUS, ACP_P1_HS_TX_FIFOADDR,
SW1_HS_TX_FIFO_ADDR, ACP_P1_HS_TX_FIFOSIZE, SW1_HS_FIFO_SIZE,
ACP_P1_HS_TX_RINGBUFADDR, ACP_P1_HS_TX_RINGBUFSIZE, ACP_P1_HS_TX_DMA_SIZE,
ACP_P1_HS_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1, 1},
#endif
};

/* allocate next free DMA channel */
Expand Down Expand Up @@ -136,7 +172,7 @@ static int acp_dai_sw_audio_dma_start(struct dma_chan_data *channel)
uint32_t acp_pdm_en;
int i;

for (i = 0; i < 8; i += 2) {
for (i = 0; i < DMA_CH_COUNT; i += 2) {
sw0_audio_tx_en |= io_reg_read(PU_REGISTER_BASE + sw_dev[i].sw_dev_en);
sw0_audio_rx_en |= io_reg_read(PU_REGISTER_BASE + sw_dev[i + 1].sw_dev_en);
}
Expand Down Expand Up @@ -208,7 +244,7 @@ static int acp_dai_sw_audio_dma_stop(struct dma_chan_data *channel)
return -EINVAL;
}

for (i = 0; i < 8; i += 2) {
for (i = 0; i < DMA_CH_COUNT; i += 2) {
sw0_audio_tx_en |= io_reg_read(PU_REGISTER_BASE + sw_dev[i].sw_dev_en);
sw0_audio_rx_en |= io_reg_read(PU_REGISTER_BASE + sw_dev[i + 1].sw_dev_en);
}
Expand Down Expand Up @@ -420,6 +456,10 @@ static int acp_dai_sw_audio_dma_interrupt(struct dma_chan_data *channel, enum dm
switch (channel->index) {
case SDW1_ACP_P1_SW_BT_TX_EN_CH:
case SDW1_ACP_P1_SW_BT_RX_EN_CH:
case SDW1_ACP_P1_SW_AUDIO_RX_EN_CH:
case SDW1_ACP_P1_SW_AUDIO_TX_EN_CH:
case SDW1_ACP_P1_SW_HS_RX_EN_CH:
case SDW1_ACP_P1_SW_HS_TX_EN_CH:
acp_intr_stat1 = (acp_dsp0_intr_stat1_t)dma_reg_read(channel->dma,
sw_dev[channel->index].sw_dev_dma_intr_status);
status = acp_intr_stat1.bits.audio_buffer_int_stat;
Expand All @@ -435,6 +475,10 @@ static int acp_dai_sw_audio_dma_interrupt(struct dma_chan_data *channel, enum dm
switch (channel->index) {
case SDW1_ACP_P1_SW_BT_TX_EN_CH:
case SDW1_ACP_P1_SW_BT_RX_EN_CH:
case SDW1_ACP_P1_SW_AUDIO_RX_EN_CH:
case SDW1_ACP_P1_SW_AUDIO_TX_EN_CH:
case SDW1_ACP_P1_SW_HS_RX_EN_CH:
case SDW1_ACP_P1_SW_HS_TX_EN_CH:
acp_intr_stat1.u32all = 0;
acp_intr_stat1.bits.audio_buffer_int_stat =
(1 << sw_dev[channel->index].statusindex);
Expand All @@ -456,6 +500,10 @@ static int acp_dai_sw_audio_dma_interrupt(struct dma_chan_data *channel, enum dm
switch (channel->index) {
case SDW1_ACP_P1_SW_BT_TX_EN_CH:
case SDW1_ACP_P1_SW_BT_RX_EN_CH:
case SDW1_ACP_P1_SW_AUDIO_RX_EN_CH:
case SDW1_ACP_P1_SW_AUDIO_TX_EN_CH:
case SDW1_ACP_P1_SW_HS_RX_EN_CH:
case SDW1_ACP_P1_SW_HS_TX_EN_CH:
acp_intr_cntl1 = (acp_dsp0_intr_cntl1_t)dma_reg_read(channel->dma,
sw_dev[channel->index].sw_dev_dma_intr_cntl);
acp_intr_cntl1.bits.audio_buffer_int_mask &=
Expand All @@ -479,6 +527,10 @@ static int acp_dai_sw_audio_dma_interrupt(struct dma_chan_data *channel, enum dm
switch (channel->index) {
case SDW1_ACP_P1_SW_BT_TX_EN_CH:
case SDW1_ACP_P1_SW_BT_RX_EN_CH:
case SDW1_ACP_P1_SW_AUDIO_RX_EN_CH:
case SDW1_ACP_P1_SW_AUDIO_TX_EN_CH:
case SDW1_ACP_P1_SW_HS_RX_EN_CH:
case SDW1_ACP_P1_SW_HS_TX_EN_CH:
acp_intr_cntl1 = (acp_dsp0_intr_cntl1_t)dma_reg_read(channel->dma,
sw_dev[channel->index].sw_dev_dma_intr_cntl);
acp_intr_cntl1.bits.audio_buffer_int_mask |=
Expand Down
48 changes: 48 additions & 0 deletions src/platform/amd/acp_7_0/include/platform/chip_offset_byte.h
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Original file line number Diff line number Diff line change
Expand Up @@ -136,6 +136,21 @@
#define ACP_WOV_MISC_CTRL 0x1242C5C
#define ACP_WOV_CLK_CTRL 0x1242C60

#define ACP_SW_EN 0x1243000
#define ACP_SW_EN_STATUS 0x1243004
#define ACP_SW_AUDIO_TX_EN 0x1243010
#define ACP_SW_AUDIO_TX_EN_STATUS 0x1243014
#define ACP_SW_BT_TX_EN 0x1243050
#define ACP_SW_BT_TX_EN_STATUS 0x1243054
#define ACP_SW_HS_TX_EN 0x124306C
#define ACP_SW_HS_TX_EN_STATUS 0x1243070
#define ACP_SW_AUDIO_RX_EN 0x1243088
#define ACP_SW_AUDIO_RX_EN_STATUS 0x124308C
#define ACP_SW_BT_RX_EN 0x1243128
#define ACP_SW_BT_RX_EN_STATUS 0x124312C
#define ACP_SW_HS_RX_EN 0x1243144
#define ACP_SW_HS_RX_EN_STATUS 0x1243148

/* Registers from ACP_P1_AUDIO_BUFFERS block */
#define ACP_P1_I2S_RX_RINGBUFADDR 0x1243A00
#define ACP_P1_I2S_RX_RINGBUFSIZE 0x1243A04
Expand All @@ -153,6 +168,24 @@
#define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x1243A3C
#define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW 0x1243A40
#define ACP_P1_I2S_TX_INTR_WATERMARK_SIZE 0x1243A44

#define ACP_P1_AUDIO_RX_RINGBUFADDR 0x1243A00
#define ACP_P1_AUDIO_RX_RINGBUFSIZE 0x1243A04
#define ACP_P1_AUDIO_RX_FIFOADDR 0x1243A0C
#define ACP_P1_AUDIO_RX_FIFOSIZE 0x1243A10
#define ACP_P1_AUDIO_RX_DMA_SIZE 0x1243A14
#define ACP_P1_AUDIO_RX_LINEARPOSITIONCNTR_HIGH 0x1243A18
#define ACP_P1_AUDIO_RX_LINEARPOSITIONCNTR_LOW 0x1243A1C
#define ACP_P1_AUDIO_RX_INTR_WATERMARK_SIZE 0x1243A20
#define ACP_P1_AUDIO_TX_RINGBUFADDR 0x1243A24
#define ACP_P1_AUDIO_TX_RINGBUFSIZE 0x1243A28
#define ACP_P1_AUDIO_TX_FIFOADDR 0x1243A30
#define ACP_P1_AUDIO_TX_FIFOSIZE 0x1243A34
#define ACP_P1_AUDIO_TX_DMA_SIZE 0x1243A38
#define ACP_P1_AUDIO_TX_LINEARPOSITIONCNTR_HIGH 0x1243A3C
#define ACP_P1_AUDIO_TX_LINEARPOSITIONCNTR_LOW 0x1243A40
#define ACP_P1_AUDIO_TX_INTR_WATERMARK_SIZE 0x1243A44

#define ACP_P1_BT_RX_RINGBUFADDR 0x1243A48
#define ACP_P1_BT_RX_RINGBUFSIZE 0x1243A4C
#define ACP_P1_BT_RX_FIFOADDR 0x1243A54
Expand Down Expand Up @@ -186,6 +219,21 @@
#define ACP_P1_HS_TX_LINEARPOSITIONCNTR_LOW 0x1243AD0
#define ACP_P1_HS_TX_INTR_WATERMARK_SIZE 0x1243AD4

#define ACP_P1_SW_AUDIO_TX_EN 0x1243C10
#define ACP_P1_SW_AUDIO_TX_EN_STATUS 0x1243C14
#define ACP_P1_SW_AUDIO_RX_EN 0x1243C88
#define ACP_P1_SW_AUDIO_RX_EN_STATUS 0x1243C8C

#define ACP_P1_SW_BT_TX_EN 0x1243C50
#define ACP_P1_SW_BT_TX_EN_STATUS 0x1243C54
#define ACP_P1_SW_BT_RX_EN 0x1243D28
#define ACP_P1_SW_BT_RX_EN_STATUS 0x1243D2C

#define ACP_P1_SW_HEADSET_TX_EN 0x1243C6C
#define ACP_P1_SW_HEADSET_TX_EN_STATUS 0x1243C70
#define ACP_P1_SW_HEADSET_RX_EN 0x1243D44
#define ACP_P1_SW_HEADSET_RX_EN_STATUS 0x1243D48

#define MP1_SMN_C2PMSG_69 0x58A14
#define MP1_SMN_C2PMSG_85 0x58A54
#define MP1_SMN_C2PMSG_93 0x58A74
Expand Down
12 changes: 11 additions & 1 deletion src/platform/amd/acp_7_0/include/platform/lib/memory.h
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Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,7 @@
#define DRAM1_BASE 0xE0010000
#define DRAM1_SIZE 0x10000
#define SRAM1_BASE 0x6000C000
#define SRAM1_SIZE 0x27A000
#define SRAM1_SIZE 0x274000

#define DMA0_BASE PU_REGISTER_BASE
#define DMA0_SIZE 0x4
Expand All @@ -35,12 +35,22 @@
#define DAI_BASE (PU_REGISTER_BASE + ACP_I2S_RX_RINGBUFADDR)
#define DAI_BASE_REM (PU_REGISTER_BASE + ACP_P1_I2S_RX_RINGBUFADDR)
#define DAI_SIZE 0x4

#define SW1_AUDIO_TX_FIFO_OFFST (ACP_P1_AUDIO_TX_FIFOADDR - ACP_P1_AUDIO_RX_RINGBUFADDR)
#define SW1_AUDIO_RX_FIFO_OFFST (ACP_P1_AUDIO_RX_FIFOADDR - ACP_P1_AUDIO_RX_RINGBUFADDR)

#define BT_TX_FIFO_OFFST (ACP_P1_BT_TX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR)
#define BT_RX_FIFO_OFFST (ACP_P1_BT_RX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR)

#define SW1_HS_TX_FIFO_OFFST (ACP_P1_HS_TX_FIFOADDR - ACP_P1_HS_RX_RINGBUFADDR)
#define SW1_HS_RX_FIFO_OFFST (ACP_P1_HS_RX_FIFOADDR - ACP_P1_HS_RX_RINGBUFADDR)

#define HS_TX_FIFO_OFFST (ACP_P1_HS_TX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR)
#define HS_RX_FIFO_OFFST (ACP_P1_HS_TX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR)

#define SW0_AUDIO_TX_FIFO_OFFST (ACP_AUDIO_TX_FIFOADDR - ACP_AUDIO_RX_RINGBUFADDR)
#define SW0_AUDIO_RX_FIFO_OFFST (ACP_AUDIO_RX_FIFOADDR - ACP_AUDIO_RX_RINGBUFADDR)

#define BT0_TX_FIFO_OFFST (ACP_BT_TX_FIFOADDR - ACP_AUDIO_RX_RINGBUFADDR)
#define BT0_RX_FIFO_OFFST (ACP_BT_RX_FIFOADDR - ACP_AUDIO_RX_RINGBUFADDR)

Expand Down
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