From 27642104d268eb27dee913d182c673881f5d9888 Mon Sep 17 00:00:00 2001 From: SaiSurya Ch Date: Thu, 2 Jan 2025 14:59:56 +0530 Subject: [PATCH 1/2] amd : ACP_7_0 : Add SW support for the platform ACP_7_0. amd : ACP_7_0 : Add SW support for the platform ACP_7_0. Signed-off-by: SaiSurya Ch --- src/drivers/amd/rembrandt/acp_sw_audio_dma.c | 78 ++++++++-- .../include/platform/chip_offset_byte.h | 48 ++++++ .../amd/acp_7_0/include/platform/lib/memory.h | 12 +- src/platform/amd/acp_7_0/lib/dai.c | 142 ++++++++++++++++++ src/platform/amd/acp_7_0/lib/dma.c | 15 ++ .../amd/common/include/platform/lib/dai.h | 9 +- .../amd/common/include/platform/lib/dma.h | 2 +- tools/rimage/config/acp_7_0.toml | 2 +- 8 files changed, 291 insertions(+), 17 deletions(-) diff --git a/src/drivers/amd/rembrandt/acp_sw_audio_dma.c b/src/drivers/amd/rembrandt/acp_sw_audio_dma.c index a2a20f6aa820..07c7b0d703c3 100644 --- a/src/drivers/amd/rembrandt/acp_sw_audio_dma.c +++ b/src/drivers/amd/rembrandt/acp_sw_audio_dma.c @@ -12,12 +12,18 @@ #include #include -#ifdef CONFIG_ACP_6_3 +#if defined(CONFIG_ACP_6_3) || defined(CONFIG_ACP_7_0) SOF_DEFINE_REG_UUID(acp_sw_audio); DECLARE_TR_CTX(acp_sw_audio_tr, SOF_UUID(acp_sw_audio_uuid), LOG_LEVEL_INFO); +#if defined(CONFIG_ACP_6_3) +#define DMA_CH_COUNT 8 +#elif defined(CONFIG_ACP_7_0) +#define DMA_CH_COUNT 12 +#endif + //initialization of soundwire-0 fifos(Audio, BT and HS) #define SW0_AUDIO_FIFO_SIZE 128 #define SW0_AUDIO_TX_FIFO_ADDR 0 @@ -31,10 +37,18 @@ DECLARE_TR_CTX(acp_sw_audio_tr, SOF_UUID(acp_sw_audio_uuid), LOG_LEVEL_INFO); #define SW0_HS_TX_FIFO_ADDR (SW0_BT_RX_FIFO_ADDR + SW0_BT_FIFO_SIZE) #define SW0_HS_RX_FIFO_ADDR (SW0_HS_TX_FIFO_ADDR + SW0_HS_FIFO_SIZE) -//initialization of soundwire-1 fifo -#define SW1_FIFO_SIZE 128 -#define SW1_TX_FIFO_ADDR (SW0_HS_RX_FIFO_ADDR + SW1_FIFO_SIZE) -#define SW1_RX_FIFO_ADDR (SW1_TX_FIFO_ADDR + SW1_FIFO_SIZE) +//initialization of soundwire-1 fifos(Audio, BT and HS) +#define SW1_AUDIO_FIFO_SIZE 128 +#define SW1_AUDIO_TX_FIFO_ADDR (SW0_HS_RX_FIFO_ADDR + SW0_HS_FIFO_SIZE) +#define SW1_AUDIO_RX_FIFO_ADDR (SW1_AUDIO_TX_FIFO_ADDR + SW1_AUDIO_FIFO_SIZE) + +#define SW1_BT_FIFO_SIZE 128 +#define SW1_BT_TX_FIFO_ADDR (SW1_AUDIO_RX_FIFO_ADDR + SW1_AUDIO_FIFO_SIZE) +#define SW1_BT_RX_FIFO_ADDR (SW1_BT_TX_FIFO_ADDR + SW1_BT_FIFO_SIZE) + +#define SW1_HS_FIFO_SIZE 128 +#define SW1_HS_TX_FIFO_ADDR (SW1_BT_RX_FIFO_ADDR + SW1_BT_FIFO_SIZE) +#define SW1_HS_RX_FIFO_ADDR (SW1_HS_TX_FIFO_ADDR + SW1_HS_FIFO_SIZE) static uint32_t sw_audio_buff_size_playback; static uint32_t sw_audio_buff_size_capture; @@ -55,7 +69,7 @@ struct sw_dev_register { uint32_t statusindex; }; -static struct sw_dev_register sw_dev[8] = { +static struct sw_dev_register sw_dev[DMA_CH_COUNT] = { {ACP_SW_HS_RX_EN, ACP_SW_HS_RX_EN_STATUS, ACP_HS_RX_FIFOADDR, SW0_HS_RX_FIFO_ADDR, ACP_HS_RX_FIFOSIZE, SW0_HS_FIFO_SIZE, ACP_HS_RX_RINGBUFADDR, ACP_HS_RX_RINGBUFSIZE, ACP_HS_RX_DMA_SIZE, ACP_HS_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_INTR_CNTL, 0}, @@ -64,13 +78,13 @@ ACP_HS_RX_DMA_SIZE, ACP_HS_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_ ACP_HS_TX_FIFOSIZE, SW0_HS_FIFO_SIZE, ACP_HS_TX_RINGBUFADDR, ACP_HS_TX_RINGBUFSIZE, ACP_HS_TX_DMA_SIZE, ACP_HS_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_INTR_CNTL, 1}, -{ACP_P1_SW_BT_RX_EN, ACP_P1_SW_BT_RX_EN_STATUS, ACP_P1_BT_RX_FIFOADDR, SW1_RX_FIFO_ADDR, -ACP_P1_BT_RX_FIFOSIZE, SW1_FIFO_SIZE, ACP_P1_BT_RX_RINGBUFADDR, ACP_P1_BT_RX_RINGBUFSIZE, +{ACP_P1_SW_BT_RX_EN, ACP_P1_SW_BT_RX_EN_STATUS, ACP_P1_BT_RX_FIFOADDR, SW1_BT_RX_FIFO_ADDR, +ACP_P1_BT_RX_FIFOSIZE, SW1_BT_FIFO_SIZE, ACP_P1_BT_RX_RINGBUFADDR, ACP_P1_BT_RX_RINGBUFSIZE, ACP_P1_BT_RX_DMA_SIZE, ACP_P1_BT_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1, 2}, -{ACP_P1_SW_BT_TX_EN, ACP_P1_SW_BT_TX_EN_STATUS, ACP_P1_BT_TX_FIFOADDR, SW1_TX_FIFO_ADDR, -ACP_P1_BT_TX_FIFOSIZE, SW1_FIFO_SIZE, ACP_P1_BT_TX_RINGBUFADDR, ACP_P1_BT_TX_RINGBUFSIZE, +{ACP_P1_SW_BT_TX_EN, ACP_P1_SW_BT_TX_EN_STATUS, ACP_P1_BT_TX_FIFOADDR, SW1_BT_TX_FIFO_ADDR, +ACP_P1_BT_TX_FIFOSIZE, SW1_BT_FIFO_SIZE, ACP_P1_BT_TX_RINGBUFADDR, ACP_P1_BT_TX_RINGBUFSIZE, ACP_P1_BT_TX_DMA_SIZE, ACP_P1_BT_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1, 3}, @@ -88,7 +102,29 @@ ACP_BT_RX_DMA_SIZE, ACP_BT_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_ {ACP_SW_BT_TX_EN, ACP_SW_BT_TX_EN_STATUS, ACP_BT_TX_FIFOADDR, SW0_BT_TX_FIFO_ADDR, ACP_BT_TX_FIFOSIZE, SW0_BT_FIFO_SIZE, ACP_BT_TX_RINGBUFADDR, ACP_BT_TX_RINGBUFSIZE, -ACP_BT_TX_DMA_SIZE, ACP_BT_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_INTR_CNTL, 3} +ACP_BT_TX_DMA_SIZE, ACP_BT_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT, ACP_DSP0_INTR_CNTL, 3}, + +#if defined(CONFIG_ACP_7_0) +{ACP_P1_SW_AUDIO_RX_EN, ACP_P1_SW_AUDIO_RX_EN_STATUS, ACP_P1_AUDIO_RX_FIFOADDR, +SW1_AUDIO_RX_FIFO_ADDR, ACP_P1_AUDIO_RX_FIFOSIZE, SW1_AUDIO_FIFO_SIZE, +ACP_P1_AUDIO_RX_RINGBUFADDR, ACP_P1_AUDIO_RX_RINGBUFSIZE, ACP_P1_AUDIO_RX_DMA_SIZE, +ACP_P1_AUDIO_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1, 4}, + +{ACP_P1_SW_AUDIO_TX_EN, ACP_P1_SW_AUDIO_TX_EN_STATUS, ACP_P1_AUDIO_TX_FIFOADDR, +SW1_AUDIO_TX_FIFO_ADDR, ACP_P1_AUDIO_TX_FIFOSIZE, SW1_AUDIO_FIFO_SIZE, +ACP_P1_AUDIO_TX_RINGBUFADDR, ACP_P1_AUDIO_TX_RINGBUFSIZE, ACP_P1_AUDIO_TX_DMA_SIZE, +ACP_P1_AUDIO_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1, 5}, + +{ACP_P1_SW_HEADSET_RX_EN, ACP_P1_SW_HEADSET_RX_EN_STATUS, ACP_P1_HS_RX_FIFOADDR, +SW1_HS_RX_FIFO_ADDR, ACP_P1_HS_RX_FIFOSIZE, SW1_HS_FIFO_SIZE, +ACP_P1_HS_RX_RINGBUFADDR, ACP_P1_HS_RX_RINGBUFSIZE, ACP_P1_HS_RX_DMA_SIZE, +ACP_P1_HS_RX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1, 0}, + +{ACP_P1_SW_HEADSET_TX_EN, ACP_P1_SW_HEADSET_TX_EN_STATUS, ACP_P1_HS_TX_FIFOADDR, +SW1_HS_TX_FIFO_ADDR, ACP_P1_HS_TX_FIFOSIZE, SW1_HS_FIFO_SIZE, +ACP_P1_HS_TX_RINGBUFADDR, ACP_P1_HS_TX_RINGBUFSIZE, ACP_P1_HS_TX_DMA_SIZE, +ACP_P1_HS_TX_INTR_WATERMARK_SIZE, ACP_DSP0_INTR_STAT1, ACP_DSP0_INTR_CNTL1, 1}, +#endif }; /* allocate next free DMA channel */ @@ -136,7 +172,7 @@ static int acp_dai_sw_audio_dma_start(struct dma_chan_data *channel) uint32_t acp_pdm_en; int i; - for (i = 0; i < 8; i += 2) { + for (i = 0; i < DMA_CH_COUNT; i += 2) { sw0_audio_tx_en |= io_reg_read(PU_REGISTER_BASE + sw_dev[i].sw_dev_en); sw0_audio_rx_en |= io_reg_read(PU_REGISTER_BASE + sw_dev[i + 1].sw_dev_en); } @@ -208,7 +244,7 @@ static int acp_dai_sw_audio_dma_stop(struct dma_chan_data *channel) return -EINVAL; } - for (i = 0; i < 8; i += 2) { + for (i = 0; i < DMA_CH_COUNT; i += 2) { sw0_audio_tx_en |= io_reg_read(PU_REGISTER_BASE + sw_dev[i].sw_dev_en); sw0_audio_rx_en |= io_reg_read(PU_REGISTER_BASE + sw_dev[i + 1].sw_dev_en); } @@ -420,6 +456,10 @@ static int acp_dai_sw_audio_dma_interrupt(struct dma_chan_data *channel, enum dm switch (channel->index) { case SDW1_ACP_P1_SW_BT_TX_EN_CH: case SDW1_ACP_P1_SW_BT_RX_EN_CH: + case SDW1_ACP_P1_SW_AUDIO_RX_EN_CH: + case SDW1_ACP_P1_SW_AUDIO_TX_EN_CH: + case SDW1_ACP_P1_SW_HS_RX_EN_CH: + case SDW1_ACP_P1_SW_HS_TX_EN_CH: acp_intr_stat1 = (acp_dsp0_intr_stat1_t)dma_reg_read(channel->dma, sw_dev[channel->index].sw_dev_dma_intr_status); status = acp_intr_stat1.bits.audio_buffer_int_stat; @@ -435,6 +475,10 @@ static int acp_dai_sw_audio_dma_interrupt(struct dma_chan_data *channel, enum dm switch (channel->index) { case SDW1_ACP_P1_SW_BT_TX_EN_CH: case SDW1_ACP_P1_SW_BT_RX_EN_CH: + case SDW1_ACP_P1_SW_AUDIO_RX_EN_CH: + case SDW1_ACP_P1_SW_AUDIO_TX_EN_CH: + case SDW1_ACP_P1_SW_HS_RX_EN_CH: + case SDW1_ACP_P1_SW_HS_TX_EN_CH: acp_intr_stat1.u32all = 0; acp_intr_stat1.bits.audio_buffer_int_stat = (1 << sw_dev[channel->index].statusindex); @@ -456,6 +500,10 @@ static int acp_dai_sw_audio_dma_interrupt(struct dma_chan_data *channel, enum dm switch (channel->index) { case SDW1_ACP_P1_SW_BT_TX_EN_CH: case SDW1_ACP_P1_SW_BT_RX_EN_CH: + case SDW1_ACP_P1_SW_AUDIO_RX_EN_CH: + case SDW1_ACP_P1_SW_AUDIO_TX_EN_CH: + case SDW1_ACP_P1_SW_HS_RX_EN_CH: + case SDW1_ACP_P1_SW_HS_TX_EN_CH: acp_intr_cntl1 = (acp_dsp0_intr_cntl1_t)dma_reg_read(channel->dma, sw_dev[channel->index].sw_dev_dma_intr_cntl); acp_intr_cntl1.bits.audio_buffer_int_mask &= @@ -479,6 +527,10 @@ static int acp_dai_sw_audio_dma_interrupt(struct dma_chan_data *channel, enum dm switch (channel->index) { case SDW1_ACP_P1_SW_BT_TX_EN_CH: case SDW1_ACP_P1_SW_BT_RX_EN_CH: + case SDW1_ACP_P1_SW_AUDIO_RX_EN_CH: + case SDW1_ACP_P1_SW_AUDIO_TX_EN_CH: + case SDW1_ACP_P1_SW_HS_RX_EN_CH: + case SDW1_ACP_P1_SW_HS_TX_EN_CH: acp_intr_cntl1 = (acp_dsp0_intr_cntl1_t)dma_reg_read(channel->dma, sw_dev[channel->index].sw_dev_dma_intr_cntl); acp_intr_cntl1.bits.audio_buffer_int_mask |= diff --git a/src/platform/amd/acp_7_0/include/platform/chip_offset_byte.h b/src/platform/amd/acp_7_0/include/platform/chip_offset_byte.h index cce6411e24f8..7139cdb7e65d 100644 --- a/src/platform/amd/acp_7_0/include/platform/chip_offset_byte.h +++ b/src/platform/amd/acp_7_0/include/platform/chip_offset_byte.h @@ -136,6 +136,21 @@ #define ACP_WOV_MISC_CTRL 0x1242C5C #define ACP_WOV_CLK_CTRL 0x1242C60 +#define ACP_SW_EN 0x1243000 +#define ACP_SW_EN_STATUS 0x1243004 +#define ACP_SW_AUDIO_TX_EN 0x1243010 +#define ACP_SW_AUDIO_TX_EN_STATUS 0x1243014 +#define ACP_SW_BT_TX_EN 0x1243050 +#define ACP_SW_BT_TX_EN_STATUS 0x1243054 +#define ACP_SW_HS_TX_EN 0x124306C +#define ACP_SW_HS_TX_EN_STATUS 0x1243070 +#define ACP_SW_AUDIO_RX_EN 0x1243088 +#define ACP_SW_AUDIO_RX_EN_STATUS 0x124308C +#define ACP_SW_BT_RX_EN 0x1243128 +#define ACP_SW_BT_RX_EN_STATUS 0x124312C +#define ACP_SW_HS_RX_EN 0x1243144 +#define ACP_SW_HS_RX_EN_STATUS 0x1243148 + /* Registers from ACP_P1_AUDIO_BUFFERS block */ #define ACP_P1_I2S_RX_RINGBUFADDR 0x1243A00 #define ACP_P1_I2S_RX_RINGBUFSIZE 0x1243A04 @@ -153,6 +168,24 @@ #define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x1243A3C #define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW 0x1243A40 #define ACP_P1_I2S_TX_INTR_WATERMARK_SIZE 0x1243A44 + +#define ACP_P1_AUDIO_RX_RINGBUFADDR 0x1243A00 +#define ACP_P1_AUDIO_RX_RINGBUFSIZE 0x1243A04 +#define ACP_P1_AUDIO_RX_FIFOADDR 0x1243A0C +#define ACP_P1_AUDIO_RX_FIFOSIZE 0x1243A10 +#define ACP_P1_AUDIO_RX_DMA_SIZE 0x1243A14 +#define ACP_P1_AUDIO_RX_LINEARPOSITIONCNTR_HIGH 0x1243A18 +#define ACP_P1_AUDIO_RX_LINEARPOSITIONCNTR_LOW 0x1243A1C +#define ACP_P1_AUDIO_RX_INTR_WATERMARK_SIZE 0x1243A20 +#define ACP_P1_AUDIO_TX_RINGBUFADDR 0x1243A24 +#define ACP_P1_AUDIO_TX_RINGBUFSIZE 0x1243A28 +#define ACP_P1_AUDIO_TX_FIFOADDR 0x1243A30 +#define ACP_P1_AUDIO_TX_FIFOSIZE 0x1243A34 +#define ACP_P1_AUDIO_TX_DMA_SIZE 0x1243A38 +#define ACP_P1_AUDIO_TX_LINEARPOSITIONCNTR_HIGH 0x1243A3C +#define ACP_P1_AUDIO_TX_LINEARPOSITIONCNTR_LOW 0x1243A40 +#define ACP_P1_AUDIO_TX_INTR_WATERMARK_SIZE 0x1243A44 + #define ACP_P1_BT_RX_RINGBUFADDR 0x1243A48 #define ACP_P1_BT_RX_RINGBUFSIZE 0x1243A4C #define ACP_P1_BT_RX_FIFOADDR 0x1243A54 @@ -186,6 +219,21 @@ #define ACP_P1_HS_TX_LINEARPOSITIONCNTR_LOW 0x1243AD0 #define ACP_P1_HS_TX_INTR_WATERMARK_SIZE 0x1243AD4 +#define ACP_P1_SW_AUDIO_TX_EN 0x1243C10 +#define ACP_P1_SW_AUDIO_TX_EN_STATUS 0x1243C14 +#define ACP_P1_SW_AUDIO_RX_EN 0x1243C88 +#define ACP_P1_SW_AUDIO_RX_EN_STATUS 0x1243C8C + +#define ACP_P1_SW_BT_TX_EN 0x1243C50 +#define ACP_P1_SW_BT_TX_EN_STATUS 0x1243C54 +#define ACP_P1_SW_BT_RX_EN 0x1243D28 +#define ACP_P1_SW_BT_RX_EN_STATUS 0x1243D2C + +#define ACP_P1_SW_HEADSET_TX_EN 0x1243C6C +#define ACP_P1_SW_HEADSET_TX_EN_STATUS 0x1243C70 +#define ACP_P1_SW_HEADSET_RX_EN 0x1243D44 +#define ACP_P1_SW_HEADSET_RX_EN_STATUS 0x1243D48 + #define MP1_SMN_C2PMSG_69 0x58A14 #define MP1_SMN_C2PMSG_85 0x58A54 #define MP1_SMN_C2PMSG_93 0x58A74 diff --git a/src/platform/amd/acp_7_0/include/platform/lib/memory.h b/src/platform/amd/acp_7_0/include/platform/lib/memory.h index e19c61457b8c..abf87a21e360 100644 --- a/src/platform/amd/acp_7_0/include/platform/lib/memory.h +++ b/src/platform/amd/acp_7_0/include/platform/lib/memory.h @@ -26,7 +26,7 @@ #define DRAM1_BASE 0xE0010000 #define DRAM1_SIZE 0x10000 #define SRAM1_BASE 0x6000C000 -#define SRAM1_SIZE 0x27A000 +#define SRAM1_SIZE 0x274000 #define DMA0_BASE PU_REGISTER_BASE #define DMA0_SIZE 0x4 @@ -35,12 +35,22 @@ #define DAI_BASE (PU_REGISTER_BASE + ACP_I2S_RX_RINGBUFADDR) #define DAI_BASE_REM (PU_REGISTER_BASE + ACP_P1_I2S_RX_RINGBUFADDR) #define DAI_SIZE 0x4 + +#define SW1_AUDIO_TX_FIFO_OFFST (ACP_P1_AUDIO_TX_FIFOADDR - ACP_P1_AUDIO_RX_RINGBUFADDR) +#define SW1_AUDIO_RX_FIFO_OFFST (ACP_P1_AUDIO_RX_FIFOADDR - ACP_P1_AUDIO_RX_RINGBUFADDR) + #define BT_TX_FIFO_OFFST (ACP_P1_BT_TX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR) #define BT_RX_FIFO_OFFST (ACP_P1_BT_RX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR) +#define SW1_HS_TX_FIFO_OFFST (ACP_P1_HS_TX_FIFOADDR - ACP_P1_HS_RX_RINGBUFADDR) +#define SW1_HS_RX_FIFO_OFFST (ACP_P1_HS_RX_FIFOADDR - ACP_P1_HS_RX_RINGBUFADDR) + #define HS_TX_FIFO_OFFST (ACP_P1_HS_TX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR) #define HS_RX_FIFO_OFFST (ACP_P1_HS_TX_FIFOADDR - ACP_P1_I2S_RX_RINGBUFADDR) +#define SW0_AUDIO_TX_FIFO_OFFST (ACP_AUDIO_TX_FIFOADDR - ACP_AUDIO_RX_RINGBUFADDR) +#define SW0_AUDIO_RX_FIFO_OFFST (ACP_AUDIO_RX_FIFOADDR - ACP_AUDIO_RX_RINGBUFADDR) + #define BT0_TX_FIFO_OFFST (ACP_BT_TX_FIFOADDR - ACP_AUDIO_RX_RINGBUFADDR) #define BT0_RX_FIFO_OFFST (ACP_BT_RX_FIFOADDR - ACP_AUDIO_RX_RINGBUFADDR) diff --git a/src/platform/amd/acp_7_0/lib/dai.c b/src/platform/amd/acp_7_0/lib/dai.c index a2ddf2df5386..1879c041e24c 100644 --- a/src/platform/amd/acp_7_0/lib/dai.c +++ b/src/platform/amd/acp_7_0/lib/dai.c @@ -70,6 +70,141 @@ static struct dai hsdai[] = { } }; +static struct dai swaudiodai[] = { + { + .index = DI_SDW0_ACP_SW_AUDIO_TX, + .plat_data = { + .base = DAI_BASE_REM, + .fifo[SOF_IPC_STREAM_PLAYBACK] = { + .offset = DAI_BASE_REM + SW0_AUDIO_TX_FIFO_OFFST, + .handshake = SDW0_ACP_SW_AUDIO_TX_EN_CH, + } + }, + .drv = &acp_swaudiodai_driver, + }, + { + .index = DI_SDW0_ACP_SW_AUDIO_RX, + .plat_data = { + .base = DAI_BASE_REM, + .fifo[SOF_IPC_STREAM_CAPTURE] = { + .offset = DAI_BASE_REM + SW0_AUDIO_RX_FIFO_OFFST, + .handshake = SDW0_ACP_SW_AUDIO_RX_EN_CH, + }, + }, + .drv = &acp_swaudiodai_driver, + }, + { + .index = DI_SDW0_ACP_SW_BT_TX, + .plat_data = { + .base = DAI_BASE_REM, + .fifo[SOF_IPC_STREAM_PLAYBACK] = { + .offset = DAI_BASE_REM + BT0_TX_FIFO_OFFST, + .handshake = SDW0_ACP_SW_BT_TX_EN_CH, + } + }, + .drv = &acp_swaudiodai_driver, + }, + { + .index = DI_SDW0_ACP_SW_BT_RX, + .plat_data = { + .base = DAI_BASE_REM, + .fifo[SOF_IPC_STREAM_CAPTURE] = { + .offset = DAI_BASE_REM + BT0_RX_FIFO_OFFST, + .handshake = SDW0_ACP_SW_BT_RX_EN_CH, + }, + }, + .drv = &acp_swaudiodai_driver, + }, + { + .index = DI_SDW0_ACP_SW_HS_TX, + .plat_data = { + .base = DAI_BASE_REM, + .fifo[SOF_IPC_STREAM_PLAYBACK] = { + .offset = DAI_BASE_REM + HS0_TX_FIFO_OFFST, + .handshake = SDW0_ACP_SW_HS_TX_EN_CH, + } + }, + .drv = &acp_swaudiodai_driver, + }, + { + .index = DI_SDW0_ACP_SW_HS_RX, + .plat_data = { + .base = DAI_BASE_REM, + .fifo[SOF_IPC_STREAM_CAPTURE] = { + .offset = DAI_BASE_REM + HS0_RX_FIFO_OFFST, + .handshake = SDW0_ACP_SW_HS_RX_EN_CH, + }, + }, + .drv = &acp_swaudiodai_driver, + }, + { + .index = DI_SDW1_ACP_P1_SW_BT_TX, + .plat_data = { + .base = DAI_BASE_REM, + .fifo[SOF_IPC_STREAM_PLAYBACK] = { + .offset = DAI_BASE_REM + BT_TX_FIFO_OFFST, + .handshake = SDW1_ACP_P1_SW_BT_TX_EN_CH, + } + }, + .drv = &acp_swaudiodai_driver, + }, + { + .index = DI_SDW1_ACP_P1_SW_BT_RX, + .plat_data = { + .base = DAI_BASE_REM, + .fifo[SOF_IPC_STREAM_CAPTURE] = { + .offset = DAI_BASE_REM + BT_RX_FIFO_OFFST, + .handshake = SDW1_ACP_P1_SW_BT_RX_EN_CH, + }, + }, + .drv = &acp_swaudiodai_driver, + }, + { + .index = DI_SDW1_ACP_P1_SW_AUDIO_TX, + .plat_data = { + .base = DAI_BASE_REM, + .fifo[SOF_IPC_STREAM_PLAYBACK] = { + .offset = DAI_BASE_REM + SW1_AUDIO_TX_FIFO_OFFST, + .handshake = SDW1_ACP_P1_SW_AUDIO_TX_EN_CH, + } + }, + .drv = &acp_swaudiodai_driver, + }, + { + .index = DI_SDW1_ACP_P1_SW_AUDIO_RX, + .plat_data = { + .base = DAI_BASE_REM, + .fifo[SOF_IPC_STREAM_CAPTURE] = { + .offset = DAI_BASE_REM + SW1_AUDIO_RX_FIFO_OFFST, + .handshake = SDW1_ACP_P1_SW_AUDIO_RX_EN_CH, + }, + }, + .drv = &acp_swaudiodai_driver, + }, + { + .index = DI_SDW1_ACP_P1_SW_HS_TX, + .plat_data = { + .base = DAI_BASE_REM, + .fifo[SOF_IPC_STREAM_PLAYBACK] = { + .offset = DAI_BASE_REM + SW1_HS_TX_FIFO_OFFST, + .handshake = SDW1_ACP_P1_SW_HS_TX_EN_CH, + }, + }, + .drv = &acp_swaudiodai_driver, + }, + { + .index = DI_SDW1_ACP_P1_SW_HS_RX, + .plat_data = { + .base = DAI_BASE_REM, + .fifo[SOF_IPC_STREAM_CAPTURE] = { + .offset = DAI_BASE_REM + SW1_HS_RX_FIFO_OFFST, + .handshake = SDW1_ACP_P1_SW_HS_RX_EN_CH, + }, + }, + .drv = &acp_swaudiodai_driver, + }, +}; + #ifdef ACP_SP_ENABLE static struct dai spdai[] = { { @@ -163,6 +298,11 @@ const struct dai_type_info dti[] = { .num_dais = ARRAY_SIZE(btdai) }, #endif + { + .type = SOF_DAI_AMD_SW_AUDIO, + .dai_array = swaudiodai, + .num_dais = ARRAY_SIZE(swaudiodai) + }, }; const struct dai_info lib_dai = { @@ -179,6 +319,8 @@ int dai_init(struct sof *sof) k_spinlock_init(&acp_dmic_dai[i].lock); for (i = 0; i < ARRAY_SIZE(hsdai); i++) k_spinlock_init(&hsdai[i].lock); + for (i = 0; i < ARRAY_SIZE(swaudiodai); i++) + k_spinlock_init(&swaudiodai[i].lock); #ifdef ACP_SP_ENABLE for (i = 0; i < ARRAY_SIZE(spdai); i++) k_spinlock_init(&spdai[i].lock); diff --git a/src/platform/amd/acp_7_0/lib/dma.c b/src/platform/amd/acp_7_0/lib/dma.c index 9d840c3f5a6c..bbc6b4a6cd8a 100644 --- a/src/platform/amd/acp_7_0/lib/dma.c +++ b/src/platform/amd/acp_7_0/lib/dma.c @@ -22,6 +22,7 @@ extern struct dma_ops acp_dai_bt_dma_ops; extern struct dma_ops acp_dai_sp_dma_ops; #endif extern struct dma_ops acp_dai_hs_dma_ops; +extern struct dma_ops acp_dai_sw_audio_dma_ops; SHARED_DATA struct dma dma[PLATFORM_NUM_DMACS] = { { @@ -51,6 +52,20 @@ SHARED_DATA struct dma dma[PLATFORM_NUM_DMACS] = { }, .ops = &acp_dai_hs_dma_ops, }, +{ + .plat_data = { + .id = DMA_ID_DAI_SW_AUDIO, + .dir = DMA_DIR_DEV_TO_MEM | DMA_DIR_MEM_TO_DEV, + .devs = DMA_DEV_SW, + .caps = DMA_CAP_SW, + .base = DMA0_BASE, + .chan_size = DMA0_SIZE, + .channels = 12, + .irq = IRQ_NUM_EXT_LEVEL5, + .irq_name = "irqsteer1", + }, + .ops = &acp_dai_sw_audio_dma_ops, +}, { .plat_data = { .id = DMA_ID_DAI_DMIC, diff --git a/src/platform/amd/common/include/platform/lib/dai.h b/src/platform/amd/common/include/platform/lib/dai.h index c2ed312ac4f0..250e8f945552 100644 --- a/src/platform/amd/common/include/platform/lib/dai.h +++ b/src/platform/amd/common/include/platform/lib/dai.h @@ -18,7 +18,10 @@ #define SDW0_ACP_SW_AUDIO_TX_EN_CH 5 #define SDW0_ACP_SW_BT_RX_EN_CH 6 #define SDW0_ACP_SW_BT_TX_EN_CH 7 -#define SDW0_ACP_SW_BT_CH_OFFSET 4 +#define SDW1_ACP_P1_SW_AUDIO_RX_EN_CH 8 +#define SDW1_ACP_P1_SW_AUDIO_TX_EN_CH 9 +#define SDW1_ACP_P1_SW_HS_RX_EN_CH 10 +#define SDW1_ACP_P1_SW_HS_TX_EN_CH 11 #define DI_SDW0_ACP_SW_AUDIO_TX 0 #define DI_SDW0_ACP_SW_BT_TX 1 @@ -26,8 +29,12 @@ #define DI_SDW0_ACP_SW_AUDIO_RX 3 #define DI_SDW0_ACP_SW_BT_RX 4 #define DI_SDW0_ACP_SW_HS_RX 5 +#define DI_SDW1_ACP_P1_SW_AUDIO_TX 64 #define DI_SDW1_ACP_P1_SW_BT_TX 65 +#define DI_SDW1_ACP_P1_SW_HS_TX 66 +#define DI_SDW1_ACP_P1_SW_AUDIO_RX 67 #define DI_SDW1_ACP_P1_SW_BT_RX 68 +#define DI_SDW1_ACP_P1_SW_HS_RX 69 #endif /* __PLATFORM_LIB_DAI_H__ */ diff --git a/src/platform/amd/common/include/platform/lib/dma.h b/src/platform/amd/common/include/platform/lib/dma.h index b8d6064d8862..f8d053876353 100644 --- a/src/platform/amd/common/include/platform/lib/dma.h +++ b/src/platform/amd/common/include/platform/lib/dma.h @@ -13,7 +13,7 @@ #define PLATFORM_NUM_DMACS 4 /* max number of supported DMA channels */ -#define PLATFORM_MAX_DMA_CHAN 8 +#define PLATFORM_MAX_DMA_CHAN 12 #define DMA_ID_DMA0 0 #define DMA_ID_HOST 1 diff --git a/tools/rimage/config/acp_7_0.toml b/tools/rimage/config/acp_7_0.toml index 40e9236e26bb..916bcb24f047 100644 --- a/tools/rimage/config/acp_7_0.toml +++ b/tools/rimage/config/acp_7_0.toml @@ -16,5 +16,5 @@ host_offset = "0x0" [[adsp.mem_zone]] type = "SRAM" base = "0x6000C000" -size = "0x27A000" +size = "0x274000" host_offset = "0x0" \ No newline at end of file From 0feb83a56f590ec359b62a853d8ccdae701207d9 Mon Sep 17 00:00:00 2001 From: SaiSurya Ch Date: Mon, 17 Feb 2025 16:16:01 +0530 Subject: [PATCH 2/2] amd : ACP_7_0 : Add SW topology for the platform ACP_7_0. amd : ACP_7_0 : Add SW topology for the platform ACP_7_0. Signed-off-by: SaiSurya Ch --- tools/topology/topology1/CMakeLists.txt | 1 + tools/topology/topology1/sof-acp_7_0_sdw.m4 | 150 ++++++++++++++++++++ 2 files changed, 151 insertions(+) create mode 100644 tools/topology/topology1/sof-acp_7_0_sdw.m4 diff --git a/tools/topology/topology1/CMakeLists.txt b/tools/topology/topology1/CMakeLists.txt index fbbdef677361..2d1e804ab651 100644 --- a/tools/topology/topology1/CMakeLists.txt +++ b/tools/topology/topology1/CMakeLists.txt @@ -115,6 +115,7 @@ set(TPLGS "sof-acp_6_3\;sof-acp_6_3" "sof-acp_6_3_sdw\;sof-acp_6_3-rt711-l0-rt1316-l0-rt714-l1" "sof-acp_7_0\;sof-acp_7_0" + "sof-acp_7_0_sdw\;sof-acp_7_0-rt722-l0" ) # This empty 'production/' source subdirectory exists only to create the diff --git a/tools/topology/topology1/sof-acp_7_0_sdw.m4 b/tools/topology/topology1/sof-acp_7_0_sdw.m4 new file mode 100644 index 000000000000..ca03f0cd2749 --- /dev/null +++ b/tools/topology/topology1/sof-acp_7_0_sdw.m4 @@ -0,0 +1,150 @@ +#Required Topology for rt722 with ACP DMIC Card for ACP_7_0 +# +# PCM Description DAI LINK DAI BE +# 0       HS Playback 0 SDW0-PIN0-Playback-SimpleJack       AUDIO_TX +# 1       HS Capture 1 SDW0-PIN3-Capture-SimpleJack    AUDIO_RX +# 2       Speaker playback 2 SDW0-PIN1-Playback-SmartAmp    BT_TX +# 4       SDW DMIC 4 SDW0-PIN5-Capture-SmartMic    HS_RX + +# +# Define the pipelines +# +# PCM0 ----> buffer ----> AUDIO_TX +# PCM1 <---- buffer <---- AUDIO_RX +# PCM2 ----> buffer ----> BT_TX +# PCM4 <---- buffer <---- HS_RX + +# Include topology builder +include(`utils.m4') +include(`dai.m4') +include(`pipeline.m4') +include(`acp-sdw.m4') +include(`acp-dmic.m4') + +# Include TLV library +include(`common/tlv.m4') + +# Include Token library +include(`sof/tokens.m4') + +# Include ACP DSP configuration +include(`platform/amd/acp.m4') + +DEBUG_START + +#/**********************************************************************************/ +# PCM 0, HS Playback, DAI link id 0, Dai index 0(Audio_Tx), BE SW0-PIN0-PLAYBACK + +#Driver dai index and dai BE +#DAI Index(Instance * 64 + base_index) DAI_BE +#0(AUDIO_TX) SDW0-PIN0-PLAYBACK-SimpleJack +#1(BT_TX) SDW0-PIN1-PLAYBACK-SmartAmp +#2(HS_TX) SDW0-PIN2-PLAYBACK +#3(AUDIO_RX) SDW0-PIN3-CAPTURE-SimpleJack +#4(BT_RX) SDW0-PIN4-CAPTURE-SmartAmp +#5(HS_RX) SDW0-PIN5-CAPTURE + +define(DI_SDW0_ACP_SW_Audio_TX, 0) +define(DI_SDW0_ACP_SW_BT_TX, 1) +define(DI_SDW0_ACP_SW_HS_TX, 2) +define(DI_SDW0_ACP_SW_Audio_RX, 3) +define(DI_SDW0_ACP_SW_BT_RX, 4) +define(DI_SDW0_ACP_SW_HS_RX, 5) +define(DI_SDW1_ACP_P1_SW_BT_RX, 68) +define(DI_SDW1_ACP_P1_SW_BT_TX, 65) + +define(DAI_BE_SDW0_ACP_SW_HS_TX, SDW0-PIN2-PLAYBACK) +define(DAI_BE_SDW1_ACP_P1_SW_BT_RX, SDW1-PIN1-CAPTURE-SmartMic) +define(DAI_BE_SDW1_ACP_P1_SW_BT_TX, SDW1-PIN1-PLAYBACK) +define(DAI_BE_ACP_SW_Audio_RX, SDW0-PIN3-CAPTURE-SimpleJack) +define(DAI_BE_SDW0_ACP_SW_Audio_TX, SDW0-PIN0-PLAYBACK-SimpleJack) +define(DAI_BE_SDW0_ACP_SW_BT_RX, SDW0-PIN4-CAPTURE-SmartAmp) +define(DAI_BE_SDW0_ACP_SW_BT_TX, SDW0-PIN1-PLAYBACK-SmartAmp) +define(DAI_BE_SDW0_ACP_SW_HS_RX, SDW0-PIN5-CAPTURE-SmartMic) + +#pipeline: name of the predefined pipeline +#pipe id: pipeline ID. This should be a unique ID identifying the pipeline +#pcm: PCM ID. This will be used to bind to the correct front end DAI link + +dnl PIPELINE_PCM_ADD(pipeline, +dnl pipe id, pcm, max channels, format, +dnl period, priority, core, +dnl pcm_min_rate, pcm_max_rate, pipeline_rate) +PIPELINE_PCM_ADD(sof/pipe-passthrough-playback.m4, + 0, 0, 2, s16le, + 2000, 0, 0, + 48000, 48000, 48000) + +dnl DAI_ADD(pipeline, +dnl pipe id, dai type, dai_index, dai_be, +dnl buffer, periods, format, +dnl deadline, priority, core, time_domain) +DAI_ADD(sof/pipe-dai-playback.m4, 0, ACP_SDW, DI_SDW0_ACP_SW_Audio_TX, DAI_BE_SDW0_ACP_SW_Audio_TX, + PIPELINE_SOURCE_0, 2, s16le, 2000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) + +dnl DAI_CONFIG(type, dai_index, link_id, name, acphs_config/acpdmic_config) +dnl ACPHS_CONFIG(format, mclk, bclk, fsync, tdm, acphs_config_data) +dnl ACP_CLOCK(clock, freq, codec_provider, polarity) +dnl ACPHS_CONFIG_DATA(type, idx, valid bits, mclk_id) +dnl mclk_id is optional +DAI_CONFIG(ACP_SDW, DI_SDW0_ACP_SW_Audio_TX, 0, DAI_BE_SDW0_ACP_SW_Audio_TX, + ACP_SDW_CONFIG(ACP_SDW_CONFIG_DATA(ACP_SDW, DI_SDW0_ACP_SW_Audio_TX, 48000, 2))) + +PCM_PLAYBACK_ADD(ACP-SW0-PIN0-Playback-HS, 0, PIPELINE_PCM_0) +#/**********************************************************************************/ + + +#/**********************************************************************************/ +#PCM 1, HS Capture, DAI link id 1, Dai index 3(Audio_RX), BE SW0-PIN0-CAPTURE +# Capture pipeline 1 on PCM 1 using max 2 channels of s16le. +PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, + 1, 1, 2, s16le, + 2000, 0, 0, + 48000, 48000, 48000) + +# Capture DAI is ACP soundwire using 2 periods +DAI_ADD(sof/pipe-dai-capture.m4, 1, ACP_SDW, DI_SDW0_ACP_SW_Audio_RX, DAI_BE_ACP_SW_Audio_RX, + PIPELINE_SINK_1, 2, s16le, 2000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) + +DAI_CONFIG(ACP_SDW, DI_SDW0_ACP_SW_Audio_RX, 1, DAI_BE_ACP_SW_Audio_RX, + ACP_SDW_CONFIG(ACP_SDW_CONFIG_DATA(ACP_SDW, DI_SDW0_ACP_SW_Audio_RX, 48000, 2))) + +PCM_CAPTURE_ADD(ACP-SW0-PIN0-Capture-HS, 1, PIPELINE_PCM_1) +#/**********************************************************************************/ + +#/**********************************************************************************/ +#PCM 2, Speaker Playback, DAI link id 2, Dai index 1(BT_TX), BE SW0-PIN1-PLAYBACK +PIPELINE_PCM_ADD(sof/pipe-passthrough-playback.m4, + 2, 2, 2, s16le, + 2000, 0, 0, + 48000, 48000, 48000) + +# playback DAI is ACP soundwire using 2 periods +DAI_ADD(sof/pipe-dai-playback.m4, 2, ACP_SDW, DI_SDW0_ACP_SW_BT_TX, DAI_BE_SDW0_ACP_SW_BT_TX, + PIPELINE_SOURCE_2, 2, s16le, 2000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) + +DAI_CONFIG(ACP_SDW, DI_SDW0_ACP_SW_BT_TX, 2, DAI_BE_SDW0_ACP_SW_BT_TX, + ACP_SDW_CONFIG(ACP_SDW_CONFIG_DATA(ACP_SDW, DI_SDW0_ACP_SW_BT_TX, 48000, 2))) + +PCM_PLAYBACK_ADD(ACP-SW0-PIN2-Playback-SPK, 2, PIPELINE_PCM_2) +#/**********************************************************************************/ + +#/**********************************************************************************/ +#PCM 4, SDW Capture, DAI link id 4, Dai index 5(HS_RX), BE SDW0-PIN5-CAPTURE-SmartMic +# Capture pipeline 1 on PCM 1 using max 2 channels of s16le. +PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, + 4, 4, 2, s16le, + 2000, 0, 0, + 48000, 48000, 48000) + +# Capture DAI is ACP soundwire using 2 periods +DAI_ADD(sof/pipe-dai-capture.m4, 4, ACP_SDW, DI_SDW0_ACP_SW_HS_RX, DAI_BE_SDW0_ACP_SW_HS_RX, + PIPELINE_SINK_4, 2, s16le, 2000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) + +DAI_CONFIG(ACP_SDW, DI_SDW0_ACP_SW_HS_RX, 4, DAI_BE_SDW0_ACP_SW_HS_RX, + ACP_SDW_CONFIG(ACP_SDW_CONFIG_DATA(ACP_SDW, DI_SDW0_ACP_SW_HS_RX, 48000, 2))) + +PCM_CAPTURE_ADD(ACP-SW0-PIN5-CAPTURE-DMIC, 4, PIPELINE_PCM_4) +#/**********************************************************************************/ + +DEBUG_END