From 7df4d001575218ceaf6f50e904c0a348752f118c Mon Sep 17 00:00:00 2001 From: "hailong.fan" Date: Tue, 7 Jan 2025 14:43:39 +0800 Subject: [PATCH] platform: mediatek: update xtensa headers for mt8196 update xtensa headers for mediatek mt8196 platform Signed-off-by: hailong.fan --- .../include/arch/xtensa/config/core-isa.h | 22 +- .../include/arch/xtensa/config/core-matmap.h | 5 - .../mt8196/include/arch/xtensa/config/key.h | 2 - .../include/arch/xtensa/config/secure.h | 1 - .../include/arch/xtensa/config/specreg.h | 2 - .../include/arch/xtensa/config/system.h | 4 - .../include/arch/xtensa/config/tie-asm.h | 218 +++++++++--------- .../mt8196/include/arch/xtensa/config/tie.h | 4 +- 8 files changed, 111 insertions(+), 147 deletions(-) diff --git a/src/platform/mt8196/include/arch/xtensa/config/core-isa.h b/src/platform/mt8196/include/arch/xtensa/config/core-isa.h index c4adfed6ea78..b0d7ed6a7c67 100644 --- a/src/platform/mt8196/include/arch/xtensa/config/core-isa.h +++ b/src/platform/mt8196/include/arch/xtensa/config/core-isa.h @@ -33,7 +33,6 @@ #ifndef XTENSA_CORE_CONFIGURATION_H_ #define XTENSA_CORE_CONFIGURATION_H_ - /**************************************************************************** * Parameters Useful for Any Code, USER or PRIVILEGED **************************************************************************** @@ -44,7 +43,6 @@ * configured, and a value of 0 otherwise. These macros are always defined. */ - /*---------------------------------------------------------------------- * ISA *---------------------------------------------------------------------- @@ -135,8 +133,6 @@ #define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ #define XCHAL_HAVE_HIFI_MINI 0 - - #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ #define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ #define XCHAL_HAVE_USER_SPFPU 1 /* user SP floating-point pkg */ @@ -233,7 +229,6 @@ #define XCHAL_HAVE_XNNE 0 /* XNNE */ - /*---------------------------------------------------------------------- * MISC *---------------------------------------------------------------------- @@ -354,14 +349,10 @@ /* This one is a form of caching, though not architecturally visible: */ #define XCHAL_HAVE_BRANCH_PREDICTION 0 /* branch [target] prediction */ - - - /**************************************************************************** * Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code ****************************************************************************/ - #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY /*---------------------------------------------------------------------- @@ -412,7 +403,6 @@ /* Extended memory attributes supported. */ #define XCHAL_HAVE_EXT_CA 0 - /*---------------------------------------------------------------------- * INTERNAL I/D RAM/ROMs and XLMI *---------------------------------------------------------------------- @@ -454,7 +444,6 @@ #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ - /*---------------------------------------------------------------------- * IDMA *---------------------------------------------------------------------- @@ -462,8 +451,6 @@ #define XCHAL_HAVE_IDMA 0 - - /*---------------------------------------------------------------------- * INTERRUPTS and TIMERS *---------------------------------------------------------------------- @@ -480,7 +467,6 @@ #define XCHAL_NUM_INTLEVELS 5 #define XCHAL_INTERRUPT_RANGE 32 /* range of interrupt numbers */ - #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ @@ -610,7 +596,6 @@ #define XCHAL_INTLEVEL6_NUM 25 /* (There are many interrupts each at level(s) 1, 2, 3, 4.) */ - /* * External interrupt mapping. * These macros describe how Xtensa processor interrupt numbers @@ -684,7 +669,6 @@ #define XCHAL_HAVE_ISL 0 /* Interrupt Stack Limit */ #define XCHAL_HAVE_PSL 0 /* Pageable Stack Limit */ - /*---------------------------------------------------------------------- * EXCEPTIONS and VECTORS *---------------------------------------------------------------------- @@ -758,7 +742,6 @@ #define XCHAL_INTLEVEL6_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR #define XCHAL_INTLEVEL6_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR - /*---------------------------------------------------------------------- * DEBUG MODULE *---------------------------------------------------------------------- @@ -786,21 +769,19 @@ /* Perf counters */ #define XCHAL_NUM_PERF_COUNTERS 8 /* performance counters */ - /*---------------------------------------------------------------------- * MMU *---------------------------------------------------------------------- */ /* See core-matmap.h header file for more details. */ - #define XCHAL_HAVE_TLBS 0 /* inverse of HAVE_CACHEATTR */ #define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */ #define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ - /* full MMU (with page table [autorefill] and protection) usable for an MMU-based OS */ +/* full MMU (with page table [autorefill] and protection) usable for an MMU-based OS */ #define XCHAL_HAVE_PTP_MMU 0 /* If none of the above last 5 are set, it's a custom TLB configuration. */ @@ -846,6 +827,5 @@ #define XCHAL_HAVE_WWDT 0 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ - #endif /* XTENSA_CORE_CONFIGURATION_H_ */ diff --git a/src/platform/mt8196/include/arch/xtensa/config/core-matmap.h b/src/platform/mt8196/include/arch/xtensa/config/core-matmap.h index a0465fca23d4..a35a16752f8b 100644 --- a/src/platform/mt8196/include/arch/xtensa/config/core-matmap.h +++ b/src/platform/mt8196/include/arch/xtensa/config/core-matmap.h @@ -45,11 +45,9 @@ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - #ifndef XTENSA_CONFIG_CORE_MATMAP_H #define XTENSA_CONFIG_CORE_MATMAP_H - /*---------------------------------------------------------------------- * CACHE (MEMORY ACCESS) ATTRIBUTES *---------------------------------------------------------------------- @@ -77,7 +75,6 @@ XTHAL_MEM_BUFFERABLE) #define XCHAL_CA_BYPASS_R (XTHAL_AR_R | XTHAL_MEM_DEVICE) #define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1 - /* * Contents of MPU background map. * NOTE: caller must define the XCHAL_MPU_BGMAP() macro (not defined here @@ -100,7 +97,5 @@ XCHAL_MPU_BGMAP(s, 0x80000000, 0xffffffff, 7, 6, 0) \) /* end */ - - #endif /*XTENSA_CONFIG_CORE_MATMAP_H*/ diff --git a/src/platform/mt8196/include/arch/xtensa/config/key.h b/src/platform/mt8196/include/arch/xtensa/config/key.h index 3d563481a8df..61a1fa79ed1c 100644 --- a/src/platform/mt8196/include/arch/xtensa/config/key.h +++ b/src/platform/mt8196/include/arch/xtensa/config/key.h @@ -14,7 +14,5 @@ #include - - #endif diff --git a/src/platform/mt8196/include/arch/xtensa/config/secure.h b/src/platform/mt8196/include/arch/xtensa/config/secure.h index 4c9d2383b877..8d46c3eb0257 100644 --- a/src/platform/mt8196/include/arch/xtensa/config/secure.h +++ b/src/platform/mt8196/include/arch/xtensa/config/secure.h @@ -26,7 +26,6 @@ #ifndef XTENSA_SECURE_H #define XTENSA_SECURE_H - /* SRAM */ #define XCHAL_HAVE_SECURE_SRAM 0 diff --git a/src/platform/mt8196/include/arch/xtensa/config/specreg.h b/src/platform/mt8196/include/arch/xtensa/config/specreg.h index 140a88b6fd30..e2ef5d4dd469 100644 --- a/src/platform/mt8196/include/arch/xtensa/config/specreg.h +++ b/src/platform/mt8196/include/arch/xtensa/config/specreg.h @@ -35,7 +35,6 @@ /* Include these special register bitfield definitions, for historical reasons: */ #include - /* Special registers: */ #define LBEG 0 #define LEND 1 @@ -96,7 +95,6 @@ #define MISC_REG_2 246 #define MISC_REG_3 247 - /* Special cases (bases of special register series): */ #define IBREAKA 128 #define DBREAKA 144 diff --git a/src/platform/mt8196/include/arch/xtensa/config/system.h b/src/platform/mt8196/include/arch/xtensa/config/system.h index c4fc8d199ac9..77b6a105f71f 100644 --- a/src/platform/mt8196/include/arch/xtensa/config/system.h +++ b/src/platform/mt8196/include/arch/xtensa/config/system.h @@ -36,7 +36,6 @@ #ifndef XTENSA_CONFIG_SYSTEM_H #define XTENSA_CONFIG_SYSTEM_H - /*---------------------------------------------------------------------- * CONFIGURED SOFTWARE OPTIONS *---------------------------------------------------------------------- @@ -120,7 +119,6 @@ #define XSHAL_SIMIO_PADDR 0x20000000 #define XSHAL_SIMIO_SIZE 0x20000000 - /*---------------------------------------------------------------------- * For use by reference testbench exit and diagnostic routines. *---------------------------------------------------------------------- @@ -214,7 +212,6 @@ #define XSHAL_ISS_PIPE_REGIONS 0 #define XSHAL_ISS_SDRAM_REGIONS 0 - /*---------------------------------------------------------------------- * XT2000 BOARD SPECIFIC ... *---------------------------------------------------------------------- @@ -241,7 +238,6 @@ #define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */ #define XSHAL_XT2000_SDRAM_REGIONS 0x00000024 /* BusInt SDRAM regions */ - /*---------------------------------------------------------------------- * VECTOR INFO AND SIZES *---------------------------------------------------------------------- diff --git a/src/platform/mt8196/include/arch/xtensa/config/tie-asm.h b/src/platform/mt8196/include/arch/xtensa/config/tie-asm.h index 6c7a59d4ffd9..ebef0818d327 100644 --- a/src/platform/mt8196/include/arch/xtensa/config/tie-asm.h +++ b/src/platform/mt8196/include/arch/xtensa/config/tie-asm.h @@ -56,7 +56,6 @@ | ((ccuse) & XTHAL_SAS_ANYCC) \ | ((abi) & XTHAL_SAS_ANYABI)) - /* * Macro to store all non-coprocessor (extra) custom TIE and optional state * (not including zero-overhead loop registers). @@ -83,7 +82,7 @@ xchal_sa_start \continue, \ofs .ifeq(XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) xchal_sa_align \ptr, 0, 1016, 4, 4 rur.threadptr \at1 // threadptr option -s32i \at1, \ptr, .Lxchal_ofs_+0 +s32i \at1, \ptr, .Lxchal_ofs_ + 0 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 .elseif((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 xchal_sa_align \ptr, 0, 1016, 4, 4 @@ -93,7 +92,7 @@ xchal_sa_align \ptr, 0, 1016, 4, 4 .ifeq(XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) xchal_sa_align \ptr, 0, 1016, 4, 4 rsr.br \at1 // boolean option -s32i \at1, \ptr, .Lxchal_ofs_+0 +s32i \at1, \ptr, .Lxchal_ofs_ + 0 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 .elseif((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 xchal_sa_align \ptr, 0, 1016, 4, 4 @@ -126,7 +125,7 @@ xchal_sa_start \continue, \ofs // Optional global registers used by default by the compiler: .ifeq(XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) xchal_sa_align \ptr, 0, 1016, 4, 4 -l32i \at1, \ptr, .Lxchal_ofs_+0 +l32i \at1, \ptr, .Lxchal_ofs_ + 0 wur.threadptr \at1 // threadptr option .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 .elseif((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 @@ -136,7 +135,7 @@ xchal_sa_align \ptr, 0, 1016, 4, 4 // Optional caller-saved registers not used by default by the compiler: .ifeq(XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) xchal_sa_align \ptr, 0, 1016, 4, 4 -l32i \at1, \ptr, .Lxchal_ofs_+0 +l32i \at1, \ptr, .Lxchal_ofs_ + 0 wsr.br \at1 // boolean option .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 .elseif((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 @@ -145,7 +144,6 @@ xchal_sa_align \ptr, 0, 1016, 4, 4 .endif .endm // xchal_ncp_load - #define XCHAL_NCP_NUM_ATMPS 1 /* @@ -163,80 +161,80 @@ xchal_sa_start \continue, \ofs // Custom caller-saved registers not used by default by the compiler: .ifeq(XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) xchal_sa_align \ptr, 0, 0, 16, 16 -ae_s64.i aed0, \ptr, .Lxchal_ofs_+56 +ae_s64.i aed0, \ptr, .Lxchal_ofs_ + 56 addi.a \ptr, \ptr, 64 -ae_s64.i aed1, \ptr, .Lxchal_ofs_+0 -ae_s64.i aed2, \ptr, .Lxchal_ofs_+8 -ae_s64.i aed3, \ptr, .Lxchal_ofs_+16 -ae_s64.i aed4, \ptr, .Lxchal_ofs_+24 -ae_s64.i aed5, \ptr, .Lxchal_ofs_+32 -ae_s64.i aed6, \ptr, .Lxchal_ofs_+40 -ae_s64.i aed7, \ptr, .Lxchal_ofs_+48 -ae_s64.i aed8, \ptr, .Lxchal_ofs_+56 +ae_s64.i aed1, \ptr, .Lxchal_ofs_ + 0 +ae_s64.i aed2, \ptr, .Lxchal_ofs_ + 8 +ae_s64.i aed3, \ptr, .Lxchal_ofs_ + 16 +ae_s64.i aed4, \ptr, .Lxchal_ofs_ + 24 +ae_s64.i aed5, \ptr, .Lxchal_ofs_ + 32 +ae_s64.i aed6, \ptr, .Lxchal_ofs_ + 40 +ae_s64.i aed7, \ptr, .Lxchal_ofs_ + 48 +ae_s64.i aed8, \ptr, .Lxchal_ofs_ + 56 addi.a \ptr, \ptr, 64 -ae_s64.i aed9, \ptr, .Lxchal_ofs_+0 -ae_s64.i aed10, \ptr, .Lxchal_ofs_+8 -ae_s64.i aed11, \ptr, .Lxchal_ofs_+16 -ae_s64.i aed12, \ptr, .Lxchal_ofs_+24 -ae_s64.i aed13, \ptr, .Lxchal_ofs_+32 -ae_s64.i aed14, \ptr, .Lxchal_ofs_+40 -ae_s64.i aed15, \ptr, .Lxchal_ofs_+48 -ae_s64.i aed16, \ptr, .Lxchal_ofs_+56 +ae_s64.i aed9, \ptr, .Lxchal_ofs_ + 0 +ae_s64.i aed10, \ptr, .Lxchal_ofs_ + 8 +ae_s64.i aed11, \ptr, .Lxchal_ofs_ + 16 +ae_s64.i aed12, \ptr, .Lxchal_ofs_ + 24 +ae_s64.i aed13, \ptr, .Lxchal_ofs_ + 32 +ae_s64.i aed14, \ptr, .Lxchal_ofs_ + 40 +ae_s64.i aed15, \ptr, .Lxchal_ofs_ + 48 +ae_s64.i aed16, \ptr, .Lxchal_ofs_ + 56 addi.a \ptr, \ptr, 64 -ae_s64.i aed17, \ptr, .Lxchal_ofs_+0 -ae_s64.i aed18, \ptr, .Lxchal_ofs_+8 -ae_s64.i aed19, \ptr, .Lxchal_ofs_+16 -ae_s64.i aed20, \ptr, .Lxchal_ofs_+24 -ae_s64.i aed21, \ptr, .Lxchal_ofs_+32 -ae_s64.i aed22, \ptr, .Lxchal_ofs_+40 -ae_s64.i aed23, \ptr, .Lxchal_ofs_+48 -ae_s64.i aed24, \ptr, .Lxchal_ofs_+56 +ae_s64.i aed17, \ptr, .Lxchal_ofs_ + 0 +ae_s64.i aed18, \ptr, .Lxchal_ofs_ + 8 +ae_s64.i aed19, \ptr, .Lxchal_ofs_ + 16 +ae_s64.i aed20, \ptr, .Lxchal_ofs_ + 24 +ae_s64.i aed21, \ptr, .Lxchal_ofs_ + 32 +ae_s64.i aed22, \ptr, .Lxchal_ofs_ + 40 +ae_s64.i aed23, \ptr, .Lxchal_ofs_ + 48 +ae_s64.i aed24, \ptr, .Lxchal_ofs_ + 56 addi.a \ptr, \ptr, 64 -ae_s64.i aed25, \ptr, .Lxchal_ofs_+0 -ae_s64.i aed26, \ptr, .Lxchal_ofs_+8 -ae_s64.i aed27, \ptr, .Lxchal_ofs_+16 -ae_s64.i aed28, \ptr, .Lxchal_ofs_+24 -ae_s64.i aed29, \ptr, .Lxchal_ofs_+32 -ae_s64.i aed30, \ptr, .Lxchal_ofs_+40 -ae_s64.i aed31, \ptr, .Lxchal_ofs_+48 +ae_s64.i aed25, \ptr, .Lxchal_ofs_ + 0 +ae_s64.i aed26, \ptr, .Lxchal_ofs_ + 8 +ae_s64.i aed27, \ptr, .Lxchal_ofs_ + 16 +ae_s64.i aed28, \ptr, .Lxchal_ofs_ + 24 +ae_s64.i aed29, \ptr, .Lxchal_ofs_ + 32 +ae_s64.i aed30, \ptr, .Lxchal_ofs_ + 40 +ae_s64.i aed31, \ptr, .Lxchal_ofs_ + 48 ae_movae \at1, aep0 -s8i \at1, \ptr, .Lxchal_ofs_+56 +s8i \at1, \ptr, .Lxchal_ofs_ + 56 ae_movae \at1, aep1 -s8i \at1, \ptr, .Lxchal_ofs_+57 +s8i \at1, \ptr, .Lxchal_ofs_ + 57 ae_movae \at1, aep2 -s8i \at1, \ptr, .Lxchal_ofs_+58 +s8i \at1, \ptr, .Lxchal_ofs_ + 58 ae_movae \at1, aep3 -s8i \at1, \ptr, .Lxchal_ofs_+59 +s8i \at1, \ptr, .Lxchal_ofs_ + 59 addi.a \ptr, \ptr, 64 -ae_salign128.i u0, \ptr, .Lxchal_ofs_+0 -ae_salign128.i u1, \ptr, .Lxchal_ofs_+16 -ae_salign128.i u2, \ptr, .Lxchal_ofs_+32 -ae_salign128.i u3, \ptr, .Lxchal_ofs_+48 +ae_salign128.i u0, \ptr, .Lxchal_ofs_ + 0 +ae_salign128.i u1, \ptr, .Lxchal_ofs_ + 16 +ae_salign128.i u2, \ptr, .Lxchal_ofs_ + 32 +ae_salign128.i u3, \ptr, .Lxchal_ofs_ + 48 addi.a \ptr, \ptr, -320 ae_movdrzbvc aed0 // ureg AE_ZBIASV8C -ae_s64.i aed0, \ptr, .Lxchal_ofs_+0 + 0 +ae_s64.i aed0, \ptr, .Lxchal_ofs_ + 0 + 0 ae_movvfcrfsr aed0 // ureg FCR_FSR -ae_s64.i aed0, \ptr, .Lxchal_ofs_+8 + 0 +ae_s64.i aed0, \ptr, .Lxchal_ofs_ + 8 + 0 rur.ae_ovf_sar \at1 // ureg 240 -s32i \at1, \ptr, .Lxchal_ofs_+16 +s32i \at1, \ptr, .Lxchal_ofs_ + 16 rur.ae_bithead \at1 // ureg 241 -s32i \at1, \ptr, .Lxchal_ofs_+20 +s32i \at1, \ptr, .Lxchal_ofs_ + 20 rur.ae_ts_fts_bu_bp \at1 // ureg 242 -s32i \at1, \ptr, .Lxchal_ofs_+24 +s32i \at1, \ptr, .Lxchal_ofs_ + 24 rur.ae_cw_sd_no \at1 // ureg 243 -s32i \at1, \ptr, .Lxchal_ofs_+28 +s32i \at1, \ptr, .Lxchal_ofs_ + 28 rur.ae_cbegin0 \at1 // ureg 246 -s32i \at1, \ptr, .Lxchal_ofs_+32 +s32i \at1, \ptr, .Lxchal_ofs_ + 32 rur.ae_cend0 \at1 // ureg 247 -s32i \at1, \ptr, .Lxchal_ofs_+36 +s32i \at1, \ptr, .Lxchal_ofs_ + 36 rur.ae_cbegin1 \at1 // ureg 248 -s32i \at1, \ptr, .Lxchal_ofs_+40 +s32i \at1, \ptr, .Lxchal_ofs_ + 40 rur.ae_cend1 \at1 // ureg 249 -s32i \at1, \ptr, .Lxchal_ofs_+44 +s32i \at1, \ptr, .Lxchal_ofs_ + 44 rur.ae_cbegin2 \at1 // ureg 250 -s32i \at1, \ptr, .Lxchal_ofs_+48 +s32i \at1, \ptr, .Lxchal_ofs_ + 48 rur.ae_cend2 \at1 // ureg 251 -s32i \at1, \ptr, .Lxchal_ofs_+52 +s32i \at1, \ptr, .Lxchal_ofs_ + 52 .set .Lxchal_ofs_, .Lxchal_ofs_ + 384 .elseif((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 xchal_sa_align \ptr, 0, 0, 16, 16 @@ -259,80 +257,80 @@ xchal_sa_start \continue, \ofs // Custom caller-saved registers not used by default by the compiler: .ifeq(XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) xchal_sa_align \ptr, 0, 0, 16, 16 -ae_l64.i aed0, \ptr, .Lxchal_ofs_+0 + 0 // ureg AE_ZBIASV8C +ae_l64.i aed0, \ptr, .Lxchal_ofs_ + 0 + 0 // ureg AE_ZBIASV8C ae_movzbvcdr aed0 -ae_l64.i aed0, \ptr, .Lxchal_ofs_+8 + 0 // ureg FCR_FSR +ae_l64.i aed0, \ptr, .Lxchal_ofs_ + 8 + 0 // ureg FCR_FSR ae_movfcrfsrv aed0 -l32i \at1, \ptr, .Lxchal_ofs_+16 +l32i \at1, \ptr, .Lxchal_ofs_ + 16 wur.ae_ovf_sar \at1 // ureg 240 -l32i \at1, \ptr, .Lxchal_ofs_+20 +l32i \at1, \ptr, .Lxchal_ofs_ + 20 wur.ae_bithead \at1 // ureg 241 -l32i \at1, \ptr, .Lxchal_ofs_+24 +l32i \at1, \ptr, .Lxchal_ofs_ + 24 wur.ae_ts_fts_bu_bp \at1 // ureg 242 -l32i \at1, \ptr, .Lxchal_ofs_+28 +l32i \at1, \ptr, .Lxchal_ofs_ + 28 wur.ae_cw_sd_no \at1 // ureg 243 -l32i \at1, \ptr, .Lxchal_ofs_+32 +l32i \at1, \ptr, .Lxchal_ofs_ + 32 wur.ae_cbegin0 \at1 // ureg 246 -l32i \at1, \ptr, .Lxchal_ofs_+36 +l32i \at1, \ptr, .Lxchal_ofs_ + 36 wur.ae_cend0 \at1 // ureg 247 -l32i \at1, \ptr, .Lxchal_ofs_+40 +l32i \at1, \ptr, .Lxchal_ofs_ + 40 wur.ae_cbegin1 \at1 // ureg 248 -l32i \at1, \ptr, .Lxchal_ofs_+44 +l32i \at1, \ptr, .Lxchal_ofs_ + 44 wur.ae_cend1 \at1 // ureg 249 -l32i \at1, \ptr, .Lxchal_ofs_+48 +l32i \at1, \ptr, .Lxchal_ofs_ + 48 wur.ae_cbegin2 \at1 // ureg 250 -l32i \at1, \ptr, .Lxchal_ofs_+52 +l32i \at1, \ptr, .Lxchal_ofs_ + 52 wur.ae_cend2 \at1 // ureg 251 -ae_l64.i aed0, \ptr, .Lxchal_ofs_+56 +ae_l64.i aed0, \ptr, .Lxchal_ofs_ + 56 addi.a \ptr, \ptr, 64 -ae_l64.i aed1, \ptr, .Lxchal_ofs_+0 -ae_l64.i aed2, \ptr, .Lxchal_ofs_+8 -ae_l64.i aed3, \ptr, .Lxchal_ofs_+16 -ae_l64.i aed4, \ptr, .Lxchal_ofs_+24 -ae_l64.i aed5, \ptr, .Lxchal_ofs_+32 -ae_l64.i aed6, \ptr, .Lxchal_ofs_+40 -ae_l64.i aed7, \ptr, .Lxchal_ofs_+48 -ae_l64.i aed8, \ptr, .Lxchal_ofs_+56 +ae_l64.i aed1, \ptr, .Lxchal_ofs_ + 0 +ae_l64.i aed2, \ptr, .Lxchal_ofs_ + 8 +ae_l64.i aed3, \ptr, .Lxchal_ofs_ + 16 +ae_l64.i aed4, \ptr, .Lxchal_ofs_ + 24 +ae_l64.i aed5, \ptr, .Lxchal_ofs_ + 32 +ae_l64.i aed6, \ptr, .Lxchal_ofs_ + 40 +ae_l64.i aed7, \ptr, .Lxchal_ofs_ + 48 +ae_l64.i aed8, \ptr, .Lxchal_ofs_ + 56 addi.a \ptr, \ptr, 64 -ae_l64.i aed9, \ptr, .Lxchal_ofs_+0 -ae_l64.i aed10, \ptr, .Lxchal_ofs_+8 -ae_l64.i aed11, \ptr, .Lxchal_ofs_+16 -ae_l64.i aed12, \ptr, .Lxchal_ofs_+24 -ae_l64.i aed13, \ptr, .Lxchal_ofs_+32 -ae_l64.i aed14, \ptr, .Lxchal_ofs_+40 -ae_l64.i aed15, \ptr, .Lxchal_ofs_+48 -ae_l64.i aed16, \ptr, .Lxchal_ofs_+56 +ae_l64.i aed9, \ptr, .Lxchal_ofs_ + 0 +ae_l64.i aed10, \ptr, .Lxchal_ofs_ + 8 +ae_l64.i aed11, \ptr, .Lxchal_ofs_ + 16 +ae_l64.i aed12, \ptr, .Lxchal_ofs_ + 24 +ae_l64.i aed13, \ptr, .Lxchal_ofs_ + 32 +ae_l64.i aed14, \ptr, .Lxchal_ofs_ + 40 +ae_l64.i aed15, \ptr, .Lxchal_ofs_ + 48 +ae_l64.i aed16, \ptr, .Lxchal_ofs_ + 56 addi.a \ptr, \ptr, 64 -ae_l64.i aed17, \ptr, .Lxchal_ofs_+0 -ae_l64.i aed18, \ptr, .Lxchal_ofs_+8 -ae_l64.i aed19, \ptr, .Lxchal_ofs_+16 -ae_l64.i aed20, \ptr, .Lxchal_ofs_+24 -ae_l64.i aed21, \ptr, .Lxchal_ofs_+32 -ae_l64.i aed22, \ptr, .Lxchal_ofs_+40 -ae_l64.i aed23, \ptr, .Lxchal_ofs_+48 -ae_l64.i aed24, \ptr, .Lxchal_ofs_+56 +ae_l64.i aed17, \ptr, .Lxchal_ofs_ + 0 +ae_l64.i aed18, \ptr, .Lxchal_ofs_ + 8 +ae_l64.i aed19, \ptr, .Lxchal_ofs_ + 16 +ae_l64.i aed20, \ptr, .Lxchal_ofs_ + 24 +ae_l64.i aed21, \ptr, .Lxchal_ofs_ + 32 +ae_l64.i aed22, \ptr, .Lxchal_ofs_ + 40 +ae_l64.i aed23, \ptr, .Lxchal_ofs_ + 48 +ae_l64.i aed24, \ptr, .Lxchal_ofs_ + 56 addi.a \ptr, \ptr, 64 -ae_l64.i aed25, \ptr, .Lxchal_ofs_+0 -ae_l64.i aed26, \ptr, .Lxchal_ofs_+8 -ae_l64.i aed27, \ptr, .Lxchal_ofs_+16 -ae_l64.i aed28, \ptr, .Lxchal_ofs_+24 -ae_l64.i aed29, \ptr, .Lxchal_ofs_+32 -ae_l64.i aed30, \ptr, .Lxchal_ofs_+40 -ae_l64.i aed31, \ptr, .Lxchal_ofs_+48 +ae_l64.i aed25, \ptr, .Lxchal_ofs_ + 0 +ae_l64.i aed26, \ptr, .Lxchal_ofs_ + 8 +ae_l64.i aed27, \ptr, .Lxchal_ofs_ + 16 +ae_l64.i aed28, \ptr, .Lxchal_ofs_ + 24 +ae_l64.i aed29, \ptr, .Lxchal_ofs_ + 32 +ae_l64.i aed30, \ptr, .Lxchal_ofs_ + 40 +ae_l64.i aed31, \ptr, .Lxchal_ofs_ + 48 addi.a \ptr, \ptr, 56 -l8ui \at1, \ptr, .Lxchal_ofs_+0 +l8ui \at1, \ptr, .Lxchal_ofs_ + 0 ae_movea aep0, \at1 -l8ui \at1, \ptr, .Lxchal_ofs_+1 +l8ui \at1, \ptr, .Lxchal_ofs_ + 1 ae_movea aep1, \at1 -l8ui \at1, \ptr, .Lxchal_ofs_+2 +l8ui \at1, \ptr, .Lxchal_ofs_ + 2 ae_movea aep2, \at1 -l8ui \at1, \ptr, .Lxchal_ofs_+3 +l8ui \at1, \ptr, .Lxchal_ofs_ + 3 ae_movea aep3, \at1 addi.a \ptr, \ptr, 8 -ae_lalign128.i u0, \ptr, .Lxchal_ofs_+0 -ae_lalign128.i u1, \ptr, .Lxchal_ofs_+16 -ae_lalign128.i u2, \ptr, .Lxchal_ofs_+32 -ae_lalign128.i u3, \ptr, .Lxchal_ofs_+48 +ae_lalign128.i u0, \ptr, .Lxchal_ofs_ + 0 +ae_lalign128.i u1, \ptr, .Lxchal_ofs_ + 16 +ae_lalign128.i u2, \ptr, .Lxchal_ofs_ + 32 +ae_lalign128.i u3, \ptr, .Lxchal_ofs_ + 48 .set .Lxchal_pofs_, .Lxchal_pofs_ + 320 .set .Lxchal_ofs_, .Lxchal_ofs_ + 64 .elseif((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 diff --git a/src/platform/mt8196/include/arch/xtensa/config/tie.h b/src/platform/mt8196/include/arch/xtensa/config/tie.h index e22ba13049b1..517d79faab47 100644 --- a/src/platform/mt8196/include/arch/xtensa/config/tie.h +++ b/src/platform/mt8196/include/arch/xtensa/config/tie.h @@ -42,8 +42,8 @@ #define XCHAL_CP_PORT_MASK UINT32_C(0x00) /* bitmask of only port CPs */ /* Basic parameters of each coprocessor: */ -#define XCHAL_CP1_NAME "AudioEngineLX" -#define XCHAL_CP1_IDENT AudioEngineLX +#define XCHAL_CP1_NAME "audio_engine_lx" +#define XCHAL_CP1_IDENT audio_engine_lx #define XCHAL_CP1_SA_SIZE UINT32_C(384) /* size of state save area */ #define XCHAL_CP1_SA_ALIGN UINT32_C(16) /* min alignment of save area */ #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */