platform: mediatek: update xtensa headers for mt8196

update xtensa headers for mediatek mt8196 platform

Signed-off-by: hailong.fan <hailong.fan@mediatek.com>

src/platform/mt8196/include/arch/xtensa/config/core-isa.h

@@ -33,7 +33,6 @@
 #ifndef XTENSA_CORE_CONFIGURATION_H_
 #define XTENSA_CORE_CONFIGURATION_H_
 
-
 /****************************************************************************
  *	    Parameters Useful for Any Code, USER or PRIVILEGED
  ****************************************************************************
@@ -44,7 +43,6 @@
  *  configured, and a value of 0 otherwise.  These macros are always defined.
  */
 
-
 /*----------------------------------------------------------------------
  *				ISA
  *----------------------------------------------------------------------
@@ -135,8 +133,6 @@
 #define XCHAL_HAVE_HIFI2EP		0	/* HiFi2EP */
 #define XCHAL_HAVE_HIFI_MINI		0
 
-
-
 #define XCHAL_HAVE_VECTORFPU2005	0	/* vector floating-point pkg */
 #define XCHAL_HAVE_USER_DPFPU		0       /* user DP floating-point pkg */
 #define XCHAL_HAVE_USER_SPFPU		1       /* user SP floating-point pkg */
@@ -233,7 +229,6 @@
 
 #define XCHAL_HAVE_XNNE			0		/* XNNE */
 
-
 /*----------------------------------------------------------------------
  *			MISC
  *----------------------------------------------------------------------
@@ -354,14 +349,10 @@
 /*  This one is a form of caching, though not architecturally visible:  */
 #define XCHAL_HAVE_BRANCH_PREDICTION	0	/* branch [target] prediction */
 
-
-
-
 /****************************************************************************
  *   Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
  ****************************************************************************/
 
-
 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
 
 /*----------------------------------------------------------------------
@@ -412,7 +403,6 @@
 /*  Extended memory attributes supported.  */
 #define XCHAL_HAVE_EXT_CA		0
 
-
 /*----------------------------------------------------------------------
  *			INTERNAL I/D RAM/ROMs and XLMI
  *----------------------------------------------------------------------
@@ -454,16 +444,13 @@
 
 #define XCHAL_HAVE_IMEM_LOADSTORE	1	/* can load/store to IROM/IRAM*/
 
-
 /*----------------------------------------------------------------------
  *		IDMA
  *----------------------------------------------------------------------
  */
 
 #define XCHAL_HAVE_IDMA			0
 
-
-
 /*----------------------------------------------------------------------
  *		INTERRUPTS and TIMERS
  *----------------------------------------------------------------------
@@ -480,7 +467,6 @@
 #define XCHAL_NUM_INTLEVELS		5
 #define XCHAL_INTERRUPT_RANGE		32	/* range of interrupt numbers */
 
-
 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1   /* med/high-pri. interrupts */
 #define XCHAL_EXCM_LEVEL		3	/* level masked by PS.EXCM */
 	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
@@ -610,7 +596,6 @@
 #define XCHAL_INTLEVEL6_NUM		25
 /*  (There are many interrupts each at level(s) 1, 2, 3, 4.)  */
 
-
 /*
  *  External interrupt mapping.
  *  These macros describe how Xtensa processor interrupt numbers
@@ -684,7 +669,6 @@
 #define	XCHAL_HAVE_ISL			0	/* Interrupt Stack Limit */
 #define	XCHAL_HAVE_PSL			0	/* Pageable Stack Limit */
 
-
 /*----------------------------------------------------------------------
  *		EXCEPTIONS and VECTORS
  *----------------------------------------------------------------------
@@ -758,7 +742,6 @@
 #define XCHAL_INTLEVEL6_VECTOR_VADDR	XCHAL_NMI_VECTOR_VADDR
 #define XCHAL_INTLEVEL6_VECTOR_PADDR	XCHAL_NMI_VECTOR_PADDR
 
-
 /*----------------------------------------------------------------------
  *			DEBUG MODULE
  *----------------------------------------------------------------------
@@ -786,21 +769,19 @@
 /*  Perf counters  */
 #define XCHAL_NUM_PERF_COUNTERS		8	/* performance counters */
 
-
 /*----------------------------------------------------------------------
  *			MMU
  *----------------------------------------------------------------------
  */
 
 /*  See core-matmap.h header file for more details.  */
-
 #define XCHAL_HAVE_TLBS			0	/* inverse of HAVE_CACHEATTR */
 #define XCHAL_HAVE_SPANNING_WAY		0	/* one way maps I+D 4GB vaddr */
 #define XCHAL_HAVE_IDENTITY_MAP		1	/* vaddr == paddr always */
 #define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
 #define XCHAL_HAVE_MIMIC_CACHEATTR	0	/* region protection */
 #define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
-	/* full MMU (with page table [autorefill] and protection) usable for an MMU-based OS */
+/* full MMU (with page table [autorefill] and protection) usable for an MMU-based OS */
 #define XCHAL_HAVE_PTP_MMU		0
 
 /*  If none of the above last 5 are set, it's a custom TLB configuration.  */
@@ -846,6 +827,5 @@
 #define XCHAL_HAVE_WWDT			0
 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
 
-
 #endif /* XTENSA_CORE_CONFIGURATION_H_ */
 

src/platform/mt8196/include/arch/xtensa/config/core-matmap.h

@@ -45,11 +45,9 @@
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 
-
 #ifndef XTENSA_CONFIG_CORE_MATMAP_H
 #define XTENSA_CONFIG_CORE_MATMAP_H
 
-
 /*----------------------------------------------------------------------
  * CACHE (MEMORY ACCESS) ATTRIBUTES
  *----------------------------------------------------------------------
@@ -77,7 +75,6 @@ XTHAL_MEM_BUFFERABLE)
 #define XCHAL_CA_BYPASS_R  (XTHAL_AR_R      | XTHAL_MEM_DEVICE)
 #define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1
 
-
 /*
  * Contents of MPU background map.
  * NOTE:  caller must define the XCHAL_MPU_BGMAP() macro (not defined here
@@ -100,7 +97,5 @@ XCHAL_MPU_BGMAP(s, 0x80000000, 0xffffffff, 7, 6, 0) \)
 
 /* end */
 
-
-
 #endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
 

src/platform/mt8196/include/arch/xtensa/config/key.h

@@ -14,7 +14,5 @@
 
 #include <xtensa/xtensa-types.h>
 
-
-
 #endif
 

src/platform/mt8196/include/arch/xtensa/config/secure.h

@@ -26,7 +26,6 @@
 #ifndef XTENSA_SECURE_H
 #define XTENSA_SECURE_H
 
-
 /* SRAM */
 #define XCHAL_HAVE_SECURE_SRAM	0
 

src/platform/mt8196/include/arch/xtensa/config/specreg.h

@@ -35,7 +35,6 @@
 /*  Include these special register bitfield definitions, for historical reasons:  */
 #include <xtensa/corebits.h>
 
-
 /*  Special registers:  */
 #define LBEG		0
 #define LEND		1
@@ -96,7 +95,6 @@
 #define MISC_REG_2	246
 #define MISC_REG_3	247
 
-
 /*  Special cases (bases of special register series):  */
 #define IBREAKA		128
 #define DBREAKA		144

src/platform/mt8196/include/arch/xtensa/config/system.h

@@ -36,7 +36,6 @@
 #ifndef XTENSA_CONFIG_SYSTEM_H
 #define XTENSA_CONFIG_SYSTEM_H
 
-
 /*----------------------------------------------------------------------
  * CONFIGURED SOFTWARE OPTIONS
  *----------------------------------------------------------------------
@@ -120,7 +119,6 @@
 #define XSHAL_SIMIO_PADDR		0x20000000
 #define XSHAL_SIMIO_SIZE		0x20000000
 
-
 /*----------------------------------------------------------------------
  *  For use by reference testbench exit and diagnostic routines.
  *----------------------------------------------------------------------
@@ -214,7 +212,6 @@
 #define XSHAL_ISS_PIPE_REGIONS	0
 #define XSHAL_ISS_SDRAM_REGIONS	0
 
-
 /*----------------------------------------------------------------------
  * XT2000 BOARD SPECIFIC ...
  *----------------------------------------------------------------------
@@ -241,7 +238,6 @@
 #define XSHAL_XT2000_PIPE_REGIONS	0x00000000	/* BusInt pipeline regions */
 #define XSHAL_XT2000_SDRAM_REGIONS	0x00000024	/* BusInt SDRAM regions */
 
-
 /*----------------------------------------------------------------------
  * VECTOR INFO AND SIZES
  *----------------------------------------------------------------------