Tools: Topology2: Build nocodec topologies for PTL FPGA

This patch builds test topologies sof-ptl-nocodec-fpga-2ch-pdm0.tplg
and sof-ptl-nocodec-fpga-4ch.tplg. The changes include:

- New ptl.conf where DMIC and SSP versions are updated
  vs. LNL and MTL.
- The definitions for blob 3.0 format are added to
  instruct alsa-utils to process a new format SSP blob.
- Since the blob 3.0 format includes the clock start
  and stop controls those previously where in ext blob
  the clk_config objects are added to cavs-nocodec.conf
  for PTL platform.

Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>

tools/topology/topology2/cavs-nocodec.conf

@@ -102,6 +102,7 @@ IncludeByKey.PLATFORM {
 	"adl"	"platform/intel/tgl.conf"
 	"mtl"	"platform/intel/mtl.conf"
 	"lnl"	"platform/intel/lnl.conf"
+	"ptl"	"platform/intel/ptl.conf"
 }
 
 # include DMIC config if needed.
@@ -141,6 +142,9 @@ Object.Dai.SSP [
 			Object.Base.link_config.1 {
 				clock_source	1
 			}
+			IncludeByKey.PLATFORM {
+				"ptl"	      "platform/intel/ptl_clk_config.conf"
+			}
 		}
 	}
 	{
@@ -162,6 +166,9 @@ Object.Dai.SSP [
 			Object.Base.link_config.1 {
 				clock_source	1
 			}
+			IncludeByKey.PLATFORM {
+				"ptl"	      "platform/intel/ptl_clk_config.conf"
+			}
 		}
 	}
 ]
@@ -1178,6 +1185,9 @@ IncludeByKey.SSP1_ENABLED {
 					Object.Base.link_config.1 {
 						clock_source	1
 					}
+					IncludeByKey.PLATFORM {
+						"ptl"	      "platform/intel/ptl_clk_config.conf"
+					}
 				}
 			}
 		]

tools/topology/topology2/development/tplg-targets.cmake

@@ -53,6 +53,15 @@ NHLT_BIN=nhlt-sof-lnl-nocodec-fpga-2ch-pdm0.bin,PASSTHROUGH=true,DMIC_IO_CLK=192
 PDM1_MIC_B_ENABLE=1,PREPROCESS_PLUGINS=nhlt,\
 NHLT_BIN=nhlt-sof-lnl-nocodec-fpga-4ch.bin,PASSTHROUGH=true,DMIC_IO_CLK=19200000"
 
+# SSP topology for PTL FPGA with lower DMIC IO clock of 19.2MHz, 2ch PDM0 enabled
+"cavs-nocodec\;sof-ptl-nocodec-fpga-2ch-pdm0\;PLATFORM=ptl,NUM_DMICS=2,PREPROCESS_PLUGINS=nhlt,\
+NHLT_BIN=nhlt-sof-ptl-nocodec-fpga-2ch-pdm0.bin,PASSTHROUGH=true,DMIC_IO_CLK=19200000"
+
+# SSP topology for PTL FPGA with lower DMIC IO clock of 19.2MHz, 4ch both PDM0 and PDM1 enabled
+"cavs-nocodec\;sof-ptl-nocodec-fpga-4ch\;PLATFORM=ptl,NUM_DMICS=4,PDM1_MIC_A_ENABLE=1,\
+PDM1_MIC_B_ENABLE=1,PREPROCESS_PLUGINS=nhlt,\
+NHLT_BIN=nhlt-sof-ptl-nocodec-fpga-4ch.bin,PASSTHROUGH=true,DMIC_IO_CLK=19200000"
+
 "cavs-sdw\;sof-lnl-fpga-rt711-l0\;PLATFORM=lnl,NUM_HDMIS=0,PASSTHROUGH=true"
 
 # CAVS HDA topology with mixer-based efx eq pipelines for HDA and passthrough pipelines for HDMI

tools/topology/topology2/include/common/common_definitions.conf

@@ -64,4 +64,5 @@ Define {
 
 	SSP_BLOB_VERSION_1_0			0x100
 	SSP_BLOB_VERSION_1_5			0x105
+	SSP_BLOB_VERSION_3_0			0x300
 }

tools/topology/topology2/include/dais/ssp.conf

@@ -113,6 +113,7 @@ Class.Dai."SSP" {
 			!valid_values [
 				$SSP_BLOB_VERSION_1_0
 				$SSP_BLOB_VERSION_1_5
+				$SSP_BLOB_VERSION_3_0
 			]
 		}
 	}

tools/topology/topology2/platform/intel/ptl.conf

@@ -0,0 +1,6 @@
+# PTL-specific variable definitions
+Define {
+	DMIC_DRIVER_VERSION		5
+	SSP_BLOB_VERSION		0x300
+	NUM_HDMIS			3
+}

tools/topology/topology2/platform/intel/ptl_clk_config.conf

@@ -0,0 +1,12 @@
+# TODO: Find out if this is needed!
+# With these added the alsa-utils generated blob matches with the
+# reference blob the start_control and stop_control words.
+
+Object.Base."clk_config".1 {
+	clock_warm_up	   4096
+	mclk		   0
+	warm_up_ovr	   0
+	clock_stop_delay   148
+	keep_running	   0
+	clock_stop_ovr	   0
+}