Integrate SSD and create bitstream

UART.xdc

@@ -0,0 +1,87 @@
+## This file is a general .xdc for the Basys3 rev B board
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets receive_IBUF]
+
+# Clock signal
+# Bank = 34, Pin name = ,					Sch name = CLK100MHZ
+set_property PACKAGE_PIN W5 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+# create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk]
+
+# Switches
+set_property PACKAGE_PIN R2 [get_ports receive]
+set_property IOSTANDARD LVCMOS33 [get_ports receive]
+
+set_property PACKAGE_PIN T1 [get_ports transmit]
+set_property IOSTANDARD LVCMOS33 [get_ports transmit]
+
+set_property PACKAGE_PIN V17 [get_ports data(7)]
+set_property IOSTANDARD LVCMOS33 [get_ports data(7)]
+
+set_property PACKAGE_PIN V16 [get_ports data(6)]
+set_property IOSTANDARD LVCMOS33 [get_ports data(6)]
+
+set_property PACKAGE_PIN W16 [get_ports data(5)]
+set_property IOSTANDARD LVCMOS33 [get_ports data(5)]
+
+set_property PACKAGE_PIN W17 [get_ports data(4)]
+set_property IOSTANDARD LVCMOS33 [get_ports data(4)]
+
+set_property PACKAGE_PIN W15 [get_ports data(3)]
+set_property IOSTANDARD LVCMOS33 [get_ports data(3)]
+
+set_property PACKAGE_PIN V15 [get_ports data(2)]
+set_property IOSTANDARD LVCMOS33 [get_ports data(2)]
+
+set_property PACKAGE_PIN W14 [get_ports data(1)]
+set_property IOSTANDARD LVCMOS33 [get_ports data(1)]
+
+set_property PACKAGE_PIN W13 [get_ports data(0)]
+set_property IOSTANDARD LVCMOS33 [get_ports data(0)]
+
+set_property PACKAGE_PIN U18 [get_ports execute]
+set_property IOSTANDARD LVCMOS33 [get_ports execute]
+
+# USB HID (PS/2)
+set_property PACKAGE_PIN C17 [get_ports serial_comm]						
+set_property IOSTANDARD LVCMOS33 [get_ports serial_comm]
+set_property PULLUP true [get_ports serial_comm]
+
+
+# 7 segment display
+set_property PACKAGE_PIN W7 [get_ports {cathode[0]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {cathode[0]}]
+set_property PACKAGE_PIN W6 [get_ports {cathode[1]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {cathode[1]}]
+set_property PACKAGE_PIN U8 [get_ports {cathode[2]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {cathode[2]}]
+set_property PACKAGE_PIN V8 [get_ports {cathode[3]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {cathode[3]}]
+set_property PACKAGE_PIN U5 [get_ports {cathode[4]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {cathode[4]}]
+set_property PACKAGE_PIN V5 [get_ports {cathode[5]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {cathode[5]}]
+set_property PACKAGE_PIN U7 [get_ports {cathode[6]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {cathode[6]}]
+
+set_property PACKAGE_PIN U2 [get_ports {anode[0]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {anode[0]}]
+set_property PACKAGE_PIN U4 [get_ports {anode[1]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {anode[1]}]
+set_property PACKAGE_PIN V4 [get_ports {anode[2]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {anode[2]}]
+set_property PACKAGE_PIN W4 [get_ports {anode[3]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {anode[3]}]
+
+# Others (BITSTREAM, CONFIG)
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]
+
+set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]

UART_main.vhd

@@ -9,35 +9,62 @@ entity UART_main is
 		data       : in std_logic_vector(7 downto 0);
 		receive    : in std_logic;
 		transmit   : in std_logic;
-		execute    : in std_logic);
+		execute    : in std_logic;
+		anode      : out   std_logic_vector (3 downto 0);
+        cathode    : out   std_logic_vector (6 downto 0);
+		serial_comm: inout std_logic);
+
 end UART_main;
 
 
 architecture behav of UART_main is
 
 signal data_transmit : std_logic_vector(7 downto 0);
 signal data_receive  : std_logic_vector(7 downto 0);
+signal serial_receive : std_logic;
+signal serial_transmit: std_logic;
+signal data_ssd      : std_logic_vector(15 downto 0);
 
 begin
 
+data_ssd <= "00000000" & data_receive;
+
+assign: process(clk)
+begin
+    if receive='1' then
+        serial_receive <= serial_comm;
+    elsif transmit='1' then
+        data_transmit <= data;
+        serial_transmit <= serial_comm;
+    end if;
+end process;
+
+ssd : entity work.lab4_seven_segment_display
+    port map (
+        b => data_ssd,
+        clk => clk,
+        pushbutton => '0',
+        anode => anode,
+        cathode => cathode);
+
 receiver : entity work.uart_RX 
 	generic map (
-		g_clock_per_bit => 117)
+		g_clock_per_bit => 10416)
 	port map (
 		in_clk => clk,
-		in_RX_serial => receive,
+		in_RX_serial => serial_receive,
 		out_RX_DV => open,
-		out_RX_byte => data_write);
+		out_RX_byte => data_receive);
 
 transmitter : entity work.uart_TX
 	generic map (
-		g_clock_per_bit => 117)
+		g_clock_per_bit => 10416)
 	port map (
 		in_clk => clk,
 		in_TX_DV => execute,
 		in_TX_byte => data_transmit,
 		out_TX_active => open,
-		out_TX_serial => transmit,
+		out_TX_serial => serial_transmit,
 		out_TX_done => open);
 
 end behav;