UART-Project

Universal Asynchronous Receiver-Transmitter. Semester project of Digital Logic and System Design course of fall 2017, IIT Delhi.

Name	Name	Last commit message	Last commit date
Latest commit skulltech Integrate SSD and create bitstream Nov 10, 2017 6e77031 · Nov 10, 2017 History 13 Commits
Mini Project report 3.docx	Mini Project report 3.docx	files updated	Nov 7, 2017
Mini-Project Question statement.txt	Mini-Project Question statement.txt	files updated	Nov 8, 2017
New Doc 2017-11-06_1.jpg	New Doc 2017-11-06_1.jpg	files updated	Nov 7, 2017
New Doc 2017-11-06_2.jpg	New Doc 2017-11-06_2.jpg	files updated	Nov 7, 2017
New Doc 2017-11-06_3.jpg	New Doc 2017-11-06_3.jpg	files updated	Nov 7, 2017
README.md	README.md	Initial commit	Nov 7, 2017
UART.xdc	UART.xdc	Integrate SSD and create bitstream	Nov 10, 2017
UART_main.bit	UART_main.bit	Integrate SSD and create bitstream	Nov 10, 2017
UART_main.vhd	UART_main.vhd	Integrate SSD and create bitstream	Nov 10, 2017
lab4_seven_segment_display.vhf	lab4_seven_segment_display.vhf	Integrate SSD and create bitstream	Nov 10, 2017
mini_project_uart_RX.vhd	mini_project_uart_RX.vhd	Integrate SSD and create bitstream	Nov 10, 2017
mini_project_uart_TB.vhd	mini_project_uart_TB.vhd	Integrate SSD and create bitstream	Nov 10, 2017
mini_project_uart_TX.vhd	mini_project_uart_TX.vhd	Integrate SSD and create bitstream	Nov 10, 2017
project-report.md	project-report.md	Modified report file	Nov 7, 2017
~$ni Project report 3.docx	~$ni Project report 3.docx	Integrate SSD and create bitstream	Nov 10, 2017

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